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drm/i915: Remove orphaned prototype gen6_set_pm_mask()
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
CommitLineData
1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
e9b73c67
CW		 33#include <uapi/drm/i915_drm.h>
34
585fb111 35#include "i915_reg.h"
79e53945 36#include "intel_bios.h"
8187a2b7 37#include "intel_ringbuffer.h"
b20385f1 38#include "intel_lrc.h"
0260c420 39#include "i915_gem_gtt.h"
564ddb2f 40#include "i915_gem_render_state.h"
0839ccb8 41#include <linux/io-mapping.h>
f899fc64 42#include <linux/i2c.h>
c167a6fc 43#include <linux/i2c-algo-bit.h>
0ade6386 44#include <drm/intel-gtt.h>
ba8286fa 45#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
d9fc9413 46#include <drm/drm_gem.h>
aaa6fd2a 47#include <linux/backlight.h>
5cc9ed4b 48#include <linux/hashtable.h>
2911a35b 49#include <linux/intel-iommu.h>
742cbee8 50#include <linux/kref.h>
9ee32fea 51#include <linux/pm_qos.h>
585fb111 52
1da177e4
LT		 53/* General customization:
54 */
55
1da177e4
LT		 56#define DRIVER_NAME "i915"
57#define DRIVER_DESC "Intel Graphics"
3eebaec6 58#define DRIVER_DATE "20141024"
1da177e4 59
c883ef1b
MK		 60#undef WARN_ON
61#define WARN_ON(x) WARN(x, "WARN_ON(" #x ")")
62
317c35d1 63enum pipe {
752aa88a 64 INVALID_PIPE = -1,
317c35d1
JB		 65 PIPE_A = 0,
66 PIPE_B,
9db4a9c7 67 PIPE_C,
a57c774a
AK		 68 _PIPE_EDP,
69 I915_MAX_PIPES = _PIPE_EDP
317c35d1 70};
9db4a9c7 71#define pipe_name(p) ((p) + 'A')
317c35d1 72
a5c961d1
PZ		 73enum transcoder {
74 TRANSCODER_A = 0,
75 TRANSCODER_B,
76 TRANSCODER_C,
a57c774a
AK		 77 TRANSCODER_EDP,
78 I915_MAX_TRANSCODERS
a5c961d1
PZ		 79};
80#define transcoder_name(t) ((t) + 'A')
81
84139d1e
DL		 82/*
83 * This is the maximum (across all platforms) number of planes (primary +
84 * sprites) that can be active at the same time on one pipe.
85 *
86 * This value doesn't count the cursor plane.
87 */
88#define I915_MAX_PLANES 3
89
80824003
JB		 90enum plane {
91 PLANE_A = 0,
92 PLANE_B,
9db4a9c7 93 PLANE_C,
80824003 94};
9db4a9c7 95#define plane_name(p) ((p) + 'A')
52440211 96
d615a166 97#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
06da8da2 98
2b139522
ED		 99enum port {
100 PORT_A = 0,
101 PORT_B,
102 PORT_C,
103 PORT_D,
104 PORT_E,
105 I915_MAX_PORTS
106};
107#define port_name(p) ((p) + 'A')
108
a09caddd 109#define I915_NUM_PHYS_VLV 2
e4607fcf
CML		 110
111enum dpio_channel {
112 DPIO_CH0,
113 DPIO_CH1
114};
115
116enum dpio_phy {
117 DPIO_PHY0,
118 DPIO_PHY1
119};
120
b97186f0
PZ		 121enum intel_display_power_domain {
122 POWER_DOMAIN_PIPE_A,
123 POWER_DOMAIN_PIPE_B,
124 POWER_DOMAIN_PIPE_C,
125 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
126 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
127 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
128 POWER_DOMAIN_TRANSCODER_A,
129 POWER_DOMAIN_TRANSCODER_B,
130 POWER_DOMAIN_TRANSCODER_C,
f52e353e 131 POWER_DOMAIN_TRANSCODER_EDP,
319be8ae
ID		 132 POWER_DOMAIN_PORT_DDI_A_2_LANES,
133 POWER_DOMAIN_PORT_DDI_A_4_LANES,
134 POWER_DOMAIN_PORT_DDI_B_2_LANES,
135 POWER_DOMAIN_PORT_DDI_B_4_LANES,
136 POWER_DOMAIN_PORT_DDI_C_2_LANES,
137 POWER_DOMAIN_PORT_DDI_C_4_LANES,
138 POWER_DOMAIN_PORT_DDI_D_2_LANES,
139 POWER_DOMAIN_PORT_DDI_D_4_LANES,
140 POWER_DOMAIN_PORT_DSI,
141 POWER_DOMAIN_PORT_CRT,
142 POWER_DOMAIN_PORT_OTHER,
cdf8dd7f 143 POWER_DOMAIN_VGA,
fbeeaa23 144 POWER_DOMAIN_AUDIO,
bd2bb1b9 145 POWER_DOMAIN_PLLS,
baa70707 146 POWER_DOMAIN_INIT,
bddc7645
ID		 147
148 POWER_DOMAIN_NUM,
b97186f0
PZ		 149};
150
151#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
152#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
153 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
f52e353e
ID		 154#define POWER_DOMAIN_TRANSCODER(tran) \
155 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
156 (tran) + POWER_DOMAIN_TRANSCODER_A)
b97186f0 157
1d843f9d
EE		 158enum hpd_pin {
159 HPD_NONE = 0,
160 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
161 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
162 HPD_CRT,
163 HPD_SDVO_B,
164 HPD_SDVO_C,
165 HPD_PORT_B,
166 HPD_PORT_C,
167 HPD_PORT_D,
168 HPD_NUM_PINS
169};
170
2a2d5482
CW		 171#define I915_GEM_GPU_DOMAINS \
172 (I915_GEM_DOMAIN_RENDER | \
173 I915_GEM_DOMAIN_SAMPLER | \
174 I915_GEM_DOMAIN_COMMAND | \
175 I915_GEM_DOMAIN_INSTRUCTION | \
176 I915_GEM_DOMAIN_VERTEX)
62fdfeaf 177
055e393f
DL		 178#define for_each_pipe(__dev_priv, __p) \
179 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
2d025a5b
DL		 180#define for_each_plane(pipe, p) \
181 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
d615a166 182#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
9db4a9c7 183
d79b814d
DL		 184#define for_each_crtc(dev, crtc) \
185 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
186
d063ae48
DL		 187#define for_each_intel_crtc(dev, intel_crtc) \
188 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
189
b2784e15
DL		 190#define for_each_intel_encoder(dev, intel_encoder) \
191 list_for_each_entry(intel_encoder, \
192 &(dev)->mode_config.encoder_list, \
193 base.head)
194
6c2b7c12
DV		 195#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
196 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
197 if ((intel_encoder)->base.crtc == (__crtc))
198
53f5e3ca
JB		 199#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
200 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
201 if ((intel_connector)->base.encoder == (__encoder))
202
b04c5bd6
BF		 203#define for_each_power_domain(domain, mask) \
204 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
205 if ((1 << (domain)) & (mask))
206
e7b903d2 207struct drm_i915_private;
ad46cb53 208struct i915_mm_struct;
5cc9ed4b 209struct i915_mmu_object;
e7b903d2 210
46edb027
DV		 211enum intel_dpll_id {
212 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
213 /* real shared dpll ids must be >= 0 */
9cd86933
DV		 214 DPLL_ID_PCH_PLL_A = 0,
215 DPLL_ID_PCH_PLL_B = 1,
216 DPLL_ID_WRPLL1 = 0,
217 DPLL_ID_WRPLL2 = 1,
46edb027
DV		 218};
219#define I915_NUM_PLLS 2
220
5358901f 221struct intel_dpll_hw_state {
dcfc3552 222 /* i9xx, pch plls */
66e985c0 223 uint32_t dpll;
8bcc2795 224 uint32_t dpll_md;
66e985c0
DV		 225 uint32_t fp0;
226 uint32_t fp1;
dcfc3552
DL		 227
228 /* hsw, bdw */
d452c5b6 229 uint32_t wrpll;
5358901f
DV		 230};
231
3e369b76 232struct intel_shared_dpll_config {
1e6f2ddc 233 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
3e369b76
ACO		 234 struct intel_dpll_hw_state hw_state;
235};
236
237struct intel_shared_dpll {
238 struct intel_shared_dpll_config config;
8bd31e67
ACO		 239 struct intel_shared_dpll_config *new_config;
240
ee7b9f93
JB		 241 int active; /* count of number of active CRTCs (i.e. DPMS on) */
242 bool on; /* is the PLL actually active? Disabled during modeset */
46edb027
DV		 243 const char *name;
244 /* should match the index in the dev_priv->shared_dplls array */
245 enum intel_dpll_id id;
96f6128c
DV		 246 /* The mode_set hook is optional and should be used together with the
247 * intel_prepare_shared_dpll function. */
15bdd4cf
DV		 248 void (*mode_set)(struct drm_i915_private *dev_priv,
249 struct intel_shared_dpll *pll);
e7b903d2
DV		 250 void (*enable)(struct drm_i915_private *dev_priv,
251 struct intel_shared_dpll *pll);
252 void (*disable)(struct drm_i915_private *dev_priv,
253 struct intel_shared_dpll *pll);
5358901f
DV		 254 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
255 struct intel_shared_dpll *pll,
256 struct intel_dpll_hw_state *hw_state);
ee7b9f93 257};
ee7b9f93 258
e69d0bc1
DV		 259/* Used by dp and fdi links */
260struct intel_link_m_n {
261 uint32_t tu;
262 uint32_t gmch_m;
263 uint32_t gmch_n;
264 uint32_t link_m;
265 uint32_t link_n;
266};
267
268void intel_link_compute_m_n(int bpp, int nlanes,
269 int pixel_clock, int link_clock,
270 struct intel_link_m_n *m_n);
271
1da177e4
LT		 272/* Interface history:
273 *
274 * 1.1: Original.
0d6aa60b
DA		 275 * 1.2: Add Power Management
276 * 1.3: Add vblank support
de227f5f 277 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 278 * 1.5: Add vblank pipe configuration
2228ed67
MCA		 279 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
280 * - Support vertical blank on secondary display pipe
1da177e4
LT		 281 */
282#define DRIVER_MAJOR 1
2228ed67 283#define DRIVER_MINOR 6
1da177e4
LT		 284#define DRIVER_PATCHLEVEL 0
285
23bc5982 286#define WATCH_LISTS 0
673a394b 287
0a3e67a4
JB		 288struct opregion_header;
289struct opregion_acpi;
290struct opregion_swsci;
291struct opregion_asle;
292
8ee1c3db 293struct intel_opregion {
5bc4418b
BW		 294 struct opregion_header __iomem *header;
295 struct opregion_acpi __iomem *acpi;
296 struct opregion_swsci __iomem *swsci;
ebde53c7
JN		 297 u32 swsci_gbda_sub_functions;
298 u32 swsci_sbcb_sub_functions;
5bc4418b
BW		 299 struct opregion_asle __iomem *asle;
300 void __iomem *vbt;
01fe9dbd 301 u32 __iomem *lid_state;
91a60f20 302 struct work_struct asle_work;
8ee1c3db 303};
44834a67 304#define OPREGION_SIZE (8*1024)
8ee1c3db 305
6ef3d427
CW		 306struct intel_overlay;
307struct intel_overlay_error_state;
308
ba8286fa
DV		 309struct drm_local_map;
310
7c1c2871 311struct drm_i915_master_private {
ba8286fa 312 struct drm_local_map *sarea;
7c1c2871
DA		 313 struct _drm_i915_sarea *sarea_priv;
314};
de151cf6 315#define I915_FENCE_REG_NONE -1
42b5aeab
VS		 316#define I915_MAX_NUM_FENCES 32
317/* 32 fences + sign bit for FENCE_REG_NONE */
318#define I915_MAX_NUM_FENCE_BITS 6
de151cf6
JB		 319
320struct drm_i915_fence_reg {
007cc8ac 321 struct list_head lru_list;
caea7476 322 struct drm_i915_gem_object *obj;
1690e1eb 323 int pin_count;
de151cf6 324};
7c1c2871 325
9b9d172d 326struct sdvo_device_mapping {
e957d772 327 u8 initialized;
9b9d172d 328 u8 dvo_port;
329 u8 slave_addr;
330 u8 dvo_wiring;
e957d772 331 u8 i2c_pin;
b1083333 332 u8 ddc_pin;
9b9d172d 333};
334
c4a1d9e4
CW		 335struct intel_display_error_state;
336
63eeaf38 337struct drm_i915_error_state {
742cbee8 338 struct kref ref;
585b0288
BW		 339 struct timeval time;
340
cb383002 341 char error_msg[128];
48b031e3 342 u32 reset_count;
62d5d69b 343 u32 suspend_count;
cb383002 344
585b0288 345 /* Generic register state */
63eeaf38
JB		 346 u32 eir;
347 u32 pgtbl_er;
be998e2e 348 u32 ier;
885ea5a8 349 u32 gtier[4];
b9a3906b 350 u32 ccid;
0f3b6849
CW		 351 u32 derrmr;
352 u32 forcewake;
585b0288
BW		 353 u32 error; /* gen6+ */
354 u32 err_int; /* gen7 */
355 u32 done_reg;
91ec5d11
BW		 356 u32 gac_eco;
357 u32 gam_ecochk;
358 u32 gab_ctl;
359 u32 gfx_mode;
585b0288 360 u32 extra_instdone[I915_NUM_INSTDONE_REG];
585b0288
BW		 361 u64 fence[I915_MAX_NUM_FENCES];
362 struct intel_overlay_error_state *overlay;
363 struct intel_display_error_state *display;
0ca36d78 364 struct drm_i915_error_object *semaphore_obj;
585b0288 365
52d39a21 366 struct drm_i915_error_ring {
372fbb8e 367 bool valid;
362b8af7
BW		 368 /* Software tracked state */
369 bool waiting;
370 int hangcheck_score;
371 enum intel_ring_hangcheck_action hangcheck_action;
372 int num_requests;
373
374 /* our own tracking of ring head and tail */
375 u32 cpu_ring_head;
376 u32 cpu_ring_tail;
377
378 u32 semaphore_seqno[I915_NUM_RINGS - 1];
379
380 /* Register state */
381 u32 tail;
382 u32 head;
383 u32 ctl;
384 u32 hws;
385 u32 ipeir;
386 u32 ipehr;
387 u32 instdone;
362b8af7
BW		 388 u32 bbstate;
389 u32 instpm;
390 u32 instps;
391 u32 seqno;
392 u64 bbaddr;
50877445 393 u64 acthd;
362b8af7 394 u32 fault_reg;
13ffadd1 395 u64 faddr;
362b8af7
BW		 396 u32 rc_psmi; /* sleep state */
397 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
398
52d39a21
CW		 399 struct drm_i915_error_object {
400 int page_count;
401 u32 gtt_offset;
402 u32 *pages[0];
ab0e7ff9 403 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
362b8af7 404
52d39a21
CW		 405 struct drm_i915_error_request {
406 long jiffies;
407 u32 seqno;
ee4f42b1 408 u32 tail;
52d39a21 409 } *requests;
6c7a01ec
BW		 410
411 struct {
412 u32 gfx_mode;
413 union {
414 u64 pdp[4];
415 u32 pp_dir_base;
416 };
417 } vm_info;
ab0e7ff9
CW		 418
419 pid_t pid;
420 char comm[TASK_COMM_LEN];
52d39a21 421 } ring[I915_NUM_RINGS];
3a448734 422
9df30794 423 struct drm_i915_error_buffer {
a779e5ab 424 u32 size;
9df30794 425 u32 name;
0201f1ec 426 u32 rseqno, wseqno;
9df30794
CW		 427 u32 gtt_offset;
428 u32 read_domains;
429 u32 write_domain;
4b9de737 430 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
9df30794
CW		 431 s32 pinned:2;
432 u32 tiling:2;
433 u32 dirty:1;
434 u32 purgeable:1;
5cc9ed4b 435 u32 userptr:1;
5d1333fc 436 s32 ring:4;
f56383cb 437 u32 cache_level:3;
95f5301d 438 } **active_bo, **pinned_bo;
6c7a01ec 439
95f5301d 440 u32 *active_bo_count, *pinned_bo_count;
3a448734 441 u32 vm_count;
63eeaf38
JB		 442};
443
7bd688cd 444struct intel_connector;
820d2d77 445struct intel_encoder;
b8cecdf5 446struct intel_crtc_config;
46f297fb 447struct intel_plane_config;
0e8ffe1b 448struct intel_crtc;
ee9300bb
DV		 449struct intel_limit;
450struct dpll;
b8cecdf5 451
e70236a8 452struct drm_i915_display_funcs {
ee5382ae 453 bool (*fbc_enabled)(struct drm_device *dev);
993495ae 454 void (*enable_fbc)(struct drm_crtc *crtc);
e70236a8
JB		 455 void (*disable_fbc)(struct drm_device *dev);
456 int (*get_display_clock_speed)(struct drm_device *dev);
457 int (*get_fifo_size)(struct drm_device *dev, int plane);
ee9300bb
DV		 458 /**
459 * find_dpll() - Find the best values for the PLL
460 * @limit: limits for the PLL
461 * @crtc: current CRTC
462 * @target: target frequency in kHz
463 * @refclk: reference clock frequency in kHz
464 * @match_clock: if provided, @best_clock P divider must
465 * match the P divider from @match_clock
466 * used for LVDS downclocking
467 * @best_clock: best PLL values found
468 *
469 * Returns true on success, false on failure.
470 */
471 bool (*find_dpll)(const struct intel_limit *limit,
a919ff14 472 struct intel_crtc *crtc,
ee9300bb
DV		 473 int target, int refclk,
474 struct dpll *match_clock,
475 struct dpll *best_clock);
46ba614c 476 void (*update_wm)(struct drm_crtc *crtc);
adf3d35e
VS		 477 void (*update_sprite_wm)(struct drm_plane *plane,
478 struct drm_crtc *crtc,
ed57cb8a
DL		 479 uint32_t sprite_width, uint32_t sprite_height,
480 int pixel_size, bool enable, bool scaled);
47fab737 481 void (*modeset_global_resources)(struct drm_device *dev);
0e8ffe1b
DV		 482 /* Returns the active state of the crtc, and if the crtc is active,
483 * fills out the pipe-config with the hw state. */
484 bool (*get_pipe_config)(struct intel_crtc *,
485 struct intel_crtc_config *);
46f297fb
JB		 486 void (*get_plane_config)(struct intel_crtc *,
487 struct intel_plane_config *);
8bd31e67 488 int (*crtc_compute_clock)(struct intel_crtc *crtc);
76e5a89c
DV		 489 void (*crtc_enable)(struct drm_crtc *crtc);
490 void (*crtc_disable)(struct drm_crtc *crtc);
ee7b9f93 491 void (*off)(struct drm_crtc *crtc);
69bfe1a9
JN		 492 void (*audio_codec_enable)(struct drm_connector *connector,
493 struct intel_encoder *encoder,
494 struct drm_display_mode *mode);
495 void (*audio_codec_disable)(struct intel_encoder *encoder);
674cf967 496 void (*fdi_link_train)(struct drm_crtc *crtc);
6067aaea 497 void (*init_clock_gating)(struct drm_device *dev);
8c9f3aaf
JB		 498 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
499 struct drm_framebuffer *fb,
ed8d1975 500 struct drm_i915_gem_object *obj,
a4872ba6 501 struct intel_engine_cs *ring,
ed8d1975 502 uint32_t flags);
29b9bde6
DV		 503 void (*update_primary_plane)(struct drm_crtc *crtc,
504 struct drm_framebuffer *fb,
505 int x, int y);
20afbda2 506 void (*hpd_irq_setup)(struct drm_device *dev);
e70236a8
JB		 507 /* clock updates for mode set */
508 /* cursor updates */
509 /* render clock increase/decrease */
510 /* display clock increase/decrease */
511 /* pll clock increase/decrease */
7bd688cd
JN		 512
513 int (*setup_backlight)(struct intel_connector *connector);
7bd688cd
JN		 514 uint32_t (*get_backlight)(struct intel_connector *connector);
515 void (*set_backlight)(struct intel_connector *connector,
516 uint32_t level);
517 void (*disable_backlight)(struct intel_connector *connector);
518 void (*enable_backlight)(struct intel_connector *connector);
e70236a8
JB		 519};
520
907b28c5 521struct intel_uncore_funcs {
c8d9a590
D		 522 void (*force_wake_get)(struct drm_i915_private *dev_priv,
523 int fw_engine);
524 void (*force_wake_put)(struct drm_i915_private *dev_priv,
525 int fw_engine);
0b274481
BW		 526
527 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
528 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
529 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
530 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
531
532 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
533 uint8_t val, bool trace);
534 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
535 uint16_t val, bool trace);
536 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
537 uint32_t val, bool trace);
538 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
539 uint64_t val, bool trace);
990bbdad
CW		 540};
541
907b28c5
CW		 542struct intel_uncore {
543 spinlock_t lock; /** lock is also taken in irq contexts. */
544
545 struct intel_uncore_funcs funcs;
546
547 unsigned fifo_count;
548 unsigned forcewake_count;
aec347ab 549
940aece4
D		 550 unsigned fw_rendercount;
551 unsigned fw_mediacount;
552
8232644c 553 struct timer_list force_wake_timer;
907b28c5
CW		 554};
555
79fc46df
DL		 556#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
557 func(is_mobile) sep \
558 func(is_i85x) sep \
559 func(is_i915g) sep \
560 func(is_i945gm) sep \
561 func(is_g33) sep \
562 func(need_gfx_hws) sep \
563 func(is_g4x) sep \
564 func(is_pineview) sep \
565 func(is_broadwater) sep \
566 func(is_crestline) sep \
567 func(is_ivybridge) sep \
568 func(is_valleyview) sep \
569 func(is_haswell) sep \
7201c0b3 570 func(is_skylake) sep \
b833d685 571 func(is_preliminary) sep \
79fc46df
DL		 572 func(has_fbc) sep \
573 func(has_pipe_cxsr) sep \
574 func(has_hotplug) sep \
575 func(cursor_needs_physical) sep \
576 func(has_overlay) sep \
577 func(overlay_needs_physical) sep \
578 func(supports_tv) sep \
dd93be58 579 func(has_llc) sep \
30568c45
DL		 580 func(has_ddi) sep \
581 func(has_fpga_dbg)
c96ea64e 582
a587f779
DL		 583#define DEFINE_FLAG(name) u8 name:1
584#define SEP_SEMICOLON ;
c96ea64e 585
cfdf1fa2 586struct intel_device_info {
10fce67a 587 u32 display_mmio_offset;
87f1f465 588 u16 device_id;
7eb552ae 589 u8 num_pipes:3;
d615a166 590 u8 num_sprites[I915_MAX_PIPES];
c96c3a8c 591 u8 gen;
73ae478c 592 u8 ring_mask; /* Rings supported by the HW */
a587f779 593 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
a57c774a
AK		 594 /* Register offsets for the various display pipes and transcoders */
595 int pipe_offsets[I915_MAX_TRANSCODERS];
596 int trans_offsets[I915_MAX_TRANSCODERS];
a57c774a 597 int palette_offsets[I915_MAX_PIPES];
5efb3e28 598 int cursor_offsets[I915_MAX_PIPES];
cfdf1fa2
KH		 599};
600
a587f779
DL		 601#undef DEFINE_FLAG
602#undef SEP_SEMICOLON
603
7faf1ab2
DV		 604enum i915_cache_level {
605 I915_CACHE_NONE = 0,
350ec881
CW		 606 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
607 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
608 caches, eg sampler/render caches, and the
609 large Last-Level-Cache. LLC is coherent with
610 the CPU, but L3 is only visible to the GPU. */
651d794f 611 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
7faf1ab2
DV		 612};
613
e59ec13d
MK		 614struct i915_ctx_hang_stats {
615 /* This context had batch pending when hang was declared */
616 unsigned batch_pending;
617
618 /* This context had batch active when hang was declared */
619 unsigned batch_active;
be62acb4
MK		 620
621 /* Time when this context was last blamed for a GPU reset */
622 unsigned long guilty_ts;
623
624 /* This context is banned to submit more work */
625 bool banned;
e59ec13d 626};
40521054
BW		 627
628/* This must match up with the value previously used for execbuf2.rsvd1. */
821d66dd 629#define DEFAULT_CONTEXT_HANDLE 0
31b7a88d
OM		 630/**
631 * struct intel_context - as the name implies, represents a context.
632 * @ref: reference count.
633 * @user_handle: userspace tracking identity for this context.
634 * @remap_slice: l3 row remapping information.
635 * @file_priv: filp associated with this context (NULL for global default
636 * context).
637 * @hang_stats: information about the role of this context in possible GPU
638 * hangs.
639 * @vm: virtual memory space used by this context.
640 * @legacy_hw_ctx: render context backing object and whether it is correctly
641 * initialized (legacy ring submission mechanism only).
642 * @link: link in the global list of contexts.
643 *
644 * Contexts are memory images used by the hardware to store copies of their
645 * internal state.
646 */
273497e5 647struct intel_context {
dce3271b 648 struct kref ref;
821d66dd 649 int user_handle;
3ccfd19d 650 uint8_t remap_slice;
40521054 651 struct drm_i915_file_private *file_priv;
e59ec13d 652 struct i915_ctx_hang_stats hang_stats;
ae6c4806 653 struct i915_hw_ppgtt *ppgtt;
a33afea5 654
c9e003af 655 /* Legacy ring buffer submission */
ea0c76f8
OM		 656 struct {
657 struct drm_i915_gem_object *rcs_state;
658 bool initialized;
659 } legacy_hw_ctx;
660
c9e003af 661 /* Execlists */
564ddb2f 662 bool rcs_initialized;
c9e003af
OM		 663 struct {
664 struct drm_i915_gem_object *state;
84c2377f 665 struct intel_ringbuffer *ringbuf;
c9e003af
OM		 666 } engine[I915_NUM_RINGS];
667
a33afea5 668 struct list_head link;
40521054
BW		 669};
670
5c3fe8b0
BW		 671struct i915_fbc {
672 unsigned long size;
5e59f717 673 unsigned threshold;
5c3fe8b0
BW		 674 unsigned int fb_id;
675 enum plane plane;
676 int y;
677
c4213885 678 struct drm_mm_node compressed_fb;
5c3fe8b0
BW		 679 struct drm_mm_node *compressed_llb;
680
da46f936
RV		 681 bool false_color;
682
9adccc60
PZ		 683 /* Tracks whether the HW is actually enabled, not whether the feature is
684 * possible. */
685 bool enabled;
686
1d73c2a8
RV		 687 /* On gen8 some rings cannont perform fbc clean operation so for now
688 * we are doing this on SW with mmio.
689 * This variable works in the opposite information direction
690 * of ring->fbc_dirty telling software on frontbuffer tracking
691 * to perform the cache clean on sw side.
692 */
693 bool need_sw_cache_clean;
694
5c3fe8b0
BW		 695 struct intel_fbc_work {
696 struct delayed_work work;
697 struct drm_crtc *crtc;
698 struct drm_framebuffer *fb;
5c3fe8b0
BW		 699 } *fbc_work;
700
29ebf90f
CW		 701 enum no_fbc_reason {
702 FBC_OK, /* FBC is enabled */
703 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
5c3fe8b0
BW		 704 FBC_NO_OUTPUT, /* no outputs enabled to compress */
705 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
706 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
707 FBC_MODE_TOO_LARGE, /* mode too large for compression */
708 FBC_BAD_PLANE, /* fbc not supported on plane */
709 FBC_NOT_TILED, /* buffer not tiled */
710 FBC_MULTIPLE_PIPES, /* more than one pipe active */
711 FBC_MODULE_PARAM,
712 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
713 } no_fbc_reason;
b5e50c3f
JB		 714};
715
439d7ac0
PB		 716struct i915_drrs {
717 struct intel_connector *connector;
718};
719
2807cf69 720struct intel_dp;
a031d709 721struct i915_psr {
f0355c4a 722 struct mutex lock;
a031d709
RV		 723 bool sink_support;
724 bool source_ok;
2807cf69 725 struct intel_dp *enabled;
7c8f8a70
RV		 726 bool active;
727 struct delayed_work work;
9ca15301 728 unsigned busy_frontbuffer_bits;
3f51e471 729};
5c3fe8b0 730
3bad0781 731enum intel_pch {
f0350830 732 PCH_NONE = 0, /* No PCH present */
3bad0781
ZW		 733 PCH_IBX, /* Ibexpeak PCH */
734 PCH_CPT, /* Cougarpoint PCH */
eb877ebf 735 PCH_LPT, /* Lynxpoint PCH */
e7e7ea20 736 PCH_SPT, /* Sunrisepoint PCH */
40c7ead9 737 PCH_NOP,
3bad0781
ZW		 738};
739
988d6ee8
PZ		 740enum intel_sbi_destination {
741 SBI_ICLK,
742 SBI_MPHY,
743};
744
b690e96c 745#define QUIRK_PIPEA_FORCE (1<<0)
435793df 746#define QUIRK_LVDS_SSC_DISABLE (1<<1)
4dca20ef 747#define QUIRK_INVERT_BRIGHTNESS (1<<2)
9c72cc6f 748#define QUIRK_BACKLIGHT_PRESENT (1<<3)
b6b5d049 749#define QUIRK_PIPEB_FORCE (1<<4)
b690e96c 750
8be48d92 751struct intel_fbdev;
1630fe75 752struct intel_fbc_work;
38651674 753
c2b9152f
DV		 754struct intel_gmbus {
755 struct i2c_adapter adapter;
f2ce9faf 756 u32 force_bit;
c2b9152f 757 u32 reg0;
36c785f0 758 u32 gpio_reg;
c167a6fc 759 struct i2c_algo_bit_data bit_algo;
c2b9152f
DV		 760 struct drm_i915_private *dev_priv;
761};
762
f4c956ad 763struct i915_suspend_saved_registers {
ba8bbcf6
JB		 764 u8 saveLBB;
765 u32 saveDSPACNTR;
766 u32 saveDSPBCNTR;
e948e994 767 u32 saveDSPARB;
ba8bbcf6
JB		 768 u32 savePIPEACONF;
769 u32 savePIPEBCONF;
770 u32 savePIPEASRC;
771 u32 savePIPEBSRC;
772 u32 saveFPA0;
773 u32 saveFPA1;
774 u32 saveDPLL_A;
775 u32 saveDPLL_A_MD;
776 u32 saveHTOTAL_A;
777 u32 saveHBLANK_A;
778 u32 saveHSYNC_A;
779 u32 saveVTOTAL_A;
780 u32 saveVBLANK_A;
781 u32 saveVSYNC_A;
782 u32 saveBCLRPAT_A;
5586c8bc 783 u32 saveTRANSACONF;
42048781
ZW		 784 u32 saveTRANS_HTOTAL_A;
785 u32 saveTRANS_HBLANK_A;
786 u32 saveTRANS_HSYNC_A;
787 u32 saveTRANS_VTOTAL_A;
788 u32 saveTRANS_VBLANK_A;
789 u32 saveTRANS_VSYNC_A;
0da3ea12 790 u32 savePIPEASTAT;
ba8bbcf6
JB		 791 u32 saveDSPASTRIDE;
792 u32 saveDSPASIZE;
793 u32 saveDSPAPOS;
585fb111 794 u32 saveDSPAADDR;
ba8bbcf6
JB		 795 u32 saveDSPASURF;
796 u32 saveDSPATILEOFF;
797 u32 savePFIT_PGM_RATIOS;
0eb96d6e 798 u32 saveBLC_HIST_CTL;
ba8bbcf6
JB		 799 u32 saveBLC_PWM_CTL;
800 u32 saveBLC_PWM_CTL2;
07bf139b 801 u32 saveBLC_HIST_CTL_B;
42048781
ZW		 802 u32 saveBLC_CPU_PWM_CTL;
803 u32 saveBLC_CPU_PWM_CTL2;
ba8bbcf6
JB		 804 u32 saveFPB0;
805 u32 saveFPB1;
806 u32 saveDPLL_B;
807 u32 saveDPLL_B_MD;
808 u32 saveHTOTAL_B;
809 u32 saveHBLANK_B;
810 u32 saveHSYNC_B;
811 u32 saveVTOTAL_B;
812 u32 saveVBLANK_B;
813 u32 saveVSYNC_B;
814 u32 saveBCLRPAT_B;
5586c8bc 815 u32 saveTRANSBCONF;
42048781
ZW		 816 u32 saveTRANS_HTOTAL_B;
817 u32 saveTRANS_HBLANK_B;
818 u32 saveTRANS_HSYNC_B;
819 u32 saveTRANS_VTOTAL_B;
820 u32 saveTRANS_VBLANK_B;
821 u32 saveTRANS_VSYNC_B;
0da3ea12 822 u32 savePIPEBSTAT;
ba8bbcf6
JB		 823 u32 saveDSPBSTRIDE;
824 u32 saveDSPBSIZE;
825 u32 saveDSPBPOS;
585fb111 826 u32 saveDSPBADDR;
ba8bbcf6
JB		 827 u32 saveDSPBSURF;
828 u32 saveDSPBTILEOFF;
585fb111
JB		 829 u32 saveVGA0;
830 u32 saveVGA1;
831 u32 saveVGA_PD;
ba8bbcf6
JB		 832 u32 saveVGACNTRL;
833 u32 saveADPA;
834 u32 saveLVDS;
585fb111
JB		 835 u32 savePP_ON_DELAYS;
836 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB		 837 u32 saveDVOA;
838 u32 saveDVOB;
839 u32 saveDVOC;
840 u32 savePP_ON;
841 u32 savePP_OFF;
842 u32 savePP_CONTROL;
585fb111 843 u32 savePP_DIVISOR;
ba8bbcf6
JB		 844 u32 savePFIT_CONTROL;
845 u32 save_palette_a[256];
846 u32 save_palette_b[256];
ba8bbcf6 847 u32 saveFBC_CONTROL;
0da3ea12
JB		 848 u32 saveIER;
849 u32 saveIIR;
850 u32 saveIMR;
42048781
ZW		 851 u32 saveDEIER;
852 u32 saveDEIMR;
853 u32 saveGTIER;
854 u32 saveGTIMR;
855 u32 saveFDI_RXA_IMR;
856 u32 saveFDI_RXB_IMR;
1f84e550 857 u32 saveCACHE_MODE_0;
1f84e550 858 u32 saveMI_ARB_STATE;
ba8bbcf6
JB		 859 u32 saveSWF0[16];
860 u32 saveSWF1[16];
861 u32 saveSWF2[3];
862 u8 saveMSR;
863 u8 saveSR[8];
123f794f 864 u8 saveGR[25];
ba8bbcf6 865 u8 saveAR_INDEX;
a59e122a 866 u8 saveAR[21];
ba8bbcf6 867 u8 saveDACMASK;
a59e122a 868 u8 saveCR[37];
4b9de737 869 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1fd1c624
EA		 870 u32 saveCURACNTR;
871 u32 saveCURAPOS;
872 u32 saveCURABASE;
873 u32 saveCURBCNTR;
874 u32 saveCURBPOS;
875 u32 saveCURBBASE;
876 u32 saveCURSIZE;
a4fc5ed6
KP		 877 u32 saveDP_B;
878 u32 saveDP_C;
879 u32 saveDP_D;
880 u32 savePIPEA_GMCH_DATA_M;
881 u32 savePIPEB_GMCH_DATA_M;
882 u32 savePIPEA_GMCH_DATA_N;
883 u32 savePIPEB_GMCH_DATA_N;
884 u32 savePIPEA_DP_LINK_M;
885 u32 savePIPEB_DP_LINK_M;
886 u32 savePIPEA_DP_LINK_N;
887 u32 savePIPEB_DP_LINK_N;
42048781
ZW		 888 u32 saveFDI_RXA_CTL;
889 u32 saveFDI_TXA_CTL;
890 u32 saveFDI_RXB_CTL;
891 u32 saveFDI_TXB_CTL;
892 u32 savePFA_CTL_1;
893 u32 savePFB_CTL_1;
894 u32 savePFA_WIN_SZ;
895 u32 savePFB_WIN_SZ;
896 u32 savePFA_WIN_POS;
897 u32 savePFB_WIN_POS;
5586c8bc
ZW		 898 u32 savePCH_DREF_CONTROL;
899 u32 saveDISP_ARB_CTL;
900 u32 savePIPEA_DATA_M1;
901 u32 savePIPEA_DATA_N1;
902 u32 savePIPEA_LINK_M1;
903 u32 savePIPEA_LINK_N1;
904 u32 savePIPEB_DATA_M1;
905 u32 savePIPEB_DATA_N1;
906 u32 savePIPEB_LINK_M1;
907 u32 savePIPEB_LINK_N1;
b5b72e89 908 u32 saveMCHBAR_RENDER_STANDBY;
cda2bb78 909 u32 savePCH_PORT_HOTPLUG;
f4c956ad 910};
c85aa885 911
ddeea5b0
ID		 912struct vlv_s0ix_state {
913 /* GAM */
914 u32 wr_watermark;
915 u32 gfx_prio_ctrl;
916 u32 arb_mode;
917 u32 gfx_pend_tlb0;
918 u32 gfx_pend_tlb1;
919 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
920 u32 media_max_req_count;
921 u32 gfx_max_req_count;
922 u32 render_hwsp;
923 u32 ecochk;
924 u32 bsd_hwsp;
925 u32 blt_hwsp;
926 u32 tlb_rd_addr;
927
928 /* MBC */
929 u32 g3dctl;
930 u32 gsckgctl;
931 u32 mbctl;
932
933 /* GCP */
934 u32 ucgctl1;
935 u32 ucgctl3;
936 u32 rcgctl1;
937 u32 rcgctl2;
938 u32 rstctl;
939 u32 misccpctl;
940
941 /* GPM */
942 u32 gfxpause;
943 u32 rpdeuhwtc;
944 u32 rpdeuc;
945 u32 ecobus;
946 u32 pwrdwnupctl;
947 u32 rp_down_timeout;
948 u32 rp_deucsw;
949 u32 rcubmabdtmr;
950 u32 rcedata;
951 u32 spare2gh;
952
953 /* Display 1 CZ domain */
954 u32 gt_imr;
955 u32 gt_ier;
956 u32 pm_imr;
957 u32 pm_ier;
958 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
959
960 /* GT SA CZ domain */
961 u32 tilectl;
962 u32 gt_fifoctl;
963 u32 gtlc_wake_ctrl;
964 u32 gtlc_survive;
965 u32 pmwgicz;
966
967 /* Display 2 CZ domain */
968 u32 gu_ctl0;
969 u32 gu_ctl1;
970 u32 clock_gate_dis2;
971};
972
bf225f20
CW		 973struct intel_rps_ei {
974 u32 cz_clock;
975 u32 render_c0;
976 u32 media_c0;
31685c25
D		 977};
978
c85aa885 979struct intel_gen6_power_mgmt {
59cdb63d 980 /* work and pm_iir are protected by dev_priv->irq_lock */
c85aa885
DV		 981 struct work_struct work;
982 u32 pm_iir;
59cdb63d 983
b39fb297
BW		 984 /* Frequencies are stored in potentially platform dependent multiples.
985 * In other words, *_freq needs to be multiplied by X to be interesting.
986 * Soft limits are those which are used for the dynamic reclocking done
987 * by the driver (raise frequencies under heavy loads, and lower for
988 * lighter loads). Hard limits are those imposed by the hardware.
989 *
990 * A distinction is made for overclocking, which is never enabled by
991 * default, and is considered to be above the hard limit if it's
992 * possible at all.
993 */
994 u8 cur_freq; /* Current frequency (cached, may not == HW) */
995 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
996 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
997 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
998 u8 min_freq; /* AKA RPn. Minimum frequency */
999 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1000 u8 rp1_freq; /* "less than" RP0 power/freqency */
1001 u8 rp0_freq; /* Non-overclocked max frequency. */
67c3bf6f 1002 u32 cz_freq;
1a01ab3b 1003
31685c25 1004 u32 ei_interrupt_count;
1a01ab3b 1005
dd75fdc8
CW		 1006 int last_adj;
1007 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1008
c0951f0c 1009 bool enabled;
1a01ab3b 1010 struct delayed_work delayed_resume_work;
4fc688ce 1011
bf225f20
CW		 1012 /* manual wa residency calculations */
1013 struct intel_rps_ei up_ei, down_ei;
1014
4fc688ce
JB		 1015 /*
1016 * Protects RPS/RC6 register access and PCU communication.
1017 * Must be taken after struct_mutex if nested.
1018 */
1019 struct mutex hw_lock;
c85aa885
DV		 1020};
1021
1a240d4d
DV		 1022/* defined intel_pm.c */
1023extern spinlock_t mchdev_lock;
1024
c85aa885
DV		 1025struct intel_ilk_power_mgmt {
1026 u8 cur_delay;
1027 u8 min_delay;
1028 u8 max_delay;
1029 u8 fmax;
1030 u8 fstart;
1031
1032 u64 last_count1;
1033 unsigned long last_time1;
1034 unsigned long chipset_power;
1035 u64 last_count2;
5ed0bdf2 1036 u64 last_time2;
c85aa885
DV		 1037 unsigned long gfx_power;
1038 u8 corr;
1039
1040 int c_m;
1041 int r_t;
3e373948
DV		 1042
1043 struct drm_i915_gem_object *pwrctx;
1044 struct drm_i915_gem_object *renderctx;
c85aa885
DV		 1045};
1046
c6cb582e
ID		 1047struct drm_i915_private;
1048struct i915_power_well;
1049
1050struct i915_power_well_ops {
1051 /*
1052 * Synchronize the well's hw state to match the current sw state, for
1053 * example enable/disable it based on the current refcount. Called
1054 * during driver init and resume time, possibly after first calling
1055 * the enable/disable handlers.
1056 */
1057 void (*sync_hw)(struct drm_i915_private *dev_priv,
1058 struct i915_power_well *power_well);
1059 /*
1060 * Enable the well and resources that depend on it (for example
1061 * interrupts located on the well). Called after the 0->1 refcount
1062 * transition.
1063 */
1064 void (*enable)(struct drm_i915_private *dev_priv,
1065 struct i915_power_well *power_well);
1066 /*
1067 * Disable the well and resources that depend on it. Called after
1068 * the 1->0 refcount transition.
1069 */
1070 void (*disable)(struct drm_i915_private *dev_priv,
1071 struct i915_power_well *power_well);
1072 /* Returns the hw enabled state. */
1073 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1074 struct i915_power_well *power_well);
1075};
1076
a38911a3
WX		 1077/* Power well structure for haswell */
1078struct i915_power_well {
c1ca727f 1079 const char *name;
6f3ef5dd 1080 bool always_on;
a38911a3
WX		 1081 /* power well enable/disable usage count */
1082 int count;
bfafe93a
ID		 1083 /* cached hw enabled state */
1084 bool hw_enabled;
c1ca727f 1085 unsigned long domains;
77961eb9 1086 unsigned long data;
c6cb582e 1087 const struct i915_power_well_ops *ops;
a38911a3
WX		 1088};
1089
83c00f55 1090struct i915_power_domains {
baa70707
ID		 1091 /*
1092 * Power wells needed for initialization at driver init and suspend
1093 * time are on. They are kept on until after the first modeset.
1094 */
1095 bool init_power_on;
0d116a29 1096 bool initializing;
c1ca727f 1097 int power_well_count;
baa70707 1098
83c00f55 1099 struct mutex lock;
1da51581 1100 int domain_use_count[POWER_DOMAIN_NUM];
c1ca727f 1101 struct i915_power_well *power_wells;
83c00f55
ID		 1102};
1103
231f42a4
DV		 1104struct i915_dri1_state {
1105 unsigned allow_batchbuffer : 1;
1106 u32 __iomem *gfx_hws_cpu_addr;
1107
1108 unsigned int cpp;
1109 int back_offset;
1110 int front_offset;
1111 int current_page;
1112 int page_flipping;
1113
1114 uint32_t counter;
1115};
1116
db1b76ca
DV		 1117struct i915_ums_state {
1118 /**
1119 * Flag if the X Server, and thus DRM, is not currently in
1120 * control of the device.
1121 *
1122 * This is set between LeaveVT and EnterVT. It needs to be
1123 * replaced with a semaphore. It also needs to be
1124 * transitioned away from for kernel modesetting.
1125 */
1126 int mm_suspended;
1127};
1128
35a85ac6 1129#define MAX_L3_SLICES 2
a4da4fa4 1130struct intel_l3_parity {
35a85ac6 1131 u32 *remap_info[MAX_L3_SLICES];
a4da4fa4 1132 struct work_struct error_work;
35a85ac6 1133 int which_slice;
a4da4fa4
DV		 1134};
1135
4b5aed62 1136struct i915_gem_mm {
4b5aed62
DV		 1137 /** Memory allocator for GTT stolen memory */
1138 struct drm_mm stolen;
4b5aed62
DV		 1139 /** List of all objects in gtt_space. Used to restore gtt
1140 * mappings on resume */
1141 struct list_head bound_list;
1142 /**
1143 * List of objects which are not bound to the GTT (thus
1144 * are idle and not used by the GPU) but still have
1145 * (presumably uncached) pages still attached.
1146 */
1147 struct list_head unbound_list;
1148
1149 /** Usable portion of the GTT for GEM */
1150 unsigned long stolen_base; /* limited to low memory (32-bit) */
1151
4b5aed62
DV		 1152 /** PPGTT used for aliasing the PPGTT with the GTT */
1153 struct i915_hw_ppgtt *aliasing_ppgtt;
1154
2cfcd32a 1155 struct notifier_block oom_notifier;
ceabbba5 1156 struct shrinker shrinker;
4b5aed62
DV		 1157 bool shrinker_no_lock_stealing;
1158
4b5aed62
DV		 1159 /** LRU list of objects with fence regs on them. */
1160 struct list_head fence_list;
1161
1162 /**
1163 * We leave the user IRQ off as much as possible,
1164 * but this means that requests will finish and never
1165 * be retired once the system goes idle. Set a timer to
1166 * fire periodically while the ring is running. When it
1167 * fires, go retire requests.
1168 */
1169 struct delayed_work retire_work;
1170
b29c19b6
CW		 1171 /**
1172 * When we detect an idle GPU, we want to turn on
1173 * powersaving features. So once we see that there
1174 * are no more requests outstanding and no more
1175 * arrive within a small period of time, we fire
1176 * off the idle_work.
1177 */
1178 struct delayed_work idle_work;
1179
4b5aed62
DV		 1180 /**
1181 * Are we in a non-interruptible section of code like
1182 * modesetting?
1183 */
1184 bool interruptible;
1185
f62a0076
CW		 1186 /**
1187 * Is the GPU currently considered idle, or busy executing userspace
1188 * requests? Whilst idle, we attempt to power down the hardware and
1189 * display clocks. In order to reduce the effect on performance, there
1190 * is a slight delay before we do so.
1191 */
1192 bool busy;
1193
bdf1e7e3
DV		 1194 /* the indicator for dispatch video commands on two BSD rings */
1195 int bsd_ring_dispatch_index;
1196
4b5aed62
DV		 1197 /** Bit 6 swizzling required for X tiling */
1198 uint32_t bit_6_swizzle_x;
1199 /** Bit 6 swizzling required for Y tiling */
1200 uint32_t bit_6_swizzle_y;
1201
4b5aed62 1202 /* accounting, useful for userland debugging */
c20e8355 1203 spinlock_t object_stat_lock;
4b5aed62
DV		 1204 size_t object_memory;
1205 u32 object_count;
1206};
1207
edc3d884 1208struct drm_i915_error_state_buf {
0a4cd7c8 1209 struct drm_i915_private *i915;
edc3d884
MK		 1210 unsigned bytes;
1211 unsigned size;
1212 int err;
1213 u8 *buf;
1214 loff_t start;
1215 loff_t pos;
1216};
1217
fc16b48b
MK		 1218struct i915_error_state_file_priv {
1219 struct drm_device *dev;
1220 struct drm_i915_error_state *error;
1221};
1222
99584db3
DV		 1223struct i915_gpu_error {
1224 /* For hangcheck timer */
1225#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1226#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
be62acb4
MK		 1227 /* Hang gpu twice in this window and your context gets banned */
1228#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1229
99584db3 1230 struct timer_list hangcheck_timer;
99584db3
DV		 1231
1232 /* For reset and error_state handling. */
1233 spinlock_t lock;
1234 /* Protected by the above dev->gpu_error.lock. */
1235 struct drm_i915_error_state *first_error;
1236 struct work_struct work;
99584db3 1237
094f9a54
CW		 1238
1239 unsigned long missed_irq_rings;
1240
1f83fee0 1241 /**
2ac0f450 1242 * State variable controlling the reset flow and count
1f83fee0 1243 *
2ac0f450
MK		 1244 * This is a counter which gets incremented when reset is triggered,
1245 * and again when reset has been handled. So odd values (lowest bit set)
1246 * means that reset is in progress and even values that
1247 * (reset_counter >> 1):th reset was successfully completed.
1248 *
1249 * If reset is not completed succesfully, the I915_WEDGE bit is
1250 * set meaning that hardware is terminally sour and there is no
1251 * recovery. All waiters on the reset_queue will be woken when
1252 * that happens.
1253 *
1254 * This counter is used by the wait_seqno code to notice that reset
1255 * event happened and it needs to restart the entire ioctl (since most
1256 * likely the seqno it waited for won't ever signal anytime soon).
f69061be
DV		 1257 *
1258 * This is important for lock-free wait paths, where no contended lock
1259 * naturally enforces the correct ordering between the bail-out of the
1260 * waiter and the gpu reset work code.
1f83fee0
DV		 1261 */
1262 atomic_t reset_counter;
1263
1f83fee0 1264#define I915_RESET_IN_PROGRESS_FLAG 1
2ac0f450 1265#define I915_WEDGED (1 << 31)
1f83fee0
DV		 1266
1267 /**
1268 * Waitqueue to signal when the reset has completed. Used by clients
1269 * that wait for dev_priv->mm.wedged to settle.
1270 */
1271 wait_queue_head_t reset_queue;
33196ded 1272
88b4aa87
MK		 1273 /* Userspace knobs for gpu hang simulation;
1274 * combines both a ring mask, and extra flags
1275 */
1276 u32 stop_rings;
1277#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1278#define I915_STOP_RING_ALLOW_WARN (1 << 30)
094f9a54
CW		 1279
1280 /* For missed irq/seqno simulation. */
1281 unsigned int test_irq_rings;
6689c167
MA		 1282
1283 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1284 bool reload_in_reset;
99584db3
DV		 1285};
1286
b8efb17b
ZR		 1287enum modeset_restore {
1288 MODESET_ON_LID_OPEN,
1289 MODESET_DONE,
1290 MODESET_SUSPENDED,
1291};
1292
6acab15a 1293struct ddi_vbt_port_info {
ce4dd49e
DL		 1294 /*
1295 * This is an index in the HDMI/DVI DDI buffer translation table.
1296 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1297 * populate this field.
1298 */
1299#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
6acab15a 1300 uint8_t hdmi_level_shift;
311a2094
PZ		 1301
1302 uint8_t supports_dvi:1;
1303 uint8_t supports_hdmi:1;
1304 uint8_t supports_dp:1;
6acab15a
PZ		 1305};
1306
83a7280e
PB		 1307enum drrs_support_type {
1308 DRRS_NOT_SUPPORTED = 0,
1309 STATIC_DRRS_SUPPORT = 1,
1310 SEAMLESS_DRRS_SUPPORT = 2
1311};
1312
41aa3448
RV		 1313struct intel_vbt_data {
1314 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1315 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1316
1317 /* Feature bits */
1318 unsigned int int_tv_support:1;
1319 unsigned int lvds_dither:1;
1320 unsigned int lvds_vbt:1;
1321 unsigned int int_crt_support:1;
1322 unsigned int lvds_use_ssc:1;
1323 unsigned int display_clock_mode:1;
1324 unsigned int fdi_rx_polarity_inverted:1;
3e6bd011 1325 unsigned int has_mipi:1;
41aa3448
RV		 1326 int lvds_ssc_freq;
1327 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1328
83a7280e
PB		 1329 enum drrs_support_type drrs_type;
1330
41aa3448
RV		 1331 /* eDP */
1332 int edp_rate;
1333 int edp_lanes;
1334 int edp_preemphasis;
1335 int edp_vswing;
1336 bool edp_initialized;
1337 bool edp_support;
1338 int edp_bpp;
1339 struct edp_power_seq edp_pps;
1340
f00076d2
JN		 1341 struct {
1342 u16 pwm_freq_hz;
39fbc9c8 1343 bool present;
f00076d2 1344 bool active_low_pwm;
1de6068e 1345 u8 min_brightness; /* min_brightness/255 of max */
f00076d2
JN		 1346 } backlight;
1347
d17c5443
SK		 1348 /* MIPI DSI */
1349 struct {
3e6bd011 1350 u16 port;
d17c5443 1351 u16 panel_id;
d3b542fc
SK		 1352 struct mipi_config *config;
1353 struct mipi_pps_data *pps;
1354 u8 seq_version;
1355 u32 size;
1356 u8 *data;
1357 u8 *sequence[MIPI_SEQ_MAX];
d17c5443
SK		 1358 } dsi;
1359
41aa3448
RV		 1360 int crt_ddc_pin;
1361
1362 int child_dev_num;
768f69c9 1363 union child_device_config *child_dev;
6acab15a
PZ		 1364
1365 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
41aa3448
RV		 1366};
1367
77c122bc
VS		 1368enum intel_ddb_partitioning {
1369 INTEL_DDB_PART_1_2,
1370 INTEL_DDB_PART_5_6, /* IVB+ */
1371};
1372
1fd527cc
VS		 1373struct intel_wm_level {
1374 bool enable;
1375 uint32_t pri_val;
1376 uint32_t spr_val;
1377 uint32_t cur_val;
1378 uint32_t fbc_val;
1379};
1380
820c1980 1381struct ilk_wm_values {
609cedef
VS		 1382 uint32_t wm_pipe[3];
1383 uint32_t wm_lp[3];
1384 uint32_t wm_lp_spr[3];
1385 uint32_t wm_linetime[3];
1386 bool enable_fbc_wm;
1387 enum intel_ddb_partitioning partitioning;
1388};
1389
c67a470b 1390/*
765dab67
PZ		 1391 * This struct helps tracking the state needed for runtime PM, which puts the
1392 * device in PCI D3 state. Notice that when this happens, nothing on the
1393 * graphics device works, even register access, so we don't get interrupts nor
1394 * anything else.
c67a470b 1395 *
765dab67
PZ		 1396 * Every piece of our code that needs to actually touch the hardware needs to
1397 * either call intel_runtime_pm_get or call intel_display_power_get with the
1398 * appropriate power domain.
a8a8bd54 1399 *
765dab67
PZ		 1400 * Our driver uses the autosuspend delay feature, which means we'll only really
1401 * suspend if we stay with zero refcount for a certain amount of time. The
f458ebbc 1402 * default value is currently very conservative (see intel_runtime_pm_enable), but
765dab67 1403 * it can be changed with the standard runtime PM files from sysfs.
c67a470b
PZ		 1404 *
1405 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1406 * goes back to false exactly before we reenable the IRQs. We use this variable
1407 * to check if someone is trying to enable/disable IRQs while they're supposed
1408 * to be disabled. This shouldn't happen and we'll print some error messages in
730488b2 1409 * case it happens.
c67a470b 1410 *
765dab67 1411 * For more, read the Documentation/power/runtime_pm.txt.
c67a470b 1412 */
5d584b2e
PZ		 1413struct i915_runtime_pm {
1414 bool suspended;
2aeb7d3a 1415 bool irqs_enabled;
c67a470b
PZ		 1416};
1417
926321d5
DV		 1418enum intel_pipe_crc_source {
1419 INTEL_PIPE_CRC_SOURCE_NONE,
1420 INTEL_PIPE_CRC_SOURCE_PLANE1,
1421 INTEL_PIPE_CRC_SOURCE_PLANE2,
1422 INTEL_PIPE_CRC_SOURCE_PF,
5b3a856b 1423 INTEL_PIPE_CRC_SOURCE_PIPE,
3d099a05
DV		 1424 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1425 INTEL_PIPE_CRC_SOURCE_TV,
1426 INTEL_PIPE_CRC_SOURCE_DP_B,
1427 INTEL_PIPE_CRC_SOURCE_DP_C,
1428 INTEL_PIPE_CRC_SOURCE_DP_D,
46a19188 1429 INTEL_PIPE_CRC_SOURCE_AUTO,
926321d5
DV		 1430 INTEL_PIPE_CRC_SOURCE_MAX,
1431};
1432
8bf1e9f1 1433struct intel_pipe_crc_entry {
ac2300d4 1434 uint32_t frame;
8bf1e9f1
SH		 1435 uint32_t crc[5];
1436};
1437
b2c88f5b 1438#define INTEL_PIPE_CRC_ENTRIES_NR 128
8bf1e9f1 1439struct intel_pipe_crc {
d538bbdf
DL		 1440 spinlock_t lock;
1441 bool opened; /* exclusive access to the result file */
e5f75aca 1442 struct intel_pipe_crc_entry *entries;
926321d5 1443 enum intel_pipe_crc_source source;
d538bbdf 1444 int head, tail;
07144428 1445 wait_queue_head_t wq;
8bf1e9f1
SH		 1446};
1447
f99d7069
DV		 1448struct i915_frontbuffer_tracking {
1449 struct mutex lock;
1450
1451 /*
1452 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1453 * scheduled flips.
1454 */
1455 unsigned busy_bits;
1456 unsigned flip_bits;
1457};
1458
7225342a
MK		 1459struct i915_wa_reg {
1460 u32 addr;
1461 u32 value;
1462 /* bitmask representing WA bits */
1463 u32 mask;
1464};
1465
1466#define I915_MAX_WA_REGS 16
1467
1468struct i915_workarounds {
1469 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1470 u32 count;
1471};
1472
77fec556 1473struct drm_i915_private {
f4c956ad 1474 struct drm_device *dev;
42dcedd4 1475 struct kmem_cache *slab;
f4c956ad 1476
5c969aa7 1477 const struct intel_device_info info;
f4c956ad
DV		 1478
1479 int relative_constants_mode;
1480
1481 void __iomem *regs;
1482
907b28c5 1483 struct intel_uncore uncore;
f4c956ad
DV		 1484
1485 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1486
28c70f16 1487
f4c956ad
DV		 1488 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1489 * controller on different i2c buses. */
1490 struct mutex gmbus_mutex;
1491
1492 /**
1493 * Base address of the gmbus and gpio block.
1494 */
1495 uint32_t gpio_mmio_base;
1496
b6fdd0f2
SS		 1497 /* MMIO base address for MIPI regs */
1498 uint32_t mipi_mmio_base;
1499
28c70f16
DV		 1500 wait_queue_head_t gmbus_wait_queue;
1501
f4c956ad 1502 struct pci_dev *bridge_dev;
a4872ba6 1503 struct intel_engine_cs ring[I915_NUM_RINGS];
3e78998a 1504 struct drm_i915_gem_object *semaphore_obj;
f72b3435 1505 uint32_t last_seqno, next_seqno;
f4c956ad 1506
ba8286fa 1507 struct drm_dma_handle *status_page_dmah;
f4c956ad
DV		 1508 struct resource mch_res;
1509
f4c956ad
DV		 1510 /* protects the irq masks */
1511 spinlock_t irq_lock;
1512
84c33a64
SG		 1513 /* protects the mmio flip data */
1514 spinlock_t mmio_flip_lock;
1515
f8b79e58
ID		 1516 bool display_irqs_enabled;
1517
9ee32fea
DV		 1518 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1519 struct pm_qos_request pm_qos;
1520
f4c956ad 1521 /* DPIO indirect register protection */
09153000 1522 struct mutex dpio_lock;
f4c956ad
DV		 1523
1524 /** Cached value of IMR to avoid reads in updating the bitfield */
abd58f01
BW		 1525 union {
1526 u32 irq_mask;
1527 u32 de_irq_mask[I915_MAX_PIPES];
1528 };
f4c956ad 1529 u32 gt_irq_mask;
605cd25b 1530 u32 pm_irq_mask;
a6706b45 1531 u32 pm_rps_events;
91d181dd 1532 u32 pipestat_irq_mask[I915_MAX_PIPES];
f4c956ad 1533
f4c956ad 1534 struct work_struct hotplug_work;
b543fb04
EE		 1535 struct {
1536 unsigned long hpd_last_jiffies;
1537 int hpd_cnt;
1538 enum {
1539 HPD_ENABLED = 0,
1540 HPD_DISABLED = 1,
1541 HPD_MARK_DISABLED = 2
1542 } hpd_mark;
1543 } hpd_stats[HPD_NUM_PINS];
142e2398 1544 u32 hpd_event_bits;
6323751d 1545 struct delayed_work hotplug_reenable_work;
f4c956ad 1546
5c3fe8b0 1547 struct i915_fbc fbc;
439d7ac0 1548 struct i915_drrs drrs;
f4c956ad 1549 struct intel_opregion opregion;
41aa3448 1550 struct intel_vbt_data vbt;
f4c956ad 1551
d9ceb816
JB		 1552 bool preserve_bios_swizzle;
1553
f4c956ad
DV		 1554 /* overlay */
1555 struct intel_overlay *overlay;
f4c956ad 1556
58c68779 1557 /* backlight registers and fields in struct intel_panel */
07f11d49 1558 struct mutex backlight_lock;
31ad8ec6 1559
f4c956ad 1560 /* LVDS info */
f4c956ad
DV		 1561 bool no_aux_handshake;
1562
e39b999a
VS		 1563 /* protects panel power sequencer state */
1564 struct mutex pps_mutex;
1565
f4c956ad
DV		 1566 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1567 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1568 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1569
1570 unsigned int fsb_freq, mem_freq, is_ddr3;
d60c4473 1571 unsigned int vlv_cdclk_freq;
f4c956ad 1572
645416f5
DV		 1573 /**
1574 * wq - Driver workqueue for GEM.
1575 *
1576 * NOTE: Work items scheduled here are not allowed to grab any modeset
1577 * locks, for otherwise the flushing done in the pageflip code will
1578 * result in deadlocks.
1579 */
f4c956ad
DV		 1580 struct workqueue_struct *wq;
1581
1582 /* Display functions */
1583 struct drm_i915_display_funcs display;
1584
1585 /* PCH chipset type */
1586 enum intel_pch pch_type;
17a303ec 1587 unsigned short pch_id;
f4c956ad
DV		 1588
1589 unsigned long quirks;
1590
b8efb17b
ZR		 1591 enum modeset_restore modeset_restore;
1592 struct mutex modeset_restore_lock;
673a394b 1593
a7bbbd63 1594 struct list_head vm_list; /* Global list of all address spaces */
0260c420 1595 struct i915_gtt gtt; /* VM representing the global address space */
5d4545ae 1596
4b5aed62 1597 struct i915_gem_mm mm;
ad46cb53
CW		 1598 DECLARE_HASHTABLE(mm_structs, 7);
1599 struct mutex mm_lock;
8781342d 1600
8781342d
DV		 1601 /* Kernel Modesetting */
1602
9b9d172d 1603 struct sdvo_device_mapping sdvo_mappings[2];
652c393a 1604
76c4ac04
DL		 1605 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1606 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
6b95a207
KH		 1607 wait_queue_head_t pending_flip_queue;
1608
c4597872
DV		 1609#ifdef CONFIG_DEBUG_FS
1610 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1611#endif
1612
e72f9fbf
DV		 1613 int num_shared_dpll;
1614 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
e4607fcf 1615 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
ee7b9f93 1616
7225342a 1617 struct i915_workarounds workarounds;
888b5995 1618
652c393a
JB		 1619 /* Reclocking support */
1620 bool render_reclock_avail;
1621 bool lvds_downclock_avail;
18f9ed12
ZY		 1622 /* indicates the reduced downclock for LVDS*/
1623 int lvds_downclock;
f99d7069
DV		 1624
1625 struct i915_frontbuffer_tracking fb_tracking;
1626
652c393a 1627 u16 orig_clock;
f97108d1 1628
c4804411 1629 bool mchbar_need_disable;
f97108d1 1630
a4da4fa4
DV		 1631 struct intel_l3_parity l3_parity;
1632
59124506
BW		 1633 /* Cannot be determined by PCIID. You must always read a register. */
1634 size_t ellc_size;
1635
c6a828d3 1636 /* gen6+ rps state */
c85aa885 1637 struct intel_gen6_power_mgmt rps;
c6a828d3 1638
20e4d407
DV		 1639 /* ilk-only ips/rps state. Everything in here is protected by the global
1640 * mchdev_lock in intel_pm.c */
c85aa885 1641 struct intel_ilk_power_mgmt ips;
b5e50c3f 1642
83c00f55 1643 struct i915_power_domains power_domains;
a38911a3 1644
a031d709 1645 struct i915_psr psr;
3f51e471 1646
99584db3 1647 struct i915_gpu_error gpu_error;
ae681d96 1648
c9cddffc
JB		 1649 struct drm_i915_gem_object *vlv_pctx;
1650
4520f53a 1651#ifdef CONFIG_DRM_I915_FBDEV
8be48d92
DA		 1652 /* list of fbdev register on this device */
1653 struct intel_fbdev *fbdev;
82e3b8c1 1654 struct work_struct fbdev_suspend_work;
4520f53a 1655#endif
e953fd7b
CW		 1656
1657 struct drm_property *broadcast_rgb_property;
3f43c48d 1658 struct drm_property *force_audio_property;
e3689190 1659
254f965c 1660 uint32_t hw_context_size;
a33afea5 1661 struct list_head context_list;
f4c956ad 1662
3e68320e 1663 u32 fdi_rx_config;
68d18ad7 1664
842f1c8b 1665 u32 suspend_count;
f4c956ad 1666 struct i915_suspend_saved_registers regfile;
ddeea5b0 1667 struct vlv_s0ix_state vlv_s0ix_state;
231f42a4 1668
53615a5e
VS		 1669 struct {
1670 /*
1671 * Raw watermark latency values:
1672 * in 0.1us units for WM0,
1673 * in 0.5us units for WM1+.
1674 */
1675 /* primary */
1676 uint16_t pri_latency[5];
1677 /* sprite */
1678 uint16_t spr_latency[5];
1679 /* cursor */
1680 uint16_t cur_latency[5];
609cedef
VS		 1681
1682 /* current hardware state */
820c1980 1683 struct ilk_wm_values hw;
53615a5e
VS		 1684 } wm;
1685
8a187455
PZ		 1686 struct i915_runtime_pm pm;
1687
13cf5504
DA		 1688 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1689 u32 long_hpd_port_mask;
1690 u32 short_hpd_port_mask;
1691 struct work_struct dig_port_work;
1692
0e32b39c
DA		 1693 /*
1694 * if we get a HPD irq from DP and a HPD irq from non-DP
1695 * the non-DP HPD could block the workqueue on a mode config
1696 * mutex getting, that userspace may have taken. However
1697 * userspace is waiting on the DP workqueue to run which is
1698 * blocked behind the non-DP one.
1699 */
1700 struct workqueue_struct *dp_wq;
1701
69769f9a
VS		 1702 uint32_t bios_vgacntr;
1703
231f42a4
DV		 1704 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1705 * here! */
1706 struct i915_dri1_state dri1;
db1b76ca
DV		 1707 /* Old ums support infrastructure, same warning applies. */
1708 struct i915_ums_state ums;
bdf1e7e3 1709
a83014d3
OM		 1710 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1711 struct {
1712 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1713 struct intel_engine_cs *ring,
1714 struct intel_context *ctx,
1715 struct drm_i915_gem_execbuffer2 *args,
1716 struct list_head *vmas,
1717 struct drm_i915_gem_object *batch_obj,
1718 u64 exec_start, u32 flags);
1719 int (*init_rings)(struct drm_device *dev);
1720 void (*cleanup_ring)(struct intel_engine_cs *ring);
1721 void (*stop_ring)(struct intel_engine_cs *ring);
1722 } gt;
1723
bdf1e7e3
DV		 1724 /*
1725 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1726 * will be rejected. Instead look for a better place.
1727 */
77fec556 1728};
1da177e4 1729
2c1792a1
CW		 1730static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1731{
1732 return dev->dev_private;
1733}
1734
b4519513
CW		 1735/* Iterate over initialised rings */
1736#define for_each_ring(ring__, dev_priv__, i__) \
1737 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1738 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1739
b1d7e4b4
WF		 1740enum hdmi_force_audio {
1741 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1742 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1743 HDMI_AUDIO_AUTO, /* trust EDID */
1744 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1745};
1746
190d6cd5 1747#define I915_GTT_OFFSET_NONE ((u32)-1)
ed2f3452 1748
37e680a1
CW		 1749struct drm_i915_gem_object_ops {
1750 /* Interface between the GEM object and its backing storage.
1751 * get_pages() is called once prior to the use of the associated set
1752 * of pages before to binding them into the GTT, and put_pages() is
1753 * called after we no longer need them. As we expect there to be
1754 * associated cost with migrating pages between the backing storage
1755 * and making them available for the GPU (e.g. clflush), we may hold
1756 * onto the pages after they are no longer referenced by the GPU
1757 * in case they may be used again shortly (for example migrating the
1758 * pages to a different memory domain within the GTT). put_pages()
1759 * will therefore most likely be called when the object itself is
1760 * being released or under memory pressure (where we attempt to
1761 * reap pages for the shrinker).
1762 */
1763 int (*get_pages)(struct drm_i915_gem_object *);
1764 void (*put_pages)(struct drm_i915_gem_object *);
5cc9ed4b
CW		 1765 int (*dmabuf_export)(struct drm_i915_gem_object *);
1766 void (*release)(struct drm_i915_gem_object *);
37e680a1
CW		 1767};
1768
a071fa00
DV		 1769/*
1770 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1771 * considered to be the frontbuffer for the given plane interface-vise. This
1772 * doesn't mean that the hw necessarily already scans it out, but that any
1773 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1774 *
1775 * We have one bit per pipe and per scanout plane type.
1776 */
1777#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1778#define INTEL_FRONTBUFFER_BITS \
1779 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1780#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1781 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1782#define INTEL_FRONTBUFFER_CURSOR(pipe) \
1783 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1784#define INTEL_FRONTBUFFER_SPRITE(pipe) \
1785 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1786#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1787 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
cc36513c
DV		 1788#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1789 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
a071fa00 1790
673a394b 1791struct drm_i915_gem_object {
c397b908 1792 struct drm_gem_object base;
673a394b 1793
37e680a1
CW		 1794 const struct drm_i915_gem_object_ops *ops;
1795
2f633156
BW		 1796 /** List of VMAs backed by this object */
1797 struct list_head vma_list;
1798
c1ad11fc
CW		 1799 /** Stolen memory for this object, instead of being backed by shmem. */
1800 struct drm_mm_node *stolen;
35c20a60 1801 struct list_head global_list;
673a394b 1802
69dc4987 1803 struct list_head ring_list;
b25cb2f8
BW		 1804 /** Used in execbuf to temporarily hold a ref */
1805 struct list_head obj_exec_link;
673a394b
EA		 1806
1807 /**
65ce3027
CW		 1808 * This is set if the object is on the active lists (has pending
1809 * rendering and so a non-zero seqno), and is not set if it i s on
1810 * inactive (ready to be unbound) list.
673a394b 1811 */
0206e353 1812 unsigned int active:1;
673a394b
EA		 1813
1814 /**
1815 * This is set if the object has been written to since last bound
1816 * to the GTT
1817 */
0206e353 1818 unsigned int dirty:1;
778c3544
DV		 1819
1820 /**
1821 * Fence register bits (if any) for this object. Will be set
1822 * as needed when mapped into the GTT.
1823 * Protected by dev->struct_mutex.
778c3544 1824 */
4b9de737 1825 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
778c3544 1826
778c3544
DV		 1827 /**
1828 * Advice: are the backing pages purgeable?
1829 */
0206e353 1830 unsigned int madv:2;
778c3544 1831
778c3544
DV		 1832 /**
1833 * Current tiling mode for the object.
1834 */
0206e353 1835 unsigned int tiling_mode:2;
5d82e3e6
CW		 1836 /**
1837 * Whether the tiling parameters for the currently associated fence
1838 * register have changed. Note that for the purposes of tracking
1839 * tiling changes we also treat the unfenced register, the register
1840 * slot that the object occupies whilst it executes a fenced
1841 * command (such as BLT on gen2/3), as a "fence".
1842 */
1843 unsigned int fence_dirty:1;
778c3544 1844
75e9e915
DV		 1845 /**
1846 * Is the object at the current location in the gtt mappable and
1847 * fenceable? Used to avoid costly recalculations.
1848 */
0206e353 1849 unsigned int map_and_fenceable:1;
75e9e915 1850
fb7d516a
DV		 1851 /**
1852 * Whether the current gtt mapping needs to be mappable (and isn't just
1853 * mappable by accident). Track pin and fault separate for a more
1854 * accurate mappable working set.
1855 */
0206e353
AJ		 1856 unsigned int fault_mappable:1;
1857 unsigned int pin_mappable:1;
cc98b413 1858 unsigned int pin_display:1;
fb7d516a 1859
24f3a8cf
AG		 1860 /*
1861 * Is the object to be mapped as read-only to the GPU
1862 * Only honoured if hardware has relevant pte bit
1863 */
1864 unsigned long gt_ro:1;
651d794f 1865 unsigned int cache_level:3;
93dfb40c 1866
9da3da66 1867 unsigned int has_dma_mapping:1;
7bddb01f 1868
a071fa00
DV		 1869 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1870
9da3da66 1871 struct sg_table *pages;
a5570178 1872 int pages_pin_count;
673a394b 1873
1286ff73 1874 /* prime dma-buf support */
9a70cc2a
DA		 1875 void *dma_buf_vmapping;
1876 int vmapping_count;
1877
a4872ba6 1878 struct intel_engine_cs *ring;
caea7476 1879
1c293ea3 1880 /** Breadcrumb of last rendering to the buffer. */
0201f1ec
CW		 1881 uint32_t last_read_seqno;
1882 uint32_t last_write_seqno;
caea7476
CW		 1883 /** Breadcrumb of last fenced GPU access to the buffer. */
1884 uint32_t last_fenced_seqno;
673a394b 1885
778c3544 1886 /** Current tiling stride for the object, if it's tiled. */
de151cf6 1887 uint32_t stride;
673a394b 1888
80075d49
DV		 1889 /** References from framebuffers, locks out tiling changes. */
1890 unsigned long framebuffer_references;
1891
280b713b 1892 /** Record of address bit 17 of each page at last unbind. */
d312ec25 1893 unsigned long *bit_17;
280b713b 1894
79e53945 1895 /** User space pin count and filp owning the pin */
aa5f8021 1896 unsigned long user_pin_count;
79e53945 1897 struct drm_file *pin_filp;
71acb5eb
DA		 1898
1899 /** for phy allocated objects */
ba8286fa 1900 struct drm_dma_handle *phys_handle;
673a394b 1901
5cc9ed4b
CW		 1902 union {
1903 struct i915_gem_userptr {
1904 uintptr_t ptr;
1905 unsigned read_only :1;
1906 unsigned workers :4;
1907#define I915_GEM_USERPTR_MAX_WORKERS 15
1908
ad46cb53
CW		 1909 struct i915_mm_struct *mm;
1910 struct i915_mmu_object *mmu_object;
5cc9ed4b
CW		 1911 struct work_struct *work;
1912 } userptr;
1913 };
1914};
62b8b215 1915#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
23010e43 1916
a071fa00
DV		 1917void i915_gem_track_fb(struct drm_i915_gem_object *old,
1918 struct drm_i915_gem_object *new,
1919 unsigned frontbuffer_bits);
1920
673a394b
EA		 1921/**
1922 * Request queue structure.
1923 *
1924 * The request queue allows us to note sequence numbers that have been emitted
1925 * and may be associated with active buffers to be retired.
1926 *
1927 * By keeping this list, we can avoid having to do questionable
1928 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1929 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1930 */
1931struct drm_i915_gem_request {
852835f3 1932 /** On Which ring this request was generated */
a4872ba6 1933 struct intel_engine_cs *ring;
852835f3 1934
673a394b
EA		 1935 /** GEM sequence number associated with this request. */
1936 uint32_t seqno;
1937
7d736f4f
MK		 1938 /** Position in the ringbuffer of the start of the request */
1939 u32 head;
1940
1941 /** Position in the ringbuffer of the end of the request */
a71d8d94
CW		 1942 u32 tail;
1943
0e50e96b 1944 /** Context related to this request */
273497e5 1945 struct intel_context *ctx;
0e50e96b 1946
7d736f4f
MK		 1947 /** Batch buffer related to this request if any */
1948 struct drm_i915_gem_object *batch_obj;
1949
673a394b
EA		 1950 /** Time at which this request was emitted, in jiffies. */
1951 unsigned long emitted_jiffies;
1952
b962442e 1953 /** global list entry for this request */
673a394b 1954 struct list_head list;
b962442e 1955
f787a5f5 1956 struct drm_i915_file_private *file_priv;
b962442e
EA		 1957 /** file_priv list entry for this request */
1958 struct list_head client_list;
673a394b
EA		 1959};
1960
1961struct drm_i915_file_private {
b29c19b6 1962 struct drm_i915_private *dev_priv;
ab0e7ff9 1963 struct drm_file *file;
b29c19b6 1964
673a394b 1965 struct {
99057c81 1966 spinlock_t lock;
b962442e 1967 struct list_head request_list;
b29c19b6 1968 struct delayed_work idle_work;
673a394b 1969 } mm;
40521054 1970 struct idr context_idr;
e59ec13d 1971
b29c19b6 1972 atomic_t rps_wait_boost;
a4872ba6 1973 struct intel_engine_cs *bsd_ring;
673a394b
EA		 1974};
1975
351e3db2
BV		 1976/*
1977 * A command that requires special handling by the command parser.
1978 */
1979struct drm_i915_cmd_descriptor {
1980 /*
1981 * Flags describing how the command parser processes the command.
1982 *
1983 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1984 * a length mask if not set
1985 * CMD_DESC_SKIP: The command is allowed but does not follow the
1986 * standard length encoding for the opcode range in
1987 * which it falls
1988 * CMD_DESC_REJECT: The command is never allowed
1989 * CMD_DESC_REGISTER: The command should be checked against the
1990 * register whitelist for the appropriate ring
1991 * CMD_DESC_MASTER: The command is allowed if the submitting process
1992 * is the DRM master
1993 */
1994 u32 flags;
1995#define CMD_DESC_FIXED (1<<0)
1996#define CMD_DESC_SKIP (1<<1)
1997#define CMD_DESC_REJECT (1<<2)
1998#define CMD_DESC_REGISTER (1<<3)
1999#define CMD_DESC_BITMASK (1<<4)
2000#define CMD_DESC_MASTER (1<<5)
2001
2002 /*
2003 * The command's unique identification bits and the bitmask to get them.
2004 * This isn't strictly the opcode field as defined in the spec and may
2005 * also include type, subtype, and/or subop fields.
2006 */
2007 struct {
2008 u32 value;
2009 u32 mask;
2010 } cmd;
2011
2012 /*
2013 * The command's length. The command is either fixed length (i.e. does
2014 * not include a length field) or has a length field mask. The flag
2015 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2016 * a length mask. All command entries in a command table must include
2017 * length information.
2018 */
2019 union {
2020 u32 fixed;
2021 u32 mask;
2022 } length;
2023
2024 /*
2025 * Describes where to find a register address in the command to check
2026 * against the ring's register whitelist. Only valid if flags has the
2027 * CMD_DESC_REGISTER bit set.
2028 */
2029 struct {
2030 u32 offset;
2031 u32 mask;
2032 } reg;
2033
2034#define MAX_CMD_DESC_BITMASKS 3
2035 /*
2036 * Describes command checks where a particular dword is masked and
2037 * compared against an expected value. If the command does not match
2038 * the expected value, the parser rejects it. Only valid if flags has
2039 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2040 * are valid.
d4d48035
BV		 2041 *
2042 * If the check specifies a non-zero condition_mask then the parser
2043 * only performs the check when the bits specified by condition_mask
2044 * are non-zero.
351e3db2
BV		 2045 */
2046 struct {
2047 u32 offset;
2048 u32 mask;
2049 u32 expected;
d4d48035
BV		 2050 u32 condition_offset;
2051 u32 condition_mask;
351e3db2
BV		 2052 } bits[MAX_CMD_DESC_BITMASKS];
2053};
2054
2055/*
2056 * A table of commands requiring special handling by the command parser.
2057 *
2058 * Each ring has an array of tables. Each table consists of an array of command
2059 * descriptors, which must be sorted with command opcodes in ascending order.
2060 */
2061struct drm_i915_cmd_table {
2062 const struct drm_i915_cmd_descriptor *table;
2063 int count;
2064};
2065
dbbe9127 2066/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
7312e2dd
CW		 2067#define __I915__(p) ({ \
2068 struct drm_i915_private *__p; \
2069 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2070 __p = (struct drm_i915_private *)p; \
2071 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2072 __p = to_i915((struct drm_device *)p); \
2073 else \
2074 BUILD_BUG(); \
2075 __p; \
2076})
dbbe9127 2077#define INTEL_INFO(p) (&__I915__(p)->info)
87f1f465 2078#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
cae5852d 2079
87f1f465
CW		 2080#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2081#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
cae5852d 2082#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
87f1f465 2083#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
cae5852d 2084#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
87f1f465
CW		 2085#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2086#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
cae5852d
ZN		 2087#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2088#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2089#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
87f1f465 2090#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
cae5852d 2091#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
87f1f465
CW		 2092#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2093#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
cae5852d
ZN		 2094#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2095#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
87f1f465 2096#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
4b65177b 2097#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
87f1f465
CW		 2098#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2099 INTEL_DEVID(dev) == 0x0152 || \
2100 INTEL_DEVID(dev) == 0x015a)
2101#define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2102 INTEL_DEVID(dev) == 0x0106 || \
2103 INTEL_DEVID(dev) == 0x010A)
70a3eb7a 2104#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
6df4027b 2105#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
4cae9ae0 2106#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
8179f1f0 2107#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
7201c0b3 2108#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
cae5852d 2109#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
ed1c9e2c 2110#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
87f1f465 2111 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
5dd8c4c3 2112#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
87f1f465
CW		 2113 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2114 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2115 (INTEL_DEVID(dev) & 0xf) == 0xe))
a0fcbd95
RV		 2116#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2117 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
5dd8c4c3 2118#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
87f1f465 2119 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
9435373e 2120#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
87f1f465 2121 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
9bbfd20a 2122/* ULX machines are also considered ULT. */
87f1f465
CW		 2123#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2124 INTEL_DEVID(dev) == 0x0A1E)
b833d685 2125#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
cae5852d 2126
85436696
JB		 2127/*
2128 * The genX designation typically refers to the render engine, so render
2129 * capability related checks should use IS_GEN, while display and other checks
2130 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2131 * chips, etc.).
2132 */
cae5852d
ZN		 2133#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2134#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2135#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2136#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2137#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
85436696 2138#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
d2980845 2139#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
b71252dc 2140#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
cae5852d 2141
73ae478c
BW		 2142#define RENDER_RING (1<<RCS)
2143#define BSD_RING (1<<VCS)
2144#define BLT_RING (1<<BCS)
2145#define VEBOX_RING (1<<VECS)
845f74a7 2146#define BSD2_RING (1<<VCS2)
63c42e56 2147#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
845f74a7 2148#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
63c42e56
BW		 2149#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2150#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2151#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2152#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
f2fbc690 2153 __I915__(dev)->ellc_size)
cae5852d
ZN		 2154#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2155
254f965c 2156#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
d7f621e5 2157#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
692ef70c
JB		 2158#define USES_PPGTT(dev) (i915.enable_ppgtt)
2159#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
1d2a314c 2160
05394f39 2161#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
cae5852d
ZN		 2162#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2163
b45305fc
DV		 2164/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2165#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
4e6b788c
DV		 2166/*
2167 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2168 * even when in MSI mode. This results in spurious interrupt warnings if the
2169 * legacy irq no. is shared with another device. The kernel then disables that
2170 * interrupt source and so prevents the other device from working properly.
2171 */
2172#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2173#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
b45305fc 2174
cae5852d
ZN		 2175/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2176 * rows, which changed the alignment requirements and fence programming.
2177 */
2178#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2179 IS_I915GM(dev)))
2180#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2181#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2182#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
cae5852d
ZN		 2183#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2184#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
cae5852d
ZN		 2185
2186#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2187#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
3a77c4c4 2188#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
cae5852d 2189
dbf7786e 2190#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
f5adf94e 2191
dd93be58 2192#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
30568c45 2193#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
ed8546ac 2194#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
6157d3c8 2195#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
fd7f8cce 2196 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
58abf1da
RV		 2197#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2198#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
affa9354 2199
17a303ec
PZ		 2200#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2201#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2202#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2203#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2204#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2205#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
e7e7ea20
S		 2206#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2207#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
17a303ec 2208
f2fbc690 2209#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
e7e7ea20 2210#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
eb877ebf 2211#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
cae5852d
ZN		 2212#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2213#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
40c7ead9 2214#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
45e6e3a1 2215#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
cae5852d 2216
5fafe292
SJ		 2217#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2218
040d2baa
BW		 2219/* DPF == dynamic parity feature */
2220#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2221#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
e1ef7cc2 2222
c8735b0c
BW		 2223#define GT_FREQUENCY_MULTIPLIER 50
2224
05394f39
CW		 2225#include "i915_trace.h"
2226
baa70943 2227extern const struct drm_ioctl_desc i915_ioctls[];
b3a83639
DA		 2228extern int i915_max_ioctl;
2229
fc49b3da
ID		 2230extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2231extern int i915_resume_legacy(struct drm_device *dev);
7c1c2871
DA		 2232extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2233extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2234
d330a953
JN		 2235/* i915_params.c */
2236struct i915_params {
2237 int modeset;
2238 int panel_ignore_lid;
2239 unsigned int powersave;
2240 int semaphores;
2241 unsigned int lvds_downclock;
2242 int lvds_channel_mode;
2243 int panel_use_ssc;
2244 int vbt_sdvo_panel_type;
2245 int enable_rc6;
2246 int enable_fbc;
d330a953 2247 int enable_ppgtt;
127f1003 2248 int enable_execlists;
d330a953
JN		 2249 int enable_psr;
2250 unsigned int preliminary_hw_support;
2251 int disable_power_well;
2252 int enable_ips;
e5aa6541 2253 int invert_brightness;
351e3db2 2254 int enable_cmd_parser;
e5aa6541
DL		 2255 /* leave bools at the end to not create holes */
2256 bool enable_hangcheck;
2257 bool fastboot;
d330a953
JN		 2258 bool prefault_disable;
2259 bool reset;
a0bae57f 2260 bool disable_display;
7a10dfa6 2261 bool disable_vtd_wa;
84c33a64 2262 int use_mmio_flip;
5978118c 2263 bool mmio_debug;
d330a953
JN		 2264};
2265extern struct i915_params i915 __read_mostly;
2266
1da177e4 2267 /* i915_dma.c */
d05c617e 2268void i915_update_dri1_breadcrumb(struct drm_device *dev);
84b1fd10 2269extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 2270extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 2271extern int i915_driver_unload(struct drm_device *);
2885f6ac 2272extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
84b1fd10 2273extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac 2274extern void i915_driver_preclose(struct drm_device *dev,
2885f6ac 2275 struct drm_file *file);
673a394b 2276extern void i915_driver_postclose(struct drm_device *dev,
2885f6ac 2277 struct drm_file *file);
84b1fd10 2278extern int i915_driver_device_is_agp(struct drm_device * dev);
c43b5634 2279#ifdef CONFIG_COMPAT
0d6aa60b
DA		 2280extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2281 unsigned long arg);
c43b5634 2282#endif
673a394b 2283extern int i915_emit_box(struct drm_device *dev,
c4e7a414
CW		 2284 struct drm_clip_rect *box,
2285 int DR1, int DR4);
8e96d9c4 2286extern int intel_gpu_reset(struct drm_device *dev);
d4b8bb2a 2287extern int i915_reset(struct drm_device *dev);
7648fa99
JB		 2288extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2289extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2290extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2291extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
650ad970 2292int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1d0d343a 2293void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
7648fa99 2294
1da177e4 2295/* i915_irq.c */
10cd45b6 2296void i915_queue_hangcheck(struct drm_device *dev);
58174462
MK		 2297__printf(3, 4)
2298void i915_handle_error(struct drm_device *dev, bool wedged,
2299 const char *fmt, ...);
1da177e4 2300
b963291c
DV		 2301extern void intel_irq_init(struct drm_i915_private *dev_priv);
2302extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2aeb7d3a
DV		 2303int intel_irq_install(struct drm_i915_private *dev_priv);
2304void intel_irq_uninstall(struct drm_i915_private *dev_priv);
907b28c5
CW		 2305
2306extern void intel_uncore_sanitize(struct drm_device *dev);
10018603
ID		 2307extern void intel_uncore_early_sanitize(struct drm_device *dev,
2308 bool restore_forcewake);
907b28c5 2309extern void intel_uncore_init(struct drm_device *dev);
907b28c5 2310extern void intel_uncore_check_errors(struct drm_device *dev);
aec347ab 2311extern void intel_uncore_fini(struct drm_device *dev);
156c7ca0 2312extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
b1f14ad0 2313
7c463586 2314void
50227e1c 2315i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2316 u32 status_mask);
7c463586
KP		 2317
2318void
50227e1c 2319i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2320 u32 status_mask);
7c463586 2321
f8b79e58
ID		 2322void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2323void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
47339cd9
DV		 2324void
2325ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2326void
2327ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2328void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2329 uint32_t interrupt_mask,
2330 uint32_t enabled_irq_mask);
2331#define ibx_enable_display_interrupt(dev_priv, bits) \
2332 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2333#define ibx_disable_display_interrupt(dev_priv, bits) \
2334 ibx_display_interrupt_update((dev_priv), (bits), 0)
f8b79e58 2335
673a394b
EA		 2336/* i915_gem.c */
2337int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2338 struct drm_file *file_priv);
2339int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2340 struct drm_file *file_priv);
2341int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2342 struct drm_file *file_priv);
2343int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2344 struct drm_file *file_priv);
2345int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2346 struct drm_file *file_priv);
de151cf6
JB		 2347int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2348 struct drm_file *file_priv);
673a394b
EA		 2349int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2350 struct drm_file *file_priv);
2351int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2352 struct drm_file *file_priv);
ba8b7ccb
OM		 2353void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2354 struct intel_engine_cs *ring);
2355void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2356 struct drm_file *file,
2357 struct intel_engine_cs *ring,
2358 struct drm_i915_gem_object *obj);
a83014d3
OM		 2359int i915_gem_ringbuffer_submission(struct drm_device *dev,
2360 struct drm_file *file,
2361 struct intel_engine_cs *ring,
2362 struct intel_context *ctx,
2363 struct drm_i915_gem_execbuffer2 *args,
2364 struct list_head *vmas,
2365 struct drm_i915_gem_object *batch_obj,
2366 u64 exec_start, u32 flags);
673a394b
EA		 2367int i915_gem_execbuffer(struct drm_device *dev, void *data,
2368 struct drm_file *file_priv);
76446cac
JB		 2369int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2370 struct drm_file *file_priv);
673a394b
EA		 2371int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2372 struct drm_file *file_priv);
2373int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2374 struct drm_file *file_priv);
2375int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2376 struct drm_file *file_priv);
199adf40
BW		 2377int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2378 struct drm_file *file);
2379int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2380 struct drm_file *file);
673a394b
EA		 2381int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2382 struct drm_file *file_priv);
3ef94daa
CW		 2383int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2384 struct drm_file *file_priv);
673a394b
EA		 2385int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2386 struct drm_file *file_priv);
2387int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2388 struct drm_file *file_priv);
2389int i915_gem_set_tiling(struct drm_device *dev, void *data,
2390 struct drm_file *file_priv);
2391int i915_gem_get_tiling(struct drm_device *dev, void *data,
2392 struct drm_file *file_priv);
5cc9ed4b
CW		 2393int i915_gem_init_userptr(struct drm_device *dev);
2394int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2395 struct drm_file *file);
5a125c3c
EA		 2396int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2397 struct drm_file *file_priv);
23ba4fd0
BW		 2398int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2399 struct drm_file *file_priv);
673a394b 2400void i915_gem_load(struct drm_device *dev);
21ab4e74
CW		 2401unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2402 long target,
2403 unsigned flags);
2404#define I915_SHRINK_PURGEABLE 0x1
2405#define I915_SHRINK_UNBOUND 0x2
2406#define I915_SHRINK_BOUND 0x4
42dcedd4
CW		 2407void *i915_gem_object_alloc(struct drm_device *dev);
2408void i915_gem_object_free(struct drm_i915_gem_object *obj);
37e680a1
CW		 2409void i915_gem_object_init(struct drm_i915_gem_object *obj,
2410 const struct drm_i915_gem_object_ops *ops);
05394f39
CW		 2411struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2412 size_t size);
7e0d96bc
BW		 2413void i915_init_vm(struct drm_i915_private *dev_priv,
2414 struct i915_address_space *vm);
673a394b 2415void i915_gem_free_object(struct drm_gem_object *obj);
2f633156 2416void i915_gem_vma_destroy(struct i915_vma *vma);
42dcedd4 2417
1ec9e26d
DV		 2418#define PIN_MAPPABLE 0x1
2419#define PIN_NONBLOCK 0x2
bf3d149b 2420#define PIN_GLOBAL 0x4
d23db88c
CW		 2421#define PIN_OFFSET_BIAS 0x8
2422#define PIN_OFFSET_MASK (~4095)
2021746e 2423int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
c37e2204 2424 struct i915_address_space *vm,
2021746e 2425 uint32_t alignment,
d23db88c 2426 uint64_t flags);
07fe0b12 2427int __must_check i915_vma_unbind(struct i915_vma *vma);
dd624afd 2428int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
48018a57 2429void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
05394f39 2430void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
673a394b 2431void i915_gem_lastclose(struct drm_device *dev);
f787a5f5 2432
4c914c0c
BV		 2433int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2434 int *needs_clflush);
2435
37e680a1 2436int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
9da3da66
CW		 2437static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2438{
67d5a50c
ID		 2439 struct sg_page_iter sg_iter;
2440
2441 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2db76d7c 2442 return sg_page_iter_page(&sg_iter);
67d5a50c
ID		 2443
2444 return NULL;
9da3da66 2445}
a5570178
CW		 2446static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2447{
2448 BUG_ON(obj->pages == NULL);
2449 obj->pages_pin_count++;
2450}
2451static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2452{
2453 BUG_ON(obj->pages_pin_count == 0);
2454 obj->pages_pin_count--;
2455}
2456
54cf91dc 2457int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2911a35b 2458int i915_gem_object_sync(struct drm_i915_gem_object *obj,
a4872ba6 2459 struct intel_engine_cs *to);
e2d05a8b 2460void i915_vma_move_to_active(struct i915_vma *vma,
a4872ba6 2461 struct intel_engine_cs *ring);
ff72145b
DA		 2462int i915_gem_dumb_create(struct drm_file *file_priv,
2463 struct drm_device *dev,
2464 struct drm_mode_create_dumb *args);
2465int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2466 uint32_t handle, uint64_t *offset);
f787a5f5
CW		 2467/**
2468 * Returns true if seq1 is later than seq2.
2469 */
2470static inline bool
2471i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2472{
2473 return (int32_t)(seq1 - seq2) >= 0;
2474}
2475
fca26bb4
MK		 2476int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2477int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
06d98131 2478int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
d9e86c0e 2479int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2021746e 2480
d8ffa60b
DV		 2481bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2482void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
1690e1eb 2483
8d9fc7fd 2484struct drm_i915_gem_request *
a4872ba6 2485i915_gem_find_active_request(struct intel_engine_cs *ring);
8d9fc7fd 2486
b29c19b6 2487bool i915_gem_retire_requests(struct drm_device *dev);
a4872ba6 2488void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
33196ded 2489int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
d6b2c790 2490 bool interruptible);
84c33a64
SG		 2491int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2492
1f83fee0
DV		 2493static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2494{
2495 return unlikely(atomic_read(&error->reset_counter)
2ac0f450 2496 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
1f83fee0
DV		 2497}
2498
2499static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2500{
2ac0f450
MK		 2501 return atomic_read(&error->reset_counter) & I915_WEDGED;
2502}
2503
2504static inline u32 i915_reset_count(struct i915_gpu_error *error)
2505{
2506 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
1f83fee0 2507}
a71d8d94 2508
88b4aa87
MK		 2509static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2510{
2511 return dev_priv->gpu_error.stop_rings == 0 ||
2512 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2513}
2514
2515static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2516{
2517 return dev_priv->gpu_error.stop_rings == 0 ||
2518 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2519}
2520
069efc1d 2521void i915_gem_reset(struct drm_device *dev);
000433b6 2522bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
a8198eea 2523int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1070a42b 2524int __must_check i915_gem_init(struct drm_device *dev);
a83014d3 2525int i915_gem_init_rings(struct drm_device *dev);
f691e2f4 2526int __must_check i915_gem_init_hw(struct drm_device *dev);
a4872ba6 2527int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
f691e2f4 2528void i915_gem_init_swizzling(struct drm_device *dev);
79e53945 2529void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
b2da9fe5 2530int __must_check i915_gpu_idle(struct drm_device *dev);
45c5f202 2531int __must_check i915_gem_suspend(struct drm_device *dev);
a4872ba6 2532int __i915_add_request(struct intel_engine_cs *ring,
0025c077 2533 struct drm_file *file,
7d736f4f 2534 struct drm_i915_gem_object *batch_obj,
0025c077
MK		 2535 u32 *seqno);
2536#define i915_add_request(ring, seqno) \
854c94a7 2537 __i915_add_request(ring, NULL, NULL, seqno)
a4872ba6 2538int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
199b2bc2 2539 uint32_t seqno);
de151cf6 2540int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2021746e
CW		 2541int __must_check
2542i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2543 bool write);
2544int __must_check
dabdfe02
CW		 2545i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2546int __must_check
2da3b9b9
CW		 2547i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2548 u32 alignment,
a4872ba6 2549 struct intel_engine_cs *pipelined);
cc98b413 2550void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
00731155 2551int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
6eeefaf3 2552 int align);
b29c19b6 2553int i915_gem_open(struct drm_device *dev, struct drm_file *file);
05394f39 2554void i915_gem_release(struct drm_device *dev, struct drm_file *file);
673a394b 2555
0fa87796
ID		 2556uint32_t
2557i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
467cffba 2558uint32_t
d865110c
ID		 2559i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2560 int tiling_mode, bool fenced);
467cffba 2561
e4ffd173
CW		 2562int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2563 enum i915_cache_level cache_level);
2564
1286ff73
DV		 2565struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2566 struct dma_buf *dma_buf);
2567
2568struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2569 struct drm_gem_object *gem_obj, int flags);
2570
19b2dbde
CW		 2571void i915_gem_restore_fences(struct drm_device *dev);
2572
a70a3148
BW		 2573unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2574 struct i915_address_space *vm);
2575bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2576bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2577 struct i915_address_space *vm);
2578unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2579 struct i915_address_space *vm);
2580struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2581 struct i915_address_space *vm);
accfef2e
BW		 2582struct i915_vma *
2583i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2584 struct i915_address_space *vm);
5c2abbea
BW		 2585
2586struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
d7f46fc4
BW		 2587static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2588 struct i915_vma *vma;
2589 list_for_each_entry(vma, &obj->vma_list, vma_link)
2590 if (vma->pin_count > 0)
2591 return true;
2592 return false;
2593}
5c2abbea 2594
a70a3148 2595/* Some GGTT VM helpers */
5dc383b0 2596#define i915_obj_to_ggtt(obj) \
a70a3148
BW		 2597 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2598static inline bool i915_is_ggtt(struct i915_address_space *vm)
2599{
2600 struct i915_address_space *ggtt =
2601 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2602 return vm == ggtt;
2603}
2604
841cd773
DV		 2605static inline struct i915_hw_ppgtt *
2606i915_vm_to_ppgtt(struct i915_address_space *vm)
2607{
2608 WARN_ON(i915_is_ggtt(vm));
2609
2610 return container_of(vm, struct i915_hw_ppgtt, base);
2611}
2612
2613
a70a3148
BW		 2614static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2615{
5dc383b0 2616 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
a70a3148
BW		 2617}
2618
2619static inline unsigned long
2620i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2621{
5dc383b0 2622 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
a70a3148
BW		 2623}
2624
2625static inline unsigned long
2626i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2627{
5dc383b0 2628 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
a70a3148 2629}
c37e2204
BW		 2630
2631static inline int __must_check
2632i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2633 uint32_t alignment,
1ec9e26d 2634 unsigned flags)
c37e2204 2635{
5dc383b0
DV		 2636 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2637 alignment, flags | PIN_GLOBAL);
c37e2204 2638}
a70a3148 2639
b287110e
DV		 2640static inline int
2641i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2642{
2643 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2644}
2645
2646void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2647
254f965c 2648/* i915_gem_context.c */
8245be31 2649int __must_check i915_gem_context_init(struct drm_device *dev);
254f965c 2650void i915_gem_context_fini(struct drm_device *dev);
acce9ffa 2651void i915_gem_context_reset(struct drm_device *dev);
e422b888 2652int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2fa48d8d 2653int i915_gem_context_enable(struct drm_i915_private *dev_priv);
254f965c 2654void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
a4872ba6 2655int i915_switch_context(struct intel_engine_cs *ring,
273497e5
OM		 2656 struct intel_context *to);
2657struct intel_context *
41bde553 2658i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
dce3271b 2659void i915_gem_context_free(struct kref *ctx_ref);
8c857917
OM		 2660struct drm_i915_gem_object *
2661i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
273497e5 2662static inline void i915_gem_context_reference(struct intel_context *ctx)
dce3271b 2663{
691e6415 2664 kref_get(&ctx->ref);
dce3271b
MK		 2665}
2666
273497e5 2667static inline void i915_gem_context_unreference(struct intel_context *ctx)
dce3271b 2668{
691e6415 2669 kref_put(&ctx->ref, i915_gem_context_free);
dce3271b
MK		 2670}
2671
273497e5 2672static inline bool i915_gem_context_is_default(const struct intel_context *c)
3fac8978 2673{
821d66dd 2674 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3fac8978
MK		 2675}
2676
84624813
BW		 2677int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2678 struct drm_file *file);
2679int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2680 struct drm_file *file);
1286ff73 2681
679845ed
BW		 2682/* i915_gem_evict.c */
2683int __must_check i915_gem_evict_something(struct drm_device *dev,
2684 struct i915_address_space *vm,
2685 int min_size,
2686 unsigned alignment,
2687 unsigned cache_level,
d23db88c
CW		 2688 unsigned long start,
2689 unsigned long end,
1ec9e26d 2690 unsigned flags);
679845ed
BW		 2691int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2692int i915_gem_evict_everything(struct drm_device *dev);
1d2a314c 2693
0260c420 2694/* belongs in i915_gem_gtt.h */
d09105c6 2695static inline void i915_gem_chipset_flush(struct drm_device *dev)
e76e9aeb
BW		 2696{
2697 if (INTEL_INFO(dev)->gen < 6)
2698 intel_gtt_chipset_flush();
2699}
246cbfb5 2700
9797fbfb
CW		 2701/* i915_gem_stolen.c */
2702int i915_gem_init_stolen(struct drm_device *dev);
5e59f717 2703int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
11be49eb 2704void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
9797fbfb 2705void i915_gem_cleanup_stolen(struct drm_device *dev);
0104fdbb
CW		 2706struct drm_i915_gem_object *
2707i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
866d12b4
CW		 2708struct drm_i915_gem_object *
2709i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2710 u32 stolen_offset,
2711 u32 gtt_offset,
2712 u32 size);
9797fbfb 2713
673a394b 2714/* i915_gem_tiling.c */
2c1792a1 2715static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
e9b73c67 2716{
50227e1c 2717 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
e9b73c67
CW		 2718
2719 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2720 obj->tiling_mode != I915_TILING_NONE;
2721}
2722
673a394b 2723void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
05394f39
CW		 2724void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2725void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
673a394b
EA		 2726
2727/* i915_gem_debug.c */
23bc5982
CW		 2728#if WATCH_LISTS
2729int i915_verify_lists(struct drm_device *dev);
673a394b 2730#else
23bc5982 2731#define i915_verify_lists(dev) 0
673a394b 2732#endif
1da177e4 2733
2017263e 2734/* i915_debugfs.c */
27c202ad
BG		 2735int i915_debugfs_init(struct drm_minor *minor);
2736void i915_debugfs_cleanup(struct drm_minor *minor);
f8c168fa 2737#ifdef CONFIG_DEBUG_FS
07144428
DL		 2738void intel_display_crc_init(struct drm_device *dev);
2739#else
f8c168fa 2740static inline void intel_display_crc_init(struct drm_device *dev) {}
07144428 2741#endif
84734a04
MK		 2742
2743/* i915_gpu_error.c */
edc3d884
MK		 2744__printf(2, 3)
2745void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
fc16b48b
MK		 2746int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2747 const struct i915_error_state_file_priv *error);
4dc955f7 2748int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
0a4cd7c8 2749 struct drm_i915_private *i915,
4dc955f7
MK		 2750 size_t count, loff_t pos);
2751static inline void i915_error_state_buf_release(
2752 struct drm_i915_error_state_buf *eb)
2753{
2754 kfree(eb->buf);
2755}
58174462
MK		 2756void i915_capture_error_state(struct drm_device *dev, bool wedge,
2757 const char *error_msg);
84734a04
MK		 2758void i915_error_state_get(struct drm_device *dev,
2759 struct i915_error_state_file_priv *error_priv);
2760void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2761void i915_destroy_error_state(struct drm_device *dev);
2762
2763void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
0a4cd7c8 2764const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2017263e 2765
351e3db2 2766/* i915_cmd_parser.c */
d728c8ef 2767int i915_cmd_parser_get_version(void);
a4872ba6
OM		 2768int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2769void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2770bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2771int i915_parse_cmds(struct intel_engine_cs *ring,
351e3db2
BV		 2772 struct drm_i915_gem_object *batch_obj,
2773 u32 batch_start_offset,
2774 bool is_master);
2775
317c35d1
JB		 2776/* i915_suspend.c */
2777extern int i915_save_state(struct drm_device *dev);
2778extern int i915_restore_state(struct drm_device *dev);
0a3e67a4 2779
d8157a36
DV		 2780/* i915_ums.c */
2781void i915_save_display_reg(struct drm_device *dev);
2782void i915_restore_display_reg(struct drm_device *dev);
317c35d1 2783
0136db58
BW		 2784/* i915_sysfs.c */
2785void i915_setup_sysfs(struct drm_device *dev_priv);
2786void i915_teardown_sysfs(struct drm_device *dev_priv);
2787
f899fc64
CW		 2788/* intel_i2c.c */
2789extern int intel_setup_gmbus(struct drm_device *dev);
2790extern void intel_teardown_gmbus(struct drm_device *dev);
8f375e10 2791static inline bool intel_gmbus_is_port_valid(unsigned port)
3bd7d909 2792{
2ed06c93 2793 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
3bd7d909
DK		 2794}
2795
2796extern struct i2c_adapter *intel_gmbus_get_adapter(
2797 struct drm_i915_private *dev_priv, unsigned port);
e957d772
CW		 2798extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2799extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
8f375e10 2800static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
b8232e90
CW		 2801{
2802 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2803}
f899fc64
CW		 2804extern void intel_i2c_reset(struct drm_device *dev);
2805
3b617967 2806/* intel_opregion.c */
44834a67 2807#ifdef CONFIG_ACPI
27d50c82 2808extern int intel_opregion_setup(struct drm_device *dev);
44834a67
CW		 2809extern void intel_opregion_init(struct drm_device *dev);
2810extern void intel_opregion_fini(struct drm_device *dev);
3b617967 2811extern void intel_opregion_asle_intr(struct drm_device *dev);
9c4b0a68
JN		 2812extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2813 bool enable);
ecbc5cf3
JN		 2814extern int intel_opregion_notify_adapter(struct drm_device *dev,
2815 pci_power_t state);
65e082c9 2816#else
27d50c82 2817static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
44834a67
CW		 2818static inline void intel_opregion_init(struct drm_device *dev) { return; }
2819static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3b617967 2820static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
9c4b0a68
JN		 2821static inline int
2822intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2823{
2824 return 0;
2825}
ecbc5cf3
JN		 2826static inline int
2827intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2828{
2829 return 0;
2830}
65e082c9 2831#endif
8ee1c3db 2832
723bfd70
JB		 2833/* intel_acpi.c */
2834#ifdef CONFIG_ACPI
2835extern void intel_register_dsm_handler(void);
2836extern void intel_unregister_dsm_handler(void);
2837#else
2838static inline void intel_register_dsm_handler(void) { return; }
2839static inline void intel_unregister_dsm_handler(void) { return; }
2840#endif /* CONFIG_ACPI */
2841
79e53945 2842/* modesetting */
f817586c 2843extern void intel_modeset_init_hw(struct drm_device *dev);
79e53945 2844extern void intel_modeset_init(struct drm_device *dev);
2c7111db 2845extern void intel_modeset_gem_init(struct drm_device *dev);
79e53945 2846extern void intel_modeset_cleanup(struct drm_device *dev);
4932e2c3 2847extern void intel_connector_unregister(struct intel_connector *);
28d52043 2848extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
45e2b5f6
DV		 2849extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2850 bool force_restore);
44cec740 2851extern void i915_redisable_vga(struct drm_device *dev);
04098753 2852extern void i915_redisable_vga_power_on(struct drm_device *dev);
ee5382ae 2853extern bool intel_fbc_enabled(struct drm_device *dev);
1d73c2a8 2854extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
43a9539f 2855extern void intel_disable_fbc(struct drm_device *dev);
7648fa99 2856extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
dde86e2d 2857extern void intel_init_pch_refclk(struct drm_device *dev);
3b8d8d91 2858extern void gen6_set_rps(struct drm_device *dev, u8 val);
0a073b84 2859extern void valleyview_set_rps(struct drm_device *dev, u8 val);
5209b1f4
ID		 2860extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2861 bool enable);
0206e353
AJ		 2862extern void intel_detect_pch(struct drm_device *dev);
2863extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
0136db58 2864extern int intel_enable_rc6(const struct drm_device *dev);
3bad0781 2865
2911a35b 2866extern bool i915_semaphore_is_enabled(struct drm_device *dev);
c0c7babc
BW		 2867int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2868 struct drm_file *file);
b6359918
MK		 2869int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2870 struct drm_file *file);
575155a9 2871
84c33a64
SG		 2872void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2873
6ef3d427
CW		 2874/* overlay */
2875extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
edc3d884
MK		 2876extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2877 struct intel_overlay_error_state *error);
c4a1d9e4
CW		 2878
2879extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
edc3d884 2880extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
c4a1d9e4
CW		 2881 struct drm_device *dev,
2882 struct intel_display_error_state *error);
6ef3d427 2883
b7287d80
BW		 2884/* On SNB platform, before reading ring registers forcewake bit
2885 * must be set to prevent GT core from power down and stale values being
2886 * returned.
2887 */
c8d9a590
D		 2888void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2889void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
e998c40f 2890void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
b7287d80 2891
42c0526c
BW		 2892int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2893int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
59de0813
JN		 2894
2895/* intel_sideband.c */
64936258
JN		 2896u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2897void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2898u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
e9f882a3
JN		 2899u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2900void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2901u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2902void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2903u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2904void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
f3419158
JB		 2905u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2906void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
e9f882a3
JN		 2907u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2908void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
5e69f97f
CML		 2909u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2910void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
59de0813
JN		 2911u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2912 enum intel_sbi_destination destination);
2913void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2914 enum intel_sbi_destination destination);
e9fe51c6
SK		 2915u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2916void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
0a073b84 2917
2ec3815f
VS		 2918int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2919int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
42c0526c 2920
c8d9a590
D		 2921#define FORCEWAKE_RENDER (1 << 0)
2922#define FORCEWAKE_MEDIA (1 << 1)
2923#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2924
2925
0b274481
BW		 2926#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2927#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2928
2929#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2930#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2931#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2932#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2933
2934#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2935#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2936#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2937#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2938
698b3135
CW		 2939/* Be very careful with read/write 64-bit values. On 32-bit machines, they
2940 * will be implemented using 2 32-bit writes in an arbitrary order with
2941 * an arbitrary delay between them. This can cause the hardware to
2942 * act upon the intermediate value, possibly leading to corruption and
2943 * machine death. You have been warned.
2944 */
0b274481
BW		 2945#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2946#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
cae5852d 2947
50877445
CW		 2948#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2949 u32 upper = I915_READ(upper_reg); \
2950 u32 lower = I915_READ(lower_reg); \
2951 u32 tmp = I915_READ(upper_reg); \
2952 if (upper != tmp) { \
2953 upper = tmp; \
2954 lower = I915_READ(lower_reg); \
2955 WARN_ON(I915_READ(upper_reg) != upper); \
2956 } \
2957 (u64)upper << 32 | lower; })
2958
cae5852d
ZN		 2959#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2960#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2961
55bc60db
VS		 2962/* "Broadcast RGB" property */
2963#define INTEL_BROADCAST_RGB_AUTO 0
2964#define INTEL_BROADCAST_RGB_FULL 1
2965#define INTEL_BROADCAST_RGB_LIMITED 2
ba4f01a3 2966
766aa1c4
VS		 2967static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2968{
92e23b99 2969 if (IS_VALLEYVIEW(dev))
766aa1c4 2970 return VLV_VGACNTRL;
92e23b99
SJ		 2971 else if (INTEL_INFO(dev)->gen >= 5)
2972 return CPU_VGACNTRL;
766aa1c4
VS		 2973 else
2974 return VGACNTRL;
2975}
2976
2bb4629a
VS		 2977static inline void __user *to_user_ptr(u64 address)
2978{
2979 return (void __user *)(uintptr_t)address;
2980}
2981
df97729f
ID		 2982static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2983{
2984 unsigned long j = msecs_to_jiffies(m);
2985
2986 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2987}
2988
2989static inline unsigned long
2990timespec_to_jiffies_timeout(const struct timespec *value)
2991{
2992 unsigned long j = timespec_to_jiffies(value);
2993
2994 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2995}
2996
dce56b3c
PZ		 2997/*
2998 * If you need to wait X milliseconds between events A and B, but event B
2999 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3000 * when event A happened, then just before event B you call this function and
3001 * pass the timestamp as the first argument, and X as the second argument.
3002 */
3003static inline void
3004wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3005{
ec5e0cfb 3006 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
dce56b3c
PZ		 3007
3008 /*
3009 * Don't re-read the value of "jiffies" every time since it may change
3010 * behind our back and break the math.
3011 */
3012 tmp_jiffies = jiffies;
3013 target_jiffies = timestamp_jiffies +
3014 msecs_to_jiffies_timeout(to_wait_ms);
3015
3016 if (time_after(target_jiffies, tmp_jiffies)) {
ec5e0cfb
ID		 3017 remaining_jiffies = target_jiffies - tmp_jiffies;
3018 while (remaining_jiffies)
3019 remaining_jiffies =
3020 schedule_timeout_uninterruptible(remaining_jiffies);
dce56b3c
PZ		 3021 }
3022}
3023
1da177e4 3024#endif
Linux kernel - Deliverables
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