Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
e23ceb83 | 36 | #include <drm/drmP.h> |
c838d719 | 37 | #include "i915_params.h" |
585fb111 | 38 | #include "i915_reg.h" |
79e53945 | 39 | #include "intel_bios.h" |
8187a2b7 | 40 | #include "intel_ringbuffer.h" |
b20385f1 | 41 | #include "intel_lrc.h" |
0260c420 | 42 | #include "i915_gem_gtt.h" |
564ddb2f | 43 | #include "i915_gem_render_state.h" |
0839ccb8 | 44 | #include <linux/io-mapping.h> |
f899fc64 | 45 | #include <linux/i2c.h> |
c167a6fc | 46 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 47 | #include <drm/intel-gtt.h> |
ba8286fa | 48 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
d9fc9413 | 49 | #include <drm/drm_gem.h> |
aaa6fd2a | 50 | #include <linux/backlight.h> |
5cc9ed4b | 51 | #include <linux/hashtable.h> |
2911a35b | 52 | #include <linux/intel-iommu.h> |
742cbee8 | 53 | #include <linux/kref.h> |
9ee32fea | 54 | #include <linux/pm_qos.h> |
33a732f4 | 55 | #include "intel_guc.h" |
ac7f11c6 | 56 | #include "intel_dpll_mgr.h" |
585fb111 | 57 | |
1da177e4 LT |
58 | /* General customization: |
59 | */ | |
60 | ||
1da177e4 LT |
61 | #define DRIVER_NAME "i915" |
62 | #define DRIVER_DESC "Intel Graphics" | |
5790ff74 | 63 | #define DRIVER_DATE "20160229" |
1da177e4 | 64 | |
c883ef1b | 65 | #undef WARN_ON |
5f77eeb0 DV |
66 | /* Many gcc seem to no see through this and fall over :( */ |
67 | #if 0 | |
68 | #define WARN_ON(x) ({ \ | |
69 | bool __i915_warn_cond = (x); \ | |
70 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
71 | BUILD_BUG_ON(__i915_warn_cond); \ | |
72 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
73 | #else | |
152b2262 | 74 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") |
5f77eeb0 DV |
75 | #endif |
76 | ||
cd9bfacb | 77 | #undef WARN_ON_ONCE |
152b2262 | 78 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") |
cd9bfacb | 79 | |
5f77eeb0 DV |
80 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
81 | (long) (x), __func__); | |
c883ef1b | 82 | |
e2c719b7 RC |
83 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
84 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
85 | * which may not necessarily be a user visible problem. This will either | |
86 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
87 | * enable distros and users to tailor their preferred amount of i915 abrt | |
88 | * spam. | |
89 | */ | |
90 | #define I915_STATE_WARN(condition, format...) ({ \ | |
91 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
92 | if (unlikely(__ret_warn_on)) \ |
93 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 94 | DRM_ERROR(format); \ |
e2c719b7 RC |
95 | unlikely(__ret_warn_on); \ |
96 | }) | |
97 | ||
152b2262 JL |
98 | #define I915_STATE_WARN_ON(x) \ |
99 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 100 | |
42a8ca4c JN |
101 | static inline const char *yesno(bool v) |
102 | { | |
103 | return v ? "yes" : "no"; | |
104 | } | |
105 | ||
87ad3212 JN |
106 | static inline const char *onoff(bool v) |
107 | { | |
108 | return v ? "on" : "off"; | |
109 | } | |
110 | ||
317c35d1 | 111 | enum pipe { |
752aa88a | 112 | INVALID_PIPE = -1, |
317c35d1 JB |
113 | PIPE_A = 0, |
114 | PIPE_B, | |
9db4a9c7 | 115 | PIPE_C, |
a57c774a AK |
116 | _PIPE_EDP, |
117 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 118 | }; |
9db4a9c7 | 119 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 120 | |
a5c961d1 PZ |
121 | enum transcoder { |
122 | TRANSCODER_A = 0, | |
123 | TRANSCODER_B, | |
124 | TRANSCODER_C, | |
a57c774a AK |
125 | TRANSCODER_EDP, |
126 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
127 | }; |
128 | #define transcoder_name(t) ((t) + 'A') | |
129 | ||
84139d1e | 130 | /* |
31409e97 MR |
131 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
132 | * number of planes per CRTC. Not all platforms really have this many planes, | |
133 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
134 | * between the topmost sprite plane and the cursor plane. | |
84139d1e | 135 | */ |
80824003 JB |
136 | enum plane { |
137 | PLANE_A = 0, | |
138 | PLANE_B, | |
9db4a9c7 | 139 | PLANE_C, |
31409e97 MR |
140 | PLANE_CURSOR, |
141 | I915_MAX_PLANES, | |
80824003 | 142 | }; |
9db4a9c7 | 143 | #define plane_name(p) ((p) + 'A') |
52440211 | 144 | |
d615a166 | 145 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 146 | |
2b139522 ED |
147 | enum port { |
148 | PORT_A = 0, | |
149 | PORT_B, | |
150 | PORT_C, | |
151 | PORT_D, | |
152 | PORT_E, | |
153 | I915_MAX_PORTS | |
154 | }; | |
155 | #define port_name(p) ((p) + 'A') | |
156 | ||
a09caddd | 157 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
158 | |
159 | enum dpio_channel { | |
160 | DPIO_CH0, | |
161 | DPIO_CH1 | |
162 | }; | |
163 | ||
164 | enum dpio_phy { | |
165 | DPIO_PHY0, | |
166 | DPIO_PHY1 | |
167 | }; | |
168 | ||
b97186f0 PZ |
169 | enum intel_display_power_domain { |
170 | POWER_DOMAIN_PIPE_A, | |
171 | POWER_DOMAIN_PIPE_B, | |
172 | POWER_DOMAIN_PIPE_C, | |
173 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
174 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
175 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
176 | POWER_DOMAIN_TRANSCODER_A, | |
177 | POWER_DOMAIN_TRANSCODER_B, | |
178 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 179 | POWER_DOMAIN_TRANSCODER_EDP, |
6331a704 PJ |
180 | POWER_DOMAIN_PORT_DDI_A_LANES, |
181 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
182 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
183 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
184 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
319be8ae ID |
185 | POWER_DOMAIN_PORT_DSI, |
186 | POWER_DOMAIN_PORT_CRT, | |
187 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 188 | POWER_DOMAIN_VGA, |
fbeeaa23 | 189 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 190 | POWER_DOMAIN_PLLS, |
1407121a S |
191 | POWER_DOMAIN_AUX_A, |
192 | POWER_DOMAIN_AUX_B, | |
193 | POWER_DOMAIN_AUX_C, | |
194 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 195 | POWER_DOMAIN_GMBUS, |
dfa57627 | 196 | POWER_DOMAIN_MODESET, |
baa70707 | 197 | POWER_DOMAIN_INIT, |
bddc7645 ID |
198 | |
199 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
200 | }; |
201 | ||
202 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
203 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
204 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
205 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
206 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
207 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 208 | |
1d843f9d EE |
209 | enum hpd_pin { |
210 | HPD_NONE = 0, | |
1d843f9d EE |
211 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
212 | HPD_CRT, | |
213 | HPD_SDVO_B, | |
214 | HPD_SDVO_C, | |
cc24fcdc | 215 | HPD_PORT_A, |
1d843f9d EE |
216 | HPD_PORT_B, |
217 | HPD_PORT_C, | |
218 | HPD_PORT_D, | |
26951caf | 219 | HPD_PORT_E, |
1d843f9d EE |
220 | HPD_NUM_PINS |
221 | }; | |
222 | ||
c91711f9 JN |
223 | #define for_each_hpd_pin(__pin) \ |
224 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
225 | ||
5fcece80 JN |
226 | struct i915_hotplug { |
227 | struct work_struct hotplug_work; | |
228 | ||
229 | struct { | |
230 | unsigned long last_jiffies; | |
231 | int count; | |
232 | enum { | |
233 | HPD_ENABLED = 0, | |
234 | HPD_DISABLED = 1, | |
235 | HPD_MARK_DISABLED = 2 | |
236 | } state; | |
237 | } stats[HPD_NUM_PINS]; | |
238 | u32 event_bits; | |
239 | struct delayed_work reenable_work; | |
240 | ||
241 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
242 | u32 long_port_mask; | |
243 | u32 short_port_mask; | |
244 | struct work_struct dig_port_work; | |
245 | ||
246 | /* | |
247 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
248 | * the non-DP HPD could block the workqueue on a mode config | |
249 | * mutex getting, that userspace may have taken. However | |
250 | * userspace is waiting on the DP workqueue to run which is | |
251 | * blocked behind the non-DP one. | |
252 | */ | |
253 | struct workqueue_struct *dp_wq; | |
254 | }; | |
255 | ||
2a2d5482 CW |
256 | #define I915_GEM_GPU_DOMAINS \ |
257 | (I915_GEM_DOMAIN_RENDER | \ | |
258 | I915_GEM_DOMAIN_SAMPLER | \ | |
259 | I915_GEM_DOMAIN_COMMAND | \ | |
260 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
261 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 262 | |
055e393f DL |
263 | #define for_each_pipe(__dev_priv, __p) \ |
264 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
6831f3e3 VS |
265 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ |
266 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
267 | for_each_if ((__mask) & (1 << (__p))) | |
dd740780 DL |
268 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
269 | for ((__p) = 0; \ | |
270 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
271 | (__p)++) | |
3bdcfc0c DL |
272 | #define for_each_sprite(__dev_priv, __p, __s) \ |
273 | for ((__s) = 0; \ | |
274 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
275 | (__s)++) | |
9db4a9c7 | 276 | |
d79b814d DL |
277 | #define for_each_crtc(dev, crtc) \ |
278 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
279 | ||
27321ae8 ML |
280 | #define for_each_intel_plane(dev, intel_plane) \ |
281 | list_for_each_entry(intel_plane, \ | |
282 | &dev->mode_config.plane_list, \ | |
283 | base.head) | |
284 | ||
262cd2e1 VS |
285 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
286 | list_for_each_entry(intel_plane, \ | |
287 | &(dev)->mode_config.plane_list, \ | |
288 | base.head) \ | |
95150bdf | 289 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 290 | |
d063ae48 DL |
291 | #define for_each_intel_crtc(dev, intel_crtc) \ |
292 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
293 | ||
b2784e15 DL |
294 | #define for_each_intel_encoder(dev, intel_encoder) \ |
295 | list_for_each_entry(intel_encoder, \ | |
296 | &(dev)->mode_config.encoder_list, \ | |
297 | base.head) | |
298 | ||
3a3371ff ACO |
299 | #define for_each_intel_connector(dev, intel_connector) \ |
300 | list_for_each_entry(intel_connector, \ | |
301 | &dev->mode_config.connector_list, \ | |
302 | base.head) | |
303 | ||
6c2b7c12 DV |
304 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
305 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 306 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 307 | |
53f5e3ca JB |
308 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
309 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 310 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 311 | |
b04c5bd6 BF |
312 | #define for_each_power_domain(domain, mask) \ |
313 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
95150bdf | 314 | for_each_if ((1 << (domain)) & (mask)) |
b04c5bd6 | 315 | |
e7b903d2 | 316 | struct drm_i915_private; |
ad46cb53 | 317 | struct i915_mm_struct; |
5cc9ed4b | 318 | struct i915_mmu_object; |
e7b903d2 | 319 | |
a6f766f3 CW |
320 | struct drm_i915_file_private { |
321 | struct drm_i915_private *dev_priv; | |
322 | struct drm_file *file; | |
323 | ||
324 | struct { | |
325 | spinlock_t lock; | |
326 | struct list_head request_list; | |
d0bc54f2 CW |
327 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
328 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
329 | * (when using lax throttling for the frontbuffer). We also use it to | |
330 | * offer free GPU waitboosts for severely congested workloads. | |
331 | */ | |
332 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
333 | } mm; |
334 | struct idr context_idr; | |
335 | ||
2e1b8730 CW |
336 | struct intel_rps_client { |
337 | struct list_head link; | |
338 | unsigned boosts; | |
339 | } rps; | |
a6f766f3 | 340 | |
de1add36 | 341 | unsigned int bsd_ring; |
a6f766f3 CW |
342 | }; |
343 | ||
e69d0bc1 DV |
344 | /* Used by dp and fdi links */ |
345 | struct intel_link_m_n { | |
346 | uint32_t tu; | |
347 | uint32_t gmch_m; | |
348 | uint32_t gmch_n; | |
349 | uint32_t link_m; | |
350 | uint32_t link_n; | |
351 | }; | |
352 | ||
353 | void intel_link_compute_m_n(int bpp, int nlanes, | |
354 | int pixel_clock, int link_clock, | |
355 | struct intel_link_m_n *m_n); | |
356 | ||
1da177e4 LT |
357 | /* Interface history: |
358 | * | |
359 | * 1.1: Original. | |
0d6aa60b DA |
360 | * 1.2: Add Power Management |
361 | * 1.3: Add vblank support | |
de227f5f | 362 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 363 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
364 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
365 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
366 | */ |
367 | #define DRIVER_MAJOR 1 | |
2228ed67 | 368 | #define DRIVER_MINOR 6 |
1da177e4 LT |
369 | #define DRIVER_PATCHLEVEL 0 |
370 | ||
23bc5982 | 371 | #define WATCH_LISTS 0 |
673a394b | 372 | |
0a3e67a4 JB |
373 | struct opregion_header; |
374 | struct opregion_acpi; | |
375 | struct opregion_swsci; | |
376 | struct opregion_asle; | |
377 | ||
8ee1c3db | 378 | struct intel_opregion { |
115719fc WD |
379 | struct opregion_header *header; |
380 | struct opregion_acpi *acpi; | |
381 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
382 | u32 swsci_gbda_sub_functions; |
383 | u32 swsci_sbcb_sub_functions; | |
115719fc | 384 | struct opregion_asle *asle; |
04ebaadb | 385 | void *rvda; |
82730385 | 386 | const void *vbt; |
ada8f955 | 387 | u32 vbt_size; |
115719fc | 388 | u32 *lid_state; |
91a60f20 | 389 | struct work_struct asle_work; |
8ee1c3db | 390 | }; |
44834a67 | 391 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 392 | |
6ef3d427 CW |
393 | struct intel_overlay; |
394 | struct intel_overlay_error_state; | |
395 | ||
de151cf6 | 396 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
397 | #define I915_MAX_NUM_FENCES 32 |
398 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
399 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
400 | |
401 | struct drm_i915_fence_reg { | |
007cc8ac | 402 | struct list_head lru_list; |
caea7476 | 403 | struct drm_i915_gem_object *obj; |
1690e1eb | 404 | int pin_count; |
de151cf6 | 405 | }; |
7c1c2871 | 406 | |
9b9d172d | 407 | struct sdvo_device_mapping { |
e957d772 | 408 | u8 initialized; |
9b9d172d | 409 | u8 dvo_port; |
410 | u8 slave_addr; | |
411 | u8 dvo_wiring; | |
e957d772 | 412 | u8 i2c_pin; |
b1083333 | 413 | u8 ddc_pin; |
9b9d172d | 414 | }; |
415 | ||
c4a1d9e4 CW |
416 | struct intel_display_error_state; |
417 | ||
63eeaf38 | 418 | struct drm_i915_error_state { |
742cbee8 | 419 | struct kref ref; |
585b0288 BW |
420 | struct timeval time; |
421 | ||
cb383002 | 422 | char error_msg[128]; |
eb5be9d0 | 423 | int iommu; |
48b031e3 | 424 | u32 reset_count; |
62d5d69b | 425 | u32 suspend_count; |
cb383002 | 426 | |
585b0288 | 427 | /* Generic register state */ |
63eeaf38 JB |
428 | u32 eir; |
429 | u32 pgtbl_er; | |
be998e2e | 430 | u32 ier; |
885ea5a8 | 431 | u32 gtier[4]; |
b9a3906b | 432 | u32 ccid; |
0f3b6849 CW |
433 | u32 derrmr; |
434 | u32 forcewake; | |
585b0288 BW |
435 | u32 error; /* gen6+ */ |
436 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
437 | u32 fault_data0; /* gen8, gen9 */ |
438 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 439 | u32 done_reg; |
91ec5d11 BW |
440 | u32 gac_eco; |
441 | u32 gam_ecochk; | |
442 | u32 gab_ctl; | |
443 | u32 gfx_mode; | |
585b0288 | 444 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
445 | u64 fence[I915_MAX_NUM_FENCES]; |
446 | struct intel_overlay_error_state *overlay; | |
447 | struct intel_display_error_state *display; | |
0ca36d78 | 448 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 449 | |
52d39a21 | 450 | struct drm_i915_error_ring { |
372fbb8e | 451 | bool valid; |
362b8af7 BW |
452 | /* Software tracked state */ |
453 | bool waiting; | |
454 | int hangcheck_score; | |
455 | enum intel_ring_hangcheck_action hangcheck_action; | |
456 | int num_requests; | |
457 | ||
458 | /* our own tracking of ring head and tail */ | |
459 | u32 cpu_ring_head; | |
460 | u32 cpu_ring_tail; | |
461 | ||
462 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
463 | ||
464 | /* Register state */ | |
94f8cf10 | 465 | u32 start; |
362b8af7 BW |
466 | u32 tail; |
467 | u32 head; | |
468 | u32 ctl; | |
469 | u32 hws; | |
470 | u32 ipeir; | |
471 | u32 ipehr; | |
472 | u32 instdone; | |
362b8af7 BW |
473 | u32 bbstate; |
474 | u32 instpm; | |
475 | u32 instps; | |
476 | u32 seqno; | |
477 | u64 bbaddr; | |
50877445 | 478 | u64 acthd; |
362b8af7 | 479 | u32 fault_reg; |
13ffadd1 | 480 | u64 faddr; |
362b8af7 BW |
481 | u32 rc_psmi; /* sleep state */ |
482 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
483 | ||
52d39a21 CW |
484 | struct drm_i915_error_object { |
485 | int page_count; | |
e1f12325 | 486 | u64 gtt_offset; |
52d39a21 | 487 | u32 *pages[0]; |
ab0e7ff9 | 488 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 489 | |
f85db059 | 490 | struct drm_i915_error_object *wa_ctx; |
491 | ||
52d39a21 CW |
492 | struct drm_i915_error_request { |
493 | long jiffies; | |
494 | u32 seqno; | |
ee4f42b1 | 495 | u32 tail; |
52d39a21 | 496 | } *requests; |
6c7a01ec BW |
497 | |
498 | struct { | |
499 | u32 gfx_mode; | |
500 | union { | |
501 | u64 pdp[4]; | |
502 | u32 pp_dir_base; | |
503 | }; | |
504 | } vm_info; | |
ab0e7ff9 CW |
505 | |
506 | pid_t pid; | |
507 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 508 | } ring[I915_NUM_RINGS]; |
3a448734 | 509 | |
9df30794 | 510 | struct drm_i915_error_buffer { |
a779e5ab | 511 | u32 size; |
9df30794 | 512 | u32 name; |
b4716185 | 513 | u32 rseqno[I915_NUM_RINGS], wseqno; |
e1f12325 | 514 | u64 gtt_offset; |
9df30794 CW |
515 | u32 read_domains; |
516 | u32 write_domain; | |
4b9de737 | 517 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
518 | s32 pinned:2; |
519 | u32 tiling:2; | |
520 | u32 dirty:1; | |
521 | u32 purgeable:1; | |
5cc9ed4b | 522 | u32 userptr:1; |
5d1333fc | 523 | s32 ring:4; |
f56383cb | 524 | u32 cache_level:3; |
95f5301d | 525 | } **active_bo, **pinned_bo; |
6c7a01ec | 526 | |
95f5301d | 527 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 528 | u32 vm_count; |
63eeaf38 JB |
529 | }; |
530 | ||
7bd688cd | 531 | struct intel_connector; |
820d2d77 | 532 | struct intel_encoder; |
5cec258b | 533 | struct intel_crtc_state; |
5724dbd1 | 534 | struct intel_initial_plane_config; |
0e8ffe1b | 535 | struct intel_crtc; |
ee9300bb DV |
536 | struct intel_limit; |
537 | struct dpll; | |
b8cecdf5 | 538 | |
e70236a8 | 539 | struct drm_i915_display_funcs { |
e70236a8 JB |
540 | int (*get_display_clock_speed)(struct drm_device *dev); |
541 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
542 | /** |
543 | * find_dpll() - Find the best values for the PLL | |
544 | * @limit: limits for the PLL | |
545 | * @crtc: current CRTC | |
546 | * @target: target frequency in kHz | |
547 | * @refclk: reference clock frequency in kHz | |
548 | * @match_clock: if provided, @best_clock P divider must | |
549 | * match the P divider from @match_clock | |
550 | * used for LVDS downclocking | |
551 | * @best_clock: best PLL values found | |
552 | * | |
553 | * Returns true on success, false on failure. | |
554 | */ | |
555 | bool (*find_dpll)(const struct intel_limit *limit, | |
a93e255f | 556 | struct intel_crtc_state *crtc_state, |
ee9300bb DV |
557 | int target, int refclk, |
558 | struct dpll *match_clock, | |
559 | struct dpll *best_clock); | |
e3bddded | 560 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
561 | int (*compute_intermediate_wm)(struct drm_device *dev, |
562 | struct intel_crtc *intel_crtc, | |
563 | struct intel_crtc_state *newstate); | |
564 | void (*initial_watermarks)(struct intel_crtc_state *cstate); | |
565 | void (*optimize_watermarks)(struct intel_crtc_state *cstate); | |
46ba614c | 566 | void (*update_wm)(struct drm_crtc *crtc); |
27c329ed ML |
567 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
568 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
569 | /* Returns the active state of the crtc, and if the crtc is active, |
570 | * fills out the pipe-config with the hw state. */ | |
571 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 572 | struct intel_crtc_state *); |
5724dbd1 DL |
573 | void (*get_initial_plane_config)(struct intel_crtc *, |
574 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
575 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
576 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
577 | void (*crtc_enable)(struct drm_crtc *crtc); |
578 | void (*crtc_disable)(struct drm_crtc *crtc); | |
69bfe1a9 JN |
579 | void (*audio_codec_enable)(struct drm_connector *connector, |
580 | struct intel_encoder *encoder, | |
5e7234c9 | 581 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 582 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 583 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 584 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
585 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
586 | struct drm_framebuffer *fb, | |
ed8d1975 | 587 | struct drm_i915_gem_object *obj, |
6258fbe2 | 588 | struct drm_i915_gem_request *req, |
ed8d1975 | 589 | uint32_t flags); |
20afbda2 | 590 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
591 | /* clock updates for mode set */ |
592 | /* cursor updates */ | |
593 | /* render clock increase/decrease */ | |
594 | /* display clock increase/decrease */ | |
595 | /* pll clock increase/decrease */ | |
e70236a8 JB |
596 | }; |
597 | ||
48c1026a MK |
598 | enum forcewake_domain_id { |
599 | FW_DOMAIN_ID_RENDER = 0, | |
600 | FW_DOMAIN_ID_BLITTER, | |
601 | FW_DOMAIN_ID_MEDIA, | |
602 | ||
603 | FW_DOMAIN_ID_COUNT | |
604 | }; | |
605 | ||
606 | enum forcewake_domains { | |
607 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
608 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
609 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
610 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
611 | FORCEWAKE_BLITTER | | |
612 | FORCEWAKE_MEDIA) | |
613 | }; | |
614 | ||
907b28c5 | 615 | struct intel_uncore_funcs { |
c8d9a590 | 616 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 617 | enum forcewake_domains domains); |
c8d9a590 | 618 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 619 | enum forcewake_domains domains); |
0b274481 | 620 | |
f0f59a00 VS |
621 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
622 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
623 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
624 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
0b274481 | 625 | |
f0f59a00 | 626 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 627 | uint8_t val, bool trace); |
f0f59a00 | 628 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 629 | uint16_t val, bool trace); |
f0f59a00 | 630 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 631 | uint32_t val, bool trace); |
f0f59a00 | 632 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 633 | uint64_t val, bool trace); |
990bbdad CW |
634 | }; |
635 | ||
907b28c5 CW |
636 | struct intel_uncore { |
637 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
638 | ||
639 | struct intel_uncore_funcs funcs; | |
640 | ||
641 | unsigned fifo_count; | |
48c1026a | 642 | enum forcewake_domains fw_domains; |
b2cff0db CW |
643 | |
644 | struct intel_uncore_forcewake_domain { | |
645 | struct drm_i915_private *i915; | |
48c1026a | 646 | enum forcewake_domain_id id; |
b2cff0db CW |
647 | unsigned wake_count; |
648 | struct timer_list timer; | |
f0f59a00 | 649 | i915_reg_t reg_set; |
05a2fb15 MK |
650 | u32 val_set; |
651 | u32 val_clear; | |
f0f59a00 VS |
652 | i915_reg_t reg_ack; |
653 | i915_reg_t reg_post; | |
05a2fb15 | 654 | u32 val_reset; |
b2cff0db | 655 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
75714940 MK |
656 | |
657 | int unclaimed_mmio_check; | |
b2cff0db CW |
658 | }; |
659 | ||
660 | /* Iterate over initialised fw domains */ | |
661 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ | |
662 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
663 | (i__) < FW_DOMAIN_ID_COUNT; \ | |
664 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ | |
95150bdf | 665 | for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) |
b2cff0db CW |
666 | |
667 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ | |
668 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) | |
907b28c5 | 669 | |
b6e7d894 DL |
670 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
671 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
672 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
673 | ||
eb805623 | 674 | struct intel_csr { |
8144ac59 | 675 | struct work_struct work; |
eb805623 | 676 | const char *fw_path; |
a7f749f9 | 677 | uint32_t *dmc_payload; |
eb805623 | 678 | uint32_t dmc_fw_size; |
b6e7d894 | 679 | uint32_t version; |
eb805623 | 680 | uint32_t mmio_count; |
f0f59a00 | 681 | i915_reg_t mmioaddr[8]; |
eb805623 | 682 | uint32_t mmiodata[8]; |
832dba88 | 683 | uint32_t dc_state; |
a37baf3b | 684 | uint32_t allowed_dc_mask; |
eb805623 DV |
685 | }; |
686 | ||
79fc46df DL |
687 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
688 | func(is_mobile) sep \ | |
689 | func(is_i85x) sep \ | |
690 | func(is_i915g) sep \ | |
691 | func(is_i945gm) sep \ | |
692 | func(is_g33) sep \ | |
693 | func(need_gfx_hws) sep \ | |
694 | func(is_g4x) sep \ | |
695 | func(is_pineview) sep \ | |
696 | func(is_broadwater) sep \ | |
697 | func(is_crestline) sep \ | |
698 | func(is_ivybridge) sep \ | |
699 | func(is_valleyview) sep \ | |
666a4537 | 700 | func(is_cherryview) sep \ |
79fc46df | 701 | func(is_haswell) sep \ |
7201c0b3 | 702 | func(is_skylake) sep \ |
7526ac19 | 703 | func(is_broxton) sep \ |
ef11bdb3 | 704 | func(is_kabylake) sep \ |
b833d685 | 705 | func(is_preliminary) sep \ |
79fc46df DL |
706 | func(has_fbc) sep \ |
707 | func(has_pipe_cxsr) sep \ | |
708 | func(has_hotplug) sep \ | |
709 | func(cursor_needs_physical) sep \ | |
710 | func(has_overlay) sep \ | |
711 | func(overlay_needs_physical) sep \ | |
712 | func(supports_tv) sep \ | |
dd93be58 | 713 | func(has_llc) sep \ |
ca377809 | 714 | func(has_snoop) sep \ |
30568c45 DL |
715 | func(has_ddi) sep \ |
716 | func(has_fpga_dbg) | |
c96ea64e | 717 | |
a587f779 DL |
718 | #define DEFINE_FLAG(name) u8 name:1 |
719 | #define SEP_SEMICOLON ; | |
c96ea64e | 720 | |
cfdf1fa2 | 721 | struct intel_device_info { |
10fce67a | 722 | u32 display_mmio_offset; |
87f1f465 | 723 | u16 device_id; |
7eb552ae | 724 | u8 num_pipes:3; |
d615a166 | 725 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 726 | u8 gen; |
73ae478c | 727 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 728 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
729 | /* Register offsets for the various display pipes and transcoders */ |
730 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
731 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 732 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 733 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
734 | |
735 | /* Slice/subslice/EU info */ | |
736 | u8 slice_total; | |
737 | u8 subslice_total; | |
738 | u8 subslice_per_slice; | |
739 | u8 eu_total; | |
740 | u8 eu_per_subslice; | |
b7668791 DL |
741 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
742 | u8 subslice_7eu[3]; | |
3873218f JM |
743 | u8 has_slice_pg:1; |
744 | u8 has_subslice_pg:1; | |
745 | u8 has_eu_pg:1; | |
cfdf1fa2 KH |
746 | }; |
747 | ||
a587f779 DL |
748 | #undef DEFINE_FLAG |
749 | #undef SEP_SEMICOLON | |
750 | ||
7faf1ab2 DV |
751 | enum i915_cache_level { |
752 | I915_CACHE_NONE = 0, | |
350ec881 CW |
753 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
754 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
755 | caches, eg sampler/render caches, and the | |
756 | large Last-Level-Cache. LLC is coherent with | |
757 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 758 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
759 | }; |
760 | ||
e59ec13d MK |
761 | struct i915_ctx_hang_stats { |
762 | /* This context had batch pending when hang was declared */ | |
763 | unsigned batch_pending; | |
764 | ||
765 | /* This context had batch active when hang was declared */ | |
766 | unsigned batch_active; | |
be62acb4 MK |
767 | |
768 | /* Time when this context was last blamed for a GPU reset */ | |
769 | unsigned long guilty_ts; | |
770 | ||
676fa572 CW |
771 | /* If the contexts causes a second GPU hang within this time, |
772 | * it is permanently banned from submitting any more work. | |
773 | */ | |
774 | unsigned long ban_period_seconds; | |
775 | ||
be62acb4 MK |
776 | /* This context is banned to submit more work */ |
777 | bool banned; | |
e59ec13d | 778 | }; |
40521054 BW |
779 | |
780 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 781 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 DW |
782 | |
783 | #define CONTEXT_NO_ZEROMAP (1<<0) | |
31b7a88d OM |
784 | /** |
785 | * struct intel_context - as the name implies, represents a context. | |
786 | * @ref: reference count. | |
787 | * @user_handle: userspace tracking identity for this context. | |
788 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
789 | * @flags: context specific flags: |
790 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
791 | * @file_priv: filp associated with this context (NULL for global default |
792 | * context). | |
793 | * @hang_stats: information about the role of this context in possible GPU | |
794 | * hangs. | |
7df113e4 | 795 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
796 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
797 | * initialized (legacy ring submission mechanism only). | |
798 | * @link: link in the global list of contexts. | |
799 | * | |
800 | * Contexts are memory images used by the hardware to store copies of their | |
801 | * internal state. | |
802 | */ | |
273497e5 | 803 | struct intel_context { |
dce3271b | 804 | struct kref ref; |
821d66dd | 805 | int user_handle; |
3ccfd19d | 806 | uint8_t remap_slice; |
9ea4feec | 807 | struct drm_i915_private *i915; |
b1b38278 | 808 | int flags; |
40521054 | 809 | struct drm_i915_file_private *file_priv; |
e59ec13d | 810 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 811 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 812 | |
c9e003af | 813 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
814 | struct { |
815 | struct drm_i915_gem_object *rcs_state; | |
816 | bool initialized; | |
817 | } legacy_hw_ctx; | |
818 | ||
c9e003af OM |
819 | /* Execlists */ |
820 | struct { | |
821 | struct drm_i915_gem_object *state; | |
84c2377f | 822 | struct intel_ringbuffer *ringbuf; |
a7cbedec | 823 | int pin_count; |
ca82580c TU |
824 | struct i915_vma *lrc_vma; |
825 | u64 lrc_desc; | |
82352e90 | 826 | uint32_t *lrc_reg_state; |
c9e003af OM |
827 | } engine[I915_NUM_RINGS]; |
828 | ||
a33afea5 | 829 | struct list_head link; |
40521054 BW |
830 | }; |
831 | ||
a4001f1b PZ |
832 | enum fb_op_origin { |
833 | ORIGIN_GTT, | |
834 | ORIGIN_CPU, | |
835 | ORIGIN_CS, | |
836 | ORIGIN_FLIP, | |
74b4ea1e | 837 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
838 | }; |
839 | ||
ab34a7e8 | 840 | struct intel_fbc { |
25ad93fd PZ |
841 | /* This is always the inner lock when overlapping with struct_mutex and |
842 | * it's the outer lock when overlapping with stolen_lock. */ | |
843 | struct mutex lock; | |
5e59f717 | 844 | unsigned threshold; |
dbef0f15 PZ |
845 | unsigned int possible_framebuffer_bits; |
846 | unsigned int busy_bits; | |
010cf73d | 847 | unsigned int visible_pipes_mask; |
e35fef21 | 848 | struct intel_crtc *crtc; |
5c3fe8b0 | 849 | |
c4213885 | 850 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
851 | struct drm_mm_node *compressed_llb; |
852 | ||
da46f936 RV |
853 | bool false_color; |
854 | ||
d029bcad | 855 | bool enabled; |
0e631adc | 856 | bool active; |
9adccc60 | 857 | |
aaf78d27 PZ |
858 | struct intel_fbc_state_cache { |
859 | struct { | |
860 | unsigned int mode_flags; | |
861 | uint32_t hsw_bdw_pixel_rate; | |
862 | } crtc; | |
863 | ||
864 | struct { | |
865 | unsigned int rotation; | |
866 | int src_w; | |
867 | int src_h; | |
868 | bool visible; | |
869 | } plane; | |
870 | ||
871 | struct { | |
872 | u64 ilk_ggtt_offset; | |
aaf78d27 PZ |
873 | uint32_t pixel_format; |
874 | unsigned int stride; | |
875 | int fence_reg; | |
876 | unsigned int tiling_mode; | |
877 | } fb; | |
878 | } state_cache; | |
879 | ||
b183b3f1 PZ |
880 | struct intel_fbc_reg_params { |
881 | struct { | |
882 | enum pipe pipe; | |
883 | enum plane plane; | |
884 | unsigned int fence_y_offset; | |
885 | } crtc; | |
886 | ||
887 | struct { | |
888 | u64 ggtt_offset; | |
b183b3f1 PZ |
889 | uint32_t pixel_format; |
890 | unsigned int stride; | |
891 | int fence_reg; | |
892 | } fb; | |
893 | ||
894 | int cfb_size; | |
895 | } params; | |
896 | ||
5c3fe8b0 | 897 | struct intel_fbc_work { |
128d7356 | 898 | bool scheduled; |
ca18d51d | 899 | u32 scheduled_vblank; |
128d7356 | 900 | struct work_struct work; |
128d7356 | 901 | } work; |
5c3fe8b0 | 902 | |
bf6189c6 | 903 | const char *no_fbc_reason; |
b5e50c3f JB |
904 | }; |
905 | ||
96178eeb VK |
906 | /** |
907 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
908 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
909 | * parsing for same resolution. | |
910 | */ | |
911 | enum drrs_refresh_rate_type { | |
912 | DRRS_HIGH_RR, | |
913 | DRRS_LOW_RR, | |
914 | DRRS_MAX_RR, /* RR count */ | |
915 | }; | |
916 | ||
917 | enum drrs_support_type { | |
918 | DRRS_NOT_SUPPORTED = 0, | |
919 | STATIC_DRRS_SUPPORT = 1, | |
920 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
921 | }; |
922 | ||
2807cf69 | 923 | struct intel_dp; |
96178eeb VK |
924 | struct i915_drrs { |
925 | struct mutex mutex; | |
926 | struct delayed_work work; | |
927 | struct intel_dp *dp; | |
928 | unsigned busy_frontbuffer_bits; | |
929 | enum drrs_refresh_rate_type refresh_rate_type; | |
930 | enum drrs_support_type type; | |
931 | }; | |
932 | ||
a031d709 | 933 | struct i915_psr { |
f0355c4a | 934 | struct mutex lock; |
a031d709 RV |
935 | bool sink_support; |
936 | bool source_ok; | |
2807cf69 | 937 | struct intel_dp *enabled; |
7c8f8a70 RV |
938 | bool active; |
939 | struct delayed_work work; | |
9ca15301 | 940 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
941 | bool psr2_support; |
942 | bool aux_frame_sync; | |
60e5ffe3 | 943 | bool link_standby; |
3f51e471 | 944 | }; |
5c3fe8b0 | 945 | |
3bad0781 | 946 | enum intel_pch { |
f0350830 | 947 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
948 | PCH_IBX, /* Ibexpeak PCH */ |
949 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 950 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 951 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 952 | PCH_NOP, |
3bad0781 ZW |
953 | }; |
954 | ||
988d6ee8 PZ |
955 | enum intel_sbi_destination { |
956 | SBI_ICLK, | |
957 | SBI_MPHY, | |
958 | }; | |
959 | ||
b690e96c | 960 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 961 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 962 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 963 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 964 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 965 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 966 | |
8be48d92 | 967 | struct intel_fbdev; |
1630fe75 | 968 | struct intel_fbc_work; |
38651674 | 969 | |
c2b9152f DV |
970 | struct intel_gmbus { |
971 | struct i2c_adapter adapter; | |
f2ce9faf | 972 | u32 force_bit; |
c2b9152f | 973 | u32 reg0; |
f0f59a00 | 974 | i915_reg_t gpio_reg; |
c167a6fc | 975 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
976 | struct drm_i915_private *dev_priv; |
977 | }; | |
978 | ||
f4c956ad | 979 | struct i915_suspend_saved_registers { |
e948e994 | 980 | u32 saveDSPARB; |
ba8bbcf6 | 981 | u32 saveLVDS; |
585fb111 JB |
982 | u32 savePP_ON_DELAYS; |
983 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
984 | u32 savePP_ON; |
985 | u32 savePP_OFF; | |
986 | u32 savePP_CONTROL; | |
585fb111 | 987 | u32 savePP_DIVISOR; |
ba8bbcf6 | 988 | u32 saveFBC_CONTROL; |
1f84e550 | 989 | u32 saveCACHE_MODE_0; |
1f84e550 | 990 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
991 | u32 saveSWF0[16]; |
992 | u32 saveSWF1[16]; | |
85fa792b | 993 | u32 saveSWF3[3]; |
4b9de737 | 994 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 995 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 996 | u16 saveGCDGMBUS; |
f4c956ad | 997 | }; |
c85aa885 | 998 | |
ddeea5b0 ID |
999 | struct vlv_s0ix_state { |
1000 | /* GAM */ | |
1001 | u32 wr_watermark; | |
1002 | u32 gfx_prio_ctrl; | |
1003 | u32 arb_mode; | |
1004 | u32 gfx_pend_tlb0; | |
1005 | u32 gfx_pend_tlb1; | |
1006 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1007 | u32 media_max_req_count; | |
1008 | u32 gfx_max_req_count; | |
1009 | u32 render_hwsp; | |
1010 | u32 ecochk; | |
1011 | u32 bsd_hwsp; | |
1012 | u32 blt_hwsp; | |
1013 | u32 tlb_rd_addr; | |
1014 | ||
1015 | /* MBC */ | |
1016 | u32 g3dctl; | |
1017 | u32 gsckgctl; | |
1018 | u32 mbctl; | |
1019 | ||
1020 | /* GCP */ | |
1021 | u32 ucgctl1; | |
1022 | u32 ucgctl3; | |
1023 | u32 rcgctl1; | |
1024 | u32 rcgctl2; | |
1025 | u32 rstctl; | |
1026 | u32 misccpctl; | |
1027 | ||
1028 | /* GPM */ | |
1029 | u32 gfxpause; | |
1030 | u32 rpdeuhwtc; | |
1031 | u32 rpdeuc; | |
1032 | u32 ecobus; | |
1033 | u32 pwrdwnupctl; | |
1034 | u32 rp_down_timeout; | |
1035 | u32 rp_deucsw; | |
1036 | u32 rcubmabdtmr; | |
1037 | u32 rcedata; | |
1038 | u32 spare2gh; | |
1039 | ||
1040 | /* Display 1 CZ domain */ | |
1041 | u32 gt_imr; | |
1042 | u32 gt_ier; | |
1043 | u32 pm_imr; | |
1044 | u32 pm_ier; | |
1045 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1046 | ||
1047 | /* GT SA CZ domain */ | |
1048 | u32 tilectl; | |
1049 | u32 gt_fifoctl; | |
1050 | u32 gtlc_wake_ctrl; | |
1051 | u32 gtlc_survive; | |
1052 | u32 pmwgicz; | |
1053 | ||
1054 | /* Display 2 CZ domain */ | |
1055 | u32 gu_ctl0; | |
1056 | u32 gu_ctl1; | |
9c25210f | 1057 | u32 pcbr; |
ddeea5b0 ID |
1058 | u32 clock_gate_dis2; |
1059 | }; | |
1060 | ||
bf225f20 CW |
1061 | struct intel_rps_ei { |
1062 | u32 cz_clock; | |
1063 | u32 render_c0; | |
1064 | u32 media_c0; | |
31685c25 D |
1065 | }; |
1066 | ||
c85aa885 | 1067 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1068 | /* |
1069 | * work, interrupts_enabled and pm_iir are protected by | |
1070 | * dev_priv->irq_lock | |
1071 | */ | |
c85aa885 | 1072 | struct work_struct work; |
d4d70aa5 | 1073 | bool interrupts_enabled; |
c85aa885 | 1074 | u32 pm_iir; |
59cdb63d | 1075 | |
b39fb297 BW |
1076 | /* Frequencies are stored in potentially platform dependent multiples. |
1077 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1078 | * Soft limits are those which are used for the dynamic reclocking done | |
1079 | * by the driver (raise frequencies under heavy loads, and lower for | |
1080 | * lighter loads). Hard limits are those imposed by the hardware. | |
1081 | * | |
1082 | * A distinction is made for overclocking, which is never enabled by | |
1083 | * default, and is considered to be above the hard limit if it's | |
1084 | * possible at all. | |
1085 | */ | |
1086 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1087 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1088 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1089 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1090 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
aed242ff | 1091 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1092 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1093 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1094 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
1a01ab3b | 1095 | |
8fb55197 CW |
1096 | u8 up_threshold; /* Current %busy required to uplock */ |
1097 | u8 down_threshold; /* Current %busy required to downclock */ | |
1098 | ||
dd75fdc8 CW |
1099 | int last_adj; |
1100 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1101 | ||
8d3afd7d CW |
1102 | spinlock_t client_lock; |
1103 | struct list_head clients; | |
1104 | bool client_boost; | |
1105 | ||
c0951f0c | 1106 | bool enabled; |
1a01ab3b | 1107 | struct delayed_work delayed_resume_work; |
1854d5ca | 1108 | unsigned boosts; |
4fc688ce | 1109 | |
2e1b8730 | 1110 | struct intel_rps_client semaphores, mmioflips; |
a6f766f3 | 1111 | |
bf225f20 CW |
1112 | /* manual wa residency calculations */ |
1113 | struct intel_rps_ei up_ei, down_ei; | |
1114 | ||
4fc688ce JB |
1115 | /* |
1116 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1117 | * Must be taken after struct_mutex if nested. Note that |
1118 | * this lock may be held for long periods of time when | |
1119 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1120 | */ |
1121 | struct mutex hw_lock; | |
c85aa885 DV |
1122 | }; |
1123 | ||
1a240d4d DV |
1124 | /* defined intel_pm.c */ |
1125 | extern spinlock_t mchdev_lock; | |
1126 | ||
c85aa885 DV |
1127 | struct intel_ilk_power_mgmt { |
1128 | u8 cur_delay; | |
1129 | u8 min_delay; | |
1130 | u8 max_delay; | |
1131 | u8 fmax; | |
1132 | u8 fstart; | |
1133 | ||
1134 | u64 last_count1; | |
1135 | unsigned long last_time1; | |
1136 | unsigned long chipset_power; | |
1137 | u64 last_count2; | |
5ed0bdf2 | 1138 | u64 last_time2; |
c85aa885 DV |
1139 | unsigned long gfx_power; |
1140 | u8 corr; | |
1141 | ||
1142 | int c_m; | |
1143 | int r_t; | |
1144 | }; | |
1145 | ||
c6cb582e ID |
1146 | struct drm_i915_private; |
1147 | struct i915_power_well; | |
1148 | ||
1149 | struct i915_power_well_ops { | |
1150 | /* | |
1151 | * Synchronize the well's hw state to match the current sw state, for | |
1152 | * example enable/disable it based on the current refcount. Called | |
1153 | * during driver init and resume time, possibly after first calling | |
1154 | * the enable/disable handlers. | |
1155 | */ | |
1156 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1157 | struct i915_power_well *power_well); | |
1158 | /* | |
1159 | * Enable the well and resources that depend on it (for example | |
1160 | * interrupts located on the well). Called after the 0->1 refcount | |
1161 | * transition. | |
1162 | */ | |
1163 | void (*enable)(struct drm_i915_private *dev_priv, | |
1164 | struct i915_power_well *power_well); | |
1165 | /* | |
1166 | * Disable the well and resources that depend on it. Called after | |
1167 | * the 1->0 refcount transition. | |
1168 | */ | |
1169 | void (*disable)(struct drm_i915_private *dev_priv, | |
1170 | struct i915_power_well *power_well); | |
1171 | /* Returns the hw enabled state. */ | |
1172 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1173 | struct i915_power_well *power_well); | |
1174 | }; | |
1175 | ||
a38911a3 WX |
1176 | /* Power well structure for haswell */ |
1177 | struct i915_power_well { | |
c1ca727f | 1178 | const char *name; |
6f3ef5dd | 1179 | bool always_on; |
a38911a3 WX |
1180 | /* power well enable/disable usage count */ |
1181 | int count; | |
bfafe93a ID |
1182 | /* cached hw enabled state */ |
1183 | bool hw_enabled; | |
c1ca727f | 1184 | unsigned long domains; |
77961eb9 | 1185 | unsigned long data; |
c6cb582e | 1186 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1187 | }; |
1188 | ||
83c00f55 | 1189 | struct i915_power_domains { |
baa70707 ID |
1190 | /* |
1191 | * Power wells needed for initialization at driver init and suspend | |
1192 | * time are on. They are kept on until after the first modeset. | |
1193 | */ | |
1194 | bool init_power_on; | |
0d116a29 | 1195 | bool initializing; |
c1ca727f | 1196 | int power_well_count; |
baa70707 | 1197 | |
83c00f55 | 1198 | struct mutex lock; |
1da51581 | 1199 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1200 | struct i915_power_well *power_wells; |
83c00f55 ID |
1201 | }; |
1202 | ||
35a85ac6 | 1203 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1204 | struct intel_l3_parity { |
35a85ac6 | 1205 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1206 | struct work_struct error_work; |
35a85ac6 | 1207 | int which_slice; |
a4da4fa4 DV |
1208 | }; |
1209 | ||
4b5aed62 | 1210 | struct i915_gem_mm { |
4b5aed62 DV |
1211 | /** Memory allocator for GTT stolen memory */ |
1212 | struct drm_mm stolen; | |
92e97d2f PZ |
1213 | /** Protects the usage of the GTT stolen memory allocator. This is |
1214 | * always the inner lock when overlapping with struct_mutex. */ | |
1215 | struct mutex stolen_lock; | |
1216 | ||
4b5aed62 DV |
1217 | /** List of all objects in gtt_space. Used to restore gtt |
1218 | * mappings on resume */ | |
1219 | struct list_head bound_list; | |
1220 | /** | |
1221 | * List of objects which are not bound to the GTT (thus | |
1222 | * are idle and not used by the GPU) but still have | |
1223 | * (presumably uncached) pages still attached. | |
1224 | */ | |
1225 | struct list_head unbound_list; | |
1226 | ||
1227 | /** Usable portion of the GTT for GEM */ | |
1228 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1229 | ||
4b5aed62 DV |
1230 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1231 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1232 | ||
2cfcd32a | 1233 | struct notifier_block oom_notifier; |
ceabbba5 | 1234 | struct shrinker shrinker; |
4b5aed62 DV |
1235 | bool shrinker_no_lock_stealing; |
1236 | ||
4b5aed62 DV |
1237 | /** LRU list of objects with fence regs on them. */ |
1238 | struct list_head fence_list; | |
1239 | ||
1240 | /** | |
1241 | * We leave the user IRQ off as much as possible, | |
1242 | * but this means that requests will finish and never | |
1243 | * be retired once the system goes idle. Set a timer to | |
1244 | * fire periodically while the ring is running. When it | |
1245 | * fires, go retire requests. | |
1246 | */ | |
1247 | struct delayed_work retire_work; | |
1248 | ||
b29c19b6 CW |
1249 | /** |
1250 | * When we detect an idle GPU, we want to turn on | |
1251 | * powersaving features. So once we see that there | |
1252 | * are no more requests outstanding and no more | |
1253 | * arrive within a small period of time, we fire | |
1254 | * off the idle_work. | |
1255 | */ | |
1256 | struct delayed_work idle_work; | |
1257 | ||
4b5aed62 DV |
1258 | /** |
1259 | * Are we in a non-interruptible section of code like | |
1260 | * modesetting? | |
1261 | */ | |
1262 | bool interruptible; | |
1263 | ||
f62a0076 CW |
1264 | /** |
1265 | * Is the GPU currently considered idle, or busy executing userspace | |
1266 | * requests? Whilst idle, we attempt to power down the hardware and | |
1267 | * display clocks. In order to reduce the effect on performance, there | |
1268 | * is a slight delay before we do so. | |
1269 | */ | |
1270 | bool busy; | |
1271 | ||
bdf1e7e3 | 1272 | /* the indicator for dispatch video commands on two BSD rings */ |
de1add36 | 1273 | unsigned int bsd_ring_dispatch_index; |
bdf1e7e3 | 1274 | |
4b5aed62 DV |
1275 | /** Bit 6 swizzling required for X tiling */ |
1276 | uint32_t bit_6_swizzle_x; | |
1277 | /** Bit 6 swizzling required for Y tiling */ | |
1278 | uint32_t bit_6_swizzle_y; | |
1279 | ||
4b5aed62 | 1280 | /* accounting, useful for userland debugging */ |
c20e8355 | 1281 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1282 | size_t object_memory; |
1283 | u32 object_count; | |
1284 | }; | |
1285 | ||
edc3d884 | 1286 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1287 | struct drm_i915_private *i915; |
edc3d884 MK |
1288 | unsigned bytes; |
1289 | unsigned size; | |
1290 | int err; | |
1291 | u8 *buf; | |
1292 | loff_t start; | |
1293 | loff_t pos; | |
1294 | }; | |
1295 | ||
fc16b48b MK |
1296 | struct i915_error_state_file_priv { |
1297 | struct drm_device *dev; | |
1298 | struct drm_i915_error_state *error; | |
1299 | }; | |
1300 | ||
99584db3 DV |
1301 | struct i915_gpu_error { |
1302 | /* For hangcheck timer */ | |
1303 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1304 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1305 | /* Hang gpu twice in this window and your context gets banned */ |
1306 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1307 | ||
737b1506 CW |
1308 | struct workqueue_struct *hangcheck_wq; |
1309 | struct delayed_work hangcheck_work; | |
99584db3 DV |
1310 | |
1311 | /* For reset and error_state handling. */ | |
1312 | spinlock_t lock; | |
1313 | /* Protected by the above dev->gpu_error.lock. */ | |
1314 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1315 | |
1316 | unsigned long missed_irq_rings; | |
1317 | ||
1f83fee0 | 1318 | /** |
2ac0f450 | 1319 | * State variable controlling the reset flow and count |
1f83fee0 | 1320 | * |
2ac0f450 MK |
1321 | * This is a counter which gets incremented when reset is triggered, |
1322 | * and again when reset has been handled. So odd values (lowest bit set) | |
1323 | * means that reset is in progress and even values that | |
1324 | * (reset_counter >> 1):th reset was successfully completed. | |
1325 | * | |
1326 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1327 | * set meaning that hardware is terminally sour and there is no | |
1328 | * recovery. All waiters on the reset_queue will be woken when | |
1329 | * that happens. | |
1330 | * | |
1331 | * This counter is used by the wait_seqno code to notice that reset | |
1332 | * event happened and it needs to restart the entire ioctl (since most | |
1333 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1334 | * |
1335 | * This is important for lock-free wait paths, where no contended lock | |
1336 | * naturally enforces the correct ordering between the bail-out of the | |
1337 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1338 | */ |
1339 | atomic_t reset_counter; | |
1340 | ||
1f83fee0 | 1341 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1342 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1343 | |
1344 | /** | |
1345 | * Waitqueue to signal when the reset has completed. Used by clients | |
1346 | * that wait for dev_priv->mm.wedged to settle. | |
1347 | */ | |
1348 | wait_queue_head_t reset_queue; | |
33196ded | 1349 | |
88b4aa87 MK |
1350 | /* Userspace knobs for gpu hang simulation; |
1351 | * combines both a ring mask, and extra flags | |
1352 | */ | |
1353 | u32 stop_rings; | |
1354 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1355 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1356 | |
1357 | /* For missed irq/seqno simulation. */ | |
1358 | unsigned int test_irq_rings; | |
6689c167 MA |
1359 | |
1360 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1361 | bool reload_in_reset; | |
99584db3 DV |
1362 | }; |
1363 | ||
b8efb17b ZR |
1364 | enum modeset_restore { |
1365 | MODESET_ON_LID_OPEN, | |
1366 | MODESET_DONE, | |
1367 | MODESET_SUSPENDED, | |
1368 | }; | |
1369 | ||
500ea70d RV |
1370 | #define DP_AUX_A 0x40 |
1371 | #define DP_AUX_B 0x10 | |
1372 | #define DP_AUX_C 0x20 | |
1373 | #define DP_AUX_D 0x30 | |
1374 | ||
11c1b657 XZ |
1375 | #define DDC_PIN_B 0x05 |
1376 | #define DDC_PIN_C 0x04 | |
1377 | #define DDC_PIN_D 0x06 | |
1378 | ||
6acab15a | 1379 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1380 | /* |
1381 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1382 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1383 | * populate this field. | |
1384 | */ | |
1385 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1386 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1387 | |
1388 | uint8_t supports_dvi:1; | |
1389 | uint8_t supports_hdmi:1; | |
1390 | uint8_t supports_dp:1; | |
500ea70d RV |
1391 | |
1392 | uint8_t alternate_aux_channel; | |
11c1b657 | 1393 | uint8_t alternate_ddc_pin; |
75067dde AK |
1394 | |
1395 | uint8_t dp_boost_level; | |
1396 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1397 | }; |
1398 | ||
bfd7ebda RV |
1399 | enum psr_lines_to_wait { |
1400 | PSR_0_LINES_TO_WAIT = 0, | |
1401 | PSR_1_LINE_TO_WAIT, | |
1402 | PSR_4_LINES_TO_WAIT, | |
1403 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1404 | }; |
1405 | ||
41aa3448 RV |
1406 | struct intel_vbt_data { |
1407 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1408 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1409 | ||
1410 | /* Feature bits */ | |
1411 | unsigned int int_tv_support:1; | |
1412 | unsigned int lvds_dither:1; | |
1413 | unsigned int lvds_vbt:1; | |
1414 | unsigned int int_crt_support:1; | |
1415 | unsigned int lvds_use_ssc:1; | |
1416 | unsigned int display_clock_mode:1; | |
1417 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1418 | unsigned int has_mipi:1; |
41aa3448 RV |
1419 | int lvds_ssc_freq; |
1420 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1421 | ||
83a7280e PB |
1422 | enum drrs_support_type drrs_type; |
1423 | ||
41aa3448 RV |
1424 | /* eDP */ |
1425 | int edp_rate; | |
1426 | int edp_lanes; | |
1427 | int edp_preemphasis; | |
1428 | int edp_vswing; | |
1429 | bool edp_initialized; | |
1430 | bool edp_support; | |
1431 | int edp_bpp; | |
1432 | struct edp_power_seq edp_pps; | |
1433 | ||
bfd7ebda RV |
1434 | struct { |
1435 | bool full_link; | |
1436 | bool require_aux_wakeup; | |
1437 | int idle_frames; | |
1438 | enum psr_lines_to_wait lines_to_wait; | |
1439 | int tp1_wakeup_time; | |
1440 | int tp2_tp3_wakeup_time; | |
1441 | } psr; | |
1442 | ||
f00076d2 JN |
1443 | struct { |
1444 | u16 pwm_freq_hz; | |
39fbc9c8 | 1445 | bool present; |
f00076d2 | 1446 | bool active_low_pwm; |
1de6068e | 1447 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1448 | } backlight; |
1449 | ||
d17c5443 SK |
1450 | /* MIPI DSI */ |
1451 | struct { | |
3e6bd011 | 1452 | u16 port; |
d17c5443 | 1453 | u16 panel_id; |
d3b542fc SK |
1454 | struct mipi_config *config; |
1455 | struct mipi_pps_data *pps; | |
1456 | u8 seq_version; | |
1457 | u32 size; | |
1458 | u8 *data; | |
8d3ed2f3 | 1459 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1460 | } dsi; |
1461 | ||
41aa3448 RV |
1462 | int crt_ddc_pin; |
1463 | ||
1464 | int child_dev_num; | |
768f69c9 | 1465 | union child_device_config *child_dev; |
6acab15a PZ |
1466 | |
1467 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1468 | }; |
1469 | ||
77c122bc VS |
1470 | enum intel_ddb_partitioning { |
1471 | INTEL_DDB_PART_1_2, | |
1472 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1473 | }; | |
1474 | ||
1fd527cc VS |
1475 | struct intel_wm_level { |
1476 | bool enable; | |
1477 | uint32_t pri_val; | |
1478 | uint32_t spr_val; | |
1479 | uint32_t cur_val; | |
1480 | uint32_t fbc_val; | |
1481 | }; | |
1482 | ||
820c1980 | 1483 | struct ilk_wm_values { |
609cedef VS |
1484 | uint32_t wm_pipe[3]; |
1485 | uint32_t wm_lp[3]; | |
1486 | uint32_t wm_lp_spr[3]; | |
1487 | uint32_t wm_linetime[3]; | |
1488 | bool enable_fbc_wm; | |
1489 | enum intel_ddb_partitioning partitioning; | |
1490 | }; | |
1491 | ||
262cd2e1 VS |
1492 | struct vlv_pipe_wm { |
1493 | uint16_t primary; | |
1494 | uint16_t sprite[2]; | |
1495 | uint8_t cursor; | |
1496 | }; | |
ae80152d | 1497 | |
262cd2e1 VS |
1498 | struct vlv_sr_wm { |
1499 | uint16_t plane; | |
1500 | uint8_t cursor; | |
1501 | }; | |
ae80152d | 1502 | |
262cd2e1 VS |
1503 | struct vlv_wm_values { |
1504 | struct vlv_pipe_wm pipe[3]; | |
1505 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1506 | struct { |
1507 | uint8_t cursor; | |
1508 | uint8_t sprite[2]; | |
1509 | uint8_t primary; | |
1510 | } ddl[3]; | |
6eb1a681 VS |
1511 | uint8_t level; |
1512 | bool cxsr; | |
0018fda1 VS |
1513 | }; |
1514 | ||
c193924e | 1515 | struct skl_ddb_entry { |
16160e3d | 1516 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1517 | }; |
1518 | ||
1519 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1520 | { | |
16160e3d | 1521 | return entry->end - entry->start; |
c193924e DL |
1522 | } |
1523 | ||
08db6652 DL |
1524 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1525 | const struct skl_ddb_entry *e2) | |
1526 | { | |
1527 | if (e1->start == e2->start && e1->end == e2->end) | |
1528 | return true; | |
1529 | ||
1530 | return false; | |
1531 | } | |
1532 | ||
c193924e | 1533 | struct skl_ddb_allocation { |
34bb56af | 1534 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 | 1535 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1536 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1537 | }; |
1538 | ||
2ac96d2a PB |
1539 | struct skl_wm_values { |
1540 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1541 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1542 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1543 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
2ac96d2a | 1544 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
2ac96d2a PB |
1545 | }; |
1546 | ||
1547 | struct skl_wm_level { | |
1548 | bool plane_en[I915_MAX_PLANES]; | |
1549 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1550 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1551 | }; |
1552 | ||
c67a470b | 1553 | /* |
765dab67 PZ |
1554 | * This struct helps tracking the state needed for runtime PM, which puts the |
1555 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1556 | * graphics device works, even register access, so we don't get interrupts nor | |
1557 | * anything else. | |
c67a470b | 1558 | * |
765dab67 PZ |
1559 | * Every piece of our code that needs to actually touch the hardware needs to |
1560 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1561 | * appropriate power domain. | |
a8a8bd54 | 1562 | * |
765dab67 PZ |
1563 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1564 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1565 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1566 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1567 | * |
1568 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1569 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1570 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1571 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1572 | * case it happens. |
c67a470b | 1573 | * |
765dab67 | 1574 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1575 | */ |
5d584b2e | 1576 | struct i915_runtime_pm { |
1f814dac | 1577 | atomic_t wakeref_count; |
2b19efeb | 1578 | atomic_t atomic_seq; |
5d584b2e | 1579 | bool suspended; |
2aeb7d3a | 1580 | bool irqs_enabled; |
c67a470b PZ |
1581 | }; |
1582 | ||
926321d5 DV |
1583 | enum intel_pipe_crc_source { |
1584 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1585 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1586 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1587 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1588 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1589 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1590 | INTEL_PIPE_CRC_SOURCE_TV, | |
1591 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1592 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1593 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1594 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1595 | INTEL_PIPE_CRC_SOURCE_MAX, |
1596 | }; | |
1597 | ||
8bf1e9f1 | 1598 | struct intel_pipe_crc_entry { |
ac2300d4 | 1599 | uint32_t frame; |
8bf1e9f1 SH |
1600 | uint32_t crc[5]; |
1601 | }; | |
1602 | ||
b2c88f5b | 1603 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1604 | struct intel_pipe_crc { |
d538bbdf DL |
1605 | spinlock_t lock; |
1606 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1607 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1608 | enum intel_pipe_crc_source source; |
d538bbdf | 1609 | int head, tail; |
07144428 | 1610 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1611 | }; |
1612 | ||
f99d7069 DV |
1613 | struct i915_frontbuffer_tracking { |
1614 | struct mutex lock; | |
1615 | ||
1616 | /* | |
1617 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1618 | * scheduled flips. | |
1619 | */ | |
1620 | unsigned busy_bits; | |
1621 | unsigned flip_bits; | |
1622 | }; | |
1623 | ||
7225342a | 1624 | struct i915_wa_reg { |
f0f59a00 | 1625 | i915_reg_t addr; |
7225342a MK |
1626 | u32 value; |
1627 | /* bitmask representing WA bits */ | |
1628 | u32 mask; | |
1629 | }; | |
1630 | ||
33136b06 AS |
1631 | /* |
1632 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1633 | * allowing it for RCS as we don't foresee any requirement of having | |
1634 | * a whitelist for other engines. When it is really required for | |
1635 | * other engines then the limit need to be increased. | |
1636 | */ | |
1637 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
7225342a MK |
1638 | |
1639 | struct i915_workarounds { | |
1640 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1641 | u32 count; | |
33136b06 | 1642 | u32 hw_whitelist_count[I915_NUM_RINGS]; |
7225342a MK |
1643 | }; |
1644 | ||
cf9d2890 YZ |
1645 | struct i915_virtual_gpu { |
1646 | bool active; | |
1647 | }; | |
1648 | ||
5f19e2bf JH |
1649 | struct i915_execbuffer_params { |
1650 | struct drm_device *dev; | |
1651 | struct drm_file *file; | |
1652 | uint32_t dispatch_flags; | |
1653 | uint32_t args_batch_start_offset; | |
af98714e | 1654 | uint64_t batch_obj_vm_offset; |
5f19e2bf JH |
1655 | struct intel_engine_cs *ring; |
1656 | struct drm_i915_gem_object *batch_obj; | |
1657 | struct intel_context *ctx; | |
6a6ae79a | 1658 | struct drm_i915_gem_request *request; |
5f19e2bf JH |
1659 | }; |
1660 | ||
aa363136 MR |
1661 | /* used in computing the new watermarks state */ |
1662 | struct intel_wm_config { | |
1663 | unsigned int num_pipes_active; | |
1664 | bool sprites_enabled; | |
1665 | bool sprites_scaled; | |
1666 | }; | |
1667 | ||
77fec556 | 1668 | struct drm_i915_private { |
f4c956ad | 1669 | struct drm_device *dev; |
efab6d8d | 1670 | struct kmem_cache *objects; |
e20d2ab7 | 1671 | struct kmem_cache *vmas; |
efab6d8d | 1672 | struct kmem_cache *requests; |
f4c956ad | 1673 | |
5c969aa7 | 1674 | const struct intel_device_info info; |
f4c956ad DV |
1675 | |
1676 | int relative_constants_mode; | |
1677 | ||
1678 | void __iomem *regs; | |
1679 | ||
907b28c5 | 1680 | struct intel_uncore uncore; |
f4c956ad | 1681 | |
cf9d2890 YZ |
1682 | struct i915_virtual_gpu vgpu; |
1683 | ||
33a732f4 AD |
1684 | struct intel_guc guc; |
1685 | ||
eb805623 DV |
1686 | struct intel_csr csr; |
1687 | ||
5ea6e5e3 | 1688 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1689 | |
f4c956ad DV |
1690 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1691 | * controller on different i2c buses. */ | |
1692 | struct mutex gmbus_mutex; | |
1693 | ||
1694 | /** | |
1695 | * Base address of the gmbus and gpio block. | |
1696 | */ | |
1697 | uint32_t gpio_mmio_base; | |
1698 | ||
b6fdd0f2 SS |
1699 | /* MMIO base address for MIPI regs */ |
1700 | uint32_t mipi_mmio_base; | |
1701 | ||
443a389f VS |
1702 | uint32_t psr_mmio_base; |
1703 | ||
28c70f16 DV |
1704 | wait_queue_head_t gmbus_wait_queue; |
1705 | ||
f4c956ad | 1706 | struct pci_dev *bridge_dev; |
a4872ba6 | 1707 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1708 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1709 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1710 | |
ba8286fa | 1711 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1712 | struct resource mch_res; |
1713 | ||
f4c956ad DV |
1714 | /* protects the irq masks */ |
1715 | spinlock_t irq_lock; | |
1716 | ||
84c33a64 SG |
1717 | /* protects the mmio flip data */ |
1718 | spinlock_t mmio_flip_lock; | |
1719 | ||
f8b79e58 ID |
1720 | bool display_irqs_enabled; |
1721 | ||
9ee32fea DV |
1722 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1723 | struct pm_qos_request pm_qos; | |
1724 | ||
a580516d VS |
1725 | /* Sideband mailbox protection */ |
1726 | struct mutex sb_lock; | |
f4c956ad DV |
1727 | |
1728 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1729 | union { |
1730 | u32 irq_mask; | |
1731 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1732 | }; | |
f4c956ad | 1733 | u32 gt_irq_mask; |
605cd25b | 1734 | u32 pm_irq_mask; |
a6706b45 | 1735 | u32 pm_rps_events; |
91d181dd | 1736 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1737 | |
5fcece80 | 1738 | struct i915_hotplug hotplug; |
ab34a7e8 | 1739 | struct intel_fbc fbc; |
439d7ac0 | 1740 | struct i915_drrs drrs; |
f4c956ad | 1741 | struct intel_opregion opregion; |
41aa3448 | 1742 | struct intel_vbt_data vbt; |
f4c956ad | 1743 | |
d9ceb816 JB |
1744 | bool preserve_bios_swizzle; |
1745 | ||
f4c956ad DV |
1746 | /* overlay */ |
1747 | struct intel_overlay *overlay; | |
f4c956ad | 1748 | |
58c68779 | 1749 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1750 | struct mutex backlight_lock; |
31ad8ec6 | 1751 | |
f4c956ad | 1752 | /* LVDS info */ |
f4c956ad DV |
1753 | bool no_aux_handshake; |
1754 | ||
e39b999a VS |
1755 | /* protects panel power sequencer state */ |
1756 | struct mutex pps_mutex; | |
1757 | ||
f4c956ad | 1758 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1759 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1760 | ||
1761 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
5d96d8af | 1762 | unsigned int skl_boot_cdclk; |
1a617b77 | 1763 | unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; |
adafdc6f | 1764 | unsigned int max_dotclk_freq; |
e7dc33f3 | 1765 | unsigned int rawclk_freq; |
6bcda4f0 | 1766 | unsigned int hpll_freq; |
bfa7df01 | 1767 | unsigned int czclk_freq; |
f4c956ad | 1768 | |
645416f5 DV |
1769 | /** |
1770 | * wq - Driver workqueue for GEM. | |
1771 | * | |
1772 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1773 | * locks, for otherwise the flushing done in the pageflip code will | |
1774 | * result in deadlocks. | |
1775 | */ | |
f4c956ad DV |
1776 | struct workqueue_struct *wq; |
1777 | ||
1778 | /* Display functions */ | |
1779 | struct drm_i915_display_funcs display; | |
1780 | ||
1781 | /* PCH chipset type */ | |
1782 | enum intel_pch pch_type; | |
17a303ec | 1783 | unsigned short pch_id; |
f4c956ad DV |
1784 | |
1785 | unsigned long quirks; | |
1786 | ||
b8efb17b ZR |
1787 | enum modeset_restore modeset_restore; |
1788 | struct mutex modeset_restore_lock; | |
e2c8b870 | 1789 | struct drm_atomic_state *modeset_restore_state; |
673a394b | 1790 | |
a7bbbd63 | 1791 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1792 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1793 | |
4b5aed62 | 1794 | struct i915_gem_mm mm; |
ad46cb53 CW |
1795 | DECLARE_HASHTABLE(mm_structs, 7); |
1796 | struct mutex mm_lock; | |
8781342d | 1797 | |
8781342d DV |
1798 | /* Kernel Modesetting */ |
1799 | ||
9b9d172d | 1800 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1801 | |
76c4ac04 DL |
1802 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1803 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1804 | wait_queue_head_t pending_flip_queue; |
1805 | ||
c4597872 DV |
1806 | #ifdef CONFIG_DEBUG_FS |
1807 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1808 | #endif | |
1809 | ||
565602d7 | 1810 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
1811 | int num_shared_dpll; |
1812 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 1813 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 ML |
1814 | |
1815 | unsigned int active_crtcs; | |
1816 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
1817 | ||
e4607fcf | 1818 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1819 | |
7225342a | 1820 | struct i915_workarounds workarounds; |
888b5995 | 1821 | |
652c393a JB |
1822 | /* Reclocking support */ |
1823 | bool render_reclock_avail; | |
f99d7069 DV |
1824 | |
1825 | struct i915_frontbuffer_tracking fb_tracking; | |
1826 | ||
652c393a | 1827 | u16 orig_clock; |
f97108d1 | 1828 | |
c4804411 | 1829 | bool mchbar_need_disable; |
f97108d1 | 1830 | |
a4da4fa4 DV |
1831 | struct intel_l3_parity l3_parity; |
1832 | ||
59124506 BW |
1833 | /* Cannot be determined by PCIID. You must always read a register. */ |
1834 | size_t ellc_size; | |
1835 | ||
c6a828d3 | 1836 | /* gen6+ rps state */ |
c85aa885 | 1837 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1838 | |
20e4d407 DV |
1839 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1840 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1841 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1842 | |
83c00f55 | 1843 | struct i915_power_domains power_domains; |
a38911a3 | 1844 | |
a031d709 | 1845 | struct i915_psr psr; |
3f51e471 | 1846 | |
99584db3 | 1847 | struct i915_gpu_error gpu_error; |
ae681d96 | 1848 | |
c9cddffc JB |
1849 | struct drm_i915_gem_object *vlv_pctx; |
1850 | ||
0695726e | 1851 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
1852 | /* list of fbdev register on this device */ |
1853 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1854 | struct work_struct fbdev_suspend_work; |
4520f53a | 1855 | #endif |
e953fd7b CW |
1856 | |
1857 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1858 | struct drm_property *force_audio_property; |
e3689190 | 1859 | |
58fddc28 | 1860 | /* hda/i915 audio component */ |
51e1d83c | 1861 | struct i915_audio_component *audio_component; |
58fddc28 | 1862 | bool audio_component_registered; |
4a21ef7d LY |
1863 | /** |
1864 | * av_mutex - mutex for audio/video sync | |
1865 | * | |
1866 | */ | |
1867 | struct mutex av_mutex; | |
58fddc28 | 1868 | |
254f965c | 1869 | uint32_t hw_context_size; |
a33afea5 | 1870 | struct list_head context_list; |
f4c956ad | 1871 | |
3e68320e | 1872 | u32 fdi_rx_config; |
68d18ad7 | 1873 | |
70722468 VS |
1874 | u32 chv_phy_control; |
1875 | ||
842f1c8b | 1876 | u32 suspend_count; |
bc87229f | 1877 | bool suspended_to_idle; |
f4c956ad | 1878 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1879 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1880 | |
53615a5e VS |
1881 | struct { |
1882 | /* | |
1883 | * Raw watermark latency values: | |
1884 | * in 0.1us units for WM0, | |
1885 | * in 0.5us units for WM1+. | |
1886 | */ | |
1887 | /* primary */ | |
1888 | uint16_t pri_latency[5]; | |
1889 | /* sprite */ | |
1890 | uint16_t spr_latency[5]; | |
1891 | /* cursor */ | |
1892 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1893 | /* |
1894 | * Raw watermark memory latency values | |
1895 | * for SKL for all 8 levels | |
1896 | * in 1us units. | |
1897 | */ | |
1898 | uint16_t skl_latency[8]; | |
609cedef | 1899 | |
aa363136 MR |
1900 | /* Committed wm config */ |
1901 | struct intel_wm_config config; | |
1902 | ||
2d41c0b5 PB |
1903 | /* |
1904 | * The skl_wm_values structure is a bit too big for stack | |
1905 | * allocation, so we keep the staging struct where we store | |
1906 | * intermediate results here instead. | |
1907 | */ | |
1908 | struct skl_wm_values skl_results; | |
1909 | ||
609cedef | 1910 | /* current hardware state */ |
2d41c0b5 PB |
1911 | union { |
1912 | struct ilk_wm_values hw; | |
1913 | struct skl_wm_values skl_hw; | |
0018fda1 | 1914 | struct vlv_wm_values vlv; |
2d41c0b5 | 1915 | }; |
58590c14 VS |
1916 | |
1917 | uint8_t max_level; | |
ed4a6a7c MR |
1918 | |
1919 | /* | |
1920 | * Should be held around atomic WM register writing; also | |
1921 | * protects * intel_crtc->wm.active and | |
1922 | * cstate->wm.need_postvbl_update. | |
1923 | */ | |
1924 | struct mutex wm_mutex; | |
53615a5e VS |
1925 | } wm; |
1926 | ||
8a187455 PZ |
1927 | struct i915_runtime_pm pm; |
1928 | ||
a83014d3 OM |
1929 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1930 | struct { | |
5f19e2bf | 1931 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
f3dc74c0 | 1932 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1933 | struct list_head *vmas); |
a83014d3 OM |
1934 | int (*init_rings)(struct drm_device *dev); |
1935 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1936 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1937 | } gt; | |
1938 | ||
ed54c1a1 DG |
1939 | struct intel_context *kernel_context; |
1940 | ||
9e458034 SJ |
1941 | bool edp_low_vswing; |
1942 | ||
3be60de9 VS |
1943 | /* perform PHY state sanity checks? */ |
1944 | bool chv_phy_assert[2]; | |
1945 | ||
0bdf5a05 TI |
1946 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
1947 | ||
bdf1e7e3 DV |
1948 | /* |
1949 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1950 | * will be rejected. Instead look for a better place. | |
1951 | */ | |
77fec556 | 1952 | }; |
1da177e4 | 1953 | |
2c1792a1 CW |
1954 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1955 | { | |
1956 | return dev->dev_private; | |
1957 | } | |
1958 | ||
888d0d42 ID |
1959 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
1960 | { | |
1961 | return to_i915(dev_get_drvdata(dev)); | |
1962 | } | |
1963 | ||
33a732f4 AD |
1964 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
1965 | { | |
1966 | return container_of(guc, struct drm_i915_private, guc); | |
1967 | } | |
1968 | ||
b4519513 CW |
1969 | /* Iterate over initialised rings */ |
1970 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1971 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
95150bdf | 1972 | for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))) |
b4519513 | 1973 | |
b1d7e4b4 WF |
1974 | enum hdmi_force_audio { |
1975 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1976 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1977 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1978 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1979 | }; | |
1980 | ||
190d6cd5 | 1981 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1982 | |
37e680a1 | 1983 | struct drm_i915_gem_object_ops { |
de472664 CW |
1984 | unsigned int flags; |
1985 | #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 | |
1986 | ||
37e680a1 CW |
1987 | /* Interface between the GEM object and its backing storage. |
1988 | * get_pages() is called once prior to the use of the associated set | |
1989 | * of pages before to binding them into the GTT, and put_pages() is | |
1990 | * called after we no longer need them. As we expect there to be | |
1991 | * associated cost with migrating pages between the backing storage | |
1992 | * and making them available for the GPU (e.g. clflush), we may hold | |
1993 | * onto the pages after they are no longer referenced by the GPU | |
1994 | * in case they may be used again shortly (for example migrating the | |
1995 | * pages to a different memory domain within the GTT). put_pages() | |
1996 | * will therefore most likely be called when the object itself is | |
1997 | * being released or under memory pressure (where we attempt to | |
1998 | * reap pages for the shrinker). | |
1999 | */ | |
2000 | int (*get_pages)(struct drm_i915_gem_object *); | |
2001 | void (*put_pages)(struct drm_i915_gem_object *); | |
de472664 | 2002 | |
5cc9ed4b CW |
2003 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2004 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
2005 | }; |
2006 | ||
a071fa00 DV |
2007 | /* |
2008 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2009 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2010 | * doesn't mean that the hw necessarily already scans it out, but that any |
2011 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2012 | * | |
2013 | * We have one bit per pipe and per scanout plane type. | |
2014 | */ | |
d1b9d039 SAK |
2015 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2016 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2017 | #define INTEL_FRONTBUFFER_BITS \ |
2018 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
2019 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
2020 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2021 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2022 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2023 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2024 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2025 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2026 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2027 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2028 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2029 | |
673a394b | 2030 | struct drm_i915_gem_object { |
c397b908 | 2031 | struct drm_gem_object base; |
673a394b | 2032 | |
37e680a1 CW |
2033 | const struct drm_i915_gem_object_ops *ops; |
2034 | ||
2f633156 BW |
2035 | /** List of VMAs backed by this object */ |
2036 | struct list_head vma_list; | |
2037 | ||
c1ad11fc CW |
2038 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2039 | struct drm_mm_node *stolen; | |
35c20a60 | 2040 | struct list_head global_list; |
673a394b | 2041 | |
b4716185 | 2042 | struct list_head ring_list[I915_NUM_RINGS]; |
b25cb2f8 BW |
2043 | /** Used in execbuf to temporarily hold a ref */ |
2044 | struct list_head obj_exec_link; | |
673a394b | 2045 | |
8d9d5744 | 2046 | struct list_head batch_pool_link; |
493018dc | 2047 | |
673a394b | 2048 | /** |
65ce3027 CW |
2049 | * This is set if the object is on the active lists (has pending |
2050 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2051 | * inactive (ready to be unbound) list. | |
673a394b | 2052 | */ |
b4716185 | 2053 | unsigned int active:I915_NUM_RINGS; |
673a394b EA |
2054 | |
2055 | /** | |
2056 | * This is set if the object has been written to since last bound | |
2057 | * to the GTT | |
2058 | */ | |
0206e353 | 2059 | unsigned int dirty:1; |
778c3544 DV |
2060 | |
2061 | /** | |
2062 | * Fence register bits (if any) for this object. Will be set | |
2063 | * as needed when mapped into the GTT. | |
2064 | * Protected by dev->struct_mutex. | |
778c3544 | 2065 | */ |
4b9de737 | 2066 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 2067 | |
778c3544 DV |
2068 | /** |
2069 | * Advice: are the backing pages purgeable? | |
2070 | */ | |
0206e353 | 2071 | unsigned int madv:2; |
778c3544 | 2072 | |
778c3544 DV |
2073 | /** |
2074 | * Current tiling mode for the object. | |
2075 | */ | |
0206e353 | 2076 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
2077 | /** |
2078 | * Whether the tiling parameters for the currently associated fence | |
2079 | * register have changed. Note that for the purposes of tracking | |
2080 | * tiling changes we also treat the unfenced register, the register | |
2081 | * slot that the object occupies whilst it executes a fenced | |
2082 | * command (such as BLT on gen2/3), as a "fence". | |
2083 | */ | |
2084 | unsigned int fence_dirty:1; | |
778c3544 | 2085 | |
75e9e915 DV |
2086 | /** |
2087 | * Is the object at the current location in the gtt mappable and | |
2088 | * fenceable? Used to avoid costly recalculations. | |
2089 | */ | |
0206e353 | 2090 | unsigned int map_and_fenceable:1; |
75e9e915 | 2091 | |
fb7d516a DV |
2092 | /** |
2093 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2094 | * mappable by accident). Track pin and fault separate for a more | |
2095 | * accurate mappable working set. | |
2096 | */ | |
0206e353 | 2097 | unsigned int fault_mappable:1; |
fb7d516a | 2098 | |
24f3a8cf AG |
2099 | /* |
2100 | * Is the object to be mapped as read-only to the GPU | |
2101 | * Only honoured if hardware has relevant pte bit | |
2102 | */ | |
2103 | unsigned long gt_ro:1; | |
651d794f | 2104 | unsigned int cache_level:3; |
0f71979a | 2105 | unsigned int cache_dirty:1; |
93dfb40c | 2106 | |
a071fa00 DV |
2107 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2108 | ||
8a0c39b1 TU |
2109 | unsigned int pin_display; |
2110 | ||
9da3da66 | 2111 | struct sg_table *pages; |
a5570178 | 2112 | int pages_pin_count; |
ee286370 CW |
2113 | struct get_page { |
2114 | struct scatterlist *sg; | |
2115 | int last; | |
2116 | } get_page; | |
673a394b | 2117 | |
1286ff73 | 2118 | /* prime dma-buf support */ |
9a70cc2a DA |
2119 | void *dma_buf_vmapping; |
2120 | int vmapping_count; | |
2121 | ||
b4716185 CW |
2122 | /** Breadcrumb of last rendering to the buffer. |
2123 | * There can only be one writer, but we allow for multiple readers. | |
2124 | * If there is a writer that necessarily implies that all other | |
2125 | * read requests are complete - but we may only be lazily clearing | |
2126 | * the read requests. A read request is naturally the most recent | |
2127 | * request on a ring, so we may have two different write and read | |
2128 | * requests on one ring where the write request is older than the | |
2129 | * read request. This allows for the CPU to read from an active | |
2130 | * buffer by only waiting for the write to complete. | |
2131 | * */ | |
2132 | struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; | |
97b2a6a1 | 2133 | struct drm_i915_gem_request *last_write_req; |
caea7476 | 2134 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 2135 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 2136 | |
778c3544 | 2137 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 2138 | uint32_t stride; |
673a394b | 2139 | |
80075d49 DV |
2140 | /** References from framebuffers, locks out tiling changes. */ |
2141 | unsigned long framebuffer_references; | |
2142 | ||
280b713b | 2143 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2144 | unsigned long *bit_17; |
280b713b | 2145 | |
5cc9ed4b | 2146 | union { |
6a2c4232 CW |
2147 | /** for phy allocated objects */ |
2148 | struct drm_dma_handle *phys_handle; | |
2149 | ||
5cc9ed4b CW |
2150 | struct i915_gem_userptr { |
2151 | uintptr_t ptr; | |
2152 | unsigned read_only :1; | |
2153 | unsigned workers :4; | |
2154 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2155 | ||
ad46cb53 CW |
2156 | struct i915_mm_struct *mm; |
2157 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2158 | struct work_struct *work; |
2159 | } userptr; | |
2160 | }; | |
2161 | }; | |
62b8b215 | 2162 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 2163 | |
a071fa00 DV |
2164 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2165 | struct drm_i915_gem_object *new, | |
2166 | unsigned frontbuffer_bits); | |
2167 | ||
673a394b EA |
2168 | /** |
2169 | * Request queue structure. | |
2170 | * | |
2171 | * The request queue allows us to note sequence numbers that have been emitted | |
2172 | * and may be associated with active buffers to be retired. | |
2173 | * | |
97b2a6a1 JH |
2174 | * By keeping this list, we can avoid having to do questionable sequence |
2175 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2176 | * emission time to be associated with the request for tracking how far ahead | |
2177 | * of the GPU the submission is. | |
b3a38998 NH |
2178 | * |
2179 | * The requests are reference counted, so upon creation they should have an | |
2180 | * initial reference taken using kref_init | |
673a394b EA |
2181 | */ |
2182 | struct drm_i915_gem_request { | |
abfe262a JH |
2183 | struct kref ref; |
2184 | ||
852835f3 | 2185 | /** On Which ring this request was generated */ |
efab6d8d | 2186 | struct drm_i915_private *i915; |
a4872ba6 | 2187 | struct intel_engine_cs *ring; |
852835f3 | 2188 | |
821485dc CW |
2189 | /** GEM sequence number associated with the previous request, |
2190 | * when the HWS breadcrumb is equal to this the GPU is processing | |
2191 | * this request. | |
2192 | */ | |
2193 | u32 previous_seqno; | |
2194 | ||
2195 | /** GEM sequence number associated with this request, | |
2196 | * when the HWS breadcrumb is equal or greater than this the GPU | |
2197 | * has finished processing this request. | |
2198 | */ | |
2199 | u32 seqno; | |
673a394b | 2200 | |
7d736f4f MK |
2201 | /** Position in the ringbuffer of the start of the request */ |
2202 | u32 head; | |
2203 | ||
72f95afa NH |
2204 | /** |
2205 | * Position in the ringbuffer of the start of the postfix. | |
2206 | * This is required to calculate the maximum available ringbuffer | |
2207 | * space without overwriting the postfix. | |
2208 | */ | |
2209 | u32 postfix; | |
2210 | ||
2211 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2212 | u32 tail; |
2213 | ||
b3a38998 | 2214 | /** |
a8c6ecb3 | 2215 | * Context and ring buffer related to this request |
b3a38998 NH |
2216 | * Contexts are refcounted, so when this request is associated with a |
2217 | * context, we must increment the context's refcount, to guarantee that | |
2218 | * it persists while any request is linked to it. Requests themselves | |
2219 | * are also refcounted, so the request will only be freed when the last | |
2220 | * reference to it is dismissed, and the code in | |
2221 | * i915_gem_request_free() will then decrement the refcount on the | |
2222 | * context. | |
2223 | */ | |
273497e5 | 2224 | struct intel_context *ctx; |
98e1bd4a | 2225 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2226 | |
dc4be607 JH |
2227 | /** Batch buffer related to this request if any (used for |
2228 | error state dump only) */ | |
7d736f4f MK |
2229 | struct drm_i915_gem_object *batch_obj; |
2230 | ||
673a394b EA |
2231 | /** Time at which this request was emitted, in jiffies. */ |
2232 | unsigned long emitted_jiffies; | |
2233 | ||
b962442e | 2234 | /** global list entry for this request */ |
673a394b | 2235 | struct list_head list; |
b962442e | 2236 | |
f787a5f5 | 2237 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2238 | /** file_priv list entry for this request */ |
2239 | struct list_head client_list; | |
67e2937b | 2240 | |
071c92de MK |
2241 | /** process identifier submitting this request */ |
2242 | struct pid *pid; | |
2243 | ||
6d3d8274 NH |
2244 | /** |
2245 | * The ELSP only accepts two elements at a time, so we queue | |
2246 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2247 | * hardware is available. The queue serves a double purpose: we also use | |
2248 | * it to keep track of the up to 2 contexts currently in the hardware | |
2249 | * (usually one in execution and the other queued up by the GPU): We | |
2250 | * only remove elements from the head of the queue when the hardware | |
2251 | * informs us that an element has been completed. | |
2252 | * | |
2253 | * All accesses to the queue are mediated by a spinlock | |
2254 | * (ring->execlist_lock). | |
2255 | */ | |
2256 | ||
2257 | /** Execlist link in the submission queue.*/ | |
2258 | struct list_head execlist_link; | |
2259 | ||
2260 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2261 | int elsp_submitted; | |
2262 | ||
673a394b EA |
2263 | }; |
2264 | ||
26827088 DG |
2265 | struct drm_i915_gem_request * __must_check |
2266 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
2267 | struct intel_context *ctx); | |
29b1b415 | 2268 | void i915_gem_request_cancel(struct drm_i915_gem_request *req); |
abfe262a | 2269 | void i915_gem_request_free(struct kref *req_ref); |
fcfa423c JH |
2270 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
2271 | struct drm_file *file); | |
abfe262a | 2272 | |
b793a00a JH |
2273 | static inline uint32_t |
2274 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2275 | { | |
2276 | return req ? req->seqno : 0; | |
2277 | } | |
2278 | ||
2279 | static inline struct intel_engine_cs * | |
2280 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2281 | { | |
2282 | return req ? req->ring : NULL; | |
2283 | } | |
2284 | ||
b2cfe0ab | 2285 | static inline struct drm_i915_gem_request * |
abfe262a JH |
2286 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2287 | { | |
b2cfe0ab CW |
2288 | if (req) |
2289 | kref_get(&req->ref); | |
2290 | return req; | |
abfe262a JH |
2291 | } |
2292 | ||
2293 | static inline void | |
2294 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2295 | { | |
f245860e | 2296 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
abfe262a JH |
2297 | kref_put(&req->ref, i915_gem_request_free); |
2298 | } | |
2299 | ||
41037f9f CW |
2300 | static inline void |
2301 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) | |
2302 | { | |
b833bb61 ML |
2303 | struct drm_device *dev; |
2304 | ||
2305 | if (!req) | |
2306 | return; | |
41037f9f | 2307 | |
b833bb61 ML |
2308 | dev = req->ring->dev; |
2309 | if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) | |
41037f9f | 2310 | mutex_unlock(&dev->struct_mutex); |
41037f9f CW |
2311 | } |
2312 | ||
abfe262a JH |
2313 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
2314 | struct drm_i915_gem_request *src) | |
2315 | { | |
2316 | if (src) | |
2317 | i915_gem_request_reference(src); | |
2318 | ||
2319 | if (*pdst) | |
2320 | i915_gem_request_unreference(*pdst); | |
2321 | ||
2322 | *pdst = src; | |
2323 | } | |
2324 | ||
1b5a433a JH |
2325 | /* |
2326 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2327 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2328 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2329 | */ | |
2330 | ||
351e3db2 BV |
2331 | /* |
2332 | * A command that requires special handling by the command parser. | |
2333 | */ | |
2334 | struct drm_i915_cmd_descriptor { | |
2335 | /* | |
2336 | * Flags describing how the command parser processes the command. | |
2337 | * | |
2338 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2339 | * a length mask if not set | |
2340 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2341 | * standard length encoding for the opcode range in | |
2342 | * which it falls | |
2343 | * CMD_DESC_REJECT: The command is never allowed | |
2344 | * CMD_DESC_REGISTER: The command should be checked against the | |
2345 | * register whitelist for the appropriate ring | |
2346 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2347 | * is the DRM master | |
2348 | */ | |
2349 | u32 flags; | |
2350 | #define CMD_DESC_FIXED (1<<0) | |
2351 | #define CMD_DESC_SKIP (1<<1) | |
2352 | #define CMD_DESC_REJECT (1<<2) | |
2353 | #define CMD_DESC_REGISTER (1<<3) | |
2354 | #define CMD_DESC_BITMASK (1<<4) | |
2355 | #define CMD_DESC_MASTER (1<<5) | |
2356 | ||
2357 | /* | |
2358 | * The command's unique identification bits and the bitmask to get them. | |
2359 | * This isn't strictly the opcode field as defined in the spec and may | |
2360 | * also include type, subtype, and/or subop fields. | |
2361 | */ | |
2362 | struct { | |
2363 | u32 value; | |
2364 | u32 mask; | |
2365 | } cmd; | |
2366 | ||
2367 | /* | |
2368 | * The command's length. The command is either fixed length (i.e. does | |
2369 | * not include a length field) or has a length field mask. The flag | |
2370 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2371 | * a length mask. All command entries in a command table must include | |
2372 | * length information. | |
2373 | */ | |
2374 | union { | |
2375 | u32 fixed; | |
2376 | u32 mask; | |
2377 | } length; | |
2378 | ||
2379 | /* | |
2380 | * Describes where to find a register address in the command to check | |
2381 | * against the ring's register whitelist. Only valid if flags has the | |
2382 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2383 | * |
2384 | * A non-zero step value implies that the command may access multiple | |
2385 | * registers in sequence (e.g. LRI), in that case step gives the | |
2386 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2387 | */ |
2388 | struct { | |
2389 | u32 offset; | |
2390 | u32 mask; | |
6a65c5b9 | 2391 | u32 step; |
351e3db2 BV |
2392 | } reg; |
2393 | ||
2394 | #define MAX_CMD_DESC_BITMASKS 3 | |
2395 | /* | |
2396 | * Describes command checks where a particular dword is masked and | |
2397 | * compared against an expected value. If the command does not match | |
2398 | * the expected value, the parser rejects it. Only valid if flags has | |
2399 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2400 | * are valid. | |
d4d48035 BV |
2401 | * |
2402 | * If the check specifies a non-zero condition_mask then the parser | |
2403 | * only performs the check when the bits specified by condition_mask | |
2404 | * are non-zero. | |
351e3db2 BV |
2405 | */ |
2406 | struct { | |
2407 | u32 offset; | |
2408 | u32 mask; | |
2409 | u32 expected; | |
d4d48035 BV |
2410 | u32 condition_offset; |
2411 | u32 condition_mask; | |
351e3db2 BV |
2412 | } bits[MAX_CMD_DESC_BITMASKS]; |
2413 | }; | |
2414 | ||
2415 | /* | |
2416 | * A table of commands requiring special handling by the command parser. | |
2417 | * | |
2418 | * Each ring has an array of tables. Each table consists of an array of command | |
2419 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2420 | */ | |
2421 | struct drm_i915_cmd_table { | |
2422 | const struct drm_i915_cmd_descriptor *table; | |
2423 | int count; | |
2424 | }; | |
2425 | ||
dbbe9127 | 2426 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2427 | #define __I915__(p) ({ \ |
2428 | struct drm_i915_private *__p; \ | |
2429 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2430 | __p = (struct drm_i915_private *)p; \ | |
2431 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2432 | __p = to_i915((struct drm_device *)p); \ | |
2433 | else \ | |
2434 | BUILD_BUG(); \ | |
2435 | __p; \ | |
2436 | }) | |
dbbe9127 | 2437 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2438 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
e90a21d4 | 2439 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
cae5852d | 2440 | |
e87a005d JN |
2441 | #define REVID_FOREVER 0xff |
2442 | /* | |
2443 | * Return true if revision is in range [since,until] inclusive. | |
2444 | * | |
2445 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2446 | */ | |
2447 | #define IS_REVID(p, since, until) \ | |
2448 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2449 | ||
87f1f465 CW |
2450 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2451 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2452 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2453 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2454 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2455 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2456 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2457 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2458 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2459 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2460 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2461 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2462 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2463 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2464 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2465 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2466 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2467 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2468 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2469 | INTEL_DEVID(dev) == 0x0152 || \ | |
2470 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2471 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
666a4537 | 2472 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
4cae9ae0 | 2473 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
666a4537 | 2474 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev)) |
7201c0b3 | 2475 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
7526ac19 | 2476 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
ef11bdb3 | 2477 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
cae5852d | 2478 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2479 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2480 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2481 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2482 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2483 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2484 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2485 | /* ULX machines are also considered ULT. */ |
2486 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2487 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2488 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2489 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2490 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2491 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2492 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2493 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2494 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2495 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2496 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2497 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2498 | INTEL_DEVID(dev) == 0x1913 || \ | |
2499 | INTEL_DEVID(dev) == 0x1916 || \ | |
2500 | INTEL_DEVID(dev) == 0x1921 || \ | |
2501 | INTEL_DEVID(dev) == 0x1926) | |
2502 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2503 | INTEL_DEVID(dev) == 0x1915 || \ | |
2504 | INTEL_DEVID(dev) == 0x191E) | |
a5b7991c RV |
2505 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
2506 | INTEL_DEVID(dev) == 0x5913 || \ | |
2507 | INTEL_DEVID(dev) == 0x5916 || \ | |
2508 | INTEL_DEVID(dev) == 0x5921 || \ | |
2509 | INTEL_DEVID(dev) == 0x5926) | |
2510 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ | |
2511 | INTEL_DEVID(dev) == 0x5915 || \ | |
2512 | INTEL_DEVID(dev) == 0x591E) | |
7a58bad0 SAK |
2513 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2514 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2515 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2516 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2517 | ||
b833d685 | 2518 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2519 | |
ef712bb4 JN |
2520 | #define SKL_REVID_A0 0x0 |
2521 | #define SKL_REVID_B0 0x1 | |
2522 | #define SKL_REVID_C0 0x2 | |
2523 | #define SKL_REVID_D0 0x3 | |
2524 | #define SKL_REVID_E0 0x4 | |
2525 | #define SKL_REVID_F0 0x5 | |
2526 | ||
e87a005d JN |
2527 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2528 | ||
ef712bb4 | 2529 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2530 | #define BXT_REVID_A1 0x1 |
ef712bb4 JN |
2531 | #define BXT_REVID_B0 0x3 |
2532 | #define BXT_REVID_C0 0x9 | |
6c74c87f | 2533 | |
e87a005d JN |
2534 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2535 | ||
85436696 JB |
2536 | /* |
2537 | * The genX designation typically refers to the render engine, so render | |
2538 | * capability related checks should use IS_GEN, while display and other checks | |
2539 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2540 | * chips, etc.). | |
2541 | */ | |
cae5852d ZN |
2542 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2543 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2544 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2545 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2546 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2547 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2548 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2549 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2550 | |
73ae478c BW |
2551 | #define RENDER_RING (1<<RCS) |
2552 | #define BSD_RING (1<<VCS) | |
2553 | #define BLT_RING (1<<BCS) | |
2554 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2555 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2556 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2557 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2558 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2559 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2560 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
ca377809 | 2561 | #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) |
63c42e56 | 2562 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ |
f2fbc690 | 2563 | __I915__(dev)->ellc_size) |
cae5852d ZN |
2564 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2565 | ||
254f965c | 2566 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2567 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c | 2568 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2569 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2570 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2571 | |
05394f39 | 2572 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2573 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2574 | ||
b45305fc DV |
2575 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2576 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
06e668ac MK |
2577 | |
2578 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
2579 | #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \ | |
2580 | ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \ | |
2581 | IS_SKL_REVID(dev, 0, SKL_REVID_F0))) | |
4e6b788c DV |
2582 | /* |
2583 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2584 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2585 | * legacy irq no. is shared with another device. The kernel then disables that | |
2586 | * interrupt source and so prevents the other device from working properly. | |
2587 | */ | |
2588 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2589 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2590 | |
cae5852d ZN |
2591 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2592 | * rows, which changed the alignment requirements and fence programming. | |
2593 | */ | |
2594 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2595 | IS_I915GM(dev))) | |
cae5852d ZN |
2596 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2597 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2598 | |
2599 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2600 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2601 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2602 | |
dbf7786e | 2603 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2604 | |
0c9b3715 JN |
2605 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2606 | INTEL_INFO(dev)->gen >= 9) | |
2607 | ||
dd93be58 | 2608 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2609 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2610 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 | 2611 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
ef11bdb3 | 2612 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
6157d3c8 | 2613 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 | 2614 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
666a4537 WB |
2615 | IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \ |
2616 | IS_KABYLAKE(dev)) | |
58abf1da RV |
2617 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2618 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2619 | |
7b403ffb | 2620 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
eb805623 | 2621 | |
2b81b844 RV |
2622 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) |
2623 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) | |
33a732f4 | 2624 | |
a9ed33ca AJ |
2625 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2626 | INTEL_INFO(dev)->gen >= 8) | |
2627 | ||
97d3308a | 2628 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
666a4537 WB |
2629 | !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ |
2630 | !IS_BROXTON(dev)) | |
97d3308a | 2631 | |
17a303ec PZ |
2632 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2633 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2634 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2635 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2636 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2637 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2638 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2639 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
30c964a6 | 2640 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
39bfcd52 | 2641 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2642 | |
f2fbc690 | 2643 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2644 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2645 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
c2699524 | 2646 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
56f5f700 | 2647 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
cae5852d ZN |
2648 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2649 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2650 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2651 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2652 | |
666a4537 WB |
2653 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ |
2654 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
5fafe292 | 2655 | |
040d2baa BW |
2656 | /* DPF == dynamic parity feature */ |
2657 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2658 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2659 | |
c8735b0c | 2660 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2661 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2662 | |
05394f39 CW |
2663 | #include "i915_trace.h" |
2664 | ||
baa70943 | 2665 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2666 | extern int i915_max_ioctl; |
2667 | ||
1751fcf9 ML |
2668 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2669 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2670 | |
c838d719 | 2671 | /* i915_dma.c */ |
22eae947 | 2672 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2673 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2674 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2675 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2676 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2677 | struct drm_file *file); |
673a394b | 2678 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2679 | struct drm_file *file); |
c43b5634 | 2680 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2681 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2682 | unsigned long arg); | |
c43b5634 | 2683 | #endif |
8e96d9c4 | 2684 | extern int intel_gpu_reset(struct drm_device *dev); |
49e4d842 | 2685 | extern bool intel_has_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2686 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2687 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2688 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2689 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2690 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2691 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2692 | |
77913b39 JN |
2693 | /* intel_hotplug.c */ |
2694 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); | |
2695 | void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2696 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2697 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2698 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
77913b39 | 2699 | |
1da177e4 | 2700 | /* i915_irq.c */ |
10cd45b6 | 2701 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2702 | __printf(3, 4) |
2703 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2704 | const char *fmt, ...); | |
1da177e4 | 2705 | |
b963291c | 2706 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2707 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2708 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2709 | |
2710 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2711 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2712 | bool restore_forcewake); | |
907b28c5 | 2713 | extern void intel_uncore_init(struct drm_device *dev); |
fc97618b | 2714 | extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); |
bc3b9346 | 2715 | extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); |
aec347ab | 2716 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2717 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
48c1026a | 2718 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2719 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2720 | enum forcewake_domains domains); |
59bad947 | 2721 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2722 | enum forcewake_domains domains); |
a6111f7b CW |
2723 | /* Like above but the caller must manage the uncore.lock itself. |
2724 | * Must be used with I915_READ_FW and friends. | |
2725 | */ | |
2726 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2727 | enum forcewake_domains domains); | |
2728 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2729 | enum forcewake_domains domains); | |
59bad947 | 2730 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
cf9d2890 YZ |
2731 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2732 | { | |
2733 | return to_i915(dev)->vgpu.active; | |
2734 | } | |
b1f14ad0 | 2735 | |
7c463586 | 2736 | void |
50227e1c | 2737 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2738 | u32 status_mask); |
7c463586 KP |
2739 | |
2740 | void | |
50227e1c | 2741 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2742 | u32 status_mask); |
7c463586 | 2743 | |
f8b79e58 ID |
2744 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2745 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2746 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2747 | uint32_t mask, | |
2748 | uint32_t bits); | |
fbdedaea VS |
2749 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2750 | uint32_t interrupt_mask, | |
2751 | uint32_t enabled_irq_mask); | |
2752 | static inline void | |
2753 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2754 | { | |
2755 | ilk_update_display_irq(dev_priv, bits, bits); | |
2756 | } | |
2757 | static inline void | |
2758 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2759 | { | |
2760 | ilk_update_display_irq(dev_priv, bits, 0); | |
2761 | } | |
013d3752 VS |
2762 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
2763 | enum pipe pipe, | |
2764 | uint32_t interrupt_mask, | |
2765 | uint32_t enabled_irq_mask); | |
2766 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
2767 | enum pipe pipe, uint32_t bits) | |
2768 | { | |
2769 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
2770 | } | |
2771 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
2772 | enum pipe pipe, uint32_t bits) | |
2773 | { | |
2774 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
2775 | } | |
47339cd9 DV |
2776 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2777 | uint32_t interrupt_mask, | |
2778 | uint32_t enabled_irq_mask); | |
14443261 VS |
2779 | static inline void |
2780 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2781 | { | |
2782 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
2783 | } | |
2784 | static inline void | |
2785 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2786 | { | |
2787 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
2788 | } | |
2789 | ||
f8b79e58 | 2790 | |
673a394b | 2791 | /* i915_gem.c */ |
673a394b EA |
2792 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2793 | struct drm_file *file_priv); | |
2794 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2795 | struct drm_file *file_priv); | |
2796 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2797 | struct drm_file *file_priv); | |
2798 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2799 | struct drm_file *file_priv); | |
de151cf6 JB |
2800 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2801 | struct drm_file *file_priv); | |
673a394b EA |
2802 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2803 | struct drm_file *file_priv); | |
2804 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2805 | struct drm_file *file_priv); | |
ba8b7ccb | 2806 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 2807 | struct drm_i915_gem_request *req); |
adeca76d | 2808 | void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params); |
5f19e2bf | 2809 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 2810 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 2811 | struct list_head *vmas); |
673a394b EA |
2812 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2813 | struct drm_file *file_priv); | |
76446cac JB |
2814 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2815 | struct drm_file *file_priv); | |
673a394b EA |
2816 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2817 | struct drm_file *file_priv); | |
199adf40 BW |
2818 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2819 | struct drm_file *file); | |
2820 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2821 | struct drm_file *file); | |
673a394b EA |
2822 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2823 | struct drm_file *file_priv); | |
3ef94daa CW |
2824 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2825 | struct drm_file *file_priv); | |
673a394b EA |
2826 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2827 | struct drm_file *file_priv); | |
2828 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2829 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2830 | int i915_gem_init_userptr(struct drm_device *dev); |
2831 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2832 | struct drm_file *file); | |
5a125c3c EA |
2833 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2834 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2835 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2836 | struct drm_file *file_priv); | |
d64aa096 ID |
2837 | void i915_gem_load_init(struct drm_device *dev); |
2838 | void i915_gem_load_cleanup(struct drm_device *dev); | |
42dcedd4 CW |
2839 | void *i915_gem_object_alloc(struct drm_device *dev); |
2840 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2841 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2842 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2843 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2844 | size_t size); | |
ea70299d DG |
2845 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
2846 | struct drm_device *dev, const void *data, size_t size); | |
673a394b | 2847 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2848 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2849 | |
0875546c DV |
2850 | /* Flags used by pin/bind&friends. */ |
2851 | #define PIN_MAPPABLE (1<<0) | |
2852 | #define PIN_NONBLOCK (1<<1) | |
2853 | #define PIN_GLOBAL (1<<2) | |
2854 | #define PIN_OFFSET_BIAS (1<<3) | |
2855 | #define PIN_USER (1<<4) | |
2856 | #define PIN_UPDATE (1<<5) | |
101b506a MT |
2857 | #define PIN_ZONE_4G (1<<6) |
2858 | #define PIN_HIGH (1<<7) | |
506a8e87 | 2859 | #define PIN_OFFSET_FIXED (1<<8) |
d23db88c | 2860 | #define PIN_OFFSET_MASK (~4095) |
ec7adb6e JL |
2861 | int __must_check |
2862 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
2863 | struct i915_address_space *vm, | |
2864 | uint32_t alignment, | |
2865 | uint64_t flags); | |
2866 | int __must_check | |
2867 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
2868 | const struct i915_ggtt_view *view, | |
2869 | uint32_t alignment, | |
2870 | uint64_t flags); | |
fe14d5f4 TU |
2871 | |
2872 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2873 | u32 flags); | |
d0710abb | 2874 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
07fe0b12 | 2875 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
e9f24d5f TU |
2876 | /* |
2877 | * BEWARE: Do not use the function below unless you can _absolutely_ | |
2878 | * _guarantee_ VMA in question is _not in use_ anywhere. | |
2879 | */ | |
2880 | int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); | |
dd624afd | 2881 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2882 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2883 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2884 | |
4c914c0c BV |
2885 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2886 | int *needs_clflush); | |
2887 | ||
37e680a1 | 2888 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
2889 | |
2890 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 2891 | { |
ee286370 CW |
2892 | return sg->length >> PAGE_SHIFT; |
2893 | } | |
67d5a50c | 2894 | |
033908ae DG |
2895 | struct page * |
2896 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); | |
2897 | ||
ee286370 CW |
2898 | static inline struct page * |
2899 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 2900 | { |
ee286370 CW |
2901 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2902 | return NULL; | |
67d5a50c | 2903 | |
ee286370 CW |
2904 | if (n < obj->get_page.last) { |
2905 | obj->get_page.sg = obj->pages->sgl; | |
2906 | obj->get_page.last = 0; | |
2907 | } | |
67d5a50c | 2908 | |
ee286370 CW |
2909 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
2910 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
2911 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
2912 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
2913 | } | |
67d5a50c | 2914 | |
ee286370 | 2915 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 2916 | } |
ee286370 | 2917 | |
a5570178 CW |
2918 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2919 | { | |
2920 | BUG_ON(obj->pages == NULL); | |
2921 | obj->pages_pin_count++; | |
2922 | } | |
2923 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2924 | { | |
2925 | BUG_ON(obj->pages_pin_count == 0); | |
2926 | obj->pages_pin_count--; | |
2927 | } | |
2928 | ||
54cf91dc | 2929 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2930 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
91af127f JH |
2931 | struct intel_engine_cs *to, |
2932 | struct drm_i915_gem_request **to_req); | |
e2d05a8b | 2933 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2934 | struct drm_i915_gem_request *req); |
ff72145b DA |
2935 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2936 | struct drm_device *dev, | |
2937 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
2938 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2939 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2940 | /** |
2941 | * Returns true if seq1 is later than seq2. | |
2942 | */ | |
2943 | static inline bool | |
2944 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2945 | { | |
2946 | return (int32_t)(seq1 - seq2) >= 0; | |
2947 | } | |
2948 | ||
821485dc CW |
2949 | static inline bool i915_gem_request_started(struct drm_i915_gem_request *req, |
2950 | bool lazy_coherency) | |
2951 | { | |
2952 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); | |
2953 | return i915_seqno_passed(seqno, req->previous_seqno); | |
2954 | } | |
2955 | ||
1b5a433a JH |
2956 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
2957 | bool lazy_coherency) | |
2958 | { | |
821485dc | 2959 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); |
1b5a433a JH |
2960 | return i915_seqno_passed(seqno, req->seqno); |
2961 | } | |
2962 | ||
fca26bb4 MK |
2963 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2964 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
1690e1eb | 2965 | |
8d9fc7fd | 2966 | struct drm_i915_gem_request * |
a4872ba6 | 2967 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2968 | |
b29c19b6 | 2969 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2970 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2971 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2972 | bool interruptible); |
84c33a64 | 2973 | |
1f83fee0 DV |
2974 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2975 | { | |
2976 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2977 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2978 | } |
2979 | ||
2980 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2981 | { | |
2ac0f450 MK |
2982 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2983 | } | |
2984 | ||
2985 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2986 | { | |
2987 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2988 | } |
a71d8d94 | 2989 | |
88b4aa87 MK |
2990 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2991 | { | |
2992 | return dev_priv->gpu_error.stop_rings == 0 || | |
2993 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2994 | } | |
2995 | ||
2996 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2997 | { | |
2998 | return dev_priv->gpu_error.stop_rings == 0 || | |
2999 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
3000 | } | |
3001 | ||
069efc1d | 3002 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 3003 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 3004 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 3005 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 3006 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
6909a666 | 3007 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice); |
f691e2f4 | 3008 | void i915_gem_init_swizzling(struct drm_device *dev); |
1ffedc06 | 3009 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 3010 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 3011 | int __must_check i915_gem_suspend(struct drm_device *dev); |
75289874 | 3012 | void __i915_add_request(struct drm_i915_gem_request *req, |
5b4a60c2 JH |
3013 | struct drm_i915_gem_object *batch_obj, |
3014 | bool flush_caches); | |
75289874 | 3015 | #define i915_add_request(req) \ |
fcfa423c | 3016 | __i915_add_request(req, NULL, true) |
75289874 | 3017 | #define i915_add_request_no_flush(req) \ |
fcfa423c | 3018 | __i915_add_request(req, NULL, false) |
9c654818 | 3019 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
3020 | unsigned reset_counter, |
3021 | bool interruptible, | |
3022 | s64 *timeout, | |
2e1b8730 | 3023 | struct intel_rps_client *rps); |
a4b3a571 | 3024 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 3025 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 3026 | int __must_check |
2e2f351d CW |
3027 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3028 | bool readonly); | |
3029 | int __must_check | |
2021746e CW |
3030 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3031 | bool write); | |
3032 | int __must_check | |
dabdfe02 CW |
3033 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3034 | int __must_check | |
2da3b9b9 CW |
3035 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3036 | u32 alignment, | |
e6617330 TU |
3037 | const struct i915_ggtt_view *view); |
3038 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
3039 | const struct i915_ggtt_view *view); | |
00731155 | 3040 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3041 | int align); |
b29c19b6 | 3042 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3043 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3044 | |
0fa87796 ID |
3045 | uint32_t |
3046 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 3047 | uint32_t |
d865110c ID |
3048 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
3049 | int tiling_mode, bool fenced); | |
467cffba | 3050 | |
e4ffd173 CW |
3051 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3052 | enum i915_cache_level cache_level); | |
3053 | ||
1286ff73 DV |
3054 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3055 | struct dma_buf *dma_buf); | |
3056 | ||
3057 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3058 | struct drm_gem_object *gem_obj, int flags); | |
3059 | ||
088e0df4 MT |
3060 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
3061 | const struct i915_ggtt_view *view); | |
3062 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
3063 | struct i915_address_space *vm); | |
3064 | static inline u64 | |
ec7adb6e | 3065 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
fe14d5f4 | 3066 | { |
9abc4648 | 3067 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 3068 | } |
ec7adb6e | 3069 | |
a70a3148 | 3070 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
ec7adb6e | 3071 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 3072 | const struct i915_ggtt_view *view); |
a70a3148 | 3073 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 3074 | struct i915_address_space *vm); |
fe14d5f4 | 3075 | |
a70a3148 BW |
3076 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
3077 | struct i915_address_space *vm); | |
fe14d5f4 | 3078 | struct i915_vma * |
ec7adb6e JL |
3079 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3080 | struct i915_address_space *vm); | |
3081 | struct i915_vma * | |
3082 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
3083 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3084 | |
accfef2e BW |
3085 | struct i915_vma * |
3086 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
3087 | struct i915_address_space *vm); |
3088 | struct i915_vma * | |
3089 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
3090 | const struct i915_ggtt_view *view); | |
5c2abbea | 3091 | |
ec7adb6e JL |
3092 | static inline struct i915_vma * |
3093 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
3094 | { | |
3095 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 3096 | } |
ec7adb6e | 3097 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 3098 | |
a70a3148 | 3099 | /* Some GGTT VM helpers */ |
5dc383b0 | 3100 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 | 3101 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
a70a3148 | 3102 | |
841cd773 DV |
3103 | static inline struct i915_hw_ppgtt * |
3104 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3105 | { | |
3106 | WARN_ON(i915_is_ggtt(vm)); | |
841cd773 DV |
3107 | return container_of(vm, struct i915_hw_ppgtt, base); |
3108 | } | |
3109 | ||
3110 | ||
a70a3148 BW |
3111 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3112 | { | |
9abc4648 | 3113 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
3114 | } |
3115 | ||
3116 | static inline unsigned long | |
3117 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
3118 | { | |
5dc383b0 | 3119 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 3120 | } |
c37e2204 BW |
3121 | |
3122 | static inline int __must_check | |
3123 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
3124 | uint32_t alignment, | |
1ec9e26d | 3125 | unsigned flags) |
c37e2204 | 3126 | { |
5dc383b0 DV |
3127 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
3128 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 3129 | } |
a70a3148 | 3130 | |
b287110e DV |
3131 | static inline int |
3132 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
3133 | { | |
3134 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
3135 | } | |
3136 | ||
e6617330 TU |
3137 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3138 | const struct i915_ggtt_view *view); | |
3139 | static inline void | |
3140 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3141 | { | |
3142 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3143 | } | |
b287110e | 3144 | |
41a36b73 DV |
3145 | /* i915_gem_fence.c */ |
3146 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
3147 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
3148 | ||
3149 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
3150 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
3151 | ||
3152 | void i915_gem_restore_fences(struct drm_device *dev); | |
3153 | ||
7f96ecaf DV |
3154 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3155 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3156 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3157 | ||
254f965c | 3158 | /* i915_gem_context.c */ |
8245be31 | 3159 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 3160 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3161 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3162 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
b3dd6b96 | 3163 | int i915_gem_context_enable(struct drm_i915_gem_request *req); |
254f965c | 3164 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3165 | int i915_switch_context(struct drm_i915_gem_request *req); |
273497e5 | 3166 | struct intel_context * |
41bde553 | 3167 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 3168 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3169 | struct drm_i915_gem_object * |
3170 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 3171 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 3172 | { |
691e6415 | 3173 | kref_get(&ctx->ref); |
dce3271b MK |
3174 | } |
3175 | ||
273497e5 | 3176 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 3177 | { |
691e6415 | 3178 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3179 | } |
3180 | ||
273497e5 | 3181 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 3182 | { |
821d66dd | 3183 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3184 | } |
3185 | ||
84624813 BW |
3186 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3187 | struct drm_file *file); | |
3188 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3189 | struct drm_file *file); | |
c9dc0f35 CW |
3190 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3191 | struct drm_file *file_priv); | |
3192 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3193 | struct drm_file *file_priv); | |
1286ff73 | 3194 | |
679845ed BW |
3195 | /* i915_gem_evict.c */ |
3196 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3197 | struct i915_address_space *vm, | |
3198 | int min_size, | |
3199 | unsigned alignment, | |
3200 | unsigned cache_level, | |
d23db88c CW |
3201 | unsigned long start, |
3202 | unsigned long end, | |
1ec9e26d | 3203 | unsigned flags); |
506a8e87 | 3204 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
679845ed | 3205 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3206 | |
0260c420 | 3207 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 3208 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
3209 | { |
3210 | if (INTEL_INFO(dev)->gen < 6) | |
3211 | intel_gtt_chipset_flush(); | |
3212 | } | |
246cbfb5 | 3213 | |
9797fbfb | 3214 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3215 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3216 | struct drm_mm_node *node, u64 size, | |
3217 | unsigned alignment); | |
a9da512b PZ |
3218 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3219 | struct drm_mm_node *node, u64 size, | |
3220 | unsigned alignment, u64 start, | |
3221 | u64 end); | |
d713fd49 PZ |
3222 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3223 | struct drm_mm_node *node); | |
9797fbfb CW |
3224 | int i915_gem_init_stolen(struct drm_device *dev); |
3225 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3226 | struct drm_i915_gem_object * |
3227 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3228 | struct drm_i915_gem_object * |
3229 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3230 | u32 stolen_offset, | |
3231 | u32 gtt_offset, | |
3232 | u32 size); | |
9797fbfb | 3233 | |
be6a0376 DV |
3234 | /* i915_gem_shrinker.c */ |
3235 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3236 | unsigned long target, |
be6a0376 DV |
3237 | unsigned flags); |
3238 | #define I915_SHRINK_PURGEABLE 0x1 | |
3239 | #define I915_SHRINK_UNBOUND 0x2 | |
3240 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3241 | #define I915_SHRINK_ACTIVE 0x8 |
be6a0376 DV |
3242 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3243 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3244 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3245 | |
3246 | ||
673a394b | 3247 | /* i915_gem_tiling.c */ |
2c1792a1 | 3248 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3249 | { |
50227e1c | 3250 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
3251 | |
3252 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3253 | obj->tiling_mode != I915_TILING_NONE; | |
3254 | } | |
3255 | ||
673a394b | 3256 | /* i915_gem_debug.c */ |
23bc5982 CW |
3257 | #if WATCH_LISTS |
3258 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 3259 | #else |
23bc5982 | 3260 | #define i915_verify_lists(dev) 0 |
673a394b | 3261 | #endif |
1da177e4 | 3262 | |
2017263e | 3263 | /* i915_debugfs.c */ |
27c202ad BG |
3264 | int i915_debugfs_init(struct drm_minor *minor); |
3265 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 3266 | #ifdef CONFIG_DEBUG_FS |
249e87de | 3267 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3268 | void intel_display_crc_init(struct drm_device *dev); |
3269 | #else | |
101057fa DV |
3270 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3271 | { return 0; } | |
f8c168fa | 3272 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3273 | #endif |
84734a04 MK |
3274 | |
3275 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3276 | __printf(2, 3) |
3277 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3278 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3279 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3280 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3281 | struct drm_i915_private *i915, |
4dc955f7 MK |
3282 | size_t count, loff_t pos); |
3283 | static inline void i915_error_state_buf_release( | |
3284 | struct drm_i915_error_state_buf *eb) | |
3285 | { | |
3286 | kfree(eb->buf); | |
3287 | } | |
58174462 MK |
3288 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
3289 | const char *error_msg); | |
84734a04 MK |
3290 | void i915_error_state_get(struct drm_device *dev, |
3291 | struct i915_error_state_file_priv *error_priv); | |
3292 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3293 | void i915_destroy_error_state(struct drm_device *dev); | |
3294 | ||
3295 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 3296 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3297 | |
351e3db2 | 3298 | /* i915_cmd_parser.c */ |
d728c8ef | 3299 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
3300 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
3301 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
3302 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
3303 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 | 3304 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3305 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3306 | u32 batch_start_offset, |
b9ffd80e | 3307 | u32 batch_len, |
351e3db2 BV |
3308 | bool is_master); |
3309 | ||
317c35d1 JB |
3310 | /* i915_suspend.c */ |
3311 | extern int i915_save_state(struct drm_device *dev); | |
3312 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3313 | |
0136db58 BW |
3314 | /* i915_sysfs.c */ |
3315 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3316 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3317 | ||
f899fc64 CW |
3318 | /* intel_i2c.c */ |
3319 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3320 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3321 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3322 | unsigned int pin); | |
3bd7d909 | 3323 | |
0184df46 JN |
3324 | extern struct i2c_adapter * |
3325 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3326 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3327 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3328 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3329 | { |
3330 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3331 | } | |
f899fc64 CW |
3332 | extern void intel_i2c_reset(struct drm_device *dev); |
3333 | ||
8b8e1a89 | 3334 | /* intel_bios.c */ |
98f3a1dc | 3335 | int intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3336 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
8b8e1a89 | 3337 | |
3b617967 | 3338 | /* intel_opregion.c */ |
44834a67 | 3339 | #ifdef CONFIG_ACPI |
27d50c82 | 3340 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
3341 | extern void intel_opregion_init(struct drm_device *dev); |
3342 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 3343 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
3344 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3345 | bool enable); | |
ecbc5cf3 JN |
3346 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3347 | pci_power_t state); | |
65e082c9 | 3348 | #else |
27d50c82 | 3349 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
3350 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3351 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 3352 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
3353 | static inline int |
3354 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3355 | { | |
3356 | return 0; | |
3357 | } | |
ecbc5cf3 JN |
3358 | static inline int |
3359 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3360 | { | |
3361 | return 0; | |
3362 | } | |
65e082c9 | 3363 | #endif |
8ee1c3db | 3364 | |
723bfd70 JB |
3365 | /* intel_acpi.c */ |
3366 | #ifdef CONFIG_ACPI | |
3367 | extern void intel_register_dsm_handler(void); | |
3368 | extern void intel_unregister_dsm_handler(void); | |
3369 | #else | |
3370 | static inline void intel_register_dsm_handler(void) { return; } | |
3371 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3372 | #endif /* CONFIG_ACPI */ | |
3373 | ||
79e53945 | 3374 | /* modesetting */ |
f817586c | 3375 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3376 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3377 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3378 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 3379 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 3380 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3381 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3382 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3383 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
7648fa99 | 3384 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 3385 | extern void intel_init_pch_refclk(struct drm_device *dev); |
ffe02b40 | 3386 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
3387 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3388 | bool enable); | |
0206e353 | 3389 | extern void intel_detect_pch(struct drm_device *dev); |
0136db58 | 3390 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 3391 | |
2911a35b | 3392 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
3393 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3394 | struct drm_file *file); | |
b6359918 MK |
3395 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3396 | struct drm_file *file); | |
575155a9 | 3397 | |
6ef3d427 CW |
3398 | /* overlay */ |
3399 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
3400 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3401 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
3402 | |
3403 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 3404 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3405 | struct drm_device *dev, |
3406 | struct intel_display_error_state *error); | |
6ef3d427 | 3407 | |
151a49d0 TR |
3408 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3409 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3410 | |
3411 | /* intel_sideband.c */ | |
707b6e3d D |
3412 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3413 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3414 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3415 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3416 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3417 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3418 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3419 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3420 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3421 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3422 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3423 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3424 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3425 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3426 | enum intel_sbi_destination destination); | |
3427 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3428 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3429 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3430 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3431 | |
616bc820 VS |
3432 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3433 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3434 | |
0b274481 BW |
3435 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3436 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3437 | ||
3438 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3439 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3440 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3441 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3442 | ||
3443 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3444 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3445 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3446 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3447 | ||
698b3135 CW |
3448 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3449 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3450 | * an arbitrary delay between them. This can cause the hardware to | |
3451 | * act upon the intermediate value, possibly leading to corruption and | |
3452 | * machine death. You have been warned. | |
3453 | */ | |
0b274481 BW |
3454 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3455 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3456 | |
50877445 | 3457 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3458 | u32 upper, lower, old_upper, loop = 0; \ |
3459 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3460 | do { \ |
acd29f7b | 3461 | old_upper = upper; \ |
ee0a227b | 3462 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3463 | upper = I915_READ(upper_reg); \ |
3464 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3465 | (u64)upper << 32 | lower; }) |
50877445 | 3466 | |
cae5852d ZN |
3467 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3468 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3469 | ||
75aa3f63 VS |
3470 | #define __raw_read(x, s) \ |
3471 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3472 | i915_reg_t reg) \ |
75aa3f63 | 3473 | { \ |
f0f59a00 | 3474 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3475 | } |
3476 | ||
3477 | #define __raw_write(x, s) \ | |
3478 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3479 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3480 | { \ |
f0f59a00 | 3481 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3482 | } |
3483 | __raw_read(8, b) | |
3484 | __raw_read(16, w) | |
3485 | __raw_read(32, l) | |
3486 | __raw_read(64, q) | |
3487 | ||
3488 | __raw_write(8, b) | |
3489 | __raw_write(16, w) | |
3490 | __raw_write(32, l) | |
3491 | __raw_write(64, q) | |
3492 | ||
3493 | #undef __raw_read | |
3494 | #undef __raw_write | |
3495 | ||
a6111f7b CW |
3496 | /* These are untraced mmio-accessors that are only valid to be used inside |
3497 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3498 | * controlled. | |
3499 | * Think twice, and think again, before using these. | |
3500 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3501 | * intel_uncore_forcewake_irqunlock(). | |
3502 | */ | |
75aa3f63 VS |
3503 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3504 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
a6111f7b CW |
3505 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3506 | ||
55bc60db VS |
3507 | /* "Broadcast RGB" property */ |
3508 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3509 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3510 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3511 | |
f0f59a00 | 3512 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
766aa1c4 | 3513 | { |
666a4537 | 3514 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
766aa1c4 | 3515 | return VLV_VGACNTRL; |
92e23b99 SJ |
3516 | else if (INTEL_INFO(dev)->gen >= 5) |
3517 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3518 | else |
3519 | return VGACNTRL; | |
3520 | } | |
3521 | ||
2bb4629a VS |
3522 | static inline void __user *to_user_ptr(u64 address) |
3523 | { | |
3524 | return (void __user *)(uintptr_t)address; | |
3525 | } | |
3526 | ||
df97729f ID |
3527 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3528 | { | |
3529 | unsigned long j = msecs_to_jiffies(m); | |
3530 | ||
3531 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3532 | } | |
3533 | ||
7bd0e226 DV |
3534 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3535 | { | |
3536 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3537 | } | |
3538 | ||
df97729f ID |
3539 | static inline unsigned long |
3540 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3541 | { | |
3542 | unsigned long j = timespec_to_jiffies(value); | |
3543 | ||
3544 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3545 | } | |
3546 | ||
dce56b3c PZ |
3547 | /* |
3548 | * If you need to wait X milliseconds between events A and B, but event B | |
3549 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3550 | * when event A happened, then just before event B you call this function and | |
3551 | * pass the timestamp as the first argument, and X as the second argument. | |
3552 | */ | |
3553 | static inline void | |
3554 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3555 | { | |
ec5e0cfb | 3556 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3557 | |
3558 | /* | |
3559 | * Don't re-read the value of "jiffies" every time since it may change | |
3560 | * behind our back and break the math. | |
3561 | */ | |
3562 | tmp_jiffies = jiffies; | |
3563 | target_jiffies = timestamp_jiffies + | |
3564 | msecs_to_jiffies_timeout(to_wait_ms); | |
3565 | ||
3566 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3567 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3568 | while (remaining_jiffies) | |
3569 | remaining_jiffies = | |
3570 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3571 | } |
3572 | } | |
3573 | ||
581c26e8 JH |
3574 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3575 | struct drm_i915_gem_request *req) | |
3576 | { | |
3577 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) | |
3578 | i915_gem_request_assign(&ring->trace_irq_req, req); | |
3579 | } | |
3580 | ||
1da177e4 | 3581 | #endif |