Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
585fb111 | 36 | #include "i915_reg.h" |
79e53945 | 37 | #include "intel_bios.h" |
8187a2b7 | 38 | #include "intel_ringbuffer.h" |
b20385f1 | 39 | #include "intel_lrc.h" |
0260c420 | 40 | #include "i915_gem_gtt.h" |
564ddb2f | 41 | #include "i915_gem_render_state.h" |
0839ccb8 | 42 | #include <linux/io-mapping.h> |
f899fc64 | 43 | #include <linux/i2c.h> |
c167a6fc | 44 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 45 | #include <drm/intel-gtt.h> |
ba8286fa | 46 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
d9fc9413 | 47 | #include <drm/drm_gem.h> |
aaa6fd2a | 48 | #include <linux/backlight.h> |
5cc9ed4b | 49 | #include <linux/hashtable.h> |
2911a35b | 50 | #include <linux/intel-iommu.h> |
742cbee8 | 51 | #include <linux/kref.h> |
9ee32fea | 52 | #include <linux/pm_qos.h> |
585fb111 | 53 | |
1da177e4 LT |
54 | /* General customization: |
55 | */ | |
56 | ||
1da177e4 LT |
57 | #define DRIVER_NAME "i915" |
58 | #define DRIVER_DESC "Intel Graphics" | |
d4495cba | 59 | #define DRIVER_DATE "20150214" |
1da177e4 | 60 | |
c883ef1b | 61 | #undef WARN_ON |
5f77eeb0 DV |
62 | /* Many gcc seem to no see through this and fall over :( */ |
63 | #if 0 | |
64 | #define WARN_ON(x) ({ \ | |
65 | bool __i915_warn_cond = (x); \ | |
66 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
67 | BUILD_BUG_ON(__i915_warn_cond); \ | |
68 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
69 | #else | |
70 | #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")") | |
71 | #endif | |
72 | ||
73 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ | |
74 | (long) (x), __func__); | |
c883ef1b | 75 | |
e2c719b7 RC |
76 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
77 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
78 | * which may not necessarily be a user visible problem. This will either | |
79 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
80 | * enable distros and users to tailor their preferred amount of i915 abrt | |
81 | * spam. | |
82 | */ | |
83 | #define I915_STATE_WARN(condition, format...) ({ \ | |
84 | int __ret_warn_on = !!(condition); \ | |
85 | if (unlikely(__ret_warn_on)) { \ | |
86 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 87 | WARN(1, format); \ |
e2c719b7 RC |
88 | else \ |
89 | DRM_ERROR(format); \ | |
90 | } \ | |
91 | unlikely(__ret_warn_on); \ | |
92 | }) | |
93 | ||
94 | #define I915_STATE_WARN_ON(condition) ({ \ | |
95 | int __ret_warn_on = !!(condition); \ | |
96 | if (unlikely(__ret_warn_on)) { \ | |
97 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 98 | WARN(1, "WARN_ON(" #condition ")\n"); \ |
e2c719b7 RC |
99 | else \ |
100 | DRM_ERROR("WARN_ON(" #condition ")\n"); \ | |
101 | } \ | |
102 | unlikely(__ret_warn_on); \ | |
103 | }) | |
104 | ||
317c35d1 | 105 | enum pipe { |
752aa88a | 106 | INVALID_PIPE = -1, |
317c35d1 JB |
107 | PIPE_A = 0, |
108 | PIPE_B, | |
9db4a9c7 | 109 | PIPE_C, |
a57c774a AK |
110 | _PIPE_EDP, |
111 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 112 | }; |
9db4a9c7 | 113 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 114 | |
a5c961d1 PZ |
115 | enum transcoder { |
116 | TRANSCODER_A = 0, | |
117 | TRANSCODER_B, | |
118 | TRANSCODER_C, | |
a57c774a AK |
119 | TRANSCODER_EDP, |
120 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
121 | }; |
122 | #define transcoder_name(t) ((t) + 'A') | |
123 | ||
84139d1e DL |
124 | /* |
125 | * This is the maximum (across all platforms) number of planes (primary + | |
126 | * sprites) that can be active at the same time on one pipe. | |
127 | * | |
128 | * This value doesn't count the cursor plane. | |
129 | */ | |
130 | #define I915_MAX_PLANES 3 | |
131 | ||
80824003 JB |
132 | enum plane { |
133 | PLANE_A = 0, | |
134 | PLANE_B, | |
9db4a9c7 | 135 | PLANE_C, |
80824003 | 136 | }; |
9db4a9c7 | 137 | #define plane_name(p) ((p) + 'A') |
52440211 | 138 | |
d615a166 | 139 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 140 | |
2b139522 ED |
141 | enum port { |
142 | PORT_A = 0, | |
143 | PORT_B, | |
144 | PORT_C, | |
145 | PORT_D, | |
146 | PORT_E, | |
147 | I915_MAX_PORTS | |
148 | }; | |
149 | #define port_name(p) ((p) + 'A') | |
150 | ||
a09caddd | 151 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
152 | |
153 | enum dpio_channel { | |
154 | DPIO_CH0, | |
155 | DPIO_CH1 | |
156 | }; | |
157 | ||
158 | enum dpio_phy { | |
159 | DPIO_PHY0, | |
160 | DPIO_PHY1 | |
161 | }; | |
162 | ||
b97186f0 PZ |
163 | enum intel_display_power_domain { |
164 | POWER_DOMAIN_PIPE_A, | |
165 | POWER_DOMAIN_PIPE_B, | |
166 | POWER_DOMAIN_PIPE_C, | |
167 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
168 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
169 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
170 | POWER_DOMAIN_TRANSCODER_A, | |
171 | POWER_DOMAIN_TRANSCODER_B, | |
172 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 173 | POWER_DOMAIN_TRANSCODER_EDP, |
319be8ae ID |
174 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
175 | POWER_DOMAIN_PORT_DDI_A_4_LANES, | |
176 | POWER_DOMAIN_PORT_DDI_B_2_LANES, | |
177 | POWER_DOMAIN_PORT_DDI_B_4_LANES, | |
178 | POWER_DOMAIN_PORT_DDI_C_2_LANES, | |
179 | POWER_DOMAIN_PORT_DDI_C_4_LANES, | |
180 | POWER_DOMAIN_PORT_DDI_D_2_LANES, | |
181 | POWER_DOMAIN_PORT_DDI_D_4_LANES, | |
182 | POWER_DOMAIN_PORT_DSI, | |
183 | POWER_DOMAIN_PORT_CRT, | |
184 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 185 | POWER_DOMAIN_VGA, |
fbeeaa23 | 186 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 187 | POWER_DOMAIN_PLLS, |
1407121a S |
188 | POWER_DOMAIN_AUX_A, |
189 | POWER_DOMAIN_AUX_B, | |
190 | POWER_DOMAIN_AUX_C, | |
191 | POWER_DOMAIN_AUX_D, | |
baa70707 | 192 | POWER_DOMAIN_INIT, |
bddc7645 ID |
193 | |
194 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
195 | }; |
196 | ||
197 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
198 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
199 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
200 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
201 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
202 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 203 | |
1d843f9d EE |
204 | enum hpd_pin { |
205 | HPD_NONE = 0, | |
206 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
207 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
208 | HPD_CRT, | |
209 | HPD_SDVO_B, | |
210 | HPD_SDVO_C, | |
211 | HPD_PORT_B, | |
212 | HPD_PORT_C, | |
213 | HPD_PORT_D, | |
214 | HPD_NUM_PINS | |
215 | }; | |
216 | ||
2a2d5482 CW |
217 | #define I915_GEM_GPU_DOMAINS \ |
218 | (I915_GEM_DOMAIN_RENDER | \ | |
219 | I915_GEM_DOMAIN_SAMPLER | \ | |
220 | I915_GEM_DOMAIN_COMMAND | \ | |
221 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
222 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 223 | |
055e393f DL |
224 | #define for_each_pipe(__dev_priv, __p) \ |
225 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
2d025a5b DL |
226 | #define for_each_plane(pipe, p) \ |
227 | for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++) | |
d615a166 | 228 | #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) |
9db4a9c7 | 229 | |
d79b814d DL |
230 | #define for_each_crtc(dev, crtc) \ |
231 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
232 | ||
d063ae48 DL |
233 | #define for_each_intel_crtc(dev, intel_crtc) \ |
234 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
235 | ||
b2784e15 DL |
236 | #define for_each_intel_encoder(dev, intel_encoder) \ |
237 | list_for_each_entry(intel_encoder, \ | |
238 | &(dev)->mode_config.encoder_list, \ | |
239 | base.head) | |
240 | ||
6c2b7c12 DV |
241 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
242 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
243 | if ((intel_encoder)->base.crtc == (__crtc)) | |
244 | ||
53f5e3ca JB |
245 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
246 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
247 | if ((intel_connector)->base.encoder == (__encoder)) | |
248 | ||
b04c5bd6 BF |
249 | #define for_each_power_domain(domain, mask) \ |
250 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
251 | if ((1 << (domain)) & (mask)) | |
252 | ||
e7b903d2 | 253 | struct drm_i915_private; |
ad46cb53 | 254 | struct i915_mm_struct; |
5cc9ed4b | 255 | struct i915_mmu_object; |
e7b903d2 | 256 | |
46edb027 DV |
257 | enum intel_dpll_id { |
258 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
259 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
260 | DPLL_ID_PCH_PLL_A = 0, |
261 | DPLL_ID_PCH_PLL_B = 1, | |
429d47d5 | 262 | /* hsw/bdw */ |
9cd86933 DV |
263 | DPLL_ID_WRPLL1 = 0, |
264 | DPLL_ID_WRPLL2 = 1, | |
429d47d5 S |
265 | /* skl */ |
266 | DPLL_ID_SKL_DPLL1 = 0, | |
267 | DPLL_ID_SKL_DPLL2 = 1, | |
268 | DPLL_ID_SKL_DPLL3 = 2, | |
46edb027 | 269 | }; |
429d47d5 | 270 | #define I915_NUM_PLLS 3 |
46edb027 | 271 | |
5358901f | 272 | struct intel_dpll_hw_state { |
dcfc3552 | 273 | /* i9xx, pch plls */ |
66e985c0 | 274 | uint32_t dpll; |
8bcc2795 | 275 | uint32_t dpll_md; |
66e985c0 DV |
276 | uint32_t fp0; |
277 | uint32_t fp1; | |
dcfc3552 DL |
278 | |
279 | /* hsw, bdw */ | |
d452c5b6 | 280 | uint32_t wrpll; |
d1a2dc78 S |
281 | |
282 | /* skl */ | |
283 | /* | |
284 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in | |
285 | * lower part of crtl1 and they get shifted into position when writing | |
286 | * the register. This allows us to easily compare the state to share | |
287 | * the DPLL. | |
288 | */ | |
289 | uint32_t ctrl1; | |
290 | /* HDMI only, 0 when used for DP */ | |
291 | uint32_t cfgcr1, cfgcr2; | |
5358901f DV |
292 | }; |
293 | ||
3e369b76 | 294 | struct intel_shared_dpll_config { |
1e6f2ddc | 295 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
3e369b76 ACO |
296 | struct intel_dpll_hw_state hw_state; |
297 | }; | |
298 | ||
299 | struct intel_shared_dpll { | |
300 | struct intel_shared_dpll_config config; | |
8bd31e67 ACO |
301 | struct intel_shared_dpll_config *new_config; |
302 | ||
ee7b9f93 JB |
303 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
304 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
305 | const char *name; |
306 | /* should match the index in the dev_priv->shared_dplls array */ | |
307 | enum intel_dpll_id id; | |
96f6128c DV |
308 | /* The mode_set hook is optional and should be used together with the |
309 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
310 | void (*mode_set)(struct drm_i915_private *dev_priv, |
311 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
312 | void (*enable)(struct drm_i915_private *dev_priv, |
313 | struct intel_shared_dpll *pll); | |
314 | void (*disable)(struct drm_i915_private *dev_priv, | |
315 | struct intel_shared_dpll *pll); | |
5358901f DV |
316 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
317 | struct intel_shared_dpll *pll, | |
318 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 319 | }; |
ee7b9f93 | 320 | |
429d47d5 S |
321 | #define SKL_DPLL0 0 |
322 | #define SKL_DPLL1 1 | |
323 | #define SKL_DPLL2 2 | |
324 | #define SKL_DPLL3 3 | |
325 | ||
e69d0bc1 DV |
326 | /* Used by dp and fdi links */ |
327 | struct intel_link_m_n { | |
328 | uint32_t tu; | |
329 | uint32_t gmch_m; | |
330 | uint32_t gmch_n; | |
331 | uint32_t link_m; | |
332 | uint32_t link_n; | |
333 | }; | |
334 | ||
335 | void intel_link_compute_m_n(int bpp, int nlanes, | |
336 | int pixel_clock, int link_clock, | |
337 | struct intel_link_m_n *m_n); | |
338 | ||
1da177e4 LT |
339 | /* Interface history: |
340 | * | |
341 | * 1.1: Original. | |
0d6aa60b DA |
342 | * 1.2: Add Power Management |
343 | * 1.3: Add vblank support | |
de227f5f | 344 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 345 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
346 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
347 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
348 | */ |
349 | #define DRIVER_MAJOR 1 | |
2228ed67 | 350 | #define DRIVER_MINOR 6 |
1da177e4 LT |
351 | #define DRIVER_PATCHLEVEL 0 |
352 | ||
23bc5982 | 353 | #define WATCH_LISTS 0 |
673a394b | 354 | |
0a3e67a4 JB |
355 | struct opregion_header; |
356 | struct opregion_acpi; | |
357 | struct opregion_swsci; | |
358 | struct opregion_asle; | |
359 | ||
8ee1c3db | 360 | struct intel_opregion { |
5bc4418b BW |
361 | struct opregion_header __iomem *header; |
362 | struct opregion_acpi __iomem *acpi; | |
363 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
364 | u32 swsci_gbda_sub_functions; |
365 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
366 | struct opregion_asle __iomem *asle; |
367 | void __iomem *vbt; | |
01fe9dbd | 368 | u32 __iomem *lid_state; |
91a60f20 | 369 | struct work_struct asle_work; |
8ee1c3db | 370 | }; |
44834a67 | 371 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 372 | |
6ef3d427 CW |
373 | struct intel_overlay; |
374 | struct intel_overlay_error_state; | |
375 | ||
de151cf6 | 376 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
377 | #define I915_MAX_NUM_FENCES 32 |
378 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
379 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
380 | |
381 | struct drm_i915_fence_reg { | |
007cc8ac | 382 | struct list_head lru_list; |
caea7476 | 383 | struct drm_i915_gem_object *obj; |
1690e1eb | 384 | int pin_count; |
de151cf6 | 385 | }; |
7c1c2871 | 386 | |
9b9d172d | 387 | struct sdvo_device_mapping { |
e957d772 | 388 | u8 initialized; |
9b9d172d | 389 | u8 dvo_port; |
390 | u8 slave_addr; | |
391 | u8 dvo_wiring; | |
e957d772 | 392 | u8 i2c_pin; |
b1083333 | 393 | u8 ddc_pin; |
9b9d172d | 394 | }; |
395 | ||
c4a1d9e4 CW |
396 | struct intel_display_error_state; |
397 | ||
63eeaf38 | 398 | struct drm_i915_error_state { |
742cbee8 | 399 | struct kref ref; |
585b0288 BW |
400 | struct timeval time; |
401 | ||
cb383002 | 402 | char error_msg[128]; |
48b031e3 | 403 | u32 reset_count; |
62d5d69b | 404 | u32 suspend_count; |
cb383002 | 405 | |
585b0288 | 406 | /* Generic register state */ |
63eeaf38 JB |
407 | u32 eir; |
408 | u32 pgtbl_er; | |
be998e2e | 409 | u32 ier; |
885ea5a8 | 410 | u32 gtier[4]; |
b9a3906b | 411 | u32 ccid; |
0f3b6849 CW |
412 | u32 derrmr; |
413 | u32 forcewake; | |
585b0288 BW |
414 | u32 error; /* gen6+ */ |
415 | u32 err_int; /* gen7 */ | |
416 | u32 done_reg; | |
91ec5d11 BW |
417 | u32 gac_eco; |
418 | u32 gam_ecochk; | |
419 | u32 gab_ctl; | |
420 | u32 gfx_mode; | |
585b0288 | 421 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
422 | u64 fence[I915_MAX_NUM_FENCES]; |
423 | struct intel_overlay_error_state *overlay; | |
424 | struct intel_display_error_state *display; | |
0ca36d78 | 425 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 426 | |
52d39a21 | 427 | struct drm_i915_error_ring { |
372fbb8e | 428 | bool valid; |
362b8af7 BW |
429 | /* Software tracked state */ |
430 | bool waiting; | |
431 | int hangcheck_score; | |
432 | enum intel_ring_hangcheck_action hangcheck_action; | |
433 | int num_requests; | |
434 | ||
435 | /* our own tracking of ring head and tail */ | |
436 | u32 cpu_ring_head; | |
437 | u32 cpu_ring_tail; | |
438 | ||
439 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
440 | ||
441 | /* Register state */ | |
442 | u32 tail; | |
443 | u32 head; | |
444 | u32 ctl; | |
445 | u32 hws; | |
446 | u32 ipeir; | |
447 | u32 ipehr; | |
448 | u32 instdone; | |
362b8af7 BW |
449 | u32 bbstate; |
450 | u32 instpm; | |
451 | u32 instps; | |
452 | u32 seqno; | |
453 | u64 bbaddr; | |
50877445 | 454 | u64 acthd; |
362b8af7 | 455 | u32 fault_reg; |
13ffadd1 | 456 | u64 faddr; |
362b8af7 BW |
457 | u32 rc_psmi; /* sleep state */ |
458 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
459 | ||
52d39a21 CW |
460 | struct drm_i915_error_object { |
461 | int page_count; | |
462 | u32 gtt_offset; | |
463 | u32 *pages[0]; | |
ab0e7ff9 | 464 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 465 | |
52d39a21 CW |
466 | struct drm_i915_error_request { |
467 | long jiffies; | |
468 | u32 seqno; | |
ee4f42b1 | 469 | u32 tail; |
52d39a21 | 470 | } *requests; |
6c7a01ec BW |
471 | |
472 | struct { | |
473 | u32 gfx_mode; | |
474 | union { | |
475 | u64 pdp[4]; | |
476 | u32 pp_dir_base; | |
477 | }; | |
478 | } vm_info; | |
ab0e7ff9 CW |
479 | |
480 | pid_t pid; | |
481 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 482 | } ring[I915_NUM_RINGS]; |
3a448734 | 483 | |
9df30794 | 484 | struct drm_i915_error_buffer { |
a779e5ab | 485 | u32 size; |
9df30794 | 486 | u32 name; |
0201f1ec | 487 | u32 rseqno, wseqno; |
9df30794 CW |
488 | u32 gtt_offset; |
489 | u32 read_domains; | |
490 | u32 write_domain; | |
4b9de737 | 491 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
492 | s32 pinned:2; |
493 | u32 tiling:2; | |
494 | u32 dirty:1; | |
495 | u32 purgeable:1; | |
5cc9ed4b | 496 | u32 userptr:1; |
5d1333fc | 497 | s32 ring:4; |
f56383cb | 498 | u32 cache_level:3; |
95f5301d | 499 | } **active_bo, **pinned_bo; |
6c7a01ec | 500 | |
95f5301d | 501 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 502 | u32 vm_count; |
63eeaf38 JB |
503 | }; |
504 | ||
7bd688cd | 505 | struct intel_connector; |
820d2d77 | 506 | struct intel_encoder; |
5cec258b | 507 | struct intel_crtc_state; |
5724dbd1 | 508 | struct intel_initial_plane_config; |
0e8ffe1b | 509 | struct intel_crtc; |
ee9300bb DV |
510 | struct intel_limit; |
511 | struct dpll; | |
b8cecdf5 | 512 | |
e70236a8 | 513 | struct drm_i915_display_funcs { |
ee5382ae | 514 | bool (*fbc_enabled)(struct drm_device *dev); |
993495ae | 515 | void (*enable_fbc)(struct drm_crtc *crtc); |
e70236a8 JB |
516 | void (*disable_fbc)(struct drm_device *dev); |
517 | int (*get_display_clock_speed)(struct drm_device *dev); | |
518 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
519 | /** |
520 | * find_dpll() - Find the best values for the PLL | |
521 | * @limit: limits for the PLL | |
522 | * @crtc: current CRTC | |
523 | * @target: target frequency in kHz | |
524 | * @refclk: reference clock frequency in kHz | |
525 | * @match_clock: if provided, @best_clock P divider must | |
526 | * match the P divider from @match_clock | |
527 | * used for LVDS downclocking | |
528 | * @best_clock: best PLL values found | |
529 | * | |
530 | * Returns true on success, false on failure. | |
531 | */ | |
532 | bool (*find_dpll)(const struct intel_limit *limit, | |
a919ff14 | 533 | struct intel_crtc *crtc, |
ee9300bb DV |
534 | int target, int refclk, |
535 | struct dpll *match_clock, | |
536 | struct dpll *best_clock); | |
46ba614c | 537 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
538 | void (*update_sprite_wm)(struct drm_plane *plane, |
539 | struct drm_crtc *crtc, | |
ed57cb8a DL |
540 | uint32_t sprite_width, uint32_t sprite_height, |
541 | int pixel_size, bool enable, bool scaled); | |
47fab737 | 542 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
543 | /* Returns the active state of the crtc, and if the crtc is active, |
544 | * fills out the pipe-config with the hw state. */ | |
545 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 546 | struct intel_crtc_state *); |
5724dbd1 DL |
547 | void (*get_initial_plane_config)(struct intel_crtc *, |
548 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
549 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
550 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
551 | void (*crtc_enable)(struct drm_crtc *crtc); |
552 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 553 | void (*off)(struct drm_crtc *crtc); |
69bfe1a9 JN |
554 | void (*audio_codec_enable)(struct drm_connector *connector, |
555 | struct intel_encoder *encoder, | |
556 | struct drm_display_mode *mode); | |
557 | void (*audio_codec_disable)(struct intel_encoder *encoder); | |
674cf967 | 558 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 559 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
560 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
561 | struct drm_framebuffer *fb, | |
ed8d1975 | 562 | struct drm_i915_gem_object *obj, |
a4872ba6 | 563 | struct intel_engine_cs *ring, |
ed8d1975 | 564 | uint32_t flags); |
29b9bde6 DV |
565 | void (*update_primary_plane)(struct drm_crtc *crtc, |
566 | struct drm_framebuffer *fb, | |
567 | int x, int y); | |
20afbda2 | 568 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
569 | /* clock updates for mode set */ |
570 | /* cursor updates */ | |
571 | /* render clock increase/decrease */ | |
572 | /* display clock increase/decrease */ | |
573 | /* pll clock increase/decrease */ | |
7bd688cd | 574 | |
6517d273 | 575 | int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); |
7bd688cd JN |
576 | uint32_t (*get_backlight)(struct intel_connector *connector); |
577 | void (*set_backlight)(struct intel_connector *connector, | |
578 | uint32_t level); | |
579 | void (*disable_backlight)(struct intel_connector *connector); | |
580 | void (*enable_backlight)(struct intel_connector *connector); | |
e70236a8 JB |
581 | }; |
582 | ||
48c1026a MK |
583 | enum forcewake_domain_id { |
584 | FW_DOMAIN_ID_RENDER = 0, | |
585 | FW_DOMAIN_ID_BLITTER, | |
586 | FW_DOMAIN_ID_MEDIA, | |
587 | ||
588 | FW_DOMAIN_ID_COUNT | |
589 | }; | |
590 | ||
591 | enum forcewake_domains { | |
592 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
593 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
594 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
595 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
596 | FORCEWAKE_BLITTER | | |
597 | FORCEWAKE_MEDIA) | |
598 | }; | |
599 | ||
907b28c5 | 600 | struct intel_uncore_funcs { |
c8d9a590 | 601 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 602 | enum forcewake_domains domains); |
c8d9a590 | 603 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 604 | enum forcewake_domains domains); |
0b274481 BW |
605 | |
606 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
607 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
608 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
609 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
610 | ||
611 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
612 | uint8_t val, bool trace); | |
613 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
614 | uint16_t val, bool trace); | |
615 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
616 | uint32_t val, bool trace); | |
617 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
618 | uint64_t val, bool trace); | |
990bbdad CW |
619 | }; |
620 | ||
907b28c5 CW |
621 | struct intel_uncore { |
622 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
623 | ||
624 | struct intel_uncore_funcs funcs; | |
625 | ||
626 | unsigned fifo_count; | |
48c1026a | 627 | enum forcewake_domains fw_domains; |
b2cff0db CW |
628 | |
629 | struct intel_uncore_forcewake_domain { | |
630 | struct drm_i915_private *i915; | |
48c1026a | 631 | enum forcewake_domain_id id; |
b2cff0db CW |
632 | unsigned wake_count; |
633 | struct timer_list timer; | |
05a2fb15 MK |
634 | u32 reg_set; |
635 | u32 val_set; | |
636 | u32 val_clear; | |
637 | u32 reg_ack; | |
638 | u32 reg_post; | |
639 | u32 val_reset; | |
b2cff0db | 640 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
b2cff0db CW |
641 | }; |
642 | ||
643 | /* Iterate over initialised fw domains */ | |
644 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ | |
645 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
646 | (i__) < FW_DOMAIN_ID_COUNT; \ | |
647 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ | |
648 | if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) | |
649 | ||
650 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ | |
651 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) | |
907b28c5 | 652 | |
79fc46df DL |
653 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
654 | func(is_mobile) sep \ | |
655 | func(is_i85x) sep \ | |
656 | func(is_i915g) sep \ | |
657 | func(is_i945gm) sep \ | |
658 | func(is_g33) sep \ | |
659 | func(need_gfx_hws) sep \ | |
660 | func(is_g4x) sep \ | |
661 | func(is_pineview) sep \ | |
662 | func(is_broadwater) sep \ | |
663 | func(is_crestline) sep \ | |
664 | func(is_ivybridge) sep \ | |
665 | func(is_valleyview) sep \ | |
666 | func(is_haswell) sep \ | |
7201c0b3 | 667 | func(is_skylake) sep \ |
b833d685 | 668 | func(is_preliminary) sep \ |
79fc46df DL |
669 | func(has_fbc) sep \ |
670 | func(has_pipe_cxsr) sep \ | |
671 | func(has_hotplug) sep \ | |
672 | func(cursor_needs_physical) sep \ | |
673 | func(has_overlay) sep \ | |
674 | func(overlay_needs_physical) sep \ | |
675 | func(supports_tv) sep \ | |
dd93be58 | 676 | func(has_llc) sep \ |
30568c45 DL |
677 | func(has_ddi) sep \ |
678 | func(has_fpga_dbg) | |
c96ea64e | 679 | |
a587f779 DL |
680 | #define DEFINE_FLAG(name) u8 name:1 |
681 | #define SEP_SEMICOLON ; | |
c96ea64e | 682 | |
cfdf1fa2 | 683 | struct intel_device_info { |
10fce67a | 684 | u32 display_mmio_offset; |
87f1f465 | 685 | u16 device_id; |
7eb552ae | 686 | u8 num_pipes:3; |
d615a166 | 687 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 688 | u8 gen; |
73ae478c | 689 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 690 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
691 | /* Register offsets for the various display pipes and transcoders */ |
692 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
693 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 694 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 695 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
696 | |
697 | /* Slice/subslice/EU info */ | |
698 | u8 slice_total; | |
699 | u8 subslice_total; | |
700 | u8 subslice_per_slice; | |
701 | u8 eu_total; | |
702 | u8 eu_per_subslice; | |
b7668791 DL |
703 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
704 | u8 subslice_7eu[3]; | |
3873218f JM |
705 | u8 has_slice_pg:1; |
706 | u8 has_subslice_pg:1; | |
707 | u8 has_eu_pg:1; | |
cfdf1fa2 KH |
708 | }; |
709 | ||
a587f779 DL |
710 | #undef DEFINE_FLAG |
711 | #undef SEP_SEMICOLON | |
712 | ||
7faf1ab2 DV |
713 | enum i915_cache_level { |
714 | I915_CACHE_NONE = 0, | |
350ec881 CW |
715 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
716 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
717 | caches, eg sampler/render caches, and the | |
718 | large Last-Level-Cache. LLC is coherent with | |
719 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 720 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
721 | }; |
722 | ||
e59ec13d MK |
723 | struct i915_ctx_hang_stats { |
724 | /* This context had batch pending when hang was declared */ | |
725 | unsigned batch_pending; | |
726 | ||
727 | /* This context had batch active when hang was declared */ | |
728 | unsigned batch_active; | |
be62acb4 MK |
729 | |
730 | /* Time when this context was last blamed for a GPU reset */ | |
731 | unsigned long guilty_ts; | |
732 | ||
676fa572 CW |
733 | /* If the contexts causes a second GPU hang within this time, |
734 | * it is permanently banned from submitting any more work. | |
735 | */ | |
736 | unsigned long ban_period_seconds; | |
737 | ||
be62acb4 MK |
738 | /* This context is banned to submit more work */ |
739 | bool banned; | |
e59ec13d | 740 | }; |
40521054 BW |
741 | |
742 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 743 | #define DEFAULT_CONTEXT_HANDLE 0 |
31b7a88d OM |
744 | /** |
745 | * struct intel_context - as the name implies, represents a context. | |
746 | * @ref: reference count. | |
747 | * @user_handle: userspace tracking identity for this context. | |
748 | * @remap_slice: l3 row remapping information. | |
749 | * @file_priv: filp associated with this context (NULL for global default | |
750 | * context). | |
751 | * @hang_stats: information about the role of this context in possible GPU | |
752 | * hangs. | |
753 | * @vm: virtual memory space used by this context. | |
754 | * @legacy_hw_ctx: render context backing object and whether it is correctly | |
755 | * initialized (legacy ring submission mechanism only). | |
756 | * @link: link in the global list of contexts. | |
757 | * | |
758 | * Contexts are memory images used by the hardware to store copies of their | |
759 | * internal state. | |
760 | */ | |
273497e5 | 761 | struct intel_context { |
dce3271b | 762 | struct kref ref; |
821d66dd | 763 | int user_handle; |
3ccfd19d | 764 | uint8_t remap_slice; |
40521054 | 765 | struct drm_i915_file_private *file_priv; |
e59ec13d | 766 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 767 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 768 | |
c9e003af | 769 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
770 | struct { |
771 | struct drm_i915_gem_object *rcs_state; | |
772 | bool initialized; | |
773 | } legacy_hw_ctx; | |
774 | ||
c9e003af | 775 | /* Execlists */ |
564ddb2f | 776 | bool rcs_initialized; |
c9e003af OM |
777 | struct { |
778 | struct drm_i915_gem_object *state; | |
84c2377f | 779 | struct intel_ringbuffer *ringbuf; |
a7cbedec | 780 | int pin_count; |
c9e003af OM |
781 | } engine[I915_NUM_RINGS]; |
782 | ||
a33afea5 | 783 | struct list_head link; |
40521054 BW |
784 | }; |
785 | ||
5c3fe8b0 | 786 | struct i915_fbc { |
60ee5cd2 | 787 | unsigned long uncompressed_size; |
5e59f717 | 788 | unsigned threshold; |
5c3fe8b0 | 789 | unsigned int fb_id; |
e35fef21 | 790 | struct intel_crtc *crtc; |
5c3fe8b0 BW |
791 | int y; |
792 | ||
c4213885 | 793 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
794 | struct drm_mm_node *compressed_llb; |
795 | ||
da46f936 RV |
796 | bool false_color; |
797 | ||
9adccc60 PZ |
798 | /* Tracks whether the HW is actually enabled, not whether the feature is |
799 | * possible. */ | |
800 | bool enabled; | |
801 | ||
1d73c2a8 RV |
802 | /* On gen8 some rings cannont perform fbc clean operation so for now |
803 | * we are doing this on SW with mmio. | |
804 | * This variable works in the opposite information direction | |
805 | * of ring->fbc_dirty telling software on frontbuffer tracking | |
806 | * to perform the cache clean on sw side. | |
807 | */ | |
808 | bool need_sw_cache_clean; | |
809 | ||
5c3fe8b0 BW |
810 | struct intel_fbc_work { |
811 | struct delayed_work work; | |
812 | struct drm_crtc *crtc; | |
813 | struct drm_framebuffer *fb; | |
5c3fe8b0 BW |
814 | } *fbc_work; |
815 | ||
29ebf90f CW |
816 | enum no_fbc_reason { |
817 | FBC_OK, /* FBC is enabled */ | |
818 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
819 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
820 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
821 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
822 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
823 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
824 | FBC_NOT_TILED, /* buffer not tiled */ | |
825 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
826 | FBC_MODULE_PARAM, | |
827 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
828 | } no_fbc_reason; | |
b5e50c3f JB |
829 | }; |
830 | ||
96178eeb VK |
831 | /** |
832 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
833 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
834 | * parsing for same resolution. | |
835 | */ | |
836 | enum drrs_refresh_rate_type { | |
837 | DRRS_HIGH_RR, | |
838 | DRRS_LOW_RR, | |
839 | DRRS_MAX_RR, /* RR count */ | |
840 | }; | |
841 | ||
842 | enum drrs_support_type { | |
843 | DRRS_NOT_SUPPORTED = 0, | |
844 | STATIC_DRRS_SUPPORT = 1, | |
845 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
846 | }; |
847 | ||
2807cf69 | 848 | struct intel_dp; |
96178eeb VK |
849 | struct i915_drrs { |
850 | struct mutex mutex; | |
851 | struct delayed_work work; | |
852 | struct intel_dp *dp; | |
853 | unsigned busy_frontbuffer_bits; | |
854 | enum drrs_refresh_rate_type refresh_rate_type; | |
855 | enum drrs_support_type type; | |
856 | }; | |
857 | ||
a031d709 | 858 | struct i915_psr { |
f0355c4a | 859 | struct mutex lock; |
a031d709 RV |
860 | bool sink_support; |
861 | bool source_ok; | |
2807cf69 | 862 | struct intel_dp *enabled; |
7c8f8a70 RV |
863 | bool active; |
864 | struct delayed_work work; | |
9ca15301 | 865 | unsigned busy_frontbuffer_bits; |
0243f7ba | 866 | bool link_standby; |
3f51e471 | 867 | }; |
5c3fe8b0 | 868 | |
3bad0781 | 869 | enum intel_pch { |
f0350830 | 870 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
871 | PCH_IBX, /* Ibexpeak PCH */ |
872 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 873 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 874 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 875 | PCH_NOP, |
3bad0781 ZW |
876 | }; |
877 | ||
988d6ee8 PZ |
878 | enum intel_sbi_destination { |
879 | SBI_ICLK, | |
880 | SBI_MPHY, | |
881 | }; | |
882 | ||
b690e96c | 883 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 884 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 885 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 886 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 887 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 888 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 889 | |
8be48d92 | 890 | struct intel_fbdev; |
1630fe75 | 891 | struct intel_fbc_work; |
38651674 | 892 | |
c2b9152f DV |
893 | struct intel_gmbus { |
894 | struct i2c_adapter adapter; | |
f2ce9faf | 895 | u32 force_bit; |
c2b9152f | 896 | u32 reg0; |
36c785f0 | 897 | u32 gpio_reg; |
c167a6fc | 898 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
899 | struct drm_i915_private *dev_priv; |
900 | }; | |
901 | ||
f4c956ad | 902 | struct i915_suspend_saved_registers { |
e948e994 | 903 | u32 saveDSPARB; |
ba8bbcf6 | 904 | u32 saveLVDS; |
585fb111 JB |
905 | u32 savePP_ON_DELAYS; |
906 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
907 | u32 savePP_ON; |
908 | u32 savePP_OFF; | |
909 | u32 savePP_CONTROL; | |
585fb111 | 910 | u32 savePP_DIVISOR; |
ba8bbcf6 | 911 | u32 saveFBC_CONTROL; |
1f84e550 | 912 | u32 saveCACHE_MODE_0; |
1f84e550 | 913 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
914 | u32 saveSWF0[16]; |
915 | u32 saveSWF1[16]; | |
916 | u32 saveSWF2[3]; | |
4b9de737 | 917 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 918 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 919 | u16 saveGCDGMBUS; |
f4c956ad | 920 | }; |
c85aa885 | 921 | |
ddeea5b0 ID |
922 | struct vlv_s0ix_state { |
923 | /* GAM */ | |
924 | u32 wr_watermark; | |
925 | u32 gfx_prio_ctrl; | |
926 | u32 arb_mode; | |
927 | u32 gfx_pend_tlb0; | |
928 | u32 gfx_pend_tlb1; | |
929 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
930 | u32 media_max_req_count; | |
931 | u32 gfx_max_req_count; | |
932 | u32 render_hwsp; | |
933 | u32 ecochk; | |
934 | u32 bsd_hwsp; | |
935 | u32 blt_hwsp; | |
936 | u32 tlb_rd_addr; | |
937 | ||
938 | /* MBC */ | |
939 | u32 g3dctl; | |
940 | u32 gsckgctl; | |
941 | u32 mbctl; | |
942 | ||
943 | /* GCP */ | |
944 | u32 ucgctl1; | |
945 | u32 ucgctl3; | |
946 | u32 rcgctl1; | |
947 | u32 rcgctl2; | |
948 | u32 rstctl; | |
949 | u32 misccpctl; | |
950 | ||
951 | /* GPM */ | |
952 | u32 gfxpause; | |
953 | u32 rpdeuhwtc; | |
954 | u32 rpdeuc; | |
955 | u32 ecobus; | |
956 | u32 pwrdwnupctl; | |
957 | u32 rp_down_timeout; | |
958 | u32 rp_deucsw; | |
959 | u32 rcubmabdtmr; | |
960 | u32 rcedata; | |
961 | u32 spare2gh; | |
962 | ||
963 | /* Display 1 CZ domain */ | |
964 | u32 gt_imr; | |
965 | u32 gt_ier; | |
966 | u32 pm_imr; | |
967 | u32 pm_ier; | |
968 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
969 | ||
970 | /* GT SA CZ domain */ | |
971 | u32 tilectl; | |
972 | u32 gt_fifoctl; | |
973 | u32 gtlc_wake_ctrl; | |
974 | u32 gtlc_survive; | |
975 | u32 pmwgicz; | |
976 | ||
977 | /* Display 2 CZ domain */ | |
978 | u32 gu_ctl0; | |
979 | u32 gu_ctl1; | |
980 | u32 clock_gate_dis2; | |
981 | }; | |
982 | ||
bf225f20 CW |
983 | struct intel_rps_ei { |
984 | u32 cz_clock; | |
985 | u32 render_c0; | |
986 | u32 media_c0; | |
31685c25 D |
987 | }; |
988 | ||
c85aa885 | 989 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
990 | /* |
991 | * work, interrupts_enabled and pm_iir are protected by | |
992 | * dev_priv->irq_lock | |
993 | */ | |
c85aa885 | 994 | struct work_struct work; |
d4d70aa5 | 995 | bool interrupts_enabled; |
c85aa885 | 996 | u32 pm_iir; |
59cdb63d | 997 | |
b39fb297 BW |
998 | /* Frequencies are stored in potentially platform dependent multiples. |
999 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1000 | * Soft limits are those which are used for the dynamic reclocking done | |
1001 | * by the driver (raise frequencies under heavy loads, and lower for | |
1002 | * lighter loads). Hard limits are those imposed by the hardware. | |
1003 | * | |
1004 | * A distinction is made for overclocking, which is never enabled by | |
1005 | * default, and is considered to be above the hard limit if it's | |
1006 | * possible at all. | |
1007 | */ | |
1008 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1009 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1010 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1011 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1012 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
1013 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ | |
1014 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1015 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
67c3bf6f | 1016 | u32 cz_freq; |
1a01ab3b | 1017 | |
31685c25 | 1018 | u32 ei_interrupt_count; |
1a01ab3b | 1019 | |
dd75fdc8 CW |
1020 | int last_adj; |
1021 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1022 | ||
c0951f0c | 1023 | bool enabled; |
1a01ab3b | 1024 | struct delayed_work delayed_resume_work; |
4fc688ce | 1025 | |
bf225f20 CW |
1026 | /* manual wa residency calculations */ |
1027 | struct intel_rps_ei up_ei, down_ei; | |
1028 | ||
4fc688ce JB |
1029 | /* |
1030 | * Protects RPS/RC6 register access and PCU communication. | |
1031 | * Must be taken after struct_mutex if nested. | |
1032 | */ | |
1033 | struct mutex hw_lock; | |
c85aa885 DV |
1034 | }; |
1035 | ||
1a240d4d DV |
1036 | /* defined intel_pm.c */ |
1037 | extern spinlock_t mchdev_lock; | |
1038 | ||
c85aa885 DV |
1039 | struct intel_ilk_power_mgmt { |
1040 | u8 cur_delay; | |
1041 | u8 min_delay; | |
1042 | u8 max_delay; | |
1043 | u8 fmax; | |
1044 | u8 fstart; | |
1045 | ||
1046 | u64 last_count1; | |
1047 | unsigned long last_time1; | |
1048 | unsigned long chipset_power; | |
1049 | u64 last_count2; | |
5ed0bdf2 | 1050 | u64 last_time2; |
c85aa885 DV |
1051 | unsigned long gfx_power; |
1052 | u8 corr; | |
1053 | ||
1054 | int c_m; | |
1055 | int r_t; | |
3e373948 DV |
1056 | |
1057 | struct drm_i915_gem_object *pwrctx; | |
1058 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
1059 | }; |
1060 | ||
c6cb582e ID |
1061 | struct drm_i915_private; |
1062 | struct i915_power_well; | |
1063 | ||
1064 | struct i915_power_well_ops { | |
1065 | /* | |
1066 | * Synchronize the well's hw state to match the current sw state, for | |
1067 | * example enable/disable it based on the current refcount. Called | |
1068 | * during driver init and resume time, possibly after first calling | |
1069 | * the enable/disable handlers. | |
1070 | */ | |
1071 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1072 | struct i915_power_well *power_well); | |
1073 | /* | |
1074 | * Enable the well and resources that depend on it (for example | |
1075 | * interrupts located on the well). Called after the 0->1 refcount | |
1076 | * transition. | |
1077 | */ | |
1078 | void (*enable)(struct drm_i915_private *dev_priv, | |
1079 | struct i915_power_well *power_well); | |
1080 | /* | |
1081 | * Disable the well and resources that depend on it. Called after | |
1082 | * the 1->0 refcount transition. | |
1083 | */ | |
1084 | void (*disable)(struct drm_i915_private *dev_priv, | |
1085 | struct i915_power_well *power_well); | |
1086 | /* Returns the hw enabled state. */ | |
1087 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1088 | struct i915_power_well *power_well); | |
1089 | }; | |
1090 | ||
a38911a3 WX |
1091 | /* Power well structure for haswell */ |
1092 | struct i915_power_well { | |
c1ca727f | 1093 | const char *name; |
6f3ef5dd | 1094 | bool always_on; |
a38911a3 WX |
1095 | /* power well enable/disable usage count */ |
1096 | int count; | |
bfafe93a ID |
1097 | /* cached hw enabled state */ |
1098 | bool hw_enabled; | |
c1ca727f | 1099 | unsigned long domains; |
77961eb9 | 1100 | unsigned long data; |
c6cb582e | 1101 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1102 | }; |
1103 | ||
83c00f55 | 1104 | struct i915_power_domains { |
baa70707 ID |
1105 | /* |
1106 | * Power wells needed for initialization at driver init and suspend | |
1107 | * time are on. They are kept on until after the first modeset. | |
1108 | */ | |
1109 | bool init_power_on; | |
0d116a29 | 1110 | bool initializing; |
c1ca727f | 1111 | int power_well_count; |
baa70707 | 1112 | |
83c00f55 | 1113 | struct mutex lock; |
1da51581 | 1114 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1115 | struct i915_power_well *power_wells; |
83c00f55 ID |
1116 | }; |
1117 | ||
35a85ac6 | 1118 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1119 | struct intel_l3_parity { |
35a85ac6 | 1120 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1121 | struct work_struct error_work; |
35a85ac6 | 1122 | int which_slice; |
a4da4fa4 DV |
1123 | }; |
1124 | ||
493018dc BV |
1125 | struct i915_gem_batch_pool { |
1126 | struct drm_device *dev; | |
1127 | struct list_head cache_list; | |
1128 | }; | |
1129 | ||
4b5aed62 | 1130 | struct i915_gem_mm { |
4b5aed62 DV |
1131 | /** Memory allocator for GTT stolen memory */ |
1132 | struct drm_mm stolen; | |
4b5aed62 DV |
1133 | /** List of all objects in gtt_space. Used to restore gtt |
1134 | * mappings on resume */ | |
1135 | struct list_head bound_list; | |
1136 | /** | |
1137 | * List of objects which are not bound to the GTT (thus | |
1138 | * are idle and not used by the GPU) but still have | |
1139 | * (presumably uncached) pages still attached. | |
1140 | */ | |
1141 | struct list_head unbound_list; | |
1142 | ||
493018dc BV |
1143 | /* |
1144 | * A pool of objects to use as shadow copies of client batch buffers | |
1145 | * when the command parser is enabled. Prevents the client from | |
1146 | * modifying the batch contents after software parsing. | |
1147 | */ | |
1148 | struct i915_gem_batch_pool batch_pool; | |
1149 | ||
4b5aed62 DV |
1150 | /** Usable portion of the GTT for GEM */ |
1151 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1152 | ||
4b5aed62 DV |
1153 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1154 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1155 | ||
2cfcd32a | 1156 | struct notifier_block oom_notifier; |
ceabbba5 | 1157 | struct shrinker shrinker; |
4b5aed62 DV |
1158 | bool shrinker_no_lock_stealing; |
1159 | ||
4b5aed62 DV |
1160 | /** LRU list of objects with fence regs on them. */ |
1161 | struct list_head fence_list; | |
1162 | ||
1163 | /** | |
1164 | * We leave the user IRQ off as much as possible, | |
1165 | * but this means that requests will finish and never | |
1166 | * be retired once the system goes idle. Set a timer to | |
1167 | * fire periodically while the ring is running. When it | |
1168 | * fires, go retire requests. | |
1169 | */ | |
1170 | struct delayed_work retire_work; | |
1171 | ||
b29c19b6 CW |
1172 | /** |
1173 | * When we detect an idle GPU, we want to turn on | |
1174 | * powersaving features. So once we see that there | |
1175 | * are no more requests outstanding and no more | |
1176 | * arrive within a small period of time, we fire | |
1177 | * off the idle_work. | |
1178 | */ | |
1179 | struct delayed_work idle_work; | |
1180 | ||
4b5aed62 DV |
1181 | /** |
1182 | * Are we in a non-interruptible section of code like | |
1183 | * modesetting? | |
1184 | */ | |
1185 | bool interruptible; | |
1186 | ||
f62a0076 CW |
1187 | /** |
1188 | * Is the GPU currently considered idle, or busy executing userspace | |
1189 | * requests? Whilst idle, we attempt to power down the hardware and | |
1190 | * display clocks. In order to reduce the effect on performance, there | |
1191 | * is a slight delay before we do so. | |
1192 | */ | |
1193 | bool busy; | |
1194 | ||
bdf1e7e3 DV |
1195 | /* the indicator for dispatch video commands on two BSD rings */ |
1196 | int bsd_ring_dispatch_index; | |
1197 | ||
4b5aed62 DV |
1198 | /** Bit 6 swizzling required for X tiling */ |
1199 | uint32_t bit_6_swizzle_x; | |
1200 | /** Bit 6 swizzling required for Y tiling */ | |
1201 | uint32_t bit_6_swizzle_y; | |
1202 | ||
4b5aed62 | 1203 | /* accounting, useful for userland debugging */ |
c20e8355 | 1204 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1205 | size_t object_memory; |
1206 | u32 object_count; | |
1207 | }; | |
1208 | ||
edc3d884 | 1209 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1210 | struct drm_i915_private *i915; |
edc3d884 MK |
1211 | unsigned bytes; |
1212 | unsigned size; | |
1213 | int err; | |
1214 | u8 *buf; | |
1215 | loff_t start; | |
1216 | loff_t pos; | |
1217 | }; | |
1218 | ||
fc16b48b MK |
1219 | struct i915_error_state_file_priv { |
1220 | struct drm_device *dev; | |
1221 | struct drm_i915_error_state *error; | |
1222 | }; | |
1223 | ||
99584db3 DV |
1224 | struct i915_gpu_error { |
1225 | /* For hangcheck timer */ | |
1226 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1227 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1228 | /* Hang gpu twice in this window and your context gets banned */ |
1229 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1230 | ||
737b1506 CW |
1231 | struct workqueue_struct *hangcheck_wq; |
1232 | struct delayed_work hangcheck_work; | |
99584db3 DV |
1233 | |
1234 | /* For reset and error_state handling. */ | |
1235 | spinlock_t lock; | |
1236 | /* Protected by the above dev->gpu_error.lock. */ | |
1237 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1238 | |
1239 | unsigned long missed_irq_rings; | |
1240 | ||
1f83fee0 | 1241 | /** |
2ac0f450 | 1242 | * State variable controlling the reset flow and count |
1f83fee0 | 1243 | * |
2ac0f450 MK |
1244 | * This is a counter which gets incremented when reset is triggered, |
1245 | * and again when reset has been handled. So odd values (lowest bit set) | |
1246 | * means that reset is in progress and even values that | |
1247 | * (reset_counter >> 1):th reset was successfully completed. | |
1248 | * | |
1249 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1250 | * set meaning that hardware is terminally sour and there is no | |
1251 | * recovery. All waiters on the reset_queue will be woken when | |
1252 | * that happens. | |
1253 | * | |
1254 | * This counter is used by the wait_seqno code to notice that reset | |
1255 | * event happened and it needs to restart the entire ioctl (since most | |
1256 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1257 | * |
1258 | * This is important for lock-free wait paths, where no contended lock | |
1259 | * naturally enforces the correct ordering between the bail-out of the | |
1260 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1261 | */ |
1262 | atomic_t reset_counter; | |
1263 | ||
1f83fee0 | 1264 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1265 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1266 | |
1267 | /** | |
1268 | * Waitqueue to signal when the reset has completed. Used by clients | |
1269 | * that wait for dev_priv->mm.wedged to settle. | |
1270 | */ | |
1271 | wait_queue_head_t reset_queue; | |
33196ded | 1272 | |
88b4aa87 MK |
1273 | /* Userspace knobs for gpu hang simulation; |
1274 | * combines both a ring mask, and extra flags | |
1275 | */ | |
1276 | u32 stop_rings; | |
1277 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1278 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1279 | |
1280 | /* For missed irq/seqno simulation. */ | |
1281 | unsigned int test_irq_rings; | |
6689c167 MA |
1282 | |
1283 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1284 | bool reload_in_reset; | |
99584db3 DV |
1285 | }; |
1286 | ||
b8efb17b ZR |
1287 | enum modeset_restore { |
1288 | MODESET_ON_LID_OPEN, | |
1289 | MODESET_DONE, | |
1290 | MODESET_SUSPENDED, | |
1291 | }; | |
1292 | ||
6acab15a | 1293 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1294 | /* |
1295 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1296 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1297 | * populate this field. | |
1298 | */ | |
1299 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1300 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1301 | |
1302 | uint8_t supports_dvi:1; | |
1303 | uint8_t supports_hdmi:1; | |
1304 | uint8_t supports_dp:1; | |
6acab15a PZ |
1305 | }; |
1306 | ||
bfd7ebda RV |
1307 | enum psr_lines_to_wait { |
1308 | PSR_0_LINES_TO_WAIT = 0, | |
1309 | PSR_1_LINE_TO_WAIT, | |
1310 | PSR_4_LINES_TO_WAIT, | |
1311 | PSR_8_LINES_TO_WAIT | |
1312 | }; | |
1313 | ||
41aa3448 RV |
1314 | struct intel_vbt_data { |
1315 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1316 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1317 | ||
1318 | /* Feature bits */ | |
1319 | unsigned int int_tv_support:1; | |
1320 | unsigned int lvds_dither:1; | |
1321 | unsigned int lvds_vbt:1; | |
1322 | unsigned int int_crt_support:1; | |
1323 | unsigned int lvds_use_ssc:1; | |
1324 | unsigned int display_clock_mode:1; | |
1325 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1326 | unsigned int has_mipi:1; |
41aa3448 RV |
1327 | int lvds_ssc_freq; |
1328 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1329 | ||
83a7280e PB |
1330 | enum drrs_support_type drrs_type; |
1331 | ||
41aa3448 RV |
1332 | /* eDP */ |
1333 | int edp_rate; | |
1334 | int edp_lanes; | |
1335 | int edp_preemphasis; | |
1336 | int edp_vswing; | |
1337 | bool edp_initialized; | |
1338 | bool edp_support; | |
1339 | int edp_bpp; | |
9a57f5bb | 1340 | bool edp_low_vswing; |
41aa3448 RV |
1341 | struct edp_power_seq edp_pps; |
1342 | ||
bfd7ebda RV |
1343 | struct { |
1344 | bool full_link; | |
1345 | bool require_aux_wakeup; | |
1346 | int idle_frames; | |
1347 | enum psr_lines_to_wait lines_to_wait; | |
1348 | int tp1_wakeup_time; | |
1349 | int tp2_tp3_wakeup_time; | |
1350 | } psr; | |
1351 | ||
f00076d2 JN |
1352 | struct { |
1353 | u16 pwm_freq_hz; | |
39fbc9c8 | 1354 | bool present; |
f00076d2 | 1355 | bool active_low_pwm; |
1de6068e | 1356 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1357 | } backlight; |
1358 | ||
d17c5443 SK |
1359 | /* MIPI DSI */ |
1360 | struct { | |
3e6bd011 | 1361 | u16 port; |
d17c5443 | 1362 | u16 panel_id; |
d3b542fc SK |
1363 | struct mipi_config *config; |
1364 | struct mipi_pps_data *pps; | |
1365 | u8 seq_version; | |
1366 | u32 size; | |
1367 | u8 *data; | |
1368 | u8 *sequence[MIPI_SEQ_MAX]; | |
d17c5443 SK |
1369 | } dsi; |
1370 | ||
41aa3448 RV |
1371 | int crt_ddc_pin; |
1372 | ||
1373 | int child_dev_num; | |
768f69c9 | 1374 | union child_device_config *child_dev; |
6acab15a PZ |
1375 | |
1376 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1377 | }; |
1378 | ||
77c122bc VS |
1379 | enum intel_ddb_partitioning { |
1380 | INTEL_DDB_PART_1_2, | |
1381 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1382 | }; | |
1383 | ||
1fd527cc VS |
1384 | struct intel_wm_level { |
1385 | bool enable; | |
1386 | uint32_t pri_val; | |
1387 | uint32_t spr_val; | |
1388 | uint32_t cur_val; | |
1389 | uint32_t fbc_val; | |
1390 | }; | |
1391 | ||
820c1980 | 1392 | struct ilk_wm_values { |
609cedef VS |
1393 | uint32_t wm_pipe[3]; |
1394 | uint32_t wm_lp[3]; | |
1395 | uint32_t wm_lp_spr[3]; | |
1396 | uint32_t wm_linetime[3]; | |
1397 | bool enable_fbc_wm; | |
1398 | enum intel_ddb_partitioning partitioning; | |
1399 | }; | |
1400 | ||
c193924e | 1401 | struct skl_ddb_entry { |
16160e3d | 1402 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1403 | }; |
1404 | ||
1405 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1406 | { | |
16160e3d | 1407 | return entry->end - entry->start; |
c193924e DL |
1408 | } |
1409 | ||
08db6652 DL |
1410 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1411 | const struct skl_ddb_entry *e2) | |
1412 | { | |
1413 | if (e1->start == e2->start && e1->end == e2->end) | |
1414 | return true; | |
1415 | ||
1416 | return false; | |
1417 | } | |
1418 | ||
c193924e | 1419 | struct skl_ddb_allocation { |
34bb56af | 1420 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
c193924e DL |
1421 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
1422 | struct skl_ddb_entry cursor[I915_MAX_PIPES]; | |
1423 | }; | |
1424 | ||
2ac96d2a PB |
1425 | struct skl_wm_values { |
1426 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1427 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1428 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1429 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
1430 | uint32_t cursor[I915_MAX_PIPES][8]; | |
1431 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1432 | uint32_t cursor_trans[I915_MAX_PIPES]; | |
1433 | }; | |
1434 | ||
1435 | struct skl_wm_level { | |
1436 | bool plane_en[I915_MAX_PLANES]; | |
b99f58da | 1437 | bool cursor_en; |
2ac96d2a PB |
1438 | uint16_t plane_res_b[I915_MAX_PLANES]; |
1439 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1440 | uint16_t cursor_res_b; |
1441 | uint8_t cursor_res_l; | |
1442 | }; | |
1443 | ||
c67a470b | 1444 | /* |
765dab67 PZ |
1445 | * This struct helps tracking the state needed for runtime PM, which puts the |
1446 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1447 | * graphics device works, even register access, so we don't get interrupts nor | |
1448 | * anything else. | |
c67a470b | 1449 | * |
765dab67 PZ |
1450 | * Every piece of our code that needs to actually touch the hardware needs to |
1451 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1452 | * appropriate power domain. | |
a8a8bd54 | 1453 | * |
765dab67 PZ |
1454 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1455 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1456 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1457 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1458 | * |
1459 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1460 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1461 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1462 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1463 | * case it happens. |
c67a470b | 1464 | * |
765dab67 | 1465 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1466 | */ |
5d584b2e PZ |
1467 | struct i915_runtime_pm { |
1468 | bool suspended; | |
2aeb7d3a | 1469 | bool irqs_enabled; |
c67a470b PZ |
1470 | }; |
1471 | ||
926321d5 DV |
1472 | enum intel_pipe_crc_source { |
1473 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1474 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1475 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1476 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1477 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1478 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1479 | INTEL_PIPE_CRC_SOURCE_TV, | |
1480 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1481 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1482 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1483 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1484 | INTEL_PIPE_CRC_SOURCE_MAX, |
1485 | }; | |
1486 | ||
8bf1e9f1 | 1487 | struct intel_pipe_crc_entry { |
ac2300d4 | 1488 | uint32_t frame; |
8bf1e9f1 SH |
1489 | uint32_t crc[5]; |
1490 | }; | |
1491 | ||
b2c88f5b | 1492 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1493 | struct intel_pipe_crc { |
d538bbdf DL |
1494 | spinlock_t lock; |
1495 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1496 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1497 | enum intel_pipe_crc_source source; |
d538bbdf | 1498 | int head, tail; |
07144428 | 1499 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1500 | }; |
1501 | ||
f99d7069 DV |
1502 | struct i915_frontbuffer_tracking { |
1503 | struct mutex lock; | |
1504 | ||
1505 | /* | |
1506 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1507 | * scheduled flips. | |
1508 | */ | |
1509 | unsigned busy_bits; | |
1510 | unsigned flip_bits; | |
1511 | }; | |
1512 | ||
7225342a MK |
1513 | struct i915_wa_reg { |
1514 | u32 addr; | |
1515 | u32 value; | |
1516 | /* bitmask representing WA bits */ | |
1517 | u32 mask; | |
1518 | }; | |
1519 | ||
1520 | #define I915_MAX_WA_REGS 16 | |
1521 | ||
1522 | struct i915_workarounds { | |
1523 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1524 | u32 count; | |
1525 | }; | |
1526 | ||
cf9d2890 YZ |
1527 | struct i915_virtual_gpu { |
1528 | bool active; | |
1529 | }; | |
1530 | ||
77fec556 | 1531 | struct drm_i915_private { |
f4c956ad | 1532 | struct drm_device *dev; |
42dcedd4 | 1533 | struct kmem_cache *slab; |
f4c956ad | 1534 | |
5c969aa7 | 1535 | const struct intel_device_info info; |
f4c956ad DV |
1536 | |
1537 | int relative_constants_mode; | |
1538 | ||
1539 | void __iomem *regs; | |
1540 | ||
907b28c5 | 1541 | struct intel_uncore uncore; |
f4c956ad | 1542 | |
cf9d2890 YZ |
1543 | struct i915_virtual_gpu vgpu; |
1544 | ||
f4c956ad DV |
1545 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
1546 | ||
28c70f16 | 1547 | |
f4c956ad DV |
1548 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1549 | * controller on different i2c buses. */ | |
1550 | struct mutex gmbus_mutex; | |
1551 | ||
1552 | /** | |
1553 | * Base address of the gmbus and gpio block. | |
1554 | */ | |
1555 | uint32_t gpio_mmio_base; | |
1556 | ||
b6fdd0f2 SS |
1557 | /* MMIO base address for MIPI regs */ |
1558 | uint32_t mipi_mmio_base; | |
1559 | ||
28c70f16 DV |
1560 | wait_queue_head_t gmbus_wait_queue; |
1561 | ||
f4c956ad | 1562 | struct pci_dev *bridge_dev; |
a4872ba6 | 1563 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1564 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1565 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1566 | |
ba8286fa | 1567 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1568 | struct resource mch_res; |
1569 | ||
f4c956ad DV |
1570 | /* protects the irq masks */ |
1571 | spinlock_t irq_lock; | |
1572 | ||
84c33a64 SG |
1573 | /* protects the mmio flip data */ |
1574 | spinlock_t mmio_flip_lock; | |
1575 | ||
f8b79e58 ID |
1576 | bool display_irqs_enabled; |
1577 | ||
9ee32fea DV |
1578 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1579 | struct pm_qos_request pm_qos; | |
1580 | ||
f4c956ad | 1581 | /* DPIO indirect register protection */ |
09153000 | 1582 | struct mutex dpio_lock; |
f4c956ad DV |
1583 | |
1584 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1585 | union { |
1586 | u32 irq_mask; | |
1587 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1588 | }; | |
f4c956ad | 1589 | u32 gt_irq_mask; |
605cd25b | 1590 | u32 pm_irq_mask; |
a6706b45 | 1591 | u32 pm_rps_events; |
91d181dd | 1592 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1593 | |
f4c956ad | 1594 | struct work_struct hotplug_work; |
b543fb04 EE |
1595 | struct { |
1596 | unsigned long hpd_last_jiffies; | |
1597 | int hpd_cnt; | |
1598 | enum { | |
1599 | HPD_ENABLED = 0, | |
1600 | HPD_DISABLED = 1, | |
1601 | HPD_MARK_DISABLED = 2 | |
1602 | } hpd_mark; | |
1603 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 1604 | u32 hpd_event_bits; |
6323751d | 1605 | struct delayed_work hotplug_reenable_work; |
f4c956ad | 1606 | |
5c3fe8b0 | 1607 | struct i915_fbc fbc; |
439d7ac0 | 1608 | struct i915_drrs drrs; |
f4c956ad | 1609 | struct intel_opregion opregion; |
41aa3448 | 1610 | struct intel_vbt_data vbt; |
f4c956ad | 1611 | |
d9ceb816 JB |
1612 | bool preserve_bios_swizzle; |
1613 | ||
f4c956ad DV |
1614 | /* overlay */ |
1615 | struct intel_overlay *overlay; | |
f4c956ad | 1616 | |
58c68779 | 1617 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1618 | struct mutex backlight_lock; |
31ad8ec6 | 1619 | |
f4c956ad | 1620 | /* LVDS info */ |
f4c956ad DV |
1621 | bool no_aux_handshake; |
1622 | ||
e39b999a VS |
1623 | /* protects panel power sequencer state */ |
1624 | struct mutex pps_mutex; | |
1625 | ||
f4c956ad DV |
1626 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1627 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1628 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1629 | ||
1630 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
d60c4473 | 1631 | unsigned int vlv_cdclk_freq; |
6bcda4f0 | 1632 | unsigned int hpll_freq; |
f4c956ad | 1633 | |
645416f5 DV |
1634 | /** |
1635 | * wq - Driver workqueue for GEM. | |
1636 | * | |
1637 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1638 | * locks, for otherwise the flushing done in the pageflip code will | |
1639 | * result in deadlocks. | |
1640 | */ | |
f4c956ad DV |
1641 | struct workqueue_struct *wq; |
1642 | ||
1643 | /* Display functions */ | |
1644 | struct drm_i915_display_funcs display; | |
1645 | ||
1646 | /* PCH chipset type */ | |
1647 | enum intel_pch pch_type; | |
17a303ec | 1648 | unsigned short pch_id; |
f4c956ad DV |
1649 | |
1650 | unsigned long quirks; | |
1651 | ||
b8efb17b ZR |
1652 | enum modeset_restore modeset_restore; |
1653 | struct mutex modeset_restore_lock; | |
673a394b | 1654 | |
a7bbbd63 | 1655 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1656 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1657 | |
4b5aed62 | 1658 | struct i915_gem_mm mm; |
ad46cb53 CW |
1659 | DECLARE_HASHTABLE(mm_structs, 7); |
1660 | struct mutex mm_lock; | |
8781342d | 1661 | |
8781342d DV |
1662 | /* Kernel Modesetting */ |
1663 | ||
9b9d172d | 1664 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1665 | |
76c4ac04 DL |
1666 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1667 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1668 | wait_queue_head_t pending_flip_queue; |
1669 | ||
c4597872 DV |
1670 | #ifdef CONFIG_DEBUG_FS |
1671 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1672 | #endif | |
1673 | ||
e72f9fbf DV |
1674 | int num_shared_dpll; |
1675 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
e4607fcf | 1676 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1677 | |
7225342a | 1678 | struct i915_workarounds workarounds; |
888b5995 | 1679 | |
652c393a JB |
1680 | /* Reclocking support */ |
1681 | bool render_reclock_avail; | |
1682 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1683 | /* indicates the reduced downclock for LVDS*/ |
1684 | int lvds_downclock; | |
f99d7069 DV |
1685 | |
1686 | struct i915_frontbuffer_tracking fb_tracking; | |
1687 | ||
652c393a | 1688 | u16 orig_clock; |
f97108d1 | 1689 | |
c4804411 | 1690 | bool mchbar_need_disable; |
f97108d1 | 1691 | |
a4da4fa4 DV |
1692 | struct intel_l3_parity l3_parity; |
1693 | ||
59124506 BW |
1694 | /* Cannot be determined by PCIID. You must always read a register. */ |
1695 | size_t ellc_size; | |
1696 | ||
c6a828d3 | 1697 | /* gen6+ rps state */ |
c85aa885 | 1698 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1699 | |
20e4d407 DV |
1700 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1701 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1702 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1703 | |
83c00f55 | 1704 | struct i915_power_domains power_domains; |
a38911a3 | 1705 | |
a031d709 | 1706 | struct i915_psr psr; |
3f51e471 | 1707 | |
99584db3 | 1708 | struct i915_gpu_error gpu_error; |
ae681d96 | 1709 | |
c9cddffc JB |
1710 | struct drm_i915_gem_object *vlv_pctx; |
1711 | ||
4520f53a | 1712 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1713 | /* list of fbdev register on this device */ |
1714 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1715 | struct work_struct fbdev_suspend_work; |
4520f53a | 1716 | #endif |
e953fd7b CW |
1717 | |
1718 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1719 | struct drm_property *force_audio_property; |
e3689190 | 1720 | |
58fddc28 ID |
1721 | /* hda/i915 audio component */ |
1722 | bool audio_component_registered; | |
1723 | ||
254f965c | 1724 | uint32_t hw_context_size; |
a33afea5 | 1725 | struct list_head context_list; |
f4c956ad | 1726 | |
3e68320e | 1727 | u32 fdi_rx_config; |
68d18ad7 | 1728 | |
842f1c8b | 1729 | u32 suspend_count; |
f4c956ad | 1730 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1731 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1732 | |
53615a5e VS |
1733 | struct { |
1734 | /* | |
1735 | * Raw watermark latency values: | |
1736 | * in 0.1us units for WM0, | |
1737 | * in 0.5us units for WM1+. | |
1738 | */ | |
1739 | /* primary */ | |
1740 | uint16_t pri_latency[5]; | |
1741 | /* sprite */ | |
1742 | uint16_t spr_latency[5]; | |
1743 | /* cursor */ | |
1744 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1745 | /* |
1746 | * Raw watermark memory latency values | |
1747 | * for SKL for all 8 levels | |
1748 | * in 1us units. | |
1749 | */ | |
1750 | uint16_t skl_latency[8]; | |
609cedef | 1751 | |
2d41c0b5 PB |
1752 | /* |
1753 | * The skl_wm_values structure is a bit too big for stack | |
1754 | * allocation, so we keep the staging struct where we store | |
1755 | * intermediate results here instead. | |
1756 | */ | |
1757 | struct skl_wm_values skl_results; | |
1758 | ||
609cedef | 1759 | /* current hardware state */ |
2d41c0b5 PB |
1760 | union { |
1761 | struct ilk_wm_values hw; | |
1762 | struct skl_wm_values skl_hw; | |
1763 | }; | |
53615a5e VS |
1764 | } wm; |
1765 | ||
8a187455 PZ |
1766 | struct i915_runtime_pm pm; |
1767 | ||
13cf5504 DA |
1768 | struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; |
1769 | u32 long_hpd_port_mask; | |
1770 | u32 short_hpd_port_mask; | |
1771 | struct work_struct dig_port_work; | |
1772 | ||
0e32b39c DA |
1773 | /* |
1774 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
1775 | * the non-DP HPD could block the workqueue on a mode config | |
1776 | * mutex getting, that userspace may have taken. However | |
1777 | * userspace is waiting on the DP workqueue to run which is | |
1778 | * blocked behind the non-DP one. | |
1779 | */ | |
1780 | struct workqueue_struct *dp_wq; | |
1781 | ||
a83014d3 OM |
1782 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1783 | struct { | |
1784 | int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, | |
1785 | struct intel_engine_cs *ring, | |
1786 | struct intel_context *ctx, | |
1787 | struct drm_i915_gem_execbuffer2 *args, | |
1788 | struct list_head *vmas, | |
1789 | struct drm_i915_gem_object *batch_obj, | |
1790 | u64 exec_start, u32 flags); | |
1791 | int (*init_rings)(struct drm_device *dev); | |
1792 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1793 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1794 | } gt; | |
1795 | ||
67e2937b JH |
1796 | uint32_t request_uniq; |
1797 | ||
bdf1e7e3 DV |
1798 | /* |
1799 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1800 | * will be rejected. Instead look for a better place. | |
1801 | */ | |
77fec556 | 1802 | }; |
1da177e4 | 1803 | |
2c1792a1 CW |
1804 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1805 | { | |
1806 | return dev->dev_private; | |
1807 | } | |
1808 | ||
888d0d42 ID |
1809 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
1810 | { | |
1811 | return to_i915(dev_get_drvdata(dev)); | |
1812 | } | |
1813 | ||
b4519513 CW |
1814 | /* Iterate over initialised rings */ |
1815 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1816 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1817 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1818 | ||
b1d7e4b4 WF |
1819 | enum hdmi_force_audio { |
1820 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1821 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1822 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1823 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1824 | }; | |
1825 | ||
190d6cd5 | 1826 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1827 | |
37e680a1 CW |
1828 | struct drm_i915_gem_object_ops { |
1829 | /* Interface between the GEM object and its backing storage. | |
1830 | * get_pages() is called once prior to the use of the associated set | |
1831 | * of pages before to binding them into the GTT, and put_pages() is | |
1832 | * called after we no longer need them. As we expect there to be | |
1833 | * associated cost with migrating pages between the backing storage | |
1834 | * and making them available for the GPU (e.g. clflush), we may hold | |
1835 | * onto the pages after they are no longer referenced by the GPU | |
1836 | * in case they may be used again shortly (for example migrating the | |
1837 | * pages to a different memory domain within the GTT). put_pages() | |
1838 | * will therefore most likely be called when the object itself is | |
1839 | * being released or under memory pressure (where we attempt to | |
1840 | * reap pages for the shrinker). | |
1841 | */ | |
1842 | int (*get_pages)(struct drm_i915_gem_object *); | |
1843 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
1844 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
1845 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
1846 | }; |
1847 | ||
a071fa00 DV |
1848 | /* |
1849 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
1850 | * considered to be the frontbuffer for the given plane interface-vise. This | |
1851 | * doesn't mean that the hw necessarily already scans it out, but that any | |
1852 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
1853 | * | |
1854 | * We have one bit per pipe and per scanout plane type. | |
1855 | */ | |
1856 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 | |
1857 | #define INTEL_FRONTBUFFER_BITS \ | |
1858 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
1859 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
1860 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
1861 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
1862 | (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1863 | #define INTEL_FRONTBUFFER_SPRITE(pipe) \ | |
1864 | (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1865 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
1866 | (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
cc36513c DV |
1867 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
1868 | (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
a071fa00 | 1869 | |
673a394b | 1870 | struct drm_i915_gem_object { |
c397b908 | 1871 | struct drm_gem_object base; |
673a394b | 1872 | |
37e680a1 CW |
1873 | const struct drm_i915_gem_object_ops *ops; |
1874 | ||
2f633156 BW |
1875 | /** List of VMAs backed by this object */ |
1876 | struct list_head vma_list; | |
1877 | ||
c1ad11fc CW |
1878 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1879 | struct drm_mm_node *stolen; | |
35c20a60 | 1880 | struct list_head global_list; |
673a394b | 1881 | |
69dc4987 | 1882 | struct list_head ring_list; |
b25cb2f8 BW |
1883 | /** Used in execbuf to temporarily hold a ref */ |
1884 | struct list_head obj_exec_link; | |
673a394b | 1885 | |
493018dc BV |
1886 | struct list_head batch_pool_list; |
1887 | ||
673a394b | 1888 | /** |
65ce3027 CW |
1889 | * This is set if the object is on the active lists (has pending |
1890 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1891 | * inactive (ready to be unbound) list. | |
673a394b | 1892 | */ |
0206e353 | 1893 | unsigned int active:1; |
673a394b EA |
1894 | |
1895 | /** | |
1896 | * This is set if the object has been written to since last bound | |
1897 | * to the GTT | |
1898 | */ | |
0206e353 | 1899 | unsigned int dirty:1; |
778c3544 DV |
1900 | |
1901 | /** | |
1902 | * Fence register bits (if any) for this object. Will be set | |
1903 | * as needed when mapped into the GTT. | |
1904 | * Protected by dev->struct_mutex. | |
778c3544 | 1905 | */ |
4b9de737 | 1906 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1907 | |
778c3544 DV |
1908 | /** |
1909 | * Advice: are the backing pages purgeable? | |
1910 | */ | |
0206e353 | 1911 | unsigned int madv:2; |
778c3544 | 1912 | |
778c3544 DV |
1913 | /** |
1914 | * Current tiling mode for the object. | |
1915 | */ | |
0206e353 | 1916 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1917 | /** |
1918 | * Whether the tiling parameters for the currently associated fence | |
1919 | * register have changed. Note that for the purposes of tracking | |
1920 | * tiling changes we also treat the unfenced register, the register | |
1921 | * slot that the object occupies whilst it executes a fenced | |
1922 | * command (such as BLT on gen2/3), as a "fence". | |
1923 | */ | |
1924 | unsigned int fence_dirty:1; | |
778c3544 | 1925 | |
75e9e915 DV |
1926 | /** |
1927 | * Is the object at the current location in the gtt mappable and | |
1928 | * fenceable? Used to avoid costly recalculations. | |
1929 | */ | |
0206e353 | 1930 | unsigned int map_and_fenceable:1; |
75e9e915 | 1931 | |
fb7d516a DV |
1932 | /** |
1933 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1934 | * mappable by accident). Track pin and fault separate for a more | |
1935 | * accurate mappable working set. | |
1936 | */ | |
0206e353 AJ |
1937 | unsigned int fault_mappable:1; |
1938 | unsigned int pin_mappable:1; | |
cc98b413 | 1939 | unsigned int pin_display:1; |
fb7d516a | 1940 | |
24f3a8cf AG |
1941 | /* |
1942 | * Is the object to be mapped as read-only to the GPU | |
1943 | * Only honoured if hardware has relevant pte bit | |
1944 | */ | |
1945 | unsigned long gt_ro:1; | |
651d794f | 1946 | unsigned int cache_level:3; |
0f71979a | 1947 | unsigned int cache_dirty:1; |
93dfb40c | 1948 | |
9da3da66 | 1949 | unsigned int has_dma_mapping:1; |
7bddb01f | 1950 | |
a071fa00 DV |
1951 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
1952 | ||
9da3da66 | 1953 | struct sg_table *pages; |
a5570178 | 1954 | int pages_pin_count; |
673a394b | 1955 | |
1286ff73 | 1956 | /* prime dma-buf support */ |
9a70cc2a DA |
1957 | void *dma_buf_vmapping; |
1958 | int vmapping_count; | |
1959 | ||
1c293ea3 | 1960 | /** Breadcrumb of last rendering to the buffer. */ |
97b2a6a1 JH |
1961 | struct drm_i915_gem_request *last_read_req; |
1962 | struct drm_i915_gem_request *last_write_req; | |
caea7476 | 1963 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 1964 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 1965 | |
778c3544 | 1966 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1967 | uint32_t stride; |
673a394b | 1968 | |
80075d49 DV |
1969 | /** References from framebuffers, locks out tiling changes. */ |
1970 | unsigned long framebuffer_references; | |
1971 | ||
280b713b | 1972 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1973 | unsigned long *bit_17; |
280b713b | 1974 | |
5cc9ed4b | 1975 | union { |
6a2c4232 CW |
1976 | /** for phy allocated objects */ |
1977 | struct drm_dma_handle *phys_handle; | |
1978 | ||
5cc9ed4b CW |
1979 | struct i915_gem_userptr { |
1980 | uintptr_t ptr; | |
1981 | unsigned read_only :1; | |
1982 | unsigned workers :4; | |
1983 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
1984 | ||
ad46cb53 CW |
1985 | struct i915_mm_struct *mm; |
1986 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
1987 | struct work_struct *work; |
1988 | } userptr; | |
1989 | }; | |
1990 | }; | |
62b8b215 | 1991 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1992 | |
a071fa00 DV |
1993 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
1994 | struct drm_i915_gem_object *new, | |
1995 | unsigned frontbuffer_bits); | |
1996 | ||
673a394b EA |
1997 | /** |
1998 | * Request queue structure. | |
1999 | * | |
2000 | * The request queue allows us to note sequence numbers that have been emitted | |
2001 | * and may be associated with active buffers to be retired. | |
2002 | * | |
97b2a6a1 JH |
2003 | * By keeping this list, we can avoid having to do questionable sequence |
2004 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2005 | * emission time to be associated with the request for tracking how far ahead | |
2006 | * of the GPU the submission is. | |
673a394b EA |
2007 | */ |
2008 | struct drm_i915_gem_request { | |
abfe262a JH |
2009 | struct kref ref; |
2010 | ||
852835f3 | 2011 | /** On Which ring this request was generated */ |
a4872ba6 | 2012 | struct intel_engine_cs *ring; |
852835f3 | 2013 | |
673a394b EA |
2014 | /** GEM sequence number associated with this request. */ |
2015 | uint32_t seqno; | |
2016 | ||
7d736f4f MK |
2017 | /** Position in the ringbuffer of the start of the request */ |
2018 | u32 head; | |
2019 | ||
72f95afa NH |
2020 | /** |
2021 | * Position in the ringbuffer of the start of the postfix. | |
2022 | * This is required to calculate the maximum available ringbuffer | |
2023 | * space without overwriting the postfix. | |
2024 | */ | |
2025 | u32 postfix; | |
2026 | ||
2027 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2028 | u32 tail; |
2029 | ||
98e1bd4a | 2030 | /** Context and ring buffer related to this request */ |
273497e5 | 2031 | struct intel_context *ctx; |
98e1bd4a | 2032 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2033 | |
7d736f4f MK |
2034 | /** Batch buffer related to this request if any */ |
2035 | struct drm_i915_gem_object *batch_obj; | |
2036 | ||
673a394b EA |
2037 | /** Time at which this request was emitted, in jiffies. */ |
2038 | unsigned long emitted_jiffies; | |
2039 | ||
b962442e | 2040 | /** global list entry for this request */ |
673a394b | 2041 | struct list_head list; |
b962442e | 2042 | |
f787a5f5 | 2043 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2044 | /** file_priv list entry for this request */ |
2045 | struct list_head client_list; | |
67e2937b | 2046 | |
071c92de MK |
2047 | /** process identifier submitting this request */ |
2048 | struct pid *pid; | |
2049 | ||
67e2937b | 2050 | uint32_t uniq; |
6d3d8274 NH |
2051 | |
2052 | /** | |
2053 | * The ELSP only accepts two elements at a time, so we queue | |
2054 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2055 | * hardware is available. The queue serves a double purpose: we also use | |
2056 | * it to keep track of the up to 2 contexts currently in the hardware | |
2057 | * (usually one in execution and the other queued up by the GPU): We | |
2058 | * only remove elements from the head of the queue when the hardware | |
2059 | * informs us that an element has been completed. | |
2060 | * | |
2061 | * All accesses to the queue are mediated by a spinlock | |
2062 | * (ring->execlist_lock). | |
2063 | */ | |
2064 | ||
2065 | /** Execlist link in the submission queue.*/ | |
2066 | struct list_head execlist_link; | |
2067 | ||
2068 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2069 | int elsp_submitted; | |
2070 | ||
673a394b EA |
2071 | }; |
2072 | ||
abfe262a JH |
2073 | void i915_gem_request_free(struct kref *req_ref); |
2074 | ||
b793a00a JH |
2075 | static inline uint32_t |
2076 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2077 | { | |
2078 | return req ? req->seqno : 0; | |
2079 | } | |
2080 | ||
2081 | static inline struct intel_engine_cs * | |
2082 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2083 | { | |
2084 | return req ? req->ring : NULL; | |
2085 | } | |
2086 | ||
abfe262a JH |
2087 | static inline void |
2088 | i915_gem_request_reference(struct drm_i915_gem_request *req) | |
2089 | { | |
2090 | kref_get(&req->ref); | |
2091 | } | |
2092 | ||
2093 | static inline void | |
2094 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2095 | { | |
f245860e | 2096 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
abfe262a JH |
2097 | kref_put(&req->ref, i915_gem_request_free); |
2098 | } | |
2099 | ||
2100 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, | |
2101 | struct drm_i915_gem_request *src) | |
2102 | { | |
2103 | if (src) | |
2104 | i915_gem_request_reference(src); | |
2105 | ||
2106 | if (*pdst) | |
2107 | i915_gem_request_unreference(*pdst); | |
2108 | ||
2109 | *pdst = src; | |
2110 | } | |
2111 | ||
1b5a433a JH |
2112 | /* |
2113 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2114 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2115 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2116 | */ | |
2117 | ||
673a394b | 2118 | struct drm_i915_file_private { |
b29c19b6 | 2119 | struct drm_i915_private *dev_priv; |
ab0e7ff9 | 2120 | struct drm_file *file; |
b29c19b6 | 2121 | |
673a394b | 2122 | struct { |
99057c81 | 2123 | spinlock_t lock; |
b962442e | 2124 | struct list_head request_list; |
b29c19b6 | 2125 | struct delayed_work idle_work; |
673a394b | 2126 | } mm; |
40521054 | 2127 | struct idr context_idr; |
e59ec13d | 2128 | |
b29c19b6 | 2129 | atomic_t rps_wait_boost; |
a4872ba6 | 2130 | struct intel_engine_cs *bsd_ring; |
673a394b EA |
2131 | }; |
2132 | ||
351e3db2 BV |
2133 | /* |
2134 | * A command that requires special handling by the command parser. | |
2135 | */ | |
2136 | struct drm_i915_cmd_descriptor { | |
2137 | /* | |
2138 | * Flags describing how the command parser processes the command. | |
2139 | * | |
2140 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2141 | * a length mask if not set | |
2142 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2143 | * standard length encoding for the opcode range in | |
2144 | * which it falls | |
2145 | * CMD_DESC_REJECT: The command is never allowed | |
2146 | * CMD_DESC_REGISTER: The command should be checked against the | |
2147 | * register whitelist for the appropriate ring | |
2148 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2149 | * is the DRM master | |
2150 | */ | |
2151 | u32 flags; | |
2152 | #define CMD_DESC_FIXED (1<<0) | |
2153 | #define CMD_DESC_SKIP (1<<1) | |
2154 | #define CMD_DESC_REJECT (1<<2) | |
2155 | #define CMD_DESC_REGISTER (1<<3) | |
2156 | #define CMD_DESC_BITMASK (1<<4) | |
2157 | #define CMD_DESC_MASTER (1<<5) | |
2158 | ||
2159 | /* | |
2160 | * The command's unique identification bits and the bitmask to get them. | |
2161 | * This isn't strictly the opcode field as defined in the spec and may | |
2162 | * also include type, subtype, and/or subop fields. | |
2163 | */ | |
2164 | struct { | |
2165 | u32 value; | |
2166 | u32 mask; | |
2167 | } cmd; | |
2168 | ||
2169 | /* | |
2170 | * The command's length. The command is either fixed length (i.e. does | |
2171 | * not include a length field) or has a length field mask. The flag | |
2172 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2173 | * a length mask. All command entries in a command table must include | |
2174 | * length information. | |
2175 | */ | |
2176 | union { | |
2177 | u32 fixed; | |
2178 | u32 mask; | |
2179 | } length; | |
2180 | ||
2181 | /* | |
2182 | * Describes where to find a register address in the command to check | |
2183 | * against the ring's register whitelist. Only valid if flags has the | |
2184 | * CMD_DESC_REGISTER bit set. | |
2185 | */ | |
2186 | struct { | |
2187 | u32 offset; | |
2188 | u32 mask; | |
2189 | } reg; | |
2190 | ||
2191 | #define MAX_CMD_DESC_BITMASKS 3 | |
2192 | /* | |
2193 | * Describes command checks where a particular dword is masked and | |
2194 | * compared against an expected value. If the command does not match | |
2195 | * the expected value, the parser rejects it. Only valid if flags has | |
2196 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2197 | * are valid. | |
d4d48035 BV |
2198 | * |
2199 | * If the check specifies a non-zero condition_mask then the parser | |
2200 | * only performs the check when the bits specified by condition_mask | |
2201 | * are non-zero. | |
351e3db2 BV |
2202 | */ |
2203 | struct { | |
2204 | u32 offset; | |
2205 | u32 mask; | |
2206 | u32 expected; | |
d4d48035 BV |
2207 | u32 condition_offset; |
2208 | u32 condition_mask; | |
351e3db2 BV |
2209 | } bits[MAX_CMD_DESC_BITMASKS]; |
2210 | }; | |
2211 | ||
2212 | /* | |
2213 | * A table of commands requiring special handling by the command parser. | |
2214 | * | |
2215 | * Each ring has an array of tables. Each table consists of an array of command | |
2216 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2217 | */ | |
2218 | struct drm_i915_cmd_table { | |
2219 | const struct drm_i915_cmd_descriptor *table; | |
2220 | int count; | |
2221 | }; | |
2222 | ||
dbbe9127 | 2223 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2224 | #define __I915__(p) ({ \ |
2225 | struct drm_i915_private *__p; \ | |
2226 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2227 | __p = (struct drm_i915_private *)p; \ | |
2228 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2229 | __p = to_i915((struct drm_device *)p); \ | |
2230 | else \ | |
2231 | BUILD_BUG(); \ | |
2232 | __p; \ | |
2233 | }) | |
dbbe9127 | 2234 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2235 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
e90a21d4 | 2236 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
cae5852d | 2237 | |
87f1f465 CW |
2238 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2239 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2240 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2241 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2242 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2243 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2244 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2245 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2246 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2247 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2248 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2249 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2250 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2251 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2252 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2253 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2254 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2255 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2256 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2257 | INTEL_DEVID(dev) == 0x0152 || \ | |
2258 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2259 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
6df4027b | 2260 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
4cae9ae0 | 2261 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
8179f1f0 | 2262 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
7201c0b3 | 2263 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
cae5852d | 2264 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2265 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2266 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2267 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
87f1f465 CW |
2268 | ((INTEL_DEVID(dev) & 0xf) == 0x2 || \ |
2269 | (INTEL_DEVID(dev) & 0xf) == 0x6 || \ | |
2270 | (INTEL_DEVID(dev) & 0xf) == 0xe)) | |
a0fcbd95 RV |
2271 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2272 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2273 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2274 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2275 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2276 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2277 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2278 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2279 | INTEL_DEVID(dev) == 0x0A1E) | |
b833d685 | 2280 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2281 | |
e90a21d4 HN |
2282 | #define SKL_REVID_A0 (0x0) |
2283 | #define SKL_REVID_B0 (0x1) | |
2284 | #define SKL_REVID_C0 (0x2) | |
2285 | #define SKL_REVID_D0 (0x3) | |
8bc0ccf6 | 2286 | #define SKL_REVID_E0 (0x4) |
e90a21d4 | 2287 | |
85436696 JB |
2288 | /* |
2289 | * The genX designation typically refers to the render engine, so render | |
2290 | * capability related checks should use IS_GEN, while display and other checks | |
2291 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2292 | * chips, etc.). | |
2293 | */ | |
cae5852d ZN |
2294 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2295 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2296 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2297 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2298 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2299 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2300 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2301 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2302 | |
73ae478c BW |
2303 | #define RENDER_RING (1<<RCS) |
2304 | #define BSD_RING (1<<VCS) | |
2305 | #define BLT_RING (1<<BCS) | |
2306 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2307 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2308 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2309 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2310 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2311 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2312 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2313 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
f2fbc690 | 2314 | __I915__(dev)->ellc_size) |
cae5852d ZN |
2315 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2316 | ||
254f965c | 2317 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2318 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c JB |
2319 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
2320 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) | |
1d2a314c | 2321 | |
05394f39 | 2322 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2323 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2324 | ||
b45305fc DV |
2325 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2326 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
4e6b788c DV |
2327 | /* |
2328 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2329 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2330 | * legacy irq no. is shared with another device. The kernel then disables that | |
2331 | * interrupt source and so prevents the other device from working properly. | |
2332 | */ | |
2333 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2334 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2335 | |
cae5852d ZN |
2336 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2337 | * rows, which changed the alignment requirements and fence programming. | |
2338 | */ | |
2339 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2340 | IS_I915GM(dev))) | |
2341 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
2342 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
2343 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
cae5852d ZN |
2344 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2345 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2346 | |
2347 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2348 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2349 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2350 | |
dbf7786e | 2351 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2352 | |
dd93be58 | 2353 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2354 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2355 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 SJ |
2356 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
2357 | IS_SKYLAKE(dev)) | |
6157d3c8 | 2358 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
fd7f8cce | 2359 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) |
58abf1da RV |
2360 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2361 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2362 | |
17a303ec PZ |
2363 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2364 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2365 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2366 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2367 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2368 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2369 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2370 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
17a303ec | 2371 | |
f2fbc690 | 2372 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2373 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2374 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
2375 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2376 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2377 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2378 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2379 | |
5fafe292 SJ |
2380 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2381 | ||
040d2baa BW |
2382 | /* DPF == dynamic parity feature */ |
2383 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2384 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2385 | |
c8735b0c BW |
2386 | #define GT_FREQUENCY_MULTIPLIER 50 |
2387 | ||
05394f39 CW |
2388 | #include "i915_trace.h" |
2389 | ||
baa70943 | 2390 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2391 | extern int i915_max_ioctl; |
2392 | ||
fc49b3da ID |
2393 | extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); |
2394 | extern int i915_resume_legacy(struct drm_device *dev); | |
7c1c2871 | 2395 | |
d330a953 JN |
2396 | /* i915_params.c */ |
2397 | struct i915_params { | |
2398 | int modeset; | |
2399 | int panel_ignore_lid; | |
2400 | unsigned int powersave; | |
2401 | int semaphores; | |
2402 | unsigned int lvds_downclock; | |
2403 | int lvds_channel_mode; | |
2404 | int panel_use_ssc; | |
2405 | int vbt_sdvo_panel_type; | |
2406 | int enable_rc6; | |
2407 | int enable_fbc; | |
d330a953 | 2408 | int enable_ppgtt; |
127f1003 | 2409 | int enable_execlists; |
d330a953 JN |
2410 | int enable_psr; |
2411 | unsigned int preliminary_hw_support; | |
2412 | int disable_power_well; | |
2413 | int enable_ips; | |
e5aa6541 | 2414 | int invert_brightness; |
351e3db2 | 2415 | int enable_cmd_parser; |
e5aa6541 DL |
2416 | /* leave bools at the end to not create holes */ |
2417 | bool enable_hangcheck; | |
2418 | bool fastboot; | |
d330a953 JN |
2419 | bool prefault_disable; |
2420 | bool reset; | |
a0bae57f | 2421 | bool disable_display; |
7a10dfa6 | 2422 | bool disable_vtd_wa; |
84c33a64 | 2423 | int use_mmio_flip; |
5978118c | 2424 | bool mmio_debug; |
e2c719b7 | 2425 | bool verbose_state_checks; |
b2e7723b | 2426 | bool nuclear_pageflip; |
d330a953 JN |
2427 | }; |
2428 | extern struct i915_params i915 __read_mostly; | |
2429 | ||
1da177e4 | 2430 | /* i915_dma.c */ |
22eae947 | 2431 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2432 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2433 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2434 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2435 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2436 | struct drm_file *file); |
673a394b | 2437 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2438 | struct drm_file *file); |
84b1fd10 | 2439 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 2440 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2441 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2442 | unsigned long arg); | |
c43b5634 | 2443 | #endif |
8e96d9c4 | 2444 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2445 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2446 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2447 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2448 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2449 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2450 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
1d0d343a | 2451 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); |
7648fa99 | 2452 | |
1da177e4 | 2453 | /* i915_irq.c */ |
10cd45b6 | 2454 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2455 | __printf(3, 4) |
2456 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2457 | const char *fmt, ...); | |
1da177e4 | 2458 | |
b963291c DV |
2459 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2460 | extern void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2aeb7d3a DV |
2461 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2462 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2463 | |
2464 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2465 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2466 | bool restore_forcewake); | |
907b28c5 | 2467 | extern void intel_uncore_init(struct drm_device *dev); |
907b28c5 | 2468 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2469 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2470 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
48c1026a | 2471 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2472 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2473 | enum forcewake_domains domains); |
59bad947 | 2474 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2475 | enum forcewake_domains domains); |
59bad947 | 2476 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
cf9d2890 YZ |
2477 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2478 | { | |
2479 | return to_i915(dev)->vgpu.active; | |
2480 | } | |
b1f14ad0 | 2481 | |
7c463586 | 2482 | void |
50227e1c | 2483 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2484 | u32 status_mask); |
7c463586 KP |
2485 | |
2486 | void | |
50227e1c | 2487 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2488 | u32 status_mask); |
7c463586 | 2489 | |
f8b79e58 ID |
2490 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2491 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
2492 | void |
2493 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2494 | void | |
2495 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2496 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
2497 | uint32_t interrupt_mask, | |
2498 | uint32_t enabled_irq_mask); | |
2499 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
2500 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
2501 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
2502 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
f8b79e58 | 2503 | |
673a394b | 2504 | /* i915_gem.c */ |
673a394b EA |
2505 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2506 | struct drm_file *file_priv); | |
2507 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2508 | struct drm_file *file_priv); | |
2509 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2510 | struct drm_file *file_priv); | |
2511 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2512 | struct drm_file *file_priv); | |
de151cf6 JB |
2513 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2514 | struct drm_file *file_priv); | |
673a394b EA |
2515 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2516 | struct drm_file *file_priv); | |
2517 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2518 | struct drm_file *file_priv); | |
ba8b7ccb OM |
2519 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
2520 | struct intel_engine_cs *ring); | |
2521 | void i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
2522 | struct drm_file *file, | |
2523 | struct intel_engine_cs *ring, | |
2524 | struct drm_i915_gem_object *obj); | |
a83014d3 OM |
2525 | int i915_gem_ringbuffer_submission(struct drm_device *dev, |
2526 | struct drm_file *file, | |
2527 | struct intel_engine_cs *ring, | |
2528 | struct intel_context *ctx, | |
2529 | struct drm_i915_gem_execbuffer2 *args, | |
2530 | struct list_head *vmas, | |
2531 | struct drm_i915_gem_object *batch_obj, | |
2532 | u64 exec_start, u32 flags); | |
673a394b EA |
2533 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2534 | struct drm_file *file_priv); | |
76446cac JB |
2535 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2536 | struct drm_file *file_priv); | |
673a394b EA |
2537 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2538 | struct drm_file *file_priv); | |
199adf40 BW |
2539 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2540 | struct drm_file *file); | |
2541 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2542 | struct drm_file *file); | |
673a394b EA |
2543 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2544 | struct drm_file *file_priv); | |
3ef94daa CW |
2545 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2546 | struct drm_file *file_priv); | |
673a394b EA |
2547 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2548 | struct drm_file *file_priv); | |
2549 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2550 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2551 | int i915_gem_init_userptr(struct drm_device *dev); |
2552 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2553 | struct drm_file *file); | |
5a125c3c EA |
2554 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2555 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2556 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2557 | struct drm_file *file_priv); | |
673a394b | 2558 | void i915_gem_load(struct drm_device *dev); |
21ab4e74 CW |
2559 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, |
2560 | long target, | |
2561 | unsigned flags); | |
2562 | #define I915_SHRINK_PURGEABLE 0x1 | |
2563 | #define I915_SHRINK_UNBOUND 0x2 | |
2564 | #define I915_SHRINK_BOUND 0x4 | |
42dcedd4 CW |
2565 | void *i915_gem_object_alloc(struct drm_device *dev); |
2566 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2567 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2568 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2569 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2570 | size_t size); | |
7e0d96bc BW |
2571 | void i915_init_vm(struct drm_i915_private *dev_priv, |
2572 | struct i915_address_space *vm); | |
673a394b | 2573 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2574 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2575 | |
1ec9e26d DV |
2576 | #define PIN_MAPPABLE 0x1 |
2577 | #define PIN_NONBLOCK 0x2 | |
bf3d149b | 2578 | #define PIN_GLOBAL 0x4 |
d23db88c CW |
2579 | #define PIN_OFFSET_BIAS 0x8 |
2580 | #define PIN_OFFSET_MASK (~4095) | |
fe14d5f4 TU |
2581 | int __must_check i915_gem_object_pin_view(struct drm_i915_gem_object *obj, |
2582 | struct i915_address_space *vm, | |
2583 | uint32_t alignment, | |
2584 | uint64_t flags, | |
2585 | const struct i915_ggtt_view *view); | |
2586 | static inline | |
2021746e | 2587 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 2588 | struct i915_address_space *vm, |
2021746e | 2589 | uint32_t alignment, |
fe14d5f4 TU |
2590 | uint64_t flags) |
2591 | { | |
2592 | return i915_gem_object_pin_view(obj, vm, alignment, flags, | |
2593 | &i915_ggtt_view_normal); | |
2594 | } | |
2595 | ||
2596 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2597 | u32 flags); | |
07fe0b12 | 2598 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
dd624afd | 2599 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2600 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2601 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2602 | |
4c914c0c BV |
2603 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2604 | int *needs_clflush); | |
2605 | ||
37e680a1 | 2606 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
2607 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2608 | { | |
67d5a50c ID |
2609 | struct sg_page_iter sg_iter; |
2610 | ||
2611 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 2612 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
2613 | |
2614 | return NULL; | |
9da3da66 | 2615 | } |
a5570178 CW |
2616 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2617 | { | |
2618 | BUG_ON(obj->pages == NULL); | |
2619 | obj->pages_pin_count++; | |
2620 | } | |
2621 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2622 | { | |
2623 | BUG_ON(obj->pages_pin_count == 0); | |
2624 | obj->pages_pin_count--; | |
2625 | } | |
2626 | ||
54cf91dc | 2627 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2628 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
a4872ba6 | 2629 | struct intel_engine_cs *to); |
e2d05a8b | 2630 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2631 | struct intel_engine_cs *ring); |
ff72145b DA |
2632 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2633 | struct drm_device *dev, | |
2634 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
2635 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2636 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2637 | /** |
2638 | * Returns true if seq1 is later than seq2. | |
2639 | */ | |
2640 | static inline bool | |
2641 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2642 | { | |
2643 | return (int32_t)(seq1 - seq2) >= 0; | |
2644 | } | |
2645 | ||
1b5a433a JH |
2646 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
2647 | bool lazy_coherency) | |
2648 | { | |
2649 | u32 seqno; | |
2650 | ||
2651 | BUG_ON(req == NULL); | |
2652 | ||
2653 | seqno = req->ring->get_seqno(req->ring, lazy_coherency); | |
2654 | ||
2655 | return i915_seqno_passed(seqno, req->seqno); | |
2656 | } | |
2657 | ||
fca26bb4 MK |
2658 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2659 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 2660 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 2661 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 2662 | |
d8ffa60b DV |
2663 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); |
2664 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
1690e1eb | 2665 | |
8d9fc7fd | 2666 | struct drm_i915_gem_request * |
a4872ba6 | 2667 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2668 | |
b29c19b6 | 2669 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2670 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2671 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2672 | bool interruptible); |
b6660d59 | 2673 | int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req); |
84c33a64 | 2674 | |
1f83fee0 DV |
2675 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2676 | { | |
2677 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2678 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2679 | } |
2680 | ||
2681 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2682 | { | |
2ac0f450 MK |
2683 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2684 | } | |
2685 | ||
2686 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2687 | { | |
2688 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2689 | } |
a71d8d94 | 2690 | |
88b4aa87 MK |
2691 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2692 | { | |
2693 | return dev_priv->gpu_error.stop_rings == 0 || | |
2694 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2695 | } | |
2696 | ||
2697 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2698 | { | |
2699 | return dev_priv->gpu_error.stop_rings == 0 || | |
2700 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2701 | } | |
2702 | ||
069efc1d | 2703 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2704 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
a8198eea | 2705 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 2706 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 2707 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 2708 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
a4872ba6 | 2709 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); |
f691e2f4 | 2710 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2711 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2712 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2713 | int __must_check i915_gem_suspend(struct drm_device *dev); |
a4872ba6 | 2714 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2715 | struct drm_file *file, |
9400ae5c JH |
2716 | struct drm_i915_gem_object *batch_obj); |
2717 | #define i915_add_request(ring) \ | |
2718 | __i915_add_request(ring, NULL, NULL) | |
9c654818 | 2719 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
2720 | unsigned reset_counter, |
2721 | bool interruptible, | |
2722 | s64 *timeout, | |
2723 | struct drm_i915_file_private *file_priv); | |
a4b3a571 | 2724 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 2725 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
2726 | int __must_check |
2727 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
2728 | bool write); | |
2729 | int __must_check | |
dabdfe02 CW |
2730 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2731 | int __must_check | |
2da3b9b9 CW |
2732 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2733 | u32 alignment, | |
a4872ba6 | 2734 | struct intel_engine_cs *pipelined); |
cc98b413 | 2735 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
00731155 | 2736 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 2737 | int align); |
b29c19b6 | 2738 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2739 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2740 | |
0fa87796 ID |
2741 | uint32_t |
2742 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2743 | uint32_t |
d865110c ID |
2744 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2745 | int tiling_mode, bool fenced); | |
467cffba | 2746 | |
e4ffd173 CW |
2747 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2748 | enum i915_cache_level cache_level); | |
2749 | ||
1286ff73 DV |
2750 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2751 | struct dma_buf *dma_buf); | |
2752 | ||
2753 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2754 | struct drm_gem_object *gem_obj, int flags); | |
2755 | ||
19b2dbde CW |
2756 | void i915_gem_restore_fences(struct drm_device *dev); |
2757 | ||
fe14d5f4 TU |
2758 | unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o, |
2759 | struct i915_address_space *vm, | |
2760 | enum i915_ggtt_view_type view); | |
2761 | static inline | |
a70a3148 | 2762 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
fe14d5f4 TU |
2763 | struct i915_address_space *vm) |
2764 | { | |
2765 | return i915_gem_obj_offset_view(o, vm, I915_GGTT_VIEW_NORMAL); | |
2766 | } | |
a70a3148 | 2767 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
fe14d5f4 TU |
2768 | bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o, |
2769 | struct i915_address_space *vm, | |
2770 | enum i915_ggtt_view_type view); | |
2771 | static inline | |
a70a3148 | 2772 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
fe14d5f4 TU |
2773 | struct i915_address_space *vm) |
2774 | { | |
2775 | return i915_gem_obj_bound_view(o, vm, I915_GGTT_VIEW_NORMAL); | |
2776 | } | |
2777 | ||
a70a3148 BW |
2778 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
2779 | struct i915_address_space *vm); | |
fe14d5f4 TU |
2780 | struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj, |
2781 | struct i915_address_space *vm, | |
2782 | const struct i915_ggtt_view *view); | |
2783 | static inline | |
a70a3148 | 2784 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
fe14d5f4 TU |
2785 | struct i915_address_space *vm) |
2786 | { | |
2787 | return i915_gem_obj_to_vma_view(obj, vm, &i915_ggtt_view_normal); | |
2788 | } | |
2789 | ||
2790 | struct i915_vma * | |
2791 | i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj, | |
2792 | struct i915_address_space *vm, | |
2793 | const struct i915_ggtt_view *view); | |
2794 | ||
2795 | static inline | |
accfef2e BW |
2796 | struct i915_vma * |
2797 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 TU |
2798 | struct i915_address_space *vm) |
2799 | { | |
2800 | return i915_gem_obj_lookup_or_create_vma_view(obj, vm, | |
2801 | &i915_ggtt_view_normal); | |
2802 | } | |
5c2abbea BW |
2803 | |
2804 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); | |
d7f46fc4 BW |
2805 | static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { |
2806 | struct i915_vma *vma; | |
2807 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
2808 | if (vma->pin_count > 0) | |
2809 | return true; | |
2810 | return false; | |
2811 | } | |
5c2abbea | 2812 | |
a70a3148 | 2813 | /* Some GGTT VM helpers */ |
5dc383b0 | 2814 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 BW |
2815 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
2816 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2817 | { | |
2818 | struct i915_address_space *ggtt = | |
2819 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2820 | return vm == ggtt; | |
2821 | } | |
2822 | ||
841cd773 DV |
2823 | static inline struct i915_hw_ppgtt * |
2824 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
2825 | { | |
2826 | WARN_ON(i915_is_ggtt(vm)); | |
2827 | ||
2828 | return container_of(vm, struct i915_hw_ppgtt, base); | |
2829 | } | |
2830 | ||
2831 | ||
a70a3148 BW |
2832 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
2833 | { | |
5dc383b0 | 2834 | return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj)); |
a70a3148 BW |
2835 | } |
2836 | ||
2837 | static inline unsigned long | |
2838 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) | |
2839 | { | |
5dc383b0 | 2840 | return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj)); |
a70a3148 BW |
2841 | } |
2842 | ||
2843 | static inline unsigned long | |
2844 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2845 | { | |
5dc383b0 | 2846 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 2847 | } |
c37e2204 BW |
2848 | |
2849 | static inline int __must_check | |
2850 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2851 | uint32_t alignment, | |
1ec9e26d | 2852 | unsigned flags) |
c37e2204 | 2853 | { |
5dc383b0 DV |
2854 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
2855 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 2856 | } |
a70a3148 | 2857 | |
b287110e DV |
2858 | static inline int |
2859 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2860 | { | |
2861 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
2862 | } | |
2863 | ||
2864 | void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); | |
2865 | ||
254f965c | 2866 | /* i915_gem_context.c */ |
8245be31 | 2867 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 2868 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 2869 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 2870 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
2fa48d8d | 2871 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
254f965c | 2872 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
a4872ba6 | 2873 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 OM |
2874 | struct intel_context *to); |
2875 | struct intel_context * | |
41bde553 | 2876 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 2877 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
2878 | struct drm_i915_gem_object * |
2879 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 2880 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 2881 | { |
691e6415 | 2882 | kref_get(&ctx->ref); |
dce3271b MK |
2883 | } |
2884 | ||
273497e5 | 2885 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 2886 | { |
691e6415 | 2887 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
2888 | } |
2889 | ||
273497e5 | 2890 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 2891 | { |
821d66dd | 2892 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
2893 | } |
2894 | ||
84624813 BW |
2895 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2896 | struct drm_file *file); | |
2897 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
2898 | struct drm_file *file); | |
c9dc0f35 CW |
2899 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
2900 | struct drm_file *file_priv); | |
2901 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
2902 | struct drm_file *file_priv); | |
1286ff73 | 2903 | |
679845ed BW |
2904 | /* i915_gem_evict.c */ |
2905 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
2906 | struct i915_address_space *vm, | |
2907 | int min_size, | |
2908 | unsigned alignment, | |
2909 | unsigned cache_level, | |
d23db88c CW |
2910 | unsigned long start, |
2911 | unsigned long end, | |
1ec9e26d | 2912 | unsigned flags); |
679845ed BW |
2913 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
2914 | int i915_gem_evict_everything(struct drm_device *dev); | |
1d2a314c | 2915 | |
0260c420 | 2916 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 2917 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
2918 | { |
2919 | if (INTEL_INFO(dev)->gen < 6) | |
2920 | intel_gtt_chipset_flush(); | |
2921 | } | |
246cbfb5 | 2922 | |
9797fbfb CW |
2923 | /* i915_gem_stolen.c */ |
2924 | int i915_gem_init_stolen(struct drm_device *dev); | |
5e59f717 | 2925 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); |
11be49eb | 2926 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
9797fbfb | 2927 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
2928 | struct drm_i915_gem_object * |
2929 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
2930 | struct drm_i915_gem_object * |
2931 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
2932 | u32 stolen_offset, | |
2933 | u32 gtt_offset, | |
2934 | u32 size); | |
9797fbfb | 2935 | |
673a394b | 2936 | /* i915_gem_tiling.c */ |
2c1792a1 | 2937 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 2938 | { |
50227e1c | 2939 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
2940 | |
2941 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
2942 | obj->tiling_mode != I915_TILING_NONE; | |
2943 | } | |
2944 | ||
673a394b | 2945 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
2946 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
2947 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
2948 | |
2949 | /* i915_gem_debug.c */ | |
23bc5982 CW |
2950 | #if WATCH_LISTS |
2951 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 2952 | #else |
23bc5982 | 2953 | #define i915_verify_lists(dev) 0 |
673a394b | 2954 | #endif |
1da177e4 | 2955 | |
2017263e | 2956 | /* i915_debugfs.c */ |
27c202ad BG |
2957 | int i915_debugfs_init(struct drm_minor *minor); |
2958 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 2959 | #ifdef CONFIG_DEBUG_FS |
07144428 DL |
2960 | void intel_display_crc_init(struct drm_device *dev); |
2961 | #else | |
f8c168fa | 2962 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 2963 | #endif |
84734a04 MK |
2964 | |
2965 | /* i915_gpu_error.c */ | |
edc3d884 MK |
2966 | __printf(2, 3) |
2967 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
2968 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
2969 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 2970 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 2971 | struct drm_i915_private *i915, |
4dc955f7 MK |
2972 | size_t count, loff_t pos); |
2973 | static inline void i915_error_state_buf_release( | |
2974 | struct drm_i915_error_state_buf *eb) | |
2975 | { | |
2976 | kfree(eb->buf); | |
2977 | } | |
58174462 MK |
2978 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
2979 | const char *error_msg); | |
84734a04 MK |
2980 | void i915_error_state_get(struct drm_device *dev, |
2981 | struct i915_error_state_file_priv *error_priv); | |
2982 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
2983 | void i915_destroy_error_state(struct drm_device *dev); | |
2984 | ||
2985 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 2986 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 2987 | |
493018dc BV |
2988 | /* i915_gem_batch_pool.c */ |
2989 | void i915_gem_batch_pool_init(struct drm_device *dev, | |
2990 | struct i915_gem_batch_pool *pool); | |
2991 | void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool); | |
2992 | struct drm_i915_gem_object* | |
2993 | i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size); | |
2994 | ||
351e3db2 | 2995 | /* i915_cmd_parser.c */ |
d728c8ef | 2996 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
2997 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
2998 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
2999 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
3000 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 | 3001 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3002 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3003 | u32 batch_start_offset, |
b9ffd80e | 3004 | u32 batch_len, |
351e3db2 BV |
3005 | bool is_master); |
3006 | ||
317c35d1 JB |
3007 | /* i915_suspend.c */ |
3008 | extern int i915_save_state(struct drm_device *dev); | |
3009 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3010 | |
0136db58 BW |
3011 | /* i915_sysfs.c */ |
3012 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3013 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3014 | ||
f899fc64 CW |
3015 | /* intel_i2c.c */ |
3016 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3017 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
8f375e10 | 3018 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3bd7d909 | 3019 | { |
2ed06c93 | 3020 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
3021 | } |
3022 | ||
3023 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
3024 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
3025 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3026 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3027 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3028 | { |
3029 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3030 | } | |
f899fc64 CW |
3031 | extern void intel_i2c_reset(struct drm_device *dev); |
3032 | ||
3b617967 | 3033 | /* intel_opregion.c */ |
44834a67 | 3034 | #ifdef CONFIG_ACPI |
27d50c82 | 3035 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
3036 | extern void intel_opregion_init(struct drm_device *dev); |
3037 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 3038 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
3039 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3040 | bool enable); | |
ecbc5cf3 JN |
3041 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3042 | pci_power_t state); | |
65e082c9 | 3043 | #else |
27d50c82 | 3044 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
3045 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3046 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 3047 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
3048 | static inline int |
3049 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3050 | { | |
3051 | return 0; | |
3052 | } | |
ecbc5cf3 JN |
3053 | static inline int |
3054 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3055 | { | |
3056 | return 0; | |
3057 | } | |
65e082c9 | 3058 | #endif |
8ee1c3db | 3059 | |
723bfd70 JB |
3060 | /* intel_acpi.c */ |
3061 | #ifdef CONFIG_ACPI | |
3062 | extern void intel_register_dsm_handler(void); | |
3063 | extern void intel_unregister_dsm_handler(void); | |
3064 | #else | |
3065 | static inline void intel_register_dsm_handler(void) { return; } | |
3066 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3067 | #endif /* CONFIG_ACPI */ | |
3068 | ||
79e53945 | 3069 | /* modesetting */ |
f817586c | 3070 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3071 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3072 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3073 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 3074 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 3075 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
3076 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
3077 | bool force_restore); | |
44cec740 | 3078 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3079 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
7648fa99 | 3080 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 3081 | extern void intel_init_pch_refclk(struct drm_device *dev); |
ffe02b40 | 3082 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
3083 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3084 | bool enable); | |
0206e353 AJ |
3085 | extern void intel_detect_pch(struct drm_device *dev); |
3086 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 3087 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 3088 | |
2911a35b | 3089 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
3090 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3091 | struct drm_file *file); | |
b6359918 MK |
3092 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3093 | struct drm_file *file); | |
575155a9 | 3094 | |
6ef3d427 CW |
3095 | /* overlay */ |
3096 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
3097 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3098 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
3099 | |
3100 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 3101 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3102 | struct drm_device *dev, |
3103 | struct intel_display_error_state *error); | |
6ef3d427 | 3104 | |
151a49d0 TR |
3105 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3106 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3107 | |
3108 | /* intel_sideband.c */ | |
707b6e3d D |
3109 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3110 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3111 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
e9f882a3 JN |
3112 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
3113 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3114 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
3115 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3116 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3117 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3118 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3119 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
3120 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3121 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3122 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3123 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3124 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3125 | enum intel_sbi_destination destination); | |
3126 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3127 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3128 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3129 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3130 | |
616bc820 VS |
3131 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3132 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
42c0526c | 3133 | |
0b274481 BW |
3134 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3135 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3136 | ||
3137 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3138 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3139 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3140 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3141 | ||
3142 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3143 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3144 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3145 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3146 | ||
698b3135 CW |
3147 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3148 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3149 | * an arbitrary delay between them. This can cause the hardware to | |
3150 | * act upon the intermediate value, possibly leading to corruption and | |
3151 | * machine death. You have been warned. | |
3152 | */ | |
0b274481 BW |
3153 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3154 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3155 | |
50877445 CW |
3156 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
3157 | u32 upper = I915_READ(upper_reg); \ | |
3158 | u32 lower = I915_READ(lower_reg); \ | |
3159 | u32 tmp = I915_READ(upper_reg); \ | |
3160 | if (upper != tmp) { \ | |
3161 | upper = tmp; \ | |
3162 | lower = I915_READ(lower_reg); \ | |
3163 | WARN_ON(I915_READ(upper_reg) != upper); \ | |
3164 | } \ | |
3165 | (u64)upper << 32 | lower; }) | |
3166 | ||
cae5852d ZN |
3167 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3168 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3169 | ||
55bc60db VS |
3170 | /* "Broadcast RGB" property */ |
3171 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3172 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3173 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3174 | |
766aa1c4 VS |
3175 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
3176 | { | |
92e23b99 | 3177 | if (IS_VALLEYVIEW(dev)) |
766aa1c4 | 3178 | return VLV_VGACNTRL; |
92e23b99 SJ |
3179 | else if (INTEL_INFO(dev)->gen >= 5) |
3180 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3181 | else |
3182 | return VGACNTRL; | |
3183 | } | |
3184 | ||
2bb4629a VS |
3185 | static inline void __user *to_user_ptr(u64 address) |
3186 | { | |
3187 | return (void __user *)(uintptr_t)address; | |
3188 | } | |
3189 | ||
df97729f ID |
3190 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3191 | { | |
3192 | unsigned long j = msecs_to_jiffies(m); | |
3193 | ||
3194 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3195 | } | |
3196 | ||
7bd0e226 DV |
3197 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3198 | { | |
3199 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3200 | } | |
3201 | ||
df97729f ID |
3202 | static inline unsigned long |
3203 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3204 | { | |
3205 | unsigned long j = timespec_to_jiffies(value); | |
3206 | ||
3207 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3208 | } | |
3209 | ||
dce56b3c PZ |
3210 | /* |
3211 | * If you need to wait X milliseconds between events A and B, but event B | |
3212 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3213 | * when event A happened, then just before event B you call this function and | |
3214 | * pass the timestamp as the first argument, and X as the second argument. | |
3215 | */ | |
3216 | static inline void | |
3217 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3218 | { | |
ec5e0cfb | 3219 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3220 | |
3221 | /* | |
3222 | * Don't re-read the value of "jiffies" every time since it may change | |
3223 | * behind our back and break the math. | |
3224 | */ | |
3225 | tmp_jiffies = jiffies; | |
3226 | target_jiffies = timestamp_jiffies + | |
3227 | msecs_to_jiffies_timeout(to_wait_ms); | |
3228 | ||
3229 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3230 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3231 | while (remaining_jiffies) | |
3232 | remaining_jiffies = | |
3233 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3234 | } |
3235 | } | |
3236 | ||
581c26e8 JH |
3237 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3238 | struct drm_i915_gem_request *req) | |
3239 | { | |
3240 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) | |
3241 | i915_gem_request_assign(&ring->trace_irq_req, req); | |
3242 | } | |
3243 | ||
1da177e4 | 3244 | #endif |