Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 39 | #include <drm/intel-gtt.h> |
aaa6fd2a | 40 | #include <linux/backlight.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
585fb111 | 42 | |
1da177e4 LT |
43 | /* General customization: |
44 | */ | |
45 | ||
46 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
47 | ||
48 | #define DRIVER_NAME "i915" | |
49 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 50 | #define DRIVER_DATE "20080730" |
1da177e4 | 51 | |
317c35d1 JB |
52 | enum pipe { |
53 | PIPE_A = 0, | |
54 | PIPE_B, | |
9db4a9c7 JB |
55 | PIPE_C, |
56 | I915_MAX_PIPES | |
317c35d1 | 57 | }; |
9db4a9c7 | 58 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 59 | |
80824003 JB |
60 | enum plane { |
61 | PLANE_A = 0, | |
62 | PLANE_B, | |
9db4a9c7 | 63 | PLANE_C, |
80824003 | 64 | }; |
9db4a9c7 | 65 | #define plane_name(p) ((p) + 'A') |
52440211 | 66 | |
2b139522 ED |
67 | enum port { |
68 | PORT_A = 0, | |
69 | PORT_B, | |
70 | PORT_C, | |
71 | PORT_D, | |
72 | PORT_E, | |
73 | I915_MAX_PORTS | |
74 | }; | |
75 | #define port_name(p) ((p) + 'A') | |
76 | ||
62fdfeaf EA |
77 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
78 | ||
9db4a9c7 JB |
79 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
80 | ||
1da177e4 LT |
81 | /* Interface history: |
82 | * | |
83 | * 1.1: Original. | |
0d6aa60b DA |
84 | * 1.2: Add Power Management |
85 | * 1.3: Add vblank support | |
de227f5f | 86 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 87 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
88 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
89 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
90 | */ |
91 | #define DRIVER_MAJOR 1 | |
2228ed67 | 92 | #define DRIVER_MINOR 6 |
1da177e4 LT |
93 | #define DRIVER_PATCHLEVEL 0 |
94 | ||
673a394b | 95 | #define WATCH_COHERENCY 0 |
23bc5982 | 96 | #define WATCH_LISTS 0 |
673a394b | 97 | |
71acb5eb DA |
98 | #define I915_GEM_PHYS_CURSOR_0 1 |
99 | #define I915_GEM_PHYS_CURSOR_1 2 | |
100 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
101 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
102 | ||
103 | struct drm_i915_gem_phys_object { | |
104 | int id; | |
105 | struct page **page_list; | |
106 | drm_dma_handle_t *handle; | |
05394f39 | 107 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
108 | }; |
109 | ||
1da177e4 LT |
110 | struct mem_block { |
111 | struct mem_block *next; | |
112 | struct mem_block *prev; | |
113 | int start; | |
114 | int size; | |
6c340eac | 115 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
116 | }; |
117 | ||
0a3e67a4 JB |
118 | struct opregion_header; |
119 | struct opregion_acpi; | |
120 | struct opregion_swsci; | |
121 | struct opregion_asle; | |
8d715f00 | 122 | struct drm_i915_private; |
0a3e67a4 | 123 | |
8ee1c3db MG |
124 | struct intel_opregion { |
125 | struct opregion_header *header; | |
126 | struct opregion_acpi *acpi; | |
127 | struct opregion_swsci *swsci; | |
128 | struct opregion_asle *asle; | |
44834a67 | 129 | void *vbt; |
01fe9dbd | 130 | u32 __iomem *lid_state; |
8ee1c3db | 131 | }; |
44834a67 | 132 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 133 | |
6ef3d427 CW |
134 | struct intel_overlay; |
135 | struct intel_overlay_error_state; | |
136 | ||
7c1c2871 DA |
137 | struct drm_i915_master_private { |
138 | drm_local_map_t *sarea; | |
139 | struct _drm_i915_sarea *sarea_priv; | |
140 | }; | |
de151cf6 | 141 | #define I915_FENCE_REG_NONE -1 |
4b9de737 DV |
142 | #define I915_MAX_NUM_FENCES 16 |
143 | /* 16 fences + sign bit for FENCE_REG_NONE */ | |
144 | #define I915_MAX_NUM_FENCE_BITS 5 | |
de151cf6 JB |
145 | |
146 | struct drm_i915_fence_reg { | |
007cc8ac | 147 | struct list_head lru_list; |
caea7476 | 148 | struct drm_i915_gem_object *obj; |
1690e1eb | 149 | int pin_count; |
de151cf6 | 150 | }; |
7c1c2871 | 151 | |
9b9d172d | 152 | struct sdvo_device_mapping { |
e957d772 | 153 | u8 initialized; |
9b9d172d | 154 | u8 dvo_port; |
155 | u8 slave_addr; | |
156 | u8 dvo_wiring; | |
e957d772 | 157 | u8 i2c_pin; |
b1083333 | 158 | u8 ddc_pin; |
9b9d172d | 159 | }; |
160 | ||
c4a1d9e4 CW |
161 | struct intel_display_error_state; |
162 | ||
63eeaf38 JB |
163 | struct drm_i915_error_state { |
164 | u32 eir; | |
165 | u32 pgtbl_er; | |
9db4a9c7 | 166 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
167 | u32 tail[I915_NUM_RINGS]; |
168 | u32 head[I915_NUM_RINGS]; | |
d27b1e0e DV |
169 | u32 ipeir[I915_NUM_RINGS]; |
170 | u32 ipehr[I915_NUM_RINGS]; | |
171 | u32 instdone[I915_NUM_RINGS]; | |
172 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 DV |
173 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
174 | /* our own tracking of ring head and tail */ | |
175 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
176 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 177 | u32 error; /* gen6+ */ |
c1cd90ed DV |
178 | u32 instpm[I915_NUM_RINGS]; |
179 | u32 instps[I915_NUM_RINGS]; | |
63eeaf38 | 180 | u32 instdone1; |
d27b1e0e | 181 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 182 | u64 bbaddr; |
33f3f518 DV |
183 | u32 fault_reg[I915_NUM_RINGS]; |
184 | u32 done_reg; | |
c1cd90ed | 185 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 186 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 187 | struct timeval time; |
52d39a21 CW |
188 | struct drm_i915_error_ring { |
189 | struct drm_i915_error_object { | |
190 | int page_count; | |
191 | u32 gtt_offset; | |
192 | u32 *pages[0]; | |
193 | } *ringbuffer, *batchbuffer; | |
194 | struct drm_i915_error_request { | |
195 | long jiffies; | |
196 | u32 seqno; | |
ee4f42b1 | 197 | u32 tail; |
52d39a21 CW |
198 | } *requests; |
199 | int num_requests; | |
200 | } ring[I915_NUM_RINGS]; | |
9df30794 | 201 | struct drm_i915_error_buffer { |
a779e5ab | 202 | u32 size; |
9df30794 CW |
203 | u32 name; |
204 | u32 seqno; | |
205 | u32 gtt_offset; | |
206 | u32 read_domains; | |
207 | u32 write_domain; | |
4b9de737 | 208 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
209 | s32 pinned:2; |
210 | u32 tiling:2; | |
211 | u32 dirty:1; | |
212 | u32 purgeable:1; | |
5d1333fc | 213 | s32 ring:4; |
93dfb40c | 214 | u32 cache_level:2; |
c724e8a9 CW |
215 | } *active_bo, *pinned_bo; |
216 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 217 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 218 | struct intel_display_error_state *display; |
63eeaf38 JB |
219 | }; |
220 | ||
e70236a8 JB |
221 | struct drm_i915_display_funcs { |
222 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 223 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
224 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
225 | void (*disable_fbc)(struct drm_device *dev); | |
226 | int (*get_display_clock_speed)(struct drm_device *dev); | |
227 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 228 | void (*update_wm)(struct drm_device *dev); |
b840d907 JB |
229 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
230 | uint32_t sprite_width, int pixel_size); | |
f564048e EA |
231 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
232 | struct drm_display_mode *mode, | |
233 | struct drm_display_mode *adjusted_mode, | |
234 | int x, int y, | |
235 | struct drm_framebuffer *old_fb); | |
e0dac65e WF |
236 | void (*write_eld)(struct drm_connector *connector, |
237 | struct drm_crtc *crtc); | |
674cf967 | 238 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 239 | void (*init_clock_gating)(struct drm_device *dev); |
645c62a5 | 240 | void (*init_pch_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
241 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
242 | struct drm_framebuffer *fb, | |
243 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
244 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
245 | int x, int y); | |
8d715f00 KP |
246 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
247 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
e70236a8 JB |
248 | /* clock updates for mode set */ |
249 | /* cursor updates */ | |
250 | /* render clock increase/decrease */ | |
251 | /* display clock increase/decrease */ | |
252 | /* pll clock increase/decrease */ | |
e70236a8 JB |
253 | }; |
254 | ||
cfdf1fa2 | 255 | struct intel_device_info { |
c96c3a8c | 256 | u8 gen; |
0206e353 AJ |
257 | u8 is_mobile:1; |
258 | u8 is_i85x:1; | |
259 | u8 is_i915g:1; | |
260 | u8 is_i945gm:1; | |
261 | u8 is_g33:1; | |
262 | u8 need_gfx_hws:1; | |
263 | u8 is_g4x:1; | |
264 | u8 is_pineview:1; | |
265 | u8 is_broadwater:1; | |
266 | u8 is_crestline:1; | |
267 | u8 is_ivybridge:1; | |
70a3eb7a | 268 | u8 is_valleyview:1; |
7e508a27 | 269 | u8 has_pch_split:1; |
4cae9ae0 | 270 | u8 is_haswell:1; |
0206e353 AJ |
271 | u8 has_fbc:1; |
272 | u8 has_pipe_cxsr:1; | |
273 | u8 has_hotplug:1; | |
274 | u8 cursor_needs_physical:1; | |
275 | u8 has_overlay:1; | |
276 | u8 overlay_needs_physical:1; | |
277 | u8 supports_tv:1; | |
278 | u8 has_bsd_ring:1; | |
279 | u8 has_blt_ring:1; | |
3d29b842 | 280 | u8 has_llc:1; |
cfdf1fa2 KH |
281 | }; |
282 | ||
1d2a314c DV |
283 | #define I915_PPGTT_PD_ENTRIES 512 |
284 | #define I915_PPGTT_PT_ENTRIES 1024 | |
285 | struct i915_hw_ppgtt { | |
286 | unsigned num_pd_entries; | |
287 | struct page **pt_pages; | |
288 | uint32_t pd_offset; | |
289 | dma_addr_t *pt_dma_addr; | |
290 | dma_addr_t scratch_page_dma_addr; | |
291 | }; | |
292 | ||
b5e50c3f | 293 | enum no_fbc_reason { |
bed4a673 | 294 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
295 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
296 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
297 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
298 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
299 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 300 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 301 | FBC_MODULE_PARAM, |
b5e50c3f JB |
302 | }; |
303 | ||
3bad0781 ZW |
304 | enum intel_pch { |
305 | PCH_IBX, /* Ibexpeak PCH */ | |
306 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 307 | PCH_LPT, /* Lynxpoint PCH */ |
3bad0781 ZW |
308 | }; |
309 | ||
b690e96c | 310 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 311 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 312 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 313 | |
8be48d92 | 314 | struct intel_fbdev; |
1630fe75 | 315 | struct intel_fbc_work; |
38651674 | 316 | |
c2b9152f DV |
317 | struct intel_gmbus { |
318 | struct i2c_adapter adapter; | |
f6f808c8 | 319 | bool force_bit; |
c2b9152f | 320 | u32 reg0; |
36c785f0 | 321 | u32 gpio_reg; |
c167a6fc | 322 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
323 | struct drm_i915_private *dev_priv; |
324 | }; | |
325 | ||
1da177e4 | 326 | typedef struct drm_i915_private { |
673a394b EA |
327 | struct drm_device *dev; |
328 | ||
cfdf1fa2 KH |
329 | const struct intel_device_info *info; |
330 | ||
ac5c4e76 | 331 | int has_gem; |
72bfa19c | 332 | int relative_constants_mode; |
ac5c4e76 | 333 | |
3043c60c | 334 | void __iomem *regs; |
9f1f46a4 DV |
335 | /** gt_fifo_count and the subsequent register write are synchronized |
336 | * with dev->struct_mutex. */ | |
337 | unsigned gt_fifo_count; | |
338 | /** forcewake_count is protected by gt_lock */ | |
339 | unsigned forcewake_count; | |
340 | /** gt_lock is also taken in irq contexts. */ | |
341 | struct spinlock gt_lock; | |
1da177e4 | 342 | |
f2c9677b | 343 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
f899fc64 | 344 | |
8a8ed1f5 YS |
345 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
346 | * controller on different i2c buses. */ | |
347 | struct mutex gmbus_mutex; | |
348 | ||
110447fc DV |
349 | /** |
350 | * Base address of the gmbus and gpio block. | |
351 | */ | |
352 | uint32_t gpio_mmio_base; | |
353 | ||
ec2a4c3f | 354 | struct pci_dev *bridge_dev; |
1ec14ad3 | 355 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
6f392d54 | 356 | uint32_t next_seqno; |
1da177e4 | 357 | |
9c8da5eb | 358 | drm_dma_handle_t *status_page_dmah; |
0a3e67a4 | 359 | uint32_t counter; |
dc7a9319 | 360 | drm_local_map_t hws_map; |
05394f39 CW |
361 | struct drm_i915_gem_object *pwrctx; |
362 | struct drm_i915_gem_object *renderctx; | |
1da177e4 | 363 | |
d7658989 JB |
364 | struct resource mch_res; |
365 | ||
a6b54f3f | 366 | unsigned int cpp; |
1da177e4 LT |
367 | int back_offset; |
368 | int front_offset; | |
369 | int current_page; | |
370 | int page_flipping; | |
1da177e4 | 371 | |
1da177e4 | 372 | atomic_t irq_received; |
1ec14ad3 CW |
373 | |
374 | /* protects the irq masks */ | |
375 | spinlock_t irq_lock; | |
57f350b6 JB |
376 | |
377 | /* DPIO indirect register protection */ | |
378 | spinlock_t dpio_lock; | |
379 | ||
ed4cb414 | 380 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
7c463586 | 381 | u32 pipestat[2]; |
1ec14ad3 CW |
382 | u32 irq_mask; |
383 | u32 gt_irq_mask; | |
384 | u32 pch_irq_mask; | |
1da177e4 | 385 | |
5ca58282 JB |
386 | u32 hotplug_supported_mask; |
387 | struct work_struct hotplug_work; | |
388 | ||
1da177e4 LT |
389 | int tex_lru_log_granularity; |
390 | int allow_batchbuffer; | |
0d6aa60b | 391 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 392 | int vblank_pipe; |
a3524f1b | 393 | int num_pipe; |
a6b54f3f | 394 | |
f65d9421 | 395 | /* For hangcheck timer */ |
576ae4b8 | 396 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
f65d9421 BG |
397 | struct timer_list hangcheck_timer; |
398 | int hangcheck_count; | |
399 | uint32_t last_acthd; | |
097354eb DV |
400 | uint32_t last_acthd_bsd; |
401 | uint32_t last_acthd_blt; | |
cbb465e7 CW |
402 | uint32_t last_instdone; |
403 | uint32_t last_instdone1; | |
f65d9421 | 404 | |
80824003 | 405 | unsigned long cfb_size; |
016b9b61 CW |
406 | unsigned int cfb_fb; |
407 | enum plane cfb_plane; | |
bed4a673 | 408 | int cfb_y; |
1630fe75 | 409 | struct intel_fbc_work *fbc_work; |
80824003 | 410 | |
8ee1c3db MG |
411 | struct intel_opregion opregion; |
412 | ||
02e792fb DV |
413 | /* overlay */ |
414 | struct intel_overlay *overlay; | |
b840d907 | 415 | bool sprite_scaling_enabled; |
02e792fb | 416 | |
79e53945 | 417 | /* LVDS info */ |
a9573556 | 418 | int backlight_level; /* restore backlight to this value */ |
47356eb6 | 419 | bool backlight_enabled; |
88631706 ML |
420 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
421 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
422 | |
423 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
424 | unsigned int int_tv_support:1; |
425 | unsigned int lvds_dither:1; | |
426 | unsigned int lvds_vbt:1; | |
427 | unsigned int int_crt_support:1; | |
43565a06 | 428 | unsigned int lvds_use_ssc:1; |
abd06860 | 429 | unsigned int display_clock_mode:1; |
43565a06 | 430 | int lvds_ssc_freq; |
b0354385 TI |
431 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
432 | unsigned int lvds_val; /* used for checking LVDS channel mode */ | |
5ceb0f9b | 433 | struct { |
9f0e7ff4 JB |
434 | int rate; |
435 | int lanes; | |
436 | int preemphasis; | |
437 | int vswing; | |
438 | ||
439 | bool initialized; | |
440 | bool support; | |
441 | int bpp; | |
442 | struct edp_power_seq pps; | |
5ceb0f9b | 443 | } edp; |
89667383 | 444 | bool no_aux_handshake; |
79e53945 | 445 | |
c1c7af60 JB |
446 | struct notifier_block lid_notifier; |
447 | ||
f899fc64 | 448 | int crt_ddc_pin; |
4b9de737 | 449 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
de151cf6 JB |
450 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
451 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
452 | ||
95534263 | 453 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 454 | |
63eeaf38 JB |
455 | spinlock_t error_lock; |
456 | struct drm_i915_error_state *first_error; | |
8a905236 | 457 | struct work_struct error_work; |
30dbf0c0 | 458 | struct completion error_completion; |
9c9fe1f8 | 459 | struct workqueue_struct *wq; |
63eeaf38 | 460 | |
e70236a8 JB |
461 | /* Display functions */ |
462 | struct drm_i915_display_funcs display; | |
463 | ||
3bad0781 ZW |
464 | /* PCH chipset type */ |
465 | enum intel_pch pch_type; | |
466 | ||
b690e96c JB |
467 | unsigned long quirks; |
468 | ||
ba8bbcf6 | 469 | /* Register state */ |
c9354c85 | 470 | bool modeset_on_lid; |
ba8bbcf6 JB |
471 | u8 saveLBB; |
472 | u32 saveDSPACNTR; | |
473 | u32 saveDSPBCNTR; | |
e948e994 | 474 | u32 saveDSPARB; |
968b503e | 475 | u32 saveHWS; |
ba8bbcf6 JB |
476 | u32 savePIPEACONF; |
477 | u32 savePIPEBCONF; | |
478 | u32 savePIPEASRC; | |
479 | u32 savePIPEBSRC; | |
480 | u32 saveFPA0; | |
481 | u32 saveFPA1; | |
482 | u32 saveDPLL_A; | |
483 | u32 saveDPLL_A_MD; | |
484 | u32 saveHTOTAL_A; | |
485 | u32 saveHBLANK_A; | |
486 | u32 saveHSYNC_A; | |
487 | u32 saveVTOTAL_A; | |
488 | u32 saveVBLANK_A; | |
489 | u32 saveVSYNC_A; | |
490 | u32 saveBCLRPAT_A; | |
5586c8bc | 491 | u32 saveTRANSACONF; |
42048781 ZW |
492 | u32 saveTRANS_HTOTAL_A; |
493 | u32 saveTRANS_HBLANK_A; | |
494 | u32 saveTRANS_HSYNC_A; | |
495 | u32 saveTRANS_VTOTAL_A; | |
496 | u32 saveTRANS_VBLANK_A; | |
497 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 498 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
499 | u32 saveDSPASTRIDE; |
500 | u32 saveDSPASIZE; | |
501 | u32 saveDSPAPOS; | |
585fb111 | 502 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
503 | u32 saveDSPASURF; |
504 | u32 saveDSPATILEOFF; | |
505 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 506 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
507 | u32 saveBLC_PWM_CTL; |
508 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
509 | u32 saveBLC_CPU_PWM_CTL; |
510 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
511 | u32 saveFPB0; |
512 | u32 saveFPB1; | |
513 | u32 saveDPLL_B; | |
514 | u32 saveDPLL_B_MD; | |
515 | u32 saveHTOTAL_B; | |
516 | u32 saveHBLANK_B; | |
517 | u32 saveHSYNC_B; | |
518 | u32 saveVTOTAL_B; | |
519 | u32 saveVBLANK_B; | |
520 | u32 saveVSYNC_B; | |
521 | u32 saveBCLRPAT_B; | |
5586c8bc | 522 | u32 saveTRANSBCONF; |
42048781 ZW |
523 | u32 saveTRANS_HTOTAL_B; |
524 | u32 saveTRANS_HBLANK_B; | |
525 | u32 saveTRANS_HSYNC_B; | |
526 | u32 saveTRANS_VTOTAL_B; | |
527 | u32 saveTRANS_VBLANK_B; | |
528 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 529 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
530 | u32 saveDSPBSTRIDE; |
531 | u32 saveDSPBSIZE; | |
532 | u32 saveDSPBPOS; | |
585fb111 | 533 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
534 | u32 saveDSPBSURF; |
535 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
536 | u32 saveVGA0; |
537 | u32 saveVGA1; | |
538 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
539 | u32 saveVGACNTRL; |
540 | u32 saveADPA; | |
541 | u32 saveLVDS; | |
585fb111 JB |
542 | u32 savePP_ON_DELAYS; |
543 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
544 | u32 saveDVOA; |
545 | u32 saveDVOB; | |
546 | u32 saveDVOC; | |
547 | u32 savePP_ON; | |
548 | u32 savePP_OFF; | |
549 | u32 savePP_CONTROL; | |
585fb111 | 550 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
551 | u32 savePFIT_CONTROL; |
552 | u32 save_palette_a[256]; | |
553 | u32 save_palette_b[256]; | |
06027f91 | 554 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
555 | u32 saveFBC_CFB_BASE; |
556 | u32 saveFBC_LL_BASE; | |
557 | u32 saveFBC_CONTROL; | |
558 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
559 | u32 saveIER; |
560 | u32 saveIIR; | |
561 | u32 saveIMR; | |
42048781 ZW |
562 | u32 saveDEIER; |
563 | u32 saveDEIMR; | |
564 | u32 saveGTIER; | |
565 | u32 saveGTIMR; | |
566 | u32 saveFDI_RXA_IMR; | |
567 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 568 | u32 saveCACHE_MODE_0; |
1f84e550 | 569 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
570 | u32 saveSWF0[16]; |
571 | u32 saveSWF1[16]; | |
572 | u32 saveSWF2[3]; | |
573 | u8 saveMSR; | |
574 | u8 saveSR[8]; | |
123f794f | 575 | u8 saveGR[25]; |
ba8bbcf6 | 576 | u8 saveAR_INDEX; |
a59e122a | 577 | u8 saveAR[21]; |
ba8bbcf6 | 578 | u8 saveDACMASK; |
a59e122a | 579 | u8 saveCR[37]; |
4b9de737 | 580 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
581 | u32 saveCURACNTR; |
582 | u32 saveCURAPOS; | |
583 | u32 saveCURABASE; | |
584 | u32 saveCURBCNTR; | |
585 | u32 saveCURBPOS; | |
586 | u32 saveCURBBASE; | |
587 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
588 | u32 saveDP_B; |
589 | u32 saveDP_C; | |
590 | u32 saveDP_D; | |
591 | u32 savePIPEA_GMCH_DATA_M; | |
592 | u32 savePIPEB_GMCH_DATA_M; | |
593 | u32 savePIPEA_GMCH_DATA_N; | |
594 | u32 savePIPEB_GMCH_DATA_N; | |
595 | u32 savePIPEA_DP_LINK_M; | |
596 | u32 savePIPEB_DP_LINK_M; | |
597 | u32 savePIPEA_DP_LINK_N; | |
598 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
599 | u32 saveFDI_RXA_CTL; |
600 | u32 saveFDI_TXA_CTL; | |
601 | u32 saveFDI_RXB_CTL; | |
602 | u32 saveFDI_TXB_CTL; | |
603 | u32 savePFA_CTL_1; | |
604 | u32 savePFB_CTL_1; | |
605 | u32 savePFA_WIN_SZ; | |
606 | u32 savePFB_WIN_SZ; | |
607 | u32 savePFA_WIN_POS; | |
608 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
609 | u32 savePCH_DREF_CONTROL; |
610 | u32 saveDISP_ARB_CTL; | |
611 | u32 savePIPEA_DATA_M1; | |
612 | u32 savePIPEA_DATA_N1; | |
613 | u32 savePIPEA_LINK_M1; | |
614 | u32 savePIPEA_LINK_N1; | |
615 | u32 savePIPEB_DATA_M1; | |
616 | u32 savePIPEB_DATA_N1; | |
617 | u32 savePIPEB_LINK_M1; | |
618 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 619 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 620 | u32 savePCH_PORT_HOTPLUG; |
673a394b EA |
621 | |
622 | struct { | |
19966754 | 623 | /** Bridge to intel-gtt-ko */ |
c64f7ba5 | 624 | const struct intel_gtt *gtt; |
19966754 | 625 | /** Memory allocator for GTT stolen memory */ |
fe669bf8 | 626 | struct drm_mm stolen; |
19966754 | 627 | /** Memory allocator for GTT */ |
673a394b | 628 | struct drm_mm gtt_space; |
93a37f20 DV |
629 | /** List of all objects in gtt_space. Used to restore gtt |
630 | * mappings on resume */ | |
631 | struct list_head gtt_list; | |
bee4a186 CW |
632 | |
633 | /** Usable portion of the GTT for GEM */ | |
634 | unsigned long gtt_start; | |
a6e0aa42 | 635 | unsigned long gtt_mappable_end; |
bee4a186 | 636 | unsigned long gtt_end; |
673a394b | 637 | |
0839ccb8 | 638 | struct io_mapping *gtt_mapping; |
ab657db1 | 639 | int gtt_mtrr; |
0839ccb8 | 640 | |
1d2a314c DV |
641 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
642 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
643 | ||
17250b71 | 644 | struct shrinker inactive_shrinker; |
31169714 | 645 | |
69dc4987 CW |
646 | /** |
647 | * List of objects currently involved in rendering. | |
648 | * | |
649 | * Includes buffers having the contents of their GPU caches | |
650 | * flushed, not necessarily primitives. last_rendering_seqno | |
651 | * represents when the rendering involved will be completed. | |
652 | * | |
653 | * A reference is held on the buffer while on this list. | |
654 | */ | |
655 | struct list_head active_list; | |
656 | ||
673a394b EA |
657 | /** |
658 | * List of objects which are not in the ringbuffer but which | |
659 | * still have a write_domain which needs to be flushed before | |
660 | * unbinding. | |
661 | * | |
ce44b0ea EA |
662 | * last_rendering_seqno is 0 while an object is in this list. |
663 | * | |
673a394b EA |
664 | * A reference is held on the buffer while on this list. |
665 | */ | |
666 | struct list_head flushing_list; | |
667 | ||
668 | /** | |
669 | * LRU list of objects which are not in the ringbuffer and | |
670 | * are ready to unbind, but are still in the GTT. | |
671 | * | |
ce44b0ea EA |
672 | * last_rendering_seqno is 0 while an object is in this list. |
673 | * | |
673a394b EA |
674 | * A reference is not held on the buffer while on this list, |
675 | * as merely being GTT-bound shouldn't prevent its being | |
676 | * freed, and we'll pull it off the list in the free path. | |
677 | */ | |
678 | struct list_head inactive_list; | |
679 | ||
f13d3f73 CW |
680 | /** |
681 | * LRU list of objects which are not in the ringbuffer but | |
682 | * are still pinned in the GTT. | |
683 | */ | |
684 | struct list_head pinned_list; | |
685 | ||
a09ba7fa EA |
686 | /** LRU list of objects with fence regs on them. */ |
687 | struct list_head fence_list; | |
688 | ||
be72615b CW |
689 | /** |
690 | * List of objects currently pending being freed. | |
691 | * | |
692 | * These objects are no longer in use, but due to a signal | |
693 | * we were prevented from freeing them at the appointed time. | |
694 | */ | |
695 | struct list_head deferred_free_list; | |
696 | ||
673a394b EA |
697 | /** |
698 | * We leave the user IRQ off as much as possible, | |
699 | * but this means that requests will finish and never | |
700 | * be retired once the system goes idle. Set a timer to | |
701 | * fire periodically while the ring is running. When it | |
702 | * fires, go retire requests. | |
703 | */ | |
704 | struct delayed_work retire_work; | |
705 | ||
ce453d81 CW |
706 | /** |
707 | * Are we in a non-interruptible section of code like | |
708 | * modesetting? | |
709 | */ | |
710 | bool interruptible; | |
711 | ||
673a394b EA |
712 | /** |
713 | * Flag if the X Server, and thus DRM, is not currently in | |
714 | * control of the device. | |
715 | * | |
716 | * This is set between LeaveVT and EnterVT. It needs to be | |
717 | * replaced with a semaphore. It also needs to be | |
718 | * transitioned away from for kernel modesetting. | |
719 | */ | |
720 | int suspended; | |
721 | ||
722 | /** | |
723 | * Flag if the hardware appears to be wedged. | |
724 | * | |
725 | * This is set when attempts to idle the device timeout. | |
25985edc | 726 | * It prevents command submission from occurring and makes |
673a394b EA |
727 | * every pending request fail |
728 | */ | |
ba1234d1 | 729 | atomic_t wedged; |
673a394b EA |
730 | |
731 | /** Bit 6 swizzling required for X tiling */ | |
732 | uint32_t bit_6_swizzle_x; | |
733 | /** Bit 6 swizzling required for Y tiling */ | |
734 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
735 | |
736 | /* storage for physical objects */ | |
737 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 738 | |
73aa808f | 739 | /* accounting, useful for userland debugging */ |
73aa808f | 740 | size_t gtt_total; |
6299f992 CW |
741 | size_t mappable_gtt_total; |
742 | size_t object_memory; | |
73aa808f | 743 | u32 object_count; |
673a394b | 744 | } mm; |
9b9d172d | 745 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
746 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
747 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
748 | /* Panel fitter placement and size for Ironlake+ */ |
749 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 750 | |
27f8227b JB |
751 | struct drm_crtc *plane_to_crtc_mapping[3]; |
752 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 | 753 | wait_queue_head_t pending_flip_queue; |
1afe3e9d | 754 | bool flip_pending_is_done; |
6b95a207 | 755 | |
652c393a JB |
756 | /* Reclocking support */ |
757 | bool render_reclock_avail; | |
758 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
759 | /* indicates the reduced downclock for LVDS*/ |
760 | int lvds_downclock; | |
652c393a JB |
761 | struct work_struct idle_work; |
762 | struct timer_list idle_timer; | |
763 | bool busy; | |
764 | u16 orig_clock; | |
6363ee6f ZY |
765 | int child_dev_num; |
766 | struct child_device_config *child_dev; | |
a2565377 | 767 | struct drm_connector *int_lvds_connector; |
aaa6fd2a | 768 | struct drm_connector *int_edp_connector; |
f97108d1 | 769 | |
c4804411 | 770 | bool mchbar_need_disable; |
f97108d1 | 771 | |
4912d041 BW |
772 | struct work_struct rps_work; |
773 | spinlock_t rps_lock; | |
774 | u32 pm_iir; | |
775 | ||
f97108d1 JB |
776 | u8 cur_delay; |
777 | u8 min_delay; | |
778 | u8 max_delay; | |
7648fa99 JB |
779 | u8 fmax; |
780 | u8 fstart; | |
781 | ||
05394f39 CW |
782 | u64 last_count1; |
783 | unsigned long last_time1; | |
4ed0b577 | 784 | unsigned long chipset_power; |
05394f39 CW |
785 | u64 last_count2; |
786 | struct timespec last_time2; | |
787 | unsigned long gfx_power; | |
788 | int c_m; | |
789 | int r_t; | |
790 | u8 corr; | |
7648fa99 | 791 | spinlock_t *mchdev_lock; |
b5e50c3f JB |
792 | |
793 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 794 | |
20bf377e JB |
795 | struct drm_mm_node *compressed_fb; |
796 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 797 | |
ae681d96 CW |
798 | unsigned long last_gpu_reset; |
799 | ||
8be48d92 DA |
800 | /* list of fbdev register on this device */ |
801 | struct intel_fbdev *fbdev; | |
e953fd7b | 802 | |
aaa6fd2a MG |
803 | struct backlight_device *backlight; |
804 | ||
e953fd7b | 805 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 806 | struct drm_property *force_audio_property; |
1da177e4 LT |
807 | } drm_i915_private_t; |
808 | ||
b1d7e4b4 WF |
809 | enum hdmi_force_audio { |
810 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
811 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
812 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
813 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
814 | }; | |
815 | ||
93dfb40c CW |
816 | enum i915_cache_level { |
817 | I915_CACHE_NONE, | |
818 | I915_CACHE_LLC, | |
819 | I915_CACHE_LLC_MLC, /* gen6+ */ | |
820 | }; | |
821 | ||
673a394b | 822 | struct drm_i915_gem_object { |
c397b908 | 823 | struct drm_gem_object base; |
673a394b EA |
824 | |
825 | /** Current space allocated to this object in the GTT, if any. */ | |
826 | struct drm_mm_node *gtt_space; | |
93a37f20 | 827 | struct list_head gtt_list; |
673a394b EA |
828 | |
829 | /** This object's place on the active/flushing/inactive lists */ | |
69dc4987 CW |
830 | struct list_head ring_list; |
831 | struct list_head mm_list; | |
99fcb766 DV |
832 | /** This object's place on GPU write list */ |
833 | struct list_head gpu_write_list; | |
432e58ed CW |
834 | /** This object's place in the batchbuffer or on the eviction list */ |
835 | struct list_head exec_list; | |
673a394b EA |
836 | |
837 | /** | |
838 | * This is set if the object is on the active or flushing lists | |
839 | * (has pending rendering), and is not set if it's on inactive (ready | |
840 | * to be unbound). | |
841 | */ | |
0206e353 | 842 | unsigned int active:1; |
673a394b EA |
843 | |
844 | /** | |
845 | * This is set if the object has been written to since last bound | |
846 | * to the GTT | |
847 | */ | |
0206e353 | 848 | unsigned int dirty:1; |
778c3544 | 849 | |
87ca9c8a CW |
850 | /** |
851 | * This is set if the object has been written to since the last | |
852 | * GPU flush. | |
853 | */ | |
0206e353 | 854 | unsigned int pending_gpu_write:1; |
87ca9c8a | 855 | |
778c3544 DV |
856 | /** |
857 | * Fence register bits (if any) for this object. Will be set | |
858 | * as needed when mapped into the GTT. | |
859 | * Protected by dev->struct_mutex. | |
778c3544 | 860 | */ |
4b9de737 | 861 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 862 | |
778c3544 DV |
863 | /** |
864 | * Advice: are the backing pages purgeable? | |
865 | */ | |
0206e353 | 866 | unsigned int madv:2; |
778c3544 | 867 | |
778c3544 DV |
868 | /** |
869 | * Current tiling mode for the object. | |
870 | */ | |
0206e353 AJ |
871 | unsigned int tiling_mode:2; |
872 | unsigned int tiling_changed:1; | |
778c3544 DV |
873 | |
874 | /** How many users have pinned this object in GTT space. The following | |
875 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
876 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
877 | * times for the same batchbuffer), and the framebuffer code. When | |
878 | * switching/pageflipping, the framebuffer code has at most two buffers | |
879 | * pinned per crtc. | |
880 | * | |
881 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
882 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 883 | unsigned int pin_count:4; |
778c3544 | 884 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 885 | |
75e9e915 DV |
886 | /** |
887 | * Is the object at the current location in the gtt mappable and | |
888 | * fenceable? Used to avoid costly recalculations. | |
889 | */ | |
0206e353 | 890 | unsigned int map_and_fenceable:1; |
75e9e915 | 891 | |
fb7d516a DV |
892 | /** |
893 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
894 | * mappable by accident). Track pin and fault separate for a more | |
895 | * accurate mappable working set. | |
896 | */ | |
0206e353 AJ |
897 | unsigned int fault_mappable:1; |
898 | unsigned int pin_mappable:1; | |
fb7d516a | 899 | |
caea7476 CW |
900 | /* |
901 | * Is the GPU currently using a fence to access this buffer, | |
902 | */ | |
903 | unsigned int pending_fenced_gpu_access:1; | |
904 | unsigned int fenced_gpu_access:1; | |
905 | ||
93dfb40c CW |
906 | unsigned int cache_level:2; |
907 | ||
7bddb01f | 908 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 909 | unsigned int has_global_gtt_mapping:1; |
7bddb01f | 910 | |
856fa198 | 911 | struct page **pages; |
673a394b | 912 | |
185cbcb3 DV |
913 | /** |
914 | * DMAR support | |
915 | */ | |
916 | struct scatterlist *sg_list; | |
917 | int num_sg; | |
918 | ||
67731b87 CW |
919 | /** |
920 | * Used for performing relocations during execbuffer insertion. | |
921 | */ | |
922 | struct hlist_node exec_node; | |
923 | unsigned long exec_handle; | |
6fe4f140 | 924 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 925 | |
673a394b EA |
926 | /** |
927 | * Current offset of the object in GTT space. | |
928 | * | |
929 | * This is the same as gtt_space->start | |
930 | */ | |
931 | uint32_t gtt_offset; | |
e67b8ce1 | 932 | |
caea7476 CW |
933 | struct intel_ring_buffer *ring; |
934 | ||
1c293ea3 CW |
935 | /** Breadcrumb of last rendering to the buffer. */ |
936 | uint32_t last_rendering_seqno; | |
caea7476 CW |
937 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
938 | uint32_t last_fenced_seqno; | |
673a394b | 939 | |
778c3544 | 940 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 941 | uint32_t stride; |
673a394b | 942 | |
280b713b | 943 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 944 | unsigned long *bit_17; |
280b713b | 945 | |
79e53945 JB |
946 | /** User space pin count and filp owning the pin */ |
947 | uint32_t user_pin_count; | |
948 | struct drm_file *pin_filp; | |
71acb5eb DA |
949 | |
950 | /** for phy allocated objects */ | |
951 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 952 | |
6b95a207 KH |
953 | /** |
954 | * Number of crtcs where this object is currently the fb, but | |
955 | * will be page flipped away on the next vblank. When it | |
956 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
957 | */ | |
958 | atomic_t pending_flip; | |
673a394b EA |
959 | }; |
960 | ||
62b8b215 | 961 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 962 | |
673a394b EA |
963 | /** |
964 | * Request queue structure. | |
965 | * | |
966 | * The request queue allows us to note sequence numbers that have been emitted | |
967 | * and may be associated with active buffers to be retired. | |
968 | * | |
969 | * By keeping this list, we can avoid having to do questionable | |
970 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
971 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
972 | */ | |
973 | struct drm_i915_gem_request { | |
852835f3 ZN |
974 | /** On Which ring this request was generated */ |
975 | struct intel_ring_buffer *ring; | |
976 | ||
673a394b EA |
977 | /** GEM sequence number associated with this request. */ |
978 | uint32_t seqno; | |
979 | ||
a71d8d94 CW |
980 | /** Postion in the ringbuffer of the end of the request */ |
981 | u32 tail; | |
982 | ||
673a394b EA |
983 | /** Time at which this request was emitted, in jiffies. */ |
984 | unsigned long emitted_jiffies; | |
985 | ||
b962442e | 986 | /** global list entry for this request */ |
673a394b | 987 | struct list_head list; |
b962442e | 988 | |
f787a5f5 | 989 | struct drm_i915_file_private *file_priv; |
b962442e EA |
990 | /** file_priv list entry for this request */ |
991 | struct list_head client_list; | |
673a394b EA |
992 | }; |
993 | ||
994 | struct drm_i915_file_private { | |
995 | struct { | |
1c25595f | 996 | struct spinlock lock; |
b962442e | 997 | struct list_head request_list; |
673a394b EA |
998 | } mm; |
999 | }; | |
1000 | ||
cae5852d ZN |
1001 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1002 | ||
1003 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1004 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1005 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
1006 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1007 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1008 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1009 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1010 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1011 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1012 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
1013 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1014 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1015 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1016 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1017 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1018 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
1019 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
1020 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 1021 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
70a3eb7a | 1022 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1023 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
cae5852d ZN |
1024 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
1025 | ||
85436696 JB |
1026 | /* |
1027 | * The genX designation typically refers to the render engine, so render | |
1028 | * capability related checks should use IS_GEN, while display and other checks | |
1029 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1030 | * chips, etc.). | |
1031 | */ | |
cae5852d ZN |
1032 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1033 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1034 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1035 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1036 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1037 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1038 | |
1039 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1040 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
3d29b842 | 1041 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
1042 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1043 | ||
1d2a314c DV |
1044 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) |
1045 | ||
05394f39 | 1046 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1047 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1048 | ||
1049 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
1050 | * rows, which changed the alignment requirements and fence programming. | |
1051 | */ | |
1052 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1053 | IS_I915GM(dev))) | |
1054 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1055 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1056 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1057 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1058 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1059 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
1060 | /* dsparb controlled by hw only */ | |
1061 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1062 | ||
1063 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1064 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1065 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1066 | |
7e508a27 | 1067 | #define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split) |
eceae481 | 1068 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
cae5852d ZN |
1069 | |
1070 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
eb877ebf | 1071 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1072 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1073 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
1074 | ||
05394f39 CW |
1075 | #include "i915_trace.h" |
1076 | ||
83b7f9ac ED |
1077 | /** |
1078 | * RC6 is a special power stage which allows the GPU to enter an very | |
1079 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
1080 | * stage is entered automatically when the GPU is idle when RC6 support is | |
1081 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
1082 | * | |
1083 | * There are different RC6 modes available in Intel GPU, which differentiate | |
1084 | * among each other with the latency required to enter and leave RC6 and | |
1085 | * voltage consumed by the GPU in different states. | |
1086 | * | |
1087 | * The combination of the following flags define which states GPU is allowed | |
1088 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
1089 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
1090 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
1091 | * which brings the most power savings; deeper states save more power, but | |
1092 | * require higher latency to switch to and wake up. | |
1093 | */ | |
1094 | #define INTEL_RC6_ENABLE (1<<0) | |
1095 | #define INTEL_RC6p_ENABLE (1<<1) | |
1096 | #define INTEL_RC6pp_ENABLE (1<<2) | |
1097 | ||
c153f45f | 1098 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1099 | extern int i915_max_ioctl; |
a35d9d3c BW |
1100 | extern unsigned int i915_fbpercrtc __always_unused; |
1101 | extern int i915_panel_ignore_lid __read_mostly; | |
1102 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1103 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1104 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1105 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1106 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1107 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1108 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1109 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1110 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1111 | extern int i915_enable_ppgtt __read_mostly; |
b3a83639 | 1112 | |
6a9ee8af DA |
1113 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1114 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1115 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1116 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1117 | ||
1da177e4 | 1118 | /* i915_dma.c */ |
84b1fd10 | 1119 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1120 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1121 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1122 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1123 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1124 | extern void i915_driver_preclose(struct drm_device *dev, |
1125 | struct drm_file *file_priv); | |
673a394b EA |
1126 | extern void i915_driver_postclose(struct drm_device *dev, |
1127 | struct drm_file *file_priv); | |
84b1fd10 | 1128 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1129 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1130 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1131 | unsigned long arg); | |
c43b5634 | 1132 | #endif |
673a394b | 1133 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1134 | struct drm_clip_rect *box, |
1135 | int DR1, int DR4); | |
f803aa55 | 1136 | extern int i915_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
1137 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1138 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1139 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1140 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1141 | ||
af6061af | 1142 | |
1da177e4 | 1143 | /* i915_irq.c */ |
f65d9421 | 1144 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1145 | void i915_handle_error(struct drm_device *dev, bool wedged); |
c153f45f EA |
1146 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
1147 | struct drm_file *file_priv); | |
1148 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
1149 | struct drm_file *file_priv); | |
1da177e4 | 1150 | |
f71d4af4 | 1151 | extern void intel_irq_init(struct drm_device *dev); |
b1f14ad0 | 1152 | |
c153f45f EA |
1153 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1154 | struct drm_file *file_priv); | |
1155 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
1156 | struct drm_file *file_priv); | |
1157 | extern int i915_vblank_swap(struct drm_device *dev, void *data, | |
1158 | struct drm_file *file_priv); | |
1da177e4 | 1159 | |
7c463586 KP |
1160 | void |
1161 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1162 | ||
1163 | void | |
1164 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1165 | ||
0206e353 | 1166 | void intel_enable_asle(struct drm_device *dev); |
01c66889 | 1167 | |
3bd3c932 CW |
1168 | #ifdef CONFIG_DEBUG_FS |
1169 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1170 | #else | |
1171 | #define i915_destroy_error_state(x) | |
1172 | #endif | |
1173 | ||
7c463586 | 1174 | |
673a394b EA |
1175 | /* i915_gem.c */ |
1176 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1177 | struct drm_file *file_priv); | |
1178 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1179 | struct drm_file *file_priv); | |
1180 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1181 | struct drm_file *file_priv); | |
1182 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1183 | struct drm_file *file_priv); | |
1184 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1185 | struct drm_file *file_priv); | |
de151cf6 JB |
1186 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1187 | struct drm_file *file_priv); | |
673a394b EA |
1188 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1189 | struct drm_file *file_priv); | |
1190 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1191 | struct drm_file *file_priv); | |
1192 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1193 | struct drm_file *file_priv); | |
76446cac JB |
1194 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1195 | struct drm_file *file_priv); | |
673a394b EA |
1196 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1197 | struct drm_file *file_priv); | |
1198 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1199 | struct drm_file *file_priv); | |
1200 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1201 | struct drm_file *file_priv); | |
1202 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
1203 | struct drm_file *file_priv); | |
3ef94daa CW |
1204 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1205 | struct drm_file *file_priv); | |
673a394b EA |
1206 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1207 | struct drm_file *file_priv); | |
1208 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1209 | struct drm_file *file_priv); | |
1210 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1211 | struct drm_file *file_priv); | |
1212 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1213 | struct drm_file *file_priv); | |
5a125c3c EA |
1214 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1215 | struct drm_file *file_priv); | |
673a394b | 1216 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1217 | int i915_gem_init_object(struct drm_gem_object *obj); |
db53a302 | 1218 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
88241785 CW |
1219 | uint32_t invalidate_domains, |
1220 | uint32_t flush_domains); | |
05394f39 CW |
1221 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1222 | size_t size); | |
673a394b | 1223 | void i915_gem_free_object(struct drm_gem_object *obj); |
2021746e CW |
1224 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1225 | uint32_t alignment, | |
1226 | bool map_and_fenceable); | |
05394f39 | 1227 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1228 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 1229 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1230 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1231 | |
54cf91dc | 1232 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
ce453d81 | 1233 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
2911a35b BW |
1234 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1235 | struct intel_ring_buffer *to); | |
54cf91dc | 1236 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1237 | struct intel_ring_buffer *ring, |
1238 | u32 seqno); | |
54cf91dc | 1239 | |
ff72145b DA |
1240 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1241 | struct drm_device *dev, | |
1242 | struct drm_mode_create_dumb *args); | |
1243 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1244 | uint32_t handle, uint64_t *offset); | |
1245 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1246 | uint32_t handle); |
f787a5f5 CW |
1247 | /** |
1248 | * Returns true if seq1 is later than seq2. | |
1249 | */ | |
1250 | static inline bool | |
1251 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1252 | { | |
1253 | return (int32_t)(seq1 - seq2) >= 0; | |
1254 | } | |
1255 | ||
53d227f2 | 1256 | u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); |
54cf91dc | 1257 | |
06d98131 | 1258 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 1259 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1260 | |
9a5a53b3 | 1261 | static inline bool |
1690e1eb CW |
1262 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
1263 | { | |
1264 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1265 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1266 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
1267 | return true; |
1268 | } else | |
1269 | return false; | |
1690e1eb CW |
1270 | } |
1271 | ||
1272 | static inline void | |
1273 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1274 | { | |
1275 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1276 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1277 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1278 | } | |
1279 | } | |
1280 | ||
b09a1fec | 1281 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 CW |
1282 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
1283 | ||
069efc1d | 1284 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1285 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1286 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1287 | uint32_t read_domains, | |
1288 | uint32_t write_domain); | |
a8198eea | 1289 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
f691e2f4 DV |
1290 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
1291 | void i915_gem_init_swizzling(struct drm_device *dev); | |
e21af88d | 1292 | void i915_gem_init_ppgtt(struct drm_device *dev); |
79e53945 | 1293 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b93f9cf1 | 1294 | int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire); |
2021746e | 1295 | int __must_check i915_gem_idle(struct drm_device *dev); |
db53a302 CW |
1296 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1297 | struct drm_file *file, | |
1298 | struct drm_i915_gem_request *request); | |
1299 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, | |
b93f9cf1 BW |
1300 | uint32_t seqno, |
1301 | bool do_retire); | |
de151cf6 | 1302 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1303 | int __must_check |
1304 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1305 | bool write); | |
1306 | int __must_check | |
dabdfe02 CW |
1307 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1308 | int __must_check | |
2da3b9b9 CW |
1309 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1310 | u32 alignment, | |
2021746e | 1311 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1312 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1313 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1314 | int id, |
1315 | int align); | |
71acb5eb | 1316 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1317 | struct drm_i915_gem_object *obj); |
71acb5eb | 1318 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1319 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1320 | |
467cffba | 1321 | uint32_t |
e28f8711 CW |
1322 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1323 | uint32_t size, | |
1324 | int tiling_mode); | |
467cffba | 1325 | |
e4ffd173 CW |
1326 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1327 | enum i915_cache_level cache_level); | |
1328 | ||
76aaf220 | 1329 | /* i915_gem_gtt.c */ |
1d2a314c DV |
1330 | int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); |
1331 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); | |
7bddb01f DV |
1332 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
1333 | struct drm_i915_gem_object *obj, | |
1334 | enum i915_cache_level cache_level); | |
1335 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
1336 | struct drm_i915_gem_object *obj); | |
1d2a314c | 1337 | |
76aaf220 | 1338 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
1339 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1340 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 1341 | enum i915_cache_level cache_level); |
05394f39 | 1342 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 1343 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
644ec02b DV |
1344 | void i915_gem_init_global_gtt(struct drm_device *dev, |
1345 | unsigned long start, | |
1346 | unsigned long mappable_end, | |
1347 | unsigned long end); | |
76aaf220 | 1348 | |
b47eb4a2 | 1349 | /* i915_gem_evict.c */ |
2021746e CW |
1350 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1351 | unsigned alignment, bool mappable); | |
1352 | int __must_check i915_gem_evict_everything(struct drm_device *dev, | |
1353 | bool purgeable_only); | |
1354 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, | |
1355 | bool purgeable_only); | |
b47eb4a2 | 1356 | |
673a394b EA |
1357 | /* i915_gem_tiling.c */ |
1358 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
05394f39 CW |
1359 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1360 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1361 | |
1362 | /* i915_gem_debug.c */ | |
05394f39 | 1363 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1364 | const char *where, uint32_t mark); |
23bc5982 CW |
1365 | #if WATCH_LISTS |
1366 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1367 | #else |
23bc5982 | 1368 | #define i915_verify_lists(dev) 0 |
673a394b | 1369 | #endif |
05394f39 CW |
1370 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1371 | int handle); | |
1372 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1373 | const char *where, uint32_t mark); |
1da177e4 | 1374 | |
2017263e | 1375 | /* i915_debugfs.c */ |
27c202ad BG |
1376 | int i915_debugfs_init(struct drm_minor *minor); |
1377 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1378 | |
317c35d1 JB |
1379 | /* i915_suspend.c */ |
1380 | extern int i915_save_state(struct drm_device *dev); | |
1381 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1382 | |
1383 | /* i915_suspend.c */ | |
1384 | extern int i915_save_state(struct drm_device *dev); | |
1385 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1386 | |
0136db58 BW |
1387 | /* i915_sysfs.c */ |
1388 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
1389 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
1390 | ||
f899fc64 CW |
1391 | /* intel_i2c.c */ |
1392 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1393 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
3bd7d909 DK |
1394 | extern inline bool intel_gmbus_is_port_valid(unsigned port) |
1395 | { | |
2ed06c93 | 1396 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
1397 | } |
1398 | ||
1399 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
1400 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
1401 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1402 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1403 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1404 | { | |
1405 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1406 | } | |
f899fc64 CW |
1407 | extern void intel_i2c_reset(struct drm_device *dev); |
1408 | ||
3b617967 | 1409 | /* intel_opregion.c */ |
44834a67 CW |
1410 | extern int intel_opregion_setup(struct drm_device *dev); |
1411 | #ifdef CONFIG_ACPI | |
1412 | extern void intel_opregion_init(struct drm_device *dev); | |
1413 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1414 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1415 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1416 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1417 | #else |
44834a67 CW |
1418 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1419 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1420 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1421 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1422 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1423 | #endif |
8ee1c3db | 1424 | |
723bfd70 JB |
1425 | /* intel_acpi.c */ |
1426 | #ifdef CONFIG_ACPI | |
1427 | extern void intel_register_dsm_handler(void); | |
1428 | extern void intel_unregister_dsm_handler(void); | |
1429 | #else | |
1430 | static inline void intel_register_dsm_handler(void) { return; } | |
1431 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1432 | #endif /* CONFIG_ACPI */ | |
1433 | ||
79e53945 | 1434 | /* modesetting */ |
f817586c | 1435 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 1436 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 1437 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1438 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1439 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
ee5382ae | 1440 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1441 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1442 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
9fb526db | 1443 | extern void ironlake_init_pch_refclk(struct drm_device *dev); |
d5bb081b | 1444 | extern void ironlake_enable_rc6(struct drm_device *dev); |
3b8d8d91 | 1445 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0206e353 AJ |
1446 | extern void intel_detect_pch(struct drm_device *dev); |
1447 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 1448 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 1449 | |
2911a35b | 1450 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
8d715f00 KP |
1451 | extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1452 | extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); | |
1453 | extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
1454 | extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); | |
1455 | ||
575155a9 JB |
1456 | extern void vlv_force_wake_get(struct drm_i915_private *dev_priv); |
1457 | extern void vlv_force_wake_put(struct drm_i915_private *dev_priv); | |
1458 | ||
6ef3d427 | 1459 | /* overlay */ |
3bd3c932 | 1460 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1461 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1462 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1463 | |
1464 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1465 | extern void intel_display_print_error_state(struct seq_file *m, | |
1466 | struct drm_device *dev, | |
1467 | struct intel_display_error_state *error); | |
3bd3c932 | 1468 | #endif |
6ef3d427 | 1469 | |
1ec14ad3 CW |
1470 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1471 | ||
1472 | #define BEGIN_LP_RING(n) \ | |
1473 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
1474 | ||
1475 | #define OUT_RING(x) \ | |
1476 | intel_ring_emit(LP_RING(dev_priv), x) | |
1477 | ||
1478 | #define ADVANCE_LP_RING() \ | |
1479 | intel_ring_advance(LP_RING(dev_priv)) | |
1480 | ||
546b0974 EA |
1481 | /** |
1482 | * Lock test for when it's just for synchronization of ring access. | |
1483 | * | |
1484 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1485 | * has access to the ring. | |
1486 | */ | |
05394f39 | 1487 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1ec14ad3 | 1488 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
05394f39 | 1489 | LOCK_TEST_WITH_RETURN(dev, file); \ |
546b0974 EA |
1490 | } while (0) |
1491 | ||
b7287d80 BW |
1492 | /* On SNB platform, before reading ring registers forcewake bit |
1493 | * must be set to prevent GT core from power down and stale values being | |
1494 | * returned. | |
1495 | */ | |
fcca7926 BW |
1496 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1497 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
67a3744f | 1498 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
b7287d80 | 1499 | |
5f75377d | 1500 | #define __i915_read(x, y) \ |
f7000883 | 1501 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1502 | |
5f75377d KP |
1503 | __i915_read(8, b) |
1504 | __i915_read(16, w) | |
1505 | __i915_read(32, l) | |
1506 | __i915_read(64, q) | |
1507 | #undef __i915_read | |
1508 | ||
1509 | #define __i915_write(x, y) \ | |
f7000883 AK |
1510 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1511 | ||
5f75377d KP |
1512 | __i915_write(8, b) |
1513 | __i915_write(16, w) | |
1514 | __i915_write(32, l) | |
1515 | __i915_write(64, q) | |
1516 | #undef __i915_write | |
1517 | ||
1518 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1519 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1520 | ||
1521 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1522 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1523 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1524 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1525 | ||
1526 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1527 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1528 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1529 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1530 | |
1531 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1532 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1533 | |
1534 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1535 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1536 | ||
ba4f01a3 | 1537 | |
1da177e4 | 1538 | #endif |