Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
0ade6386 | 38 | #include <drm/intel-gtt.h> |
585fb111 | 39 | |
1da177e4 LT |
40 | /* General customization: |
41 | */ | |
42 | ||
43 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
44 | ||
45 | #define DRIVER_NAME "i915" | |
46 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 47 | #define DRIVER_DATE "20080730" |
1da177e4 | 48 | |
317c35d1 JB |
49 | enum pipe { |
50 | PIPE_A = 0, | |
51 | PIPE_B, | |
9db4a9c7 JB |
52 | PIPE_C, |
53 | I915_MAX_PIPES | |
317c35d1 | 54 | }; |
9db4a9c7 | 55 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 56 | |
80824003 JB |
57 | enum plane { |
58 | PLANE_A = 0, | |
59 | PLANE_B, | |
9db4a9c7 | 60 | PLANE_C, |
80824003 | 61 | }; |
9db4a9c7 | 62 | #define plane_name(p) ((p) + 'A') |
52440211 | 63 | |
62fdfeaf EA |
64 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
65 | ||
9db4a9c7 JB |
66 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
67 | ||
1da177e4 LT |
68 | /* Interface history: |
69 | * | |
70 | * 1.1: Original. | |
0d6aa60b DA |
71 | * 1.2: Add Power Management |
72 | * 1.3: Add vblank support | |
de227f5f | 73 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 74 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
75 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
76 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
77 | */ |
78 | #define DRIVER_MAJOR 1 | |
2228ed67 | 79 | #define DRIVER_MINOR 6 |
1da177e4 LT |
80 | #define DRIVER_PATCHLEVEL 0 |
81 | ||
673a394b | 82 | #define WATCH_COHERENCY 0 |
23bc5982 | 83 | #define WATCH_LISTS 0 |
673a394b | 84 | |
71acb5eb DA |
85 | #define I915_GEM_PHYS_CURSOR_0 1 |
86 | #define I915_GEM_PHYS_CURSOR_1 2 | |
87 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
88 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
89 | ||
90 | struct drm_i915_gem_phys_object { | |
91 | int id; | |
92 | struct page **page_list; | |
93 | drm_dma_handle_t *handle; | |
05394f39 | 94 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
95 | }; |
96 | ||
1da177e4 LT |
97 | struct mem_block { |
98 | struct mem_block *next; | |
99 | struct mem_block *prev; | |
100 | int start; | |
101 | int size; | |
6c340eac | 102 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
103 | }; |
104 | ||
0a3e67a4 JB |
105 | struct opregion_header; |
106 | struct opregion_acpi; | |
107 | struct opregion_swsci; | |
108 | struct opregion_asle; | |
109 | ||
8ee1c3db MG |
110 | struct intel_opregion { |
111 | struct opregion_header *header; | |
112 | struct opregion_acpi *acpi; | |
113 | struct opregion_swsci *swsci; | |
114 | struct opregion_asle *asle; | |
44834a67 | 115 | void *vbt; |
01fe9dbd | 116 | u32 __iomem *lid_state; |
8ee1c3db | 117 | }; |
44834a67 | 118 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 119 | |
6ef3d427 CW |
120 | struct intel_overlay; |
121 | struct intel_overlay_error_state; | |
122 | ||
7c1c2871 DA |
123 | struct drm_i915_master_private { |
124 | drm_local_map_t *sarea; | |
125 | struct _drm_i915_sarea *sarea_priv; | |
126 | }; | |
de151cf6 JB |
127 | #define I915_FENCE_REG_NONE -1 |
128 | ||
129 | struct drm_i915_fence_reg { | |
007cc8ac | 130 | struct list_head lru_list; |
caea7476 | 131 | struct drm_i915_gem_object *obj; |
d9e86c0e | 132 | uint32_t setup_seqno; |
de151cf6 | 133 | }; |
7c1c2871 | 134 | |
9b9d172d | 135 | struct sdvo_device_mapping { |
e957d772 | 136 | u8 initialized; |
9b9d172d | 137 | u8 dvo_port; |
138 | u8 slave_addr; | |
139 | u8 dvo_wiring; | |
e957d772 CW |
140 | u8 i2c_pin; |
141 | u8 i2c_speed; | |
b1083333 | 142 | u8 ddc_pin; |
9b9d172d | 143 | }; |
144 | ||
c4a1d9e4 CW |
145 | struct intel_display_error_state; |
146 | ||
63eeaf38 JB |
147 | struct drm_i915_error_state { |
148 | u32 eir; | |
149 | u32 pgtbl_er; | |
9db4a9c7 | 150 | u32 pipestat[I915_MAX_PIPES]; |
63eeaf38 JB |
151 | u32 ipeir; |
152 | u32 ipehr; | |
153 | u32 instdone; | |
154 | u32 acthd; | |
1d8f38f4 CW |
155 | u32 error; /* gen6+ */ |
156 | u32 bcs_acthd; /* gen6+ blt engine */ | |
157 | u32 bcs_ipehr; | |
158 | u32 bcs_ipeir; | |
159 | u32 bcs_instdone; | |
160 | u32 bcs_seqno; | |
add354dd CW |
161 | u32 vcs_acthd; /* gen6+ bsd engine */ |
162 | u32 vcs_ipehr; | |
163 | u32 vcs_ipeir; | |
164 | u32 vcs_instdone; | |
165 | u32 vcs_seqno; | |
63eeaf38 JB |
166 | u32 instpm; |
167 | u32 instps; | |
168 | u32 instdone1; | |
169 | u32 seqno; | |
9df30794 | 170 | u64 bbaddr; |
748ebc60 | 171 | u64 fence[16]; |
63eeaf38 | 172 | struct timeval time; |
9df30794 CW |
173 | struct drm_i915_error_object { |
174 | int page_count; | |
175 | u32 gtt_offset; | |
176 | u32 *pages[0]; | |
e2f973d5 | 177 | } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; |
9df30794 | 178 | struct drm_i915_error_buffer { |
a779e5ab | 179 | u32 size; |
9df30794 CW |
180 | u32 name; |
181 | u32 seqno; | |
182 | u32 gtt_offset; | |
183 | u32 read_domains; | |
184 | u32 write_domain; | |
a779e5ab | 185 | s32 fence_reg:5; |
9df30794 CW |
186 | s32 pinned:2; |
187 | u32 tiling:2; | |
188 | u32 dirty:1; | |
189 | u32 purgeable:1; | |
e5c65260 | 190 | u32 ring:4; |
93dfb40c | 191 | u32 cache_level:2; |
c724e8a9 CW |
192 | } *active_bo, *pinned_bo; |
193 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 194 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 195 | struct intel_display_error_state *display; |
63eeaf38 JB |
196 | }; |
197 | ||
e70236a8 JB |
198 | struct drm_i915_display_funcs { |
199 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 200 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
201 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
202 | void (*disable_fbc)(struct drm_device *dev); | |
203 | int (*get_display_clock_speed)(struct drm_device *dev); | |
204 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 205 | void (*update_wm)(struct drm_device *dev); |
f564048e EA |
206 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
207 | struct drm_display_mode *mode, | |
208 | struct drm_display_mode *adjusted_mode, | |
209 | int x, int y, | |
210 | struct drm_framebuffer *old_fb); | |
211 | ||
e70236a8 JB |
212 | /* clock updates for mode set */ |
213 | /* cursor updates */ | |
214 | /* render clock increase/decrease */ | |
215 | /* display clock increase/decrease */ | |
216 | /* pll clock increase/decrease */ | |
217 | /* clock gating init */ | |
218 | }; | |
219 | ||
cfdf1fa2 | 220 | struct intel_device_info { |
c96c3a8c | 221 | u8 gen; |
cfdf1fa2 | 222 | u8 is_mobile : 1; |
5ce8ba7c | 223 | u8 is_i85x : 1; |
cfdf1fa2 | 224 | u8 is_i915g : 1; |
cfdf1fa2 | 225 | u8 is_i945gm : 1; |
cfdf1fa2 KH |
226 | u8 is_g33 : 1; |
227 | u8 need_gfx_hws : 1; | |
228 | u8 is_g4x : 1; | |
229 | u8 is_pineview : 1; | |
534843da CW |
230 | u8 is_broadwater : 1; |
231 | u8 is_crestline : 1; | |
cfdf1fa2 | 232 | u8 has_fbc : 1; |
cfdf1fa2 KH |
233 | u8 has_pipe_cxsr : 1; |
234 | u8 has_hotplug : 1; | |
b295d1b6 | 235 | u8 cursor_needs_physical : 1; |
31578148 CW |
236 | u8 has_overlay : 1; |
237 | u8 overlay_needs_physical : 1; | |
a6c45cf0 | 238 | u8 supports_tv : 1; |
92f49d9c | 239 | u8 has_bsd_ring : 1; |
549f7365 | 240 | u8 has_blt_ring : 1; |
cfdf1fa2 KH |
241 | }; |
242 | ||
b5e50c3f | 243 | enum no_fbc_reason { |
bed4a673 | 244 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
245 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
246 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
247 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
248 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
249 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 250 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
b5e50c3f JB |
251 | }; |
252 | ||
3bad0781 ZW |
253 | enum intel_pch { |
254 | PCH_IBX, /* Ibexpeak PCH */ | |
255 | PCH_CPT, /* Cougarpoint PCH */ | |
256 | }; | |
257 | ||
b690e96c JB |
258 | #define QUIRK_PIPEA_FORCE (1<<0) |
259 | ||
8be48d92 | 260 | struct intel_fbdev; |
38651674 | 261 | |
1da177e4 | 262 | typedef struct drm_i915_private { |
673a394b EA |
263 | struct drm_device *dev; |
264 | ||
cfdf1fa2 KH |
265 | const struct intel_device_info *info; |
266 | ||
ac5c4e76 | 267 | int has_gem; |
72bfa19c | 268 | int relative_constants_mode; |
ac5c4e76 | 269 | |
3043c60c | 270 | void __iomem *regs; |
1da177e4 | 271 | |
f899fc64 CW |
272 | struct intel_gmbus { |
273 | struct i2c_adapter adapter; | |
e957d772 CW |
274 | struct i2c_adapter *force_bit; |
275 | u32 reg0; | |
f899fc64 CW |
276 | } *gmbus; |
277 | ||
ec2a4c3f | 278 | struct pci_dev *bridge_dev; |
1ec14ad3 | 279 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
6f392d54 | 280 | uint32_t next_seqno; |
1da177e4 | 281 | |
9c8da5eb | 282 | drm_dma_handle_t *status_page_dmah; |
0a3e67a4 | 283 | uint32_t counter; |
dc7a9319 | 284 | drm_local_map_t hws_map; |
05394f39 CW |
285 | struct drm_i915_gem_object *pwrctx; |
286 | struct drm_i915_gem_object *renderctx; | |
1da177e4 | 287 | |
d7658989 JB |
288 | struct resource mch_res; |
289 | ||
a6b54f3f | 290 | unsigned int cpp; |
1da177e4 LT |
291 | int back_offset; |
292 | int front_offset; | |
293 | int current_page; | |
294 | int page_flipping; | |
1da177e4 | 295 | |
1da177e4 | 296 | atomic_t irq_received; |
1ec14ad3 CW |
297 | |
298 | /* protects the irq masks */ | |
299 | spinlock_t irq_lock; | |
ed4cb414 | 300 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
7c463586 | 301 | u32 pipestat[2]; |
1ec14ad3 CW |
302 | u32 irq_mask; |
303 | u32 gt_irq_mask; | |
304 | u32 pch_irq_mask; | |
1da177e4 | 305 | |
5ca58282 JB |
306 | u32 hotplug_supported_mask; |
307 | struct work_struct hotplug_work; | |
308 | ||
1da177e4 LT |
309 | int tex_lru_log_granularity; |
310 | int allow_batchbuffer; | |
311 | struct mem_block *agp_heap; | |
0d6aa60b | 312 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 313 | int vblank_pipe; |
a3524f1b | 314 | int num_pipe; |
a6b54f3f | 315 | |
f65d9421 | 316 | /* For hangcheck timer */ |
576ae4b8 | 317 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
f65d9421 BG |
318 | struct timer_list hangcheck_timer; |
319 | int hangcheck_count; | |
320 | uint32_t last_acthd; | |
cbb465e7 CW |
321 | uint32_t last_instdone; |
322 | uint32_t last_instdone1; | |
f65d9421 | 323 | |
80824003 JB |
324 | unsigned long cfb_size; |
325 | unsigned long cfb_pitch; | |
bed4a673 | 326 | unsigned long cfb_offset; |
80824003 JB |
327 | int cfb_fence; |
328 | int cfb_plane; | |
bed4a673 | 329 | int cfb_y; |
80824003 | 330 | |
8ee1c3db MG |
331 | struct intel_opregion opregion; |
332 | ||
02e792fb DV |
333 | /* overlay */ |
334 | struct intel_overlay *overlay; | |
335 | ||
79e53945 | 336 | /* LVDS info */ |
a9573556 | 337 | int backlight_level; /* restore backlight to this value */ |
47356eb6 | 338 | bool backlight_enabled; |
79e53945 | 339 | struct drm_display_mode *panel_fixed_mode; |
88631706 ML |
340 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
341 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
342 | |
343 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
344 | unsigned int int_tv_support:1; |
345 | unsigned int lvds_dither:1; | |
346 | unsigned int lvds_vbt:1; | |
347 | unsigned int int_crt_support:1; | |
43565a06 KH |
348 | unsigned int lvds_use_ssc:1; |
349 | int lvds_ssc_freq; | |
5ceb0f9b | 350 | struct { |
9f0e7ff4 JB |
351 | int rate; |
352 | int lanes; | |
353 | int preemphasis; | |
354 | int vswing; | |
355 | ||
356 | bool initialized; | |
357 | bool support; | |
358 | int bpp; | |
359 | struct edp_power_seq pps; | |
5ceb0f9b | 360 | } edp; |
89667383 | 361 | bool no_aux_handshake; |
79e53945 | 362 | |
c1c7af60 JB |
363 | struct notifier_block lid_notifier; |
364 | ||
f899fc64 | 365 | int crt_ddc_pin; |
de151cf6 JB |
366 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
367 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
368 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
369 | ||
95534263 | 370 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 371 | |
63eeaf38 JB |
372 | spinlock_t error_lock; |
373 | struct drm_i915_error_state *first_error; | |
8a905236 | 374 | struct work_struct error_work; |
30dbf0c0 | 375 | struct completion error_completion; |
9c9fe1f8 | 376 | struct workqueue_struct *wq; |
63eeaf38 | 377 | |
e70236a8 JB |
378 | /* Display functions */ |
379 | struct drm_i915_display_funcs display; | |
380 | ||
3bad0781 ZW |
381 | /* PCH chipset type */ |
382 | enum intel_pch pch_type; | |
383 | ||
b690e96c JB |
384 | unsigned long quirks; |
385 | ||
ba8bbcf6 | 386 | /* Register state */ |
c9354c85 | 387 | bool modeset_on_lid; |
ba8bbcf6 JB |
388 | u8 saveLBB; |
389 | u32 saveDSPACNTR; | |
390 | u32 saveDSPBCNTR; | |
e948e994 | 391 | u32 saveDSPARB; |
968b503e | 392 | u32 saveHWS; |
ba8bbcf6 JB |
393 | u32 savePIPEACONF; |
394 | u32 savePIPEBCONF; | |
395 | u32 savePIPEASRC; | |
396 | u32 savePIPEBSRC; | |
397 | u32 saveFPA0; | |
398 | u32 saveFPA1; | |
399 | u32 saveDPLL_A; | |
400 | u32 saveDPLL_A_MD; | |
401 | u32 saveHTOTAL_A; | |
402 | u32 saveHBLANK_A; | |
403 | u32 saveHSYNC_A; | |
404 | u32 saveVTOTAL_A; | |
405 | u32 saveVBLANK_A; | |
406 | u32 saveVSYNC_A; | |
407 | u32 saveBCLRPAT_A; | |
5586c8bc | 408 | u32 saveTRANSACONF; |
42048781 ZW |
409 | u32 saveTRANS_HTOTAL_A; |
410 | u32 saveTRANS_HBLANK_A; | |
411 | u32 saveTRANS_HSYNC_A; | |
412 | u32 saveTRANS_VTOTAL_A; | |
413 | u32 saveTRANS_VBLANK_A; | |
414 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 415 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
416 | u32 saveDSPASTRIDE; |
417 | u32 saveDSPASIZE; | |
418 | u32 saveDSPAPOS; | |
585fb111 | 419 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
420 | u32 saveDSPASURF; |
421 | u32 saveDSPATILEOFF; | |
422 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 423 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
424 | u32 saveBLC_PWM_CTL; |
425 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
426 | u32 saveBLC_CPU_PWM_CTL; |
427 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
428 | u32 saveFPB0; |
429 | u32 saveFPB1; | |
430 | u32 saveDPLL_B; | |
431 | u32 saveDPLL_B_MD; | |
432 | u32 saveHTOTAL_B; | |
433 | u32 saveHBLANK_B; | |
434 | u32 saveHSYNC_B; | |
435 | u32 saveVTOTAL_B; | |
436 | u32 saveVBLANK_B; | |
437 | u32 saveVSYNC_B; | |
438 | u32 saveBCLRPAT_B; | |
5586c8bc | 439 | u32 saveTRANSBCONF; |
42048781 ZW |
440 | u32 saveTRANS_HTOTAL_B; |
441 | u32 saveTRANS_HBLANK_B; | |
442 | u32 saveTRANS_HSYNC_B; | |
443 | u32 saveTRANS_VTOTAL_B; | |
444 | u32 saveTRANS_VBLANK_B; | |
445 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 446 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
447 | u32 saveDSPBSTRIDE; |
448 | u32 saveDSPBSIZE; | |
449 | u32 saveDSPBPOS; | |
585fb111 | 450 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
451 | u32 saveDSPBSURF; |
452 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
453 | u32 saveVGA0; |
454 | u32 saveVGA1; | |
455 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
456 | u32 saveVGACNTRL; |
457 | u32 saveADPA; | |
458 | u32 saveLVDS; | |
585fb111 JB |
459 | u32 savePP_ON_DELAYS; |
460 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
461 | u32 saveDVOA; |
462 | u32 saveDVOB; | |
463 | u32 saveDVOC; | |
464 | u32 savePP_ON; | |
465 | u32 savePP_OFF; | |
466 | u32 savePP_CONTROL; | |
585fb111 | 467 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
468 | u32 savePFIT_CONTROL; |
469 | u32 save_palette_a[256]; | |
470 | u32 save_palette_b[256]; | |
06027f91 | 471 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
472 | u32 saveFBC_CFB_BASE; |
473 | u32 saveFBC_LL_BASE; | |
474 | u32 saveFBC_CONTROL; | |
475 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
476 | u32 saveIER; |
477 | u32 saveIIR; | |
478 | u32 saveIMR; | |
42048781 ZW |
479 | u32 saveDEIER; |
480 | u32 saveDEIMR; | |
481 | u32 saveGTIER; | |
482 | u32 saveGTIMR; | |
483 | u32 saveFDI_RXA_IMR; | |
484 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 485 | u32 saveCACHE_MODE_0; |
1f84e550 | 486 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
487 | u32 saveSWF0[16]; |
488 | u32 saveSWF1[16]; | |
489 | u32 saveSWF2[3]; | |
490 | u8 saveMSR; | |
491 | u8 saveSR[8]; | |
123f794f | 492 | u8 saveGR[25]; |
ba8bbcf6 | 493 | u8 saveAR_INDEX; |
a59e122a | 494 | u8 saveAR[21]; |
ba8bbcf6 | 495 | u8 saveDACMASK; |
a59e122a | 496 | u8 saveCR[37]; |
79f11c19 | 497 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
498 | u32 saveCURACNTR; |
499 | u32 saveCURAPOS; | |
500 | u32 saveCURABASE; | |
501 | u32 saveCURBCNTR; | |
502 | u32 saveCURBPOS; | |
503 | u32 saveCURBBASE; | |
504 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
505 | u32 saveDP_B; |
506 | u32 saveDP_C; | |
507 | u32 saveDP_D; | |
508 | u32 savePIPEA_GMCH_DATA_M; | |
509 | u32 savePIPEB_GMCH_DATA_M; | |
510 | u32 savePIPEA_GMCH_DATA_N; | |
511 | u32 savePIPEB_GMCH_DATA_N; | |
512 | u32 savePIPEA_DP_LINK_M; | |
513 | u32 savePIPEB_DP_LINK_M; | |
514 | u32 savePIPEA_DP_LINK_N; | |
515 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
516 | u32 saveFDI_RXA_CTL; |
517 | u32 saveFDI_TXA_CTL; | |
518 | u32 saveFDI_RXB_CTL; | |
519 | u32 saveFDI_TXB_CTL; | |
520 | u32 savePFA_CTL_1; | |
521 | u32 savePFB_CTL_1; | |
522 | u32 savePFA_WIN_SZ; | |
523 | u32 savePFB_WIN_SZ; | |
524 | u32 savePFA_WIN_POS; | |
525 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
526 | u32 savePCH_DREF_CONTROL; |
527 | u32 saveDISP_ARB_CTL; | |
528 | u32 savePIPEA_DATA_M1; | |
529 | u32 savePIPEA_DATA_N1; | |
530 | u32 savePIPEA_LINK_M1; | |
531 | u32 savePIPEA_LINK_N1; | |
532 | u32 savePIPEB_DATA_M1; | |
533 | u32 savePIPEB_DATA_N1; | |
534 | u32 savePIPEB_LINK_M1; | |
535 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 536 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
537 | |
538 | struct { | |
19966754 | 539 | /** Bridge to intel-gtt-ko */ |
c64f7ba5 | 540 | const struct intel_gtt *gtt; |
19966754 | 541 | /** Memory allocator for GTT stolen memory */ |
fe669bf8 | 542 | struct drm_mm stolen; |
19966754 | 543 | /** Memory allocator for GTT */ |
673a394b | 544 | struct drm_mm gtt_space; |
93a37f20 DV |
545 | /** List of all objects in gtt_space. Used to restore gtt |
546 | * mappings on resume */ | |
547 | struct list_head gtt_list; | |
bee4a186 CW |
548 | |
549 | /** Usable portion of the GTT for GEM */ | |
550 | unsigned long gtt_start; | |
a6e0aa42 | 551 | unsigned long gtt_mappable_end; |
bee4a186 | 552 | unsigned long gtt_end; |
673a394b | 553 | |
0839ccb8 | 554 | struct io_mapping *gtt_mapping; |
ab657db1 | 555 | int gtt_mtrr; |
0839ccb8 | 556 | |
17250b71 | 557 | struct shrinker inactive_shrinker; |
31169714 | 558 | |
69dc4987 CW |
559 | /** |
560 | * List of objects currently involved in rendering. | |
561 | * | |
562 | * Includes buffers having the contents of their GPU caches | |
563 | * flushed, not necessarily primitives. last_rendering_seqno | |
564 | * represents when the rendering involved will be completed. | |
565 | * | |
566 | * A reference is held on the buffer while on this list. | |
567 | */ | |
568 | struct list_head active_list; | |
569 | ||
673a394b EA |
570 | /** |
571 | * List of objects which are not in the ringbuffer but which | |
572 | * still have a write_domain which needs to be flushed before | |
573 | * unbinding. | |
574 | * | |
ce44b0ea EA |
575 | * last_rendering_seqno is 0 while an object is in this list. |
576 | * | |
673a394b EA |
577 | * A reference is held on the buffer while on this list. |
578 | */ | |
579 | struct list_head flushing_list; | |
580 | ||
581 | /** | |
582 | * LRU list of objects which are not in the ringbuffer and | |
583 | * are ready to unbind, but are still in the GTT. | |
584 | * | |
ce44b0ea EA |
585 | * last_rendering_seqno is 0 while an object is in this list. |
586 | * | |
673a394b EA |
587 | * A reference is not held on the buffer while on this list, |
588 | * as merely being GTT-bound shouldn't prevent its being | |
589 | * freed, and we'll pull it off the list in the free path. | |
590 | */ | |
591 | struct list_head inactive_list; | |
592 | ||
f13d3f73 CW |
593 | /** |
594 | * LRU list of objects which are not in the ringbuffer but | |
595 | * are still pinned in the GTT. | |
596 | */ | |
597 | struct list_head pinned_list; | |
598 | ||
a09ba7fa EA |
599 | /** LRU list of objects with fence regs on them. */ |
600 | struct list_head fence_list; | |
601 | ||
be72615b CW |
602 | /** |
603 | * List of objects currently pending being freed. | |
604 | * | |
605 | * These objects are no longer in use, but due to a signal | |
606 | * we were prevented from freeing them at the appointed time. | |
607 | */ | |
608 | struct list_head deferred_free_list; | |
609 | ||
673a394b EA |
610 | /** |
611 | * We leave the user IRQ off as much as possible, | |
612 | * but this means that requests will finish and never | |
613 | * be retired once the system goes idle. Set a timer to | |
614 | * fire periodically while the ring is running. When it | |
615 | * fires, go retire requests. | |
616 | */ | |
617 | struct delayed_work retire_work; | |
618 | ||
ce453d81 CW |
619 | /** |
620 | * Are we in a non-interruptible section of code like | |
621 | * modesetting? | |
622 | */ | |
623 | bool interruptible; | |
624 | ||
673a394b EA |
625 | /** |
626 | * Flag if the X Server, and thus DRM, is not currently in | |
627 | * control of the device. | |
628 | * | |
629 | * This is set between LeaveVT and EnterVT. It needs to be | |
630 | * replaced with a semaphore. It also needs to be | |
631 | * transitioned away from for kernel modesetting. | |
632 | */ | |
633 | int suspended; | |
634 | ||
635 | /** | |
636 | * Flag if the hardware appears to be wedged. | |
637 | * | |
638 | * This is set when attempts to idle the device timeout. | |
25985edc | 639 | * It prevents command submission from occurring and makes |
673a394b EA |
640 | * every pending request fail |
641 | */ | |
ba1234d1 | 642 | atomic_t wedged; |
673a394b EA |
643 | |
644 | /** Bit 6 swizzling required for X tiling */ | |
645 | uint32_t bit_6_swizzle_x; | |
646 | /** Bit 6 swizzling required for Y tiling */ | |
647 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
648 | |
649 | /* storage for physical objects */ | |
650 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 651 | |
73aa808f | 652 | /* accounting, useful for userland debugging */ |
73aa808f | 653 | size_t gtt_total; |
6299f992 CW |
654 | size_t mappable_gtt_total; |
655 | size_t object_memory; | |
73aa808f | 656 | u32 object_count; |
673a394b | 657 | } mm; |
9b9d172d | 658 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
659 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
660 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
661 | /* Panel fitter placement and size for Ironlake+ */ |
662 | u32 pch_pf_pos, pch_pf_size; | |
5d613501 | 663 | int panel_t3, panel_t12; |
652c393a | 664 | |
6b95a207 KH |
665 | struct drm_crtc *plane_to_crtc_mapping[2]; |
666 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
667 | wait_queue_head_t pending_flip_queue; | |
1afe3e9d | 668 | bool flip_pending_is_done; |
6b95a207 | 669 | |
652c393a JB |
670 | /* Reclocking support */ |
671 | bool render_reclock_avail; | |
672 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
673 | /* indicates the reduced downclock for LVDS*/ |
674 | int lvds_downclock; | |
652c393a JB |
675 | struct work_struct idle_work; |
676 | struct timer_list idle_timer; | |
677 | bool busy; | |
678 | u16 orig_clock; | |
6363ee6f ZY |
679 | int child_dev_num; |
680 | struct child_device_config *child_dev; | |
a2565377 | 681 | struct drm_connector *int_lvds_connector; |
f97108d1 | 682 | |
c4804411 | 683 | bool mchbar_need_disable; |
f97108d1 JB |
684 | |
685 | u8 cur_delay; | |
686 | u8 min_delay; | |
687 | u8 max_delay; | |
7648fa99 JB |
688 | u8 fmax; |
689 | u8 fstart; | |
690 | ||
05394f39 CW |
691 | u64 last_count1; |
692 | unsigned long last_time1; | |
693 | u64 last_count2; | |
694 | struct timespec last_time2; | |
695 | unsigned long gfx_power; | |
696 | int c_m; | |
697 | int r_t; | |
698 | u8 corr; | |
7648fa99 | 699 | spinlock_t *mchdev_lock; |
b5e50c3f JB |
700 | |
701 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 702 | |
20bf377e JB |
703 | struct drm_mm_node *compressed_fb; |
704 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 705 | |
ae681d96 CW |
706 | unsigned long last_gpu_reset; |
707 | ||
8be48d92 DA |
708 | /* list of fbdev register on this device */ |
709 | struct intel_fbdev *fbdev; | |
e953fd7b CW |
710 | |
711 | struct drm_property *broadcast_rgb_property; | |
1da177e4 LT |
712 | } drm_i915_private_t; |
713 | ||
93dfb40c CW |
714 | enum i915_cache_level { |
715 | I915_CACHE_NONE, | |
716 | I915_CACHE_LLC, | |
717 | I915_CACHE_LLC_MLC, /* gen6+ */ | |
718 | }; | |
719 | ||
673a394b | 720 | struct drm_i915_gem_object { |
c397b908 | 721 | struct drm_gem_object base; |
673a394b EA |
722 | |
723 | /** Current space allocated to this object in the GTT, if any. */ | |
724 | struct drm_mm_node *gtt_space; | |
93a37f20 | 725 | struct list_head gtt_list; |
673a394b EA |
726 | |
727 | /** This object's place on the active/flushing/inactive lists */ | |
69dc4987 CW |
728 | struct list_head ring_list; |
729 | struct list_head mm_list; | |
99fcb766 DV |
730 | /** This object's place on GPU write list */ |
731 | struct list_head gpu_write_list; | |
432e58ed CW |
732 | /** This object's place in the batchbuffer or on the eviction list */ |
733 | struct list_head exec_list; | |
673a394b EA |
734 | |
735 | /** | |
736 | * This is set if the object is on the active or flushing lists | |
737 | * (has pending rendering), and is not set if it's on inactive (ready | |
738 | * to be unbound). | |
739 | */ | |
778c3544 | 740 | unsigned int active : 1; |
673a394b EA |
741 | |
742 | /** | |
743 | * This is set if the object has been written to since last bound | |
744 | * to the GTT | |
745 | */ | |
778c3544 DV |
746 | unsigned int dirty : 1; |
747 | ||
87ca9c8a CW |
748 | /** |
749 | * This is set if the object has been written to since the last | |
750 | * GPU flush. | |
751 | */ | |
752 | unsigned int pending_gpu_write : 1; | |
753 | ||
778c3544 DV |
754 | /** |
755 | * Fence register bits (if any) for this object. Will be set | |
756 | * as needed when mapped into the GTT. | |
757 | * Protected by dev->struct_mutex. | |
758 | * | |
759 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) | |
760 | */ | |
11824e8c | 761 | signed int fence_reg : 5; |
778c3544 | 762 | |
778c3544 DV |
763 | /** |
764 | * Advice: are the backing pages purgeable? | |
765 | */ | |
766 | unsigned int madv : 2; | |
767 | ||
778c3544 DV |
768 | /** |
769 | * Current tiling mode for the object. | |
770 | */ | |
771 | unsigned int tiling_mode : 2; | |
d9e86c0e | 772 | unsigned int tiling_changed : 1; |
778c3544 DV |
773 | |
774 | /** How many users have pinned this object in GTT space. The following | |
775 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
776 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
777 | * times for the same batchbuffer), and the framebuffer code. When | |
778 | * switching/pageflipping, the framebuffer code has at most two buffers | |
779 | * pinned per crtc. | |
780 | * | |
781 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
782 | * bits with absolutely no headroom. So use 4 bits. */ | |
11824e8c | 783 | unsigned int pin_count : 4; |
778c3544 | 784 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 785 | |
75e9e915 DV |
786 | /** |
787 | * Is the object at the current location in the gtt mappable and | |
788 | * fenceable? Used to avoid costly recalculations. | |
789 | */ | |
790 | unsigned int map_and_fenceable : 1; | |
791 | ||
fb7d516a DV |
792 | /** |
793 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
794 | * mappable by accident). Track pin and fault separate for a more | |
795 | * accurate mappable working set. | |
796 | */ | |
797 | unsigned int fault_mappable : 1; | |
798 | unsigned int pin_mappable : 1; | |
799 | ||
caea7476 CW |
800 | /* |
801 | * Is the GPU currently using a fence to access this buffer, | |
802 | */ | |
803 | unsigned int pending_fenced_gpu_access:1; | |
804 | unsigned int fenced_gpu_access:1; | |
805 | ||
93dfb40c CW |
806 | unsigned int cache_level:2; |
807 | ||
856fa198 | 808 | struct page **pages; |
673a394b | 809 | |
185cbcb3 DV |
810 | /** |
811 | * DMAR support | |
812 | */ | |
813 | struct scatterlist *sg_list; | |
814 | int num_sg; | |
815 | ||
67731b87 CW |
816 | /** |
817 | * Used for performing relocations during execbuffer insertion. | |
818 | */ | |
819 | struct hlist_node exec_node; | |
820 | unsigned long exec_handle; | |
6fe4f140 | 821 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 822 | |
673a394b EA |
823 | /** |
824 | * Current offset of the object in GTT space. | |
825 | * | |
826 | * This is the same as gtt_space->start | |
827 | */ | |
828 | uint32_t gtt_offset; | |
e67b8ce1 | 829 | |
673a394b EA |
830 | /** Breadcrumb of last rendering to the buffer. */ |
831 | uint32_t last_rendering_seqno; | |
caea7476 CW |
832 | struct intel_ring_buffer *ring; |
833 | ||
834 | /** Breadcrumb of last fenced GPU access to the buffer. */ | |
835 | uint32_t last_fenced_seqno; | |
836 | struct intel_ring_buffer *last_fenced_ring; | |
673a394b | 837 | |
778c3544 | 838 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 839 | uint32_t stride; |
673a394b | 840 | |
280b713b | 841 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 842 | unsigned long *bit_17; |
280b713b | 843 | |
ba1eb1d8 | 844 | |
673a394b | 845 | /** |
e47c68e9 EA |
846 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
847 | * flags which individual pages are valid. | |
673a394b EA |
848 | */ |
849 | uint8_t *page_cpu_valid; | |
79e53945 JB |
850 | |
851 | /** User space pin count and filp owning the pin */ | |
852 | uint32_t user_pin_count; | |
853 | struct drm_file *pin_filp; | |
71acb5eb DA |
854 | |
855 | /** for phy allocated objects */ | |
856 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 857 | |
6b95a207 KH |
858 | /** |
859 | * Number of crtcs where this object is currently the fb, but | |
860 | * will be page flipped away on the next vblank. When it | |
861 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
862 | */ | |
863 | atomic_t pending_flip; | |
673a394b EA |
864 | }; |
865 | ||
62b8b215 | 866 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 867 | |
673a394b EA |
868 | /** |
869 | * Request queue structure. | |
870 | * | |
871 | * The request queue allows us to note sequence numbers that have been emitted | |
872 | * and may be associated with active buffers to be retired. | |
873 | * | |
874 | * By keeping this list, we can avoid having to do questionable | |
875 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
876 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
877 | */ | |
878 | struct drm_i915_gem_request { | |
852835f3 ZN |
879 | /** On Which ring this request was generated */ |
880 | struct intel_ring_buffer *ring; | |
881 | ||
673a394b EA |
882 | /** GEM sequence number associated with this request. */ |
883 | uint32_t seqno; | |
884 | ||
885 | /** Time at which this request was emitted, in jiffies. */ | |
886 | unsigned long emitted_jiffies; | |
887 | ||
b962442e | 888 | /** global list entry for this request */ |
673a394b | 889 | struct list_head list; |
b962442e | 890 | |
f787a5f5 | 891 | struct drm_i915_file_private *file_priv; |
b962442e EA |
892 | /** file_priv list entry for this request */ |
893 | struct list_head client_list; | |
673a394b EA |
894 | }; |
895 | ||
896 | struct drm_i915_file_private { | |
897 | struct { | |
1c25595f | 898 | struct spinlock lock; |
b962442e | 899 | struct list_head request_list; |
673a394b EA |
900 | } mm; |
901 | }; | |
902 | ||
79e53945 JB |
903 | enum intel_chip_family { |
904 | CHIP_I8XX = 0x01, | |
905 | CHIP_I9XX = 0x02, | |
906 | CHIP_I915 = 0x04, | |
907 | CHIP_I965 = 0x08, | |
908 | }; | |
909 | ||
cae5852d ZN |
910 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
911 | ||
912 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
913 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
914 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
915 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
916 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
917 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
918 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
919 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
920 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
921 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
922 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
923 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
924 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
925 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
926 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
927 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
928 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
929 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
930 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) | |
931 | ||
932 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) | |
933 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
934 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
935 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
936 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
937 | ||
938 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
939 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
940 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) | |
941 | ||
05394f39 | 942 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
943 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
944 | ||
945 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
946 | * rows, which changed the alignment requirements and fence programming. | |
947 | */ | |
948 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
949 | IS_I915GM(dev))) | |
950 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
951 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
952 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
953 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
954 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
955 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
956 | /* dsparb controlled by hw only */ | |
957 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
958 | ||
959 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
960 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
961 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d ZN |
962 | |
963 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev)) | |
964 | #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev)) | |
965 | ||
966 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
967 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
968 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
969 | ||
05394f39 CW |
970 | #include "i915_trace.h" |
971 | ||
c153f45f | 972 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 973 | extern int i915_max_ioctl; |
79e53945 | 974 | extern unsigned int i915_fbpercrtc; |
fca87409 | 975 | extern int i915_panel_ignore_lid; |
652c393a | 976 | extern unsigned int i915_powersave; |
a1656b90 | 977 | extern unsigned int i915_semaphores; |
33814341 | 978 | extern unsigned int i915_lvds_downclock; |
a7615030 | 979 | extern unsigned int i915_panel_use_ssc; |
5a1e5b6c | 980 | extern int i915_vbt_sdvo_panel_type; |
ac668088 | 981 | extern unsigned int i915_enable_rc6; |
b3a83639 | 982 | |
6a9ee8af DA |
983 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
984 | extern int i915_resume(struct drm_device *dev); | |
1341d655 BG |
985 | extern void i915_save_display(struct drm_device *dev); |
986 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
987 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
988 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
989 | ||
1da177e4 | 990 | /* i915_dma.c */ |
84b1fd10 | 991 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 992 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 993 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 994 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 995 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
996 | extern void i915_driver_preclose(struct drm_device *dev, |
997 | struct drm_file *file_priv); | |
673a394b EA |
998 | extern void i915_driver_postclose(struct drm_device *dev, |
999 | struct drm_file *file_priv); | |
84b1fd10 | 1000 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
1001 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1002 | unsigned long arg); | |
673a394b | 1003 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1004 | struct drm_clip_rect *box, |
1005 | int DR1, int DR4); | |
f803aa55 | 1006 | extern int i915_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
1007 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1008 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1009 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1010 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1011 | ||
af6061af | 1012 | |
1da177e4 | 1013 | /* i915_irq.c */ |
f65d9421 | 1014 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1015 | void i915_handle_error(struct drm_device *dev, bool wedged); |
c153f45f EA |
1016 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
1017 | struct drm_file *file_priv); | |
1018 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
1019 | struct drm_file *file_priv); | |
1da177e4 LT |
1020 | |
1021 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 1022 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 1023 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 1024 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
1025 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1026 | struct drm_file *file_priv); | |
1027 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
1028 | struct drm_file *file_priv); | |
0a3e67a4 JB |
1029 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
1030 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
1031 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 1032 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
1033 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
1034 | struct drm_file *file_priv); | |
1da177e4 | 1035 | |
7c463586 KP |
1036 | void |
1037 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1038 | ||
1039 | void | |
1040 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1041 | ||
01c66889 | 1042 | void intel_enable_asle (struct drm_device *dev); |
0af7e4df MK |
1043 | int i915_get_vblank_timestamp(struct drm_device *dev, int crtc, |
1044 | int *max_error, | |
1045 | struct timeval *vblank_time, | |
1046 | unsigned flags); | |
1047 | ||
1048 | int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, | |
1049 | int *vpos, int *hpos); | |
01c66889 | 1050 | |
3bd3c932 CW |
1051 | #ifdef CONFIG_DEBUG_FS |
1052 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1053 | #else | |
1054 | #define i915_destroy_error_state(x) | |
1055 | #endif | |
1056 | ||
7c463586 | 1057 | |
1da177e4 | 1058 | /* i915_mem.c */ |
c153f45f EA |
1059 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
1060 | struct drm_file *file_priv); | |
1061 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
1062 | struct drm_file *file_priv); | |
1063 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
1064 | struct drm_file *file_priv); | |
1065 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
1066 | struct drm_file *file_priv); | |
1da177e4 | 1067 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 1068 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 1069 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
1070 | /* i915_gem.c */ |
1071 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1072 | struct drm_file *file_priv); | |
1073 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1074 | struct drm_file *file_priv); | |
1075 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1076 | struct drm_file *file_priv); | |
1077 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1078 | struct drm_file *file_priv); | |
1079 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1080 | struct drm_file *file_priv); | |
de151cf6 JB |
1081 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1082 | struct drm_file *file_priv); | |
673a394b EA |
1083 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1084 | struct drm_file *file_priv); | |
1085 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1086 | struct drm_file *file_priv); | |
1087 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1088 | struct drm_file *file_priv); | |
76446cac JB |
1089 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1090 | struct drm_file *file_priv); | |
673a394b EA |
1091 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1092 | struct drm_file *file_priv); | |
1093 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1094 | struct drm_file *file_priv); | |
1095 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1096 | struct drm_file *file_priv); | |
1097 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
1098 | struct drm_file *file_priv); | |
3ef94daa CW |
1099 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1100 | struct drm_file *file_priv); | |
673a394b EA |
1101 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1102 | struct drm_file *file_priv); | |
1103 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1104 | struct drm_file *file_priv); | |
1105 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1106 | struct drm_file *file_priv); | |
1107 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1108 | struct drm_file *file_priv); | |
5a125c3c EA |
1109 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1110 | struct drm_file *file_priv); | |
673a394b | 1111 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1112 | int i915_gem_init_object(struct drm_gem_object *obj); |
db53a302 | 1113 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
88241785 CW |
1114 | uint32_t invalidate_domains, |
1115 | uint32_t flush_domains); | |
05394f39 CW |
1116 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1117 | size_t size); | |
673a394b | 1118 | void i915_gem_free_object(struct drm_gem_object *obj); |
2021746e CW |
1119 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1120 | uint32_t alignment, | |
1121 | bool map_and_fenceable); | |
05394f39 | 1122 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1123 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 1124 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1125 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1126 | |
54cf91dc | 1127 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
ce453d81 | 1128 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
54cf91dc | 1129 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1130 | struct intel_ring_buffer *ring, |
1131 | u32 seqno); | |
54cf91dc | 1132 | |
ff72145b DA |
1133 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1134 | struct drm_device *dev, | |
1135 | struct drm_mode_create_dumb *args); | |
1136 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1137 | uint32_t handle, uint64_t *offset); | |
1138 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
1139 | uint32_t handle); | |
f787a5f5 CW |
1140 | /** |
1141 | * Returns true if seq1 is later than seq2. | |
1142 | */ | |
1143 | static inline bool | |
1144 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1145 | { | |
1146 | return (int32_t)(seq1 - seq2) >= 0; | |
1147 | } | |
1148 | ||
54cf91dc | 1149 | static inline u32 |
db53a302 | 1150 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
54cf91dc | 1151 | { |
db53a302 | 1152 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
54cf91dc CW |
1153 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
1154 | } | |
1155 | ||
d9e86c0e | 1156 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 1157 | struct intel_ring_buffer *pipelined); |
d9e86c0e | 1158 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1159 | |
b09a1fec | 1160 | void i915_gem_retire_requests(struct drm_device *dev); |
069efc1d | 1161 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1162 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1163 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1164 | uint32_t read_domains, | |
1165 | uint32_t write_domain); | |
ce453d81 | 1166 | int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj); |
2021746e | 1167 | int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); |
79e53945 | 1168 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
2021746e CW |
1169 | void i915_gem_do_init(struct drm_device *dev, |
1170 | unsigned long start, | |
1171 | unsigned long mappable_end, | |
1172 | unsigned long end); | |
1173 | int __must_check i915_gpu_idle(struct drm_device *dev); | |
1174 | int __must_check i915_gem_idle(struct drm_device *dev); | |
db53a302 CW |
1175 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1176 | struct drm_file *file, | |
1177 | struct drm_i915_gem_request *request); | |
1178 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, | |
ce453d81 | 1179 | uint32_t seqno); |
de151cf6 | 1180 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1181 | int __must_check |
1182 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1183 | bool write); | |
1184 | int __must_check | |
1185 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, | |
1186 | struct intel_ring_buffer *pipelined); | |
71acb5eb | 1187 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1188 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1189 | int id, |
1190 | int align); | |
71acb5eb | 1191 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1192 | struct drm_i915_gem_object *obj); |
71acb5eb | 1193 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1194 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1195 | |
467cffba CW |
1196 | uint32_t |
1197 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj); | |
1198 | ||
76aaf220 DV |
1199 | /* i915_gem_gtt.c */ |
1200 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | |
2021746e | 1201 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
05394f39 | 1202 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
76aaf220 | 1203 | |
b47eb4a2 | 1204 | /* i915_gem_evict.c */ |
2021746e CW |
1205 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1206 | unsigned alignment, bool mappable); | |
1207 | int __must_check i915_gem_evict_everything(struct drm_device *dev, | |
1208 | bool purgeable_only); | |
1209 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, | |
1210 | bool purgeable_only); | |
b47eb4a2 | 1211 | |
673a394b EA |
1212 | /* i915_gem_tiling.c */ |
1213 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
05394f39 CW |
1214 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1215 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1216 | |
1217 | /* i915_gem_debug.c */ | |
05394f39 | 1218 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1219 | const char *where, uint32_t mark); |
23bc5982 CW |
1220 | #if WATCH_LISTS |
1221 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1222 | #else |
23bc5982 | 1223 | #define i915_verify_lists(dev) 0 |
673a394b | 1224 | #endif |
05394f39 CW |
1225 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1226 | int handle); | |
1227 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1228 | const char *where, uint32_t mark); |
1da177e4 | 1229 | |
2017263e | 1230 | /* i915_debugfs.c */ |
27c202ad BG |
1231 | int i915_debugfs_init(struct drm_minor *minor); |
1232 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1233 | |
317c35d1 JB |
1234 | /* i915_suspend.c */ |
1235 | extern int i915_save_state(struct drm_device *dev); | |
1236 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1237 | |
1238 | /* i915_suspend.c */ | |
1239 | extern int i915_save_state(struct drm_device *dev); | |
1240 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1241 | |
f899fc64 CW |
1242 | /* intel_i2c.c */ |
1243 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1244 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
e957d772 CW |
1245 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1246 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1247 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1248 | { | |
1249 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1250 | } | |
f899fc64 CW |
1251 | extern void intel_i2c_reset(struct drm_device *dev); |
1252 | ||
3b617967 | 1253 | /* intel_opregion.c */ |
44834a67 CW |
1254 | extern int intel_opregion_setup(struct drm_device *dev); |
1255 | #ifdef CONFIG_ACPI | |
1256 | extern void intel_opregion_init(struct drm_device *dev); | |
1257 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1258 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1259 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1260 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1261 | #else |
44834a67 CW |
1262 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1263 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1264 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1265 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1266 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1267 | #endif |
8ee1c3db | 1268 | |
723bfd70 JB |
1269 | /* intel_acpi.c */ |
1270 | #ifdef CONFIG_ACPI | |
1271 | extern void intel_register_dsm_handler(void); | |
1272 | extern void intel_unregister_dsm_handler(void); | |
1273 | #else | |
1274 | static inline void intel_register_dsm_handler(void) { return; } | |
1275 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1276 | #endif /* CONFIG_ACPI */ | |
1277 | ||
79e53945 JB |
1278 | /* modesetting */ |
1279 | extern void intel_modeset_init(struct drm_device *dev); | |
1280 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
28d52043 | 1281 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
80824003 | 1282 | extern void i8xx_disable_fbc(struct drm_device *dev); |
74dff282 | 1283 | extern void g4x_disable_fbc(struct drm_device *dev); |
b52eb4dc | 1284 | extern void ironlake_disable_fbc(struct drm_device *dev); |
ee5382ae AJ |
1285 | extern void intel_disable_fbc(struct drm_device *dev); |
1286 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
1287 | extern bool intel_fbc_enabled(struct drm_device *dev); | |
7648fa99 | 1288 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
d5bb081b | 1289 | extern void ironlake_enable_rc6(struct drm_device *dev); |
3b8d8d91 | 1290 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
3bad0781 | 1291 | extern void intel_detect_pch (struct drm_device *dev); |
e3421a18 | 1292 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
3bad0781 | 1293 | |
6ef3d427 | 1294 | /* overlay */ |
3bd3c932 | 1295 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1296 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1297 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1298 | |
1299 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1300 | extern void intel_display_print_error_state(struct seq_file *m, | |
1301 | struct drm_device *dev, | |
1302 | struct intel_display_error_state *error); | |
3bd3c932 | 1303 | #endif |
6ef3d427 | 1304 | |
1ec14ad3 CW |
1305 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1306 | ||
1307 | #define BEGIN_LP_RING(n) \ | |
1308 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
1309 | ||
1310 | #define OUT_RING(x) \ | |
1311 | intel_ring_emit(LP_RING(dev_priv), x) | |
1312 | ||
1313 | #define ADVANCE_LP_RING() \ | |
1314 | intel_ring_advance(LP_RING(dev_priv)) | |
1315 | ||
546b0974 EA |
1316 | /** |
1317 | * Lock test for when it's just for synchronization of ring access. | |
1318 | * | |
1319 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1320 | * has access to the ring. | |
1321 | */ | |
05394f39 | 1322 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1ec14ad3 | 1323 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
05394f39 | 1324 | LOCK_TEST_WITH_RETURN(dev, file); \ |
546b0974 EA |
1325 | } while (0) |
1326 | ||
cae5852d | 1327 | |
5f75377d KP |
1328 | #define __i915_read(x, y) \ |
1329 | static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
1330 | u##x val = read##y(dev_priv->regs + reg); \ | |
db53a302 | 1331 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
5f75377d KP |
1332 | return val; \ |
1333 | } | |
1334 | __i915_read(8, b) | |
1335 | __i915_read(16, w) | |
1336 | __i915_read(32, l) | |
1337 | __i915_read(64, q) | |
1338 | #undef __i915_read | |
1339 | ||
1340 | #define __i915_write(x, y) \ | |
1341 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
db53a302 | 1342 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
5f75377d KP |
1343 | write##y(val, dev_priv->regs + reg); \ |
1344 | } | |
1345 | __i915_write(8, b) | |
1346 | __i915_write(16, w) | |
1347 | __i915_write(32, l) | |
1348 | __i915_write(64, q) | |
1349 | #undef __i915_write | |
1350 | ||
1351 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1352 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1353 | ||
1354 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1355 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1356 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1357 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1358 | ||
1359 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1360 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1361 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1362 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1363 | |
1364 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1365 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1366 | |
1367 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1368 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1369 | ||
ba4f01a3 | 1370 | |
cae5852d ZN |
1371 | /* On SNB platform, before reading ring registers forcewake bit |
1372 | * must be set to prevent GT core from power down and stale values being | |
1373 | * returned. | |
1374 | */ | |
91355834 CW |
1375 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1376 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
1377 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); | |
1378 | ||
1379 | static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg) | |
cae5852d | 1380 | { |
eb43f4af CW |
1381 | u32 val; |
1382 | ||
1383 | if (dev_priv->info->gen >= 6) { | |
91355834 | 1384 | __gen6_gt_force_wake_get(dev_priv); |
eb43f4af | 1385 | val = I915_READ(reg); |
91355834 | 1386 | __gen6_gt_force_wake_put(dev_priv); |
eb43f4af CW |
1387 | } else |
1388 | val = I915_READ(reg); | |
1389 | ||
1390 | return val; | |
cae5852d ZN |
1391 | } |
1392 | ||
91355834 CW |
1393 | static inline void i915_gt_write(struct drm_i915_private *dev_priv, |
1394 | u32 reg, u32 val) | |
ba4f01a3 | 1395 | { |
91355834 CW |
1396 | if (dev_priv->info->gen >= 6) |
1397 | __gen6_gt_wait_for_fifo(dev_priv); | |
1398 | I915_WRITE(reg, val); | |
ba4f01a3 | 1399 | } |
1da177e4 | 1400 | #endif |