Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
0ade6386 | 38 | #include <drm/intel-gtt.h> |
585fb111 | 39 | |
1da177e4 LT |
40 | /* General customization: |
41 | */ | |
42 | ||
43 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
44 | ||
45 | #define DRIVER_NAME "i915" | |
46 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 47 | #define DRIVER_DATE "20080730" |
1da177e4 | 48 | |
317c35d1 JB |
49 | enum pipe { |
50 | PIPE_A = 0, | |
51 | PIPE_B, | |
52 | }; | |
53 | ||
80824003 JB |
54 | enum plane { |
55 | PLANE_A = 0, | |
56 | PLANE_B, | |
57 | }; | |
58 | ||
52440211 KP |
59 | #define I915_NUM_PIPE 2 |
60 | ||
62fdfeaf EA |
61 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
62 | ||
1da177e4 LT |
63 | /* Interface history: |
64 | * | |
65 | * 1.1: Original. | |
0d6aa60b DA |
66 | * 1.2: Add Power Management |
67 | * 1.3: Add vblank support | |
de227f5f | 68 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 69 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
70 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
71 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
72 | */ |
73 | #define DRIVER_MAJOR 1 | |
2228ed67 | 74 | #define DRIVER_MINOR 6 |
1da177e4 LT |
75 | #define DRIVER_PATCHLEVEL 0 |
76 | ||
673a394b | 77 | #define WATCH_COHERENCY 0 |
673a394b | 78 | #define WATCH_EXEC 0 |
673a394b | 79 | #define WATCH_RELOC 0 |
23bc5982 | 80 | #define WATCH_LISTS 0 |
673a394b EA |
81 | #define WATCH_PWRITE 0 |
82 | ||
71acb5eb DA |
83 | #define I915_GEM_PHYS_CURSOR_0 1 |
84 | #define I915_GEM_PHYS_CURSOR_1 2 | |
85 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
86 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
87 | ||
88 | struct drm_i915_gem_phys_object { | |
89 | int id; | |
90 | struct page **page_list; | |
91 | drm_dma_handle_t *handle; | |
92 | struct drm_gem_object *cur_obj; | |
93 | }; | |
94 | ||
1da177e4 LT |
95 | struct mem_block { |
96 | struct mem_block *next; | |
97 | struct mem_block *prev; | |
98 | int start; | |
99 | int size; | |
6c340eac | 100 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
101 | }; |
102 | ||
0a3e67a4 JB |
103 | struct opregion_header; |
104 | struct opregion_acpi; | |
105 | struct opregion_swsci; | |
106 | struct opregion_asle; | |
107 | ||
8ee1c3db MG |
108 | struct intel_opregion { |
109 | struct opregion_header *header; | |
110 | struct opregion_acpi *acpi; | |
111 | struct opregion_swsci *swsci; | |
112 | struct opregion_asle *asle; | |
44834a67 | 113 | void *vbt; |
8ee1c3db | 114 | }; |
44834a67 | 115 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 116 | |
6ef3d427 CW |
117 | struct intel_overlay; |
118 | struct intel_overlay_error_state; | |
119 | ||
7c1c2871 DA |
120 | struct drm_i915_master_private { |
121 | drm_local_map_t *sarea; | |
122 | struct _drm_i915_sarea *sarea_priv; | |
123 | }; | |
de151cf6 JB |
124 | #define I915_FENCE_REG_NONE -1 |
125 | ||
126 | struct drm_i915_fence_reg { | |
127 | struct drm_gem_object *obj; | |
007cc8ac | 128 | struct list_head lru_list; |
53640e1d | 129 | bool gpu; |
de151cf6 | 130 | }; |
7c1c2871 | 131 | |
9b9d172d | 132 | struct sdvo_device_mapping { |
e957d772 | 133 | u8 initialized; |
9b9d172d | 134 | u8 dvo_port; |
135 | u8 slave_addr; | |
136 | u8 dvo_wiring; | |
e957d772 CW |
137 | u8 i2c_pin; |
138 | u8 i2c_speed; | |
b1083333 | 139 | u8 ddc_pin; |
9b9d172d | 140 | }; |
141 | ||
63eeaf38 JB |
142 | struct drm_i915_error_state { |
143 | u32 eir; | |
144 | u32 pgtbl_er; | |
145 | u32 pipeastat; | |
146 | u32 pipebstat; | |
147 | u32 ipeir; | |
148 | u32 ipehr; | |
149 | u32 instdone; | |
150 | u32 acthd; | |
151 | u32 instpm; | |
152 | u32 instps; | |
153 | u32 instdone1; | |
154 | u32 seqno; | |
9df30794 | 155 | u64 bbaddr; |
63eeaf38 | 156 | struct timeval time; |
9df30794 CW |
157 | struct drm_i915_error_object { |
158 | int page_count; | |
159 | u32 gtt_offset; | |
160 | u32 *pages[0]; | |
161 | } *ringbuffer, *batchbuffer[2]; | |
162 | struct drm_i915_error_buffer { | |
163 | size_t size; | |
164 | u32 name; | |
165 | u32 seqno; | |
166 | u32 gtt_offset; | |
167 | u32 read_domains; | |
168 | u32 write_domain; | |
169 | u32 fence_reg; | |
170 | s32 pinned:2; | |
171 | u32 tiling:2; | |
172 | u32 dirty:1; | |
173 | u32 purgeable:1; | |
174 | } *active_bo; | |
175 | u32 active_bo_count; | |
6ef3d427 | 176 | struct intel_overlay_error_state *overlay; |
63eeaf38 JB |
177 | }; |
178 | ||
e70236a8 JB |
179 | struct drm_i915_display_funcs { |
180 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 181 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
182 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
183 | void (*disable_fbc)(struct drm_device *dev); | |
184 | int (*get_display_clock_speed)(struct drm_device *dev); | |
185 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
186 | void (*update_wm)(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
187 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
188 | int pixel_size); | |
e70236a8 JB |
189 | /* clock updates for mode set */ |
190 | /* cursor updates */ | |
191 | /* render clock increase/decrease */ | |
192 | /* display clock increase/decrease */ | |
193 | /* pll clock increase/decrease */ | |
194 | /* clock gating init */ | |
195 | }; | |
196 | ||
cfdf1fa2 | 197 | struct intel_device_info { |
c96c3a8c | 198 | u8 gen; |
cfdf1fa2 | 199 | u8 is_mobile : 1; |
5ce8ba7c | 200 | u8 is_i85x : 1; |
cfdf1fa2 | 201 | u8 is_i915g : 1; |
cfdf1fa2 | 202 | u8 is_i945gm : 1; |
cfdf1fa2 KH |
203 | u8 is_g33 : 1; |
204 | u8 need_gfx_hws : 1; | |
205 | u8 is_g4x : 1; | |
206 | u8 is_pineview : 1; | |
534843da CW |
207 | u8 is_broadwater : 1; |
208 | u8 is_crestline : 1; | |
cfdf1fa2 KH |
209 | u8 has_fbc : 1; |
210 | u8 has_rc6 : 1; | |
211 | u8 has_pipe_cxsr : 1; | |
212 | u8 has_hotplug : 1; | |
b295d1b6 | 213 | u8 cursor_needs_physical : 1; |
31578148 CW |
214 | u8 has_overlay : 1; |
215 | u8 overlay_needs_physical : 1; | |
a6c45cf0 | 216 | u8 supports_tv : 1; |
92f49d9c | 217 | u8 has_bsd_ring : 1; |
549f7365 | 218 | u8 has_blt_ring : 1; |
cfdf1fa2 KH |
219 | }; |
220 | ||
b5e50c3f | 221 | enum no_fbc_reason { |
bed4a673 | 222 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
223 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
224 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
225 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
226 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
227 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 228 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
b5e50c3f JB |
229 | }; |
230 | ||
3bad0781 ZW |
231 | enum intel_pch { |
232 | PCH_IBX, /* Ibexpeak PCH */ | |
233 | PCH_CPT, /* Cougarpoint PCH */ | |
234 | }; | |
235 | ||
b690e96c JB |
236 | #define QUIRK_PIPEA_FORCE (1<<0) |
237 | ||
8be48d92 | 238 | struct intel_fbdev; |
38651674 | 239 | |
1da177e4 | 240 | typedef struct drm_i915_private { |
673a394b EA |
241 | struct drm_device *dev; |
242 | ||
cfdf1fa2 KH |
243 | const struct intel_device_info *info; |
244 | ||
ac5c4e76 DA |
245 | int has_gem; |
246 | ||
3043c60c | 247 | void __iomem *regs; |
1da177e4 | 248 | |
f899fc64 CW |
249 | struct intel_gmbus { |
250 | struct i2c_adapter adapter; | |
e957d772 CW |
251 | struct i2c_adapter *force_bit; |
252 | u32 reg0; | |
f899fc64 CW |
253 | } *gmbus; |
254 | ||
ec2a4c3f | 255 | struct pci_dev *bridge_dev; |
8187a2b7 | 256 | struct intel_ring_buffer render_ring; |
d1b851fc | 257 | struct intel_ring_buffer bsd_ring; |
549f7365 | 258 | struct intel_ring_buffer blt_ring; |
6f392d54 | 259 | uint32_t next_seqno; |
1da177e4 | 260 | |
9c8da5eb | 261 | drm_dma_handle_t *status_page_dmah; |
e552eb70 | 262 | void *seqno_page; |
1da177e4 | 263 | dma_addr_t dma_status_page; |
0a3e67a4 | 264 | uint32_t counter; |
e552eb70 | 265 | unsigned int seqno_gfx_addr; |
dc7a9319 | 266 | drm_local_map_t hws_map; |
e552eb70 | 267 | struct drm_gem_object *seqno_obj; |
97f5ab66 | 268 | struct drm_gem_object *pwrctx; |
aa40d6bb | 269 | struct drm_gem_object *renderctx; |
1da177e4 | 270 | |
d7658989 JB |
271 | struct resource mch_res; |
272 | ||
a6b54f3f | 273 | unsigned int cpp; |
1da177e4 LT |
274 | int back_offset; |
275 | int front_offset; | |
276 | int current_page; | |
277 | int page_flipping; | |
be282fd4 JB |
278 | #define I915_DEBUG_READ (1<<0) |
279 | #define I915_DEBUG_WRITE (1<<1) | |
280 | unsigned long debug_flags; | |
1da177e4 LT |
281 | |
282 | wait_queue_head_t irq_queue; | |
283 | atomic_t irq_received; | |
ed4cb414 EA |
284 | /** Protects user_irq_refcount and irq_mask_reg */ |
285 | spinlock_t user_irq_lock; | |
9d34e5db | 286 | u32 trace_irq_seqno; |
ed4cb414 EA |
287 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
288 | u32 irq_mask_reg; | |
7c463586 | 289 | u32 pipestat[2]; |
f2b115e6 | 290 | /** splitted irq regs for graphics and display engine on Ironlake, |
036a4a7d ZW |
291 | irq_mask_reg is still used for display irq. */ |
292 | u32 gt_irq_mask_reg; | |
293 | u32 gt_irq_enable_reg; | |
294 | u32 de_irq_enable_reg; | |
c650156a ZW |
295 | u32 pch_irq_mask_reg; |
296 | u32 pch_irq_enable_reg; | |
1da177e4 | 297 | |
5ca58282 JB |
298 | u32 hotplug_supported_mask; |
299 | struct work_struct hotplug_work; | |
300 | ||
1da177e4 LT |
301 | int tex_lru_log_granularity; |
302 | int allow_batchbuffer; | |
303 | struct mem_block *agp_heap; | |
0d6aa60b | 304 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 305 | int vblank_pipe; |
a3524f1b | 306 | int num_pipe; |
a6b54f3f | 307 | |
f65d9421 | 308 | /* For hangcheck timer */ |
b3b079db | 309 | #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */ |
f65d9421 BG |
310 | struct timer_list hangcheck_timer; |
311 | int hangcheck_count; | |
312 | uint32_t last_acthd; | |
cbb465e7 CW |
313 | uint32_t last_instdone; |
314 | uint32_t last_instdone1; | |
f65d9421 | 315 | |
80824003 JB |
316 | unsigned long cfb_size; |
317 | unsigned long cfb_pitch; | |
bed4a673 | 318 | unsigned long cfb_offset; |
80824003 JB |
319 | int cfb_fence; |
320 | int cfb_plane; | |
bed4a673 | 321 | int cfb_y; |
80824003 | 322 | |
79e53945 JB |
323 | int irq_enabled; |
324 | ||
8ee1c3db MG |
325 | struct intel_opregion opregion; |
326 | ||
02e792fb DV |
327 | /* overlay */ |
328 | struct intel_overlay *overlay; | |
329 | ||
79e53945 | 330 | /* LVDS info */ |
a9573556 | 331 | int backlight_level; /* restore backlight to this value */ |
79e53945 | 332 | struct drm_display_mode *panel_fixed_mode; |
88631706 ML |
333 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
334 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
335 | |
336 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
337 | unsigned int int_tv_support:1; |
338 | unsigned int lvds_dither:1; | |
339 | unsigned int lvds_vbt:1; | |
340 | unsigned int int_crt_support:1; | |
43565a06 KH |
341 | unsigned int lvds_use_ssc:1; |
342 | int lvds_ssc_freq; | |
5ceb0f9b | 343 | struct { |
9f0e7ff4 JB |
344 | int rate; |
345 | int lanes; | |
346 | int preemphasis; | |
347 | int vswing; | |
348 | ||
349 | bool initialized; | |
350 | bool support; | |
351 | int bpp; | |
352 | struct edp_power_seq pps; | |
5ceb0f9b | 353 | } edp; |
89667383 | 354 | bool no_aux_handshake; |
79e53945 | 355 | |
c1c7af60 JB |
356 | struct notifier_block lid_notifier; |
357 | ||
f899fc64 | 358 | int crt_ddc_pin; |
de151cf6 JB |
359 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
360 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
361 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
362 | ||
95534263 | 363 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 364 | |
63eeaf38 JB |
365 | spinlock_t error_lock; |
366 | struct drm_i915_error_state *first_error; | |
8a905236 | 367 | struct work_struct error_work; |
30dbf0c0 | 368 | struct completion error_completion; |
9c9fe1f8 | 369 | struct workqueue_struct *wq; |
63eeaf38 | 370 | |
e70236a8 JB |
371 | /* Display functions */ |
372 | struct drm_i915_display_funcs display; | |
373 | ||
3bad0781 ZW |
374 | /* PCH chipset type */ |
375 | enum intel_pch pch_type; | |
376 | ||
b690e96c JB |
377 | unsigned long quirks; |
378 | ||
ba8bbcf6 | 379 | /* Register state */ |
c9354c85 | 380 | bool modeset_on_lid; |
ba8bbcf6 JB |
381 | u8 saveLBB; |
382 | u32 saveDSPACNTR; | |
383 | u32 saveDSPBCNTR; | |
e948e994 | 384 | u32 saveDSPARB; |
461cba2d | 385 | u32 saveHWS; |
ba8bbcf6 JB |
386 | u32 savePIPEACONF; |
387 | u32 savePIPEBCONF; | |
388 | u32 savePIPEASRC; | |
389 | u32 savePIPEBSRC; | |
390 | u32 saveFPA0; | |
391 | u32 saveFPA1; | |
392 | u32 saveDPLL_A; | |
393 | u32 saveDPLL_A_MD; | |
394 | u32 saveHTOTAL_A; | |
395 | u32 saveHBLANK_A; | |
396 | u32 saveHSYNC_A; | |
397 | u32 saveVTOTAL_A; | |
398 | u32 saveVBLANK_A; | |
399 | u32 saveVSYNC_A; | |
400 | u32 saveBCLRPAT_A; | |
5586c8bc | 401 | u32 saveTRANSACONF; |
42048781 ZW |
402 | u32 saveTRANS_HTOTAL_A; |
403 | u32 saveTRANS_HBLANK_A; | |
404 | u32 saveTRANS_HSYNC_A; | |
405 | u32 saveTRANS_VTOTAL_A; | |
406 | u32 saveTRANS_VBLANK_A; | |
407 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 408 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
409 | u32 saveDSPASTRIDE; |
410 | u32 saveDSPASIZE; | |
411 | u32 saveDSPAPOS; | |
585fb111 | 412 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
413 | u32 saveDSPASURF; |
414 | u32 saveDSPATILEOFF; | |
415 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 416 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
417 | u32 saveBLC_PWM_CTL; |
418 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
419 | u32 saveBLC_CPU_PWM_CTL; |
420 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
421 | u32 saveFPB0; |
422 | u32 saveFPB1; | |
423 | u32 saveDPLL_B; | |
424 | u32 saveDPLL_B_MD; | |
425 | u32 saveHTOTAL_B; | |
426 | u32 saveHBLANK_B; | |
427 | u32 saveHSYNC_B; | |
428 | u32 saveVTOTAL_B; | |
429 | u32 saveVBLANK_B; | |
430 | u32 saveVSYNC_B; | |
431 | u32 saveBCLRPAT_B; | |
5586c8bc | 432 | u32 saveTRANSBCONF; |
42048781 ZW |
433 | u32 saveTRANS_HTOTAL_B; |
434 | u32 saveTRANS_HBLANK_B; | |
435 | u32 saveTRANS_HSYNC_B; | |
436 | u32 saveTRANS_VTOTAL_B; | |
437 | u32 saveTRANS_VBLANK_B; | |
438 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 439 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
440 | u32 saveDSPBSTRIDE; |
441 | u32 saveDSPBSIZE; | |
442 | u32 saveDSPBPOS; | |
585fb111 | 443 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
444 | u32 saveDSPBSURF; |
445 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
446 | u32 saveVGA0; |
447 | u32 saveVGA1; | |
448 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
449 | u32 saveVGACNTRL; |
450 | u32 saveADPA; | |
451 | u32 saveLVDS; | |
585fb111 JB |
452 | u32 savePP_ON_DELAYS; |
453 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
454 | u32 saveDVOA; |
455 | u32 saveDVOB; | |
456 | u32 saveDVOC; | |
457 | u32 savePP_ON; | |
458 | u32 savePP_OFF; | |
459 | u32 savePP_CONTROL; | |
585fb111 | 460 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
461 | u32 savePFIT_CONTROL; |
462 | u32 save_palette_a[256]; | |
463 | u32 save_palette_b[256]; | |
06027f91 | 464 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
465 | u32 saveFBC_CFB_BASE; |
466 | u32 saveFBC_LL_BASE; | |
467 | u32 saveFBC_CONTROL; | |
468 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
469 | u32 saveIER; |
470 | u32 saveIIR; | |
471 | u32 saveIMR; | |
42048781 ZW |
472 | u32 saveDEIER; |
473 | u32 saveDEIMR; | |
474 | u32 saveGTIER; | |
475 | u32 saveGTIMR; | |
476 | u32 saveFDI_RXA_IMR; | |
477 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 478 | u32 saveCACHE_MODE_0; |
1f84e550 | 479 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
480 | u32 saveSWF0[16]; |
481 | u32 saveSWF1[16]; | |
482 | u32 saveSWF2[3]; | |
483 | u8 saveMSR; | |
484 | u8 saveSR[8]; | |
123f794f | 485 | u8 saveGR[25]; |
ba8bbcf6 | 486 | u8 saveAR_INDEX; |
a59e122a | 487 | u8 saveAR[21]; |
ba8bbcf6 | 488 | u8 saveDACMASK; |
a59e122a | 489 | u8 saveCR[37]; |
79f11c19 | 490 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
491 | u32 saveCURACNTR; |
492 | u32 saveCURAPOS; | |
493 | u32 saveCURABASE; | |
494 | u32 saveCURBCNTR; | |
495 | u32 saveCURBPOS; | |
496 | u32 saveCURBBASE; | |
497 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
498 | u32 saveDP_B; |
499 | u32 saveDP_C; | |
500 | u32 saveDP_D; | |
501 | u32 savePIPEA_GMCH_DATA_M; | |
502 | u32 savePIPEB_GMCH_DATA_M; | |
503 | u32 savePIPEA_GMCH_DATA_N; | |
504 | u32 savePIPEB_GMCH_DATA_N; | |
505 | u32 savePIPEA_DP_LINK_M; | |
506 | u32 savePIPEB_DP_LINK_M; | |
507 | u32 savePIPEA_DP_LINK_N; | |
508 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
509 | u32 saveFDI_RXA_CTL; |
510 | u32 saveFDI_TXA_CTL; | |
511 | u32 saveFDI_RXB_CTL; | |
512 | u32 saveFDI_TXB_CTL; | |
513 | u32 savePFA_CTL_1; | |
514 | u32 savePFB_CTL_1; | |
515 | u32 savePFA_WIN_SZ; | |
516 | u32 savePFB_WIN_SZ; | |
517 | u32 savePFA_WIN_POS; | |
518 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
519 | u32 savePCH_DREF_CONTROL; |
520 | u32 saveDISP_ARB_CTL; | |
521 | u32 savePIPEA_DATA_M1; | |
522 | u32 savePIPEA_DATA_N1; | |
523 | u32 savePIPEA_LINK_M1; | |
524 | u32 savePIPEA_LINK_N1; | |
525 | u32 savePIPEB_DATA_M1; | |
526 | u32 savePIPEB_DATA_N1; | |
527 | u32 savePIPEB_LINK_M1; | |
528 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 529 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
530 | |
531 | struct { | |
19966754 DV |
532 | /** Bridge to intel-gtt-ko */ |
533 | struct intel_gtt *gtt; | |
534 | /** Memory allocator for GTT stolen memory */ | |
535 | struct drm_mm vram; | |
536 | /** Memory allocator for GTT */ | |
673a394b | 537 | struct drm_mm gtt_space; |
a6e0aa42 DV |
538 | /** End of mappable part of GTT */ |
539 | unsigned long gtt_mappable_end; | |
673a394b | 540 | |
0839ccb8 | 541 | struct io_mapping *gtt_mapping; |
ab657db1 | 542 | int gtt_mtrr; |
0839ccb8 | 543 | |
31169714 CW |
544 | /** |
545 | * Membership on list of all loaded devices, used to evict | |
546 | * inactive buffers under memory pressure. | |
547 | * | |
548 | * Modifications should only be done whilst holding the | |
549 | * shrink_list_lock spinlock. | |
550 | */ | |
551 | struct list_head shrink_list; | |
552 | ||
69dc4987 CW |
553 | /** |
554 | * List of objects currently involved in rendering. | |
555 | * | |
556 | * Includes buffers having the contents of their GPU caches | |
557 | * flushed, not necessarily primitives. last_rendering_seqno | |
558 | * represents when the rendering involved will be completed. | |
559 | * | |
560 | * A reference is held on the buffer while on this list. | |
561 | */ | |
562 | struct list_head active_list; | |
563 | ||
673a394b EA |
564 | /** |
565 | * List of objects which are not in the ringbuffer but which | |
566 | * still have a write_domain which needs to be flushed before | |
567 | * unbinding. | |
568 | * | |
ce44b0ea EA |
569 | * last_rendering_seqno is 0 while an object is in this list. |
570 | * | |
673a394b EA |
571 | * A reference is held on the buffer while on this list. |
572 | */ | |
573 | struct list_head flushing_list; | |
574 | ||
575 | /** | |
576 | * LRU list of objects which are not in the ringbuffer and | |
577 | * are ready to unbind, but are still in the GTT. | |
578 | * | |
ce44b0ea EA |
579 | * last_rendering_seqno is 0 while an object is in this list. |
580 | * | |
673a394b EA |
581 | * A reference is not held on the buffer while on this list, |
582 | * as merely being GTT-bound shouldn't prevent its being | |
583 | * freed, and we'll pull it off the list in the free path. | |
584 | */ | |
585 | struct list_head inactive_list; | |
586 | ||
f13d3f73 CW |
587 | /** |
588 | * LRU list of objects which are not in the ringbuffer but | |
589 | * are still pinned in the GTT. | |
590 | */ | |
591 | struct list_head pinned_list; | |
592 | ||
a09ba7fa EA |
593 | /** LRU list of objects with fence regs on them. */ |
594 | struct list_head fence_list; | |
595 | ||
be72615b CW |
596 | /** |
597 | * List of objects currently pending being freed. | |
598 | * | |
599 | * These objects are no longer in use, but due to a signal | |
600 | * we were prevented from freeing them at the appointed time. | |
601 | */ | |
602 | struct list_head deferred_free_list; | |
603 | ||
673a394b EA |
604 | /** |
605 | * We leave the user IRQ off as much as possible, | |
606 | * but this means that requests will finish and never | |
607 | * be retired once the system goes idle. Set a timer to | |
608 | * fire periodically while the ring is running. When it | |
609 | * fires, go retire requests. | |
610 | */ | |
611 | struct delayed_work retire_work; | |
612 | ||
673a394b EA |
613 | /** |
614 | * Flag if the X Server, and thus DRM, is not currently in | |
615 | * control of the device. | |
616 | * | |
617 | * This is set between LeaveVT and EnterVT. It needs to be | |
618 | * replaced with a semaphore. It also needs to be | |
619 | * transitioned away from for kernel modesetting. | |
620 | */ | |
621 | int suspended; | |
622 | ||
623 | /** | |
624 | * Flag if the hardware appears to be wedged. | |
625 | * | |
626 | * This is set when attempts to idle the device timeout. | |
627 | * It prevents command submission from occuring and makes | |
628 | * every pending request fail | |
629 | */ | |
ba1234d1 | 630 | atomic_t wedged; |
673a394b EA |
631 | |
632 | /** Bit 6 swizzling required for X tiling */ | |
633 | uint32_t bit_6_swizzle_x; | |
634 | /** Bit 6 swizzling required for Y tiling */ | |
635 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
636 | |
637 | /* storage for physical objects */ | |
638 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a CW |
639 | |
640 | uint32_t flush_rings; | |
73aa808f CW |
641 | |
642 | /* accounting, useful for userland debugging */ | |
643 | size_t object_memory; | |
644 | size_t pin_memory; | |
645 | size_t gtt_memory; | |
646 | size_t gtt_total; | |
647 | u32 object_count; | |
648 | u32 pin_count; | |
649 | u32 gtt_count; | |
673a394b | 650 | } mm; |
9b9d172d | 651 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
652 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
653 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
654 | /* Panel fitter placement and size for Ironlake+ */ |
655 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 656 | |
6b95a207 KH |
657 | struct drm_crtc *plane_to_crtc_mapping[2]; |
658 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
659 | wait_queue_head_t pending_flip_queue; | |
1afe3e9d | 660 | bool flip_pending_is_done; |
6b95a207 | 661 | |
652c393a JB |
662 | /* Reclocking support */ |
663 | bool render_reclock_avail; | |
664 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
665 | /* indicates the reduced downclock for LVDS*/ |
666 | int lvds_downclock; | |
652c393a JB |
667 | struct work_struct idle_work; |
668 | struct timer_list idle_timer; | |
669 | bool busy; | |
670 | u16 orig_clock; | |
6363ee6f ZY |
671 | int child_dev_num; |
672 | struct child_device_config *child_dev; | |
a2565377 | 673 | struct drm_connector *int_lvds_connector; |
f97108d1 | 674 | |
c4804411 | 675 | bool mchbar_need_disable; |
f97108d1 JB |
676 | |
677 | u8 cur_delay; | |
678 | u8 min_delay; | |
679 | u8 max_delay; | |
7648fa99 JB |
680 | u8 fmax; |
681 | u8 fstart; | |
682 | ||
683 | u64 last_count1; | |
684 | unsigned long last_time1; | |
685 | u64 last_count2; | |
686 | struct timespec last_time2; | |
687 | unsigned long gfx_power; | |
688 | int c_m; | |
689 | int r_t; | |
690 | u8 corr; | |
691 | spinlock_t *mchdev_lock; | |
b5e50c3f JB |
692 | |
693 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 694 | |
20bf377e JB |
695 | struct drm_mm_node *compressed_fb; |
696 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 697 | |
ae681d96 CW |
698 | unsigned long last_gpu_reset; |
699 | ||
8be48d92 DA |
700 | /* list of fbdev register on this device */ |
701 | struct intel_fbdev *fbdev; | |
1da177e4 LT |
702 | } drm_i915_private_t; |
703 | ||
673a394b EA |
704 | /** driver private structure attached to each drm_gem_object */ |
705 | struct drm_i915_gem_object { | |
c397b908 | 706 | struct drm_gem_object base; |
673a394b EA |
707 | |
708 | /** Current space allocated to this object in the GTT, if any. */ | |
709 | struct drm_mm_node *gtt_space; | |
710 | ||
711 | /** This object's place on the active/flushing/inactive lists */ | |
69dc4987 CW |
712 | struct list_head ring_list; |
713 | struct list_head mm_list; | |
99fcb766 DV |
714 | /** This object's place on GPU write list */ |
715 | struct list_head gpu_write_list; | |
cd377ea9 CW |
716 | /** This object's place on eviction list */ |
717 | struct list_head evict_list; | |
673a394b EA |
718 | |
719 | /** | |
720 | * This is set if the object is on the active or flushing lists | |
721 | * (has pending rendering), and is not set if it's on inactive (ready | |
722 | * to be unbound). | |
723 | */ | |
778c3544 | 724 | unsigned int active : 1; |
673a394b EA |
725 | |
726 | /** | |
727 | * This is set if the object has been written to since last bound | |
728 | * to the GTT | |
729 | */ | |
778c3544 DV |
730 | unsigned int dirty : 1; |
731 | ||
732 | /** | |
733 | * Fence register bits (if any) for this object. Will be set | |
734 | * as needed when mapped into the GTT. | |
735 | * Protected by dev->struct_mutex. | |
736 | * | |
737 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) | |
738 | */ | |
11824e8c | 739 | signed int fence_reg : 5; |
778c3544 DV |
740 | |
741 | /** | |
742 | * Used for checking the object doesn't appear more than once | |
743 | * in an execbuffer object list. | |
744 | */ | |
745 | unsigned int in_execbuffer : 1; | |
746 | ||
747 | /** | |
748 | * Advice: are the backing pages purgeable? | |
749 | */ | |
750 | unsigned int madv : 2; | |
751 | ||
752 | /** | |
753 | * Refcount for the pages array. With the current locking scheme, there | |
754 | * are at most two concurrent users: Binding a bo to the gtt and | |
755 | * pwrite/pread using physical addresses. So two bits for a maximum | |
756 | * of two users are enough. | |
757 | */ | |
758 | unsigned int pages_refcount : 2; | |
759 | #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3 | |
760 | ||
761 | /** | |
762 | * Current tiling mode for the object. | |
763 | */ | |
764 | unsigned int tiling_mode : 2; | |
765 | ||
766 | /** How many users have pinned this object in GTT space. The following | |
767 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
768 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
769 | * times for the same batchbuffer), and the framebuffer code. When | |
770 | * switching/pageflipping, the framebuffer code has at most two buffers | |
771 | * pinned per crtc. | |
772 | * | |
773 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
774 | * bits with absolutely no headroom. So use 4 bits. */ | |
11824e8c | 775 | unsigned int pin_count : 4; |
778c3544 | 776 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b EA |
777 | |
778 | /** AGP memory structure for our GTT binding. */ | |
779 | DRM_AGP_MEM *agp_mem; | |
780 | ||
856fa198 | 781 | struct page **pages; |
673a394b EA |
782 | |
783 | /** | |
784 | * Current offset of the object in GTT space. | |
785 | * | |
786 | * This is the same as gtt_space->start | |
787 | */ | |
788 | uint32_t gtt_offset; | |
e67b8ce1 | 789 | |
852835f3 ZN |
790 | /* Which ring is refering to is this object */ |
791 | struct intel_ring_buffer *ring; | |
792 | ||
de151cf6 JB |
793 | /** |
794 | * Fake offset for use by mmap(2) | |
795 | */ | |
796 | uint64_t mmap_offset; | |
797 | ||
673a394b EA |
798 | /** Breadcrumb of last rendering to the buffer. */ |
799 | uint32_t last_rendering_seqno; | |
800 | ||
778c3544 | 801 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 802 | uint32_t stride; |
673a394b | 803 | |
280b713b | 804 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 805 | unsigned long *bit_17; |
280b713b | 806 | |
ba1eb1d8 KP |
807 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
808 | uint32_t agp_type; | |
809 | ||
673a394b | 810 | /** |
e47c68e9 EA |
811 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
812 | * flags which individual pages are valid. | |
673a394b EA |
813 | */ |
814 | uint8_t *page_cpu_valid; | |
79e53945 JB |
815 | |
816 | /** User space pin count and filp owning the pin */ | |
817 | uint32_t user_pin_count; | |
818 | struct drm_file *pin_filp; | |
71acb5eb DA |
819 | |
820 | /** for phy allocated objects */ | |
821 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 822 | |
6b95a207 KH |
823 | /** |
824 | * Number of crtcs where this object is currently the fb, but | |
825 | * will be page flipped away on the next vblank. When it | |
826 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
827 | */ | |
828 | atomic_t pending_flip; | |
673a394b EA |
829 | }; |
830 | ||
62b8b215 | 831 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 832 | |
673a394b EA |
833 | /** |
834 | * Request queue structure. | |
835 | * | |
836 | * The request queue allows us to note sequence numbers that have been emitted | |
837 | * and may be associated with active buffers to be retired. | |
838 | * | |
839 | * By keeping this list, we can avoid having to do questionable | |
840 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
841 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
842 | */ | |
843 | struct drm_i915_gem_request { | |
852835f3 ZN |
844 | /** On Which ring this request was generated */ |
845 | struct intel_ring_buffer *ring; | |
846 | ||
673a394b EA |
847 | /** GEM sequence number associated with this request. */ |
848 | uint32_t seqno; | |
849 | ||
850 | /** Time at which this request was emitted, in jiffies. */ | |
851 | unsigned long emitted_jiffies; | |
852 | ||
b962442e | 853 | /** global list entry for this request */ |
673a394b | 854 | struct list_head list; |
b962442e | 855 | |
f787a5f5 | 856 | struct drm_i915_file_private *file_priv; |
b962442e EA |
857 | /** file_priv list entry for this request */ |
858 | struct list_head client_list; | |
673a394b EA |
859 | }; |
860 | ||
861 | struct drm_i915_file_private { | |
862 | struct { | |
1c25595f | 863 | struct spinlock lock; |
b962442e | 864 | struct list_head request_list; |
673a394b EA |
865 | } mm; |
866 | }; | |
867 | ||
79e53945 JB |
868 | enum intel_chip_family { |
869 | CHIP_I8XX = 0x01, | |
870 | CHIP_I9XX = 0x02, | |
871 | CHIP_I915 = 0x04, | |
872 | CHIP_I965 = 0x08, | |
873 | }; | |
874 | ||
c153f45f | 875 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 876 | extern int i915_max_ioctl; |
79e53945 | 877 | extern unsigned int i915_fbpercrtc; |
652c393a | 878 | extern unsigned int i915_powersave; |
33814341 | 879 | extern unsigned int i915_lvds_downclock; |
b3a83639 | 880 | |
6a9ee8af DA |
881 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
882 | extern int i915_resume(struct drm_device *dev); | |
1341d655 BG |
883 | extern void i915_save_display(struct drm_device *dev); |
884 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
885 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
886 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
887 | ||
1da177e4 | 888 | /* i915_dma.c */ |
84b1fd10 | 889 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 890 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 891 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 892 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 893 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
894 | extern void i915_driver_preclose(struct drm_device *dev, |
895 | struct drm_file *file_priv); | |
673a394b EA |
896 | extern void i915_driver_postclose(struct drm_device *dev, |
897 | struct drm_file *file_priv); | |
84b1fd10 | 898 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
899 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
900 | unsigned long arg); | |
673a394b | 901 | extern int i915_emit_box(struct drm_device *dev, |
201361a5 | 902 | struct drm_clip_rect *boxes, |
673a394b | 903 | int i, int DR1, int DR4); |
f803aa55 | 904 | extern int i915_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
905 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
906 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
907 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
908 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
909 | ||
af6061af | 910 | |
1da177e4 | 911 | /* i915_irq.c */ |
f65d9421 | 912 | void i915_hangcheck_elapsed(unsigned long data); |
c153f45f EA |
913 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
914 | struct drm_file *file_priv); | |
915 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
916 | struct drm_file *file_priv); | |
9d34e5db | 917 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno); |
79e53945 | 918 | extern void i915_enable_interrupt (struct drm_device *dev); |
1da177e4 LT |
919 | |
920 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 921 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 922 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 923 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
924 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
925 | struct drm_file *file_priv); | |
926 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
927 | struct drm_file *file_priv); | |
0a3e67a4 JB |
928 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
929 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
930 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 931 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
932 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
933 | struct drm_file *file_priv); | |
8ee1c3db | 934 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
62fdfeaf | 935 | extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask); |
8187a2b7 ZN |
936 | extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, |
937 | u32 mask); | |
938 | extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, | |
939 | u32 mask); | |
1da177e4 | 940 | |
7c463586 KP |
941 | void |
942 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
943 | ||
944 | void | |
945 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
946 | ||
01c66889 ZY |
947 | void intel_enable_asle (struct drm_device *dev); |
948 | ||
3bd3c932 CW |
949 | #ifdef CONFIG_DEBUG_FS |
950 | extern void i915_destroy_error_state(struct drm_device *dev); | |
951 | #else | |
952 | #define i915_destroy_error_state(x) | |
953 | #endif | |
954 | ||
7c463586 | 955 | |
1da177e4 | 956 | /* i915_mem.c */ |
c153f45f EA |
957 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
958 | struct drm_file *file_priv); | |
959 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
960 | struct drm_file *file_priv); | |
961 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
962 | struct drm_file *file_priv); | |
963 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
964 | struct drm_file *file_priv); | |
1da177e4 | 965 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 966 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 967 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b | 968 | /* i915_gem.c */ |
30dbf0c0 | 969 | int i915_gem_check_is_wedged(struct drm_device *dev); |
673a394b EA |
970 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
971 | struct drm_file *file_priv); | |
972 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
973 | struct drm_file *file_priv); | |
974 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
975 | struct drm_file *file_priv); | |
976 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
977 | struct drm_file *file_priv); | |
978 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
979 | struct drm_file *file_priv); | |
de151cf6 JB |
980 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
981 | struct drm_file *file_priv); | |
673a394b EA |
982 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
983 | struct drm_file *file_priv); | |
984 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
985 | struct drm_file *file_priv); | |
986 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
987 | struct drm_file *file_priv); | |
76446cac JB |
988 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
989 | struct drm_file *file_priv); | |
673a394b EA |
990 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
991 | struct drm_file *file_priv); | |
992 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
993 | struct drm_file *file_priv); | |
994 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
995 | struct drm_file *file_priv); | |
996 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
997 | struct drm_file *file_priv); | |
3ef94daa CW |
998 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
999 | struct drm_file *file_priv); | |
673a394b EA |
1000 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1001 | struct drm_file *file_priv); | |
1002 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1003 | struct drm_file *file_priv); | |
1004 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1005 | struct drm_file *file_priv); | |
1006 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1007 | struct drm_file *file_priv); | |
5a125c3c EA |
1008 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1009 | struct drm_file *file_priv); | |
673a394b | 1010 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1011 | int i915_gem_init_object(struct drm_gem_object *obj); |
ac52bc56 DV |
1012 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
1013 | size_t size); | |
673a394b EA |
1014 | void i915_gem_free_object(struct drm_gem_object *obj); |
1015 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); | |
1016 | void i915_gem_object_unpin(struct drm_gem_object *obj); | |
0f973f27 | 1017 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
d05ca301 | 1018 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
673a394b | 1019 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 CW |
1020 | |
1021 | /** | |
1022 | * Returns true if seq1 is later than seq2. | |
1023 | */ | |
1024 | static inline bool | |
1025 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1026 | { | |
1027 | return (int32_t)(seq1 - seq2) >= 0; | |
1028 | } | |
1029 | ||
2cf34d7b CW |
1030 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
1031 | bool interruptible); | |
1032 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj, | |
1033 | bool interruptible); | |
b09a1fec | 1034 | void i915_gem_retire_requests(struct drm_device *dev); |
069efc1d | 1035 | void i915_gem_reset(struct drm_device *dev); |
673a394b | 1036 | void i915_gem_clflush_object(struct drm_gem_object *obj); |
79e53945 JB |
1037 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
1038 | uint32_t read_domains, | |
1039 | uint32_t write_domain); | |
1040 | int i915_gem_init_ringbuffer(struct drm_device *dev); | |
1041 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
1042 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, | |
1043 | unsigned long end); | |
b47eb4a2 | 1044 | int i915_gpu_idle(struct drm_device *dev); |
5669fcac | 1045 | int i915_gem_idle(struct drm_device *dev); |
3cce469c CW |
1046 | int i915_add_request(struct drm_device *dev, |
1047 | struct drm_file *file_priv, | |
1048 | struct drm_i915_gem_request *request, | |
1049 | struct intel_ring_buffer *ring); | |
852835f3 | 1050 | int i915_do_wait_request(struct drm_device *dev, |
8a1a49f9 DV |
1051 | uint32_t seqno, |
1052 | bool interruptible, | |
1053 | struct intel_ring_buffer *ring); | |
de151cf6 | 1054 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
79e53945 JB |
1055 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
1056 | int write); | |
48b956c5 CW |
1057 | int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
1058 | bool pipelined); | |
71acb5eb | 1059 | int i915_gem_attach_phys_object(struct drm_device *dev, |
6eeefaf3 CW |
1060 | struct drm_gem_object *obj, |
1061 | int id, | |
1062 | int align); | |
71acb5eb DA |
1063 | void i915_gem_detach_phys_object(struct drm_device *dev, |
1064 | struct drm_gem_object *obj); | |
1065 | void i915_gem_free_all_phys_object(struct drm_device *dev); | |
1fd1c624 | 1066 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
673a394b | 1067 | |
31169714 CW |
1068 | void i915_gem_shrinker_init(void); |
1069 | void i915_gem_shrinker_exit(void); | |
1070 | ||
b47eb4a2 | 1071 | /* i915_gem_evict.c */ |
a6e0aa42 DV |
1072 | int i915_gem_evict_something(struct drm_device *dev, int min_size, |
1073 | unsigned alignment, bool mappable); | |
b47eb4a2 CW |
1074 | int i915_gem_evict_everything(struct drm_device *dev); |
1075 | int i915_gem_evict_inactive(struct drm_device *dev); | |
1076 | ||
673a394b EA |
1077 | /* i915_gem_tiling.c */ |
1078 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
280b713b EA |
1079 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
1080 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); | |
76446cac JB |
1081 | bool i915_tiling_ok(struct drm_device *dev, int stride, int size, |
1082 | int tiling_mode); | |
f590d279 OA |
1083 | bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, |
1084 | int tiling_mode); | |
673a394b EA |
1085 | |
1086 | /* i915_gem_debug.c */ | |
1087 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1088 | const char *where, uint32_t mark); | |
23bc5982 CW |
1089 | #if WATCH_LISTS |
1090 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1091 | #else |
23bc5982 | 1092 | #define i915_verify_lists(dev) 0 |
673a394b EA |
1093 | #endif |
1094 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
1095 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1096 | const char *where, uint32_t mark); | |
1da177e4 | 1097 | |
2017263e | 1098 | /* i915_debugfs.c */ |
27c202ad BG |
1099 | int i915_debugfs_init(struct drm_minor *minor); |
1100 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1101 | |
317c35d1 JB |
1102 | /* i915_suspend.c */ |
1103 | extern int i915_save_state(struct drm_device *dev); | |
1104 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1105 | |
1106 | /* i915_suspend.c */ | |
1107 | extern int i915_save_state(struct drm_device *dev); | |
1108 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1109 | |
f899fc64 CW |
1110 | /* intel_i2c.c */ |
1111 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1112 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
e957d772 CW |
1113 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1114 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1115 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1116 | { | |
1117 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1118 | } | |
f899fc64 CW |
1119 | extern void intel_i2c_reset(struct drm_device *dev); |
1120 | ||
3b617967 | 1121 | /* intel_opregion.c */ |
44834a67 CW |
1122 | extern int intel_opregion_setup(struct drm_device *dev); |
1123 | #ifdef CONFIG_ACPI | |
1124 | extern void intel_opregion_init(struct drm_device *dev); | |
1125 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1126 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1127 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1128 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1129 | #else |
44834a67 CW |
1130 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1131 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1132 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1133 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1134 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1135 | #endif |
8ee1c3db | 1136 | |
723bfd70 JB |
1137 | /* intel_acpi.c */ |
1138 | #ifdef CONFIG_ACPI | |
1139 | extern void intel_register_dsm_handler(void); | |
1140 | extern void intel_unregister_dsm_handler(void); | |
1141 | #else | |
1142 | static inline void intel_register_dsm_handler(void) { return; } | |
1143 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1144 | #endif /* CONFIG_ACPI */ | |
1145 | ||
79e53945 JB |
1146 | /* modesetting */ |
1147 | extern void intel_modeset_init(struct drm_device *dev); | |
1148 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
28d52043 | 1149 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
80824003 | 1150 | extern void i8xx_disable_fbc(struct drm_device *dev); |
74dff282 | 1151 | extern void g4x_disable_fbc(struct drm_device *dev); |
b52eb4dc | 1152 | extern void ironlake_disable_fbc(struct drm_device *dev); |
ee5382ae AJ |
1153 | extern void intel_disable_fbc(struct drm_device *dev); |
1154 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
1155 | extern bool intel_fbc_enabled(struct drm_device *dev); | |
7648fa99 | 1156 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
3bad0781 | 1157 | extern void intel_detect_pch (struct drm_device *dev); |
e3421a18 | 1158 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
3bad0781 | 1159 | |
6ef3d427 | 1160 | /* overlay */ |
3bd3c932 | 1161 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1162 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1163 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
3bd3c932 | 1164 | #endif |
6ef3d427 | 1165 | |
546b0974 EA |
1166 | /** |
1167 | * Lock test for when it's just for synchronization of ring access. | |
1168 | * | |
1169 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1170 | * has access to the ring. | |
1171 | */ | |
1172 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
8187a2b7 ZN |
1173 | if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \ |
1174 | == NULL) \ | |
546b0974 EA |
1175 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ |
1176 | } while (0) | |
1177 | ||
be282fd4 JB |
1178 | static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg) |
1179 | { | |
1180 | u32 val; | |
1181 | ||
1182 | val = readl(dev_priv->regs + reg); | |
1183 | if (dev_priv->debug_flags & I915_DEBUG_READ) | |
1184 | printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg); | |
1185 | return val; | |
1186 | } | |
1187 | ||
1188 | static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, | |
1189 | u32 val) | |
1190 | { | |
1191 | writel(val, dev_priv->regs + reg); | |
1192 | if (dev_priv->debug_flags & I915_DEBUG_WRITE) | |
1193 | printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg); | |
1194 | } | |
1195 | ||
1196 | #define I915_READ(reg) i915_read(dev_priv, (reg)) | |
1197 | #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val)) | |
3043c60c EA |
1198 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) |
1199 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) | |
1200 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) | |
1201 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) | |
de151cf6 | 1202 | #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) |
049ef7e4 | 1203 | #define I915_READ64(reg) readq(dev_priv->regs + (reg)) |
7d57382e | 1204 | #define POSTING_READ(reg) (void)I915_READ(reg) |
7648fa99 | 1205 | #define POSTING_READ16(reg) (void)I915_READ16(reg) |
1da177e4 | 1206 | |
be282fd4 JB |
1207 | #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \ |
1208 | I915_DEBUG_WRITE) | |
1209 | #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \ | |
1210 | I915_DEBUG_WRITE)) | |
1211 | ||
e1f99ce6 CW |
1212 | #define BEGIN_LP_RING(n) \ |
1213 | intel_ring_begin(&dev_priv->render_ring, (n)) | |
1da177e4 | 1214 | |
e1f99ce6 CW |
1215 | #define OUT_RING(x) \ |
1216 | intel_ring_emit(&dev_priv->render_ring, x) | |
1da177e4 | 1217 | |
e1f99ce6 CW |
1218 | #define ADVANCE_LP_RING() \ |
1219 | intel_ring_advance(&dev_priv->render_ring) | |
1da177e4 | 1220 | |
ba8bbcf6 | 1221 | /** |
585fb111 JB |
1222 | * Reads a dword out of the status page, which is written to from the command |
1223 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
1224 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 1225 | * |
585fb111 | 1226 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
1227 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
1228 | * 0x04: ring 0 head pointer | |
1229 | * 0x05: ring 1 head pointer (915-class) | |
1230 | * 0x06: ring 2 head pointer (915-class) | |
1231 | * 0x10-0x1b: Context status DWords (GM45) | |
1232 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 1233 | * |
0cdad7e8 | 1234 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 1235 | */ |
8187a2b7 ZN |
1236 | #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\ |
1237 | (dev_priv->render_ring.status_page.page_addr))[reg]) | |
0baf823a | 1238 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 1239 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 1240 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 1241 | |
cfdf1fa2 KH |
1242 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1243 | ||
1244 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1245 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
5ce8ba7c | 1246 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
cfdf1fa2 | 1247 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
cfdf1fa2 KH |
1248 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
1249 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1250 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1251 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
534843da CW |
1252 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
1253 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
cfdf1fa2 KH |
1254 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
1255 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1256 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1257 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1258 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1259 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
f2b115e6 AJ |
1260 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
1261 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
cfdf1fa2 | 1262 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ba8bbcf6 | 1263 | |
c96c3a8c CW |
1264 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1265 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1266 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1267 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1268 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
bad720ff | 1269 | |
92f49d9c | 1270 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
549f7365 | 1271 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
cfdf1fa2 | 1272 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
ba8bbcf6 | 1273 | |
31578148 CW |
1274 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
1275 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) | |
1276 | ||
0f973f27 JB |
1277 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1278 | * rows, which changed the alignment requirements and fence programming. | |
1279 | */ | |
a6c45cf0 | 1280 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
0f973f27 | 1281 | IS_I915GM(dev))) |
a6c45cf0 | 1282 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
f00a3ddf CW |
1283 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
1284 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
f2b115e6 | 1285 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
a6c45cf0 | 1286 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
cfdf1fa2 | 1287 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
7662c8bd | 1288 | /* dsparb controlled by hw only */ |
f2b115e6 | 1289 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
b39d50e5 | 1290 | |
a6c45cf0 | 1291 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
cfdf1fa2 KH |
1292 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
1293 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
1294 | #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) | |
652c393a | 1295 | |
f00a3ddf CW |
1296 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev)) |
1297 | #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev)) | |
bad720ff | 1298 | |
3bad0781 ZW |
1299 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
1300 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
1301 | ||
ba8bbcf6 | 1302 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 1303 | |
1da177e4 | 1304 | #endif |