Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 39 | #include <drm/intel-gtt.h> |
aaa6fd2a | 40 | #include <linux/backlight.h> |
585fb111 | 41 | |
1da177e4 LT |
42 | /* General customization: |
43 | */ | |
44 | ||
45 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
46 | ||
47 | #define DRIVER_NAME "i915" | |
48 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 49 | #define DRIVER_DATE "20080730" |
1da177e4 | 50 | |
317c35d1 JB |
51 | enum pipe { |
52 | PIPE_A = 0, | |
53 | PIPE_B, | |
9db4a9c7 JB |
54 | PIPE_C, |
55 | I915_MAX_PIPES | |
317c35d1 | 56 | }; |
9db4a9c7 | 57 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 58 | |
80824003 JB |
59 | enum plane { |
60 | PLANE_A = 0, | |
61 | PLANE_B, | |
9db4a9c7 | 62 | PLANE_C, |
80824003 | 63 | }; |
9db4a9c7 | 64 | #define plane_name(p) ((p) + 'A') |
52440211 | 65 | |
62fdfeaf EA |
66 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
67 | ||
9db4a9c7 JB |
68 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
69 | ||
1da177e4 LT |
70 | /* Interface history: |
71 | * | |
72 | * 1.1: Original. | |
0d6aa60b DA |
73 | * 1.2: Add Power Management |
74 | * 1.3: Add vblank support | |
de227f5f | 75 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 76 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
77 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
78 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
79 | */ |
80 | #define DRIVER_MAJOR 1 | |
2228ed67 | 81 | #define DRIVER_MINOR 6 |
1da177e4 LT |
82 | #define DRIVER_PATCHLEVEL 0 |
83 | ||
673a394b | 84 | #define WATCH_COHERENCY 0 |
23bc5982 | 85 | #define WATCH_LISTS 0 |
673a394b | 86 | |
71acb5eb DA |
87 | #define I915_GEM_PHYS_CURSOR_0 1 |
88 | #define I915_GEM_PHYS_CURSOR_1 2 | |
89 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
90 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
91 | ||
92 | struct drm_i915_gem_phys_object { | |
93 | int id; | |
94 | struct page **page_list; | |
95 | drm_dma_handle_t *handle; | |
05394f39 | 96 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
97 | }; |
98 | ||
1da177e4 LT |
99 | struct mem_block { |
100 | struct mem_block *next; | |
101 | struct mem_block *prev; | |
102 | int start; | |
103 | int size; | |
6c340eac | 104 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
105 | }; |
106 | ||
0a3e67a4 JB |
107 | struct opregion_header; |
108 | struct opregion_acpi; | |
109 | struct opregion_swsci; | |
110 | struct opregion_asle; | |
8d715f00 | 111 | struct drm_i915_private; |
0a3e67a4 | 112 | |
8ee1c3db MG |
113 | struct intel_opregion { |
114 | struct opregion_header *header; | |
115 | struct opregion_acpi *acpi; | |
116 | struct opregion_swsci *swsci; | |
117 | struct opregion_asle *asle; | |
44834a67 | 118 | void *vbt; |
01fe9dbd | 119 | u32 __iomem *lid_state; |
8ee1c3db | 120 | }; |
44834a67 | 121 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 122 | |
6ef3d427 CW |
123 | struct intel_overlay; |
124 | struct intel_overlay_error_state; | |
125 | ||
7c1c2871 DA |
126 | struct drm_i915_master_private { |
127 | drm_local_map_t *sarea; | |
128 | struct _drm_i915_sarea *sarea_priv; | |
129 | }; | |
de151cf6 | 130 | #define I915_FENCE_REG_NONE -1 |
4b9de737 DV |
131 | #define I915_MAX_NUM_FENCES 16 |
132 | /* 16 fences + sign bit for FENCE_REG_NONE */ | |
133 | #define I915_MAX_NUM_FENCE_BITS 5 | |
de151cf6 JB |
134 | |
135 | struct drm_i915_fence_reg { | |
007cc8ac | 136 | struct list_head lru_list; |
caea7476 | 137 | struct drm_i915_gem_object *obj; |
d9e86c0e | 138 | uint32_t setup_seqno; |
1690e1eb | 139 | int pin_count; |
de151cf6 | 140 | }; |
7c1c2871 | 141 | |
9b9d172d | 142 | struct sdvo_device_mapping { |
e957d772 | 143 | u8 initialized; |
9b9d172d | 144 | u8 dvo_port; |
145 | u8 slave_addr; | |
146 | u8 dvo_wiring; | |
e957d772 | 147 | u8 i2c_pin; |
b1083333 | 148 | u8 ddc_pin; |
9b9d172d | 149 | }; |
150 | ||
c4a1d9e4 CW |
151 | struct intel_display_error_state; |
152 | ||
63eeaf38 JB |
153 | struct drm_i915_error_state { |
154 | u32 eir; | |
155 | u32 pgtbl_er; | |
9db4a9c7 | 156 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
157 | u32 tail[I915_NUM_RINGS]; |
158 | u32 head[I915_NUM_RINGS]; | |
d27b1e0e DV |
159 | u32 ipeir[I915_NUM_RINGS]; |
160 | u32 ipehr[I915_NUM_RINGS]; | |
161 | u32 instdone[I915_NUM_RINGS]; | |
162 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 DV |
163 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
164 | /* our own tracking of ring head and tail */ | |
165 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
166 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 167 | u32 error; /* gen6+ */ |
c1cd90ed DV |
168 | u32 instpm[I915_NUM_RINGS]; |
169 | u32 instps[I915_NUM_RINGS]; | |
63eeaf38 | 170 | u32 instdone1; |
d27b1e0e | 171 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 172 | u64 bbaddr; |
33f3f518 DV |
173 | u32 fault_reg[I915_NUM_RINGS]; |
174 | u32 done_reg; | |
c1cd90ed | 175 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 176 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 177 | struct timeval time; |
52d39a21 CW |
178 | struct drm_i915_error_ring { |
179 | struct drm_i915_error_object { | |
180 | int page_count; | |
181 | u32 gtt_offset; | |
182 | u32 *pages[0]; | |
183 | } *ringbuffer, *batchbuffer; | |
184 | struct drm_i915_error_request { | |
185 | long jiffies; | |
186 | u32 seqno; | |
ee4f42b1 | 187 | u32 tail; |
52d39a21 CW |
188 | } *requests; |
189 | int num_requests; | |
190 | } ring[I915_NUM_RINGS]; | |
9df30794 | 191 | struct drm_i915_error_buffer { |
a779e5ab | 192 | u32 size; |
9df30794 CW |
193 | u32 name; |
194 | u32 seqno; | |
195 | u32 gtt_offset; | |
196 | u32 read_domains; | |
197 | u32 write_domain; | |
4b9de737 | 198 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
199 | s32 pinned:2; |
200 | u32 tiling:2; | |
201 | u32 dirty:1; | |
202 | u32 purgeable:1; | |
5d1333fc | 203 | s32 ring:4; |
93dfb40c | 204 | u32 cache_level:2; |
c724e8a9 CW |
205 | } *active_bo, *pinned_bo; |
206 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 207 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 208 | struct intel_display_error_state *display; |
63eeaf38 JB |
209 | }; |
210 | ||
e70236a8 JB |
211 | struct drm_i915_display_funcs { |
212 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 213 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
214 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
215 | void (*disable_fbc)(struct drm_device *dev); | |
216 | int (*get_display_clock_speed)(struct drm_device *dev); | |
217 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 218 | void (*update_wm)(struct drm_device *dev); |
b840d907 JB |
219 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
220 | uint32_t sprite_width, int pixel_size); | |
f564048e EA |
221 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
222 | struct drm_display_mode *mode, | |
223 | struct drm_display_mode *adjusted_mode, | |
224 | int x, int y, | |
225 | struct drm_framebuffer *old_fb); | |
e0dac65e WF |
226 | void (*write_eld)(struct drm_connector *connector, |
227 | struct drm_crtc *crtc); | |
674cf967 | 228 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 229 | void (*init_clock_gating)(struct drm_device *dev); |
645c62a5 | 230 | void (*init_pch_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
231 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
232 | struct drm_framebuffer *fb, | |
233 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
234 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
235 | int x, int y); | |
8d715f00 KP |
236 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
237 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
e70236a8 JB |
238 | /* clock updates for mode set */ |
239 | /* cursor updates */ | |
240 | /* render clock increase/decrease */ | |
241 | /* display clock increase/decrease */ | |
242 | /* pll clock increase/decrease */ | |
e70236a8 JB |
243 | }; |
244 | ||
cfdf1fa2 | 245 | struct intel_device_info { |
c96c3a8c | 246 | u8 gen; |
0206e353 AJ |
247 | u8 is_mobile:1; |
248 | u8 is_i85x:1; | |
249 | u8 is_i915g:1; | |
250 | u8 is_i945gm:1; | |
251 | u8 is_g33:1; | |
252 | u8 need_gfx_hws:1; | |
253 | u8 is_g4x:1; | |
254 | u8 is_pineview:1; | |
255 | u8 is_broadwater:1; | |
256 | u8 is_crestline:1; | |
257 | u8 is_ivybridge:1; | |
258 | u8 has_fbc:1; | |
259 | u8 has_pipe_cxsr:1; | |
260 | u8 has_hotplug:1; | |
261 | u8 cursor_needs_physical:1; | |
262 | u8 has_overlay:1; | |
263 | u8 overlay_needs_physical:1; | |
264 | u8 supports_tv:1; | |
265 | u8 has_bsd_ring:1; | |
266 | u8 has_blt_ring:1; | |
3d29b842 | 267 | u8 has_llc:1; |
cfdf1fa2 KH |
268 | }; |
269 | ||
1d2a314c DV |
270 | #define I915_PPGTT_PD_ENTRIES 512 |
271 | #define I915_PPGTT_PT_ENTRIES 1024 | |
272 | struct i915_hw_ppgtt { | |
273 | unsigned num_pd_entries; | |
274 | struct page **pt_pages; | |
275 | uint32_t pd_offset; | |
276 | dma_addr_t *pt_dma_addr; | |
277 | dma_addr_t scratch_page_dma_addr; | |
278 | }; | |
279 | ||
b5e50c3f | 280 | enum no_fbc_reason { |
bed4a673 | 281 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
282 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
283 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
284 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
285 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
286 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 287 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 288 | FBC_MODULE_PARAM, |
b5e50c3f JB |
289 | }; |
290 | ||
3bad0781 ZW |
291 | enum intel_pch { |
292 | PCH_IBX, /* Ibexpeak PCH */ | |
293 | PCH_CPT, /* Cougarpoint PCH */ | |
294 | }; | |
295 | ||
b690e96c | 296 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 297 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 298 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 299 | |
8be48d92 | 300 | struct intel_fbdev; |
1630fe75 | 301 | struct intel_fbc_work; |
38651674 | 302 | |
c2b9152f DV |
303 | struct intel_gmbus { |
304 | struct i2c_adapter adapter; | |
f6f808c8 DV |
305 | bool force_bit; |
306 | bool has_gpio; | |
c2b9152f | 307 | u32 reg0; |
36c785f0 | 308 | u32 gpio_reg; |
c167a6fc | 309 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
310 | struct drm_i915_private *dev_priv; |
311 | }; | |
312 | ||
1da177e4 | 313 | typedef struct drm_i915_private { |
673a394b EA |
314 | struct drm_device *dev; |
315 | ||
cfdf1fa2 KH |
316 | const struct intel_device_info *info; |
317 | ||
ac5c4e76 | 318 | int has_gem; |
72bfa19c | 319 | int relative_constants_mode; |
ac5c4e76 | 320 | |
3043c60c | 321 | void __iomem *regs; |
9f1f46a4 DV |
322 | /** gt_fifo_count and the subsequent register write are synchronized |
323 | * with dev->struct_mutex. */ | |
324 | unsigned gt_fifo_count; | |
325 | /** forcewake_count is protected by gt_lock */ | |
326 | unsigned forcewake_count; | |
327 | /** gt_lock is also taken in irq contexts. */ | |
328 | struct spinlock gt_lock; | |
1da177e4 | 329 | |
c2b9152f | 330 | struct intel_gmbus *gmbus; |
f899fc64 | 331 | |
8a8ed1f5 YS |
332 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
333 | * controller on different i2c buses. */ | |
334 | struct mutex gmbus_mutex; | |
335 | ||
ec2a4c3f | 336 | struct pci_dev *bridge_dev; |
1ec14ad3 | 337 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
6f392d54 | 338 | uint32_t next_seqno; |
1da177e4 | 339 | |
9c8da5eb | 340 | drm_dma_handle_t *status_page_dmah; |
0a3e67a4 | 341 | uint32_t counter; |
dc7a9319 | 342 | drm_local_map_t hws_map; |
05394f39 CW |
343 | struct drm_i915_gem_object *pwrctx; |
344 | struct drm_i915_gem_object *renderctx; | |
1da177e4 | 345 | |
d7658989 JB |
346 | struct resource mch_res; |
347 | ||
a6b54f3f | 348 | unsigned int cpp; |
1da177e4 LT |
349 | int back_offset; |
350 | int front_offset; | |
351 | int current_page; | |
352 | int page_flipping; | |
1da177e4 | 353 | |
1da177e4 | 354 | atomic_t irq_received; |
1ec14ad3 CW |
355 | |
356 | /* protects the irq masks */ | |
357 | spinlock_t irq_lock; | |
ed4cb414 | 358 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
7c463586 | 359 | u32 pipestat[2]; |
1ec14ad3 CW |
360 | u32 irq_mask; |
361 | u32 gt_irq_mask; | |
362 | u32 pch_irq_mask; | |
1da177e4 | 363 | |
5ca58282 JB |
364 | u32 hotplug_supported_mask; |
365 | struct work_struct hotplug_work; | |
366 | ||
1da177e4 LT |
367 | int tex_lru_log_granularity; |
368 | int allow_batchbuffer; | |
0d6aa60b | 369 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 370 | int vblank_pipe; |
a3524f1b | 371 | int num_pipe; |
a6b54f3f | 372 | |
f65d9421 | 373 | /* For hangcheck timer */ |
576ae4b8 | 374 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
f65d9421 BG |
375 | struct timer_list hangcheck_timer; |
376 | int hangcheck_count; | |
377 | uint32_t last_acthd; | |
097354eb DV |
378 | uint32_t last_acthd_bsd; |
379 | uint32_t last_acthd_blt; | |
cbb465e7 CW |
380 | uint32_t last_instdone; |
381 | uint32_t last_instdone1; | |
f65d9421 | 382 | |
80824003 | 383 | unsigned long cfb_size; |
016b9b61 CW |
384 | unsigned int cfb_fb; |
385 | enum plane cfb_plane; | |
bed4a673 | 386 | int cfb_y; |
1630fe75 | 387 | struct intel_fbc_work *fbc_work; |
80824003 | 388 | |
8ee1c3db MG |
389 | struct intel_opregion opregion; |
390 | ||
02e792fb DV |
391 | /* overlay */ |
392 | struct intel_overlay *overlay; | |
b840d907 | 393 | bool sprite_scaling_enabled; |
02e792fb | 394 | |
79e53945 | 395 | /* LVDS info */ |
a9573556 | 396 | int backlight_level; /* restore backlight to this value */ |
47356eb6 | 397 | bool backlight_enabled; |
88631706 ML |
398 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
399 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
400 | |
401 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
402 | unsigned int int_tv_support:1; |
403 | unsigned int lvds_dither:1; | |
404 | unsigned int lvds_vbt:1; | |
405 | unsigned int int_crt_support:1; | |
43565a06 | 406 | unsigned int lvds_use_ssc:1; |
abd06860 | 407 | unsigned int display_clock_mode:1; |
43565a06 | 408 | int lvds_ssc_freq; |
b0354385 TI |
409 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
410 | unsigned int lvds_val; /* used for checking LVDS channel mode */ | |
5ceb0f9b | 411 | struct { |
9f0e7ff4 JB |
412 | int rate; |
413 | int lanes; | |
414 | int preemphasis; | |
415 | int vswing; | |
416 | ||
417 | bool initialized; | |
418 | bool support; | |
419 | int bpp; | |
420 | struct edp_power_seq pps; | |
5ceb0f9b | 421 | } edp; |
89667383 | 422 | bool no_aux_handshake; |
79e53945 | 423 | |
c1c7af60 JB |
424 | struct notifier_block lid_notifier; |
425 | ||
f899fc64 | 426 | int crt_ddc_pin; |
4b9de737 | 427 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
de151cf6 JB |
428 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
429 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
430 | ||
95534263 | 431 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 432 | |
63eeaf38 JB |
433 | spinlock_t error_lock; |
434 | struct drm_i915_error_state *first_error; | |
8a905236 | 435 | struct work_struct error_work; |
30dbf0c0 | 436 | struct completion error_completion; |
9c9fe1f8 | 437 | struct workqueue_struct *wq; |
63eeaf38 | 438 | |
e70236a8 JB |
439 | /* Display functions */ |
440 | struct drm_i915_display_funcs display; | |
441 | ||
3bad0781 ZW |
442 | /* PCH chipset type */ |
443 | enum intel_pch pch_type; | |
444 | ||
b690e96c JB |
445 | unsigned long quirks; |
446 | ||
ba8bbcf6 | 447 | /* Register state */ |
c9354c85 | 448 | bool modeset_on_lid; |
ba8bbcf6 JB |
449 | u8 saveLBB; |
450 | u32 saveDSPACNTR; | |
451 | u32 saveDSPBCNTR; | |
e948e994 | 452 | u32 saveDSPARB; |
968b503e | 453 | u32 saveHWS; |
ba8bbcf6 JB |
454 | u32 savePIPEACONF; |
455 | u32 savePIPEBCONF; | |
456 | u32 savePIPEASRC; | |
457 | u32 savePIPEBSRC; | |
458 | u32 saveFPA0; | |
459 | u32 saveFPA1; | |
460 | u32 saveDPLL_A; | |
461 | u32 saveDPLL_A_MD; | |
462 | u32 saveHTOTAL_A; | |
463 | u32 saveHBLANK_A; | |
464 | u32 saveHSYNC_A; | |
465 | u32 saveVTOTAL_A; | |
466 | u32 saveVBLANK_A; | |
467 | u32 saveVSYNC_A; | |
468 | u32 saveBCLRPAT_A; | |
5586c8bc | 469 | u32 saveTRANSACONF; |
42048781 ZW |
470 | u32 saveTRANS_HTOTAL_A; |
471 | u32 saveTRANS_HBLANK_A; | |
472 | u32 saveTRANS_HSYNC_A; | |
473 | u32 saveTRANS_VTOTAL_A; | |
474 | u32 saveTRANS_VBLANK_A; | |
475 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 476 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
477 | u32 saveDSPASTRIDE; |
478 | u32 saveDSPASIZE; | |
479 | u32 saveDSPAPOS; | |
585fb111 | 480 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
481 | u32 saveDSPASURF; |
482 | u32 saveDSPATILEOFF; | |
483 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 484 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
485 | u32 saveBLC_PWM_CTL; |
486 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
487 | u32 saveBLC_CPU_PWM_CTL; |
488 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
489 | u32 saveFPB0; |
490 | u32 saveFPB1; | |
491 | u32 saveDPLL_B; | |
492 | u32 saveDPLL_B_MD; | |
493 | u32 saveHTOTAL_B; | |
494 | u32 saveHBLANK_B; | |
495 | u32 saveHSYNC_B; | |
496 | u32 saveVTOTAL_B; | |
497 | u32 saveVBLANK_B; | |
498 | u32 saveVSYNC_B; | |
499 | u32 saveBCLRPAT_B; | |
5586c8bc | 500 | u32 saveTRANSBCONF; |
42048781 ZW |
501 | u32 saveTRANS_HTOTAL_B; |
502 | u32 saveTRANS_HBLANK_B; | |
503 | u32 saveTRANS_HSYNC_B; | |
504 | u32 saveTRANS_VTOTAL_B; | |
505 | u32 saveTRANS_VBLANK_B; | |
506 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 507 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
508 | u32 saveDSPBSTRIDE; |
509 | u32 saveDSPBSIZE; | |
510 | u32 saveDSPBPOS; | |
585fb111 | 511 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
512 | u32 saveDSPBSURF; |
513 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
514 | u32 saveVGA0; |
515 | u32 saveVGA1; | |
516 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
517 | u32 saveVGACNTRL; |
518 | u32 saveADPA; | |
519 | u32 saveLVDS; | |
585fb111 JB |
520 | u32 savePP_ON_DELAYS; |
521 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
522 | u32 saveDVOA; |
523 | u32 saveDVOB; | |
524 | u32 saveDVOC; | |
525 | u32 savePP_ON; | |
526 | u32 savePP_OFF; | |
527 | u32 savePP_CONTROL; | |
585fb111 | 528 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
529 | u32 savePFIT_CONTROL; |
530 | u32 save_palette_a[256]; | |
531 | u32 save_palette_b[256]; | |
06027f91 | 532 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
533 | u32 saveFBC_CFB_BASE; |
534 | u32 saveFBC_LL_BASE; | |
535 | u32 saveFBC_CONTROL; | |
536 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
537 | u32 saveIER; |
538 | u32 saveIIR; | |
539 | u32 saveIMR; | |
42048781 ZW |
540 | u32 saveDEIER; |
541 | u32 saveDEIMR; | |
542 | u32 saveGTIER; | |
543 | u32 saveGTIMR; | |
544 | u32 saveFDI_RXA_IMR; | |
545 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 546 | u32 saveCACHE_MODE_0; |
1f84e550 | 547 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
548 | u32 saveSWF0[16]; |
549 | u32 saveSWF1[16]; | |
550 | u32 saveSWF2[3]; | |
551 | u8 saveMSR; | |
552 | u8 saveSR[8]; | |
123f794f | 553 | u8 saveGR[25]; |
ba8bbcf6 | 554 | u8 saveAR_INDEX; |
a59e122a | 555 | u8 saveAR[21]; |
ba8bbcf6 | 556 | u8 saveDACMASK; |
a59e122a | 557 | u8 saveCR[37]; |
4b9de737 | 558 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
559 | u32 saveCURACNTR; |
560 | u32 saveCURAPOS; | |
561 | u32 saveCURABASE; | |
562 | u32 saveCURBCNTR; | |
563 | u32 saveCURBPOS; | |
564 | u32 saveCURBBASE; | |
565 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
566 | u32 saveDP_B; |
567 | u32 saveDP_C; | |
568 | u32 saveDP_D; | |
569 | u32 savePIPEA_GMCH_DATA_M; | |
570 | u32 savePIPEB_GMCH_DATA_M; | |
571 | u32 savePIPEA_GMCH_DATA_N; | |
572 | u32 savePIPEB_GMCH_DATA_N; | |
573 | u32 savePIPEA_DP_LINK_M; | |
574 | u32 savePIPEB_DP_LINK_M; | |
575 | u32 savePIPEA_DP_LINK_N; | |
576 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
577 | u32 saveFDI_RXA_CTL; |
578 | u32 saveFDI_TXA_CTL; | |
579 | u32 saveFDI_RXB_CTL; | |
580 | u32 saveFDI_TXB_CTL; | |
581 | u32 savePFA_CTL_1; | |
582 | u32 savePFB_CTL_1; | |
583 | u32 savePFA_WIN_SZ; | |
584 | u32 savePFB_WIN_SZ; | |
585 | u32 savePFA_WIN_POS; | |
586 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
587 | u32 savePCH_DREF_CONTROL; |
588 | u32 saveDISP_ARB_CTL; | |
589 | u32 savePIPEA_DATA_M1; | |
590 | u32 savePIPEA_DATA_N1; | |
591 | u32 savePIPEA_LINK_M1; | |
592 | u32 savePIPEA_LINK_N1; | |
593 | u32 savePIPEB_DATA_M1; | |
594 | u32 savePIPEB_DATA_N1; | |
595 | u32 savePIPEB_LINK_M1; | |
596 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 597 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 598 | u32 savePCH_PORT_HOTPLUG; |
673a394b EA |
599 | |
600 | struct { | |
19966754 | 601 | /** Bridge to intel-gtt-ko */ |
c64f7ba5 | 602 | const struct intel_gtt *gtt; |
19966754 | 603 | /** Memory allocator for GTT stolen memory */ |
fe669bf8 | 604 | struct drm_mm stolen; |
19966754 | 605 | /** Memory allocator for GTT */ |
673a394b | 606 | struct drm_mm gtt_space; |
93a37f20 DV |
607 | /** List of all objects in gtt_space. Used to restore gtt |
608 | * mappings on resume */ | |
609 | struct list_head gtt_list; | |
bee4a186 CW |
610 | |
611 | /** Usable portion of the GTT for GEM */ | |
612 | unsigned long gtt_start; | |
a6e0aa42 | 613 | unsigned long gtt_mappable_end; |
bee4a186 | 614 | unsigned long gtt_end; |
673a394b | 615 | |
0839ccb8 | 616 | struct io_mapping *gtt_mapping; |
ab657db1 | 617 | int gtt_mtrr; |
0839ccb8 | 618 | |
1d2a314c DV |
619 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
620 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
621 | ||
17250b71 | 622 | struct shrinker inactive_shrinker; |
31169714 | 623 | |
69dc4987 CW |
624 | /** |
625 | * List of objects currently involved in rendering. | |
626 | * | |
627 | * Includes buffers having the contents of their GPU caches | |
628 | * flushed, not necessarily primitives. last_rendering_seqno | |
629 | * represents when the rendering involved will be completed. | |
630 | * | |
631 | * A reference is held on the buffer while on this list. | |
632 | */ | |
633 | struct list_head active_list; | |
634 | ||
673a394b EA |
635 | /** |
636 | * List of objects which are not in the ringbuffer but which | |
637 | * still have a write_domain which needs to be flushed before | |
638 | * unbinding. | |
639 | * | |
ce44b0ea EA |
640 | * last_rendering_seqno is 0 while an object is in this list. |
641 | * | |
673a394b EA |
642 | * A reference is held on the buffer while on this list. |
643 | */ | |
644 | struct list_head flushing_list; | |
645 | ||
646 | /** | |
647 | * LRU list of objects which are not in the ringbuffer and | |
648 | * are ready to unbind, but are still in the GTT. | |
649 | * | |
ce44b0ea EA |
650 | * last_rendering_seqno is 0 while an object is in this list. |
651 | * | |
673a394b EA |
652 | * A reference is not held on the buffer while on this list, |
653 | * as merely being GTT-bound shouldn't prevent its being | |
654 | * freed, and we'll pull it off the list in the free path. | |
655 | */ | |
656 | struct list_head inactive_list; | |
657 | ||
f13d3f73 CW |
658 | /** |
659 | * LRU list of objects which are not in the ringbuffer but | |
660 | * are still pinned in the GTT. | |
661 | */ | |
662 | struct list_head pinned_list; | |
663 | ||
a09ba7fa EA |
664 | /** LRU list of objects with fence regs on them. */ |
665 | struct list_head fence_list; | |
666 | ||
be72615b CW |
667 | /** |
668 | * List of objects currently pending being freed. | |
669 | * | |
670 | * These objects are no longer in use, but due to a signal | |
671 | * we were prevented from freeing them at the appointed time. | |
672 | */ | |
673 | struct list_head deferred_free_list; | |
674 | ||
673a394b EA |
675 | /** |
676 | * We leave the user IRQ off as much as possible, | |
677 | * but this means that requests will finish and never | |
678 | * be retired once the system goes idle. Set a timer to | |
679 | * fire periodically while the ring is running. When it | |
680 | * fires, go retire requests. | |
681 | */ | |
682 | struct delayed_work retire_work; | |
683 | ||
ce453d81 CW |
684 | /** |
685 | * Are we in a non-interruptible section of code like | |
686 | * modesetting? | |
687 | */ | |
688 | bool interruptible; | |
689 | ||
673a394b EA |
690 | /** |
691 | * Flag if the X Server, and thus DRM, is not currently in | |
692 | * control of the device. | |
693 | * | |
694 | * This is set between LeaveVT and EnterVT. It needs to be | |
695 | * replaced with a semaphore. It also needs to be | |
696 | * transitioned away from for kernel modesetting. | |
697 | */ | |
698 | int suspended; | |
699 | ||
700 | /** | |
701 | * Flag if the hardware appears to be wedged. | |
702 | * | |
703 | * This is set when attempts to idle the device timeout. | |
25985edc | 704 | * It prevents command submission from occurring and makes |
673a394b EA |
705 | * every pending request fail |
706 | */ | |
ba1234d1 | 707 | atomic_t wedged; |
673a394b EA |
708 | |
709 | /** Bit 6 swizzling required for X tiling */ | |
710 | uint32_t bit_6_swizzle_x; | |
711 | /** Bit 6 swizzling required for Y tiling */ | |
712 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
713 | |
714 | /* storage for physical objects */ | |
715 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 716 | |
73aa808f | 717 | /* accounting, useful for userland debugging */ |
73aa808f | 718 | size_t gtt_total; |
6299f992 CW |
719 | size_t mappable_gtt_total; |
720 | size_t object_memory; | |
73aa808f | 721 | u32 object_count; |
673a394b | 722 | } mm; |
9b9d172d | 723 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
724 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
725 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
726 | /* Panel fitter placement and size for Ironlake+ */ |
727 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 728 | |
27f8227b JB |
729 | struct drm_crtc *plane_to_crtc_mapping[3]; |
730 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 | 731 | wait_queue_head_t pending_flip_queue; |
1afe3e9d | 732 | bool flip_pending_is_done; |
6b95a207 | 733 | |
652c393a JB |
734 | /* Reclocking support */ |
735 | bool render_reclock_avail; | |
736 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
737 | /* indicates the reduced downclock for LVDS*/ |
738 | int lvds_downclock; | |
652c393a JB |
739 | struct work_struct idle_work; |
740 | struct timer_list idle_timer; | |
741 | bool busy; | |
742 | u16 orig_clock; | |
6363ee6f ZY |
743 | int child_dev_num; |
744 | struct child_device_config *child_dev; | |
a2565377 | 745 | struct drm_connector *int_lvds_connector; |
aaa6fd2a | 746 | struct drm_connector *int_edp_connector; |
f97108d1 | 747 | |
c4804411 | 748 | bool mchbar_need_disable; |
f97108d1 | 749 | |
4912d041 BW |
750 | struct work_struct rps_work; |
751 | spinlock_t rps_lock; | |
752 | u32 pm_iir; | |
753 | ||
f97108d1 JB |
754 | u8 cur_delay; |
755 | u8 min_delay; | |
756 | u8 max_delay; | |
7648fa99 JB |
757 | u8 fmax; |
758 | u8 fstart; | |
759 | ||
05394f39 CW |
760 | u64 last_count1; |
761 | unsigned long last_time1; | |
4ed0b577 | 762 | unsigned long chipset_power; |
05394f39 CW |
763 | u64 last_count2; |
764 | struct timespec last_time2; | |
765 | unsigned long gfx_power; | |
766 | int c_m; | |
767 | int r_t; | |
768 | u8 corr; | |
7648fa99 | 769 | spinlock_t *mchdev_lock; |
b5e50c3f JB |
770 | |
771 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 772 | |
20bf377e JB |
773 | struct drm_mm_node *compressed_fb; |
774 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 775 | |
ae681d96 CW |
776 | unsigned long last_gpu_reset; |
777 | ||
8be48d92 DA |
778 | /* list of fbdev register on this device */ |
779 | struct intel_fbdev *fbdev; | |
e953fd7b | 780 | |
aaa6fd2a MG |
781 | struct backlight_device *backlight; |
782 | ||
e953fd7b | 783 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 784 | struct drm_property *force_audio_property; |
1da177e4 LT |
785 | } drm_i915_private_t; |
786 | ||
b1d7e4b4 WF |
787 | enum hdmi_force_audio { |
788 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
789 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
790 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
791 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
792 | }; | |
793 | ||
93dfb40c CW |
794 | enum i915_cache_level { |
795 | I915_CACHE_NONE, | |
796 | I915_CACHE_LLC, | |
797 | I915_CACHE_LLC_MLC, /* gen6+ */ | |
798 | }; | |
799 | ||
673a394b | 800 | struct drm_i915_gem_object { |
c397b908 | 801 | struct drm_gem_object base; |
673a394b EA |
802 | |
803 | /** Current space allocated to this object in the GTT, if any. */ | |
804 | struct drm_mm_node *gtt_space; | |
93a37f20 | 805 | struct list_head gtt_list; |
673a394b EA |
806 | |
807 | /** This object's place on the active/flushing/inactive lists */ | |
69dc4987 CW |
808 | struct list_head ring_list; |
809 | struct list_head mm_list; | |
99fcb766 DV |
810 | /** This object's place on GPU write list */ |
811 | struct list_head gpu_write_list; | |
432e58ed CW |
812 | /** This object's place in the batchbuffer or on the eviction list */ |
813 | struct list_head exec_list; | |
673a394b EA |
814 | |
815 | /** | |
816 | * This is set if the object is on the active or flushing lists | |
817 | * (has pending rendering), and is not set if it's on inactive (ready | |
818 | * to be unbound). | |
819 | */ | |
0206e353 | 820 | unsigned int active:1; |
673a394b EA |
821 | |
822 | /** | |
823 | * This is set if the object has been written to since last bound | |
824 | * to the GTT | |
825 | */ | |
0206e353 | 826 | unsigned int dirty:1; |
778c3544 | 827 | |
87ca9c8a CW |
828 | /** |
829 | * This is set if the object has been written to since the last | |
830 | * GPU flush. | |
831 | */ | |
0206e353 | 832 | unsigned int pending_gpu_write:1; |
87ca9c8a | 833 | |
778c3544 DV |
834 | /** |
835 | * Fence register bits (if any) for this object. Will be set | |
836 | * as needed when mapped into the GTT. | |
837 | * Protected by dev->struct_mutex. | |
778c3544 | 838 | */ |
4b9de737 | 839 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 840 | |
778c3544 DV |
841 | /** |
842 | * Advice: are the backing pages purgeable? | |
843 | */ | |
0206e353 | 844 | unsigned int madv:2; |
778c3544 | 845 | |
778c3544 DV |
846 | /** |
847 | * Current tiling mode for the object. | |
848 | */ | |
0206e353 AJ |
849 | unsigned int tiling_mode:2; |
850 | unsigned int tiling_changed:1; | |
778c3544 DV |
851 | |
852 | /** How many users have pinned this object in GTT space. The following | |
853 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
854 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
855 | * times for the same batchbuffer), and the framebuffer code. When | |
856 | * switching/pageflipping, the framebuffer code has at most two buffers | |
857 | * pinned per crtc. | |
858 | * | |
859 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
860 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 861 | unsigned int pin_count:4; |
778c3544 | 862 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 863 | |
75e9e915 DV |
864 | /** |
865 | * Is the object at the current location in the gtt mappable and | |
866 | * fenceable? Used to avoid costly recalculations. | |
867 | */ | |
0206e353 | 868 | unsigned int map_and_fenceable:1; |
75e9e915 | 869 | |
fb7d516a DV |
870 | /** |
871 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
872 | * mappable by accident). Track pin and fault separate for a more | |
873 | * accurate mappable working set. | |
874 | */ | |
0206e353 AJ |
875 | unsigned int fault_mappable:1; |
876 | unsigned int pin_mappable:1; | |
fb7d516a | 877 | |
caea7476 CW |
878 | /* |
879 | * Is the GPU currently using a fence to access this buffer, | |
880 | */ | |
881 | unsigned int pending_fenced_gpu_access:1; | |
882 | unsigned int fenced_gpu_access:1; | |
883 | ||
93dfb40c CW |
884 | unsigned int cache_level:2; |
885 | ||
7bddb01f | 886 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 887 | unsigned int has_global_gtt_mapping:1; |
7bddb01f | 888 | |
856fa198 | 889 | struct page **pages; |
673a394b | 890 | |
185cbcb3 DV |
891 | /** |
892 | * DMAR support | |
893 | */ | |
894 | struct scatterlist *sg_list; | |
895 | int num_sg; | |
896 | ||
67731b87 CW |
897 | /** |
898 | * Used for performing relocations during execbuffer insertion. | |
899 | */ | |
900 | struct hlist_node exec_node; | |
901 | unsigned long exec_handle; | |
6fe4f140 | 902 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 903 | |
673a394b EA |
904 | /** |
905 | * Current offset of the object in GTT space. | |
906 | * | |
907 | * This is the same as gtt_space->start | |
908 | */ | |
909 | uint32_t gtt_offset; | |
e67b8ce1 | 910 | |
673a394b EA |
911 | /** Breadcrumb of last rendering to the buffer. */ |
912 | uint32_t last_rendering_seqno; | |
caea7476 CW |
913 | struct intel_ring_buffer *ring; |
914 | ||
915 | /** Breadcrumb of last fenced GPU access to the buffer. */ | |
916 | uint32_t last_fenced_seqno; | |
917 | struct intel_ring_buffer *last_fenced_ring; | |
673a394b | 918 | |
778c3544 | 919 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 920 | uint32_t stride; |
673a394b | 921 | |
280b713b | 922 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 923 | unsigned long *bit_17; |
280b713b | 924 | |
ba1eb1d8 | 925 | |
673a394b | 926 | /** |
e47c68e9 EA |
927 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
928 | * flags which individual pages are valid. | |
673a394b EA |
929 | */ |
930 | uint8_t *page_cpu_valid; | |
79e53945 JB |
931 | |
932 | /** User space pin count and filp owning the pin */ | |
933 | uint32_t user_pin_count; | |
934 | struct drm_file *pin_filp; | |
71acb5eb DA |
935 | |
936 | /** for phy allocated objects */ | |
937 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 938 | |
6b95a207 KH |
939 | /** |
940 | * Number of crtcs where this object is currently the fb, but | |
941 | * will be page flipped away on the next vblank. When it | |
942 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
943 | */ | |
944 | atomic_t pending_flip; | |
673a394b EA |
945 | }; |
946 | ||
62b8b215 | 947 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 948 | |
673a394b EA |
949 | /** |
950 | * Request queue structure. | |
951 | * | |
952 | * The request queue allows us to note sequence numbers that have been emitted | |
953 | * and may be associated with active buffers to be retired. | |
954 | * | |
955 | * By keeping this list, we can avoid having to do questionable | |
956 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
957 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
958 | */ | |
959 | struct drm_i915_gem_request { | |
852835f3 ZN |
960 | /** On Which ring this request was generated */ |
961 | struct intel_ring_buffer *ring; | |
962 | ||
673a394b EA |
963 | /** GEM sequence number associated with this request. */ |
964 | uint32_t seqno; | |
965 | ||
a71d8d94 CW |
966 | /** Postion in the ringbuffer of the end of the request */ |
967 | u32 tail; | |
968 | ||
673a394b EA |
969 | /** Time at which this request was emitted, in jiffies. */ |
970 | unsigned long emitted_jiffies; | |
971 | ||
b962442e | 972 | /** global list entry for this request */ |
673a394b | 973 | struct list_head list; |
b962442e | 974 | |
f787a5f5 | 975 | struct drm_i915_file_private *file_priv; |
b962442e EA |
976 | /** file_priv list entry for this request */ |
977 | struct list_head client_list; | |
673a394b EA |
978 | }; |
979 | ||
980 | struct drm_i915_file_private { | |
981 | struct { | |
1c25595f | 982 | struct spinlock lock; |
b962442e | 983 | struct list_head request_list; |
673a394b EA |
984 | } mm; |
985 | }; | |
986 | ||
cae5852d ZN |
987 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
988 | ||
989 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
990 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
991 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
992 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
993 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
994 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
995 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
996 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
997 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
998 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
999 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1000 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1001 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1002 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1003 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1004 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
1005 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
1006 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 1007 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
cae5852d ZN |
1008 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
1009 | ||
85436696 JB |
1010 | /* |
1011 | * The genX designation typically refers to the render engine, so render | |
1012 | * capability related checks should use IS_GEN, while display and other checks | |
1013 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1014 | * chips, etc.). | |
1015 | */ | |
cae5852d ZN |
1016 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1017 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1018 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1019 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1020 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1021 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1022 | |
1023 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1024 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
3d29b842 | 1025 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
1026 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1027 | ||
1d2a314c DV |
1028 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) |
1029 | ||
05394f39 | 1030 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1031 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1032 | ||
1033 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
1034 | * rows, which changed the alignment requirements and fence programming. | |
1035 | */ | |
1036 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1037 | IS_I915GM(dev))) | |
1038 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1039 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1040 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1041 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1042 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1043 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
1044 | /* dsparb controlled by hw only */ | |
1045 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1046 | ||
1047 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1048 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1049 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1050 | |
eceae481 JB |
1051 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
1052 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) | |
cae5852d ZN |
1053 | |
1054 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
1055 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
1056 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
1057 | ||
05394f39 CW |
1058 | #include "i915_trace.h" |
1059 | ||
c153f45f | 1060 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1061 | extern int i915_max_ioctl; |
a35d9d3c BW |
1062 | extern unsigned int i915_fbpercrtc __always_unused; |
1063 | extern int i915_panel_ignore_lid __read_mostly; | |
1064 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1065 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1066 | extern unsigned int i915_lvds_downclock __read_mostly; |
4415e63b | 1067 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1068 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1069 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1070 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1071 | extern bool i915_enable_hangcheck __read_mostly; |
e21af88d | 1072 | extern bool i915_enable_ppgtt __read_mostly; |
b3a83639 | 1073 | |
6a9ee8af DA |
1074 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1075 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1076 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1077 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1078 | ||
1da177e4 | 1079 | /* i915_dma.c */ |
84b1fd10 | 1080 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1081 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1082 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1083 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1084 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1085 | extern void i915_driver_preclose(struct drm_device *dev, |
1086 | struct drm_file *file_priv); | |
673a394b EA |
1087 | extern void i915_driver_postclose(struct drm_device *dev, |
1088 | struct drm_file *file_priv); | |
84b1fd10 | 1089 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
1090 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1091 | unsigned long arg); | |
673a394b | 1092 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1093 | struct drm_clip_rect *box, |
1094 | int DR1, int DR4); | |
f803aa55 | 1095 | extern int i915_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
1096 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1097 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1098 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1099 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1100 | ||
af6061af | 1101 | |
1da177e4 | 1102 | /* i915_irq.c */ |
f65d9421 | 1103 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1104 | void i915_handle_error(struct drm_device *dev, bool wedged); |
c153f45f EA |
1105 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
1106 | struct drm_file *file_priv); | |
1107 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
1108 | struct drm_file *file_priv); | |
1da177e4 | 1109 | |
f71d4af4 | 1110 | extern void intel_irq_init(struct drm_device *dev); |
b1f14ad0 | 1111 | |
c153f45f EA |
1112 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1113 | struct drm_file *file_priv); | |
1114 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
1115 | struct drm_file *file_priv); | |
1116 | extern int i915_vblank_swap(struct drm_device *dev, void *data, | |
1117 | struct drm_file *file_priv); | |
1da177e4 | 1118 | |
7c463586 KP |
1119 | void |
1120 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1121 | ||
1122 | void | |
1123 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1124 | ||
0206e353 | 1125 | void intel_enable_asle(struct drm_device *dev); |
01c66889 | 1126 | |
3bd3c932 CW |
1127 | #ifdef CONFIG_DEBUG_FS |
1128 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1129 | #else | |
1130 | #define i915_destroy_error_state(x) | |
1131 | #endif | |
1132 | ||
7c463586 | 1133 | |
673a394b EA |
1134 | /* i915_gem.c */ |
1135 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1136 | struct drm_file *file_priv); | |
1137 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1138 | struct drm_file *file_priv); | |
1139 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1140 | struct drm_file *file_priv); | |
1141 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1142 | struct drm_file *file_priv); | |
1143 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1144 | struct drm_file *file_priv); | |
de151cf6 JB |
1145 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1146 | struct drm_file *file_priv); | |
673a394b EA |
1147 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1148 | struct drm_file *file_priv); | |
1149 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1150 | struct drm_file *file_priv); | |
1151 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1152 | struct drm_file *file_priv); | |
76446cac JB |
1153 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1154 | struct drm_file *file_priv); | |
673a394b EA |
1155 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1156 | struct drm_file *file_priv); | |
1157 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1158 | struct drm_file *file_priv); | |
1159 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1160 | struct drm_file *file_priv); | |
1161 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
1162 | struct drm_file *file_priv); | |
3ef94daa CW |
1163 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1164 | struct drm_file *file_priv); | |
673a394b EA |
1165 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1166 | struct drm_file *file_priv); | |
1167 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1168 | struct drm_file *file_priv); | |
1169 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1170 | struct drm_file *file_priv); | |
1171 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1172 | struct drm_file *file_priv); | |
5a125c3c EA |
1173 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1174 | struct drm_file *file_priv); | |
673a394b | 1175 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1176 | int i915_gem_init_object(struct drm_gem_object *obj); |
db53a302 | 1177 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
88241785 CW |
1178 | uint32_t invalidate_domains, |
1179 | uint32_t flush_domains); | |
05394f39 CW |
1180 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1181 | size_t size); | |
673a394b | 1182 | void i915_gem_free_object(struct drm_gem_object *obj); |
2021746e CW |
1183 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1184 | uint32_t alignment, | |
1185 | bool map_and_fenceable); | |
05394f39 | 1186 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1187 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 1188 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1189 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1190 | |
54cf91dc | 1191 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
ce453d81 | 1192 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
54cf91dc | 1193 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1194 | struct intel_ring_buffer *ring, |
1195 | u32 seqno); | |
54cf91dc | 1196 | |
ff72145b DA |
1197 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1198 | struct drm_device *dev, | |
1199 | struct drm_mode_create_dumb *args); | |
1200 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1201 | uint32_t handle, uint64_t *offset); | |
1202 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1203 | uint32_t handle); |
f787a5f5 CW |
1204 | /** |
1205 | * Returns true if seq1 is later than seq2. | |
1206 | */ | |
1207 | static inline bool | |
1208 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1209 | { | |
1210 | return (int32_t)(seq1 - seq2) >= 0; | |
1211 | } | |
1212 | ||
53d227f2 | 1213 | u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); |
54cf91dc | 1214 | |
d9e86c0e | 1215 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 1216 | struct intel_ring_buffer *pipelined); |
d9e86c0e | 1217 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1218 | |
1690e1eb CW |
1219 | static inline void |
1220 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
1221 | { | |
1222 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1223 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1224 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
1225 | } | |
1226 | } | |
1227 | ||
1228 | static inline void | |
1229 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1230 | { | |
1231 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1232 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1233 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1234 | } | |
1235 | } | |
1236 | ||
b09a1fec | 1237 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 CW |
1238 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
1239 | ||
069efc1d | 1240 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1241 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1242 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1243 | uint32_t read_domains, | |
1244 | uint32_t write_domain); | |
a8198eea | 1245 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
f691e2f4 DV |
1246 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
1247 | void i915_gem_init_swizzling(struct drm_device *dev); | |
e21af88d | 1248 | void i915_gem_init_ppgtt(struct drm_device *dev); |
79e53945 | 1249 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
2021746e CW |
1250 | void i915_gem_do_init(struct drm_device *dev, |
1251 | unsigned long start, | |
1252 | unsigned long mappable_end, | |
1253 | unsigned long end); | |
b93f9cf1 | 1254 | int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire); |
2021746e | 1255 | int __must_check i915_gem_idle(struct drm_device *dev); |
db53a302 CW |
1256 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1257 | struct drm_file *file, | |
1258 | struct drm_i915_gem_request *request); | |
1259 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, | |
b93f9cf1 BW |
1260 | uint32_t seqno, |
1261 | bool do_retire); | |
de151cf6 | 1262 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1263 | int __must_check |
1264 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1265 | bool write); | |
1266 | int __must_check | |
2da3b9b9 CW |
1267 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1268 | u32 alignment, | |
2021746e | 1269 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1270 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1271 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1272 | int id, |
1273 | int align); | |
71acb5eb | 1274 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1275 | struct drm_i915_gem_object *obj); |
71acb5eb | 1276 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1277 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1278 | |
467cffba | 1279 | uint32_t |
e28f8711 CW |
1280 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1281 | uint32_t size, | |
1282 | int tiling_mode); | |
467cffba | 1283 | |
e4ffd173 CW |
1284 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1285 | enum i915_cache_level cache_level); | |
1286 | ||
76aaf220 | 1287 | /* i915_gem_gtt.c */ |
1d2a314c DV |
1288 | int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); |
1289 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); | |
7bddb01f DV |
1290 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
1291 | struct drm_i915_gem_object *obj, | |
1292 | enum i915_cache_level cache_level); | |
1293 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
1294 | struct drm_i915_gem_object *obj); | |
1d2a314c | 1295 | |
76aaf220 | 1296 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
1297 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1298 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 1299 | enum i915_cache_level cache_level); |
05394f39 | 1300 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 1301 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
76aaf220 | 1302 | |
b47eb4a2 | 1303 | /* i915_gem_evict.c */ |
2021746e CW |
1304 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1305 | unsigned alignment, bool mappable); | |
1306 | int __must_check i915_gem_evict_everything(struct drm_device *dev, | |
1307 | bool purgeable_only); | |
1308 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, | |
1309 | bool purgeable_only); | |
b47eb4a2 | 1310 | |
673a394b EA |
1311 | /* i915_gem_tiling.c */ |
1312 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
05394f39 CW |
1313 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1314 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1315 | |
1316 | /* i915_gem_debug.c */ | |
05394f39 | 1317 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1318 | const char *where, uint32_t mark); |
23bc5982 CW |
1319 | #if WATCH_LISTS |
1320 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1321 | #else |
23bc5982 | 1322 | #define i915_verify_lists(dev) 0 |
673a394b | 1323 | #endif |
05394f39 CW |
1324 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1325 | int handle); | |
1326 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1327 | const char *where, uint32_t mark); |
1da177e4 | 1328 | |
2017263e | 1329 | /* i915_debugfs.c */ |
27c202ad BG |
1330 | int i915_debugfs_init(struct drm_minor *minor); |
1331 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1332 | |
317c35d1 JB |
1333 | /* i915_suspend.c */ |
1334 | extern int i915_save_state(struct drm_device *dev); | |
1335 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1336 | |
1337 | /* i915_suspend.c */ | |
1338 | extern int i915_save_state(struct drm_device *dev); | |
1339 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1340 | |
f899fc64 CW |
1341 | /* intel_i2c.c */ |
1342 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1343 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
e957d772 CW |
1344 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1345 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1346 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1347 | { | |
1348 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1349 | } | |
f899fc64 CW |
1350 | extern void intel_i2c_reset(struct drm_device *dev); |
1351 | ||
3b617967 | 1352 | /* intel_opregion.c */ |
44834a67 CW |
1353 | extern int intel_opregion_setup(struct drm_device *dev); |
1354 | #ifdef CONFIG_ACPI | |
1355 | extern void intel_opregion_init(struct drm_device *dev); | |
1356 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1357 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1358 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1359 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1360 | #else |
44834a67 CW |
1361 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1362 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1363 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1364 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1365 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1366 | #endif |
8ee1c3db | 1367 | |
723bfd70 JB |
1368 | /* intel_acpi.c */ |
1369 | #ifdef CONFIG_ACPI | |
1370 | extern void intel_register_dsm_handler(void); | |
1371 | extern void intel_unregister_dsm_handler(void); | |
1372 | #else | |
1373 | static inline void intel_register_dsm_handler(void) { return; } | |
1374 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1375 | #endif /* CONFIG_ACPI */ | |
1376 | ||
79e53945 JB |
1377 | /* modesetting */ |
1378 | extern void intel_modeset_init(struct drm_device *dev); | |
2c7111db | 1379 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1380 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1381 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
ee5382ae | 1382 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1383 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1384 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
9fb526db | 1385 | extern void ironlake_init_pch_refclk(struct drm_device *dev); |
d5bb081b | 1386 | extern void ironlake_enable_rc6(struct drm_device *dev); |
3b8d8d91 | 1387 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0206e353 AJ |
1388 | extern void intel_detect_pch(struct drm_device *dev); |
1389 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
3bad0781 | 1390 | |
8d715f00 KP |
1391 | extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1392 | extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); | |
1393 | extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
1394 | extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); | |
1395 | ||
6ef3d427 | 1396 | /* overlay */ |
3bd3c932 | 1397 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1398 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1399 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1400 | |
1401 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1402 | extern void intel_display_print_error_state(struct seq_file *m, | |
1403 | struct drm_device *dev, | |
1404 | struct intel_display_error_state *error); | |
3bd3c932 | 1405 | #endif |
6ef3d427 | 1406 | |
1ec14ad3 CW |
1407 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1408 | ||
1409 | #define BEGIN_LP_RING(n) \ | |
1410 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
1411 | ||
1412 | #define OUT_RING(x) \ | |
1413 | intel_ring_emit(LP_RING(dev_priv), x) | |
1414 | ||
1415 | #define ADVANCE_LP_RING() \ | |
1416 | intel_ring_advance(LP_RING(dev_priv)) | |
1417 | ||
546b0974 EA |
1418 | /** |
1419 | * Lock test for when it's just for synchronization of ring access. | |
1420 | * | |
1421 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1422 | * has access to the ring. | |
1423 | */ | |
05394f39 | 1424 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1ec14ad3 | 1425 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
05394f39 | 1426 | LOCK_TEST_WITH_RETURN(dev, file); \ |
546b0974 EA |
1427 | } while (0) |
1428 | ||
b7287d80 BW |
1429 | /* On SNB platform, before reading ring registers forcewake bit |
1430 | * must be set to prevent GT core from power down and stale values being | |
1431 | * returned. | |
1432 | */ | |
fcca7926 BW |
1433 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1434 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
67a3744f | 1435 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
b7287d80 BW |
1436 | |
1437 | /* We give fast paths for the really cool registers */ | |
1438 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
1439 | (((dev_priv)->info->gen >= 6) && \ | |
8d715f00 | 1440 | ((reg) < 0x40000) && \ |
c7dffff7 | 1441 | ((reg) != FORCEWAKE)) |
cae5852d | 1442 | |
5f75377d | 1443 | #define __i915_read(x, y) \ |
f7000883 | 1444 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1445 | |
5f75377d KP |
1446 | __i915_read(8, b) |
1447 | __i915_read(16, w) | |
1448 | __i915_read(32, l) | |
1449 | __i915_read(64, q) | |
1450 | #undef __i915_read | |
1451 | ||
1452 | #define __i915_write(x, y) \ | |
f7000883 AK |
1453 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1454 | ||
5f75377d KP |
1455 | __i915_write(8, b) |
1456 | __i915_write(16, w) | |
1457 | __i915_write(32, l) | |
1458 | __i915_write(64, q) | |
1459 | #undef __i915_write | |
1460 | ||
1461 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1462 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1463 | ||
1464 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1465 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1466 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1467 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1468 | ||
1469 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1470 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1471 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1472 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1473 | |
1474 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1475 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1476 | |
1477 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1478 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1479 | ||
ba4f01a3 | 1480 | |
1da177e4 | 1481 | #endif |