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drm/i915: Add pipe B force quirk for 830M
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
CommitLineData
1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
e9b73c67
CW		 33#include <uapi/drm/i915_drm.h>
34
585fb111 35#include "i915_reg.h"
79e53945 36#include "intel_bios.h"
8187a2b7 37#include "intel_ringbuffer.h"
b20385f1 38#include "intel_lrc.h"
0260c420 39#include "i915_gem_gtt.h"
564ddb2f 40#include "i915_gem_render_state.h"
0839ccb8 41#include <linux/io-mapping.h>
f899fc64 42#include <linux/i2c.h>
c167a6fc 43#include <linux/i2c-algo-bit.h>
0ade6386 44#include <drm/intel-gtt.h>
aaa6fd2a 45#include <linux/backlight.h>
5cc9ed4b 46#include <linux/hashtable.h>
2911a35b 47#include <linux/intel-iommu.h>
742cbee8 48#include <linux/kref.h>
9ee32fea 49#include <linux/pm_qos.h>
585fb111 50
1da177e4
LT		 51/* General customization:
52 */
53
1da177e4
LT		 54#define DRIVER_NAME "i915"
55#define DRIVER_DESC "Intel Graphics"
c2813548 56#define DRIVER_DATE "20140822"
1da177e4 57
317c35d1 58enum pipe {
752aa88a 59 INVALID_PIPE = -1,
317c35d1
JB		 60 PIPE_A = 0,
61 PIPE_B,
9db4a9c7 62 PIPE_C,
a57c774a
AK		 63 _PIPE_EDP,
64 I915_MAX_PIPES = _PIPE_EDP
317c35d1 65};
9db4a9c7 66#define pipe_name(p) ((p) + 'A')
317c35d1 67
a5c961d1
PZ		 68enum transcoder {
69 TRANSCODER_A = 0,
70 TRANSCODER_B,
71 TRANSCODER_C,
a57c774a
AK		 72 TRANSCODER_EDP,
73 I915_MAX_TRANSCODERS
a5c961d1
PZ		 74};
75#define transcoder_name(t) ((t) + 'A')
76
80824003
JB		 77enum plane {
78 PLANE_A = 0,
79 PLANE_B,
9db4a9c7 80 PLANE_C,
80824003 81};
9db4a9c7 82#define plane_name(p) ((p) + 'A')
52440211 83
d615a166 84#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
06da8da2 85
2b139522
ED		 86enum port {
87 PORT_A = 0,
88 PORT_B,
89 PORT_C,
90 PORT_D,
91 PORT_E,
92 I915_MAX_PORTS
93};
94#define port_name(p) ((p) + 'A')
95
a09caddd 96#define I915_NUM_PHYS_VLV 2
e4607fcf
CML		 97
98enum dpio_channel {
99 DPIO_CH0,
100 DPIO_CH1
101};
102
103enum dpio_phy {
104 DPIO_PHY0,
105 DPIO_PHY1
106};
107
b97186f0
PZ		 108enum intel_display_power_domain {
109 POWER_DOMAIN_PIPE_A,
110 POWER_DOMAIN_PIPE_B,
111 POWER_DOMAIN_PIPE_C,
112 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
113 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
114 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
115 POWER_DOMAIN_TRANSCODER_A,
116 POWER_DOMAIN_TRANSCODER_B,
117 POWER_DOMAIN_TRANSCODER_C,
f52e353e 118 POWER_DOMAIN_TRANSCODER_EDP,
319be8ae
ID		 119 POWER_DOMAIN_PORT_DDI_A_2_LANES,
120 POWER_DOMAIN_PORT_DDI_A_4_LANES,
121 POWER_DOMAIN_PORT_DDI_B_2_LANES,
122 POWER_DOMAIN_PORT_DDI_B_4_LANES,
123 POWER_DOMAIN_PORT_DDI_C_2_LANES,
124 POWER_DOMAIN_PORT_DDI_C_4_LANES,
125 POWER_DOMAIN_PORT_DDI_D_2_LANES,
126 POWER_DOMAIN_PORT_DDI_D_4_LANES,
127 POWER_DOMAIN_PORT_DSI,
128 POWER_DOMAIN_PORT_CRT,
129 POWER_DOMAIN_PORT_OTHER,
cdf8dd7f 130 POWER_DOMAIN_VGA,
fbeeaa23 131 POWER_DOMAIN_AUDIO,
bd2bb1b9 132 POWER_DOMAIN_PLLS,
baa70707 133 POWER_DOMAIN_INIT,
bddc7645
ID		 134
135 POWER_DOMAIN_NUM,
b97186f0
PZ		 136};
137
138#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
139#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
140 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
f52e353e
ID		 141#define POWER_DOMAIN_TRANSCODER(tran) \
142 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
143 (tran) + POWER_DOMAIN_TRANSCODER_A)
b97186f0 144
1d843f9d
EE		 145enum hpd_pin {
146 HPD_NONE = 0,
147 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
148 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
149 HPD_CRT,
150 HPD_SDVO_B,
151 HPD_SDVO_C,
152 HPD_PORT_B,
153 HPD_PORT_C,
154 HPD_PORT_D,
155 HPD_NUM_PINS
156};
157
2a2d5482
CW		 158#define I915_GEM_GPU_DOMAINS \
159 (I915_GEM_DOMAIN_RENDER | \
160 I915_GEM_DOMAIN_SAMPLER | \
161 I915_GEM_DOMAIN_COMMAND | \
162 I915_GEM_DOMAIN_INSTRUCTION | \
163 I915_GEM_DOMAIN_VERTEX)
62fdfeaf 164
055e393f
DL		 165#define for_each_pipe(__dev_priv, __p) \
166 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
d615a166 167#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
9db4a9c7 168
d79b814d
DL		 169#define for_each_crtc(dev, crtc) \
170 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
171
d063ae48
DL		 172#define for_each_intel_crtc(dev, intel_crtc) \
173 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
174
b2784e15
DL		 175#define for_each_intel_encoder(dev, intel_encoder) \
176 list_for_each_entry(intel_encoder, \
177 &(dev)->mode_config.encoder_list, \
178 base.head)
179
6c2b7c12
DV		 180#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
181 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
182 if ((intel_encoder)->base.crtc == (__crtc))
183
53f5e3ca
JB		 184#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
185 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
186 if ((intel_connector)->base.encoder == (__encoder))
187
b04c5bd6
BF		 188#define for_each_power_domain(domain, mask) \
189 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
190 if ((1 << (domain)) & (mask))
191
e7b903d2 192struct drm_i915_private;
5cc9ed4b 193struct i915_mmu_object;
e7b903d2 194
46edb027
DV		 195enum intel_dpll_id {
196 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
197 /* real shared dpll ids must be >= 0 */
9cd86933
DV		 198 DPLL_ID_PCH_PLL_A = 0,
199 DPLL_ID_PCH_PLL_B = 1,
200 DPLL_ID_WRPLL1 = 0,
201 DPLL_ID_WRPLL2 = 1,
46edb027
DV		 202};
203#define I915_NUM_PLLS 2
204
5358901f 205struct intel_dpll_hw_state {
dcfc3552 206 /* i9xx, pch plls */
66e985c0 207 uint32_t dpll;
8bcc2795 208 uint32_t dpll_md;
66e985c0
DV		 209 uint32_t fp0;
210 uint32_t fp1;
dcfc3552
DL		 211
212 /* hsw, bdw */
d452c5b6 213 uint32_t wrpll;
5358901f
DV		 214};
215
e72f9fbf 216struct intel_shared_dpll {
ee7b9f93
JB		 217 int refcount; /* count of number of CRTCs sharing this PLL */
218 int active; /* count of number of active CRTCs (i.e. DPMS on) */
219 bool on; /* is the PLL actually active? Disabled during modeset */
46edb027
DV		 220 const char *name;
221 /* should match the index in the dev_priv->shared_dplls array */
222 enum intel_dpll_id id;
5358901f 223 struct intel_dpll_hw_state hw_state;
96f6128c
DV		 224 /* The mode_set hook is optional and should be used together with the
225 * intel_prepare_shared_dpll function. */
15bdd4cf
DV		 226 void (*mode_set)(struct drm_i915_private *dev_priv,
227 struct intel_shared_dpll *pll);
e7b903d2
DV		 228 void (*enable)(struct drm_i915_private *dev_priv,
229 struct intel_shared_dpll *pll);
230 void (*disable)(struct drm_i915_private *dev_priv,
231 struct intel_shared_dpll *pll);
5358901f
DV		 232 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
233 struct intel_shared_dpll *pll,
234 struct intel_dpll_hw_state *hw_state);
ee7b9f93 235};
ee7b9f93 236
e69d0bc1
DV		 237/* Used by dp and fdi links */
238struct intel_link_m_n {
239 uint32_t tu;
240 uint32_t gmch_m;
241 uint32_t gmch_n;
242 uint32_t link_m;
243 uint32_t link_n;
244};
245
246void intel_link_compute_m_n(int bpp, int nlanes,
247 int pixel_clock, int link_clock,
248 struct intel_link_m_n *m_n);
249
1da177e4
LT		 250/* Interface history:
251 *
252 * 1.1: Original.
0d6aa60b
DA		 253 * 1.2: Add Power Management
254 * 1.3: Add vblank support
de227f5f 255 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 256 * 1.5: Add vblank pipe configuration
2228ed67
MCA		 257 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
258 * - Support vertical blank on secondary display pipe
1da177e4
LT		 259 */
260#define DRIVER_MAJOR 1
2228ed67 261#define DRIVER_MINOR 6
1da177e4
LT		 262#define DRIVER_PATCHLEVEL 0
263
23bc5982 264#define WATCH_LISTS 0
42d6ab48 265#define WATCH_GTT 0
673a394b 266
0a3e67a4
JB		 267struct opregion_header;
268struct opregion_acpi;
269struct opregion_swsci;
270struct opregion_asle;
271
8ee1c3db 272struct intel_opregion {
5bc4418b
BW		 273 struct opregion_header __iomem *header;
274 struct opregion_acpi __iomem *acpi;
275 struct opregion_swsci __iomem *swsci;
ebde53c7
JN		 276 u32 swsci_gbda_sub_functions;
277 u32 swsci_sbcb_sub_functions;
5bc4418b
BW		 278 struct opregion_asle __iomem *asle;
279 void __iomem *vbt;
01fe9dbd 280 u32 __iomem *lid_state;
91a60f20 281 struct work_struct asle_work;
8ee1c3db 282};
44834a67 283#define OPREGION_SIZE (8*1024)
8ee1c3db 284
6ef3d427
CW		 285struct intel_overlay;
286struct intel_overlay_error_state;
287
7c1c2871
DA		 288struct drm_i915_master_private {
289 drm_local_map_t *sarea;
290 struct _drm_i915_sarea *sarea_priv;
291};
de151cf6 292#define I915_FENCE_REG_NONE -1
42b5aeab
VS		 293#define I915_MAX_NUM_FENCES 32
294/* 32 fences + sign bit for FENCE_REG_NONE */
295#define I915_MAX_NUM_FENCE_BITS 6
de151cf6
JB		 296
297struct drm_i915_fence_reg {
007cc8ac 298 struct list_head lru_list;
caea7476 299 struct drm_i915_gem_object *obj;
1690e1eb 300 int pin_count;
de151cf6 301};
7c1c2871 302
9b9d172d 303struct sdvo_device_mapping {
e957d772 304 u8 initialized;
9b9d172d 305 u8 dvo_port;
306 u8 slave_addr;
307 u8 dvo_wiring;
e957d772 308 u8 i2c_pin;
b1083333 309 u8 ddc_pin;
9b9d172d 310};
311
c4a1d9e4
CW		 312struct intel_display_error_state;
313
63eeaf38 314struct drm_i915_error_state {
742cbee8 315 struct kref ref;
585b0288
BW		 316 struct timeval time;
317
cb383002 318 char error_msg[128];
48b031e3 319 u32 reset_count;
62d5d69b 320 u32 suspend_count;
cb383002 321
585b0288 322 /* Generic register state */
63eeaf38
JB		 323 u32 eir;
324 u32 pgtbl_er;
be998e2e 325 u32 ier;
885ea5a8 326 u32 gtier[4];
b9a3906b 327 u32 ccid;
0f3b6849
CW		 328 u32 derrmr;
329 u32 forcewake;
585b0288
BW		 330 u32 error; /* gen6+ */
331 u32 err_int; /* gen7 */
332 u32 done_reg;
91ec5d11
BW		 333 u32 gac_eco;
334 u32 gam_ecochk;
335 u32 gab_ctl;
336 u32 gfx_mode;
585b0288 337 u32 extra_instdone[I915_NUM_INSTDONE_REG];
585b0288
BW		 338 u64 fence[I915_MAX_NUM_FENCES];
339 struct intel_overlay_error_state *overlay;
340 struct intel_display_error_state *display;
0ca36d78 341 struct drm_i915_error_object *semaphore_obj;
585b0288 342
52d39a21 343 struct drm_i915_error_ring {
372fbb8e 344 bool valid;
362b8af7
BW		 345 /* Software tracked state */
346 bool waiting;
347 int hangcheck_score;
348 enum intel_ring_hangcheck_action hangcheck_action;
349 int num_requests;
350
351 /* our own tracking of ring head and tail */
352 u32 cpu_ring_head;
353 u32 cpu_ring_tail;
354
355 u32 semaphore_seqno[I915_NUM_RINGS - 1];
356
357 /* Register state */
358 u32 tail;
359 u32 head;
360 u32 ctl;
361 u32 hws;
362 u32 ipeir;
363 u32 ipehr;
364 u32 instdone;
362b8af7
BW		 365 u32 bbstate;
366 u32 instpm;
367 u32 instps;
368 u32 seqno;
369 u64 bbaddr;
50877445 370 u64 acthd;
362b8af7 371 u32 fault_reg;
13ffadd1 372 u64 faddr;
362b8af7
BW		 373 u32 rc_psmi; /* sleep state */
374 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
375
52d39a21
CW		 376 struct drm_i915_error_object {
377 int page_count;
378 u32 gtt_offset;
379 u32 *pages[0];
ab0e7ff9 380 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
362b8af7 381
52d39a21
CW		 382 struct drm_i915_error_request {
383 long jiffies;
384 u32 seqno;
ee4f42b1 385 u32 tail;
52d39a21 386 } *requests;
6c7a01ec
BW		 387
388 struct {
389 u32 gfx_mode;
390 union {
391 u64 pdp[4];
392 u32 pp_dir_base;
393 };
394 } vm_info;
ab0e7ff9
CW		 395
396 pid_t pid;
397 char comm[TASK_COMM_LEN];
52d39a21 398 } ring[I915_NUM_RINGS];
3a448734 399
9df30794 400 struct drm_i915_error_buffer {
a779e5ab 401 u32 size;
9df30794 402 u32 name;
0201f1ec 403 u32 rseqno, wseqno;
9df30794
CW		 404 u32 gtt_offset;
405 u32 read_domains;
406 u32 write_domain;
4b9de737 407 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
9df30794
CW		 408 s32 pinned:2;
409 u32 tiling:2;
410 u32 dirty:1;
411 u32 purgeable:1;
5cc9ed4b 412 u32 userptr:1;
5d1333fc 413 s32 ring:4;
f56383cb 414 u32 cache_level:3;
95f5301d 415 } **active_bo, **pinned_bo;
6c7a01ec 416
95f5301d 417 u32 *active_bo_count, *pinned_bo_count;
3a448734 418 u32 vm_count;
63eeaf38
JB		 419};
420
7bd688cd 421struct intel_connector;
b8cecdf5 422struct intel_crtc_config;
46f297fb 423struct intel_plane_config;
0e8ffe1b 424struct intel_crtc;
ee9300bb
DV		 425struct intel_limit;
426struct dpll;
b8cecdf5 427
e70236a8 428struct drm_i915_display_funcs {
ee5382ae 429 bool (*fbc_enabled)(struct drm_device *dev);
993495ae 430 void (*enable_fbc)(struct drm_crtc *crtc);
e70236a8
JB		 431 void (*disable_fbc)(struct drm_device *dev);
432 int (*get_display_clock_speed)(struct drm_device *dev);
433 int (*get_fifo_size)(struct drm_device *dev, int plane);
ee9300bb
DV		 434 /**
435 * find_dpll() - Find the best values for the PLL
436 * @limit: limits for the PLL
437 * @crtc: current CRTC
438 * @target: target frequency in kHz
439 * @refclk: reference clock frequency in kHz
440 * @match_clock: if provided, @best_clock P divider must
441 * match the P divider from @match_clock
442 * used for LVDS downclocking
443 * @best_clock: best PLL values found
444 *
445 * Returns true on success, false on failure.
446 */
447 bool (*find_dpll)(const struct intel_limit *limit,
448 struct drm_crtc *crtc,
449 int target, int refclk,
450 struct dpll *match_clock,
451 struct dpll *best_clock);
46ba614c 452 void (*update_wm)(struct drm_crtc *crtc);
adf3d35e
VS		 453 void (*update_sprite_wm)(struct drm_plane *plane,
454 struct drm_crtc *crtc,
ed57cb8a
DL		 455 uint32_t sprite_width, uint32_t sprite_height,
456 int pixel_size, bool enable, bool scaled);
47fab737 457 void (*modeset_global_resources)(struct drm_device *dev);
0e8ffe1b
DV		 458 /* Returns the active state of the crtc, and if the crtc is active,
459 * fills out the pipe-config with the hw state. */
460 bool (*get_pipe_config)(struct intel_crtc *,
461 struct intel_crtc_config *);
46f297fb
JB		 462 void (*get_plane_config)(struct intel_crtc *,
463 struct intel_plane_config *);
f564048e 464 int (*crtc_mode_set)(struct drm_crtc *crtc,
f564048e
EA		 465 int x, int y,
466 struct drm_framebuffer *old_fb);
76e5a89c
DV		 467 void (*crtc_enable)(struct drm_crtc *crtc);
468 void (*crtc_disable)(struct drm_crtc *crtc);
ee7b9f93 469 void (*off)(struct drm_crtc *crtc);
e0dac65e 470 void (*write_eld)(struct drm_connector *connector,
34427052
JN		 471 struct drm_crtc *crtc,
472 struct drm_display_mode *mode);
674cf967 473 void (*fdi_link_train)(struct drm_crtc *crtc);
6067aaea 474 void (*init_clock_gating)(struct drm_device *dev);
8c9f3aaf
JB		 475 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
476 struct drm_framebuffer *fb,
ed8d1975 477 struct drm_i915_gem_object *obj,
a4872ba6 478 struct intel_engine_cs *ring,
ed8d1975 479 uint32_t flags);
29b9bde6
DV		 480 void (*update_primary_plane)(struct drm_crtc *crtc,
481 struct drm_framebuffer *fb,
482 int x, int y);
20afbda2 483 void (*hpd_irq_setup)(struct drm_device *dev);
e70236a8
JB		 484 /* clock updates for mode set */
485 /* cursor updates */
486 /* render clock increase/decrease */
487 /* display clock increase/decrease */
488 /* pll clock increase/decrease */
7bd688cd
JN		 489
490 int (*setup_backlight)(struct intel_connector *connector);
7bd688cd
JN		 491 uint32_t (*get_backlight)(struct intel_connector *connector);
492 void (*set_backlight)(struct intel_connector *connector,
493 uint32_t level);
494 void (*disable_backlight)(struct intel_connector *connector);
495 void (*enable_backlight)(struct intel_connector *connector);
e70236a8
JB		 496};
497
907b28c5 498struct intel_uncore_funcs {
c8d9a590
D		 499 void (*force_wake_get)(struct drm_i915_private *dev_priv,
500 int fw_engine);
501 void (*force_wake_put)(struct drm_i915_private *dev_priv,
502 int fw_engine);
0b274481
BW		 503
504 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
505 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
506 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
507 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
508
509 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
510 uint8_t val, bool trace);
511 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
512 uint16_t val, bool trace);
513 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
514 uint32_t val, bool trace);
515 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
516 uint64_t val, bool trace);
990bbdad
CW		 517};
518
907b28c5
CW		 519struct intel_uncore {
520 spinlock_t lock; /** lock is also taken in irq contexts. */
521
522 struct intel_uncore_funcs funcs;
523
524 unsigned fifo_count;
525 unsigned forcewake_count;
aec347ab 526
940aece4
D		 527 unsigned fw_rendercount;
528 unsigned fw_mediacount;
529
8232644c 530 struct timer_list force_wake_timer;
907b28c5
CW		 531};
532
79fc46df
DL		 533#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
534 func(is_mobile) sep \
535 func(is_i85x) sep \
536 func(is_i915g) sep \
537 func(is_i945gm) sep \
538 func(is_g33) sep \
539 func(need_gfx_hws) sep \
540 func(is_g4x) sep \
541 func(is_pineview) sep \
542 func(is_broadwater) sep \
543 func(is_crestline) sep \
544 func(is_ivybridge) sep \
545 func(is_valleyview) sep \
546 func(is_haswell) sep \
b833d685 547 func(is_preliminary) sep \
79fc46df
DL		 548 func(has_fbc) sep \
549 func(has_pipe_cxsr) sep \
550 func(has_hotplug) sep \
551 func(cursor_needs_physical) sep \
552 func(has_overlay) sep \
553 func(overlay_needs_physical) sep \
554 func(supports_tv) sep \
dd93be58 555 func(has_llc) sep \
30568c45
DL		 556 func(has_ddi) sep \
557 func(has_fpga_dbg)
c96ea64e 558
a587f779
DL		 559#define DEFINE_FLAG(name) u8 name:1
560#define SEP_SEMICOLON ;
c96ea64e 561
cfdf1fa2 562struct intel_device_info {
10fce67a 563 u32 display_mmio_offset;
87f1f465 564 u16 device_id;
7eb552ae 565 u8 num_pipes:3;
d615a166 566 u8 num_sprites[I915_MAX_PIPES];
c96c3a8c 567 u8 gen;
73ae478c 568 u8 ring_mask; /* Rings supported by the HW */
a587f779 569 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
a57c774a
AK		 570 /* Register offsets for the various display pipes and transcoders */
571 int pipe_offsets[I915_MAX_TRANSCODERS];
572 int trans_offsets[I915_MAX_TRANSCODERS];
a57c774a 573 int palette_offsets[I915_MAX_PIPES];
5efb3e28 574 int cursor_offsets[I915_MAX_PIPES];
cfdf1fa2
KH		 575};
576
a587f779
DL		 577#undef DEFINE_FLAG
578#undef SEP_SEMICOLON
579
7faf1ab2
DV		 580enum i915_cache_level {
581 I915_CACHE_NONE = 0,
350ec881
CW		 582 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
583 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
584 caches, eg sampler/render caches, and the
585 large Last-Level-Cache. LLC is coherent with
586 the CPU, but L3 is only visible to the GPU. */
651d794f 587 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
7faf1ab2
DV		 588};
589
e59ec13d
MK		 590struct i915_ctx_hang_stats {
591 /* This context had batch pending when hang was declared */
592 unsigned batch_pending;
593
594 /* This context had batch active when hang was declared */
595 unsigned batch_active;
be62acb4
MK		 596
597 /* Time when this context was last blamed for a GPU reset */
598 unsigned long guilty_ts;
599
600 /* This context is banned to submit more work */
601 bool banned;
e59ec13d 602};
40521054
BW		 603
604/* This must match up with the value previously used for execbuf2.rsvd1. */
821d66dd 605#define DEFAULT_CONTEXT_HANDLE 0
31b7a88d
OM		 606/**
607 * struct intel_context - as the name implies, represents a context.
608 * @ref: reference count.
609 * @user_handle: userspace tracking identity for this context.
610 * @remap_slice: l3 row remapping information.
611 * @file_priv: filp associated with this context (NULL for global default
612 * context).
613 * @hang_stats: information about the role of this context in possible GPU
614 * hangs.
615 * @vm: virtual memory space used by this context.
616 * @legacy_hw_ctx: render context backing object and whether it is correctly
617 * initialized (legacy ring submission mechanism only).
618 * @link: link in the global list of contexts.
619 *
620 * Contexts are memory images used by the hardware to store copies of their
621 * internal state.
622 */
273497e5 623struct intel_context {
dce3271b 624 struct kref ref;
821d66dd 625 int user_handle;
3ccfd19d 626 uint8_t remap_slice;
40521054 627 struct drm_i915_file_private *file_priv;
e59ec13d 628 struct i915_ctx_hang_stats hang_stats;
ae6c4806 629 struct i915_hw_ppgtt *ppgtt;
a33afea5 630
c9e003af 631 /* Legacy ring buffer submission */
ea0c76f8
OM		 632 struct {
633 struct drm_i915_gem_object *rcs_state;
634 bool initialized;
635 } legacy_hw_ctx;
636
c9e003af 637 /* Execlists */
564ddb2f 638 bool rcs_initialized;
c9e003af
OM		 639 struct {
640 struct drm_i915_gem_object *state;
84c2377f 641 struct intel_ringbuffer *ringbuf;
c9e003af
OM		 642 } engine[I915_NUM_RINGS];
643
a33afea5 644 struct list_head link;
40521054
BW		 645};
646
5c3fe8b0
BW		 647struct i915_fbc {
648 unsigned long size;
5e59f717 649 unsigned threshold;
5c3fe8b0
BW		 650 unsigned int fb_id;
651 enum plane plane;
652 int y;
653
c4213885 654 struct drm_mm_node compressed_fb;
5c3fe8b0
BW		 655 struct drm_mm_node *compressed_llb;
656
da46f936
RV		 657 bool false_color;
658
5c3fe8b0
BW		 659 struct intel_fbc_work {
660 struct delayed_work work;
661 struct drm_crtc *crtc;
662 struct drm_framebuffer *fb;
5c3fe8b0
BW		 663 } *fbc_work;
664
29ebf90f
CW		 665 enum no_fbc_reason {
666 FBC_OK, /* FBC is enabled */
667 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
5c3fe8b0
BW		 668 FBC_NO_OUTPUT, /* no outputs enabled to compress */
669 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
670 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
671 FBC_MODE_TOO_LARGE, /* mode too large for compression */
672 FBC_BAD_PLANE, /* fbc not supported on plane */
673 FBC_NOT_TILED, /* buffer not tiled */
674 FBC_MULTIPLE_PIPES, /* more than one pipe active */
675 FBC_MODULE_PARAM,
676 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
677 } no_fbc_reason;
b5e50c3f
JB		 678};
679
439d7ac0
PB		 680struct i915_drrs {
681 struct intel_connector *connector;
682};
683
2807cf69 684struct intel_dp;
a031d709 685struct i915_psr {
f0355c4a 686 struct mutex lock;
a031d709
RV		 687 bool sink_support;
688 bool source_ok;
2807cf69 689 struct intel_dp *enabled;
7c8f8a70
RV		 690 bool active;
691 struct delayed_work work;
9ca15301 692 unsigned busy_frontbuffer_bits;
3f51e471 693};
5c3fe8b0 694
3bad0781 695enum intel_pch {
f0350830 696 PCH_NONE = 0, /* No PCH present */
3bad0781
ZW		 697 PCH_IBX, /* Ibexpeak PCH */
698 PCH_CPT, /* Cougarpoint PCH */
eb877ebf 699 PCH_LPT, /* Lynxpoint PCH */
40c7ead9 700 PCH_NOP,
3bad0781
ZW		 701};
702
988d6ee8
PZ		 703enum intel_sbi_destination {
704 SBI_ICLK,
705 SBI_MPHY,
706};
707
b690e96c 708#define QUIRK_PIPEA_FORCE (1<<0)
435793df 709#define QUIRK_LVDS_SSC_DISABLE (1<<1)
4dca20ef 710#define QUIRK_INVERT_BRIGHTNESS (1<<2)
9c72cc6f 711#define QUIRK_BACKLIGHT_PRESENT (1<<3)
b6b5d049 712#define QUIRK_PIPEB_FORCE (1<<4)
b690e96c 713
8be48d92 714struct intel_fbdev;
1630fe75 715struct intel_fbc_work;
38651674 716
c2b9152f
DV		 717struct intel_gmbus {
718 struct i2c_adapter adapter;
f2ce9faf 719 u32 force_bit;
c2b9152f 720 u32 reg0;
36c785f0 721 u32 gpio_reg;
c167a6fc 722 struct i2c_algo_bit_data bit_algo;
c2b9152f
DV		 723 struct drm_i915_private *dev_priv;
724};
725
f4c956ad 726struct i915_suspend_saved_registers {
ba8bbcf6
JB		 727 u8 saveLBB;
728 u32 saveDSPACNTR;
729 u32 saveDSPBCNTR;
e948e994 730 u32 saveDSPARB;
ba8bbcf6
JB		 731 u32 savePIPEACONF;
732 u32 savePIPEBCONF;
733 u32 savePIPEASRC;
734 u32 savePIPEBSRC;
735 u32 saveFPA0;
736 u32 saveFPA1;
737 u32 saveDPLL_A;
738 u32 saveDPLL_A_MD;
739 u32 saveHTOTAL_A;
740 u32 saveHBLANK_A;
741 u32 saveHSYNC_A;
742 u32 saveVTOTAL_A;
743 u32 saveVBLANK_A;
744 u32 saveVSYNC_A;
745 u32 saveBCLRPAT_A;
5586c8bc 746 u32 saveTRANSACONF;
42048781
ZW		 747 u32 saveTRANS_HTOTAL_A;
748 u32 saveTRANS_HBLANK_A;
749 u32 saveTRANS_HSYNC_A;
750 u32 saveTRANS_VTOTAL_A;
751 u32 saveTRANS_VBLANK_A;
752 u32 saveTRANS_VSYNC_A;
0da3ea12 753 u32 savePIPEASTAT;
ba8bbcf6
JB		 754 u32 saveDSPASTRIDE;
755 u32 saveDSPASIZE;
756 u32 saveDSPAPOS;
585fb111 757 u32 saveDSPAADDR;
ba8bbcf6
JB		 758 u32 saveDSPASURF;
759 u32 saveDSPATILEOFF;
760 u32 savePFIT_PGM_RATIOS;
0eb96d6e 761 u32 saveBLC_HIST_CTL;
ba8bbcf6
JB		 762 u32 saveBLC_PWM_CTL;
763 u32 saveBLC_PWM_CTL2;
07bf139b 764 u32 saveBLC_HIST_CTL_B;
42048781
ZW		 765 u32 saveBLC_CPU_PWM_CTL;
766 u32 saveBLC_CPU_PWM_CTL2;
ba8bbcf6
JB		 767 u32 saveFPB0;
768 u32 saveFPB1;
769 u32 saveDPLL_B;
770 u32 saveDPLL_B_MD;
771 u32 saveHTOTAL_B;
772 u32 saveHBLANK_B;
773 u32 saveHSYNC_B;
774 u32 saveVTOTAL_B;
775 u32 saveVBLANK_B;
776 u32 saveVSYNC_B;
777 u32 saveBCLRPAT_B;
5586c8bc 778 u32 saveTRANSBCONF;
42048781
ZW		 779 u32 saveTRANS_HTOTAL_B;
780 u32 saveTRANS_HBLANK_B;
781 u32 saveTRANS_HSYNC_B;
782 u32 saveTRANS_VTOTAL_B;
783 u32 saveTRANS_VBLANK_B;
784 u32 saveTRANS_VSYNC_B;
0da3ea12 785 u32 savePIPEBSTAT;
ba8bbcf6
JB		 786 u32 saveDSPBSTRIDE;
787 u32 saveDSPBSIZE;
788 u32 saveDSPBPOS;
585fb111 789 u32 saveDSPBADDR;
ba8bbcf6
JB		 790 u32 saveDSPBSURF;
791 u32 saveDSPBTILEOFF;
585fb111
JB		 792 u32 saveVGA0;
793 u32 saveVGA1;
794 u32 saveVGA_PD;
ba8bbcf6
JB		 795 u32 saveVGACNTRL;
796 u32 saveADPA;
797 u32 saveLVDS;
585fb111
JB		 798 u32 savePP_ON_DELAYS;
799 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB		 800 u32 saveDVOA;
801 u32 saveDVOB;
802 u32 saveDVOC;
803 u32 savePP_ON;
804 u32 savePP_OFF;
805 u32 savePP_CONTROL;
585fb111 806 u32 savePP_DIVISOR;
ba8bbcf6
JB		 807 u32 savePFIT_CONTROL;
808 u32 save_palette_a[256];
809 u32 save_palette_b[256];
ba8bbcf6 810 u32 saveFBC_CONTROL;
0da3ea12
JB		 811 u32 saveIER;
812 u32 saveIIR;
813 u32 saveIMR;
42048781
ZW		 814 u32 saveDEIER;
815 u32 saveDEIMR;
816 u32 saveGTIER;
817 u32 saveGTIMR;
818 u32 saveFDI_RXA_IMR;
819 u32 saveFDI_RXB_IMR;
1f84e550 820 u32 saveCACHE_MODE_0;
1f84e550 821 u32 saveMI_ARB_STATE;
ba8bbcf6
JB		 822 u32 saveSWF0[16];
823 u32 saveSWF1[16];
824 u32 saveSWF2[3];
825 u8 saveMSR;
826 u8 saveSR[8];
123f794f 827 u8 saveGR[25];
ba8bbcf6 828 u8 saveAR_INDEX;
a59e122a 829 u8 saveAR[21];
ba8bbcf6 830 u8 saveDACMASK;
a59e122a 831 u8 saveCR[37];
4b9de737 832 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1fd1c624
EA		 833 u32 saveCURACNTR;
834 u32 saveCURAPOS;
835 u32 saveCURABASE;
836 u32 saveCURBCNTR;
837 u32 saveCURBPOS;
838 u32 saveCURBBASE;
839 u32 saveCURSIZE;
a4fc5ed6
KP		 840 u32 saveDP_B;
841 u32 saveDP_C;
842 u32 saveDP_D;
843 u32 savePIPEA_GMCH_DATA_M;
844 u32 savePIPEB_GMCH_DATA_M;
845 u32 savePIPEA_GMCH_DATA_N;
846 u32 savePIPEB_GMCH_DATA_N;
847 u32 savePIPEA_DP_LINK_M;
848 u32 savePIPEB_DP_LINK_M;
849 u32 savePIPEA_DP_LINK_N;
850 u32 savePIPEB_DP_LINK_N;
42048781
ZW		 851 u32 saveFDI_RXA_CTL;
852 u32 saveFDI_TXA_CTL;
853 u32 saveFDI_RXB_CTL;
854 u32 saveFDI_TXB_CTL;
855 u32 savePFA_CTL_1;
856 u32 savePFB_CTL_1;
857 u32 savePFA_WIN_SZ;
858 u32 savePFB_WIN_SZ;
859 u32 savePFA_WIN_POS;
860 u32 savePFB_WIN_POS;
5586c8bc
ZW		 861 u32 savePCH_DREF_CONTROL;
862 u32 saveDISP_ARB_CTL;
863 u32 savePIPEA_DATA_M1;
864 u32 savePIPEA_DATA_N1;
865 u32 savePIPEA_LINK_M1;
866 u32 savePIPEA_LINK_N1;
867 u32 savePIPEB_DATA_M1;
868 u32 savePIPEB_DATA_N1;
869 u32 savePIPEB_LINK_M1;
870 u32 savePIPEB_LINK_N1;
b5b72e89 871 u32 saveMCHBAR_RENDER_STANDBY;
cda2bb78 872 u32 savePCH_PORT_HOTPLUG;
f4c956ad 873};
c85aa885 874
ddeea5b0
ID		 875struct vlv_s0ix_state {
876 /* GAM */
877 u32 wr_watermark;
878 u32 gfx_prio_ctrl;
879 u32 arb_mode;
880 u32 gfx_pend_tlb0;
881 u32 gfx_pend_tlb1;
882 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
883 u32 media_max_req_count;
884 u32 gfx_max_req_count;
885 u32 render_hwsp;
886 u32 ecochk;
887 u32 bsd_hwsp;
888 u32 blt_hwsp;
889 u32 tlb_rd_addr;
890
891 /* MBC */
892 u32 g3dctl;
893 u32 gsckgctl;
894 u32 mbctl;
895
896 /* GCP */
897 u32 ucgctl1;
898 u32 ucgctl3;
899 u32 rcgctl1;
900 u32 rcgctl2;
901 u32 rstctl;
902 u32 misccpctl;
903
904 /* GPM */
905 u32 gfxpause;
906 u32 rpdeuhwtc;
907 u32 rpdeuc;
908 u32 ecobus;
909 u32 pwrdwnupctl;
910 u32 rp_down_timeout;
911 u32 rp_deucsw;
912 u32 rcubmabdtmr;
913 u32 rcedata;
914 u32 spare2gh;
915
916 /* Display 1 CZ domain */
917 u32 gt_imr;
918 u32 gt_ier;
919 u32 pm_imr;
920 u32 pm_ier;
921 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
922
923 /* GT SA CZ domain */
924 u32 tilectl;
925 u32 gt_fifoctl;
926 u32 gtlc_wake_ctrl;
927 u32 gtlc_survive;
928 u32 pmwgicz;
929
930 /* Display 2 CZ domain */
931 u32 gu_ctl0;
932 u32 gu_ctl1;
933 u32 clock_gate_dis2;
934};
935
bf225f20
CW		 936struct intel_rps_ei {
937 u32 cz_clock;
938 u32 render_c0;
939 u32 media_c0;
31685c25
D		 940};
941
c76bb61a
DS		 942struct intel_rps_bdw_cal {
943 u32 it_threshold_pct; /* interrupt, in percentage */
944 u32 eval_interval; /* evaluation interval, in us */
945 u32 last_ts;
946 u32 last_c0;
947 bool is_up;
948};
949
950struct intel_rps_bdw_turbo {
951 struct intel_rps_bdw_cal up;
952 struct intel_rps_bdw_cal down;
953 struct timer_list flip_timer;
954 u32 timeout;
955 atomic_t flip_received;
956 struct work_struct work_max_freq;
957};
958
c85aa885 959struct intel_gen6_power_mgmt {
59cdb63d 960 /* work and pm_iir are protected by dev_priv->irq_lock */
c85aa885
DV		 961 struct work_struct work;
962 u32 pm_iir;
59cdb63d 963
b39fb297
BW		 964 /* Frequencies are stored in potentially platform dependent multiples.
965 * In other words, *_freq needs to be multiplied by X to be interesting.
966 * Soft limits are those which are used for the dynamic reclocking done
967 * by the driver (raise frequencies under heavy loads, and lower for
968 * lighter loads). Hard limits are those imposed by the hardware.
969 *
970 * A distinction is made for overclocking, which is never enabled by
971 * default, and is considered to be above the hard limit if it's
972 * possible at all.
973 */
974 u8 cur_freq; /* Current frequency (cached, may not == HW) */
975 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
976 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
977 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
978 u8 min_freq; /* AKA RPn. Minimum frequency */
979 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
980 u8 rp1_freq; /* "less than" RP0 power/freqency */
981 u8 rp0_freq; /* Non-overclocked max frequency. */
67c3bf6f 982 u32 cz_freq;
1a01ab3b 983
31685c25 984 u32 ei_interrupt_count;
1a01ab3b 985
dd75fdc8
CW		 986 int last_adj;
987 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
988
c0951f0c 989 bool enabled;
1a01ab3b 990 struct delayed_work delayed_resume_work;
4fc688ce 991
c76bb61a
DS		 992 bool is_bdw_sw_turbo; /* Switch of BDW software turbo */
993 struct intel_rps_bdw_turbo sw_turbo; /* Calculate RP interrupt timing */
994
bf225f20
CW		 995 /* manual wa residency calculations */
996 struct intel_rps_ei up_ei, down_ei;
997
4fc688ce
JB		 998 /*
999 * Protects RPS/RC6 register access and PCU communication.
1000 * Must be taken after struct_mutex if nested.
1001 */
1002 struct mutex hw_lock;
c85aa885
DV		 1003};
1004
1a240d4d
DV		 1005/* defined intel_pm.c */
1006extern spinlock_t mchdev_lock;
1007
c85aa885
DV		 1008struct intel_ilk_power_mgmt {
1009 u8 cur_delay;
1010 u8 min_delay;
1011 u8 max_delay;
1012 u8 fmax;
1013 u8 fstart;
1014
1015 u64 last_count1;
1016 unsigned long last_time1;
1017 unsigned long chipset_power;
1018 u64 last_count2;
5ed0bdf2 1019 u64 last_time2;
c85aa885
DV		 1020 unsigned long gfx_power;
1021 u8 corr;
1022
1023 int c_m;
1024 int r_t;
3e373948
DV		 1025
1026 struct drm_i915_gem_object *pwrctx;
1027 struct drm_i915_gem_object *renderctx;
c85aa885
DV		 1028};
1029
c6cb582e
ID		 1030struct drm_i915_private;
1031struct i915_power_well;
1032
1033struct i915_power_well_ops {
1034 /*
1035 * Synchronize the well's hw state to match the current sw state, for
1036 * example enable/disable it based on the current refcount. Called
1037 * during driver init and resume time, possibly after first calling
1038 * the enable/disable handlers.
1039 */
1040 void (*sync_hw)(struct drm_i915_private *dev_priv,
1041 struct i915_power_well *power_well);
1042 /*
1043 * Enable the well and resources that depend on it (for example
1044 * interrupts located on the well). Called after the 0->1 refcount
1045 * transition.
1046 */
1047 void (*enable)(struct drm_i915_private *dev_priv,
1048 struct i915_power_well *power_well);
1049 /*
1050 * Disable the well and resources that depend on it. Called after
1051 * the 1->0 refcount transition.
1052 */
1053 void (*disable)(struct drm_i915_private *dev_priv,
1054 struct i915_power_well *power_well);
1055 /* Returns the hw enabled state. */
1056 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1057 struct i915_power_well *power_well);
1058};
1059
a38911a3
WX		 1060/* Power well structure for haswell */
1061struct i915_power_well {
c1ca727f 1062 const char *name;
6f3ef5dd 1063 bool always_on;
a38911a3
WX		 1064 /* power well enable/disable usage count */
1065 int count;
bfafe93a
ID		 1066 /* cached hw enabled state */
1067 bool hw_enabled;
c1ca727f 1068 unsigned long domains;
77961eb9 1069 unsigned long data;
c6cb582e 1070 const struct i915_power_well_ops *ops;
a38911a3
WX		 1071};
1072
83c00f55 1073struct i915_power_domains {
baa70707
ID		 1074 /*
1075 * Power wells needed for initialization at driver init and suspend
1076 * time are on. They are kept on until after the first modeset.
1077 */
1078 bool init_power_on;
0d116a29 1079 bool initializing;
c1ca727f 1080 int power_well_count;
baa70707 1081
83c00f55 1082 struct mutex lock;
1da51581 1083 int domain_use_count[POWER_DOMAIN_NUM];
c1ca727f 1084 struct i915_power_well *power_wells;
83c00f55
ID		 1085};
1086
231f42a4
DV		 1087struct i915_dri1_state {
1088 unsigned allow_batchbuffer : 1;
1089 u32 __iomem *gfx_hws_cpu_addr;
1090
1091 unsigned int cpp;
1092 int back_offset;
1093 int front_offset;
1094 int current_page;
1095 int page_flipping;
1096
1097 uint32_t counter;
1098};
1099
db1b76ca
DV		 1100struct i915_ums_state {
1101 /**
1102 * Flag if the X Server, and thus DRM, is not currently in
1103 * control of the device.
1104 *
1105 * This is set between LeaveVT and EnterVT. It needs to be
1106 * replaced with a semaphore. It also needs to be
1107 * transitioned away from for kernel modesetting.
1108 */
1109 int mm_suspended;
1110};
1111
35a85ac6 1112#define MAX_L3_SLICES 2
a4da4fa4 1113struct intel_l3_parity {
35a85ac6 1114 u32 *remap_info[MAX_L3_SLICES];
a4da4fa4 1115 struct work_struct error_work;
35a85ac6 1116 int which_slice;
a4da4fa4
DV		 1117};
1118
4b5aed62 1119struct i915_gem_mm {
4b5aed62
DV		 1120 /** Memory allocator for GTT stolen memory */
1121 struct drm_mm stolen;
4b5aed62
DV		 1122 /** List of all objects in gtt_space. Used to restore gtt
1123 * mappings on resume */
1124 struct list_head bound_list;
1125 /**
1126 * List of objects which are not bound to the GTT (thus
1127 * are idle and not used by the GPU) but still have
1128 * (presumably uncached) pages still attached.
1129 */
1130 struct list_head unbound_list;
1131
1132 /** Usable portion of the GTT for GEM */
1133 unsigned long stolen_base; /* limited to low memory (32-bit) */
1134
4b5aed62
DV		 1135 /** PPGTT used for aliasing the PPGTT with the GTT */
1136 struct i915_hw_ppgtt *aliasing_ppgtt;
1137
2cfcd32a 1138 struct notifier_block oom_notifier;
ceabbba5 1139 struct shrinker shrinker;
4b5aed62
DV		 1140 bool shrinker_no_lock_stealing;
1141
4b5aed62
DV		 1142 /** LRU list of objects with fence regs on them. */
1143 struct list_head fence_list;
1144
1145 /**
1146 * We leave the user IRQ off as much as possible,
1147 * but this means that requests will finish and never
1148 * be retired once the system goes idle. Set a timer to
1149 * fire periodically while the ring is running. When it
1150 * fires, go retire requests.
1151 */
1152 struct delayed_work retire_work;
1153
b29c19b6
CW		 1154 /**
1155 * When we detect an idle GPU, we want to turn on
1156 * powersaving features. So once we see that there
1157 * are no more requests outstanding and no more
1158 * arrive within a small period of time, we fire
1159 * off the idle_work.
1160 */
1161 struct delayed_work idle_work;
1162
4b5aed62
DV		 1163 /**
1164 * Are we in a non-interruptible section of code like
1165 * modesetting?
1166 */
1167 bool interruptible;
1168
f62a0076
CW		 1169 /**
1170 * Is the GPU currently considered idle, or busy executing userspace
1171 * requests? Whilst idle, we attempt to power down the hardware and
1172 * display clocks. In order to reduce the effect on performance, there
1173 * is a slight delay before we do so.
1174 */
1175 bool busy;
1176
bdf1e7e3
DV		 1177 /* the indicator for dispatch video commands on two BSD rings */
1178 int bsd_ring_dispatch_index;
1179
4b5aed62
DV		 1180 /** Bit 6 swizzling required for X tiling */
1181 uint32_t bit_6_swizzle_x;
1182 /** Bit 6 swizzling required for Y tiling */
1183 uint32_t bit_6_swizzle_y;
1184
4b5aed62 1185 /* accounting, useful for userland debugging */
c20e8355 1186 spinlock_t object_stat_lock;
4b5aed62
DV		 1187 size_t object_memory;
1188 u32 object_count;
1189};
1190
edc3d884 1191struct drm_i915_error_state_buf {
0a4cd7c8 1192 struct drm_i915_private *i915;
edc3d884
MK		 1193 unsigned bytes;
1194 unsigned size;
1195 int err;
1196 u8 *buf;
1197 loff_t start;
1198 loff_t pos;
1199};
1200
fc16b48b
MK		 1201struct i915_error_state_file_priv {
1202 struct drm_device *dev;
1203 struct drm_i915_error_state *error;
1204};
1205
99584db3
DV		 1206struct i915_gpu_error {
1207 /* For hangcheck timer */
1208#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1209#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
be62acb4
MK		 1210 /* Hang gpu twice in this window and your context gets banned */
1211#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1212
99584db3 1213 struct timer_list hangcheck_timer;
99584db3
DV		 1214
1215 /* For reset and error_state handling. */
1216 spinlock_t lock;
1217 /* Protected by the above dev->gpu_error.lock. */
1218 struct drm_i915_error_state *first_error;
1219 struct work_struct work;
99584db3 1220
094f9a54
CW		 1221
1222 unsigned long missed_irq_rings;
1223
1f83fee0 1224 /**
2ac0f450 1225 * State variable controlling the reset flow and count
1f83fee0 1226 *
2ac0f450
MK		 1227 * This is a counter which gets incremented when reset is triggered,
1228 * and again when reset has been handled. So odd values (lowest bit set)
1229 * means that reset is in progress and even values that
1230 * (reset_counter >> 1):th reset was successfully completed.
1231 *
1232 * If reset is not completed succesfully, the I915_WEDGE bit is
1233 * set meaning that hardware is terminally sour and there is no
1234 * recovery. All waiters on the reset_queue will be woken when
1235 * that happens.
1236 *
1237 * This counter is used by the wait_seqno code to notice that reset
1238 * event happened and it needs to restart the entire ioctl (since most
1239 * likely the seqno it waited for won't ever signal anytime soon).
f69061be
DV		 1240 *
1241 * This is important for lock-free wait paths, where no contended lock
1242 * naturally enforces the correct ordering between the bail-out of the
1243 * waiter and the gpu reset work code.
1f83fee0
DV		 1244 */
1245 atomic_t reset_counter;
1246
1f83fee0 1247#define I915_RESET_IN_PROGRESS_FLAG 1
2ac0f450 1248#define I915_WEDGED (1 << 31)
1f83fee0
DV		 1249
1250 /**
1251 * Waitqueue to signal when the reset has completed. Used by clients
1252 * that wait for dev_priv->mm.wedged to settle.
1253 */
1254 wait_queue_head_t reset_queue;
33196ded 1255
88b4aa87
MK		 1256 /* Userspace knobs for gpu hang simulation;
1257 * combines both a ring mask, and extra flags
1258 */
1259 u32 stop_rings;
1260#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1261#define I915_STOP_RING_ALLOW_WARN (1 << 30)
094f9a54
CW		 1262
1263 /* For missed irq/seqno simulation. */
1264 unsigned int test_irq_rings;
6689c167
MA		 1265
1266 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1267 bool reload_in_reset;
99584db3
DV		 1268};
1269
b8efb17b
ZR		 1270enum modeset_restore {
1271 MODESET_ON_LID_OPEN,
1272 MODESET_DONE,
1273 MODESET_SUSPENDED,
1274};
1275
6acab15a 1276struct ddi_vbt_port_info {
ce4dd49e
DL		 1277 /*
1278 * This is an index in the HDMI/DVI DDI buffer translation table.
1279 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1280 * populate this field.
1281 */
1282#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
6acab15a 1283 uint8_t hdmi_level_shift;
311a2094
PZ		 1284
1285 uint8_t supports_dvi:1;
1286 uint8_t supports_hdmi:1;
1287 uint8_t supports_dp:1;
6acab15a
PZ		 1288};
1289
83a7280e
PB		 1290enum drrs_support_type {
1291 DRRS_NOT_SUPPORTED = 0,
1292 STATIC_DRRS_SUPPORT = 1,
1293 SEAMLESS_DRRS_SUPPORT = 2
1294};
1295
41aa3448
RV		 1296struct intel_vbt_data {
1297 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1298 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1299
1300 /* Feature bits */
1301 unsigned int int_tv_support:1;
1302 unsigned int lvds_dither:1;
1303 unsigned int lvds_vbt:1;
1304 unsigned int int_crt_support:1;
1305 unsigned int lvds_use_ssc:1;
1306 unsigned int display_clock_mode:1;
1307 unsigned int fdi_rx_polarity_inverted:1;
3e6bd011 1308 unsigned int has_mipi:1;
41aa3448
RV		 1309 int lvds_ssc_freq;
1310 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1311
83a7280e
PB		 1312 enum drrs_support_type drrs_type;
1313
41aa3448
RV		 1314 /* eDP */
1315 int edp_rate;
1316 int edp_lanes;
1317 int edp_preemphasis;
1318 int edp_vswing;
1319 bool edp_initialized;
1320 bool edp_support;
1321 int edp_bpp;
1322 struct edp_power_seq edp_pps;
1323
f00076d2
JN		 1324 struct {
1325 u16 pwm_freq_hz;
39fbc9c8 1326 bool present;
f00076d2 1327 bool active_low_pwm;
1de6068e 1328 u8 min_brightness; /* min_brightness/255 of max */
f00076d2
JN		 1329 } backlight;
1330
d17c5443
SK		 1331 /* MIPI DSI */
1332 struct {
3e6bd011 1333 u16 port;
d17c5443 1334 u16 panel_id;
d3b542fc
SK		 1335 struct mipi_config *config;
1336 struct mipi_pps_data *pps;
1337 u8 seq_version;
1338 u32 size;
1339 u8 *data;
1340 u8 *sequence[MIPI_SEQ_MAX];
d17c5443
SK		 1341 } dsi;
1342
41aa3448
RV		 1343 int crt_ddc_pin;
1344
1345 int child_dev_num;
768f69c9 1346 union child_device_config *child_dev;
6acab15a
PZ		 1347
1348 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
41aa3448
RV		 1349};
1350
77c122bc
VS		 1351enum intel_ddb_partitioning {
1352 INTEL_DDB_PART_1_2,
1353 INTEL_DDB_PART_5_6, /* IVB+ */
1354};
1355
1fd527cc
VS		 1356struct intel_wm_level {
1357 bool enable;
1358 uint32_t pri_val;
1359 uint32_t spr_val;
1360 uint32_t cur_val;
1361 uint32_t fbc_val;
1362};
1363
820c1980 1364struct ilk_wm_values {
609cedef
VS		 1365 uint32_t wm_pipe[3];
1366 uint32_t wm_lp[3];
1367 uint32_t wm_lp_spr[3];
1368 uint32_t wm_linetime[3];
1369 bool enable_fbc_wm;
1370 enum intel_ddb_partitioning partitioning;
1371};
1372
c67a470b 1373/*
765dab67
PZ		 1374 * This struct helps tracking the state needed for runtime PM, which puts the
1375 * device in PCI D3 state. Notice that when this happens, nothing on the
1376 * graphics device works, even register access, so we don't get interrupts nor
1377 * anything else.
c67a470b 1378 *
765dab67
PZ		 1379 * Every piece of our code that needs to actually touch the hardware needs to
1380 * either call intel_runtime_pm_get or call intel_display_power_get with the
1381 * appropriate power domain.
a8a8bd54 1382 *
765dab67
PZ		 1383 * Our driver uses the autosuspend delay feature, which means we'll only really
1384 * suspend if we stay with zero refcount for a certain amount of time. The
1385 * default value is currently very conservative (see intel_init_runtime_pm), but
1386 * it can be changed with the standard runtime PM files from sysfs.
c67a470b
PZ		 1387 *
1388 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1389 * goes back to false exactly before we reenable the IRQs. We use this variable
1390 * to check if someone is trying to enable/disable IRQs while they're supposed
1391 * to be disabled. This shouldn't happen and we'll print some error messages in
730488b2 1392 * case it happens.
c67a470b 1393 *
765dab67 1394 * For more, read the Documentation/power/runtime_pm.txt.
c67a470b 1395 */
5d584b2e
PZ		 1396struct i915_runtime_pm {
1397 bool suspended;
9df7575f 1398 bool _irqs_disabled;
c67a470b
PZ		 1399};
1400
926321d5
DV		 1401enum intel_pipe_crc_source {
1402 INTEL_PIPE_CRC_SOURCE_NONE,
1403 INTEL_PIPE_CRC_SOURCE_PLANE1,
1404 INTEL_PIPE_CRC_SOURCE_PLANE2,
1405 INTEL_PIPE_CRC_SOURCE_PF,
5b3a856b 1406 INTEL_PIPE_CRC_SOURCE_PIPE,
3d099a05
DV		 1407 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1408 INTEL_PIPE_CRC_SOURCE_TV,
1409 INTEL_PIPE_CRC_SOURCE_DP_B,
1410 INTEL_PIPE_CRC_SOURCE_DP_C,
1411 INTEL_PIPE_CRC_SOURCE_DP_D,
46a19188 1412 INTEL_PIPE_CRC_SOURCE_AUTO,
926321d5
DV		 1413 INTEL_PIPE_CRC_SOURCE_MAX,
1414};
1415
8bf1e9f1 1416struct intel_pipe_crc_entry {
ac2300d4 1417 uint32_t frame;
8bf1e9f1
SH		 1418 uint32_t crc[5];
1419};
1420
b2c88f5b 1421#define INTEL_PIPE_CRC_ENTRIES_NR 128
8bf1e9f1 1422struct intel_pipe_crc {
d538bbdf
DL		 1423 spinlock_t lock;
1424 bool opened; /* exclusive access to the result file */
e5f75aca 1425 struct intel_pipe_crc_entry *entries;
926321d5 1426 enum intel_pipe_crc_source source;
d538bbdf 1427 int head, tail;
07144428 1428 wait_queue_head_t wq;
8bf1e9f1
SH		 1429};
1430
f99d7069
DV		 1431struct i915_frontbuffer_tracking {
1432 struct mutex lock;
1433
1434 /*
1435 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1436 * scheduled flips.
1437 */
1438 unsigned busy_bits;
1439 unsigned flip_bits;
1440};
1441
77fec556 1442struct drm_i915_private {
f4c956ad 1443 struct drm_device *dev;
42dcedd4 1444 struct kmem_cache *slab;
f4c956ad 1445
5c969aa7 1446 const struct intel_device_info info;
f4c956ad
DV		 1447
1448 int relative_constants_mode;
1449
1450 void __iomem *regs;
1451
907b28c5 1452 struct intel_uncore uncore;
f4c956ad
DV		 1453
1454 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1455
28c70f16 1456
f4c956ad
DV		 1457 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1458 * controller on different i2c buses. */
1459 struct mutex gmbus_mutex;
1460
1461 /**
1462 * Base address of the gmbus and gpio block.
1463 */
1464 uint32_t gpio_mmio_base;
1465
b6fdd0f2
SS		 1466 /* MMIO base address for MIPI regs */
1467 uint32_t mipi_mmio_base;
1468
28c70f16
DV		 1469 wait_queue_head_t gmbus_wait_queue;
1470
f4c956ad 1471 struct pci_dev *bridge_dev;
a4872ba6 1472 struct intel_engine_cs ring[I915_NUM_RINGS];
3e78998a 1473 struct drm_i915_gem_object *semaphore_obj;
f72b3435 1474 uint32_t last_seqno, next_seqno;
f4c956ad
DV		 1475
1476 drm_dma_handle_t *status_page_dmah;
f4c956ad
DV		 1477 struct resource mch_res;
1478
f4c956ad
DV		 1479 /* protects the irq masks */
1480 spinlock_t irq_lock;
1481
84c33a64
SG		 1482 /* protects the mmio flip data */
1483 spinlock_t mmio_flip_lock;
1484
f8b79e58
ID		 1485 bool display_irqs_enabled;
1486
9ee32fea
DV		 1487 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1488 struct pm_qos_request pm_qos;
1489
f4c956ad 1490 /* DPIO indirect register protection */
09153000 1491 struct mutex dpio_lock;
f4c956ad
DV		 1492
1493 /** Cached value of IMR to avoid reads in updating the bitfield */
abd58f01
BW		 1494 union {
1495 u32 irq_mask;
1496 u32 de_irq_mask[I915_MAX_PIPES];
1497 };
f4c956ad 1498 u32 gt_irq_mask;
605cd25b 1499 u32 pm_irq_mask;
a6706b45 1500 u32 pm_rps_events;
91d181dd 1501 u32 pipestat_irq_mask[I915_MAX_PIPES];
f4c956ad 1502
f4c956ad 1503 struct work_struct hotplug_work;
b543fb04
EE		 1504 struct {
1505 unsigned long hpd_last_jiffies;
1506 int hpd_cnt;
1507 enum {
1508 HPD_ENABLED = 0,
1509 HPD_DISABLED = 1,
1510 HPD_MARK_DISABLED = 2
1511 } hpd_mark;
1512 } hpd_stats[HPD_NUM_PINS];
142e2398 1513 u32 hpd_event_bits;
6323751d 1514 struct delayed_work hotplug_reenable_work;
f4c956ad 1515
5c3fe8b0 1516 struct i915_fbc fbc;
439d7ac0 1517 struct i915_drrs drrs;
f4c956ad 1518 struct intel_opregion opregion;
41aa3448 1519 struct intel_vbt_data vbt;
f4c956ad
DV		 1520
1521 /* overlay */
1522 struct intel_overlay *overlay;
f4c956ad 1523
58c68779
JN		 1524 /* backlight registers and fields in struct intel_panel */
1525 spinlock_t backlight_lock;
31ad8ec6 1526
f4c956ad 1527 /* LVDS info */
f4c956ad
DV		 1528 bool no_aux_handshake;
1529
f4c956ad
DV		 1530 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1531 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1532 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1533
1534 unsigned int fsb_freq, mem_freq, is_ddr3;
d60c4473 1535 unsigned int vlv_cdclk_freq;
f4c956ad 1536
645416f5
DV		 1537 /**
1538 * wq - Driver workqueue for GEM.
1539 *
1540 * NOTE: Work items scheduled here are not allowed to grab any modeset
1541 * locks, for otherwise the flushing done in the pageflip code will
1542 * result in deadlocks.
1543 */
f4c956ad
DV		 1544 struct workqueue_struct *wq;
1545
1546 /* Display functions */
1547 struct drm_i915_display_funcs display;
1548
1549 /* PCH chipset type */
1550 enum intel_pch pch_type;
17a303ec 1551 unsigned short pch_id;
f4c956ad
DV		 1552
1553 unsigned long quirks;
1554
b8efb17b
ZR		 1555 enum modeset_restore modeset_restore;
1556 struct mutex modeset_restore_lock;
673a394b 1557
a7bbbd63 1558 struct list_head vm_list; /* Global list of all address spaces */
0260c420 1559 struct i915_gtt gtt; /* VM representing the global address space */
5d4545ae 1560
4b5aed62 1561 struct i915_gem_mm mm;
5cc9ed4b
CW		 1562#if defined(CONFIG_MMU_NOTIFIER)
1563 DECLARE_HASHTABLE(mmu_notifiers, 7);
1564#endif
8781342d 1565
8781342d
DV		 1566 /* Kernel Modesetting */
1567
9b9d172d 1568 struct sdvo_device_mapping sdvo_mappings[2];
652c393a 1569
76c4ac04
DL		 1570 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1571 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
6b95a207
KH		 1572 wait_queue_head_t pending_flip_queue;
1573
c4597872
DV		 1574#ifdef CONFIG_DEBUG_FS
1575 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1576#endif
1577
e72f9fbf
DV		 1578 int num_shared_dpll;
1579 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
e4607fcf 1580 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
ee7b9f93 1581
888b5995
AS		 1582 /*
1583 * workarounds are currently applied at different places and
1584 * changes are being done to consolidate them so exact count is
1585 * not clear at this point, use a max value for now.
1586 */
1587#define I915_MAX_WA_REGS 16
1588 struct {
1589 u32 addr;
1590 u32 value;
1591 /* bitmask representing WA bits */
1592 u32 mask;
1593 } intel_wa_regs[I915_MAX_WA_REGS];
1594 u32 num_wa_regs;
1595
652c393a
JB		 1596 /* Reclocking support */
1597 bool render_reclock_avail;
1598 bool lvds_downclock_avail;
18f9ed12
ZY		 1599 /* indicates the reduced downclock for LVDS*/
1600 int lvds_downclock;
f99d7069
DV		 1601
1602 struct i915_frontbuffer_tracking fb_tracking;
1603
652c393a 1604 u16 orig_clock;
f97108d1 1605
c4804411 1606 bool mchbar_need_disable;
f97108d1 1607
a4da4fa4
DV		 1608 struct intel_l3_parity l3_parity;
1609
59124506
BW		 1610 /* Cannot be determined by PCIID. You must always read a register. */
1611 size_t ellc_size;
1612
c6a828d3 1613 /* gen6+ rps state */
c85aa885 1614 struct intel_gen6_power_mgmt rps;
c6a828d3 1615
20e4d407
DV		 1616 /* ilk-only ips/rps state. Everything in here is protected by the global
1617 * mchdev_lock in intel_pm.c */
c85aa885 1618 struct intel_ilk_power_mgmt ips;
b5e50c3f 1619
83c00f55 1620 struct i915_power_domains power_domains;
a38911a3 1621
a031d709 1622 struct i915_psr psr;
3f51e471 1623
99584db3 1624 struct i915_gpu_error gpu_error;
ae681d96 1625
c9cddffc
JB		 1626 struct drm_i915_gem_object *vlv_pctx;
1627
4520f53a 1628#ifdef CONFIG_DRM_I915_FBDEV
8be48d92
DA		 1629 /* list of fbdev register on this device */
1630 struct intel_fbdev *fbdev;
82e3b8c1 1631 struct work_struct fbdev_suspend_work;
4520f53a 1632#endif
e953fd7b
CW		 1633
1634 struct drm_property *broadcast_rgb_property;
3f43c48d 1635 struct drm_property *force_audio_property;
e3689190 1636
254f965c 1637 uint32_t hw_context_size;
a33afea5 1638 struct list_head context_list;
f4c956ad 1639
3e68320e 1640 u32 fdi_rx_config;
68d18ad7 1641
842f1c8b 1642 u32 suspend_count;
f4c956ad 1643 struct i915_suspend_saved_registers regfile;
ddeea5b0 1644 struct vlv_s0ix_state vlv_s0ix_state;
231f42a4 1645
53615a5e
VS		 1646 struct {
1647 /*
1648 * Raw watermark latency values:
1649 * in 0.1us units for WM0,
1650 * in 0.5us units for WM1+.
1651 */
1652 /* primary */
1653 uint16_t pri_latency[5];
1654 /* sprite */
1655 uint16_t spr_latency[5];
1656 /* cursor */
1657 uint16_t cur_latency[5];
609cedef
VS		 1658
1659 /* current hardware state */
820c1980 1660 struct ilk_wm_values hw;
53615a5e
VS		 1661 } wm;
1662
8a187455
PZ		 1663 struct i915_runtime_pm pm;
1664
13cf5504
DA		 1665 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1666 u32 long_hpd_port_mask;
1667 u32 short_hpd_port_mask;
1668 struct work_struct dig_port_work;
1669
0e32b39c
DA		 1670 /*
1671 * if we get a HPD irq from DP and a HPD irq from non-DP
1672 * the non-DP HPD could block the workqueue on a mode config
1673 * mutex getting, that userspace may have taken. However
1674 * userspace is waiting on the DP workqueue to run which is
1675 * blocked behind the non-DP one.
1676 */
1677 struct workqueue_struct *dp_wq;
1678
231f42a4
DV		 1679 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1680 * here! */
1681 struct i915_dri1_state dri1;
db1b76ca
DV		 1682 /* Old ums support infrastructure, same warning applies. */
1683 struct i915_ums_state ums;
bdf1e7e3 1684
a83014d3
OM		 1685 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1686 struct {
1687 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1688 struct intel_engine_cs *ring,
1689 struct intel_context *ctx,
1690 struct drm_i915_gem_execbuffer2 *args,
1691 struct list_head *vmas,
1692 struct drm_i915_gem_object *batch_obj,
1693 u64 exec_start, u32 flags);
1694 int (*init_rings)(struct drm_device *dev);
1695 void (*cleanup_ring)(struct intel_engine_cs *ring);
1696 void (*stop_ring)(struct intel_engine_cs *ring);
1697 } gt;
1698
bdf1e7e3
DV		 1699 /*
1700 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1701 * will be rejected. Instead look for a better place.
1702 */
77fec556 1703};
1da177e4 1704
2c1792a1
CW		 1705static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1706{
1707 return dev->dev_private;
1708}
1709
b4519513
CW		 1710/* Iterate over initialised rings */
1711#define for_each_ring(ring__, dev_priv__, i__) \
1712 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1713 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1714
b1d7e4b4
WF		 1715enum hdmi_force_audio {
1716 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1717 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1718 HDMI_AUDIO_AUTO, /* trust EDID */
1719 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1720};
1721
190d6cd5 1722#define I915_GTT_OFFSET_NONE ((u32)-1)
ed2f3452 1723
37e680a1
CW		 1724struct drm_i915_gem_object_ops {
1725 /* Interface between the GEM object and its backing storage.
1726 * get_pages() is called once prior to the use of the associated set
1727 * of pages before to binding them into the GTT, and put_pages() is
1728 * called after we no longer need them. As we expect there to be
1729 * associated cost with migrating pages between the backing storage
1730 * and making them available for the GPU (e.g. clflush), we may hold
1731 * onto the pages after they are no longer referenced by the GPU
1732 * in case they may be used again shortly (for example migrating the
1733 * pages to a different memory domain within the GTT). put_pages()
1734 * will therefore most likely be called when the object itself is
1735 * being released or under memory pressure (where we attempt to
1736 * reap pages for the shrinker).
1737 */
1738 int (*get_pages)(struct drm_i915_gem_object *);
1739 void (*put_pages)(struct drm_i915_gem_object *);
5cc9ed4b
CW		 1740 int (*dmabuf_export)(struct drm_i915_gem_object *);
1741 void (*release)(struct drm_i915_gem_object *);
37e680a1
CW		 1742};
1743
a071fa00
DV		 1744/*
1745 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1746 * considered to be the frontbuffer for the given plane interface-vise. This
1747 * doesn't mean that the hw necessarily already scans it out, but that any
1748 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1749 *
1750 * We have one bit per pipe and per scanout plane type.
1751 */
1752#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1753#define INTEL_FRONTBUFFER_BITS \
1754 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1755#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1756 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1757#define INTEL_FRONTBUFFER_CURSOR(pipe) \
1758 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1759#define INTEL_FRONTBUFFER_SPRITE(pipe) \
1760 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1761#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1762 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
cc36513c
DV		 1763#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1764 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
a071fa00 1765
673a394b 1766struct drm_i915_gem_object {
c397b908 1767 struct drm_gem_object base;
673a394b 1768
37e680a1
CW		 1769 const struct drm_i915_gem_object_ops *ops;
1770
2f633156
BW		 1771 /** List of VMAs backed by this object */
1772 struct list_head vma_list;
1773
c1ad11fc
CW		 1774 /** Stolen memory for this object, instead of being backed by shmem. */
1775 struct drm_mm_node *stolen;
35c20a60 1776 struct list_head global_list;
673a394b 1777
69dc4987 1778 struct list_head ring_list;
b25cb2f8
BW		 1779 /** Used in execbuf to temporarily hold a ref */
1780 struct list_head obj_exec_link;
673a394b
EA		 1781
1782 /**
65ce3027
CW		 1783 * This is set if the object is on the active lists (has pending
1784 * rendering and so a non-zero seqno), and is not set if it i s on
1785 * inactive (ready to be unbound) list.
673a394b 1786 */
0206e353 1787 unsigned int active:1;
673a394b
EA		 1788
1789 /**
1790 * This is set if the object has been written to since last bound
1791 * to the GTT
1792 */
0206e353 1793 unsigned int dirty:1;
778c3544
DV		 1794
1795 /**
1796 * Fence register bits (if any) for this object. Will be set
1797 * as needed when mapped into the GTT.
1798 * Protected by dev->struct_mutex.
778c3544 1799 */
4b9de737 1800 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
778c3544 1801
778c3544
DV		 1802 /**
1803 * Advice: are the backing pages purgeable?
1804 */
0206e353 1805 unsigned int madv:2;
778c3544 1806
778c3544
DV		 1807 /**
1808 * Current tiling mode for the object.
1809 */
0206e353 1810 unsigned int tiling_mode:2;
5d82e3e6
CW		 1811 /**
1812 * Whether the tiling parameters for the currently associated fence
1813 * register have changed. Note that for the purposes of tracking
1814 * tiling changes we also treat the unfenced register, the register
1815 * slot that the object occupies whilst it executes a fenced
1816 * command (such as BLT on gen2/3), as a "fence".
1817 */
1818 unsigned int fence_dirty:1;
778c3544 1819
75e9e915
DV		 1820 /**
1821 * Is the object at the current location in the gtt mappable and
1822 * fenceable? Used to avoid costly recalculations.
1823 */
0206e353 1824 unsigned int map_and_fenceable:1;
75e9e915 1825
fb7d516a
DV		 1826 /**
1827 * Whether the current gtt mapping needs to be mappable (and isn't just
1828 * mappable by accident). Track pin and fault separate for a more
1829 * accurate mappable working set.
1830 */
0206e353
AJ		 1831 unsigned int fault_mappable:1;
1832 unsigned int pin_mappable:1;
cc98b413 1833 unsigned int pin_display:1;
fb7d516a 1834
24f3a8cf
AG		 1835 /*
1836 * Is the object to be mapped as read-only to the GPU
1837 * Only honoured if hardware has relevant pte bit
1838 */
1839 unsigned long gt_ro:1;
651d794f 1840 unsigned int cache_level:3;
93dfb40c 1841
7bddb01f 1842 unsigned int has_aliasing_ppgtt_mapping:1;
74898d7e 1843 unsigned int has_global_gtt_mapping:1;
9da3da66 1844 unsigned int has_dma_mapping:1;
7bddb01f 1845
a071fa00
DV		 1846 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1847
9da3da66 1848 struct sg_table *pages;
a5570178 1849 int pages_pin_count;
673a394b 1850
1286ff73 1851 /* prime dma-buf support */
9a70cc2a
DA		 1852 void *dma_buf_vmapping;
1853 int vmapping_count;
1854
a4872ba6 1855 struct intel_engine_cs *ring;
caea7476 1856
1c293ea3 1857 /** Breadcrumb of last rendering to the buffer. */
0201f1ec
CW		 1858 uint32_t last_read_seqno;
1859 uint32_t last_write_seqno;
caea7476
CW		 1860 /** Breadcrumb of last fenced GPU access to the buffer. */
1861 uint32_t last_fenced_seqno;
673a394b 1862
778c3544 1863 /** Current tiling stride for the object, if it's tiled. */
de151cf6 1864 uint32_t stride;
673a394b 1865
80075d49
DV		 1866 /** References from framebuffers, locks out tiling changes. */
1867 unsigned long framebuffer_references;
1868
280b713b 1869 /** Record of address bit 17 of each page at last unbind. */
d312ec25 1870 unsigned long *bit_17;
280b713b 1871
79e53945 1872 /** User space pin count and filp owning the pin */
aa5f8021 1873 unsigned long user_pin_count;
79e53945 1874 struct drm_file *pin_filp;
71acb5eb
DA		 1875
1876 /** for phy allocated objects */
00731155 1877 drm_dma_handle_t *phys_handle;
673a394b 1878
5cc9ed4b
CW		 1879 union {
1880 struct i915_gem_userptr {
1881 uintptr_t ptr;
1882 unsigned read_only :1;
1883 unsigned workers :4;
1884#define I915_GEM_USERPTR_MAX_WORKERS 15
1885
1886 struct mm_struct *mm;
1887 struct i915_mmu_object *mn;
1888 struct work_struct *work;
1889 } userptr;
1890 };
1891};
62b8b215 1892#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
23010e43 1893
a071fa00
DV		 1894void i915_gem_track_fb(struct drm_i915_gem_object *old,
1895 struct drm_i915_gem_object *new,
1896 unsigned frontbuffer_bits);
1897
673a394b
EA		 1898/**
1899 * Request queue structure.
1900 *
1901 * The request queue allows us to note sequence numbers that have been emitted
1902 * and may be associated with active buffers to be retired.
1903 *
1904 * By keeping this list, we can avoid having to do questionable
1905 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1906 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1907 */
1908struct drm_i915_gem_request {
852835f3 1909 /** On Which ring this request was generated */
a4872ba6 1910 struct intel_engine_cs *ring;
852835f3 1911
673a394b
EA		 1912 /** GEM sequence number associated with this request. */
1913 uint32_t seqno;
1914
7d736f4f
MK		 1915 /** Position in the ringbuffer of the start of the request */
1916 u32 head;
1917
1918 /** Position in the ringbuffer of the end of the request */
a71d8d94
CW		 1919 u32 tail;
1920
0e50e96b 1921 /** Context related to this request */
273497e5 1922 struct intel_context *ctx;
0e50e96b 1923
7d736f4f
MK		 1924 /** Batch buffer related to this request if any */
1925 struct drm_i915_gem_object *batch_obj;
1926
673a394b
EA		 1927 /** Time at which this request was emitted, in jiffies. */
1928 unsigned long emitted_jiffies;
1929
b962442e 1930 /** global list entry for this request */
673a394b 1931 struct list_head list;
b962442e 1932
f787a5f5 1933 struct drm_i915_file_private *file_priv;
b962442e
EA		 1934 /** file_priv list entry for this request */
1935 struct list_head client_list;
673a394b
EA		 1936};
1937
1938struct drm_i915_file_private {
b29c19b6 1939 struct drm_i915_private *dev_priv;
ab0e7ff9 1940 struct drm_file *file;
b29c19b6 1941
673a394b 1942 struct {
99057c81 1943 spinlock_t lock;
b962442e 1944 struct list_head request_list;
b29c19b6 1945 struct delayed_work idle_work;
673a394b 1946 } mm;
40521054 1947 struct idr context_idr;
e59ec13d 1948
b29c19b6 1949 atomic_t rps_wait_boost;
a4872ba6 1950 struct intel_engine_cs *bsd_ring;
673a394b
EA		 1951};
1952
351e3db2
BV		 1953/*
1954 * A command that requires special handling by the command parser.
1955 */
1956struct drm_i915_cmd_descriptor {
1957 /*
1958 * Flags describing how the command parser processes the command.
1959 *
1960 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1961 * a length mask if not set
1962 * CMD_DESC_SKIP: The command is allowed but does not follow the
1963 * standard length encoding for the opcode range in
1964 * which it falls
1965 * CMD_DESC_REJECT: The command is never allowed
1966 * CMD_DESC_REGISTER: The command should be checked against the
1967 * register whitelist for the appropriate ring
1968 * CMD_DESC_MASTER: The command is allowed if the submitting process
1969 * is the DRM master
1970 */
1971 u32 flags;
1972#define CMD_DESC_FIXED (1<<0)
1973#define CMD_DESC_SKIP (1<<1)
1974#define CMD_DESC_REJECT (1<<2)
1975#define CMD_DESC_REGISTER (1<<3)
1976#define CMD_DESC_BITMASK (1<<4)
1977#define CMD_DESC_MASTER (1<<5)
1978
1979 /*
1980 * The command's unique identification bits and the bitmask to get them.
1981 * This isn't strictly the opcode field as defined in the spec and may
1982 * also include type, subtype, and/or subop fields.
1983 */
1984 struct {
1985 u32 value;
1986 u32 mask;
1987 } cmd;
1988
1989 /*
1990 * The command's length. The command is either fixed length (i.e. does
1991 * not include a length field) or has a length field mask. The flag
1992 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1993 * a length mask. All command entries in a command table must include
1994 * length information.
1995 */
1996 union {
1997 u32 fixed;
1998 u32 mask;
1999 } length;
2000
2001 /*
2002 * Describes where to find a register address in the command to check
2003 * against the ring's register whitelist. Only valid if flags has the
2004 * CMD_DESC_REGISTER bit set.
2005 */
2006 struct {
2007 u32 offset;
2008 u32 mask;
2009 } reg;
2010
2011#define MAX_CMD_DESC_BITMASKS 3
2012 /*
2013 * Describes command checks where a particular dword is masked and
2014 * compared against an expected value. If the command does not match
2015 * the expected value, the parser rejects it. Only valid if flags has
2016 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2017 * are valid.
d4d48035
BV		 2018 *
2019 * If the check specifies a non-zero condition_mask then the parser
2020 * only performs the check when the bits specified by condition_mask
2021 * are non-zero.
351e3db2
BV		 2022 */
2023 struct {
2024 u32 offset;
2025 u32 mask;
2026 u32 expected;
d4d48035
BV		 2027 u32 condition_offset;
2028 u32 condition_mask;
351e3db2
BV		 2029 } bits[MAX_CMD_DESC_BITMASKS];
2030};
2031
2032/*
2033 * A table of commands requiring special handling by the command parser.
2034 *
2035 * Each ring has an array of tables. Each table consists of an array of command
2036 * descriptors, which must be sorted with command opcodes in ascending order.
2037 */
2038struct drm_i915_cmd_table {
2039 const struct drm_i915_cmd_descriptor *table;
2040 int count;
2041};
2042
dbbe9127 2043/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
7312e2dd
CW		 2044#define __I915__(p) ({ \
2045 struct drm_i915_private *__p; \
2046 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2047 __p = (struct drm_i915_private *)p; \
2048 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2049 __p = to_i915((struct drm_device *)p); \
2050 else \
2051 BUILD_BUG(); \
2052 __p; \
2053})
dbbe9127 2054#define INTEL_INFO(p) (&__I915__(p)->info)
87f1f465 2055#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
cae5852d 2056
87f1f465
CW		 2057#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2058#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
cae5852d 2059#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
87f1f465 2060#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
cae5852d 2061#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
87f1f465
CW		 2062#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2063#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
cae5852d
ZN		 2064#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2065#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2066#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
87f1f465 2067#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
cae5852d 2068#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
87f1f465
CW		 2069#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2070#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
cae5852d
ZN		 2071#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2072#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
87f1f465 2073#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
4b65177b 2074#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
87f1f465
CW		 2075#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2076 INTEL_DEVID(dev) == 0x0152 || \
2077 INTEL_DEVID(dev) == 0x015a)
2078#define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2079 INTEL_DEVID(dev) == 0x0106 || \
2080 INTEL_DEVID(dev) == 0x010A)
70a3eb7a 2081#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
6df4027b 2082#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
4cae9ae0 2083#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
8179f1f0 2084#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
cae5852d 2085#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
ed1c9e2c 2086#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
87f1f465 2087 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
5dd8c4c3 2088#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
87f1f465
CW		 2089 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2090 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2091 (INTEL_DEVID(dev) & 0xf) == 0xe))
5dd8c4c3 2092#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
87f1f465 2093 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
5dd8c4c3 2094#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
9435373e 2095#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
87f1f465 2096 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
9bbfd20a 2097/* ULX machines are also considered ULT. */
87f1f465
CW		 2098#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2099 INTEL_DEVID(dev) == 0x0A1E)
b833d685 2100#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
cae5852d 2101
85436696
JB		 2102/*
2103 * The genX designation typically refers to the render engine, so render
2104 * capability related checks should use IS_GEN, while display and other checks
2105 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2106 * chips, etc.).
2107 */
cae5852d
ZN		 2108#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2109#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2110#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2111#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2112#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
85436696 2113#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
d2980845 2114#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
cae5852d 2115
73ae478c
BW		 2116#define RENDER_RING (1<<RCS)
2117#define BSD_RING (1<<VCS)
2118#define BLT_RING (1<<BCS)
2119#define VEBOX_RING (1<<VECS)
845f74a7 2120#define BSD2_RING (1<<VCS2)
63c42e56 2121#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
845f74a7 2122#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
63c42e56
BW		 2123#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2124#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2125#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2126#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2127 to_i915(dev)->ellc_size)
cae5852d
ZN		 2128#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2129
254f965c 2130#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
d7f621e5 2131#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
7365fb78
JB		 2132#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2133#define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
692ef70c
JB		 2134#define USES_PPGTT(dev) (i915.enable_ppgtt)
2135#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
1d2a314c 2136
05394f39 2137#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
cae5852d
ZN		 2138#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2139
b45305fc
DV		 2140/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2141#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
4e6b788c
DV		 2142/*
2143 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2144 * even when in MSI mode. This results in spurious interrupt warnings if the
2145 * legacy irq no. is shared with another device. The kernel then disables that
2146 * interrupt source and so prevents the other device from working properly.
2147 */
2148#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2149#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
b45305fc 2150
cae5852d
ZN		 2151/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2152 * rows, which changed the alignment requirements and fence programming.
2153 */
2154#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2155 IS_I915GM(dev)))
2156#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2157#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2158#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
cae5852d
ZN		 2159#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2160#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
cae5852d
ZN		 2161
2162#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2163#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
3a77c4c4 2164#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
cae5852d 2165
2a114cc1 2166#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
f5adf94e 2167
dd93be58 2168#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
30568c45 2169#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
ed8546ac 2170#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
6157d3c8 2171#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
fd7f8cce 2172 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
affa9354 2173
17a303ec
PZ		 2174#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2175#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2176#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2177#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2178#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2179#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2180
2c1792a1 2181#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
eb877ebf 2182#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
cae5852d
ZN		 2183#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2184#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
40c7ead9 2185#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
45e6e3a1 2186#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
cae5852d 2187
5fafe292
SJ		 2188#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2189
040d2baa
BW		 2190/* DPF == dynamic parity feature */
2191#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2192#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
e1ef7cc2 2193
c8735b0c
BW		 2194#define GT_FREQUENCY_MULTIPLIER 50
2195
05394f39
CW		 2196#include "i915_trace.h"
2197
baa70943 2198extern const struct drm_ioctl_desc i915_ioctls[];
b3a83639
DA		 2199extern int i915_max_ioctl;
2200
6a9ee8af
DA		 2201extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2202extern int i915_resume(struct drm_device *dev);
7c1c2871
DA		 2203extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2204extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2205
d330a953
JN		 2206/* i915_params.c */
2207struct i915_params {
2208 int modeset;
2209 int panel_ignore_lid;
2210 unsigned int powersave;
2211 int semaphores;
2212 unsigned int lvds_downclock;
2213 int lvds_channel_mode;
2214 int panel_use_ssc;
2215 int vbt_sdvo_panel_type;
2216 int enable_rc6;
2217 int enable_fbc;
d330a953 2218 int enable_ppgtt;
127f1003 2219 int enable_execlists;
d330a953
JN		 2220 int enable_psr;
2221 unsigned int preliminary_hw_support;
2222 int disable_power_well;
2223 int enable_ips;
e5aa6541 2224 int invert_brightness;
351e3db2 2225 int enable_cmd_parser;
e5aa6541
DL		 2226 /* leave bools at the end to not create holes */
2227 bool enable_hangcheck;
2228 bool fastboot;
d330a953
JN		 2229 bool prefault_disable;
2230 bool reset;
a0bae57f 2231 bool disable_display;
7a10dfa6 2232 bool disable_vtd_wa;
84c33a64 2233 int use_mmio_flip;
5978118c 2234 bool mmio_debug;
d330a953
JN		 2235};
2236extern struct i915_params i915 __read_mostly;
2237
1da177e4 2238 /* i915_dma.c */
d05c617e 2239void i915_update_dri1_breadcrumb(struct drm_device *dev);
84b1fd10 2240extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 2241extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 2242extern int i915_driver_unload(struct drm_device *);
2885f6ac 2243extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
84b1fd10 2244extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac 2245extern void i915_driver_preclose(struct drm_device *dev,
2885f6ac 2246 struct drm_file *file);
673a394b 2247extern void i915_driver_postclose(struct drm_device *dev,
2885f6ac 2248 struct drm_file *file);
84b1fd10 2249extern int i915_driver_device_is_agp(struct drm_device * dev);
c43b5634 2250#ifdef CONFIG_COMPAT
0d6aa60b
DA		 2251extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2252 unsigned long arg);
c43b5634 2253#endif
673a394b 2254extern int i915_emit_box(struct drm_device *dev,
c4e7a414
CW		 2255 struct drm_clip_rect *box,
2256 int DR1, int DR4);
8e96d9c4 2257extern int intel_gpu_reset(struct drm_device *dev);
d4b8bb2a 2258extern int i915_reset(struct drm_device *dev);
7648fa99
JB		 2259extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2260extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2261extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2262extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
650ad970 2263int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1d0d343a 2264void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
7648fa99 2265
1da177e4 2266/* i915_irq.c */
10cd45b6 2267void i915_queue_hangcheck(struct drm_device *dev);
58174462
MK		 2268__printf(3, 4)
2269void i915_handle_error(struct drm_device *dev, bool wedged,
2270 const char *fmt, ...);
1da177e4 2271
76c3552f
D		 2272void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2273 int new_delay);
f71d4af4 2274extern void intel_irq_init(struct drm_device *dev);
20afbda2 2275extern void intel_hpd_init(struct drm_device *dev);
907b28c5
CW		 2276
2277extern void intel_uncore_sanitize(struct drm_device *dev);
10018603
ID		 2278extern void intel_uncore_early_sanitize(struct drm_device *dev,
2279 bool restore_forcewake);
907b28c5 2280extern void intel_uncore_init(struct drm_device *dev);
907b28c5 2281extern void intel_uncore_check_errors(struct drm_device *dev);
aec347ab 2282extern void intel_uncore_fini(struct drm_device *dev);
156c7ca0 2283extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
b1f14ad0 2284
7c463586 2285void
50227e1c 2286i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2287 u32 status_mask);
7c463586
KP		 2288
2289void
50227e1c 2290i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2291 u32 status_mask);
7c463586 2292
f8b79e58
ID		 2293void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2294void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2295
673a394b
EA		 2296/* i915_gem.c */
2297int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2298 struct drm_file *file_priv);
2299int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2300 struct drm_file *file_priv);
2301int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2302 struct drm_file *file_priv);
2303int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2304 struct drm_file *file_priv);
2305int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2306 struct drm_file *file_priv);
de151cf6
JB		 2307int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2308 struct drm_file *file_priv);
673a394b
EA		 2309int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2310 struct drm_file *file_priv);
2311int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2312 struct drm_file *file_priv);
ba8b7ccb
OM		 2313void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2314 struct intel_engine_cs *ring);
2315void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2316 struct drm_file *file,
2317 struct intel_engine_cs *ring,
2318 struct drm_i915_gem_object *obj);
a83014d3
OM		 2319int i915_gem_ringbuffer_submission(struct drm_device *dev,
2320 struct drm_file *file,
2321 struct intel_engine_cs *ring,
2322 struct intel_context *ctx,
2323 struct drm_i915_gem_execbuffer2 *args,
2324 struct list_head *vmas,
2325 struct drm_i915_gem_object *batch_obj,
2326 u64 exec_start, u32 flags);
673a394b
EA		 2327int i915_gem_execbuffer(struct drm_device *dev, void *data,
2328 struct drm_file *file_priv);
76446cac
JB		 2329int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2330 struct drm_file *file_priv);
673a394b
EA		 2331int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2332 struct drm_file *file_priv);
2333int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2334 struct drm_file *file_priv);
2335int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2336 struct drm_file *file_priv);
199adf40
BW		 2337int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2338 struct drm_file *file);
2339int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2340 struct drm_file *file);
673a394b
EA		 2341int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2342 struct drm_file *file_priv);
3ef94daa
CW		 2343int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2344 struct drm_file *file_priv);
673a394b
EA		 2345int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2346 struct drm_file *file_priv);
2347int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2348 struct drm_file *file_priv);
2349int i915_gem_set_tiling(struct drm_device *dev, void *data,
2350 struct drm_file *file_priv);
2351int i915_gem_get_tiling(struct drm_device *dev, void *data,
2352 struct drm_file *file_priv);
5cc9ed4b
CW		 2353int i915_gem_init_userptr(struct drm_device *dev);
2354int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2355 struct drm_file *file);
5a125c3c
EA		 2356int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2357 struct drm_file *file_priv);
23ba4fd0
BW		 2358int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2359 struct drm_file *file_priv);
673a394b 2360void i915_gem_load(struct drm_device *dev);
42dcedd4
CW		 2361void *i915_gem_object_alloc(struct drm_device *dev);
2362void i915_gem_object_free(struct drm_i915_gem_object *obj);
37e680a1
CW		 2363void i915_gem_object_init(struct drm_i915_gem_object *obj,
2364 const struct drm_i915_gem_object_ops *ops);
05394f39
CW		 2365struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2366 size_t size);
7e0d96bc
BW		 2367void i915_init_vm(struct drm_i915_private *dev_priv,
2368 struct i915_address_space *vm);
673a394b 2369void i915_gem_free_object(struct drm_gem_object *obj);
2f633156 2370void i915_gem_vma_destroy(struct i915_vma *vma);
42dcedd4 2371
1ec9e26d
DV		 2372#define PIN_MAPPABLE 0x1
2373#define PIN_NONBLOCK 0x2
bf3d149b 2374#define PIN_GLOBAL 0x4
d23db88c
CW		 2375#define PIN_OFFSET_BIAS 0x8
2376#define PIN_OFFSET_MASK (~4095)
2021746e 2377int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
c37e2204 2378 struct i915_address_space *vm,
2021746e 2379 uint32_t alignment,
d23db88c 2380 uint64_t flags);
07fe0b12 2381int __must_check i915_vma_unbind(struct i915_vma *vma);
dd624afd 2382int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
48018a57 2383void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
05394f39 2384void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
673a394b 2385void i915_gem_lastclose(struct drm_device *dev);
f787a5f5 2386
4c914c0c
BV		 2387int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2388 int *needs_clflush);
2389
37e680a1 2390int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
9da3da66
CW		 2391static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2392{
67d5a50c
ID		 2393 struct sg_page_iter sg_iter;
2394
2395 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2db76d7c 2396 return sg_page_iter_page(&sg_iter);
67d5a50c
ID		 2397
2398 return NULL;
9da3da66 2399}
a5570178
CW		 2400static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2401{
2402 BUG_ON(obj->pages == NULL);
2403 obj->pages_pin_count++;
2404}
2405static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2406{
2407 BUG_ON(obj->pages_pin_count == 0);
2408 obj->pages_pin_count--;
2409}
2410
54cf91dc 2411int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2911a35b 2412int i915_gem_object_sync(struct drm_i915_gem_object *obj,
a4872ba6 2413 struct intel_engine_cs *to);
e2d05a8b 2414void i915_vma_move_to_active(struct i915_vma *vma,
a4872ba6 2415 struct intel_engine_cs *ring);
ff72145b
DA		 2416int i915_gem_dumb_create(struct drm_file *file_priv,
2417 struct drm_device *dev,
2418 struct drm_mode_create_dumb *args);
2419int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2420 uint32_t handle, uint64_t *offset);
f787a5f5
CW		 2421/**
2422 * Returns true if seq1 is later than seq2.
2423 */
2424static inline bool
2425i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2426{
2427 return (int32_t)(seq1 - seq2) >= 0;
2428}
2429
fca26bb4
MK		 2430int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2431int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
06d98131 2432int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
d9e86c0e 2433int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2021746e 2434
d8ffa60b
DV		 2435bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2436void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
1690e1eb 2437
8d9fc7fd 2438struct drm_i915_gem_request *
a4872ba6 2439i915_gem_find_active_request(struct intel_engine_cs *ring);
8d9fc7fd 2440
b29c19b6 2441bool i915_gem_retire_requests(struct drm_device *dev);
a4872ba6 2442void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
33196ded 2443int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
d6b2c790 2444 bool interruptible);
84c33a64
SG		 2445int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2446
1f83fee0
DV		 2447static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2448{
2449 return unlikely(atomic_read(&error->reset_counter)
2ac0f450 2450 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
1f83fee0
DV		 2451}
2452
2453static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2454{
2ac0f450
MK		 2455 return atomic_read(&error->reset_counter) & I915_WEDGED;
2456}
2457
2458static inline u32 i915_reset_count(struct i915_gpu_error *error)
2459{
2460 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
1f83fee0 2461}
a71d8d94 2462
88b4aa87
MK		 2463static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2464{
2465 return dev_priv->gpu_error.stop_rings == 0 ||
2466 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2467}
2468
2469static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2470{
2471 return dev_priv->gpu_error.stop_rings == 0 ||
2472 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2473}
2474
069efc1d 2475void i915_gem_reset(struct drm_device *dev);
000433b6 2476bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
a8198eea 2477int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1070a42b 2478int __must_check i915_gem_init(struct drm_device *dev);
a83014d3 2479int i915_gem_init_rings(struct drm_device *dev);
f691e2f4 2480int __must_check i915_gem_init_hw(struct drm_device *dev);
a4872ba6 2481int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
f691e2f4 2482void i915_gem_init_swizzling(struct drm_device *dev);
79e53945 2483void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
b2da9fe5 2484int __must_check i915_gpu_idle(struct drm_device *dev);
45c5f202 2485int __must_check i915_gem_suspend(struct drm_device *dev);
a4872ba6 2486int __i915_add_request(struct intel_engine_cs *ring,
0025c077 2487 struct drm_file *file,
7d736f4f 2488 struct drm_i915_gem_object *batch_obj,
0025c077
MK		 2489 u32 *seqno);
2490#define i915_add_request(ring, seqno) \
854c94a7 2491 __i915_add_request(ring, NULL, NULL, seqno)
a4872ba6 2492int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
199b2bc2 2493 uint32_t seqno);
de151cf6 2494int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2021746e
CW		 2495int __must_check
2496i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2497 bool write);
2498int __must_check
dabdfe02
CW		 2499i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2500int __must_check
2da3b9b9
CW		 2501i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2502 u32 alignment,
a4872ba6 2503 struct intel_engine_cs *pipelined);
cc98b413 2504void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
00731155 2505int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
6eeefaf3 2506 int align);
b29c19b6 2507int i915_gem_open(struct drm_device *dev, struct drm_file *file);
05394f39 2508void i915_gem_release(struct drm_device *dev, struct drm_file *file);
673a394b 2509
0fa87796
ID		 2510uint32_t
2511i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
467cffba 2512uint32_t
d865110c
ID		 2513i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2514 int tiling_mode, bool fenced);
467cffba 2515
e4ffd173
CW		 2516int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2517 enum i915_cache_level cache_level);
2518
1286ff73
DV		 2519struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2520 struct dma_buf *dma_buf);
2521
2522struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2523 struct drm_gem_object *gem_obj, int flags);
2524
19b2dbde
CW		 2525void i915_gem_restore_fences(struct drm_device *dev);
2526
a70a3148
BW		 2527unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2528 struct i915_address_space *vm);
2529bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2530bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2531 struct i915_address_space *vm);
2532unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2533 struct i915_address_space *vm);
2534struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2535 struct i915_address_space *vm);
accfef2e
BW		 2536struct i915_vma *
2537i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2538 struct i915_address_space *vm);
5c2abbea
BW		 2539
2540struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
d7f46fc4
BW		 2541static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2542 struct i915_vma *vma;
2543 list_for_each_entry(vma, &obj->vma_list, vma_link)
2544 if (vma->pin_count > 0)
2545 return true;
2546 return false;
2547}
5c2abbea 2548
a70a3148 2549/* Some GGTT VM helpers */
5dc383b0 2550#define i915_obj_to_ggtt(obj) \
a70a3148
BW		 2551 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2552static inline bool i915_is_ggtt(struct i915_address_space *vm)
2553{
2554 struct i915_address_space *ggtt =
2555 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2556 return vm == ggtt;
2557}
2558
841cd773
DV		 2559static inline struct i915_hw_ppgtt *
2560i915_vm_to_ppgtt(struct i915_address_space *vm)
2561{
2562 WARN_ON(i915_is_ggtt(vm));
2563
2564 return container_of(vm, struct i915_hw_ppgtt, base);
2565}
2566
2567
a70a3148
BW		 2568static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2569{
5dc383b0 2570 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
a70a3148
BW		 2571}
2572
2573static inline unsigned long
2574i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2575{
5dc383b0 2576 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
a70a3148
BW		 2577}
2578
2579static inline unsigned long
2580i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2581{
5dc383b0 2582 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
a70a3148 2583}
c37e2204
BW		 2584
2585static inline int __must_check
2586i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2587 uint32_t alignment,
1ec9e26d 2588 unsigned flags)
c37e2204 2589{
5dc383b0
DV		 2590 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2591 alignment, flags | PIN_GLOBAL);
c37e2204 2592}
a70a3148 2593
b287110e
DV		 2594static inline int
2595i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2596{
2597 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2598}
2599
2600void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2601
254f965c 2602/* i915_gem_context.c */
8245be31 2603int __must_check i915_gem_context_init(struct drm_device *dev);
254f965c 2604void i915_gem_context_fini(struct drm_device *dev);
acce9ffa 2605void i915_gem_context_reset(struct drm_device *dev);
e422b888 2606int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2fa48d8d 2607int i915_gem_context_enable(struct drm_i915_private *dev_priv);
254f965c 2608void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
a4872ba6 2609int i915_switch_context(struct intel_engine_cs *ring,
273497e5
OM		 2610 struct intel_context *to);
2611struct intel_context *
41bde553 2612i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
dce3271b 2613void i915_gem_context_free(struct kref *ctx_ref);
8c857917
OM		 2614struct drm_i915_gem_object *
2615i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
273497e5 2616static inline void i915_gem_context_reference(struct intel_context *ctx)
dce3271b 2617{
691e6415 2618 kref_get(&ctx->ref);
dce3271b
MK		 2619}
2620
273497e5 2621static inline void i915_gem_context_unreference(struct intel_context *ctx)
dce3271b 2622{
691e6415 2623 kref_put(&ctx->ref, i915_gem_context_free);
dce3271b
MK		 2624}
2625
273497e5 2626static inline bool i915_gem_context_is_default(const struct intel_context *c)
3fac8978 2627{
821d66dd 2628 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3fac8978
MK		 2629}
2630
84624813
BW		 2631int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2632 struct drm_file *file);
2633int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2634 struct drm_file *file);
1286ff73 2635
679845ed
BW		 2636/* i915_gem_evict.c */
2637int __must_check i915_gem_evict_something(struct drm_device *dev,
2638 struct i915_address_space *vm,
2639 int min_size,
2640 unsigned alignment,
2641 unsigned cache_level,
d23db88c
CW		 2642 unsigned long start,
2643 unsigned long end,
1ec9e26d 2644 unsigned flags);
679845ed
BW		 2645int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2646int i915_gem_evict_everything(struct drm_device *dev);
1d2a314c 2647
0260c420 2648/* belongs in i915_gem_gtt.h */
d09105c6 2649static inline void i915_gem_chipset_flush(struct drm_device *dev)
e76e9aeb
BW		 2650{
2651 if (INTEL_INFO(dev)->gen < 6)
2652 intel_gtt_chipset_flush();
2653}
246cbfb5 2654
9797fbfb
CW		 2655/* i915_gem_stolen.c */
2656int i915_gem_init_stolen(struct drm_device *dev);
5e59f717 2657int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
11be49eb 2658void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
9797fbfb 2659void i915_gem_cleanup_stolen(struct drm_device *dev);
0104fdbb
CW		 2660struct drm_i915_gem_object *
2661i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
866d12b4
CW		 2662struct drm_i915_gem_object *
2663i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2664 u32 stolen_offset,
2665 u32 gtt_offset,
2666 u32 size);
9797fbfb 2667
673a394b 2668/* i915_gem_tiling.c */
2c1792a1 2669static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
e9b73c67 2670{
50227e1c 2671 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
e9b73c67
CW		 2672
2673 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2674 obj->tiling_mode != I915_TILING_NONE;
2675}
2676
673a394b 2677void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
05394f39
CW		 2678void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2679void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
673a394b
EA		 2680
2681/* i915_gem_debug.c */
23bc5982
CW		 2682#if WATCH_LISTS
2683int i915_verify_lists(struct drm_device *dev);
673a394b 2684#else
23bc5982 2685#define i915_verify_lists(dev) 0
673a394b 2686#endif
1da177e4 2687
2017263e 2688/* i915_debugfs.c */
27c202ad
BG		 2689int i915_debugfs_init(struct drm_minor *minor);
2690void i915_debugfs_cleanup(struct drm_minor *minor);
f8c168fa 2691#ifdef CONFIG_DEBUG_FS
07144428
DL		 2692void intel_display_crc_init(struct drm_device *dev);
2693#else
f8c168fa 2694static inline void intel_display_crc_init(struct drm_device *dev) {}
07144428 2695#endif
84734a04
MK		 2696
2697/* i915_gpu_error.c */
edc3d884
MK		 2698__printf(2, 3)
2699void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
fc16b48b
MK		 2700int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2701 const struct i915_error_state_file_priv *error);
4dc955f7 2702int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
0a4cd7c8 2703 struct drm_i915_private *i915,
4dc955f7
MK		 2704 size_t count, loff_t pos);
2705static inline void i915_error_state_buf_release(
2706 struct drm_i915_error_state_buf *eb)
2707{
2708 kfree(eb->buf);
2709}
58174462
MK		 2710void i915_capture_error_state(struct drm_device *dev, bool wedge,
2711 const char *error_msg);
84734a04
MK		 2712void i915_error_state_get(struct drm_device *dev,
2713 struct i915_error_state_file_priv *error_priv);
2714void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2715void i915_destroy_error_state(struct drm_device *dev);
2716
2717void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
0a4cd7c8 2718const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2017263e 2719
351e3db2 2720/* i915_cmd_parser.c */
d728c8ef 2721int i915_cmd_parser_get_version(void);
a4872ba6
OM		 2722int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2723void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2724bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2725int i915_parse_cmds(struct intel_engine_cs *ring,
351e3db2
BV		 2726 struct drm_i915_gem_object *batch_obj,
2727 u32 batch_start_offset,
2728 bool is_master);
2729
317c35d1
JB		 2730/* i915_suspend.c */
2731extern int i915_save_state(struct drm_device *dev);
2732extern int i915_restore_state(struct drm_device *dev);
0a3e67a4 2733
d8157a36
DV		 2734/* i915_ums.c */
2735void i915_save_display_reg(struct drm_device *dev);
2736void i915_restore_display_reg(struct drm_device *dev);
317c35d1 2737
0136db58
BW		 2738/* i915_sysfs.c */
2739void i915_setup_sysfs(struct drm_device *dev_priv);
2740void i915_teardown_sysfs(struct drm_device *dev_priv);
2741
f899fc64
CW		 2742/* intel_i2c.c */
2743extern int intel_setup_gmbus(struct drm_device *dev);
2744extern void intel_teardown_gmbus(struct drm_device *dev);
8f375e10 2745static inline bool intel_gmbus_is_port_valid(unsigned port)
3bd7d909 2746{
2ed06c93 2747 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
3bd7d909
DK		 2748}
2749
2750extern struct i2c_adapter *intel_gmbus_get_adapter(
2751 struct drm_i915_private *dev_priv, unsigned port);
e957d772
CW		 2752extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2753extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
8f375e10 2754static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
b8232e90
CW		 2755{
2756 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2757}
f899fc64
CW		 2758extern void intel_i2c_reset(struct drm_device *dev);
2759
3b617967 2760/* intel_opregion.c */
9c4b0a68 2761struct intel_encoder;
44834a67 2762#ifdef CONFIG_ACPI
27d50c82 2763extern int intel_opregion_setup(struct drm_device *dev);
44834a67
CW		 2764extern void intel_opregion_init(struct drm_device *dev);
2765extern void intel_opregion_fini(struct drm_device *dev);
3b617967 2766extern void intel_opregion_asle_intr(struct drm_device *dev);
9c4b0a68
JN		 2767extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2768 bool enable);
ecbc5cf3
JN		 2769extern int intel_opregion_notify_adapter(struct drm_device *dev,
2770 pci_power_t state);
65e082c9 2771#else
27d50c82 2772static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
44834a67
CW		 2773static inline void intel_opregion_init(struct drm_device *dev) { return; }
2774static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3b617967 2775static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
9c4b0a68
JN		 2776static inline int
2777intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2778{
2779 return 0;
2780}
ecbc5cf3
JN		 2781static inline int
2782intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2783{
2784 return 0;
2785}
65e082c9 2786#endif
8ee1c3db 2787
723bfd70
JB		 2788/* intel_acpi.c */
2789#ifdef CONFIG_ACPI
2790extern void intel_register_dsm_handler(void);
2791extern void intel_unregister_dsm_handler(void);
2792#else
2793static inline void intel_register_dsm_handler(void) { return; }
2794static inline void intel_unregister_dsm_handler(void) { return; }
2795#endif /* CONFIG_ACPI */
2796
79e53945 2797/* modesetting */
f817586c 2798extern void intel_modeset_init_hw(struct drm_device *dev);
7d708ee4 2799extern void intel_modeset_suspend_hw(struct drm_device *dev);
79e53945 2800extern void intel_modeset_init(struct drm_device *dev);
2c7111db 2801extern void intel_modeset_gem_init(struct drm_device *dev);
79e53945 2802extern void intel_modeset_cleanup(struct drm_device *dev);
4932e2c3 2803extern void intel_connector_unregister(struct intel_connector *);
28d52043 2804extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
45e2b5f6
DV		 2805extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2806 bool force_restore);
44cec740 2807extern void i915_redisable_vga(struct drm_device *dev);
04098753 2808extern void i915_redisable_vga_power_on(struct drm_device *dev);
ee5382ae 2809extern bool intel_fbc_enabled(struct drm_device *dev);
c5ad011d 2810extern void gen8_fbc_sw_flush(struct drm_device *dev, u32 value);
43a9539f 2811extern void intel_disable_fbc(struct drm_device *dev);
7648fa99 2812extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
dde86e2d 2813extern void intel_init_pch_refclk(struct drm_device *dev);
3b8d8d91 2814extern void gen6_set_rps(struct drm_device *dev, u8 val);
c76bb61a
DS		 2815extern void bdw_software_turbo(struct drm_device *dev);
2816extern void gen8_flip_interrupt(struct drm_device *dev);
0a073b84 2817extern void valleyview_set_rps(struct drm_device *dev, u8 val);
5209b1f4
ID		 2818extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2819 bool enable);
0206e353
AJ		 2820extern void intel_detect_pch(struct drm_device *dev);
2821extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
0136db58 2822extern int intel_enable_rc6(const struct drm_device *dev);
3bad0781 2823
2911a35b 2824extern bool i915_semaphore_is_enabled(struct drm_device *dev);
c0c7babc
BW		 2825int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2826 struct drm_file *file);
b6359918
MK		 2827int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2828 struct drm_file *file);
575155a9 2829
84c33a64
SG		 2830void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2831
6ef3d427
CW		 2832/* overlay */
2833extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
edc3d884
MK		 2834extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2835 struct intel_overlay_error_state *error);
c4a1d9e4
CW		 2836
2837extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
edc3d884 2838extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
c4a1d9e4
CW		 2839 struct drm_device *dev,
2840 struct intel_display_error_state *error);
6ef3d427 2841
b7287d80
BW		 2842/* On SNB platform, before reading ring registers forcewake bit
2843 * must be set to prevent GT core from power down and stale values being
2844 * returned.
2845 */
c8d9a590
D		 2846void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2847void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
e998c40f 2848void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
b7287d80 2849
42c0526c
BW		 2850int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2851int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
59de0813
JN		 2852
2853/* intel_sideband.c */
64936258
JN		 2854u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2855void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2856u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
e9f882a3
JN		 2857u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2858void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2859u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2860void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2861u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2862void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
f3419158
JB		 2863u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2864void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
e9f882a3
JN		 2865u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2866void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
5e69f97f
CML		 2867u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2868void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
59de0813
JN		 2869u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2870 enum intel_sbi_destination destination);
2871void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2872 enum intel_sbi_destination destination);
e9fe51c6
SK		 2873u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2874void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
0a073b84 2875
2ec3815f
VS		 2876int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2877int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
42c0526c 2878
c8d9a590
D		 2879#define FORCEWAKE_RENDER (1 << 0)
2880#define FORCEWAKE_MEDIA (1 << 1)
2881#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2882
2883
0b274481
BW		 2884#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2885#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2886
2887#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2888#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2889#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2890#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2891
2892#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2893#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2894#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2895#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2896
698b3135
CW		 2897/* Be very careful with read/write 64-bit values. On 32-bit machines, they
2898 * will be implemented using 2 32-bit writes in an arbitrary order with
2899 * an arbitrary delay between them. This can cause the hardware to
2900 * act upon the intermediate value, possibly leading to corruption and
2901 * machine death. You have been warned.
2902 */
0b274481
BW		 2903#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2904#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
cae5852d 2905
50877445
CW		 2906#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2907 u32 upper = I915_READ(upper_reg); \
2908 u32 lower = I915_READ(lower_reg); \
2909 u32 tmp = I915_READ(upper_reg); \
2910 if (upper != tmp) { \
2911 upper = tmp; \
2912 lower = I915_READ(lower_reg); \
2913 WARN_ON(I915_READ(upper_reg) != upper); \
2914 } \
2915 (u64)upper << 32 | lower; })
2916
cae5852d
ZN		 2917#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2918#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2919
55bc60db
VS		 2920/* "Broadcast RGB" property */
2921#define INTEL_BROADCAST_RGB_AUTO 0
2922#define INTEL_BROADCAST_RGB_FULL 1
2923#define INTEL_BROADCAST_RGB_LIMITED 2
ba4f01a3 2924
766aa1c4
VS		 2925static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2926{
92e23b99 2927 if (IS_VALLEYVIEW(dev))
766aa1c4 2928 return VLV_VGACNTRL;
92e23b99
SJ		 2929 else if (INTEL_INFO(dev)->gen >= 5)
2930 return CPU_VGACNTRL;
766aa1c4
VS		 2931 else
2932 return VGACNTRL;
2933}
2934
2bb4629a
VS		 2935static inline void __user *to_user_ptr(u64 address)
2936{
2937 return (void __user *)(uintptr_t)address;
2938}
2939
df97729f
ID		 2940static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2941{
2942 unsigned long j = msecs_to_jiffies(m);
2943
2944 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2945}
2946
2947static inline unsigned long
2948timespec_to_jiffies_timeout(const struct timespec *value)
2949{
2950 unsigned long j = timespec_to_jiffies(value);
2951
2952 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2953}
2954
dce56b3c
PZ		 2955/*
2956 * If you need to wait X milliseconds between events A and B, but event B
2957 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2958 * when event A happened, then just before event B you call this function and
2959 * pass the timestamp as the first argument, and X as the second argument.
2960 */
2961static inline void
2962wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2963{
ec5e0cfb 2964 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
dce56b3c
PZ		 2965
2966 /*
2967 * Don't re-read the value of "jiffies" every time since it may change
2968 * behind our back and break the math.
2969 */
2970 tmp_jiffies = jiffies;
2971 target_jiffies = timestamp_jiffies +
2972 msecs_to_jiffies_timeout(to_wait_ms);
2973
2974 if (time_after(target_jiffies, tmp_jiffies)) {
ec5e0cfb
ID		 2975 remaining_jiffies = target_jiffies - tmp_jiffies;
2976 while (remaining_jiffies)
2977 remaining_jiffies =
2978 schedule_timeout_uninterruptible(remaining_jiffies);
dce56b3c
PZ		 2979 }
2980}
2981
1da177e4 2982#endif
Linux kernel - Deliverables
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