Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
0839ccb8 | 38 | #include <linux/io-mapping.h> |
f899fc64 | 39 | #include <linux/i2c.h> |
c167a6fc | 40 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 41 | #include <drm/intel-gtt.h> |
aaa6fd2a | 42 | #include <linux/backlight.h> |
2911a35b | 43 | #include <linux/intel-iommu.h> |
742cbee8 | 44 | #include <linux/kref.h> |
9ee32fea | 45 | #include <linux/pm_qos.h> |
585fb111 | 46 | |
1da177e4 LT |
47 | /* General customization: |
48 | */ | |
49 | ||
50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
51 | ||
52 | #define DRIVER_NAME "i915" | |
53 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 54 | #define DRIVER_DATE "20080730" |
1da177e4 | 55 | |
317c35d1 | 56 | enum pipe { |
752aa88a | 57 | INVALID_PIPE = -1, |
317c35d1 JB |
58 | PIPE_A = 0, |
59 | PIPE_B, | |
9db4a9c7 JB |
60 | PIPE_C, |
61 | I915_MAX_PIPES | |
317c35d1 | 62 | }; |
9db4a9c7 | 63 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 64 | |
a5c961d1 PZ |
65 | enum transcoder { |
66 | TRANSCODER_A = 0, | |
67 | TRANSCODER_B, | |
68 | TRANSCODER_C, | |
69 | TRANSCODER_EDP = 0xF, | |
70 | }; | |
71 | #define transcoder_name(t) ((t) + 'A') | |
72 | ||
80824003 JB |
73 | enum plane { |
74 | PLANE_A = 0, | |
75 | PLANE_B, | |
9db4a9c7 | 76 | PLANE_C, |
80824003 | 77 | }; |
9db4a9c7 | 78 | #define plane_name(p) ((p) + 'A') |
52440211 | 79 | |
06da8da2 VS |
80 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
81 | ||
2b139522 ED |
82 | enum port { |
83 | PORT_A = 0, | |
84 | PORT_B, | |
85 | PORT_C, | |
86 | PORT_D, | |
87 | PORT_E, | |
88 | I915_MAX_PORTS | |
89 | }; | |
90 | #define port_name(p) ((p) + 'A') | |
91 | ||
b97186f0 PZ |
92 | enum intel_display_power_domain { |
93 | POWER_DOMAIN_PIPE_A, | |
94 | POWER_DOMAIN_PIPE_B, | |
95 | POWER_DOMAIN_PIPE_C, | |
96 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
97 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
98 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
99 | POWER_DOMAIN_TRANSCODER_A, | |
100 | POWER_DOMAIN_TRANSCODER_B, | |
101 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 102 | POWER_DOMAIN_TRANSCODER_EDP, |
cdf8dd7f | 103 | POWER_DOMAIN_VGA, |
baa70707 | 104 | POWER_DOMAIN_INIT, |
bddc7645 ID |
105 | |
106 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
107 | }; |
108 | ||
bddc7645 ID |
109 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
110 | ||
b97186f0 PZ |
111 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
112 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
113 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
114 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
115 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
116 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 117 | |
bddc7645 ID |
118 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
119 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
120 | BIT(POWER_DOMAIN_TRANSCODER_EDP)) | |
6745a2ce PZ |
121 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
122 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
123 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
124 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
bddc7645 | 125 | |
1d843f9d EE |
126 | enum hpd_pin { |
127 | HPD_NONE = 0, | |
128 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
129 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
130 | HPD_CRT, | |
131 | HPD_SDVO_B, | |
132 | HPD_SDVO_C, | |
133 | HPD_PORT_B, | |
134 | HPD_PORT_C, | |
135 | HPD_PORT_D, | |
136 | HPD_NUM_PINS | |
137 | }; | |
138 | ||
2a2d5482 CW |
139 | #define I915_GEM_GPU_DOMAINS \ |
140 | (I915_GEM_DOMAIN_RENDER | \ | |
141 | I915_GEM_DOMAIN_SAMPLER | \ | |
142 | I915_GEM_DOMAIN_COMMAND | \ | |
143 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
144 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 145 | |
7eb552ae | 146 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
9db4a9c7 | 147 | |
6c2b7c12 DV |
148 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
149 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
150 | if ((intel_encoder)->base.crtc == (__crtc)) | |
151 | ||
e7b903d2 DV |
152 | struct drm_i915_private; |
153 | ||
46edb027 DV |
154 | enum intel_dpll_id { |
155 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
156 | /* real shared dpll ids must be >= 0 */ | |
157 | DPLL_ID_PCH_PLL_A, | |
158 | DPLL_ID_PCH_PLL_B, | |
159 | }; | |
160 | #define I915_NUM_PLLS 2 | |
161 | ||
5358901f | 162 | struct intel_dpll_hw_state { |
66e985c0 | 163 | uint32_t dpll; |
8bcc2795 | 164 | uint32_t dpll_md; |
66e985c0 DV |
165 | uint32_t fp0; |
166 | uint32_t fp1; | |
5358901f DV |
167 | }; |
168 | ||
e72f9fbf | 169 | struct intel_shared_dpll { |
ee7b9f93 JB |
170 | int refcount; /* count of number of CRTCs sharing this PLL */ |
171 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
172 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
173 | const char *name; |
174 | /* should match the index in the dev_priv->shared_dplls array */ | |
175 | enum intel_dpll_id id; | |
5358901f | 176 | struct intel_dpll_hw_state hw_state; |
15bdd4cf DV |
177 | void (*mode_set)(struct drm_i915_private *dev_priv, |
178 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
179 | void (*enable)(struct drm_i915_private *dev_priv, |
180 | struct intel_shared_dpll *pll); | |
181 | void (*disable)(struct drm_i915_private *dev_priv, | |
182 | struct intel_shared_dpll *pll); | |
5358901f DV |
183 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
184 | struct intel_shared_dpll *pll, | |
185 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 186 | }; |
ee7b9f93 | 187 | |
e69d0bc1 DV |
188 | /* Used by dp and fdi links */ |
189 | struct intel_link_m_n { | |
190 | uint32_t tu; | |
191 | uint32_t gmch_m; | |
192 | uint32_t gmch_n; | |
193 | uint32_t link_m; | |
194 | uint32_t link_n; | |
195 | }; | |
196 | ||
197 | void intel_link_compute_m_n(int bpp, int nlanes, | |
198 | int pixel_clock, int link_clock, | |
199 | struct intel_link_m_n *m_n); | |
200 | ||
6441ab5f PZ |
201 | struct intel_ddi_plls { |
202 | int spll_refcount; | |
203 | int wrpll1_refcount; | |
204 | int wrpll2_refcount; | |
205 | }; | |
206 | ||
1da177e4 LT |
207 | /* Interface history: |
208 | * | |
209 | * 1.1: Original. | |
0d6aa60b DA |
210 | * 1.2: Add Power Management |
211 | * 1.3: Add vblank support | |
de227f5f | 212 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 213 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
214 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
215 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
216 | */ |
217 | #define DRIVER_MAJOR 1 | |
2228ed67 | 218 | #define DRIVER_MINOR 6 |
1da177e4 LT |
219 | #define DRIVER_PATCHLEVEL 0 |
220 | ||
23bc5982 | 221 | #define WATCH_LISTS 0 |
42d6ab48 | 222 | #define WATCH_GTT 0 |
673a394b | 223 | |
71acb5eb DA |
224 | #define I915_GEM_PHYS_CURSOR_0 1 |
225 | #define I915_GEM_PHYS_CURSOR_1 2 | |
226 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
227 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
228 | ||
229 | struct drm_i915_gem_phys_object { | |
230 | int id; | |
231 | struct page **page_list; | |
232 | drm_dma_handle_t *handle; | |
05394f39 | 233 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
234 | }; |
235 | ||
0a3e67a4 JB |
236 | struct opregion_header; |
237 | struct opregion_acpi; | |
238 | struct opregion_swsci; | |
239 | struct opregion_asle; | |
240 | ||
8ee1c3db | 241 | struct intel_opregion { |
5bc4418b BW |
242 | struct opregion_header __iomem *header; |
243 | struct opregion_acpi __iomem *acpi; | |
244 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
245 | u32 swsci_gbda_sub_functions; |
246 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
247 | struct opregion_asle __iomem *asle; |
248 | void __iomem *vbt; | |
01fe9dbd | 249 | u32 __iomem *lid_state; |
91a60f20 | 250 | struct work_struct asle_work; |
8ee1c3db | 251 | }; |
44834a67 | 252 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 253 | |
6ef3d427 CW |
254 | struct intel_overlay; |
255 | struct intel_overlay_error_state; | |
256 | ||
7c1c2871 DA |
257 | struct drm_i915_master_private { |
258 | drm_local_map_t *sarea; | |
259 | struct _drm_i915_sarea *sarea_priv; | |
260 | }; | |
de151cf6 | 261 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
262 | #define I915_MAX_NUM_FENCES 32 |
263 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
264 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
265 | |
266 | struct drm_i915_fence_reg { | |
007cc8ac | 267 | struct list_head lru_list; |
caea7476 | 268 | struct drm_i915_gem_object *obj; |
1690e1eb | 269 | int pin_count; |
de151cf6 | 270 | }; |
7c1c2871 | 271 | |
9b9d172d | 272 | struct sdvo_device_mapping { |
e957d772 | 273 | u8 initialized; |
9b9d172d | 274 | u8 dvo_port; |
275 | u8 slave_addr; | |
276 | u8 dvo_wiring; | |
e957d772 | 277 | u8 i2c_pin; |
b1083333 | 278 | u8 ddc_pin; |
9b9d172d | 279 | }; |
280 | ||
c4a1d9e4 CW |
281 | struct intel_display_error_state; |
282 | ||
63eeaf38 | 283 | struct drm_i915_error_state { |
742cbee8 | 284 | struct kref ref; |
63eeaf38 JB |
285 | u32 eir; |
286 | u32 pgtbl_er; | |
be998e2e | 287 | u32 ier; |
b9a3906b | 288 | u32 ccid; |
0f3b6849 CW |
289 | u32 derrmr; |
290 | u32 forcewake; | |
9574b3fe | 291 | bool waiting[I915_NUM_RINGS]; |
9db4a9c7 | 292 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
293 | u32 tail[I915_NUM_RINGS]; |
294 | u32 head[I915_NUM_RINGS]; | |
0f3b6849 | 295 | u32 ctl[I915_NUM_RINGS]; |
d27b1e0e DV |
296 | u32 ipeir[I915_NUM_RINGS]; |
297 | u32 ipehr[I915_NUM_RINGS]; | |
298 | u32 instdone[I915_NUM_RINGS]; | |
299 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 | 300 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
df2b23d9 | 301 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
12f55818 | 302 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
7e3b8737 DV |
303 | /* our own tracking of ring head and tail */ |
304 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
305 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 306 | u32 error; /* gen6+ */ |
71e172e8 | 307 | u32 err_int; /* gen7 */ |
94e39e28 | 308 | u32 bbstate[I915_NUM_RINGS]; |
c1cd90ed DV |
309 | u32 instpm[I915_NUM_RINGS]; |
310 | u32 instps[I915_NUM_RINGS]; | |
050ee91f | 311 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
d27b1e0e | 312 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 313 | u64 bbaddr; |
33f3f518 DV |
314 | u32 fault_reg[I915_NUM_RINGS]; |
315 | u32 done_reg; | |
c1cd90ed | 316 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 317 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 318 | struct timeval time; |
52d39a21 CW |
319 | struct drm_i915_error_ring { |
320 | struct drm_i915_error_object { | |
321 | int page_count; | |
322 | u32 gtt_offset; | |
323 | u32 *pages[0]; | |
8c123e54 | 324 | } *ringbuffer, *batchbuffer, *ctx; |
52d39a21 CW |
325 | struct drm_i915_error_request { |
326 | long jiffies; | |
327 | u32 seqno; | |
ee4f42b1 | 328 | u32 tail; |
52d39a21 CW |
329 | } *requests; |
330 | int num_requests; | |
331 | } ring[I915_NUM_RINGS]; | |
9df30794 | 332 | struct drm_i915_error_buffer { |
a779e5ab | 333 | u32 size; |
9df30794 | 334 | u32 name; |
0201f1ec | 335 | u32 rseqno, wseqno; |
9df30794 CW |
336 | u32 gtt_offset; |
337 | u32 read_domains; | |
338 | u32 write_domain; | |
4b9de737 | 339 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
340 | s32 pinned:2; |
341 | u32 tiling:2; | |
342 | u32 dirty:1; | |
343 | u32 purgeable:1; | |
5d1333fc | 344 | s32 ring:4; |
f56383cb | 345 | u32 cache_level:3; |
95f5301d BW |
346 | } **active_bo, **pinned_bo; |
347 | u32 *active_bo_count, *pinned_bo_count; | |
6ef3d427 | 348 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 349 | struct intel_display_error_state *display; |
da661464 MK |
350 | int hangcheck_score[I915_NUM_RINGS]; |
351 | enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS]; | |
63eeaf38 JB |
352 | }; |
353 | ||
b8cecdf5 | 354 | struct intel_crtc_config; |
0e8ffe1b | 355 | struct intel_crtc; |
ee9300bb DV |
356 | struct intel_limit; |
357 | struct dpll; | |
b8cecdf5 | 358 | |
e70236a8 | 359 | struct drm_i915_display_funcs { |
ee5382ae | 360 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
361 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
362 | void (*disable_fbc)(struct drm_device *dev); | |
363 | int (*get_display_clock_speed)(struct drm_device *dev); | |
364 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
365 | /** |
366 | * find_dpll() - Find the best values for the PLL | |
367 | * @limit: limits for the PLL | |
368 | * @crtc: current CRTC | |
369 | * @target: target frequency in kHz | |
370 | * @refclk: reference clock frequency in kHz | |
371 | * @match_clock: if provided, @best_clock P divider must | |
372 | * match the P divider from @match_clock | |
373 | * used for LVDS downclocking | |
374 | * @best_clock: best PLL values found | |
375 | * | |
376 | * Returns true on success, false on failure. | |
377 | */ | |
378 | bool (*find_dpll)(const struct intel_limit *limit, | |
379 | struct drm_crtc *crtc, | |
380 | int target, int refclk, | |
381 | struct dpll *match_clock, | |
382 | struct dpll *best_clock); | |
46ba614c | 383 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
384 | void (*update_sprite_wm)(struct drm_plane *plane, |
385 | struct drm_crtc *crtc, | |
4c4ff43a | 386 | uint32_t sprite_width, int pixel_size, |
bdd57d03 | 387 | bool enable, bool scaled); |
47fab737 | 388 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
389 | /* Returns the active state of the crtc, and if the crtc is active, |
390 | * fills out the pipe-config with the hw state. */ | |
391 | bool (*get_pipe_config)(struct intel_crtc *, | |
392 | struct intel_crtc_config *); | |
f564048e | 393 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
f564048e EA |
394 | int x, int y, |
395 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
396 | void (*crtc_enable)(struct drm_crtc *crtc); |
397 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 398 | void (*off)(struct drm_crtc *crtc); |
e0dac65e | 399 | void (*write_eld)(struct drm_connector *connector, |
34427052 JN |
400 | struct drm_crtc *crtc, |
401 | struct drm_display_mode *mode); | |
674cf967 | 402 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 403 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
404 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
405 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
406 | struct drm_i915_gem_object *obj, |
407 | uint32_t flags); | |
17638cd6 JB |
408 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
409 | int x, int y); | |
20afbda2 | 410 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
411 | /* clock updates for mode set */ |
412 | /* cursor updates */ | |
413 | /* render clock increase/decrease */ | |
414 | /* display clock increase/decrease */ | |
415 | /* pll clock increase/decrease */ | |
e70236a8 JB |
416 | }; |
417 | ||
907b28c5 | 418 | struct intel_uncore_funcs { |
990bbdad CW |
419 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
420 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
0b274481 BW |
421 | |
422 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
423 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
424 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
425 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
426 | ||
427 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
428 | uint8_t val, bool trace); | |
429 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
430 | uint16_t val, bool trace); | |
431 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
432 | uint32_t val, bool trace); | |
433 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
434 | uint64_t val, bool trace); | |
990bbdad CW |
435 | }; |
436 | ||
907b28c5 CW |
437 | struct intel_uncore { |
438 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
439 | ||
440 | struct intel_uncore_funcs funcs; | |
441 | ||
442 | unsigned fifo_count; | |
443 | unsigned forcewake_count; | |
aec347ab CW |
444 | |
445 | struct delayed_work force_wake_work; | |
907b28c5 CW |
446 | }; |
447 | ||
79fc46df DL |
448 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
449 | func(is_mobile) sep \ | |
450 | func(is_i85x) sep \ | |
451 | func(is_i915g) sep \ | |
452 | func(is_i945gm) sep \ | |
453 | func(is_g33) sep \ | |
454 | func(need_gfx_hws) sep \ | |
455 | func(is_g4x) sep \ | |
456 | func(is_pineview) sep \ | |
457 | func(is_broadwater) sep \ | |
458 | func(is_crestline) sep \ | |
459 | func(is_ivybridge) sep \ | |
460 | func(is_valleyview) sep \ | |
461 | func(is_haswell) sep \ | |
b833d685 | 462 | func(is_preliminary) sep \ |
79fc46df DL |
463 | func(has_fbc) sep \ |
464 | func(has_pipe_cxsr) sep \ | |
465 | func(has_hotplug) sep \ | |
466 | func(cursor_needs_physical) sep \ | |
467 | func(has_overlay) sep \ | |
468 | func(overlay_needs_physical) sep \ | |
469 | func(supports_tv) sep \ | |
dd93be58 | 470 | func(has_llc) sep \ |
30568c45 DL |
471 | func(has_ddi) sep \ |
472 | func(has_fpga_dbg) | |
c96ea64e | 473 | |
a587f779 DL |
474 | #define DEFINE_FLAG(name) u8 name:1 |
475 | #define SEP_SEMICOLON ; | |
c96ea64e | 476 | |
cfdf1fa2 | 477 | struct intel_device_info { |
10fce67a | 478 | u32 display_mmio_offset; |
7eb552ae | 479 | u8 num_pipes:3; |
c96c3a8c | 480 | u8 gen; |
73ae478c | 481 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 482 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
cfdf1fa2 KH |
483 | }; |
484 | ||
a587f779 DL |
485 | #undef DEFINE_FLAG |
486 | #undef SEP_SEMICOLON | |
487 | ||
7faf1ab2 DV |
488 | enum i915_cache_level { |
489 | I915_CACHE_NONE = 0, | |
350ec881 CW |
490 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
491 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
492 | caches, eg sampler/render caches, and the | |
493 | large Last-Level-Cache. LLC is coherent with | |
494 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 495 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
496 | }; |
497 | ||
2d04befb KG |
498 | typedef uint32_t gen6_gtt_pte_t; |
499 | ||
853ba5d2 | 500 | struct i915_address_space { |
93bd8649 | 501 | struct drm_mm mm; |
853ba5d2 | 502 | struct drm_device *dev; |
a7bbbd63 | 503 | struct list_head global_link; |
853ba5d2 BW |
504 | unsigned long start; /* Start offset always 0 for dri2 */ |
505 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ | |
506 | ||
507 | struct { | |
508 | dma_addr_t addr; | |
509 | struct page *page; | |
510 | } scratch; | |
511 | ||
5cef07e1 BW |
512 | /** |
513 | * List of objects currently involved in rendering. | |
514 | * | |
515 | * Includes buffers having the contents of their GPU caches | |
516 | * flushed, not necessarily primitives. last_rendering_seqno | |
517 | * represents when the rendering involved will be completed. | |
518 | * | |
519 | * A reference is held on the buffer while on this list. | |
520 | */ | |
521 | struct list_head active_list; | |
522 | ||
523 | /** | |
524 | * LRU list of objects which are not in the ringbuffer and | |
525 | * are ready to unbind, but are still in the GTT. | |
526 | * | |
527 | * last_rendering_seqno is 0 while an object is in this list. | |
528 | * | |
529 | * A reference is not held on the buffer while on this list, | |
530 | * as merely being GTT-bound shouldn't prevent its being | |
531 | * freed, and we'll pull it off the list in the free path. | |
532 | */ | |
533 | struct list_head inactive_list; | |
534 | ||
853ba5d2 BW |
535 | /* FIXME: Need a more generic return type */ |
536 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, | |
b35b380e BW |
537 | enum i915_cache_level level, |
538 | bool valid); /* Create a valid PTE */ | |
853ba5d2 BW |
539 | void (*clear_range)(struct i915_address_space *vm, |
540 | unsigned int first_entry, | |
828c7908 BW |
541 | unsigned int num_entries, |
542 | bool use_scratch); | |
853ba5d2 BW |
543 | void (*insert_entries)(struct i915_address_space *vm, |
544 | struct sg_table *st, | |
545 | unsigned int first_entry, | |
546 | enum i915_cache_level cache_level); | |
547 | void (*cleanup)(struct i915_address_space *vm); | |
548 | }; | |
549 | ||
5d4545ae BW |
550 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
551 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
552 | * collateral associated with any va->pa translations GEN hardware also has a | |
553 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
554 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
555 | * the spec. | |
556 | */ | |
557 | struct i915_gtt { | |
853ba5d2 | 558 | struct i915_address_space base; |
baa09f5f | 559 | size_t stolen_size; /* Total size of stolen memory */ |
5d4545ae BW |
560 | |
561 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
562 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
563 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
564 | ||
565 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
566 | void __iomem *gsm; | |
a81cc00c BW |
567 | |
568 | bool do_idle_maps; | |
7faf1ab2 | 569 | |
911bdf0a | 570 | int mtrr; |
7faf1ab2 DV |
571 | |
572 | /* global gtt ops */ | |
baa09f5f | 573 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
41907ddc BW |
574 | size_t *stolen, phys_addr_t *mappable_base, |
575 | unsigned long *mappable_end); | |
5d4545ae | 576 | }; |
853ba5d2 | 577 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
5d4545ae | 578 | |
1d2a314c | 579 | struct i915_hw_ppgtt { |
853ba5d2 | 580 | struct i915_address_space base; |
1d2a314c | 581 | unsigned num_pd_entries; |
37aca44a BW |
582 | union { |
583 | struct page **pt_pages; | |
584 | struct page *gen8_pt_pages; | |
585 | }; | |
586 | struct page *pd_pages; | |
587 | int num_pd_pages; | |
588 | int num_pt_pages; | |
589 | union { | |
590 | uint32_t pd_offset; | |
591 | dma_addr_t pd_dma_addr[4]; | |
592 | }; | |
593 | union { | |
594 | dma_addr_t *pt_dma_addr; | |
595 | dma_addr_t *gen8_pt_dma_addr[4]; | |
596 | }; | |
b7c36d25 | 597 | int (*enable)(struct drm_device *dev); |
1d2a314c DV |
598 | }; |
599 | ||
0b02e798 BW |
600 | /** |
601 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a | |
602 | * VMA's presence cannot be guaranteed before binding, or after unbinding the | |
603 | * object into/from the address space. | |
604 | * | |
605 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime | |
2f633156 BW |
606 | * will always be <= an objects lifetime. So object refcounting should cover us. |
607 | */ | |
608 | struct i915_vma { | |
609 | struct drm_mm_node node; | |
610 | struct drm_i915_gem_object *obj; | |
611 | struct i915_address_space *vm; | |
612 | ||
ca191b13 BW |
613 | /** This object's place on the active/inactive lists */ |
614 | struct list_head mm_list; | |
615 | ||
2f633156 | 616 | struct list_head vma_link; /* Link in the object's VMA list */ |
82a55ad1 BW |
617 | |
618 | /** This vma's place in the batchbuffer or on the eviction list */ | |
619 | struct list_head exec_list; | |
620 | ||
27173f1f BW |
621 | /** |
622 | * Used for performing relocations during execbuffer insertion. | |
623 | */ | |
624 | struct hlist_node exec_node; | |
625 | unsigned long exec_handle; | |
626 | struct drm_i915_gem_exec_object2 *exec_entry; | |
627 | ||
1d2a314c DV |
628 | }; |
629 | ||
e59ec13d MK |
630 | struct i915_ctx_hang_stats { |
631 | /* This context had batch pending when hang was declared */ | |
632 | unsigned batch_pending; | |
633 | ||
634 | /* This context had batch active when hang was declared */ | |
635 | unsigned batch_active; | |
be62acb4 MK |
636 | |
637 | /* Time when this context was last blamed for a GPU reset */ | |
638 | unsigned long guilty_ts; | |
639 | ||
640 | /* This context is banned to submit more work */ | |
641 | bool banned; | |
e59ec13d | 642 | }; |
40521054 BW |
643 | |
644 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
645 | #define DEFAULT_CONTEXT_ID 0 | |
646 | struct i915_hw_context { | |
dce3271b | 647 | struct kref ref; |
40521054 | 648 | int id; |
e0556841 | 649 | bool is_initialized; |
3ccfd19d | 650 | uint8_t remap_slice; |
40521054 BW |
651 | struct drm_i915_file_private *file_priv; |
652 | struct intel_ring_buffer *ring; | |
653 | struct drm_i915_gem_object *obj; | |
e59ec13d | 654 | struct i915_ctx_hang_stats hang_stats; |
a33afea5 BW |
655 | |
656 | struct list_head link; | |
40521054 BW |
657 | }; |
658 | ||
5c3fe8b0 BW |
659 | struct i915_fbc { |
660 | unsigned long size; | |
661 | unsigned int fb_id; | |
662 | enum plane plane; | |
663 | int y; | |
664 | ||
665 | struct drm_mm_node *compressed_fb; | |
666 | struct drm_mm_node *compressed_llb; | |
667 | ||
668 | struct intel_fbc_work { | |
669 | struct delayed_work work; | |
670 | struct drm_crtc *crtc; | |
671 | struct drm_framebuffer *fb; | |
672 | int interval; | |
673 | } *fbc_work; | |
674 | ||
29ebf90f CW |
675 | enum no_fbc_reason { |
676 | FBC_OK, /* FBC is enabled */ | |
677 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
678 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
679 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
680 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
681 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
682 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
683 | FBC_NOT_TILED, /* buffer not tiled */ | |
684 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
685 | FBC_MODULE_PARAM, | |
686 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
687 | } no_fbc_reason; | |
b5e50c3f JB |
688 | }; |
689 | ||
a031d709 RV |
690 | struct i915_psr { |
691 | bool sink_support; | |
692 | bool source_ok; | |
3f51e471 | 693 | }; |
5c3fe8b0 | 694 | |
3bad0781 | 695 | enum intel_pch { |
f0350830 | 696 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
697 | PCH_IBX, /* Ibexpeak PCH */ |
698 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 699 | PCH_LPT, /* Lynxpoint PCH */ |
40c7ead9 | 700 | PCH_NOP, |
3bad0781 ZW |
701 | }; |
702 | ||
988d6ee8 PZ |
703 | enum intel_sbi_destination { |
704 | SBI_ICLK, | |
705 | SBI_MPHY, | |
706 | }; | |
707 | ||
b690e96c | 708 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 709 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 710 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
e85843be | 711 | #define QUIRK_NO_PCH_PWM_ENABLE (1<<3) |
b690e96c | 712 | |
8be48d92 | 713 | struct intel_fbdev; |
1630fe75 | 714 | struct intel_fbc_work; |
38651674 | 715 | |
c2b9152f DV |
716 | struct intel_gmbus { |
717 | struct i2c_adapter adapter; | |
f2ce9faf | 718 | u32 force_bit; |
c2b9152f | 719 | u32 reg0; |
36c785f0 | 720 | u32 gpio_reg; |
c167a6fc | 721 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
722 | struct drm_i915_private *dev_priv; |
723 | }; | |
724 | ||
f4c956ad | 725 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
726 | u8 saveLBB; |
727 | u32 saveDSPACNTR; | |
728 | u32 saveDSPBCNTR; | |
e948e994 | 729 | u32 saveDSPARB; |
ba8bbcf6 JB |
730 | u32 savePIPEACONF; |
731 | u32 savePIPEBCONF; | |
732 | u32 savePIPEASRC; | |
733 | u32 savePIPEBSRC; | |
734 | u32 saveFPA0; | |
735 | u32 saveFPA1; | |
736 | u32 saveDPLL_A; | |
737 | u32 saveDPLL_A_MD; | |
738 | u32 saveHTOTAL_A; | |
739 | u32 saveHBLANK_A; | |
740 | u32 saveHSYNC_A; | |
741 | u32 saveVTOTAL_A; | |
742 | u32 saveVBLANK_A; | |
743 | u32 saveVSYNC_A; | |
744 | u32 saveBCLRPAT_A; | |
5586c8bc | 745 | u32 saveTRANSACONF; |
42048781 ZW |
746 | u32 saveTRANS_HTOTAL_A; |
747 | u32 saveTRANS_HBLANK_A; | |
748 | u32 saveTRANS_HSYNC_A; | |
749 | u32 saveTRANS_VTOTAL_A; | |
750 | u32 saveTRANS_VBLANK_A; | |
751 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 752 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
753 | u32 saveDSPASTRIDE; |
754 | u32 saveDSPASIZE; | |
755 | u32 saveDSPAPOS; | |
585fb111 | 756 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
757 | u32 saveDSPASURF; |
758 | u32 saveDSPATILEOFF; | |
759 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 760 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
761 | u32 saveBLC_PWM_CTL; |
762 | u32 saveBLC_PWM_CTL2; | |
07bf139b JB |
763 | u32 saveBLC_HIST_CTL_B; |
764 | u32 saveBLC_PWM_CTL_B; | |
765 | u32 saveBLC_PWM_CTL2_B; | |
42048781 ZW |
766 | u32 saveBLC_CPU_PWM_CTL; |
767 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
768 | u32 saveFPB0; |
769 | u32 saveFPB1; | |
770 | u32 saveDPLL_B; | |
771 | u32 saveDPLL_B_MD; | |
772 | u32 saveHTOTAL_B; | |
773 | u32 saveHBLANK_B; | |
774 | u32 saveHSYNC_B; | |
775 | u32 saveVTOTAL_B; | |
776 | u32 saveVBLANK_B; | |
777 | u32 saveVSYNC_B; | |
778 | u32 saveBCLRPAT_B; | |
5586c8bc | 779 | u32 saveTRANSBCONF; |
42048781 ZW |
780 | u32 saveTRANS_HTOTAL_B; |
781 | u32 saveTRANS_HBLANK_B; | |
782 | u32 saveTRANS_HSYNC_B; | |
783 | u32 saveTRANS_VTOTAL_B; | |
784 | u32 saveTRANS_VBLANK_B; | |
785 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 786 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
787 | u32 saveDSPBSTRIDE; |
788 | u32 saveDSPBSIZE; | |
789 | u32 saveDSPBPOS; | |
585fb111 | 790 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
791 | u32 saveDSPBSURF; |
792 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
793 | u32 saveVGA0; |
794 | u32 saveVGA1; | |
795 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
796 | u32 saveVGACNTRL; |
797 | u32 saveADPA; | |
798 | u32 saveLVDS; | |
585fb111 JB |
799 | u32 savePP_ON_DELAYS; |
800 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
801 | u32 saveDVOA; |
802 | u32 saveDVOB; | |
803 | u32 saveDVOC; | |
804 | u32 savePP_ON; | |
805 | u32 savePP_OFF; | |
806 | u32 savePP_CONTROL; | |
585fb111 | 807 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
808 | u32 savePFIT_CONTROL; |
809 | u32 save_palette_a[256]; | |
810 | u32 save_palette_b[256]; | |
06027f91 | 811 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
812 | u32 saveFBC_CFB_BASE; |
813 | u32 saveFBC_LL_BASE; | |
814 | u32 saveFBC_CONTROL; | |
815 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
816 | u32 saveIER; |
817 | u32 saveIIR; | |
818 | u32 saveIMR; | |
42048781 ZW |
819 | u32 saveDEIER; |
820 | u32 saveDEIMR; | |
821 | u32 saveGTIER; | |
822 | u32 saveGTIMR; | |
823 | u32 saveFDI_RXA_IMR; | |
824 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 825 | u32 saveCACHE_MODE_0; |
1f84e550 | 826 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
827 | u32 saveSWF0[16]; |
828 | u32 saveSWF1[16]; | |
829 | u32 saveSWF2[3]; | |
830 | u8 saveMSR; | |
831 | u8 saveSR[8]; | |
123f794f | 832 | u8 saveGR[25]; |
ba8bbcf6 | 833 | u8 saveAR_INDEX; |
a59e122a | 834 | u8 saveAR[21]; |
ba8bbcf6 | 835 | u8 saveDACMASK; |
a59e122a | 836 | u8 saveCR[37]; |
4b9de737 | 837 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
838 | u32 saveCURACNTR; |
839 | u32 saveCURAPOS; | |
840 | u32 saveCURABASE; | |
841 | u32 saveCURBCNTR; | |
842 | u32 saveCURBPOS; | |
843 | u32 saveCURBBASE; | |
844 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
845 | u32 saveDP_B; |
846 | u32 saveDP_C; | |
847 | u32 saveDP_D; | |
848 | u32 savePIPEA_GMCH_DATA_M; | |
849 | u32 savePIPEB_GMCH_DATA_M; | |
850 | u32 savePIPEA_GMCH_DATA_N; | |
851 | u32 savePIPEB_GMCH_DATA_N; | |
852 | u32 savePIPEA_DP_LINK_M; | |
853 | u32 savePIPEB_DP_LINK_M; | |
854 | u32 savePIPEA_DP_LINK_N; | |
855 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
856 | u32 saveFDI_RXA_CTL; |
857 | u32 saveFDI_TXA_CTL; | |
858 | u32 saveFDI_RXB_CTL; | |
859 | u32 saveFDI_TXB_CTL; | |
860 | u32 savePFA_CTL_1; | |
861 | u32 savePFB_CTL_1; | |
862 | u32 savePFA_WIN_SZ; | |
863 | u32 savePFB_WIN_SZ; | |
864 | u32 savePFA_WIN_POS; | |
865 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
866 | u32 savePCH_DREF_CONTROL; |
867 | u32 saveDISP_ARB_CTL; | |
868 | u32 savePIPEA_DATA_M1; | |
869 | u32 savePIPEA_DATA_N1; | |
870 | u32 savePIPEA_LINK_M1; | |
871 | u32 savePIPEA_LINK_N1; | |
872 | u32 savePIPEB_DATA_M1; | |
873 | u32 savePIPEB_DATA_N1; | |
874 | u32 savePIPEB_LINK_M1; | |
875 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 876 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 877 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 878 | }; |
c85aa885 DV |
879 | |
880 | struct intel_gen6_power_mgmt { | |
59cdb63d | 881 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
c85aa885 DV |
882 | struct work_struct work; |
883 | u32 pm_iir; | |
59cdb63d | 884 | |
c85aa885 DV |
885 | /* The below variables an all the rps hw state are protected by |
886 | * dev->struct mutext. */ | |
887 | u8 cur_delay; | |
888 | u8 min_delay; | |
889 | u8 max_delay; | |
52ceb908 | 890 | u8 rpe_delay; |
dd75fdc8 CW |
891 | u8 rp1_delay; |
892 | u8 rp0_delay; | |
31c77388 | 893 | u8 hw_max; |
1a01ab3b | 894 | |
dd75fdc8 CW |
895 | int last_adj; |
896 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
897 | ||
c0951f0c | 898 | bool enabled; |
1a01ab3b | 899 | struct delayed_work delayed_resume_work; |
4fc688ce JB |
900 | |
901 | /* | |
902 | * Protects RPS/RC6 register access and PCU communication. | |
903 | * Must be taken after struct_mutex if nested. | |
904 | */ | |
905 | struct mutex hw_lock; | |
c85aa885 DV |
906 | }; |
907 | ||
1a240d4d DV |
908 | /* defined intel_pm.c */ |
909 | extern spinlock_t mchdev_lock; | |
910 | ||
c85aa885 DV |
911 | struct intel_ilk_power_mgmt { |
912 | u8 cur_delay; | |
913 | u8 min_delay; | |
914 | u8 max_delay; | |
915 | u8 fmax; | |
916 | u8 fstart; | |
917 | ||
918 | u64 last_count1; | |
919 | unsigned long last_time1; | |
920 | unsigned long chipset_power; | |
921 | u64 last_count2; | |
922 | struct timespec last_time2; | |
923 | unsigned long gfx_power; | |
924 | u8 corr; | |
925 | ||
926 | int c_m; | |
927 | int r_t; | |
3e373948 DV |
928 | |
929 | struct drm_i915_gem_object *pwrctx; | |
930 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
931 | }; |
932 | ||
a38911a3 WX |
933 | /* Power well structure for haswell */ |
934 | struct i915_power_well { | |
a38911a3 WX |
935 | /* power well enable/disable usage count */ |
936 | int count; | |
a38911a3 WX |
937 | }; |
938 | ||
83c00f55 ID |
939 | #define I915_MAX_POWER_WELLS 1 |
940 | ||
941 | struct i915_power_domains { | |
baa70707 ID |
942 | /* |
943 | * Power wells needed for initialization at driver init and suspend | |
944 | * time are on. They are kept on until after the first modeset. | |
945 | */ | |
946 | bool init_power_on; | |
947 | ||
83c00f55 ID |
948 | struct mutex lock; |
949 | struct i915_power_well power_wells[I915_MAX_POWER_WELLS]; | |
950 | }; | |
951 | ||
231f42a4 DV |
952 | struct i915_dri1_state { |
953 | unsigned allow_batchbuffer : 1; | |
954 | u32 __iomem *gfx_hws_cpu_addr; | |
955 | ||
956 | unsigned int cpp; | |
957 | int back_offset; | |
958 | int front_offset; | |
959 | int current_page; | |
960 | int page_flipping; | |
961 | ||
962 | uint32_t counter; | |
963 | }; | |
964 | ||
db1b76ca DV |
965 | struct i915_ums_state { |
966 | /** | |
967 | * Flag if the X Server, and thus DRM, is not currently in | |
968 | * control of the device. | |
969 | * | |
970 | * This is set between LeaveVT and EnterVT. It needs to be | |
971 | * replaced with a semaphore. It also needs to be | |
972 | * transitioned away from for kernel modesetting. | |
973 | */ | |
974 | int mm_suspended; | |
975 | }; | |
976 | ||
35a85ac6 | 977 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 978 | struct intel_l3_parity { |
35a85ac6 | 979 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 980 | struct work_struct error_work; |
35a85ac6 | 981 | int which_slice; |
a4da4fa4 DV |
982 | }; |
983 | ||
4b5aed62 | 984 | struct i915_gem_mm { |
4b5aed62 DV |
985 | /** Memory allocator for GTT stolen memory */ |
986 | struct drm_mm stolen; | |
4b5aed62 DV |
987 | /** List of all objects in gtt_space. Used to restore gtt |
988 | * mappings on resume */ | |
989 | struct list_head bound_list; | |
990 | /** | |
991 | * List of objects which are not bound to the GTT (thus | |
992 | * are idle and not used by the GPU) but still have | |
993 | * (presumably uncached) pages still attached. | |
994 | */ | |
995 | struct list_head unbound_list; | |
996 | ||
997 | /** Usable portion of the GTT for GEM */ | |
998 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
999 | ||
4b5aed62 DV |
1000 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1001 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1002 | ||
1003 | struct shrinker inactive_shrinker; | |
1004 | bool shrinker_no_lock_stealing; | |
1005 | ||
4b5aed62 DV |
1006 | /** LRU list of objects with fence regs on them. */ |
1007 | struct list_head fence_list; | |
1008 | ||
1009 | /** | |
1010 | * We leave the user IRQ off as much as possible, | |
1011 | * but this means that requests will finish and never | |
1012 | * be retired once the system goes idle. Set a timer to | |
1013 | * fire periodically while the ring is running. When it | |
1014 | * fires, go retire requests. | |
1015 | */ | |
1016 | struct delayed_work retire_work; | |
1017 | ||
b29c19b6 CW |
1018 | /** |
1019 | * When we detect an idle GPU, we want to turn on | |
1020 | * powersaving features. So once we see that there | |
1021 | * are no more requests outstanding and no more | |
1022 | * arrive within a small period of time, we fire | |
1023 | * off the idle_work. | |
1024 | */ | |
1025 | struct delayed_work idle_work; | |
1026 | ||
4b5aed62 DV |
1027 | /** |
1028 | * Are we in a non-interruptible section of code like | |
1029 | * modesetting? | |
1030 | */ | |
1031 | bool interruptible; | |
1032 | ||
4b5aed62 DV |
1033 | /** Bit 6 swizzling required for X tiling */ |
1034 | uint32_t bit_6_swizzle_x; | |
1035 | /** Bit 6 swizzling required for Y tiling */ | |
1036 | uint32_t bit_6_swizzle_y; | |
1037 | ||
1038 | /* storage for physical objects */ | |
1039 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
1040 | ||
1041 | /* accounting, useful for userland debugging */ | |
c20e8355 | 1042 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1043 | size_t object_memory; |
1044 | u32 object_count; | |
1045 | }; | |
1046 | ||
edc3d884 MK |
1047 | struct drm_i915_error_state_buf { |
1048 | unsigned bytes; | |
1049 | unsigned size; | |
1050 | int err; | |
1051 | u8 *buf; | |
1052 | loff_t start; | |
1053 | loff_t pos; | |
1054 | }; | |
1055 | ||
fc16b48b MK |
1056 | struct i915_error_state_file_priv { |
1057 | struct drm_device *dev; | |
1058 | struct drm_i915_error_state *error; | |
1059 | }; | |
1060 | ||
99584db3 DV |
1061 | struct i915_gpu_error { |
1062 | /* For hangcheck timer */ | |
1063 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1064 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1065 | /* Hang gpu twice in this window and your context gets banned */ |
1066 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1067 | ||
99584db3 | 1068 | struct timer_list hangcheck_timer; |
99584db3 DV |
1069 | |
1070 | /* For reset and error_state handling. */ | |
1071 | spinlock_t lock; | |
1072 | /* Protected by the above dev->gpu_error.lock. */ | |
1073 | struct drm_i915_error_state *first_error; | |
1074 | struct work_struct work; | |
99584db3 | 1075 | |
094f9a54 CW |
1076 | |
1077 | unsigned long missed_irq_rings; | |
1078 | ||
1f83fee0 | 1079 | /** |
f69061be | 1080 | * State variable and reset counter controlling the reset flow |
1f83fee0 | 1081 | * |
f69061be DV |
1082 | * Upper bits are for the reset counter. This counter is used by the |
1083 | * wait_seqno code to race-free noticed that a reset event happened and | |
1084 | * that it needs to restart the entire ioctl (since most likely the | |
1085 | * seqno it waited for won't ever signal anytime soon). | |
1086 | * | |
1087 | * This is important for lock-free wait paths, where no contended lock | |
1088 | * naturally enforces the correct ordering between the bail-out of the | |
1089 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1090 | * |
1091 | * Lowest bit controls the reset state machine: Set means a reset is in | |
1092 | * progress. This state will (presuming we don't have any bugs) decay | |
1093 | * into either unset (successful reset) or the special WEDGED value (hw | |
1094 | * terminally sour). All waiters on the reset_queue will be woken when | |
1095 | * that happens. | |
1096 | */ | |
1097 | atomic_t reset_counter; | |
1098 | ||
1099 | /** | |
1100 | * Special values/flags for reset_counter | |
1101 | * | |
1102 | * Note that the code relies on | |
1103 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG | |
1104 | * being true. | |
1105 | */ | |
1106 | #define I915_RESET_IN_PROGRESS_FLAG 1 | |
1107 | #define I915_WEDGED 0xffffffff | |
1108 | ||
1109 | /** | |
1110 | * Waitqueue to signal when the reset has completed. Used by clients | |
1111 | * that wait for dev_priv->mm.wedged to settle. | |
1112 | */ | |
1113 | wait_queue_head_t reset_queue; | |
33196ded | 1114 | |
99584db3 DV |
1115 | /* For gpu hang simulation. */ |
1116 | unsigned int stop_rings; | |
094f9a54 CW |
1117 | |
1118 | /* For missed irq/seqno simulation. */ | |
1119 | unsigned int test_irq_rings; | |
99584db3 DV |
1120 | }; |
1121 | ||
b8efb17b ZR |
1122 | enum modeset_restore { |
1123 | MODESET_ON_LID_OPEN, | |
1124 | MODESET_DONE, | |
1125 | MODESET_SUSPENDED, | |
1126 | }; | |
1127 | ||
6acab15a PZ |
1128 | struct ddi_vbt_port_info { |
1129 | uint8_t hdmi_level_shift; | |
311a2094 PZ |
1130 | |
1131 | uint8_t supports_dvi:1; | |
1132 | uint8_t supports_hdmi:1; | |
1133 | uint8_t supports_dp:1; | |
6acab15a PZ |
1134 | }; |
1135 | ||
41aa3448 RV |
1136 | struct intel_vbt_data { |
1137 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1138 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1139 | ||
1140 | /* Feature bits */ | |
1141 | unsigned int int_tv_support:1; | |
1142 | unsigned int lvds_dither:1; | |
1143 | unsigned int lvds_vbt:1; | |
1144 | unsigned int int_crt_support:1; | |
1145 | unsigned int lvds_use_ssc:1; | |
1146 | unsigned int display_clock_mode:1; | |
1147 | unsigned int fdi_rx_polarity_inverted:1; | |
1148 | int lvds_ssc_freq; | |
1149 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1150 | ||
1151 | /* eDP */ | |
1152 | int edp_rate; | |
1153 | int edp_lanes; | |
1154 | int edp_preemphasis; | |
1155 | int edp_vswing; | |
1156 | bool edp_initialized; | |
1157 | bool edp_support; | |
1158 | int edp_bpp; | |
1159 | struct edp_power_seq edp_pps; | |
1160 | ||
d17c5443 SK |
1161 | /* MIPI DSI */ |
1162 | struct { | |
1163 | u16 panel_id; | |
1164 | } dsi; | |
1165 | ||
41aa3448 RV |
1166 | int crt_ddc_pin; |
1167 | ||
1168 | int child_dev_num; | |
768f69c9 | 1169 | union child_device_config *child_dev; |
6acab15a PZ |
1170 | |
1171 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1172 | }; |
1173 | ||
77c122bc VS |
1174 | enum intel_ddb_partitioning { |
1175 | INTEL_DDB_PART_1_2, | |
1176 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1177 | }; | |
1178 | ||
1fd527cc VS |
1179 | struct intel_wm_level { |
1180 | bool enable; | |
1181 | uint32_t pri_val; | |
1182 | uint32_t spr_val; | |
1183 | uint32_t cur_val; | |
1184 | uint32_t fbc_val; | |
1185 | }; | |
1186 | ||
609cedef VS |
1187 | struct hsw_wm_values { |
1188 | uint32_t wm_pipe[3]; | |
1189 | uint32_t wm_lp[3]; | |
1190 | uint32_t wm_lp_spr[3]; | |
1191 | uint32_t wm_linetime[3]; | |
1192 | bool enable_fbc_wm; | |
1193 | enum intel_ddb_partitioning partitioning; | |
1194 | }; | |
1195 | ||
c67a470b PZ |
1196 | /* |
1197 | * This struct tracks the state needed for the Package C8+ feature. | |
1198 | * | |
1199 | * Package states C8 and deeper are really deep PC states that can only be | |
1200 | * reached when all the devices on the system allow it, so even if the graphics | |
1201 | * device allows PC8+, it doesn't mean the system will actually get to these | |
1202 | * states. | |
1203 | * | |
1204 | * Our driver only allows PC8+ when all the outputs are disabled, the power well | |
1205 | * is disabled and the GPU is idle. When these conditions are met, we manually | |
1206 | * do the other conditions: disable the interrupts, clocks and switch LCPLL | |
1207 | * refclk to Fclk. | |
1208 | * | |
1209 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
1210 | * the state of some registers, so when we come back from PC8+ we need to | |
1211 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
1212 | * need to take care of the registers kept by RC6. | |
1213 | * | |
1214 | * The interrupt disabling is part of the requirements. We can only leave the | |
1215 | * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we | |
1216 | * can lock the machine. | |
1217 | * | |
1218 | * Ideally every piece of our code that needs PC8+ disabled would call | |
1219 | * hsw_disable_package_c8, which would increment disable_count and prevent the | |
1220 | * system from reaching PC8+. But we don't have a symmetric way to do this for | |
1221 | * everything, so we have the requirements_met and gpu_idle variables. When we | |
1222 | * switch requirements_met or gpu_idle to true we decrease disable_count, and | |
1223 | * increase it in the opposite case. The requirements_met variable is true when | |
1224 | * all the CRTCs, encoders and the power well are disabled. The gpu_idle | |
1225 | * variable is true when the GPU is idle. | |
1226 | * | |
1227 | * In addition to everything, we only actually enable PC8+ if disable_count | |
1228 | * stays at zero for at least some seconds. This is implemented with the | |
1229 | * enable_work variable. We do this so we don't enable/disable PC8 dozens of | |
1230 | * consecutive times when all screens are disabled and some background app | |
1231 | * queries the state of our connectors, or we have some application constantly | |
1232 | * waking up to use the GPU. Only after the enable_work function actually | |
1233 | * enables PC8+ the "enable" variable will become true, which means that it can | |
1234 | * be false even if disable_count is 0. | |
1235 | * | |
1236 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1237 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1238 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1239 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
1240 | * case it happens, but if it actually happens we'll also update the variables | |
1241 | * inside struct regsave so when we restore the IRQs they will contain the | |
1242 | * latest expected values. | |
1243 | * | |
1244 | * For more, read "Display Sequences for Package C8" on our documentation. | |
1245 | */ | |
1246 | struct i915_package_c8 { | |
1247 | bool requirements_met; | |
1248 | bool gpu_idle; | |
1249 | bool irqs_disabled; | |
1250 | /* Only true after the delayed work task actually enables it. */ | |
1251 | bool enabled; | |
1252 | int disable_count; | |
1253 | struct mutex lock; | |
1254 | struct delayed_work enable_work; | |
1255 | ||
1256 | struct { | |
1257 | uint32_t deimr; | |
1258 | uint32_t sdeimr; | |
1259 | uint32_t gtimr; | |
1260 | uint32_t gtier; | |
1261 | uint32_t gen6_pmimr; | |
1262 | } regsave; | |
1263 | }; | |
1264 | ||
926321d5 DV |
1265 | enum intel_pipe_crc_source { |
1266 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1267 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1268 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1269 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1270 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1271 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1272 | INTEL_PIPE_CRC_SOURCE_TV, | |
1273 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1274 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1275 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1276 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1277 | INTEL_PIPE_CRC_SOURCE_MAX, |
1278 | }; | |
1279 | ||
8bf1e9f1 | 1280 | struct intel_pipe_crc_entry { |
ac2300d4 | 1281 | uint32_t frame; |
8bf1e9f1 SH |
1282 | uint32_t crc[5]; |
1283 | }; | |
1284 | ||
b2c88f5b | 1285 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1286 | struct intel_pipe_crc { |
d538bbdf DL |
1287 | spinlock_t lock; |
1288 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1289 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1290 | enum intel_pipe_crc_source source; |
d538bbdf | 1291 | int head, tail; |
07144428 | 1292 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1293 | }; |
1294 | ||
f4c956ad DV |
1295 | typedef struct drm_i915_private { |
1296 | struct drm_device *dev; | |
42dcedd4 | 1297 | struct kmem_cache *slab; |
f4c956ad DV |
1298 | |
1299 | const struct intel_device_info *info; | |
1300 | ||
1301 | int relative_constants_mode; | |
1302 | ||
1303 | void __iomem *regs; | |
1304 | ||
907b28c5 | 1305 | struct intel_uncore uncore; |
f4c956ad DV |
1306 | |
1307 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
1308 | ||
28c70f16 | 1309 | |
f4c956ad DV |
1310 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1311 | * controller on different i2c buses. */ | |
1312 | struct mutex gmbus_mutex; | |
1313 | ||
1314 | /** | |
1315 | * Base address of the gmbus and gpio block. | |
1316 | */ | |
1317 | uint32_t gpio_mmio_base; | |
1318 | ||
28c70f16 DV |
1319 | wait_queue_head_t gmbus_wait_queue; |
1320 | ||
f4c956ad DV |
1321 | struct pci_dev *bridge_dev; |
1322 | struct intel_ring_buffer ring[I915_NUM_RINGS]; | |
f72b3435 | 1323 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
1324 | |
1325 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
1326 | struct resource mch_res; |
1327 | ||
1328 | atomic_t irq_received; | |
1329 | ||
1330 | /* protects the irq masks */ | |
1331 | spinlock_t irq_lock; | |
1332 | ||
9ee32fea DV |
1333 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1334 | struct pm_qos_request pm_qos; | |
1335 | ||
f4c956ad | 1336 | /* DPIO indirect register protection */ |
09153000 | 1337 | struct mutex dpio_lock; |
f4c956ad DV |
1338 | |
1339 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1340 | union { |
1341 | u32 irq_mask; | |
1342 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1343 | }; | |
f4c956ad | 1344 | u32 gt_irq_mask; |
605cd25b | 1345 | u32 pm_irq_mask; |
f4c956ad | 1346 | |
f4c956ad | 1347 | struct work_struct hotplug_work; |
52d7eced | 1348 | bool enable_hotplug_processing; |
b543fb04 EE |
1349 | struct { |
1350 | unsigned long hpd_last_jiffies; | |
1351 | int hpd_cnt; | |
1352 | enum { | |
1353 | HPD_ENABLED = 0, | |
1354 | HPD_DISABLED = 1, | |
1355 | HPD_MARK_DISABLED = 2 | |
1356 | } hpd_mark; | |
1357 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 1358 | u32 hpd_event_bits; |
ac4c16c5 | 1359 | struct timer_list hotplug_reenable_timer; |
f4c956ad | 1360 | |
7f1f3851 | 1361 | int num_plane; |
f4c956ad | 1362 | |
5c3fe8b0 | 1363 | struct i915_fbc fbc; |
f4c956ad | 1364 | struct intel_opregion opregion; |
41aa3448 | 1365 | struct intel_vbt_data vbt; |
f4c956ad DV |
1366 | |
1367 | /* overlay */ | |
1368 | struct intel_overlay *overlay; | |
2c6602df | 1369 | unsigned int sprite_scaling_enabled; |
f4c956ad | 1370 | |
31ad8ec6 JN |
1371 | /* backlight */ |
1372 | struct { | |
1373 | int level; | |
1374 | bool enabled; | |
8ba2d185 | 1375 | spinlock_t lock; /* bl registers and the above bl fields */ |
31ad8ec6 JN |
1376 | struct backlight_device *device; |
1377 | } backlight; | |
1378 | ||
f4c956ad | 1379 | /* LVDS info */ |
f4c956ad DV |
1380 | bool no_aux_handshake; |
1381 | ||
f4c956ad DV |
1382 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1383 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1384 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1385 | ||
1386 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
1387 | ||
645416f5 DV |
1388 | /** |
1389 | * wq - Driver workqueue for GEM. | |
1390 | * | |
1391 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1392 | * locks, for otherwise the flushing done in the pageflip code will | |
1393 | * result in deadlocks. | |
1394 | */ | |
f4c956ad DV |
1395 | struct workqueue_struct *wq; |
1396 | ||
1397 | /* Display functions */ | |
1398 | struct drm_i915_display_funcs display; | |
1399 | ||
1400 | /* PCH chipset type */ | |
1401 | enum intel_pch pch_type; | |
17a303ec | 1402 | unsigned short pch_id; |
f4c956ad DV |
1403 | |
1404 | unsigned long quirks; | |
1405 | ||
b8efb17b ZR |
1406 | enum modeset_restore modeset_restore; |
1407 | struct mutex modeset_restore_lock; | |
673a394b | 1408 | |
a7bbbd63 | 1409 | struct list_head vm_list; /* Global list of all address spaces */ |
853ba5d2 | 1410 | struct i915_gtt gtt; /* VMA representing the global address space */ |
5d4545ae | 1411 | |
4b5aed62 | 1412 | struct i915_gem_mm mm; |
8781342d | 1413 | |
8781342d DV |
1414 | /* Kernel Modesetting */ |
1415 | ||
9b9d172d | 1416 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1417 | |
27f8227b JB |
1418 | struct drm_crtc *plane_to_crtc_mapping[3]; |
1419 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
1420 | wait_queue_head_t pending_flip_queue; |
1421 | ||
c4597872 DV |
1422 | #ifdef CONFIG_DEBUG_FS |
1423 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1424 | #endif | |
1425 | ||
e72f9fbf DV |
1426 | int num_shared_dpll; |
1427 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
6441ab5f | 1428 | struct intel_ddi_plls ddi_plls; |
ee7b9f93 | 1429 | |
652c393a JB |
1430 | /* Reclocking support */ |
1431 | bool render_reclock_avail; | |
1432 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1433 | /* indicates the reduced downclock for LVDS*/ |
1434 | int lvds_downclock; | |
652c393a | 1435 | u16 orig_clock; |
f97108d1 | 1436 | |
c4804411 | 1437 | bool mchbar_need_disable; |
f97108d1 | 1438 | |
a4da4fa4 DV |
1439 | struct intel_l3_parity l3_parity; |
1440 | ||
59124506 BW |
1441 | /* Cannot be determined by PCIID. You must always read a register. */ |
1442 | size_t ellc_size; | |
1443 | ||
c6a828d3 | 1444 | /* gen6+ rps state */ |
c85aa885 | 1445 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1446 | |
20e4d407 DV |
1447 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1448 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1449 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1450 | |
83c00f55 | 1451 | struct i915_power_domains power_domains; |
a38911a3 | 1452 | |
a031d709 | 1453 | struct i915_psr psr; |
3f51e471 | 1454 | |
99584db3 | 1455 | struct i915_gpu_error gpu_error; |
ae681d96 | 1456 | |
c9cddffc JB |
1457 | struct drm_i915_gem_object *vlv_pctx; |
1458 | ||
4520f53a | 1459 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1460 | /* list of fbdev register on this device */ |
1461 | struct intel_fbdev *fbdev; | |
4520f53a | 1462 | #endif |
e953fd7b | 1463 | |
073f34d9 JB |
1464 | /* |
1465 | * The console may be contended at resume, but we don't | |
1466 | * want it to block on it. | |
1467 | */ | |
1468 | struct work_struct console_resume_work; | |
1469 | ||
e953fd7b | 1470 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1471 | struct drm_property *force_audio_property; |
e3689190 | 1472 | |
254f965c BW |
1473 | bool hw_contexts_disabled; |
1474 | uint32_t hw_context_size; | |
a33afea5 | 1475 | struct list_head context_list; |
f4c956ad | 1476 | |
3e68320e | 1477 | u32 fdi_rx_config; |
68d18ad7 | 1478 | |
f4c956ad | 1479 | struct i915_suspend_saved_registers regfile; |
231f42a4 | 1480 | |
53615a5e VS |
1481 | struct { |
1482 | /* | |
1483 | * Raw watermark latency values: | |
1484 | * in 0.1us units for WM0, | |
1485 | * in 0.5us units for WM1+. | |
1486 | */ | |
1487 | /* primary */ | |
1488 | uint16_t pri_latency[5]; | |
1489 | /* sprite */ | |
1490 | uint16_t spr_latency[5]; | |
1491 | /* cursor */ | |
1492 | uint16_t cur_latency[5]; | |
609cedef VS |
1493 | |
1494 | /* current hardware state */ | |
1495 | struct hsw_wm_values hw; | |
53615a5e VS |
1496 | } wm; |
1497 | ||
c67a470b PZ |
1498 | struct i915_package_c8 pc8; |
1499 | ||
231f42a4 DV |
1500 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
1501 | * here! */ | |
1502 | struct i915_dri1_state dri1; | |
db1b76ca DV |
1503 | /* Old ums support infrastructure, same warning applies. */ |
1504 | struct i915_ums_state ums; | |
1da177e4 LT |
1505 | } drm_i915_private_t; |
1506 | ||
2c1792a1 CW |
1507 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1508 | { | |
1509 | return dev->dev_private; | |
1510 | } | |
1511 | ||
b4519513 CW |
1512 | /* Iterate over initialised rings */ |
1513 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1514 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1515 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1516 | ||
b1d7e4b4 WF |
1517 | enum hdmi_force_audio { |
1518 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1519 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1520 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1521 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1522 | }; | |
1523 | ||
190d6cd5 | 1524 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1525 | |
37e680a1 CW |
1526 | struct drm_i915_gem_object_ops { |
1527 | /* Interface between the GEM object and its backing storage. | |
1528 | * get_pages() is called once prior to the use of the associated set | |
1529 | * of pages before to binding them into the GTT, and put_pages() is | |
1530 | * called after we no longer need them. As we expect there to be | |
1531 | * associated cost with migrating pages between the backing storage | |
1532 | * and making them available for the GPU (e.g. clflush), we may hold | |
1533 | * onto the pages after they are no longer referenced by the GPU | |
1534 | * in case they may be used again shortly (for example migrating the | |
1535 | * pages to a different memory domain within the GTT). put_pages() | |
1536 | * will therefore most likely be called when the object itself is | |
1537 | * being released or under memory pressure (where we attempt to | |
1538 | * reap pages for the shrinker). | |
1539 | */ | |
1540 | int (*get_pages)(struct drm_i915_gem_object *); | |
1541 | void (*put_pages)(struct drm_i915_gem_object *); | |
1542 | }; | |
1543 | ||
673a394b | 1544 | struct drm_i915_gem_object { |
c397b908 | 1545 | struct drm_gem_object base; |
673a394b | 1546 | |
37e680a1 CW |
1547 | const struct drm_i915_gem_object_ops *ops; |
1548 | ||
2f633156 BW |
1549 | /** List of VMAs backed by this object */ |
1550 | struct list_head vma_list; | |
1551 | ||
c1ad11fc CW |
1552 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1553 | struct drm_mm_node *stolen; | |
35c20a60 | 1554 | struct list_head global_list; |
673a394b | 1555 | |
69dc4987 | 1556 | struct list_head ring_list; |
b25cb2f8 BW |
1557 | /** Used in execbuf to temporarily hold a ref */ |
1558 | struct list_head obj_exec_link; | |
673a394b EA |
1559 | |
1560 | /** | |
65ce3027 CW |
1561 | * This is set if the object is on the active lists (has pending |
1562 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1563 | * inactive (ready to be unbound) list. | |
673a394b | 1564 | */ |
0206e353 | 1565 | unsigned int active:1; |
673a394b EA |
1566 | |
1567 | /** | |
1568 | * This is set if the object has been written to since last bound | |
1569 | * to the GTT | |
1570 | */ | |
0206e353 | 1571 | unsigned int dirty:1; |
778c3544 DV |
1572 | |
1573 | /** | |
1574 | * Fence register bits (if any) for this object. Will be set | |
1575 | * as needed when mapped into the GTT. | |
1576 | * Protected by dev->struct_mutex. | |
778c3544 | 1577 | */ |
4b9de737 | 1578 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1579 | |
778c3544 DV |
1580 | /** |
1581 | * Advice: are the backing pages purgeable? | |
1582 | */ | |
0206e353 | 1583 | unsigned int madv:2; |
778c3544 | 1584 | |
778c3544 DV |
1585 | /** |
1586 | * Current tiling mode for the object. | |
1587 | */ | |
0206e353 | 1588 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1589 | /** |
1590 | * Whether the tiling parameters for the currently associated fence | |
1591 | * register have changed. Note that for the purposes of tracking | |
1592 | * tiling changes we also treat the unfenced register, the register | |
1593 | * slot that the object occupies whilst it executes a fenced | |
1594 | * command (such as BLT on gen2/3), as a "fence". | |
1595 | */ | |
1596 | unsigned int fence_dirty:1; | |
778c3544 DV |
1597 | |
1598 | /** How many users have pinned this object in GTT space. The following | |
1599 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
1600 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
1601 | * times for the same batchbuffer), and the framebuffer code. When | |
1602 | * switching/pageflipping, the framebuffer code has at most two buffers | |
1603 | * pinned per crtc. | |
1604 | * | |
1605 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
1606 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 1607 | unsigned int pin_count:4; |
778c3544 | 1608 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 1609 | |
75e9e915 DV |
1610 | /** |
1611 | * Is the object at the current location in the gtt mappable and | |
1612 | * fenceable? Used to avoid costly recalculations. | |
1613 | */ | |
0206e353 | 1614 | unsigned int map_and_fenceable:1; |
75e9e915 | 1615 | |
fb7d516a DV |
1616 | /** |
1617 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1618 | * mappable by accident). Track pin and fault separate for a more | |
1619 | * accurate mappable working set. | |
1620 | */ | |
0206e353 AJ |
1621 | unsigned int fault_mappable:1; |
1622 | unsigned int pin_mappable:1; | |
cc98b413 | 1623 | unsigned int pin_display:1; |
fb7d516a | 1624 | |
caea7476 CW |
1625 | /* |
1626 | * Is the GPU currently using a fence to access this buffer, | |
1627 | */ | |
1628 | unsigned int pending_fenced_gpu_access:1; | |
1629 | unsigned int fenced_gpu_access:1; | |
1630 | ||
651d794f | 1631 | unsigned int cache_level:3; |
93dfb40c | 1632 | |
7bddb01f | 1633 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1634 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1635 | unsigned int has_dma_mapping:1; |
7bddb01f | 1636 | |
9da3da66 | 1637 | struct sg_table *pages; |
a5570178 | 1638 | int pages_pin_count; |
673a394b | 1639 | |
1286ff73 | 1640 | /* prime dma-buf support */ |
9a70cc2a DA |
1641 | void *dma_buf_vmapping; |
1642 | int vmapping_count; | |
1643 | ||
caea7476 CW |
1644 | struct intel_ring_buffer *ring; |
1645 | ||
1c293ea3 | 1646 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1647 | uint32_t last_read_seqno; |
1648 | uint32_t last_write_seqno; | |
caea7476 CW |
1649 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1650 | uint32_t last_fenced_seqno; | |
673a394b | 1651 | |
778c3544 | 1652 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1653 | uint32_t stride; |
673a394b | 1654 | |
80075d49 DV |
1655 | /** References from framebuffers, locks out tiling changes. */ |
1656 | unsigned long framebuffer_references; | |
1657 | ||
280b713b | 1658 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1659 | unsigned long *bit_17; |
280b713b | 1660 | |
79e53945 | 1661 | /** User space pin count and filp owning the pin */ |
aa5f8021 | 1662 | unsigned long user_pin_count; |
79e53945 | 1663 | struct drm_file *pin_filp; |
71acb5eb DA |
1664 | |
1665 | /** for phy allocated objects */ | |
1666 | struct drm_i915_gem_phys_object *phys_obj; | |
673a394b | 1667 | }; |
b45305fc | 1668 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
673a394b | 1669 | |
62b8b215 | 1670 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1671 | |
673a394b EA |
1672 | /** |
1673 | * Request queue structure. | |
1674 | * | |
1675 | * The request queue allows us to note sequence numbers that have been emitted | |
1676 | * and may be associated with active buffers to be retired. | |
1677 | * | |
1678 | * By keeping this list, we can avoid having to do questionable | |
1679 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1680 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1681 | */ | |
1682 | struct drm_i915_gem_request { | |
852835f3 ZN |
1683 | /** On Which ring this request was generated */ |
1684 | struct intel_ring_buffer *ring; | |
1685 | ||
673a394b EA |
1686 | /** GEM sequence number associated with this request. */ |
1687 | uint32_t seqno; | |
1688 | ||
7d736f4f MK |
1689 | /** Position in the ringbuffer of the start of the request */ |
1690 | u32 head; | |
1691 | ||
1692 | /** Position in the ringbuffer of the end of the request */ | |
a71d8d94 CW |
1693 | u32 tail; |
1694 | ||
0e50e96b MK |
1695 | /** Context related to this request */ |
1696 | struct i915_hw_context *ctx; | |
1697 | ||
7d736f4f MK |
1698 | /** Batch buffer related to this request if any */ |
1699 | struct drm_i915_gem_object *batch_obj; | |
1700 | ||
673a394b EA |
1701 | /** Time at which this request was emitted, in jiffies. */ |
1702 | unsigned long emitted_jiffies; | |
1703 | ||
b962442e | 1704 | /** global list entry for this request */ |
673a394b | 1705 | struct list_head list; |
b962442e | 1706 | |
f787a5f5 | 1707 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1708 | /** file_priv list entry for this request */ |
1709 | struct list_head client_list; | |
673a394b EA |
1710 | }; |
1711 | ||
1712 | struct drm_i915_file_private { | |
b29c19b6 CW |
1713 | struct drm_i915_private *dev_priv; |
1714 | ||
673a394b | 1715 | struct { |
99057c81 | 1716 | spinlock_t lock; |
b962442e | 1717 | struct list_head request_list; |
b29c19b6 | 1718 | struct delayed_work idle_work; |
673a394b | 1719 | } mm; |
40521054 | 1720 | struct idr context_idr; |
e59ec13d MK |
1721 | |
1722 | struct i915_ctx_hang_stats hang_stats; | |
b29c19b6 | 1723 | atomic_t rps_wait_boost; |
673a394b EA |
1724 | }; |
1725 | ||
2c1792a1 | 1726 | #define INTEL_INFO(dev) (to_i915(dev)->info) |
cae5852d | 1727 | |
ffbab09b VS |
1728 | #define IS_I830(dev) ((dev)->pdev->device == 0x3577) |
1729 | #define IS_845G(dev) ((dev)->pdev->device == 0x2562) | |
cae5852d | 1730 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
ffbab09b | 1731 | #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) |
cae5852d | 1732 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
ffbab09b VS |
1733 | #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) |
1734 | #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) | |
cae5852d ZN |
1735 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
1736 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1737 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
ffbab09b | 1738 | #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) |
cae5852d | 1739 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
ffbab09b VS |
1740 | #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) |
1741 | #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) | |
cae5852d ZN |
1742 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
1743 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
ffbab09b | 1744 | #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) |
4b65177b | 1745 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
ffbab09b VS |
1746 | #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ |
1747 | (dev)->pdev->device == 0x0152 || \ | |
1748 | (dev)->pdev->device == 0x015a) | |
1749 | #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ | |
1750 | (dev)->pdev->device == 0x0106 || \ | |
1751 | (dev)->pdev->device == 0x010A) | |
70a3eb7a | 1752 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1753 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
4e8058a2 | 1754 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8) |
cae5852d | 1755 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 1756 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
ffbab09b | 1757 | ((dev)->pdev->device & 0xFF00) == 0x0C00) |
d567b07f | 1758 | #define IS_ULT(dev) (IS_HASWELL(dev) && \ |
ffbab09b | 1759 | ((dev)->pdev->device & 0xFF00) == 0x0A00) |
9435373e | 1760 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
ffbab09b | 1761 | ((dev)->pdev->device & 0x00F0) == 0x0020) |
b833d685 | 1762 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 1763 | |
85436696 JB |
1764 | /* |
1765 | * The genX designation typically refers to the render engine, so render | |
1766 | * capability related checks should use IS_GEN, while display and other checks | |
1767 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1768 | * chips, etc.). | |
1769 | */ | |
cae5852d ZN |
1770 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1771 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1772 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1773 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1774 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1775 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 1776 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
cae5852d | 1777 | |
73ae478c BW |
1778 | #define RENDER_RING (1<<RCS) |
1779 | #define BSD_RING (1<<VCS) | |
1780 | #define BLT_RING (1<<BCS) | |
1781 | #define VEBOX_RING (1<<VECS) | |
1782 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) | |
1783 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) | |
1784 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
3d29b842 | 1785 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
651d794f | 1786 | #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) |
cae5852d ZN |
1787 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1788 | ||
254f965c | 1789 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
93553609 | 1790 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
1d2a314c | 1791 | |
05394f39 | 1792 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1793 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1794 | ||
b45305fc DV |
1795 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1796 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
1797 | ||
cae5852d ZN |
1798 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1799 | * rows, which changed the alignment requirements and fence programming. | |
1800 | */ | |
1801 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1802 | IS_I915GM(dev))) | |
1803 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1804 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1805 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
cae5852d ZN |
1806 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
1807 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
1808 | |
1809 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1810 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1811 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1812 | |
2a114cc1 | 1813 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 1814 | |
dd93be58 | 1815 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
6745a2ce | 1816 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
30568c45 | 1817 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
ed8546ac | 1818 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
affa9354 | 1819 | |
17a303ec PZ |
1820 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1821 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
1822 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
1823 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
1824 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
1825 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
1826 | ||
2c1792a1 | 1827 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
eb877ebf | 1828 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1829 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1830 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 1831 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 1832 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1833 | |
040d2baa BW |
1834 | /* DPF == dynamic parity feature */ |
1835 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1836 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 1837 | |
c8735b0c BW |
1838 | #define GT_FREQUENCY_MULTIPLIER 50 |
1839 | ||
05394f39 CW |
1840 | #include "i915_trace.h" |
1841 | ||
baa70943 | 1842 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1843 | extern int i915_max_ioctl; |
a35d9d3c BW |
1844 | extern unsigned int i915_fbpercrtc __always_unused; |
1845 | extern int i915_panel_ignore_lid __read_mostly; | |
1846 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1847 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1848 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1849 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1850 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1851 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1852 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1853 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1854 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1855 | extern int i915_enable_ppgtt __read_mostly; |
105b7c11 | 1856 | extern int i915_enable_psr __read_mostly; |
0a3af268 | 1857 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
2124b72e | 1858 | extern int i915_disable_power_well __read_mostly; |
3c4ca58c | 1859 | extern int i915_enable_ips __read_mostly; |
2385bdf0 | 1860 | extern bool i915_fastboot __read_mostly; |
c67a470b | 1861 | extern int i915_enable_pc8 __read_mostly; |
90058745 | 1862 | extern int i915_pc8_timeout __read_mostly; |
0b74b508 | 1863 | extern bool i915_prefault_disable __read_mostly; |
b3a83639 | 1864 | |
6a9ee8af DA |
1865 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1866 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1867 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1868 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1869 | ||
1da177e4 | 1870 | /* i915_dma.c */ |
d05c617e | 1871 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1872 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1873 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1874 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1875 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1876 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1877 | extern void i915_driver_preclose(struct drm_device *dev, |
1878 | struct drm_file *file_priv); | |
673a394b EA |
1879 | extern void i915_driver_postclose(struct drm_device *dev, |
1880 | struct drm_file *file_priv); | |
84b1fd10 | 1881 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1882 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1883 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1884 | unsigned long arg); | |
c43b5634 | 1885 | #endif |
673a394b | 1886 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1887 | struct drm_clip_rect *box, |
1888 | int DR1, int DR4); | |
8e96d9c4 | 1889 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1890 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
1891 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1892 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1893 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1894 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1895 | ||
073f34d9 | 1896 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 1897 | |
1da177e4 | 1898 | /* i915_irq.c */ |
10cd45b6 | 1899 | void i915_queue_hangcheck(struct drm_device *dev); |
527f9e90 | 1900 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 1901 | |
f71d4af4 | 1902 | extern void intel_irq_init(struct drm_device *dev); |
e1b4d303 | 1903 | extern void intel_pm_init(struct drm_device *dev); |
20afbda2 | 1904 | extern void intel_hpd_init(struct drm_device *dev); |
907b28c5 CW |
1905 | extern void intel_pm_init(struct drm_device *dev); |
1906 | ||
1907 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
1908 | extern void intel_uncore_early_sanitize(struct drm_device *dev); | |
1909 | extern void intel_uncore_init(struct drm_device *dev); | |
907b28c5 CW |
1910 | extern void intel_uncore_clear_errors(struct drm_device *dev); |
1911 | extern void intel_uncore_check_errors(struct drm_device *dev); | |
aec347ab | 1912 | extern void intel_uncore_fini(struct drm_device *dev); |
b1f14ad0 | 1913 | |
7c463586 | 1914 | void |
3b6c42e8 | 1915 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
7c463586 KP |
1916 | |
1917 | void | |
3b6c42e8 | 1918 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
7c463586 | 1919 | |
673a394b EA |
1920 | /* i915_gem.c */ |
1921 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1922 | struct drm_file *file_priv); | |
1923 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1924 | struct drm_file *file_priv); | |
1925 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1926 | struct drm_file *file_priv); | |
1927 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1928 | struct drm_file *file_priv); | |
1929 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1930 | struct drm_file *file_priv); | |
de151cf6 JB |
1931 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1932 | struct drm_file *file_priv); | |
673a394b EA |
1933 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1934 | struct drm_file *file_priv); | |
1935 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1936 | struct drm_file *file_priv); | |
1937 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1938 | struct drm_file *file_priv); | |
76446cac JB |
1939 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1940 | struct drm_file *file_priv); | |
673a394b EA |
1941 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1942 | struct drm_file *file_priv); | |
1943 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1944 | struct drm_file *file_priv); | |
1945 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1946 | struct drm_file *file_priv); | |
199adf40 BW |
1947 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1948 | struct drm_file *file); | |
1949 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
1950 | struct drm_file *file); | |
673a394b EA |
1951 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1952 | struct drm_file *file_priv); | |
3ef94daa CW |
1953 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1954 | struct drm_file *file_priv); | |
673a394b EA |
1955 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1956 | struct drm_file *file_priv); | |
1957 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1958 | struct drm_file *file_priv); | |
1959 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1960 | struct drm_file *file_priv); | |
1961 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1962 | struct drm_file *file_priv); | |
5a125c3c EA |
1963 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1964 | struct drm_file *file_priv); | |
23ba4fd0 BW |
1965 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1966 | struct drm_file *file_priv); | |
673a394b | 1967 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
1968 | void *i915_gem_object_alloc(struct drm_device *dev); |
1969 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
1970 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1971 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
1972 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1973 | size_t size); | |
673a394b | 1974 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 1975 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 1976 | |
2021746e | 1977 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 1978 | struct i915_address_space *vm, |
2021746e | 1979 | uint32_t alignment, |
86a1ee26 CW |
1980 | bool map_and_fenceable, |
1981 | bool nonblocking); | |
05394f39 | 1982 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
07fe0b12 BW |
1983 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
1984 | int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); | |
dd624afd | 1985 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
05394f39 | 1986 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1987 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1988 | |
37e680a1 | 1989 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
1990 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
1991 | { | |
67d5a50c ID |
1992 | struct sg_page_iter sg_iter; |
1993 | ||
1994 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 1995 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
1996 | |
1997 | return NULL; | |
9da3da66 | 1998 | } |
a5570178 CW |
1999 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2000 | { | |
2001 | BUG_ON(obj->pages == NULL); | |
2002 | obj->pages_pin_count++; | |
2003 | } | |
2004 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2005 | { | |
2006 | BUG_ON(obj->pages_pin_count == 0); | |
2007 | obj->pages_pin_count--; | |
2008 | } | |
2009 | ||
54cf91dc | 2010 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
2011 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2012 | struct intel_ring_buffer *to); | |
e2d05a8b BW |
2013 | void i915_vma_move_to_active(struct i915_vma *vma, |
2014 | struct intel_ring_buffer *ring); | |
ff72145b DA |
2015 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2016 | struct drm_device *dev, | |
2017 | struct drm_mode_create_dumb *args); | |
2018 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
2019 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2020 | /** |
2021 | * Returns true if seq1 is later than seq2. | |
2022 | */ | |
2023 | static inline bool | |
2024 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2025 | { | |
2026 | return (int32_t)(seq1 - seq2) >= 0; | |
2027 | } | |
2028 | ||
fca26bb4 MK |
2029 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2030 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 2031 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 2032 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 2033 | |
9a5a53b3 | 2034 | static inline bool |
1690e1eb CW |
2035 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
2036 | { | |
2037 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2038 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2039 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
2040 | return true; |
2041 | } else | |
2042 | return false; | |
1690e1eb CW |
2043 | } |
2044 | ||
2045 | static inline void | |
2046 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
2047 | { | |
2048 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2049 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
b8c3af76 | 2050 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
1690e1eb CW |
2051 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
2052 | } | |
2053 | } | |
2054 | ||
b29c19b6 | 2055 | bool i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 2056 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
33196ded | 2057 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2058 | bool interruptible); |
1f83fee0 DV |
2059 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2060 | { | |
2061 | return unlikely(atomic_read(&error->reset_counter) | |
2062 | & I915_RESET_IN_PROGRESS_FLAG); | |
2063 | } | |
2064 | ||
2065 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2066 | { | |
2067 | return atomic_read(&error->reset_counter) == I915_WEDGED; | |
2068 | } | |
a71d8d94 | 2069 | |
069efc1d | 2070 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2071 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
a8198eea | 2072 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 2073 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 2074 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
c3787e2e | 2075 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice); |
f691e2f4 | 2076 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2077 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2078 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2079 | int __must_check i915_gem_suspend(struct drm_device *dev); |
0025c077 MK |
2080 | int __i915_add_request(struct intel_ring_buffer *ring, |
2081 | struct drm_file *file, | |
7d736f4f | 2082 | struct drm_i915_gem_object *batch_obj, |
0025c077 MK |
2083 | u32 *seqno); |
2084 | #define i915_add_request(ring, seqno) \ | |
854c94a7 | 2085 | __i915_add_request(ring, NULL, NULL, seqno) |
199b2bc2 BW |
2086 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
2087 | uint32_t seqno); | |
de151cf6 | 2088 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
2089 | int __must_check |
2090 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
2091 | bool write); | |
2092 | int __must_check | |
dabdfe02 CW |
2093 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2094 | int __must_check | |
2da3b9b9 CW |
2095 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2096 | u32 alignment, | |
2021746e | 2097 | struct intel_ring_buffer *pipelined); |
cc98b413 | 2098 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
71acb5eb | 2099 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 2100 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
2101 | int id, |
2102 | int align); | |
71acb5eb | 2103 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 2104 | struct drm_i915_gem_object *obj); |
71acb5eb | 2105 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
b29c19b6 | 2106 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2107 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2108 | |
0fa87796 ID |
2109 | uint32_t |
2110 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2111 | uint32_t |
d865110c ID |
2112 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2113 | int tiling_mode, bool fenced); | |
467cffba | 2114 | |
e4ffd173 CW |
2115 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2116 | enum i915_cache_level cache_level); | |
2117 | ||
1286ff73 DV |
2118 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2119 | struct dma_buf *dma_buf); | |
2120 | ||
2121 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2122 | struct drm_gem_object *gem_obj, int flags); | |
2123 | ||
19b2dbde CW |
2124 | void i915_gem_restore_fences(struct drm_device *dev); |
2125 | ||
a70a3148 BW |
2126 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
2127 | struct i915_address_space *vm); | |
2128 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); | |
2129 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
2130 | struct i915_address_space *vm); | |
2131 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
2132 | struct i915_address_space *vm); | |
2133 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
2134 | struct i915_address_space *vm); | |
accfef2e BW |
2135 | struct i915_vma * |
2136 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2137 | struct i915_address_space *vm); | |
5c2abbea BW |
2138 | |
2139 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); | |
2140 | ||
a70a3148 BW |
2141 | /* Some GGTT VM helpers */ |
2142 | #define obj_to_ggtt(obj) \ | |
2143 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) | |
2144 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2145 | { | |
2146 | struct i915_address_space *ggtt = | |
2147 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2148 | return vm == ggtt; | |
2149 | } | |
2150 | ||
2151 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) | |
2152 | { | |
2153 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); | |
2154 | } | |
2155 | ||
2156 | static inline unsigned long | |
2157 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) | |
2158 | { | |
2159 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); | |
2160 | } | |
2161 | ||
2162 | static inline unsigned long | |
2163 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2164 | { | |
2165 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); | |
2166 | } | |
c37e2204 BW |
2167 | |
2168 | static inline int __must_check | |
2169 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2170 | uint32_t alignment, | |
2171 | bool map_and_fenceable, | |
2172 | bool nonblocking) | |
2173 | { | |
2174 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, | |
2175 | map_and_fenceable, nonblocking); | |
2176 | } | |
a70a3148 | 2177 | |
254f965c BW |
2178 | /* i915_gem_context.c */ |
2179 | void i915_gem_context_init(struct drm_device *dev); | |
2180 | void i915_gem_context_fini(struct drm_device *dev); | |
254f965c | 2181 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 BW |
2182 | int i915_switch_context(struct intel_ring_buffer *ring, |
2183 | struct drm_file *file, int to_id); | |
dce3271b MK |
2184 | void i915_gem_context_free(struct kref *ctx_ref); |
2185 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) | |
2186 | { | |
2187 | kref_get(&ctx->ref); | |
2188 | } | |
2189 | ||
2190 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) | |
2191 | { | |
2192 | kref_put(&ctx->ref, i915_gem_context_free); | |
2193 | } | |
2194 | ||
c0bb617a | 2195 | struct i915_ctx_hang_stats * __must_check |
11fa3384 | 2196 | i915_gem_context_get_hang_stats(struct drm_device *dev, |
c0bb617a MK |
2197 | struct drm_file *file, |
2198 | u32 id); | |
84624813 BW |
2199 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2200 | struct drm_file *file); | |
2201 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
2202 | struct drm_file *file); | |
1286ff73 | 2203 | |
76aaf220 | 2204 | /* i915_gem_gtt.c */ |
1d2a314c | 2205 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
7bddb01f DV |
2206 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
2207 | struct drm_i915_gem_object *obj, | |
2208 | enum i915_cache_level cache_level); | |
2209 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
2210 | struct drm_i915_gem_object *obj); | |
1d2a314c | 2211 | |
828c7908 BW |
2212 | void i915_check_and_clear_faults(struct drm_device *dev); |
2213 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); | |
76aaf220 | 2214 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
2215 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
2216 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 2217 | enum i915_cache_level cache_level); |
05394f39 | 2218 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 2219 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
d7e5008f BW |
2220 | void i915_gem_init_global_gtt(struct drm_device *dev); |
2221 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, | |
2222 | unsigned long mappable_end, unsigned long end); | |
e76e9aeb | 2223 | int i915_gem_gtt_init(struct drm_device *dev); |
d09105c6 | 2224 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
2225 | { |
2226 | if (INTEL_INFO(dev)->gen < 6) | |
2227 | intel_gtt_chipset_flush(); | |
2228 | } | |
2229 | ||
76aaf220 | 2230 | |
b47eb4a2 | 2231 | /* i915_gem_evict.c */ |
f6cd1f15 BW |
2232 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
2233 | struct i915_address_space *vm, | |
2234 | int min_size, | |
42d6ab48 CW |
2235 | unsigned alignment, |
2236 | unsigned cache_level, | |
86a1ee26 CW |
2237 | bool mappable, |
2238 | bool nonblock); | |
68c8c17f | 2239 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
6c085a72 | 2240 | int i915_gem_evict_everything(struct drm_device *dev); |
b47eb4a2 | 2241 | |
9797fbfb CW |
2242 | /* i915_gem_stolen.c */ |
2243 | int i915_gem_init_stolen(struct drm_device *dev); | |
11be49eb CW |
2244 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
2245 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); | |
9797fbfb | 2246 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
2247 | struct drm_i915_gem_object * |
2248 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
2249 | struct drm_i915_gem_object * |
2250 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
2251 | u32 stolen_offset, | |
2252 | u32 gtt_offset, | |
2253 | u32 size); | |
0104fdbb | 2254 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
9797fbfb | 2255 | |
673a394b | 2256 | /* i915_gem_tiling.c */ |
2c1792a1 | 2257 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 CW |
2258 | { |
2259 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; | |
2260 | ||
2261 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
2262 | obj->tiling_mode != I915_TILING_NONE; | |
2263 | } | |
2264 | ||
673a394b | 2265 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
2266 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
2267 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
2268 | |
2269 | /* i915_gem_debug.c */ | |
23bc5982 CW |
2270 | #if WATCH_LISTS |
2271 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 2272 | #else |
23bc5982 | 2273 | #define i915_verify_lists(dev) 0 |
673a394b | 2274 | #endif |
1da177e4 | 2275 | |
2017263e | 2276 | /* i915_debugfs.c */ |
27c202ad BG |
2277 | int i915_debugfs_init(struct drm_minor *minor); |
2278 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 2279 | #ifdef CONFIG_DEBUG_FS |
07144428 DL |
2280 | void intel_display_crc_init(struct drm_device *dev); |
2281 | #else | |
f8c168fa | 2282 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 2283 | #endif |
84734a04 MK |
2284 | |
2285 | /* i915_gpu_error.c */ | |
edc3d884 MK |
2286 | __printf(2, 3) |
2287 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
2288 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
2289 | const struct i915_error_state_file_priv *error); | |
4dc955f7 MK |
2290 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
2291 | size_t count, loff_t pos); | |
2292 | static inline void i915_error_state_buf_release( | |
2293 | struct drm_i915_error_state_buf *eb) | |
2294 | { | |
2295 | kfree(eb->buf); | |
2296 | } | |
84734a04 MK |
2297 | void i915_capture_error_state(struct drm_device *dev); |
2298 | void i915_error_state_get(struct drm_device *dev, | |
2299 | struct i915_error_state_file_priv *error_priv); | |
2300 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
2301 | void i915_destroy_error_state(struct drm_device *dev); | |
2302 | ||
2303 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
2304 | const char *i915_cache_level_str(int type); | |
2017263e | 2305 | |
317c35d1 JB |
2306 | /* i915_suspend.c */ |
2307 | extern int i915_save_state(struct drm_device *dev); | |
2308 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 2309 | |
d8157a36 DV |
2310 | /* i915_ums.c */ |
2311 | void i915_save_display_reg(struct drm_device *dev); | |
2312 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 2313 | |
0136db58 BW |
2314 | /* i915_sysfs.c */ |
2315 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
2316 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
2317 | ||
f899fc64 CW |
2318 | /* intel_i2c.c */ |
2319 | extern int intel_setup_gmbus(struct drm_device *dev); | |
2320 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
8f375e10 | 2321 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3bd7d909 | 2322 | { |
2ed06c93 | 2323 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
2324 | } |
2325 | ||
2326 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
2327 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
2328 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
2329 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 2330 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
2331 | { |
2332 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
2333 | } | |
f899fc64 CW |
2334 | extern void intel_i2c_reset(struct drm_device *dev); |
2335 | ||
3b617967 | 2336 | /* intel_opregion.c */ |
9c4b0a68 | 2337 | struct intel_encoder; |
44834a67 CW |
2338 | extern int intel_opregion_setup(struct drm_device *dev); |
2339 | #ifdef CONFIG_ACPI | |
2340 | extern void intel_opregion_init(struct drm_device *dev); | |
2341 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 2342 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
2343 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
2344 | bool enable); | |
ecbc5cf3 JN |
2345 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
2346 | pci_power_t state); | |
65e082c9 | 2347 | #else |
44834a67 CW |
2348 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
2349 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 2350 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
2351 | static inline int |
2352 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
2353 | { | |
2354 | return 0; | |
2355 | } | |
ecbc5cf3 JN |
2356 | static inline int |
2357 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
2358 | { | |
2359 | return 0; | |
2360 | } | |
65e082c9 | 2361 | #endif |
8ee1c3db | 2362 | |
723bfd70 JB |
2363 | /* intel_acpi.c */ |
2364 | #ifdef CONFIG_ACPI | |
2365 | extern void intel_register_dsm_handler(void); | |
2366 | extern void intel_unregister_dsm_handler(void); | |
2367 | #else | |
2368 | static inline void intel_register_dsm_handler(void) { return; } | |
2369 | static inline void intel_unregister_dsm_handler(void) { return; } | |
2370 | #endif /* CONFIG_ACPI */ | |
2371 | ||
79e53945 | 2372 | /* modesetting */ |
f817586c | 2373 | extern void intel_modeset_init_hw(struct drm_device *dev); |
7d708ee4 | 2374 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
79e53945 | 2375 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 2376 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 2377 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 2378 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
2379 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
2380 | bool force_restore); | |
44cec740 | 2381 | extern void i915_redisable_vga(struct drm_device *dev); |
ee5382ae | 2382 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 2383 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 2384 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 2385 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 2386 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 JB |
2387 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
2388 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); | |
2389 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); | |
0206e353 AJ |
2390 | extern void intel_detect_pch(struct drm_device *dev); |
2391 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 2392 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 2393 | |
2911a35b | 2394 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
2395 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
2396 | struct drm_file *file); | |
575155a9 | 2397 | |
6ef3d427 CW |
2398 | /* overlay */ |
2399 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
2400 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
2401 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
2402 | |
2403 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 2404 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
2405 | struct drm_device *dev, |
2406 | struct intel_display_error_state *error); | |
6ef3d427 | 2407 | |
b7287d80 BW |
2408 | /* On SNB platform, before reading ring registers forcewake bit |
2409 | * must be set to prevent GT core from power down and stale values being | |
2410 | * returned. | |
2411 | */ | |
fcca7926 BW |
2412 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
2413 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
b7287d80 | 2414 | |
42c0526c BW |
2415 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
2416 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
59de0813 JN |
2417 | |
2418 | /* intel_sideband.c */ | |
64936258 JN |
2419 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
2420 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
2421 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
e9f882a3 JN |
2422 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
2423 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2424 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
2425 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2426 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
2427 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2428 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); | |
2429 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
2430 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
2431 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
2432 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
2433 | enum intel_sbi_destination destination); | |
2434 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
2435 | enum intel_sbi_destination destination); | |
0a073b84 | 2436 | |
855ba3be JB |
2437 | int vlv_gpu_freq(int ddr_freq, int val); |
2438 | int vlv_freq_opcode(int ddr_freq, int val); | |
42c0526c | 2439 | |
0b274481 BW |
2440 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
2441 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
2442 | ||
2443 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
2444 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
2445 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
2446 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
2447 | ||
2448 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
2449 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
2450 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
2451 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
2452 | ||
2453 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) | |
2454 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d ZN |
2455 | |
2456 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
2457 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
2458 | ||
55bc60db VS |
2459 | /* "Broadcast RGB" property */ |
2460 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
2461 | #define INTEL_BROADCAST_RGB_FULL 1 | |
2462 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 2463 | |
766aa1c4 VS |
2464 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
2465 | { | |
2466 | if (HAS_PCH_SPLIT(dev)) | |
2467 | return CPU_VGACNTRL; | |
2468 | else if (IS_VALLEYVIEW(dev)) | |
2469 | return VLV_VGACNTRL; | |
2470 | else | |
2471 | return VGACNTRL; | |
2472 | } | |
2473 | ||
2bb4629a VS |
2474 | static inline void __user *to_user_ptr(u64 address) |
2475 | { | |
2476 | return (void __user *)(uintptr_t)address; | |
2477 | } | |
2478 | ||
df97729f ID |
2479 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
2480 | { | |
2481 | unsigned long j = msecs_to_jiffies(m); | |
2482 | ||
2483 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2484 | } | |
2485 | ||
2486 | static inline unsigned long | |
2487 | timespec_to_jiffies_timeout(const struct timespec *value) | |
2488 | { | |
2489 | unsigned long j = timespec_to_jiffies(value); | |
2490 | ||
2491 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2492 | } | |
2493 | ||
1da177e4 | 2494 | #endif |