Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
5cc9ed4b | 40 | #include <linux/hashtable.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
9ee32fea | 43 | #include <linux/pm_qos.h> |
e73bdd20 CW |
44 | #include <linux/shmem_fs.h> |
45 | ||
46 | #include <drm/drmP.h> | |
47 | #include <drm/intel-gtt.h> | |
48 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
49 | #include <drm/drm_gem.h> | |
3b96a0b1 | 50 | #include <drm/drm_auth.h> |
e73bdd20 CW |
51 | |
52 | #include "i915_params.h" | |
53 | #include "i915_reg.h" | |
54 | ||
55 | #include "intel_bios.h" | |
ac7f11c6 | 56 | #include "intel_dpll_mgr.h" |
e73bdd20 CW |
57 | #include "intel_guc.h" |
58 | #include "intel_lrc.h" | |
59 | #include "intel_ringbuffer.h" | |
60 | ||
d501b1d2 | 61 | #include "i915_gem.h" |
e73bdd20 CW |
62 | #include "i915_gem_gtt.h" |
63 | #include "i915_gem_render_state.h" | |
05235c53 | 64 | #include "i915_gem_request.h" |
585fb111 | 65 | |
0ad35fed ZW |
66 | #include "intel_gvt.h" |
67 | ||
1da177e4 LT |
68 | /* General customization: |
69 | */ | |
70 | ||
1da177e4 LT |
71 | #define DRIVER_NAME "i915" |
72 | #define DRIVER_DESC "Intel Graphics" | |
c5b7e97b | 73 | #define DRIVER_DATE "20160808" |
1da177e4 | 74 | |
c883ef1b | 75 | #undef WARN_ON |
5f77eeb0 DV |
76 | /* Many gcc seem to no see through this and fall over :( */ |
77 | #if 0 | |
78 | #define WARN_ON(x) ({ \ | |
79 | bool __i915_warn_cond = (x); \ | |
80 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
81 | BUILD_BUG_ON(__i915_warn_cond); \ | |
82 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
83 | #else | |
152b2262 | 84 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") |
5f77eeb0 DV |
85 | #endif |
86 | ||
cd9bfacb | 87 | #undef WARN_ON_ONCE |
152b2262 | 88 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") |
cd9bfacb | 89 | |
5f77eeb0 DV |
90 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
91 | (long) (x), __func__); | |
c883ef1b | 92 | |
e2c719b7 RC |
93 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
94 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
95 | * which may not necessarily be a user visible problem. This will either | |
96 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
97 | * enable distros and users to tailor their preferred amount of i915 abrt | |
98 | * spam. | |
99 | */ | |
100 | #define I915_STATE_WARN(condition, format...) ({ \ | |
101 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
102 | if (unlikely(__ret_warn_on)) \ |
103 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 104 | DRM_ERROR(format); \ |
e2c719b7 RC |
105 | unlikely(__ret_warn_on); \ |
106 | }) | |
107 | ||
152b2262 JL |
108 | #define I915_STATE_WARN_ON(x) \ |
109 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 110 | |
4fec15d1 ID |
111 | bool __i915_inject_load_failure(const char *func, int line); |
112 | #define i915_inject_load_failure() \ | |
113 | __i915_inject_load_failure(__func__, __LINE__) | |
114 | ||
42a8ca4c JN |
115 | static inline const char *yesno(bool v) |
116 | { | |
117 | return v ? "yes" : "no"; | |
118 | } | |
119 | ||
87ad3212 JN |
120 | static inline const char *onoff(bool v) |
121 | { | |
122 | return v ? "on" : "off"; | |
123 | } | |
124 | ||
317c35d1 | 125 | enum pipe { |
752aa88a | 126 | INVALID_PIPE = -1, |
317c35d1 JB |
127 | PIPE_A = 0, |
128 | PIPE_B, | |
9db4a9c7 | 129 | PIPE_C, |
a57c774a AK |
130 | _PIPE_EDP, |
131 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 132 | }; |
9db4a9c7 | 133 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 134 | |
a5c961d1 PZ |
135 | enum transcoder { |
136 | TRANSCODER_A = 0, | |
137 | TRANSCODER_B, | |
138 | TRANSCODER_C, | |
a57c774a | 139 | TRANSCODER_EDP, |
4d1de975 JN |
140 | TRANSCODER_DSI_A, |
141 | TRANSCODER_DSI_C, | |
a57c774a | 142 | I915_MAX_TRANSCODERS |
a5c961d1 | 143 | }; |
da205630 JN |
144 | |
145 | static inline const char *transcoder_name(enum transcoder transcoder) | |
146 | { | |
147 | switch (transcoder) { | |
148 | case TRANSCODER_A: | |
149 | return "A"; | |
150 | case TRANSCODER_B: | |
151 | return "B"; | |
152 | case TRANSCODER_C: | |
153 | return "C"; | |
154 | case TRANSCODER_EDP: | |
155 | return "EDP"; | |
4d1de975 JN |
156 | case TRANSCODER_DSI_A: |
157 | return "DSI A"; | |
158 | case TRANSCODER_DSI_C: | |
159 | return "DSI C"; | |
da205630 JN |
160 | default: |
161 | return "<invalid>"; | |
162 | } | |
163 | } | |
a5c961d1 | 164 | |
4d1de975 JN |
165 | static inline bool transcoder_is_dsi(enum transcoder transcoder) |
166 | { | |
167 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
168 | } | |
169 | ||
84139d1e | 170 | /* |
31409e97 MR |
171 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
172 | * number of planes per CRTC. Not all platforms really have this many planes, | |
173 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
174 | * between the topmost sprite plane and the cursor plane. | |
84139d1e | 175 | */ |
80824003 JB |
176 | enum plane { |
177 | PLANE_A = 0, | |
178 | PLANE_B, | |
9db4a9c7 | 179 | PLANE_C, |
31409e97 MR |
180 | PLANE_CURSOR, |
181 | I915_MAX_PLANES, | |
80824003 | 182 | }; |
9db4a9c7 | 183 | #define plane_name(p) ((p) + 'A') |
52440211 | 184 | |
d615a166 | 185 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 186 | |
2b139522 ED |
187 | enum port { |
188 | PORT_A = 0, | |
189 | PORT_B, | |
190 | PORT_C, | |
191 | PORT_D, | |
192 | PORT_E, | |
193 | I915_MAX_PORTS | |
194 | }; | |
195 | #define port_name(p) ((p) + 'A') | |
196 | ||
a09caddd | 197 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
198 | |
199 | enum dpio_channel { | |
200 | DPIO_CH0, | |
201 | DPIO_CH1 | |
202 | }; | |
203 | ||
204 | enum dpio_phy { | |
205 | DPIO_PHY0, | |
206 | DPIO_PHY1 | |
207 | }; | |
208 | ||
b97186f0 PZ |
209 | enum intel_display_power_domain { |
210 | POWER_DOMAIN_PIPE_A, | |
211 | POWER_DOMAIN_PIPE_B, | |
212 | POWER_DOMAIN_PIPE_C, | |
213 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
214 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
215 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
216 | POWER_DOMAIN_TRANSCODER_A, | |
217 | POWER_DOMAIN_TRANSCODER_B, | |
218 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 219 | POWER_DOMAIN_TRANSCODER_EDP, |
4d1de975 JN |
220 | POWER_DOMAIN_TRANSCODER_DSI_A, |
221 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
6331a704 PJ |
222 | POWER_DOMAIN_PORT_DDI_A_LANES, |
223 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
224 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
225 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
226 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
319be8ae ID |
227 | POWER_DOMAIN_PORT_DSI, |
228 | POWER_DOMAIN_PORT_CRT, | |
229 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 230 | POWER_DOMAIN_VGA, |
fbeeaa23 | 231 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 232 | POWER_DOMAIN_PLLS, |
1407121a S |
233 | POWER_DOMAIN_AUX_A, |
234 | POWER_DOMAIN_AUX_B, | |
235 | POWER_DOMAIN_AUX_C, | |
236 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 237 | POWER_DOMAIN_GMBUS, |
dfa57627 | 238 | POWER_DOMAIN_MODESET, |
baa70707 | 239 | POWER_DOMAIN_INIT, |
bddc7645 ID |
240 | |
241 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
242 | }; |
243 | ||
244 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
245 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
246 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
247 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
248 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
249 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 250 | |
1d843f9d EE |
251 | enum hpd_pin { |
252 | HPD_NONE = 0, | |
1d843f9d EE |
253 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
254 | HPD_CRT, | |
255 | HPD_SDVO_B, | |
256 | HPD_SDVO_C, | |
cc24fcdc | 257 | HPD_PORT_A, |
1d843f9d EE |
258 | HPD_PORT_B, |
259 | HPD_PORT_C, | |
260 | HPD_PORT_D, | |
26951caf | 261 | HPD_PORT_E, |
1d843f9d EE |
262 | HPD_NUM_PINS |
263 | }; | |
264 | ||
c91711f9 JN |
265 | #define for_each_hpd_pin(__pin) \ |
266 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
267 | ||
5fcece80 JN |
268 | struct i915_hotplug { |
269 | struct work_struct hotplug_work; | |
270 | ||
271 | struct { | |
272 | unsigned long last_jiffies; | |
273 | int count; | |
274 | enum { | |
275 | HPD_ENABLED = 0, | |
276 | HPD_DISABLED = 1, | |
277 | HPD_MARK_DISABLED = 2 | |
278 | } state; | |
279 | } stats[HPD_NUM_PINS]; | |
280 | u32 event_bits; | |
281 | struct delayed_work reenable_work; | |
282 | ||
283 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
284 | u32 long_port_mask; | |
285 | u32 short_port_mask; | |
286 | struct work_struct dig_port_work; | |
287 | ||
19625e85 L |
288 | struct work_struct poll_init_work; |
289 | bool poll_enabled; | |
290 | ||
5fcece80 JN |
291 | /* |
292 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
293 | * the non-DP HPD could block the workqueue on a mode config | |
294 | * mutex getting, that userspace may have taken. However | |
295 | * userspace is waiting on the DP workqueue to run which is | |
296 | * blocked behind the non-DP one. | |
297 | */ | |
298 | struct workqueue_struct *dp_wq; | |
299 | }; | |
300 | ||
2a2d5482 CW |
301 | #define I915_GEM_GPU_DOMAINS \ |
302 | (I915_GEM_DOMAIN_RENDER | \ | |
303 | I915_GEM_DOMAIN_SAMPLER | \ | |
304 | I915_GEM_DOMAIN_COMMAND | \ | |
305 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
306 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 307 | |
055e393f DL |
308 | #define for_each_pipe(__dev_priv, __p) \ |
309 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
6831f3e3 VS |
310 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ |
311 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
312 | for_each_if ((__mask) & (1 << (__p))) | |
dd740780 DL |
313 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
314 | for ((__p) = 0; \ | |
315 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
316 | (__p)++) | |
3bdcfc0c DL |
317 | #define for_each_sprite(__dev_priv, __p, __s) \ |
318 | for ((__s) = 0; \ | |
319 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
320 | (__s)++) | |
9db4a9c7 | 321 | |
c3aeadc8 JN |
322 | #define for_each_port_masked(__port, __ports_mask) \ |
323 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
324 | for_each_if ((__ports_mask) & (1 << (__port))) | |
325 | ||
d79b814d | 326 | #define for_each_crtc(dev, crtc) \ |
91c8a326 | 327 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) |
d79b814d | 328 | |
27321ae8 ML |
329 | #define for_each_intel_plane(dev, intel_plane) \ |
330 | list_for_each_entry(intel_plane, \ | |
91c8a326 | 331 | &(dev)->mode_config.plane_list, \ |
27321ae8 ML |
332 | base.head) |
333 | ||
c107acfe | 334 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ |
91c8a326 CW |
335 | list_for_each_entry(intel_plane, \ |
336 | &(dev)->mode_config.plane_list, \ | |
c107acfe MR |
337 | base.head) \ |
338 | for_each_if ((plane_mask) & \ | |
339 | (1 << drm_plane_index(&intel_plane->base))) | |
340 | ||
262cd2e1 VS |
341 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
342 | list_for_each_entry(intel_plane, \ | |
343 | &(dev)->mode_config.plane_list, \ | |
344 | base.head) \ | |
95150bdf | 345 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 346 | |
91c8a326 CW |
347 | #define for_each_intel_crtc(dev, intel_crtc) \ |
348 | list_for_each_entry(intel_crtc, \ | |
349 | &(dev)->mode_config.crtc_list, \ | |
350 | base.head) | |
d063ae48 | 351 | |
91c8a326 CW |
352 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ |
353 | list_for_each_entry(intel_crtc, \ | |
354 | &(dev)->mode_config.crtc_list, \ | |
355 | base.head) \ | |
98d39494 MR |
356 | for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) |
357 | ||
b2784e15 DL |
358 | #define for_each_intel_encoder(dev, intel_encoder) \ |
359 | list_for_each_entry(intel_encoder, \ | |
360 | &(dev)->mode_config.encoder_list, \ | |
361 | base.head) | |
362 | ||
3a3371ff ACO |
363 | #define for_each_intel_connector(dev, intel_connector) \ |
364 | list_for_each_entry(intel_connector, \ | |
91c8a326 | 365 | &(dev)->mode_config.connector_list, \ |
3a3371ff ACO |
366 | base.head) |
367 | ||
6c2b7c12 DV |
368 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
369 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 370 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 371 | |
53f5e3ca JB |
372 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
373 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 374 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 375 | |
b04c5bd6 BF |
376 | #define for_each_power_domain(domain, mask) \ |
377 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
95150bdf | 378 | for_each_if ((1 << (domain)) & (mask)) |
b04c5bd6 | 379 | |
e7b903d2 | 380 | struct drm_i915_private; |
ad46cb53 | 381 | struct i915_mm_struct; |
5cc9ed4b | 382 | struct i915_mmu_object; |
e7b903d2 | 383 | |
a6f766f3 CW |
384 | struct drm_i915_file_private { |
385 | struct drm_i915_private *dev_priv; | |
386 | struct drm_file *file; | |
387 | ||
388 | struct { | |
389 | spinlock_t lock; | |
390 | struct list_head request_list; | |
d0bc54f2 CW |
391 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
392 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
393 | * (when using lax throttling for the frontbuffer). We also use it to | |
394 | * offer free GPU waitboosts for severely congested workloads. | |
395 | */ | |
396 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
397 | } mm; |
398 | struct idr context_idr; | |
399 | ||
2e1b8730 CW |
400 | struct intel_rps_client { |
401 | struct list_head link; | |
402 | unsigned boosts; | |
403 | } rps; | |
a6f766f3 | 404 | |
c80ff16e | 405 | unsigned int bsd_engine; |
a6f766f3 CW |
406 | }; |
407 | ||
e69d0bc1 DV |
408 | /* Used by dp and fdi links */ |
409 | struct intel_link_m_n { | |
410 | uint32_t tu; | |
411 | uint32_t gmch_m; | |
412 | uint32_t gmch_n; | |
413 | uint32_t link_m; | |
414 | uint32_t link_n; | |
415 | }; | |
416 | ||
417 | void intel_link_compute_m_n(int bpp, int nlanes, | |
418 | int pixel_clock, int link_clock, | |
419 | struct intel_link_m_n *m_n); | |
420 | ||
1da177e4 LT |
421 | /* Interface history: |
422 | * | |
423 | * 1.1: Original. | |
0d6aa60b DA |
424 | * 1.2: Add Power Management |
425 | * 1.3: Add vblank support | |
de227f5f | 426 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 427 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
428 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
429 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
430 | */ |
431 | #define DRIVER_MAJOR 1 | |
2228ed67 | 432 | #define DRIVER_MINOR 6 |
1da177e4 LT |
433 | #define DRIVER_PATCHLEVEL 0 |
434 | ||
0a3e67a4 JB |
435 | struct opregion_header; |
436 | struct opregion_acpi; | |
437 | struct opregion_swsci; | |
438 | struct opregion_asle; | |
439 | ||
8ee1c3db | 440 | struct intel_opregion { |
115719fc WD |
441 | struct opregion_header *header; |
442 | struct opregion_acpi *acpi; | |
443 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
444 | u32 swsci_gbda_sub_functions; |
445 | u32 swsci_sbcb_sub_functions; | |
115719fc | 446 | struct opregion_asle *asle; |
04ebaadb | 447 | void *rvda; |
82730385 | 448 | const void *vbt; |
ada8f955 | 449 | u32 vbt_size; |
115719fc | 450 | u32 *lid_state; |
91a60f20 | 451 | struct work_struct asle_work; |
8ee1c3db | 452 | }; |
44834a67 | 453 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 454 | |
6ef3d427 CW |
455 | struct intel_overlay; |
456 | struct intel_overlay_error_state; | |
457 | ||
de151cf6 | 458 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
459 | #define I915_MAX_NUM_FENCES 32 |
460 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
461 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
462 | |
463 | struct drm_i915_fence_reg { | |
007cc8ac | 464 | struct list_head lru_list; |
caea7476 | 465 | struct drm_i915_gem_object *obj; |
1690e1eb | 466 | int pin_count; |
de151cf6 | 467 | }; |
7c1c2871 | 468 | |
9b9d172d | 469 | struct sdvo_device_mapping { |
e957d772 | 470 | u8 initialized; |
9b9d172d | 471 | u8 dvo_port; |
472 | u8 slave_addr; | |
473 | u8 dvo_wiring; | |
e957d772 | 474 | u8 i2c_pin; |
b1083333 | 475 | u8 ddc_pin; |
9b9d172d | 476 | }; |
477 | ||
c4a1d9e4 CW |
478 | struct intel_display_error_state; |
479 | ||
63eeaf38 | 480 | struct drm_i915_error_state { |
742cbee8 | 481 | struct kref ref; |
585b0288 BW |
482 | struct timeval time; |
483 | ||
cb383002 | 484 | char error_msg[128]; |
bc3d6744 | 485 | bool simulated; |
eb5be9d0 | 486 | int iommu; |
48b031e3 | 487 | u32 reset_count; |
62d5d69b | 488 | u32 suspend_count; |
cb383002 | 489 | |
585b0288 | 490 | /* Generic register state */ |
63eeaf38 JB |
491 | u32 eir; |
492 | u32 pgtbl_er; | |
be998e2e | 493 | u32 ier; |
885ea5a8 | 494 | u32 gtier[4]; |
b9a3906b | 495 | u32 ccid; |
0f3b6849 CW |
496 | u32 derrmr; |
497 | u32 forcewake; | |
585b0288 BW |
498 | u32 error; /* gen6+ */ |
499 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
500 | u32 fault_data0; /* gen8, gen9 */ |
501 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 502 | u32 done_reg; |
91ec5d11 BW |
503 | u32 gac_eco; |
504 | u32 gam_ecochk; | |
505 | u32 gab_ctl; | |
506 | u32 gfx_mode; | |
585b0288 | 507 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
508 | u64 fence[I915_MAX_NUM_FENCES]; |
509 | struct intel_overlay_error_state *overlay; | |
510 | struct intel_display_error_state *display; | |
0ca36d78 | 511 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 512 | |
6361f4ba CW |
513 | struct drm_i915_error_engine { |
514 | int engine_id; | |
362b8af7 BW |
515 | /* Software tracked state */ |
516 | bool waiting; | |
688e6c72 | 517 | int num_waiters; |
362b8af7 | 518 | int hangcheck_score; |
7e37f889 | 519 | enum intel_engine_hangcheck_action hangcheck_action; |
362b8af7 BW |
520 | int num_requests; |
521 | ||
522 | /* our own tracking of ring head and tail */ | |
523 | u32 cpu_ring_head; | |
524 | u32 cpu_ring_tail; | |
525 | ||
14fd0d6d | 526 | u32 last_seqno; |
666796da | 527 | u32 semaphore_seqno[I915_NUM_ENGINES - 1]; |
362b8af7 BW |
528 | |
529 | /* Register state */ | |
94f8cf10 | 530 | u32 start; |
362b8af7 BW |
531 | u32 tail; |
532 | u32 head; | |
533 | u32 ctl; | |
534 | u32 hws; | |
535 | u32 ipeir; | |
536 | u32 ipehr; | |
537 | u32 instdone; | |
362b8af7 BW |
538 | u32 bbstate; |
539 | u32 instpm; | |
540 | u32 instps; | |
541 | u32 seqno; | |
542 | u64 bbaddr; | |
50877445 | 543 | u64 acthd; |
362b8af7 | 544 | u32 fault_reg; |
13ffadd1 | 545 | u64 faddr; |
362b8af7 | 546 | u32 rc_psmi; /* sleep state */ |
666796da | 547 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; |
362b8af7 | 548 | |
52d39a21 CW |
549 | struct drm_i915_error_object { |
550 | int page_count; | |
e1f12325 | 551 | u64 gtt_offset; |
52d39a21 | 552 | u32 *pages[0]; |
ab0e7ff9 | 553 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 554 | |
f85db059 | 555 | struct drm_i915_error_object *wa_ctx; |
556 | ||
52d39a21 CW |
557 | struct drm_i915_error_request { |
558 | long jiffies; | |
559 | u32 seqno; | |
ee4f42b1 | 560 | u32 tail; |
52d39a21 | 561 | } *requests; |
6c7a01ec | 562 | |
688e6c72 CW |
563 | struct drm_i915_error_waiter { |
564 | char comm[TASK_COMM_LEN]; | |
565 | pid_t pid; | |
566 | u32 seqno; | |
567 | } *waiters; | |
568 | ||
6c7a01ec BW |
569 | struct { |
570 | u32 gfx_mode; | |
571 | union { | |
572 | u64 pdp[4]; | |
573 | u32 pp_dir_base; | |
574 | }; | |
575 | } vm_info; | |
ab0e7ff9 CW |
576 | |
577 | pid_t pid; | |
578 | char comm[TASK_COMM_LEN]; | |
6361f4ba | 579 | } engine[I915_NUM_ENGINES]; |
3a448734 | 580 | |
9df30794 | 581 | struct drm_i915_error_buffer { |
a779e5ab | 582 | u32 size; |
9df30794 | 583 | u32 name; |
666796da | 584 | u32 rseqno[I915_NUM_ENGINES], wseqno; |
e1f12325 | 585 | u64 gtt_offset; |
9df30794 CW |
586 | u32 read_domains; |
587 | u32 write_domain; | |
4b9de737 | 588 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
589 | s32 pinned:2; |
590 | u32 tiling:2; | |
591 | u32 dirty:1; | |
592 | u32 purgeable:1; | |
5cc9ed4b | 593 | u32 userptr:1; |
6361f4ba | 594 | s32 engine:4; |
f56383cb | 595 | u32 cache_level:3; |
95f5301d | 596 | } **active_bo, **pinned_bo; |
6c7a01ec | 597 | |
95f5301d | 598 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 599 | u32 vm_count; |
63eeaf38 JB |
600 | }; |
601 | ||
7bd688cd | 602 | struct intel_connector; |
820d2d77 | 603 | struct intel_encoder; |
5cec258b | 604 | struct intel_crtc_state; |
5724dbd1 | 605 | struct intel_initial_plane_config; |
0e8ffe1b | 606 | struct intel_crtc; |
ee9300bb DV |
607 | struct intel_limit; |
608 | struct dpll; | |
b8cecdf5 | 609 | |
e70236a8 | 610 | struct drm_i915_display_funcs { |
e70236a8 JB |
611 | int (*get_display_clock_speed)(struct drm_device *dev); |
612 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
e3bddded | 613 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
614 | int (*compute_intermediate_wm)(struct drm_device *dev, |
615 | struct intel_crtc *intel_crtc, | |
616 | struct intel_crtc_state *newstate); | |
617 | void (*initial_watermarks)(struct intel_crtc_state *cstate); | |
618 | void (*optimize_watermarks)(struct intel_crtc_state *cstate); | |
98d39494 | 619 | int (*compute_global_watermarks)(struct drm_atomic_state *state); |
46ba614c | 620 | void (*update_wm)(struct drm_crtc *crtc); |
27c329ed ML |
621 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
622 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
623 | /* Returns the active state of the crtc, and if the crtc is active, |
624 | * fills out the pipe-config with the hw state. */ | |
625 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 626 | struct intel_crtc_state *); |
5724dbd1 DL |
627 | void (*get_initial_plane_config)(struct intel_crtc *, |
628 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
629 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
630 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
631 | void (*crtc_enable)(struct drm_crtc *crtc); |
632 | void (*crtc_disable)(struct drm_crtc *crtc); | |
69bfe1a9 JN |
633 | void (*audio_codec_enable)(struct drm_connector *connector, |
634 | struct intel_encoder *encoder, | |
5e7234c9 | 635 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 636 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 637 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 638 | void (*init_clock_gating)(struct drm_device *dev); |
5a21b665 DV |
639 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
640 | struct drm_framebuffer *fb, | |
641 | struct drm_i915_gem_object *obj, | |
642 | struct drm_i915_gem_request *req, | |
643 | uint32_t flags); | |
91d14251 | 644 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
645 | /* clock updates for mode set */ |
646 | /* cursor updates */ | |
647 | /* render clock increase/decrease */ | |
648 | /* display clock increase/decrease */ | |
649 | /* pll clock increase/decrease */ | |
8563b1e8 | 650 | |
b95c5321 ML |
651 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
652 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
653 | }; |
654 | ||
48c1026a MK |
655 | enum forcewake_domain_id { |
656 | FW_DOMAIN_ID_RENDER = 0, | |
657 | FW_DOMAIN_ID_BLITTER, | |
658 | FW_DOMAIN_ID_MEDIA, | |
659 | ||
660 | FW_DOMAIN_ID_COUNT | |
661 | }; | |
662 | ||
663 | enum forcewake_domains { | |
664 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
665 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
666 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
667 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
668 | FORCEWAKE_BLITTER | | |
669 | FORCEWAKE_MEDIA) | |
670 | }; | |
671 | ||
3756685a TU |
672 | #define FW_REG_READ (1) |
673 | #define FW_REG_WRITE (2) | |
674 | ||
675 | enum forcewake_domains | |
676 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
677 | i915_reg_t reg, unsigned int op); | |
678 | ||
907b28c5 | 679 | struct intel_uncore_funcs { |
c8d9a590 | 680 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 681 | enum forcewake_domains domains); |
c8d9a590 | 682 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 683 | enum forcewake_domains domains); |
0b274481 | 684 | |
f0f59a00 VS |
685 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
686 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
687 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
688 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
0b274481 | 689 | |
f0f59a00 | 690 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 691 | uint8_t val, bool trace); |
f0f59a00 | 692 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 693 | uint16_t val, bool trace); |
f0f59a00 | 694 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 695 | uint32_t val, bool trace); |
f0f59a00 | 696 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 697 | uint64_t val, bool trace); |
990bbdad CW |
698 | }; |
699 | ||
907b28c5 CW |
700 | struct intel_uncore { |
701 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
702 | ||
703 | struct intel_uncore_funcs funcs; | |
704 | ||
705 | unsigned fifo_count; | |
48c1026a | 706 | enum forcewake_domains fw_domains; |
b2cff0db CW |
707 | |
708 | struct intel_uncore_forcewake_domain { | |
709 | struct drm_i915_private *i915; | |
48c1026a | 710 | enum forcewake_domain_id id; |
33c582c1 | 711 | enum forcewake_domains mask; |
b2cff0db | 712 | unsigned wake_count; |
a57a4a67 | 713 | struct hrtimer timer; |
f0f59a00 | 714 | i915_reg_t reg_set; |
05a2fb15 MK |
715 | u32 val_set; |
716 | u32 val_clear; | |
f0f59a00 VS |
717 | i915_reg_t reg_ack; |
718 | i915_reg_t reg_post; | |
05a2fb15 | 719 | u32 val_reset; |
b2cff0db | 720 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
75714940 MK |
721 | |
722 | int unclaimed_mmio_check; | |
b2cff0db CW |
723 | }; |
724 | ||
725 | /* Iterate over initialised fw domains */ | |
33c582c1 TU |
726 | #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \ |
727 | for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
728 | (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \ | |
729 | (domain__)++) \ | |
730 | for_each_if ((mask__) & (domain__)->mask) | |
731 | ||
732 | #define for_each_fw_domain(domain__, dev_priv__) \ | |
733 | for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__) | |
907b28c5 | 734 | |
b6e7d894 DL |
735 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
736 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
737 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
738 | ||
eb805623 | 739 | struct intel_csr { |
8144ac59 | 740 | struct work_struct work; |
eb805623 | 741 | const char *fw_path; |
a7f749f9 | 742 | uint32_t *dmc_payload; |
eb805623 | 743 | uint32_t dmc_fw_size; |
b6e7d894 | 744 | uint32_t version; |
eb805623 | 745 | uint32_t mmio_count; |
f0f59a00 | 746 | i915_reg_t mmioaddr[8]; |
eb805623 | 747 | uint32_t mmiodata[8]; |
832dba88 | 748 | uint32_t dc_state; |
a37baf3b | 749 | uint32_t allowed_dc_mask; |
eb805623 DV |
750 | }; |
751 | ||
79fc46df DL |
752 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
753 | func(is_mobile) sep \ | |
754 | func(is_i85x) sep \ | |
755 | func(is_i915g) sep \ | |
756 | func(is_i945gm) sep \ | |
757 | func(is_g33) sep \ | |
758 | func(need_gfx_hws) sep \ | |
759 | func(is_g4x) sep \ | |
760 | func(is_pineview) sep \ | |
761 | func(is_broadwater) sep \ | |
762 | func(is_crestline) sep \ | |
763 | func(is_ivybridge) sep \ | |
764 | func(is_valleyview) sep \ | |
666a4537 | 765 | func(is_cherryview) sep \ |
79fc46df | 766 | func(is_haswell) sep \ |
ab0d24ac | 767 | func(is_broadwell) sep \ |
7201c0b3 | 768 | func(is_skylake) sep \ |
7526ac19 | 769 | func(is_broxton) sep \ |
ef11bdb3 | 770 | func(is_kabylake) sep \ |
b833d685 | 771 | func(is_preliminary) sep \ |
79fc46df DL |
772 | func(has_fbc) sep \ |
773 | func(has_pipe_cxsr) sep \ | |
774 | func(has_hotplug) sep \ | |
775 | func(cursor_needs_physical) sep \ | |
776 | func(has_overlay) sep \ | |
777 | func(overlay_needs_physical) sep \ | |
778 | func(supports_tv) sep \ | |
dd93be58 | 779 | func(has_llc) sep \ |
ca377809 | 780 | func(has_snoop) sep \ |
30568c45 | 781 | func(has_ddi) sep \ |
33e141ed | 782 | func(has_fpga_dbg) sep \ |
783 | func(has_pooled_eu) | |
c96ea64e | 784 | |
a587f779 DL |
785 | #define DEFINE_FLAG(name) u8 name:1 |
786 | #define SEP_SEMICOLON ; | |
c96ea64e | 787 | |
cfdf1fa2 | 788 | struct intel_device_info { |
10fce67a | 789 | u32 display_mmio_offset; |
87f1f465 | 790 | u16 device_id; |
ac208a8b | 791 | u8 num_pipes; |
d615a166 | 792 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 793 | u8 gen; |
ae5702d2 | 794 | u16 gen_mask; |
73ae478c | 795 | u8 ring_mask; /* Rings supported by the HW */ |
c1bb1145 | 796 | u8 num_rings; |
a587f779 | 797 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
798 | /* Register offsets for the various display pipes and transcoders */ |
799 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
800 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 801 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 802 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
803 | |
804 | /* Slice/subslice/EU info */ | |
805 | u8 slice_total; | |
806 | u8 subslice_total; | |
807 | u8 subslice_per_slice; | |
808 | u8 eu_total; | |
809 | u8 eu_per_subslice; | |
33e141ed | 810 | u8 min_eu_in_pool; |
b7668791 DL |
811 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
812 | u8 subslice_7eu[3]; | |
3873218f JM |
813 | u8 has_slice_pg:1; |
814 | u8 has_subslice_pg:1; | |
815 | u8 has_eu_pg:1; | |
82cf435b LL |
816 | |
817 | struct color_luts { | |
818 | u16 degamma_lut_size; | |
819 | u16 gamma_lut_size; | |
820 | } color; | |
cfdf1fa2 KH |
821 | }; |
822 | ||
a587f779 DL |
823 | #undef DEFINE_FLAG |
824 | #undef SEP_SEMICOLON | |
825 | ||
7faf1ab2 DV |
826 | enum i915_cache_level { |
827 | I915_CACHE_NONE = 0, | |
350ec881 CW |
828 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
829 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
830 | caches, eg sampler/render caches, and the | |
831 | large Last-Level-Cache. LLC is coherent with | |
832 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 833 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
834 | }; |
835 | ||
e59ec13d MK |
836 | struct i915_ctx_hang_stats { |
837 | /* This context had batch pending when hang was declared */ | |
838 | unsigned batch_pending; | |
839 | ||
840 | /* This context had batch active when hang was declared */ | |
841 | unsigned batch_active; | |
be62acb4 MK |
842 | |
843 | /* Time when this context was last blamed for a GPU reset */ | |
844 | unsigned long guilty_ts; | |
845 | ||
676fa572 CW |
846 | /* If the contexts causes a second GPU hang within this time, |
847 | * it is permanently banned from submitting any more work. | |
848 | */ | |
849 | unsigned long ban_period_seconds; | |
850 | ||
be62acb4 MK |
851 | /* This context is banned to submit more work */ |
852 | bool banned; | |
e59ec13d | 853 | }; |
40521054 BW |
854 | |
855 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 856 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 | 857 | |
31b7a88d | 858 | /** |
e2efd130 | 859 | * struct i915_gem_context - as the name implies, represents a context. |
31b7a88d OM |
860 | * @ref: reference count. |
861 | * @user_handle: userspace tracking identity for this context. | |
862 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
863 | * @flags: context specific flags: |
864 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
865 | * @file_priv: filp associated with this context (NULL for global default |
866 | * context). | |
867 | * @hang_stats: information about the role of this context in possible GPU | |
868 | * hangs. | |
7df113e4 | 869 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
870 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
871 | * initialized (legacy ring submission mechanism only). | |
872 | * @link: link in the global list of contexts. | |
873 | * | |
874 | * Contexts are memory images used by the hardware to store copies of their | |
875 | * internal state. | |
876 | */ | |
e2efd130 | 877 | struct i915_gem_context { |
dce3271b | 878 | struct kref ref; |
9ea4feec | 879 | struct drm_i915_private *i915; |
40521054 | 880 | struct drm_i915_file_private *file_priv; |
ae6c4806 | 881 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 882 | |
8d59bc6a CW |
883 | struct i915_ctx_hang_stats hang_stats; |
884 | ||
5d1808ec | 885 | /* Unique identifier for this context, used by the hw for tracking */ |
8d59bc6a | 886 | unsigned long flags; |
bc3d6744 CW |
887 | #define CONTEXT_NO_ZEROMAP BIT(0) |
888 | #define CONTEXT_NO_ERROR_CAPTURE BIT(1) | |
5d1808ec | 889 | unsigned hw_id; |
8d59bc6a | 890 | u32 user_handle; |
5d1808ec | 891 | |
0cb26a8e CW |
892 | u32 ggtt_alignment; |
893 | ||
9021ad03 | 894 | struct intel_context { |
c9e003af | 895 | struct drm_i915_gem_object *state; |
7e37f889 | 896 | struct intel_ring *ring; |
ca82580c | 897 | struct i915_vma *lrc_vma; |
82352e90 | 898 | uint32_t *lrc_reg_state; |
8d59bc6a CW |
899 | u64 lrc_desc; |
900 | int pin_count; | |
24f1d3cc | 901 | bool initialised; |
666796da | 902 | } engine[I915_NUM_ENGINES]; |
bcd794c2 | 903 | u32 ring_size; |
c01fc532 | 904 | u32 desc_template; |
3c7ba635 | 905 | struct atomic_notifier_head status_notifier; |
80a9a8db | 906 | bool execlists_force_single_submission; |
c9e003af | 907 | |
a33afea5 | 908 | struct list_head link; |
8d59bc6a CW |
909 | |
910 | u8 remap_slice; | |
50e046b6 | 911 | bool closed:1; |
40521054 BW |
912 | }; |
913 | ||
a4001f1b PZ |
914 | enum fb_op_origin { |
915 | ORIGIN_GTT, | |
916 | ORIGIN_CPU, | |
917 | ORIGIN_CS, | |
918 | ORIGIN_FLIP, | |
74b4ea1e | 919 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
920 | }; |
921 | ||
ab34a7e8 | 922 | struct intel_fbc { |
25ad93fd PZ |
923 | /* This is always the inner lock when overlapping with struct_mutex and |
924 | * it's the outer lock when overlapping with stolen_lock. */ | |
925 | struct mutex lock; | |
5e59f717 | 926 | unsigned threshold; |
dbef0f15 PZ |
927 | unsigned int possible_framebuffer_bits; |
928 | unsigned int busy_bits; | |
010cf73d | 929 | unsigned int visible_pipes_mask; |
e35fef21 | 930 | struct intel_crtc *crtc; |
5c3fe8b0 | 931 | |
c4213885 | 932 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
933 | struct drm_mm_node *compressed_llb; |
934 | ||
da46f936 RV |
935 | bool false_color; |
936 | ||
d029bcad | 937 | bool enabled; |
0e631adc | 938 | bool active; |
9adccc60 | 939 | |
aaf78d27 PZ |
940 | struct intel_fbc_state_cache { |
941 | struct { | |
942 | unsigned int mode_flags; | |
943 | uint32_t hsw_bdw_pixel_rate; | |
944 | } crtc; | |
945 | ||
946 | struct { | |
947 | unsigned int rotation; | |
948 | int src_w; | |
949 | int src_h; | |
950 | bool visible; | |
951 | } plane; | |
952 | ||
953 | struct { | |
954 | u64 ilk_ggtt_offset; | |
aaf78d27 PZ |
955 | uint32_t pixel_format; |
956 | unsigned int stride; | |
957 | int fence_reg; | |
958 | unsigned int tiling_mode; | |
959 | } fb; | |
960 | } state_cache; | |
961 | ||
b183b3f1 PZ |
962 | struct intel_fbc_reg_params { |
963 | struct { | |
964 | enum pipe pipe; | |
965 | enum plane plane; | |
966 | unsigned int fence_y_offset; | |
967 | } crtc; | |
968 | ||
969 | struct { | |
970 | u64 ggtt_offset; | |
b183b3f1 PZ |
971 | uint32_t pixel_format; |
972 | unsigned int stride; | |
973 | int fence_reg; | |
974 | } fb; | |
975 | ||
976 | int cfb_size; | |
977 | } params; | |
978 | ||
5c3fe8b0 | 979 | struct intel_fbc_work { |
128d7356 | 980 | bool scheduled; |
ca18d51d | 981 | u32 scheduled_vblank; |
128d7356 | 982 | struct work_struct work; |
128d7356 | 983 | } work; |
5c3fe8b0 | 984 | |
bf6189c6 | 985 | const char *no_fbc_reason; |
b5e50c3f JB |
986 | }; |
987 | ||
96178eeb VK |
988 | /** |
989 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
990 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
991 | * parsing for same resolution. | |
992 | */ | |
993 | enum drrs_refresh_rate_type { | |
994 | DRRS_HIGH_RR, | |
995 | DRRS_LOW_RR, | |
996 | DRRS_MAX_RR, /* RR count */ | |
997 | }; | |
998 | ||
999 | enum drrs_support_type { | |
1000 | DRRS_NOT_SUPPORTED = 0, | |
1001 | STATIC_DRRS_SUPPORT = 1, | |
1002 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
1003 | }; |
1004 | ||
2807cf69 | 1005 | struct intel_dp; |
96178eeb VK |
1006 | struct i915_drrs { |
1007 | struct mutex mutex; | |
1008 | struct delayed_work work; | |
1009 | struct intel_dp *dp; | |
1010 | unsigned busy_frontbuffer_bits; | |
1011 | enum drrs_refresh_rate_type refresh_rate_type; | |
1012 | enum drrs_support_type type; | |
1013 | }; | |
1014 | ||
a031d709 | 1015 | struct i915_psr { |
f0355c4a | 1016 | struct mutex lock; |
a031d709 RV |
1017 | bool sink_support; |
1018 | bool source_ok; | |
2807cf69 | 1019 | struct intel_dp *enabled; |
7c8f8a70 RV |
1020 | bool active; |
1021 | struct delayed_work work; | |
9ca15301 | 1022 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
1023 | bool psr2_support; |
1024 | bool aux_frame_sync; | |
60e5ffe3 | 1025 | bool link_standby; |
3f51e471 | 1026 | }; |
5c3fe8b0 | 1027 | |
3bad0781 | 1028 | enum intel_pch { |
f0350830 | 1029 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
1030 | PCH_IBX, /* Ibexpeak PCH */ |
1031 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 1032 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 1033 | PCH_SPT, /* Sunrisepoint PCH */ |
22dea0be | 1034 | PCH_KBP, /* Kabypoint PCH */ |
40c7ead9 | 1035 | PCH_NOP, |
3bad0781 ZW |
1036 | }; |
1037 | ||
988d6ee8 PZ |
1038 | enum intel_sbi_destination { |
1039 | SBI_ICLK, | |
1040 | SBI_MPHY, | |
1041 | }; | |
1042 | ||
b690e96c | 1043 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 1044 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1045 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1046 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 1047 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 1048 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 1049 | |
8be48d92 | 1050 | struct intel_fbdev; |
1630fe75 | 1051 | struct intel_fbc_work; |
38651674 | 1052 | |
c2b9152f DV |
1053 | struct intel_gmbus { |
1054 | struct i2c_adapter adapter; | |
3e4d44e0 | 1055 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 1056 | u32 force_bit; |
c2b9152f | 1057 | u32 reg0; |
f0f59a00 | 1058 | i915_reg_t gpio_reg; |
c167a6fc | 1059 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1060 | struct drm_i915_private *dev_priv; |
1061 | }; | |
1062 | ||
f4c956ad | 1063 | struct i915_suspend_saved_registers { |
e948e994 | 1064 | u32 saveDSPARB; |
ba8bbcf6 | 1065 | u32 saveFBC_CONTROL; |
1f84e550 | 1066 | u32 saveCACHE_MODE_0; |
1f84e550 | 1067 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1068 | u32 saveSWF0[16]; |
1069 | u32 saveSWF1[16]; | |
85fa792b | 1070 | u32 saveSWF3[3]; |
4b9de737 | 1071 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1072 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1073 | u16 saveGCDGMBUS; |
f4c956ad | 1074 | }; |
c85aa885 | 1075 | |
ddeea5b0 ID |
1076 | struct vlv_s0ix_state { |
1077 | /* GAM */ | |
1078 | u32 wr_watermark; | |
1079 | u32 gfx_prio_ctrl; | |
1080 | u32 arb_mode; | |
1081 | u32 gfx_pend_tlb0; | |
1082 | u32 gfx_pend_tlb1; | |
1083 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1084 | u32 media_max_req_count; | |
1085 | u32 gfx_max_req_count; | |
1086 | u32 render_hwsp; | |
1087 | u32 ecochk; | |
1088 | u32 bsd_hwsp; | |
1089 | u32 blt_hwsp; | |
1090 | u32 tlb_rd_addr; | |
1091 | ||
1092 | /* MBC */ | |
1093 | u32 g3dctl; | |
1094 | u32 gsckgctl; | |
1095 | u32 mbctl; | |
1096 | ||
1097 | /* GCP */ | |
1098 | u32 ucgctl1; | |
1099 | u32 ucgctl3; | |
1100 | u32 rcgctl1; | |
1101 | u32 rcgctl2; | |
1102 | u32 rstctl; | |
1103 | u32 misccpctl; | |
1104 | ||
1105 | /* GPM */ | |
1106 | u32 gfxpause; | |
1107 | u32 rpdeuhwtc; | |
1108 | u32 rpdeuc; | |
1109 | u32 ecobus; | |
1110 | u32 pwrdwnupctl; | |
1111 | u32 rp_down_timeout; | |
1112 | u32 rp_deucsw; | |
1113 | u32 rcubmabdtmr; | |
1114 | u32 rcedata; | |
1115 | u32 spare2gh; | |
1116 | ||
1117 | /* Display 1 CZ domain */ | |
1118 | u32 gt_imr; | |
1119 | u32 gt_ier; | |
1120 | u32 pm_imr; | |
1121 | u32 pm_ier; | |
1122 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1123 | ||
1124 | /* GT SA CZ domain */ | |
1125 | u32 tilectl; | |
1126 | u32 gt_fifoctl; | |
1127 | u32 gtlc_wake_ctrl; | |
1128 | u32 gtlc_survive; | |
1129 | u32 pmwgicz; | |
1130 | ||
1131 | /* Display 2 CZ domain */ | |
1132 | u32 gu_ctl0; | |
1133 | u32 gu_ctl1; | |
9c25210f | 1134 | u32 pcbr; |
ddeea5b0 ID |
1135 | u32 clock_gate_dis2; |
1136 | }; | |
1137 | ||
bf225f20 CW |
1138 | struct intel_rps_ei { |
1139 | u32 cz_clock; | |
1140 | u32 render_c0; | |
1141 | u32 media_c0; | |
31685c25 D |
1142 | }; |
1143 | ||
c85aa885 | 1144 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1145 | /* |
1146 | * work, interrupts_enabled and pm_iir are protected by | |
1147 | * dev_priv->irq_lock | |
1148 | */ | |
c85aa885 | 1149 | struct work_struct work; |
d4d70aa5 | 1150 | bool interrupts_enabled; |
c85aa885 | 1151 | u32 pm_iir; |
59cdb63d | 1152 | |
1800ad25 SAK |
1153 | u32 pm_intr_keep; |
1154 | ||
b39fb297 BW |
1155 | /* Frequencies are stored in potentially platform dependent multiples. |
1156 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1157 | * Soft limits are those which are used for the dynamic reclocking done | |
1158 | * by the driver (raise frequencies under heavy loads, and lower for | |
1159 | * lighter loads). Hard limits are those imposed by the hardware. | |
1160 | * | |
1161 | * A distinction is made for overclocking, which is never enabled by | |
1162 | * default, and is considered to be above the hard limit if it's | |
1163 | * possible at all. | |
1164 | */ | |
1165 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1166 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1167 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1168 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1169 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
29ecd78d | 1170 | u8 boost_freq; /* Frequency to request when wait boosting */ |
aed242ff | 1171 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1172 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1173 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1174 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 1175 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 1176 | |
8fb55197 CW |
1177 | u8 up_threshold; /* Current %busy required to uplock */ |
1178 | u8 down_threshold; /* Current %busy required to downclock */ | |
1179 | ||
dd75fdc8 CW |
1180 | int last_adj; |
1181 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1182 | ||
8d3afd7d CW |
1183 | spinlock_t client_lock; |
1184 | struct list_head clients; | |
1185 | bool client_boost; | |
1186 | ||
c0951f0c | 1187 | bool enabled; |
54b4f68f | 1188 | struct delayed_work autoenable_work; |
1854d5ca | 1189 | unsigned boosts; |
4fc688ce | 1190 | |
bf225f20 CW |
1191 | /* manual wa residency calculations */ |
1192 | struct intel_rps_ei up_ei, down_ei; | |
1193 | ||
4fc688ce JB |
1194 | /* |
1195 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1196 | * Must be taken after struct_mutex if nested. Note that |
1197 | * this lock may be held for long periods of time when | |
1198 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1199 | */ |
1200 | struct mutex hw_lock; | |
c85aa885 DV |
1201 | }; |
1202 | ||
1a240d4d DV |
1203 | /* defined intel_pm.c */ |
1204 | extern spinlock_t mchdev_lock; | |
1205 | ||
c85aa885 DV |
1206 | struct intel_ilk_power_mgmt { |
1207 | u8 cur_delay; | |
1208 | u8 min_delay; | |
1209 | u8 max_delay; | |
1210 | u8 fmax; | |
1211 | u8 fstart; | |
1212 | ||
1213 | u64 last_count1; | |
1214 | unsigned long last_time1; | |
1215 | unsigned long chipset_power; | |
1216 | u64 last_count2; | |
5ed0bdf2 | 1217 | u64 last_time2; |
c85aa885 DV |
1218 | unsigned long gfx_power; |
1219 | u8 corr; | |
1220 | ||
1221 | int c_m; | |
1222 | int r_t; | |
1223 | }; | |
1224 | ||
c6cb582e ID |
1225 | struct drm_i915_private; |
1226 | struct i915_power_well; | |
1227 | ||
1228 | struct i915_power_well_ops { | |
1229 | /* | |
1230 | * Synchronize the well's hw state to match the current sw state, for | |
1231 | * example enable/disable it based on the current refcount. Called | |
1232 | * during driver init and resume time, possibly after first calling | |
1233 | * the enable/disable handlers. | |
1234 | */ | |
1235 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1236 | struct i915_power_well *power_well); | |
1237 | /* | |
1238 | * Enable the well and resources that depend on it (for example | |
1239 | * interrupts located on the well). Called after the 0->1 refcount | |
1240 | * transition. | |
1241 | */ | |
1242 | void (*enable)(struct drm_i915_private *dev_priv, | |
1243 | struct i915_power_well *power_well); | |
1244 | /* | |
1245 | * Disable the well and resources that depend on it. Called after | |
1246 | * the 1->0 refcount transition. | |
1247 | */ | |
1248 | void (*disable)(struct drm_i915_private *dev_priv, | |
1249 | struct i915_power_well *power_well); | |
1250 | /* Returns the hw enabled state. */ | |
1251 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1252 | struct i915_power_well *power_well); | |
1253 | }; | |
1254 | ||
a38911a3 WX |
1255 | /* Power well structure for haswell */ |
1256 | struct i915_power_well { | |
c1ca727f | 1257 | const char *name; |
6f3ef5dd | 1258 | bool always_on; |
a38911a3 WX |
1259 | /* power well enable/disable usage count */ |
1260 | int count; | |
bfafe93a ID |
1261 | /* cached hw enabled state */ |
1262 | bool hw_enabled; | |
c1ca727f | 1263 | unsigned long domains; |
77961eb9 | 1264 | unsigned long data; |
c6cb582e | 1265 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1266 | }; |
1267 | ||
83c00f55 | 1268 | struct i915_power_domains { |
baa70707 ID |
1269 | /* |
1270 | * Power wells needed for initialization at driver init and suspend | |
1271 | * time are on. They are kept on until after the first modeset. | |
1272 | */ | |
1273 | bool init_power_on; | |
0d116a29 | 1274 | bool initializing; |
c1ca727f | 1275 | int power_well_count; |
baa70707 | 1276 | |
83c00f55 | 1277 | struct mutex lock; |
1da51581 | 1278 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1279 | struct i915_power_well *power_wells; |
83c00f55 ID |
1280 | }; |
1281 | ||
35a85ac6 | 1282 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1283 | struct intel_l3_parity { |
35a85ac6 | 1284 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1285 | struct work_struct error_work; |
35a85ac6 | 1286 | int which_slice; |
a4da4fa4 DV |
1287 | }; |
1288 | ||
4b5aed62 | 1289 | struct i915_gem_mm { |
4b5aed62 DV |
1290 | /** Memory allocator for GTT stolen memory */ |
1291 | struct drm_mm stolen; | |
92e97d2f PZ |
1292 | /** Protects the usage of the GTT stolen memory allocator. This is |
1293 | * always the inner lock when overlapping with struct_mutex. */ | |
1294 | struct mutex stolen_lock; | |
1295 | ||
4b5aed62 DV |
1296 | /** List of all objects in gtt_space. Used to restore gtt |
1297 | * mappings on resume */ | |
1298 | struct list_head bound_list; | |
1299 | /** | |
1300 | * List of objects which are not bound to the GTT (thus | |
1301 | * are idle and not used by the GPU) but still have | |
1302 | * (presumably uncached) pages still attached. | |
1303 | */ | |
1304 | struct list_head unbound_list; | |
1305 | ||
1306 | /** Usable portion of the GTT for GEM */ | |
1307 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1308 | ||
4b5aed62 DV |
1309 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1310 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1311 | ||
2cfcd32a | 1312 | struct notifier_block oom_notifier; |
e87666b5 | 1313 | struct notifier_block vmap_notifier; |
ceabbba5 | 1314 | struct shrinker shrinker; |
4b5aed62 | 1315 | |
4b5aed62 DV |
1316 | /** LRU list of objects with fence regs on them. */ |
1317 | struct list_head fence_list; | |
1318 | ||
4b5aed62 DV |
1319 | /** |
1320 | * Are we in a non-interruptible section of code like | |
1321 | * modesetting? | |
1322 | */ | |
1323 | bool interruptible; | |
1324 | ||
bdf1e7e3 | 1325 | /* the indicator for dispatch video commands on two BSD rings */ |
c80ff16e | 1326 | unsigned int bsd_engine_dispatch_index; |
bdf1e7e3 | 1327 | |
4b5aed62 DV |
1328 | /** Bit 6 swizzling required for X tiling */ |
1329 | uint32_t bit_6_swizzle_x; | |
1330 | /** Bit 6 swizzling required for Y tiling */ | |
1331 | uint32_t bit_6_swizzle_y; | |
1332 | ||
4b5aed62 | 1333 | /* accounting, useful for userland debugging */ |
c20e8355 | 1334 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1335 | size_t object_memory; |
1336 | u32 object_count; | |
1337 | }; | |
1338 | ||
edc3d884 | 1339 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1340 | struct drm_i915_private *i915; |
edc3d884 MK |
1341 | unsigned bytes; |
1342 | unsigned size; | |
1343 | int err; | |
1344 | u8 *buf; | |
1345 | loff_t start; | |
1346 | loff_t pos; | |
1347 | }; | |
1348 | ||
fc16b48b MK |
1349 | struct i915_error_state_file_priv { |
1350 | struct drm_device *dev; | |
1351 | struct drm_i915_error_state *error; | |
1352 | }; | |
1353 | ||
99584db3 DV |
1354 | struct i915_gpu_error { |
1355 | /* For hangcheck timer */ | |
1356 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1357 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1358 | /* Hang gpu twice in this window and your context gets banned */ |
1359 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1360 | ||
737b1506 | 1361 | struct delayed_work hangcheck_work; |
99584db3 DV |
1362 | |
1363 | /* For reset and error_state handling. */ | |
1364 | spinlock_t lock; | |
1365 | /* Protected by the above dev->gpu_error.lock. */ | |
1366 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1367 | |
1368 | unsigned long missed_irq_rings; | |
1369 | ||
1f83fee0 | 1370 | /** |
2ac0f450 | 1371 | * State variable controlling the reset flow and count |
1f83fee0 | 1372 | * |
2ac0f450 MK |
1373 | * This is a counter which gets incremented when reset is triggered, |
1374 | * and again when reset has been handled. So odd values (lowest bit set) | |
1375 | * means that reset is in progress and even values that | |
1376 | * (reset_counter >> 1):th reset was successfully completed. | |
1377 | * | |
1378 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1379 | * set meaning that hardware is terminally sour and there is no | |
1380 | * recovery. All waiters on the reset_queue will be woken when | |
1381 | * that happens. | |
1382 | * | |
1383 | * This counter is used by the wait_seqno code to notice that reset | |
1384 | * event happened and it needs to restart the entire ioctl (since most | |
1385 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1386 | * |
1387 | * This is important for lock-free wait paths, where no contended lock | |
1388 | * naturally enforces the correct ordering between the bail-out of the | |
1389 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1390 | */ |
1391 | atomic_t reset_counter; | |
1392 | ||
1f83fee0 | 1393 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1394 | #define I915_WEDGED (1 << 31) |
1f83fee0 | 1395 | |
1f15b76f CW |
1396 | /** |
1397 | * Waitqueue to signal when a hang is detected. Used to for waiters | |
1398 | * to release the struct_mutex for the reset to procede. | |
1399 | */ | |
1400 | wait_queue_head_t wait_queue; | |
1401 | ||
1f83fee0 DV |
1402 | /** |
1403 | * Waitqueue to signal when the reset has completed. Used by clients | |
1404 | * that wait for dev_priv->mm.wedged to settle. | |
1405 | */ | |
1406 | wait_queue_head_t reset_queue; | |
33196ded | 1407 | |
094f9a54 | 1408 | /* For missed irq/seqno simulation. */ |
688e6c72 | 1409 | unsigned long test_irq_rings; |
99584db3 DV |
1410 | }; |
1411 | ||
b8efb17b ZR |
1412 | enum modeset_restore { |
1413 | MODESET_ON_LID_OPEN, | |
1414 | MODESET_DONE, | |
1415 | MODESET_SUSPENDED, | |
1416 | }; | |
1417 | ||
500ea70d RV |
1418 | #define DP_AUX_A 0x40 |
1419 | #define DP_AUX_B 0x10 | |
1420 | #define DP_AUX_C 0x20 | |
1421 | #define DP_AUX_D 0x30 | |
1422 | ||
11c1b657 XZ |
1423 | #define DDC_PIN_B 0x05 |
1424 | #define DDC_PIN_C 0x04 | |
1425 | #define DDC_PIN_D 0x06 | |
1426 | ||
6acab15a | 1427 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1428 | /* |
1429 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1430 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1431 | * populate this field. | |
1432 | */ | |
1433 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1434 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1435 | |
1436 | uint8_t supports_dvi:1; | |
1437 | uint8_t supports_hdmi:1; | |
1438 | uint8_t supports_dp:1; | |
500ea70d RV |
1439 | |
1440 | uint8_t alternate_aux_channel; | |
11c1b657 | 1441 | uint8_t alternate_ddc_pin; |
75067dde AK |
1442 | |
1443 | uint8_t dp_boost_level; | |
1444 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1445 | }; |
1446 | ||
bfd7ebda RV |
1447 | enum psr_lines_to_wait { |
1448 | PSR_0_LINES_TO_WAIT = 0, | |
1449 | PSR_1_LINE_TO_WAIT, | |
1450 | PSR_4_LINES_TO_WAIT, | |
1451 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1452 | }; |
1453 | ||
41aa3448 RV |
1454 | struct intel_vbt_data { |
1455 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1456 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1457 | ||
1458 | /* Feature bits */ | |
1459 | unsigned int int_tv_support:1; | |
1460 | unsigned int lvds_dither:1; | |
1461 | unsigned int lvds_vbt:1; | |
1462 | unsigned int int_crt_support:1; | |
1463 | unsigned int lvds_use_ssc:1; | |
1464 | unsigned int display_clock_mode:1; | |
1465 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 1466 | unsigned int panel_type:4; |
41aa3448 RV |
1467 | int lvds_ssc_freq; |
1468 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1469 | ||
83a7280e PB |
1470 | enum drrs_support_type drrs_type; |
1471 | ||
6aa23e65 JN |
1472 | struct { |
1473 | int rate; | |
1474 | int lanes; | |
1475 | int preemphasis; | |
1476 | int vswing; | |
06411f08 | 1477 | bool low_vswing; |
6aa23e65 JN |
1478 | bool initialized; |
1479 | bool support; | |
1480 | int bpp; | |
1481 | struct edp_power_seq pps; | |
1482 | } edp; | |
41aa3448 | 1483 | |
bfd7ebda RV |
1484 | struct { |
1485 | bool full_link; | |
1486 | bool require_aux_wakeup; | |
1487 | int idle_frames; | |
1488 | enum psr_lines_to_wait lines_to_wait; | |
1489 | int tp1_wakeup_time; | |
1490 | int tp2_tp3_wakeup_time; | |
1491 | } psr; | |
1492 | ||
f00076d2 JN |
1493 | struct { |
1494 | u16 pwm_freq_hz; | |
39fbc9c8 | 1495 | bool present; |
f00076d2 | 1496 | bool active_low_pwm; |
1de6068e | 1497 | u8 min_brightness; /* min_brightness/255 of max */ |
9a41e17d | 1498 | enum intel_backlight_type type; |
f00076d2 JN |
1499 | } backlight; |
1500 | ||
d17c5443 SK |
1501 | /* MIPI DSI */ |
1502 | struct { | |
1503 | u16 panel_id; | |
d3b542fc SK |
1504 | struct mipi_config *config; |
1505 | struct mipi_pps_data *pps; | |
1506 | u8 seq_version; | |
1507 | u32 size; | |
1508 | u8 *data; | |
8d3ed2f3 | 1509 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1510 | } dsi; |
1511 | ||
41aa3448 RV |
1512 | int crt_ddc_pin; |
1513 | ||
1514 | int child_dev_num; | |
768f69c9 | 1515 | union child_device_config *child_dev; |
6acab15a PZ |
1516 | |
1517 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1518 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1519 | }; |
1520 | ||
77c122bc VS |
1521 | enum intel_ddb_partitioning { |
1522 | INTEL_DDB_PART_1_2, | |
1523 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1524 | }; | |
1525 | ||
1fd527cc VS |
1526 | struct intel_wm_level { |
1527 | bool enable; | |
1528 | uint32_t pri_val; | |
1529 | uint32_t spr_val; | |
1530 | uint32_t cur_val; | |
1531 | uint32_t fbc_val; | |
1532 | }; | |
1533 | ||
820c1980 | 1534 | struct ilk_wm_values { |
609cedef VS |
1535 | uint32_t wm_pipe[3]; |
1536 | uint32_t wm_lp[3]; | |
1537 | uint32_t wm_lp_spr[3]; | |
1538 | uint32_t wm_linetime[3]; | |
1539 | bool enable_fbc_wm; | |
1540 | enum intel_ddb_partitioning partitioning; | |
1541 | }; | |
1542 | ||
262cd2e1 VS |
1543 | struct vlv_pipe_wm { |
1544 | uint16_t primary; | |
1545 | uint16_t sprite[2]; | |
1546 | uint8_t cursor; | |
1547 | }; | |
ae80152d | 1548 | |
262cd2e1 VS |
1549 | struct vlv_sr_wm { |
1550 | uint16_t plane; | |
1551 | uint8_t cursor; | |
1552 | }; | |
ae80152d | 1553 | |
262cd2e1 VS |
1554 | struct vlv_wm_values { |
1555 | struct vlv_pipe_wm pipe[3]; | |
1556 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1557 | struct { |
1558 | uint8_t cursor; | |
1559 | uint8_t sprite[2]; | |
1560 | uint8_t primary; | |
1561 | } ddl[3]; | |
6eb1a681 VS |
1562 | uint8_t level; |
1563 | bool cxsr; | |
0018fda1 VS |
1564 | }; |
1565 | ||
c193924e | 1566 | struct skl_ddb_entry { |
16160e3d | 1567 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1568 | }; |
1569 | ||
1570 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1571 | { | |
16160e3d | 1572 | return entry->end - entry->start; |
c193924e DL |
1573 | } |
1574 | ||
08db6652 DL |
1575 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1576 | const struct skl_ddb_entry *e2) | |
1577 | { | |
1578 | if (e1->start == e2->start && e1->end == e2->end) | |
1579 | return true; | |
1580 | ||
1581 | return false; | |
1582 | } | |
1583 | ||
c193924e | 1584 | struct skl_ddb_allocation { |
34bb56af | 1585 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 | 1586 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1587 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1588 | }; |
1589 | ||
2ac96d2a | 1590 | struct skl_wm_values { |
2b4b9f35 | 1591 | unsigned dirty_pipes; |
c193924e | 1592 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1593 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1594 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
2ac96d2a | 1595 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
2ac96d2a PB |
1596 | }; |
1597 | ||
1598 | struct skl_wm_level { | |
1599 | bool plane_en[I915_MAX_PLANES]; | |
1600 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1601 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1602 | }; |
1603 | ||
c67a470b | 1604 | /* |
765dab67 PZ |
1605 | * This struct helps tracking the state needed for runtime PM, which puts the |
1606 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1607 | * graphics device works, even register access, so we don't get interrupts nor | |
1608 | * anything else. | |
c67a470b | 1609 | * |
765dab67 PZ |
1610 | * Every piece of our code that needs to actually touch the hardware needs to |
1611 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1612 | * appropriate power domain. | |
a8a8bd54 | 1613 | * |
765dab67 PZ |
1614 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1615 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1616 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1617 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1618 | * |
1619 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1620 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1621 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1622 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1623 | * case it happens. |
c67a470b | 1624 | * |
765dab67 | 1625 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1626 | */ |
5d584b2e | 1627 | struct i915_runtime_pm { |
1f814dac | 1628 | atomic_t wakeref_count; |
2b19efeb | 1629 | atomic_t atomic_seq; |
5d584b2e | 1630 | bool suspended; |
2aeb7d3a | 1631 | bool irqs_enabled; |
c67a470b PZ |
1632 | }; |
1633 | ||
926321d5 DV |
1634 | enum intel_pipe_crc_source { |
1635 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1636 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1637 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1638 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1639 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1640 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1641 | INTEL_PIPE_CRC_SOURCE_TV, | |
1642 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1643 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1644 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1645 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1646 | INTEL_PIPE_CRC_SOURCE_MAX, |
1647 | }; | |
1648 | ||
8bf1e9f1 | 1649 | struct intel_pipe_crc_entry { |
ac2300d4 | 1650 | uint32_t frame; |
8bf1e9f1 SH |
1651 | uint32_t crc[5]; |
1652 | }; | |
1653 | ||
b2c88f5b | 1654 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1655 | struct intel_pipe_crc { |
d538bbdf DL |
1656 | spinlock_t lock; |
1657 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1658 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1659 | enum intel_pipe_crc_source source; |
d538bbdf | 1660 | int head, tail; |
07144428 | 1661 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1662 | }; |
1663 | ||
f99d7069 | 1664 | struct i915_frontbuffer_tracking { |
b5add959 | 1665 | spinlock_t lock; |
f99d7069 DV |
1666 | |
1667 | /* | |
1668 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1669 | * scheduled flips. | |
1670 | */ | |
1671 | unsigned busy_bits; | |
1672 | unsigned flip_bits; | |
1673 | }; | |
1674 | ||
7225342a | 1675 | struct i915_wa_reg { |
f0f59a00 | 1676 | i915_reg_t addr; |
7225342a MK |
1677 | u32 value; |
1678 | /* bitmask representing WA bits */ | |
1679 | u32 mask; | |
1680 | }; | |
1681 | ||
33136b06 AS |
1682 | /* |
1683 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1684 | * allowing it for RCS as we don't foresee any requirement of having | |
1685 | * a whitelist for other engines. When it is really required for | |
1686 | * other engines then the limit need to be increased. | |
1687 | */ | |
1688 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
7225342a MK |
1689 | |
1690 | struct i915_workarounds { | |
1691 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1692 | u32 count; | |
666796da | 1693 | u32 hw_whitelist_count[I915_NUM_ENGINES]; |
7225342a MK |
1694 | }; |
1695 | ||
cf9d2890 YZ |
1696 | struct i915_virtual_gpu { |
1697 | bool active; | |
1698 | }; | |
1699 | ||
aa363136 MR |
1700 | /* used in computing the new watermarks state */ |
1701 | struct intel_wm_config { | |
1702 | unsigned int num_pipes_active; | |
1703 | bool sprites_enabled; | |
1704 | bool sprites_scaled; | |
1705 | }; | |
1706 | ||
77fec556 | 1707 | struct drm_i915_private { |
8f460e2c CW |
1708 | struct drm_device drm; |
1709 | ||
efab6d8d | 1710 | struct kmem_cache *objects; |
e20d2ab7 | 1711 | struct kmem_cache *vmas; |
efab6d8d | 1712 | struct kmem_cache *requests; |
f4c956ad | 1713 | |
5c969aa7 | 1714 | const struct intel_device_info info; |
f4c956ad DV |
1715 | |
1716 | int relative_constants_mode; | |
1717 | ||
1718 | void __iomem *regs; | |
1719 | ||
907b28c5 | 1720 | struct intel_uncore uncore; |
f4c956ad | 1721 | |
cf9d2890 YZ |
1722 | struct i915_virtual_gpu vgpu; |
1723 | ||
0ad35fed ZW |
1724 | struct intel_gvt gvt; |
1725 | ||
33a732f4 AD |
1726 | struct intel_guc guc; |
1727 | ||
eb805623 DV |
1728 | struct intel_csr csr; |
1729 | ||
5ea6e5e3 | 1730 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1731 | |
f4c956ad DV |
1732 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1733 | * controller on different i2c buses. */ | |
1734 | struct mutex gmbus_mutex; | |
1735 | ||
1736 | /** | |
1737 | * Base address of the gmbus and gpio block. | |
1738 | */ | |
1739 | uint32_t gpio_mmio_base; | |
1740 | ||
b6fdd0f2 SS |
1741 | /* MMIO base address for MIPI regs */ |
1742 | uint32_t mipi_mmio_base; | |
1743 | ||
443a389f VS |
1744 | uint32_t psr_mmio_base; |
1745 | ||
44cb734c ID |
1746 | uint32_t pps_mmio_base; |
1747 | ||
28c70f16 DV |
1748 | wait_queue_head_t gmbus_wait_queue; |
1749 | ||
f4c956ad | 1750 | struct pci_dev *bridge_dev; |
0ca5fa3a | 1751 | struct i915_gem_context *kernel_context; |
666796da | 1752 | struct intel_engine_cs engine[I915_NUM_ENGINES]; |
3e78998a | 1753 | struct drm_i915_gem_object *semaphore_obj; |
ddf07be7 | 1754 | u32 next_seqno; |
f4c956ad | 1755 | |
ba8286fa | 1756 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1757 | struct resource mch_res; |
1758 | ||
f4c956ad DV |
1759 | /* protects the irq masks */ |
1760 | spinlock_t irq_lock; | |
1761 | ||
84c33a64 SG |
1762 | /* protects the mmio flip data */ |
1763 | spinlock_t mmio_flip_lock; | |
1764 | ||
f8b79e58 ID |
1765 | bool display_irqs_enabled; |
1766 | ||
9ee32fea DV |
1767 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1768 | struct pm_qos_request pm_qos; | |
1769 | ||
a580516d VS |
1770 | /* Sideband mailbox protection */ |
1771 | struct mutex sb_lock; | |
f4c956ad DV |
1772 | |
1773 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1774 | union { |
1775 | u32 irq_mask; | |
1776 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1777 | }; | |
f4c956ad | 1778 | u32 gt_irq_mask; |
605cd25b | 1779 | u32 pm_irq_mask; |
a6706b45 | 1780 | u32 pm_rps_events; |
91d181dd | 1781 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1782 | |
5fcece80 | 1783 | struct i915_hotplug hotplug; |
ab34a7e8 | 1784 | struct intel_fbc fbc; |
439d7ac0 | 1785 | struct i915_drrs drrs; |
f4c956ad | 1786 | struct intel_opregion opregion; |
41aa3448 | 1787 | struct intel_vbt_data vbt; |
f4c956ad | 1788 | |
d9ceb816 JB |
1789 | bool preserve_bios_swizzle; |
1790 | ||
f4c956ad DV |
1791 | /* overlay */ |
1792 | struct intel_overlay *overlay; | |
f4c956ad | 1793 | |
58c68779 | 1794 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1795 | struct mutex backlight_lock; |
31ad8ec6 | 1796 | |
f4c956ad | 1797 | /* LVDS info */ |
f4c956ad DV |
1798 | bool no_aux_handshake; |
1799 | ||
e39b999a VS |
1800 | /* protects panel power sequencer state */ |
1801 | struct mutex pps_mutex; | |
1802 | ||
f4c956ad | 1803 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1804 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1805 | ||
1806 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
b2045352 | 1807 | unsigned int skl_preferred_vco_freq; |
1a617b77 | 1808 | unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; |
adafdc6f | 1809 | unsigned int max_dotclk_freq; |
e7dc33f3 | 1810 | unsigned int rawclk_freq; |
6bcda4f0 | 1811 | unsigned int hpll_freq; |
bfa7df01 | 1812 | unsigned int czclk_freq; |
f4c956ad | 1813 | |
63911d72 | 1814 | struct { |
709e05c3 | 1815 | unsigned int vco, ref; |
63911d72 VS |
1816 | } cdclk_pll; |
1817 | ||
645416f5 DV |
1818 | /** |
1819 | * wq - Driver workqueue for GEM. | |
1820 | * | |
1821 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1822 | * locks, for otherwise the flushing done in the pageflip code will | |
1823 | * result in deadlocks. | |
1824 | */ | |
f4c956ad DV |
1825 | struct workqueue_struct *wq; |
1826 | ||
1827 | /* Display functions */ | |
1828 | struct drm_i915_display_funcs display; | |
1829 | ||
1830 | /* PCH chipset type */ | |
1831 | enum intel_pch pch_type; | |
17a303ec | 1832 | unsigned short pch_id; |
f4c956ad DV |
1833 | |
1834 | unsigned long quirks; | |
1835 | ||
b8efb17b ZR |
1836 | enum modeset_restore modeset_restore; |
1837 | struct mutex modeset_restore_lock; | |
e2c8b870 | 1838 | struct drm_atomic_state *modeset_restore_state; |
73974893 | 1839 | struct drm_modeset_acquire_ctx reset_ctx; |
673a394b | 1840 | |
a7bbbd63 | 1841 | struct list_head vm_list; /* Global list of all address spaces */ |
62106b4f | 1842 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 1843 | |
4b5aed62 | 1844 | struct i915_gem_mm mm; |
ad46cb53 CW |
1845 | DECLARE_HASHTABLE(mm_structs, 7); |
1846 | struct mutex mm_lock; | |
8781342d | 1847 | |
5d1808ec CW |
1848 | /* The hw wants to have a stable context identifier for the lifetime |
1849 | * of the context (for OA, PASID, faults, etc). This is limited | |
1850 | * in execlists to 21 bits. | |
1851 | */ | |
1852 | struct ida context_hw_ida; | |
1853 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
1854 | ||
8781342d DV |
1855 | /* Kernel Modesetting */ |
1856 | ||
76c4ac04 DL |
1857 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1858 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1859 | wait_queue_head_t pending_flip_queue; |
1860 | ||
c4597872 DV |
1861 | #ifdef CONFIG_DEBUG_FS |
1862 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1863 | #endif | |
1864 | ||
565602d7 | 1865 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
1866 | int num_shared_dpll; |
1867 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 1868 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 1869 | |
fbf6d879 ML |
1870 | /* |
1871 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
1872 | * Must be global rather than per dpll, because on some platforms | |
1873 | * plls share registers. | |
1874 | */ | |
1875 | struct mutex dpll_lock; | |
1876 | ||
565602d7 ML |
1877 | unsigned int active_crtcs; |
1878 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
1879 | ||
e4607fcf | 1880 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1881 | |
7225342a | 1882 | struct i915_workarounds workarounds; |
888b5995 | 1883 | |
f99d7069 DV |
1884 | struct i915_frontbuffer_tracking fb_tracking; |
1885 | ||
652c393a | 1886 | u16 orig_clock; |
f97108d1 | 1887 | |
c4804411 | 1888 | bool mchbar_need_disable; |
f97108d1 | 1889 | |
a4da4fa4 DV |
1890 | struct intel_l3_parity l3_parity; |
1891 | ||
59124506 | 1892 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 1893 | u32 edram_cap; |
59124506 | 1894 | |
c6a828d3 | 1895 | /* gen6+ rps state */ |
c85aa885 | 1896 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1897 | |
20e4d407 DV |
1898 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1899 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1900 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1901 | |
83c00f55 | 1902 | struct i915_power_domains power_domains; |
a38911a3 | 1903 | |
a031d709 | 1904 | struct i915_psr psr; |
3f51e471 | 1905 | |
99584db3 | 1906 | struct i915_gpu_error gpu_error; |
ae681d96 | 1907 | |
c9cddffc JB |
1908 | struct drm_i915_gem_object *vlv_pctx; |
1909 | ||
0695726e | 1910 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
1911 | /* list of fbdev register on this device */ |
1912 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1913 | struct work_struct fbdev_suspend_work; |
4520f53a | 1914 | #endif |
e953fd7b CW |
1915 | |
1916 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1917 | struct drm_property *force_audio_property; |
e3689190 | 1918 | |
58fddc28 | 1919 | /* hda/i915 audio component */ |
51e1d83c | 1920 | struct i915_audio_component *audio_component; |
58fddc28 | 1921 | bool audio_component_registered; |
4a21ef7d LY |
1922 | /** |
1923 | * av_mutex - mutex for audio/video sync | |
1924 | * | |
1925 | */ | |
1926 | struct mutex av_mutex; | |
58fddc28 | 1927 | |
254f965c | 1928 | uint32_t hw_context_size; |
a33afea5 | 1929 | struct list_head context_list; |
f4c956ad | 1930 | |
3e68320e | 1931 | u32 fdi_rx_config; |
68d18ad7 | 1932 | |
c231775c | 1933 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 1934 | u32 chv_phy_control; |
c231775c VS |
1935 | /* |
1936 | * Shadows for CHV DPLL_MD regs to keep the state | |
1937 | * checker somewhat working in the presence hardware | |
1938 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
1939 | */ | |
1940 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 1941 | u32 bxt_phy_grc; |
70722468 | 1942 | |
842f1c8b | 1943 | u32 suspend_count; |
bc87229f | 1944 | bool suspended_to_idle; |
f4c956ad | 1945 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1946 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1947 | |
53615a5e VS |
1948 | struct { |
1949 | /* | |
1950 | * Raw watermark latency values: | |
1951 | * in 0.1us units for WM0, | |
1952 | * in 0.5us units for WM1+. | |
1953 | */ | |
1954 | /* primary */ | |
1955 | uint16_t pri_latency[5]; | |
1956 | /* sprite */ | |
1957 | uint16_t spr_latency[5]; | |
1958 | /* cursor */ | |
1959 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1960 | /* |
1961 | * Raw watermark memory latency values | |
1962 | * for SKL for all 8 levels | |
1963 | * in 1us units. | |
1964 | */ | |
1965 | uint16_t skl_latency[8]; | |
609cedef | 1966 | |
2d41c0b5 PB |
1967 | /* |
1968 | * The skl_wm_values structure is a bit too big for stack | |
1969 | * allocation, so we keep the staging struct where we store | |
1970 | * intermediate results here instead. | |
1971 | */ | |
1972 | struct skl_wm_values skl_results; | |
1973 | ||
609cedef | 1974 | /* current hardware state */ |
2d41c0b5 PB |
1975 | union { |
1976 | struct ilk_wm_values hw; | |
1977 | struct skl_wm_values skl_hw; | |
0018fda1 | 1978 | struct vlv_wm_values vlv; |
2d41c0b5 | 1979 | }; |
58590c14 VS |
1980 | |
1981 | uint8_t max_level; | |
ed4a6a7c MR |
1982 | |
1983 | /* | |
1984 | * Should be held around atomic WM register writing; also | |
1985 | * protects * intel_crtc->wm.active and | |
1986 | * cstate->wm.need_postvbl_update. | |
1987 | */ | |
1988 | struct mutex wm_mutex; | |
279e99d7 MR |
1989 | |
1990 | /* | |
1991 | * Set during HW readout of watermarks/DDB. Some platforms | |
1992 | * need to know when we're still using BIOS-provided values | |
1993 | * (which we don't fully trust). | |
1994 | */ | |
1995 | bool distrust_bios_wm; | |
53615a5e VS |
1996 | } wm; |
1997 | ||
8a187455 PZ |
1998 | struct i915_runtime_pm pm; |
1999 | ||
a83014d3 OM |
2000 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
2001 | struct { | |
117897f4 | 2002 | void (*cleanup_engine)(struct intel_engine_cs *engine); |
67d97da3 CW |
2003 | |
2004 | /** | |
2005 | * Is the GPU currently considered idle, or busy executing | |
2006 | * userspace requests? Whilst idle, we allow runtime power | |
2007 | * management to power down the hardware and display clocks. | |
2008 | * In order to reduce the effect on performance, there | |
2009 | * is a slight delay before we do so. | |
2010 | */ | |
2011 | unsigned int active_engines; | |
2012 | bool awake; | |
2013 | ||
2014 | /** | |
2015 | * We leave the user IRQ off as much as possible, | |
2016 | * but this means that requests will finish and never | |
2017 | * be retired once the system goes idle. Set a timer to | |
2018 | * fire periodically while the ring is running. When it | |
2019 | * fires, go retire requests. | |
2020 | */ | |
2021 | struct delayed_work retire_work; | |
2022 | ||
2023 | /** | |
2024 | * When we detect an idle GPU, we want to turn on | |
2025 | * powersaving features. So once we see that there | |
2026 | * are no more requests outstanding and no more | |
2027 | * arrive within a small period of time, we fire | |
2028 | * off the idle_work. | |
2029 | */ | |
2030 | struct delayed_work idle_work; | |
a83014d3 OM |
2031 | } gt; |
2032 | ||
3be60de9 VS |
2033 | /* perform PHY state sanity checks? */ |
2034 | bool chv_phy_assert[2]; | |
2035 | ||
0bdf5a05 TI |
2036 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
2037 | ||
bdf1e7e3 DV |
2038 | /* |
2039 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2040 | * will be rejected. Instead look for a better place. | |
2041 | */ | |
77fec556 | 2042 | }; |
1da177e4 | 2043 | |
2c1792a1 CW |
2044 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2045 | { | |
091387c1 | 2046 | return container_of(dev, struct drm_i915_private, drm); |
2c1792a1 CW |
2047 | } |
2048 | ||
888d0d42 ID |
2049 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
2050 | { | |
2051 | return to_i915(dev_get_drvdata(dev)); | |
2052 | } | |
2053 | ||
33a732f4 AD |
2054 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2055 | { | |
2056 | return container_of(guc, struct drm_i915_private, guc); | |
2057 | } | |
2058 | ||
b4ac5afc DG |
2059 | /* Simple iterator over all initialised engines */ |
2060 | #define for_each_engine(engine__, dev_priv__) \ | |
2061 | for ((engine__) = &(dev_priv__)->engine[0]; \ | |
2062 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2063 | (engine__)++) \ | |
2064 | for_each_if (intel_engine_initialized(engine__)) | |
b4519513 | 2065 | |
c3232b18 DG |
2066 | /* Iterator with engine_id */ |
2067 | #define for_each_engine_id(engine__, dev_priv__, id__) \ | |
2068 | for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \ | |
2069 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2070 | (engine__)++) \ | |
2071 | for_each_if (((id__) = (engine__)->id, \ | |
2072 | intel_engine_initialized(engine__))) | |
2073 | ||
2074 | /* Iterator over subset of engines selected by mask */ | |
ee4b6faf | 2075 | #define for_each_engine_masked(engine__, dev_priv__, mask__) \ |
b4ac5afc DG |
2076 | for ((engine__) = &(dev_priv__)->engine[0]; \ |
2077 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2078 | (engine__)++) \ | |
2079 | for_each_if (((mask__) & intel_engine_flag(engine__)) && \ | |
2080 | intel_engine_initialized(engine__)) | |
ee4b6faf | 2081 | |
b1d7e4b4 WF |
2082 | enum hdmi_force_audio { |
2083 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2084 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2085 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2086 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2087 | }; | |
2088 | ||
190d6cd5 | 2089 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2090 | |
37e680a1 | 2091 | struct drm_i915_gem_object_ops { |
de472664 CW |
2092 | unsigned int flags; |
2093 | #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 | |
2094 | ||
37e680a1 CW |
2095 | /* Interface between the GEM object and its backing storage. |
2096 | * get_pages() is called once prior to the use of the associated set | |
2097 | * of pages before to binding them into the GTT, and put_pages() is | |
2098 | * called after we no longer need them. As we expect there to be | |
2099 | * associated cost with migrating pages between the backing storage | |
2100 | * and making them available for the GPU (e.g. clflush), we may hold | |
2101 | * onto the pages after they are no longer referenced by the GPU | |
2102 | * in case they may be used again shortly (for example migrating the | |
2103 | * pages to a different memory domain within the GTT). put_pages() | |
2104 | * will therefore most likely be called when the object itself is | |
2105 | * being released or under memory pressure (where we attempt to | |
2106 | * reap pages for the shrinker). | |
2107 | */ | |
2108 | int (*get_pages)(struct drm_i915_gem_object *); | |
2109 | void (*put_pages)(struct drm_i915_gem_object *); | |
de472664 | 2110 | |
5cc9ed4b CW |
2111 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2112 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
2113 | }; |
2114 | ||
a071fa00 DV |
2115 | /* |
2116 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2117 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2118 | * doesn't mean that the hw necessarily already scans it out, but that any |
2119 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2120 | * | |
2121 | * We have one bit per pipe and per scanout plane type. | |
2122 | */ | |
d1b9d039 SAK |
2123 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2124 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2125 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ |
2126 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2127 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2128 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2129 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2130 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2131 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2132 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2133 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2134 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2135 | |
673a394b | 2136 | struct drm_i915_gem_object { |
c397b908 | 2137 | struct drm_gem_object base; |
673a394b | 2138 | |
37e680a1 CW |
2139 | const struct drm_i915_gem_object_ops *ops; |
2140 | ||
2f633156 BW |
2141 | /** List of VMAs backed by this object */ |
2142 | struct list_head vma_list; | |
2143 | ||
c1ad11fc CW |
2144 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2145 | struct drm_mm_node *stolen; | |
35c20a60 | 2146 | struct list_head global_list; |
673a394b | 2147 | |
b25cb2f8 BW |
2148 | /** Used in execbuf to temporarily hold a ref */ |
2149 | struct list_head obj_exec_link; | |
673a394b | 2150 | |
8d9d5744 | 2151 | struct list_head batch_pool_link; |
493018dc | 2152 | |
573adb39 | 2153 | unsigned long flags; |
673a394b | 2154 | /** |
65ce3027 CW |
2155 | * This is set if the object is on the active lists (has pending |
2156 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2157 | * inactive (ready to be unbound) list. | |
673a394b | 2158 | */ |
573adb39 CW |
2159 | #define I915_BO_ACTIVE_SHIFT 0 |
2160 | #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1) | |
2161 | #define __I915_BO_ACTIVE(bo) \ | |
2162 | ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK) | |
673a394b EA |
2163 | |
2164 | /** | |
2165 | * This is set if the object has been written to since last bound | |
2166 | * to the GTT | |
2167 | */ | |
0206e353 | 2168 | unsigned int dirty:1; |
778c3544 DV |
2169 | |
2170 | /** | |
2171 | * Fence register bits (if any) for this object. Will be set | |
2172 | * as needed when mapped into the GTT. | |
2173 | * Protected by dev->struct_mutex. | |
778c3544 | 2174 | */ |
4b9de737 | 2175 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 2176 | |
778c3544 DV |
2177 | /** |
2178 | * Advice: are the backing pages purgeable? | |
2179 | */ | |
0206e353 | 2180 | unsigned int madv:2; |
778c3544 | 2181 | |
5d82e3e6 CW |
2182 | /** |
2183 | * Whether the tiling parameters for the currently associated fence | |
2184 | * register have changed. Note that for the purposes of tracking | |
2185 | * tiling changes we also treat the unfenced register, the register | |
2186 | * slot that the object occupies whilst it executes a fenced | |
2187 | * command (such as BLT on gen2/3), as a "fence". | |
2188 | */ | |
2189 | unsigned int fence_dirty:1; | |
778c3544 | 2190 | |
75e9e915 DV |
2191 | /** |
2192 | * Is the object at the current location in the gtt mappable and | |
2193 | * fenceable? Used to avoid costly recalculations. | |
2194 | */ | |
0206e353 | 2195 | unsigned int map_and_fenceable:1; |
75e9e915 | 2196 | |
fb7d516a DV |
2197 | /** |
2198 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2199 | * mappable by accident). Track pin and fault separate for a more | |
2200 | * accurate mappable working set. | |
2201 | */ | |
0206e353 | 2202 | unsigned int fault_mappable:1; |
fb7d516a | 2203 | |
24f3a8cf AG |
2204 | /* |
2205 | * Is the object to be mapped as read-only to the GPU | |
2206 | * Only honoured if hardware has relevant pte bit | |
2207 | */ | |
2208 | unsigned long gt_ro:1; | |
651d794f | 2209 | unsigned int cache_level:3; |
0f71979a | 2210 | unsigned int cache_dirty:1; |
93dfb40c | 2211 | |
faf5bf0a | 2212 | atomic_t frontbuffer_bits; |
a071fa00 | 2213 | |
9ad36761 | 2214 | /** Current tiling stride for the object, if it's tiled. */ |
3e510a8e CW |
2215 | unsigned int tiling_and_stride; |
2216 | #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */ | |
2217 | #define TILING_MASK (FENCE_MINIMUM_STRIDE-1) | |
2218 | #define STRIDE_MASK (~TILING_MASK) | |
9ad36761 | 2219 | |
aeecc969 | 2220 | unsigned int has_wc_mmap; |
15717de2 CW |
2221 | /** Count of VMA actually bound by this object */ |
2222 | unsigned int bind_count; | |
8a0c39b1 TU |
2223 | unsigned int pin_display; |
2224 | ||
9da3da66 | 2225 | struct sg_table *pages; |
a5570178 | 2226 | int pages_pin_count; |
ee286370 CW |
2227 | struct get_page { |
2228 | struct scatterlist *sg; | |
2229 | int last; | |
2230 | } get_page; | |
0a798eb9 | 2231 | void *mapping; |
9a70cc2a | 2232 | |
b4716185 CW |
2233 | /** Breadcrumb of last rendering to the buffer. |
2234 | * There can only be one writer, but we allow for multiple readers. | |
2235 | * If there is a writer that necessarily implies that all other | |
2236 | * read requests are complete - but we may only be lazily clearing | |
2237 | * the read requests. A read request is naturally the most recent | |
2238 | * request on a ring, so we may have two different write and read | |
2239 | * requests on one ring where the write request is older than the | |
2240 | * read request. This allows for the CPU to read from an active | |
2241 | * buffer by only waiting for the write to complete. | |
381f371b CW |
2242 | */ |
2243 | struct i915_gem_active last_read[I915_NUM_ENGINES]; | |
2244 | struct i915_gem_active last_write; | |
2245 | struct i915_gem_active last_fence; | |
673a394b | 2246 | |
80075d49 DV |
2247 | /** References from framebuffers, locks out tiling changes. */ |
2248 | unsigned long framebuffer_references; | |
2249 | ||
280b713b | 2250 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2251 | unsigned long *bit_17; |
280b713b | 2252 | |
5cc9ed4b | 2253 | union { |
6a2c4232 CW |
2254 | /** for phy allocated objects */ |
2255 | struct drm_dma_handle *phys_handle; | |
2256 | ||
5cc9ed4b CW |
2257 | struct i915_gem_userptr { |
2258 | uintptr_t ptr; | |
2259 | unsigned read_only :1; | |
2260 | unsigned workers :4; | |
2261 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2262 | ||
ad46cb53 CW |
2263 | struct i915_mm_struct *mm; |
2264 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2265 | struct work_struct *work; |
2266 | } userptr; | |
2267 | }; | |
2268 | }; | |
03ac0642 CW |
2269 | |
2270 | static inline struct drm_i915_gem_object * | |
2271 | to_intel_bo(struct drm_gem_object *gem) | |
2272 | { | |
2273 | /* Assert that to_intel_bo(NULL) == NULL */ | |
2274 | BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base)); | |
2275 | ||
2276 | return container_of(gem, struct drm_i915_gem_object, base); | |
2277 | } | |
2278 | ||
2279 | static inline struct drm_i915_gem_object * | |
2280 | i915_gem_object_lookup(struct drm_file *file, u32 handle) | |
2281 | { | |
2282 | return to_intel_bo(drm_gem_object_lookup(file, handle)); | |
2283 | } | |
2284 | ||
2285 | __deprecated | |
2286 | extern struct drm_gem_object * | |
2287 | drm_gem_object_lookup(struct drm_file *file, u32 handle); | |
23010e43 | 2288 | |
25dc556a CW |
2289 | __attribute__((nonnull)) |
2290 | static inline struct drm_i915_gem_object * | |
2291 | i915_gem_object_get(struct drm_i915_gem_object *obj) | |
2292 | { | |
2293 | drm_gem_object_reference(&obj->base); | |
2294 | return obj; | |
2295 | } | |
2296 | ||
2297 | __deprecated | |
2298 | extern void drm_gem_object_reference(struct drm_gem_object *); | |
2299 | ||
f8c417cd CW |
2300 | __attribute__((nonnull)) |
2301 | static inline void | |
2302 | i915_gem_object_put(struct drm_i915_gem_object *obj) | |
2303 | { | |
2304 | drm_gem_object_unreference(&obj->base); | |
2305 | } | |
2306 | ||
2307 | __deprecated | |
2308 | extern void drm_gem_object_unreference(struct drm_gem_object *); | |
2309 | ||
34911fd3 CW |
2310 | __attribute__((nonnull)) |
2311 | static inline void | |
2312 | i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj) | |
2313 | { | |
2314 | drm_gem_object_unreference_unlocked(&obj->base); | |
2315 | } | |
2316 | ||
2317 | __deprecated | |
2318 | extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *); | |
2319 | ||
b9bcd14a CW |
2320 | static inline bool |
2321 | i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj) | |
2322 | { | |
2323 | return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE; | |
2324 | } | |
2325 | ||
573adb39 CW |
2326 | static inline unsigned long |
2327 | i915_gem_object_get_active(const struct drm_i915_gem_object *obj) | |
2328 | { | |
2329 | return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK; | |
2330 | } | |
2331 | ||
2332 | static inline bool | |
2333 | i915_gem_object_is_active(const struct drm_i915_gem_object *obj) | |
2334 | { | |
2335 | return i915_gem_object_get_active(obj); | |
2336 | } | |
2337 | ||
2338 | static inline void | |
2339 | i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine) | |
2340 | { | |
2341 | obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT); | |
2342 | } | |
2343 | ||
2344 | static inline void | |
2345 | i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine) | |
2346 | { | |
2347 | obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT); | |
2348 | } | |
2349 | ||
2350 | static inline bool | |
2351 | i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj, | |
2352 | int engine) | |
2353 | { | |
2354 | return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT); | |
2355 | } | |
2356 | ||
3e510a8e CW |
2357 | static inline unsigned int |
2358 | i915_gem_object_get_tiling(struct drm_i915_gem_object *obj) | |
2359 | { | |
2360 | return obj->tiling_and_stride & TILING_MASK; | |
2361 | } | |
2362 | ||
2363 | static inline bool | |
2364 | i915_gem_object_is_tiled(struct drm_i915_gem_object *obj) | |
2365 | { | |
2366 | return i915_gem_object_get_tiling(obj) != I915_TILING_NONE; | |
2367 | } | |
2368 | ||
2369 | static inline unsigned int | |
2370 | i915_gem_object_get_stride(struct drm_i915_gem_object *obj) | |
2371 | { | |
2372 | return obj->tiling_and_stride & STRIDE_MASK; | |
2373 | } | |
2374 | ||
85d1225e DG |
2375 | /* |
2376 | * Optimised SGL iterator for GEM objects | |
2377 | */ | |
2378 | static __always_inline struct sgt_iter { | |
2379 | struct scatterlist *sgp; | |
2380 | union { | |
2381 | unsigned long pfn; | |
2382 | dma_addr_t dma; | |
2383 | }; | |
2384 | unsigned int curr; | |
2385 | unsigned int max; | |
2386 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2387 | struct sgt_iter s = { .sgp = sgl }; | |
2388 | ||
2389 | if (s.sgp) { | |
2390 | s.max = s.curr = s.sgp->offset; | |
2391 | s.max += s.sgp->length; | |
2392 | if (dma) | |
2393 | s.dma = sg_dma_address(s.sgp); | |
2394 | else | |
2395 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2396 | } | |
2397 | ||
2398 | return s; | |
2399 | } | |
2400 | ||
63d15326 DG |
2401 | /** |
2402 | * __sg_next - return the next scatterlist entry in a list | |
2403 | * @sg: The current sg entry | |
2404 | * | |
2405 | * Description: | |
2406 | * If the entry is the last, return NULL; otherwise, step to the next | |
2407 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2408 | * otherwise just return the pointer to the current element. | |
2409 | **/ | |
2410 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2411 | { | |
2412 | #ifdef CONFIG_DEBUG_SG | |
2413 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2414 | #endif | |
2415 | return sg_is_last(sg) ? NULL : | |
2416 | likely(!sg_is_chain(++sg)) ? sg : | |
2417 | sg_chain_ptr(sg); | |
2418 | } | |
2419 | ||
85d1225e DG |
2420 | /** |
2421 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2422 | * @__dmap: DMA address (output) | |
2423 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2424 | * @__sgt: sg_table to iterate over (input) | |
2425 | */ | |
2426 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2427 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2428 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
2429 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2430 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0)) |
85d1225e DG |
2431 | |
2432 | /** | |
2433 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2434 | * @__pp: page pointer (output) | |
2435 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2436 | * @__sgt: sg_table to iterate over (input) | |
2437 | */ | |
2438 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2439 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2440 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2441 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
2442 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2443 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0)) |
a071fa00 | 2444 | |
351e3db2 BV |
2445 | /* |
2446 | * A command that requires special handling by the command parser. | |
2447 | */ | |
2448 | struct drm_i915_cmd_descriptor { | |
2449 | /* | |
2450 | * Flags describing how the command parser processes the command. | |
2451 | * | |
2452 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2453 | * a length mask if not set | |
2454 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2455 | * standard length encoding for the opcode range in | |
2456 | * which it falls | |
2457 | * CMD_DESC_REJECT: The command is never allowed | |
2458 | * CMD_DESC_REGISTER: The command should be checked against the | |
2459 | * register whitelist for the appropriate ring | |
2460 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2461 | * is the DRM master | |
2462 | */ | |
2463 | u32 flags; | |
2464 | #define CMD_DESC_FIXED (1<<0) | |
2465 | #define CMD_DESC_SKIP (1<<1) | |
2466 | #define CMD_DESC_REJECT (1<<2) | |
2467 | #define CMD_DESC_REGISTER (1<<3) | |
2468 | #define CMD_DESC_BITMASK (1<<4) | |
2469 | #define CMD_DESC_MASTER (1<<5) | |
2470 | ||
2471 | /* | |
2472 | * The command's unique identification bits and the bitmask to get them. | |
2473 | * This isn't strictly the opcode field as defined in the spec and may | |
2474 | * also include type, subtype, and/or subop fields. | |
2475 | */ | |
2476 | struct { | |
2477 | u32 value; | |
2478 | u32 mask; | |
2479 | } cmd; | |
2480 | ||
2481 | /* | |
2482 | * The command's length. The command is either fixed length (i.e. does | |
2483 | * not include a length field) or has a length field mask. The flag | |
2484 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2485 | * a length mask. All command entries in a command table must include | |
2486 | * length information. | |
2487 | */ | |
2488 | union { | |
2489 | u32 fixed; | |
2490 | u32 mask; | |
2491 | } length; | |
2492 | ||
2493 | /* | |
2494 | * Describes where to find a register address in the command to check | |
2495 | * against the ring's register whitelist. Only valid if flags has the | |
2496 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2497 | * |
2498 | * A non-zero step value implies that the command may access multiple | |
2499 | * registers in sequence (e.g. LRI), in that case step gives the | |
2500 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2501 | */ |
2502 | struct { | |
2503 | u32 offset; | |
2504 | u32 mask; | |
6a65c5b9 | 2505 | u32 step; |
351e3db2 BV |
2506 | } reg; |
2507 | ||
2508 | #define MAX_CMD_DESC_BITMASKS 3 | |
2509 | /* | |
2510 | * Describes command checks where a particular dword is masked and | |
2511 | * compared against an expected value. If the command does not match | |
2512 | * the expected value, the parser rejects it. Only valid if flags has | |
2513 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2514 | * are valid. | |
d4d48035 BV |
2515 | * |
2516 | * If the check specifies a non-zero condition_mask then the parser | |
2517 | * only performs the check when the bits specified by condition_mask | |
2518 | * are non-zero. | |
351e3db2 BV |
2519 | */ |
2520 | struct { | |
2521 | u32 offset; | |
2522 | u32 mask; | |
2523 | u32 expected; | |
d4d48035 BV |
2524 | u32 condition_offset; |
2525 | u32 condition_mask; | |
351e3db2 BV |
2526 | } bits[MAX_CMD_DESC_BITMASKS]; |
2527 | }; | |
2528 | ||
2529 | /* | |
2530 | * A table of commands requiring special handling by the command parser. | |
2531 | * | |
33a051a5 CW |
2532 | * Each engine has an array of tables. Each table consists of an array of |
2533 | * command descriptors, which must be sorted with command opcodes in | |
2534 | * ascending order. | |
351e3db2 BV |
2535 | */ |
2536 | struct drm_i915_cmd_table { | |
2537 | const struct drm_i915_cmd_descriptor *table; | |
2538 | int count; | |
2539 | }; | |
2540 | ||
dbbe9127 | 2541 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2542 | #define __I915__(p) ({ \ |
2543 | struct drm_i915_private *__p; \ | |
2544 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2545 | __p = (struct drm_i915_private *)p; \ | |
2546 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2547 | __p = to_i915((struct drm_device *)p); \ | |
2548 | else \ | |
2549 | BUILD_BUG(); \ | |
2550 | __p; \ | |
2551 | }) | |
dbbe9127 | 2552 | #define INTEL_INFO(p) (&__I915__(p)->info) |
3f10e82f | 2553 | #define INTEL_GEN(p) (INTEL_INFO(p)->gen) |
87f1f465 | 2554 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
cae5852d | 2555 | |
e87a005d | 2556 | #define REVID_FOREVER 0xff |
091387c1 | 2557 | #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision) |
ac657f64 TU |
2558 | |
2559 | #define GEN_FOREVER (0) | |
2560 | /* | |
2561 | * Returns true if Gen is in inclusive range [Start, End]. | |
2562 | * | |
2563 | * Use GEN_FOREVER for unbound start and or end. | |
2564 | */ | |
2565 | #define IS_GEN(p, s, e) ({ \ | |
2566 | unsigned int __s = (s), __e = (e); \ | |
2567 | BUILD_BUG_ON(!__builtin_constant_p(s)); \ | |
2568 | BUILD_BUG_ON(!__builtin_constant_p(e)); \ | |
2569 | if ((__s) != GEN_FOREVER) \ | |
2570 | __s = (s) - 1; \ | |
2571 | if ((__e) == GEN_FOREVER) \ | |
2572 | __e = BITS_PER_LONG - 1; \ | |
2573 | else \ | |
2574 | __e = (e) - 1; \ | |
2575 | !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \ | |
2576 | }) | |
2577 | ||
e87a005d JN |
2578 | /* |
2579 | * Return true if revision is in range [since,until] inclusive. | |
2580 | * | |
2581 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2582 | */ | |
2583 | #define IS_REVID(p, since, until) \ | |
2584 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2585 | ||
87f1f465 CW |
2586 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2587 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2588 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2589 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2590 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2591 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2592 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2593 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2594 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2595 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2596 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2597 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2598 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2599 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2600 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2601 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2602 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2603 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2604 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2605 | INTEL_DEVID(dev) == 0x0152 || \ | |
2606 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2607 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
666a4537 | 2608 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
4cae9ae0 | 2609 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
ab0d24ac | 2610 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell) |
7201c0b3 | 2611 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
7526ac19 | 2612 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
ef11bdb3 | 2613 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
cae5852d | 2614 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2615 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2616 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2617 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2618 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2619 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2620 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2621 | /* ULX machines are also considered ULT. */ |
2622 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2623 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2624 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2625 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2626 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2627 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2628 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2629 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2630 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2631 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2632 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2633 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2634 | INTEL_DEVID(dev) == 0x1913 || \ | |
2635 | INTEL_DEVID(dev) == 0x1916 || \ | |
2636 | INTEL_DEVID(dev) == 0x1921 || \ | |
2637 | INTEL_DEVID(dev) == 0x1926) | |
2638 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2639 | INTEL_DEVID(dev) == 0x1915 || \ | |
2640 | INTEL_DEVID(dev) == 0x191E) | |
a5b7991c RV |
2641 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
2642 | INTEL_DEVID(dev) == 0x5913 || \ | |
2643 | INTEL_DEVID(dev) == 0x5916 || \ | |
2644 | INTEL_DEVID(dev) == 0x5921 || \ | |
2645 | INTEL_DEVID(dev) == 0x5926) | |
2646 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ | |
2647 | INTEL_DEVID(dev) == 0x5915 || \ | |
2648 | INTEL_DEVID(dev) == 0x591E) | |
7a58bad0 SAK |
2649 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2650 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2651 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2652 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2653 | ||
b833d685 | 2654 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2655 | |
ef712bb4 JN |
2656 | #define SKL_REVID_A0 0x0 |
2657 | #define SKL_REVID_B0 0x1 | |
2658 | #define SKL_REVID_C0 0x2 | |
2659 | #define SKL_REVID_D0 0x3 | |
2660 | #define SKL_REVID_E0 0x4 | |
2661 | #define SKL_REVID_F0 0x5 | |
4ba9c1f7 MK |
2662 | #define SKL_REVID_G0 0x6 |
2663 | #define SKL_REVID_H0 0x7 | |
ef712bb4 | 2664 | |
e87a005d JN |
2665 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2666 | ||
ef712bb4 | 2667 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2668 | #define BXT_REVID_A1 0x1 |
ef712bb4 JN |
2669 | #define BXT_REVID_B0 0x3 |
2670 | #define BXT_REVID_C0 0x9 | |
6c74c87f | 2671 | |
e87a005d JN |
2672 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2673 | ||
c033a37c MK |
2674 | #define KBL_REVID_A0 0x0 |
2675 | #define KBL_REVID_B0 0x1 | |
fe905819 MK |
2676 | #define KBL_REVID_C0 0x2 |
2677 | #define KBL_REVID_D0 0x3 | |
2678 | #define KBL_REVID_E0 0x4 | |
c033a37c MK |
2679 | |
2680 | #define IS_KBL_REVID(p, since, until) \ | |
2681 | (IS_KABYLAKE(p) && IS_REVID(p, since, until)) | |
2682 | ||
85436696 JB |
2683 | /* |
2684 | * The genX designation typically refers to the render engine, so render | |
2685 | * capability related checks should use IS_GEN, while display and other checks | |
2686 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2687 | * chips, etc.). | |
2688 | */ | |
af1346a0 TU |
2689 | #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1))) |
2690 | #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2))) | |
2691 | #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3))) | |
2692 | #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4))) | |
2693 | #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5))) | |
2694 | #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6))) | |
2695 | #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7))) | |
2696 | #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8))) | |
cae5852d | 2697 | |
a19d6ff2 TU |
2698 | #define ENGINE_MASK(id) BIT(id) |
2699 | #define RENDER_RING ENGINE_MASK(RCS) | |
2700 | #define BSD_RING ENGINE_MASK(VCS) | |
2701 | #define BLT_RING ENGINE_MASK(BCS) | |
2702 | #define VEBOX_RING ENGINE_MASK(VECS) | |
2703 | #define BSD2_RING ENGINE_MASK(VCS2) | |
2704 | #define ALL_ENGINES (~0) | |
2705 | ||
2706 | #define HAS_ENGINE(dev_priv, id) \ | |
af1346a0 | 2707 | (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) |
a19d6ff2 TU |
2708 | |
2709 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
2710 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
2711 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
2712 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
2713 | ||
63c42e56 | 2714 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
ca377809 | 2715 | #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) |
af1346a0 | 2716 | #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED)) |
63c42e56 | 2717 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ |
3accaf7e | 2718 | HAS_EDRAM(dev)) |
cae5852d ZN |
2719 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2720 | ||
254f965c | 2721 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2722 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c | 2723 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2724 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2725 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2726 | |
05394f39 | 2727 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2728 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2729 | ||
b45305fc DV |
2730 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2731 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
06e668ac MK |
2732 | |
2733 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
61251512 TU |
2734 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ |
2735 | (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \ | |
2736 | IS_SKL_GT3(dev_priv) || \ | |
2737 | IS_SKL_GT4(dev_priv)) | |
185c66e5 | 2738 | |
4e6b788c DV |
2739 | /* |
2740 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2741 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2742 | * legacy irq no. is shared with another device. The kernel then disables that | |
2743 | * interrupt source and so prevents the other device from working properly. | |
2744 | */ | |
2745 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2746 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2747 | |
cae5852d ZN |
2748 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2749 | * rows, which changed the alignment requirements and fence programming. | |
2750 | */ | |
2751 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2752 | IS_I915GM(dev))) | |
cae5852d ZN |
2753 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2754 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2755 | |
2756 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2757 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2758 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2759 | |
dbf7786e | 2760 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2761 | |
0c9b3715 JN |
2762 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2763 | INTEL_INFO(dev)->gen >= 9) | |
2764 | ||
dd93be58 | 2765 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2766 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2767 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 | 2768 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
ef11bdb3 | 2769 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
6157d3c8 | 2770 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 | 2771 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
666a4537 | 2772 | IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \ |
8f6d855c | 2773 | IS_KABYLAKE(dev) || IS_BROXTON(dev)) |
58abf1da | 2774 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
7e22dbbb | 2775 | #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
affa9354 | 2776 | |
7b403ffb | 2777 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
eb805623 | 2778 | |
1a3d1898 DG |
2779 | /* |
2780 | * For now, anything with a GuC requires uCode loading, and then supports | |
2781 | * command submission once loaded. But these are logically independent | |
2782 | * properties, so we have separate macros to test them. | |
2783 | */ | |
6f8be280 | 2784 | #define HAS_GUC(dev) (IS_GEN9(dev)) |
1a3d1898 DG |
2785 | #define HAS_GUC_UCODE(dev) (HAS_GUC(dev)) |
2786 | #define HAS_GUC_SCHED(dev) (HAS_GUC(dev)) | |
33a732f4 | 2787 | |
a9ed33ca AJ |
2788 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2789 | INTEL_INFO(dev)->gen >= 8) | |
2790 | ||
97d3308a | 2791 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
666a4537 WB |
2792 | !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ |
2793 | !IS_BROXTON(dev)) | |
97d3308a | 2794 | |
33e141ed | 2795 | #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) |
2796 | ||
17a303ec PZ |
2797 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2798 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2799 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2800 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2801 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2802 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2803 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2804 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
22dea0be | 2805 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200 |
30c964a6 | 2806 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 2807 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 2808 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2809 | |
f2fbc690 | 2810 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
22dea0be | 2811 | #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP) |
e7e7ea20 | 2812 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2813 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
c2699524 | 2814 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
56f5f700 | 2815 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
cae5852d ZN |
2816 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2817 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2818 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2819 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2820 | |
666a4537 WB |
2821 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ |
2822 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
5fafe292 | 2823 | |
040d2baa BW |
2824 | /* DPF == dynamic parity feature */ |
2825 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2826 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2827 | |
c8735b0c | 2828 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2829 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2830 | |
05394f39 CW |
2831 | #include "i915_trace.h" |
2832 | ||
48f112fe CW |
2833 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) |
2834 | { | |
2835 | #ifdef CONFIG_INTEL_IOMMU | |
2836 | if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped) | |
2837 | return true; | |
2838 | #endif | |
2839 | return false; | |
2840 | } | |
2841 | ||
1751fcf9 ML |
2842 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2843 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2844 | |
c033666a CW |
2845 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
2846 | int enable_ppgtt); | |
0e4ca100 | 2847 | |
39df9190 CW |
2848 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); |
2849 | ||
0673ad47 | 2850 | /* i915_drv.c */ |
d15d7538 ID |
2851 | void __printf(3, 4) |
2852 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
2853 | const char *fmt, ...); | |
2854 | ||
2855 | #define i915_report_error(dev_priv, fmt, ...) \ | |
2856 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
2857 | ||
c43b5634 | 2858 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2859 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2860 | unsigned long arg); | |
c43b5634 | 2861 | #endif |
dc97997a CW |
2862 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); |
2863 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
c033666a | 2864 | extern int i915_reset(struct drm_i915_private *dev_priv); |
6b332fa2 | 2865 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); |
fc0768ce | 2866 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
7648fa99 JB |
2867 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2868 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2869 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2870 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2871 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2872 | |
77913b39 | 2873 | /* intel_hotplug.c */ |
91d14251 TU |
2874 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2875 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
2876 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2877 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2878 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2879 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
b236d7c8 L |
2880 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); |
2881 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
77913b39 | 2882 | |
1da177e4 | 2883 | /* i915_irq.c */ |
26a02b8f CW |
2884 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
2885 | { | |
2886 | unsigned long delay; | |
2887 | ||
2888 | if (unlikely(!i915.enable_hangcheck)) | |
2889 | return; | |
2890 | ||
2891 | /* Don't continually defer the hangcheck so that it is always run at | |
2892 | * least once after work has been scheduled on any ring. Otherwise, | |
2893 | * we will ignore a hung ring if a second ring is kept busy. | |
2894 | */ | |
2895 | ||
2896 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
2897 | queue_delayed_work(system_long_wq, | |
2898 | &dev_priv->gpu_error.hangcheck_work, delay); | |
2899 | } | |
2900 | ||
58174462 | 2901 | __printf(3, 4) |
c033666a CW |
2902 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2903 | u32 engine_mask, | |
58174462 | 2904 | const char *fmt, ...); |
1da177e4 | 2905 | |
b963291c | 2906 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2907 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2908 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 | 2909 | |
dc97997a CW |
2910 | extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv); |
2911 | extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, | |
10018603 | 2912 | bool restore_forcewake); |
dc97997a | 2913 | extern void intel_uncore_init(struct drm_i915_private *dev_priv); |
fc97618b | 2914 | extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); |
bc3b9346 | 2915 | extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); |
dc97997a CW |
2916 | extern void intel_uncore_fini(struct drm_i915_private *dev_priv); |
2917 | extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, | |
2918 | bool restore); | |
48c1026a | 2919 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2920 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2921 | enum forcewake_domains domains); |
59bad947 | 2922 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2923 | enum forcewake_domains domains); |
a6111f7b CW |
2924 | /* Like above but the caller must manage the uncore.lock itself. |
2925 | * Must be used with I915_READ_FW and friends. | |
2926 | */ | |
2927 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2928 | enum forcewake_domains domains); | |
2929 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2930 | enum forcewake_domains domains); | |
3accaf7e MK |
2931 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); |
2932 | ||
59bad947 | 2933 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
0ad35fed | 2934 | |
1758b90e CW |
2935 | int intel_wait_for_register(struct drm_i915_private *dev_priv, |
2936 | i915_reg_t reg, | |
2937 | const u32 mask, | |
2938 | const u32 value, | |
2939 | const unsigned long timeout_ms); | |
2940 | int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, | |
2941 | i915_reg_t reg, | |
2942 | const u32 mask, | |
2943 | const u32 value, | |
2944 | const unsigned long timeout_ms); | |
2945 | ||
0ad35fed ZW |
2946 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) |
2947 | { | |
2948 | return dev_priv->gvt.initialized; | |
2949 | } | |
2950 | ||
c033666a | 2951 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) |
cf9d2890 | 2952 | { |
c033666a | 2953 | return dev_priv->vgpu.active; |
cf9d2890 | 2954 | } |
b1f14ad0 | 2955 | |
7c463586 | 2956 | void |
50227e1c | 2957 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2958 | u32 status_mask); |
7c463586 KP |
2959 | |
2960 | void | |
50227e1c | 2961 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2962 | u32 status_mask); |
7c463586 | 2963 | |
f8b79e58 ID |
2964 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2965 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2966 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2967 | uint32_t mask, | |
2968 | uint32_t bits); | |
fbdedaea VS |
2969 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2970 | uint32_t interrupt_mask, | |
2971 | uint32_t enabled_irq_mask); | |
2972 | static inline void | |
2973 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2974 | { | |
2975 | ilk_update_display_irq(dev_priv, bits, bits); | |
2976 | } | |
2977 | static inline void | |
2978 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2979 | { | |
2980 | ilk_update_display_irq(dev_priv, bits, 0); | |
2981 | } | |
013d3752 VS |
2982 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
2983 | enum pipe pipe, | |
2984 | uint32_t interrupt_mask, | |
2985 | uint32_t enabled_irq_mask); | |
2986 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
2987 | enum pipe pipe, uint32_t bits) | |
2988 | { | |
2989 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
2990 | } | |
2991 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
2992 | enum pipe pipe, uint32_t bits) | |
2993 | { | |
2994 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
2995 | } | |
47339cd9 DV |
2996 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2997 | uint32_t interrupt_mask, | |
2998 | uint32_t enabled_irq_mask); | |
14443261 VS |
2999 | static inline void |
3000 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3001 | { | |
3002 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
3003 | } | |
3004 | static inline void | |
3005 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3006 | { | |
3007 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
3008 | } | |
3009 | ||
673a394b | 3010 | /* i915_gem.c */ |
673a394b EA |
3011 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
3012 | struct drm_file *file_priv); | |
3013 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
3014 | struct drm_file *file_priv); | |
3015 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
3016 | struct drm_file *file_priv); | |
3017 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
3018 | struct drm_file *file_priv); | |
de151cf6 JB |
3019 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
3020 | struct drm_file *file_priv); | |
673a394b EA |
3021 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
3022 | struct drm_file *file_priv); | |
3023 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
3024 | struct drm_file *file_priv); | |
3025 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3026 | struct drm_file *file_priv); | |
76446cac JB |
3027 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
3028 | struct drm_file *file_priv); | |
673a394b EA |
3029 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3030 | struct drm_file *file_priv); | |
199adf40 BW |
3031 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3032 | struct drm_file *file); | |
3033 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
3034 | struct drm_file *file); | |
673a394b EA |
3035 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3036 | struct drm_file *file_priv); | |
3ef94daa CW |
3037 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3038 | struct drm_file *file_priv); | |
673a394b EA |
3039 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
3040 | struct drm_file *file_priv); | |
3041 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
3042 | struct drm_file *file_priv); | |
72778cb2 | 3043 | void i915_gem_init_userptr(struct drm_i915_private *dev_priv); |
5cc9ed4b CW |
3044 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
3045 | struct drm_file *file); | |
5a125c3c EA |
3046 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
3047 | struct drm_file *file_priv); | |
23ba4fd0 BW |
3048 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
3049 | struct drm_file *file_priv); | |
d64aa096 ID |
3050 | void i915_gem_load_init(struct drm_device *dev); |
3051 | void i915_gem_load_cleanup(struct drm_device *dev); | |
40ae4e16 | 3052 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
461fb99c CW |
3053 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); |
3054 | ||
42dcedd4 CW |
3055 | void *i915_gem_object_alloc(struct drm_device *dev); |
3056 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
3057 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3058 | const struct drm_i915_gem_object_ops *ops); | |
d37cd8a8 | 3059 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 3060 | size_t size); |
ea70299d DG |
3061 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
3062 | struct drm_device *dev, const void *data, size_t size); | |
b1f788c6 | 3063 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); |
673a394b | 3064 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 3065 | |
ec7adb6e JL |
3066 | int __must_check |
3067 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
3068 | const struct i915_ggtt_view *view, | |
91b2db6f | 3069 | u64 size, |
2ffffd0f CW |
3070 | u64 alignment, |
3071 | u64 flags); | |
fe14d5f4 TU |
3072 | |
3073 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3074 | u32 flags); | |
d0710abb | 3075 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
07fe0b12 | 3076 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
b1f788c6 CW |
3077 | void i915_vma_close(struct i915_vma *vma); |
3078 | void i915_vma_destroy(struct i915_vma *vma); | |
aa653a68 CW |
3079 | |
3080 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj); | |
dd624afd | 3081 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 3082 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 3083 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 3084 | |
4c914c0c BV |
3085 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
3086 | int *needs_clflush); | |
3087 | ||
37e680a1 | 3088 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
3089 | |
3090 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 3091 | { |
ee286370 CW |
3092 | return sg->length >> PAGE_SHIFT; |
3093 | } | |
67d5a50c | 3094 | |
033908ae DG |
3095 | struct page * |
3096 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); | |
3097 | ||
341be1cd CW |
3098 | static inline dma_addr_t |
3099 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n) | |
3100 | { | |
3101 | if (n < obj->get_page.last) { | |
3102 | obj->get_page.sg = obj->pages->sgl; | |
3103 | obj->get_page.last = 0; | |
3104 | } | |
3105 | ||
3106 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { | |
3107 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3108 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3109 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3110 | } | |
3111 | ||
3112 | return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT); | |
3113 | } | |
3114 | ||
ee286370 CW |
3115 | static inline struct page * |
3116 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 3117 | { |
ee286370 CW |
3118 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
3119 | return NULL; | |
67d5a50c | 3120 | |
ee286370 CW |
3121 | if (n < obj->get_page.last) { |
3122 | obj->get_page.sg = obj->pages->sgl; | |
3123 | obj->get_page.last = 0; | |
3124 | } | |
67d5a50c | 3125 | |
ee286370 CW |
3126 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
3127 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3128 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3129 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3130 | } | |
67d5a50c | 3131 | |
ee286370 | 3132 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 3133 | } |
ee286370 | 3134 | |
a5570178 CW |
3135 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
3136 | { | |
3137 | BUG_ON(obj->pages == NULL); | |
3138 | obj->pages_pin_count++; | |
3139 | } | |
0a798eb9 | 3140 | |
a5570178 CW |
3141 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
3142 | { | |
3143 | BUG_ON(obj->pages_pin_count == 0); | |
3144 | obj->pages_pin_count--; | |
3145 | } | |
3146 | ||
0a798eb9 CW |
3147 | /** |
3148 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
3149 | * @obj - the object to map into kernel address space | |
3150 | * | |
3151 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3152 | * pages and then returns a contiguous mapping of the backing storage into | |
3153 | * the kernel address space. | |
3154 | * | |
8305216f DG |
3155 | * The caller must hold the struct_mutex, and is responsible for calling |
3156 | * i915_gem_object_unpin_map() when the mapping is no longer required. | |
0a798eb9 | 3157 | * |
8305216f DG |
3158 | * Returns the pointer through which to access the mapped object, or an |
3159 | * ERR_PTR() on error. | |
0a798eb9 CW |
3160 | */ |
3161 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj); | |
3162 | ||
3163 | /** | |
3164 | * i915_gem_object_unpin_map - releases an earlier mapping | |
3165 | * @obj - the object to unmap | |
3166 | * | |
3167 | * After pinning the object and mapping its pages, once you are finished | |
3168 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3169 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3170 | * removed. | |
3171 | * | |
3172 | * The caller must hold the struct_mutex. | |
3173 | */ | |
3174 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3175 | { | |
3176 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3177 | i915_gem_object_unpin_pages(obj); | |
3178 | } | |
3179 | ||
54cf91dc | 3180 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 3181 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
8e637178 | 3182 | struct drm_i915_gem_request *to); |
e2d05a8b | 3183 | void i915_vma_move_to_active(struct i915_vma *vma, |
5cf3d280 CW |
3184 | struct drm_i915_gem_request *req, |
3185 | unsigned int flags); | |
ff72145b DA |
3186 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3187 | struct drm_device *dev, | |
3188 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3189 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3190 | uint32_t handle, uint64_t *offset); | |
85d1225e DG |
3191 | |
3192 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3193 | struct drm_i915_gem_object *new, | |
3194 | unsigned frontbuffer_bits); | |
3195 | ||
fca26bb4 | 3196 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
1690e1eb | 3197 | |
8d9fc7fd | 3198 | struct drm_i915_gem_request * |
0bc40be8 | 3199 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3200 | |
67d97da3 | 3201 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv); |
84c33a64 | 3202 | |
c19ae989 CW |
3203 | static inline u32 i915_reset_counter(struct i915_gpu_error *error) |
3204 | { | |
3205 | return atomic_read(&error->reset_counter); | |
3206 | } | |
3207 | ||
3208 | static inline bool __i915_reset_in_progress(u32 reset) | |
3209 | { | |
3210 | return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG); | |
3211 | } | |
3212 | ||
3213 | static inline bool __i915_reset_in_progress_or_wedged(u32 reset) | |
3214 | { | |
3215 | return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); | |
3216 | } | |
3217 | ||
3218 | static inline bool __i915_terminally_wedged(u32 reset) | |
3219 | { | |
3220 | return unlikely(reset & I915_WEDGED); | |
3221 | } | |
3222 | ||
1f83fee0 DV |
3223 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
3224 | { | |
c19ae989 CW |
3225 | return __i915_reset_in_progress(i915_reset_counter(error)); |
3226 | } | |
3227 | ||
3228 | static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) | |
3229 | { | |
3230 | return __i915_reset_in_progress_or_wedged(i915_reset_counter(error)); | |
1f83fee0 DV |
3231 | } |
3232 | ||
3233 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
3234 | { | |
c19ae989 | 3235 | return __i915_terminally_wedged(i915_reset_counter(error)); |
2ac0f450 MK |
3236 | } |
3237 | ||
3238 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3239 | { | |
c19ae989 | 3240 | return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2; |
1f83fee0 | 3241 | } |
a71d8d94 | 3242 | |
069efc1d | 3243 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 3244 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 3245 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 DV |
3246 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
3247 | void i915_gem_init_swizzling(struct drm_device *dev); | |
117897f4 | 3248 | void i915_gem_cleanup_engines(struct drm_device *dev); |
dcff85c8 CW |
3249 | int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
3250 | bool interruptible); | |
45c5f202 | 3251 | int __must_check i915_gem_suspend(struct drm_device *dev); |
5ab57c70 | 3252 | void i915_gem_resume(struct drm_device *dev); |
de151cf6 | 3253 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 3254 | int __must_check |
2e2f351d CW |
3255 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3256 | bool readonly); | |
3257 | int __must_check | |
2021746e CW |
3258 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3259 | bool write); | |
3260 | int __must_check | |
dabdfe02 CW |
3261 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3262 | int __must_check | |
2da3b9b9 CW |
3263 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3264 | u32 alignment, | |
e6617330 TU |
3265 | const struct i915_ggtt_view *view); |
3266 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
3267 | const struct i915_ggtt_view *view); | |
00731155 | 3268 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3269 | int align); |
b29c19b6 | 3270 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3271 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3272 | |
a9f1481f CW |
3273 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size, |
3274 | int tiling_mode); | |
3275 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, | |
ad1a7d20 | 3276 | int tiling_mode, bool fenced); |
467cffba | 3277 | |
e4ffd173 CW |
3278 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3279 | enum i915_cache_level cache_level); | |
3280 | ||
1286ff73 DV |
3281 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3282 | struct dma_buf *dma_buf); | |
3283 | ||
3284 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3285 | struct drm_gem_object *gem_obj, int flags); | |
3286 | ||
088e0df4 MT |
3287 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
3288 | const struct i915_ggtt_view *view); | |
3289 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
3290 | struct i915_address_space *vm); | |
3291 | static inline u64 | |
ec7adb6e | 3292 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
fe14d5f4 | 3293 | { |
9abc4648 | 3294 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 3295 | } |
ec7adb6e | 3296 | |
ec7adb6e | 3297 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 3298 | const struct i915_ggtt_view *view); |
a70a3148 | 3299 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 3300 | struct i915_address_space *vm); |
fe14d5f4 | 3301 | |
fe14d5f4 | 3302 | struct i915_vma * |
ec7adb6e JL |
3303 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3304 | struct i915_address_space *vm); | |
3305 | struct i915_vma * | |
3306 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
3307 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3308 | |
accfef2e BW |
3309 | struct i915_vma * |
3310 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
3311 | struct i915_address_space *vm); |
3312 | struct i915_vma * | |
3313 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
3314 | const struct i915_ggtt_view *view); | |
5c2abbea | 3315 | |
ec7adb6e JL |
3316 | static inline struct i915_vma * |
3317 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
3318 | { | |
3319 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 3320 | } |
ec7adb6e | 3321 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 3322 | |
a70a3148 | 3323 | /* Some GGTT VM helpers */ |
841cd773 DV |
3324 | static inline struct i915_hw_ppgtt * |
3325 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3326 | { | |
841cd773 DV |
3327 | return container_of(vm, struct i915_hw_ppgtt, base); |
3328 | } | |
3329 | ||
a70a3148 BW |
3330 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3331 | { | |
9abc4648 | 3332 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
3333 | } |
3334 | ||
8da32727 TU |
3335 | unsigned long |
3336 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj); | |
c37e2204 | 3337 | |
e6617330 TU |
3338 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3339 | const struct i915_ggtt_view *view); | |
3340 | static inline void | |
3341 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3342 | { | |
3343 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3344 | } | |
b287110e | 3345 | |
41a36b73 DV |
3346 | /* i915_gem_fence.c */ |
3347 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
3348 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
3349 | ||
3350 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
3351 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
3352 | ||
3353 | void i915_gem_restore_fences(struct drm_device *dev); | |
3354 | ||
7f96ecaf DV |
3355 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3356 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3357 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3358 | ||
254f965c | 3359 | /* i915_gem_context.c */ |
8245be31 | 3360 | int __must_check i915_gem_context_init(struct drm_device *dev); |
b2e862d0 | 3361 | void i915_gem_context_lost(struct drm_i915_private *dev_priv); |
254f965c | 3362 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3363 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3364 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
254f965c | 3365 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3366 | int i915_switch_context(struct drm_i915_gem_request *req); |
945657b4 | 3367 | int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv); |
dce3271b | 3368 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3369 | struct drm_i915_gem_object * |
3370 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
c8c35799 ZW |
3371 | struct i915_gem_context * |
3372 | i915_gem_context_create_gvt(struct drm_device *dev); | |
ca585b5d CW |
3373 | |
3374 | static inline struct i915_gem_context * | |
3375 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3376 | { | |
3377 | struct i915_gem_context *ctx; | |
3378 | ||
091387c1 | 3379 | lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex); |
ca585b5d CW |
3380 | |
3381 | ctx = idr_find(&file_priv->context_idr, id); | |
3382 | if (!ctx) | |
3383 | return ERR_PTR(-ENOENT); | |
3384 | ||
3385 | return ctx; | |
3386 | } | |
3387 | ||
9a6feaf0 CW |
3388 | static inline struct i915_gem_context * |
3389 | i915_gem_context_get(struct i915_gem_context *ctx) | |
dce3271b | 3390 | { |
691e6415 | 3391 | kref_get(&ctx->ref); |
9a6feaf0 | 3392 | return ctx; |
dce3271b MK |
3393 | } |
3394 | ||
9a6feaf0 | 3395 | static inline void i915_gem_context_put(struct i915_gem_context *ctx) |
dce3271b | 3396 | { |
091387c1 | 3397 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
691e6415 | 3398 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3399 | } |
3400 | ||
e2efd130 | 3401 | static inline bool i915_gem_context_is_default(const struct i915_gem_context *c) |
3fac8978 | 3402 | { |
821d66dd | 3403 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3404 | } |
3405 | ||
84624813 BW |
3406 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3407 | struct drm_file *file); | |
3408 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3409 | struct drm_file *file); | |
c9dc0f35 CW |
3410 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3411 | struct drm_file *file_priv); | |
3412 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3413 | struct drm_file *file_priv); | |
d538704b CW |
3414 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, |
3415 | struct drm_file *file); | |
1286ff73 | 3416 | |
679845ed | 3417 | /* i915_gem_evict.c */ |
e522ac23 | 3418 | int __must_check i915_gem_evict_something(struct i915_address_space *vm, |
2ffffd0f | 3419 | u64 min_size, u64 alignment, |
679845ed | 3420 | unsigned cache_level, |
2ffffd0f | 3421 | u64 start, u64 end, |
1ec9e26d | 3422 | unsigned flags); |
506a8e87 | 3423 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
679845ed | 3424 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3425 | |
0260c420 | 3426 | /* belongs in i915_gem_gtt.h */ |
c033666a | 3427 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) |
e76e9aeb | 3428 | { |
c033666a | 3429 | if (INTEL_GEN(dev_priv) < 6) |
e76e9aeb BW |
3430 | intel_gtt_chipset_flush(); |
3431 | } | |
246cbfb5 | 3432 | |
9797fbfb | 3433 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3434 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3435 | struct drm_mm_node *node, u64 size, | |
3436 | unsigned alignment); | |
a9da512b PZ |
3437 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3438 | struct drm_mm_node *node, u64 size, | |
3439 | unsigned alignment, u64 start, | |
3440 | u64 end); | |
d713fd49 PZ |
3441 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3442 | struct drm_mm_node *node); | |
9797fbfb CW |
3443 | int i915_gem_init_stolen(struct drm_device *dev); |
3444 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3445 | struct drm_i915_gem_object * |
3446 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3447 | struct drm_i915_gem_object * |
3448 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3449 | u32 stolen_offset, | |
3450 | u32 gtt_offset, | |
3451 | u32 size); | |
9797fbfb | 3452 | |
be6a0376 DV |
3453 | /* i915_gem_shrinker.c */ |
3454 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3455 | unsigned long target, |
be6a0376 DV |
3456 | unsigned flags); |
3457 | #define I915_SHRINK_PURGEABLE 0x1 | |
3458 | #define I915_SHRINK_UNBOUND 0x2 | |
3459 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3460 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3461 | #define I915_SHRINK_VMAPS 0x10 |
be6a0376 DV |
3462 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3463 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3464 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3465 | |
3466 | ||
673a394b | 3467 | /* i915_gem_tiling.c */ |
2c1792a1 | 3468 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3469 | { |
091387c1 | 3470 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e9b73c67 CW |
3471 | |
3472 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3e510a8e | 3473 | i915_gem_object_is_tiled(obj); |
e9b73c67 CW |
3474 | } |
3475 | ||
2017263e | 3476 | /* i915_debugfs.c */ |
f8c168fa | 3477 | #ifdef CONFIG_DEBUG_FS |
1dac891c CW |
3478 | int i915_debugfs_register(struct drm_i915_private *dev_priv); |
3479 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv); | |
249e87de | 3480 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3481 | void intel_display_crc_init(struct drm_device *dev); |
3482 | #else | |
8d35acba CW |
3483 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} |
3484 | static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {} | |
101057fa DV |
3485 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3486 | { return 0; } | |
f8c168fa | 3487 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3488 | #endif |
84734a04 MK |
3489 | |
3490 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3491 | __printf(2, 3) |
3492 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3493 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3494 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3495 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3496 | struct drm_i915_private *i915, |
4dc955f7 MK |
3497 | size_t count, loff_t pos); |
3498 | static inline void i915_error_state_buf_release( | |
3499 | struct drm_i915_error_state_buf *eb) | |
3500 | { | |
3501 | kfree(eb->buf); | |
3502 | } | |
c033666a CW |
3503 | void i915_capture_error_state(struct drm_i915_private *dev_priv, |
3504 | u32 engine_mask, | |
58174462 | 3505 | const char *error_msg); |
84734a04 MK |
3506 | void i915_error_state_get(struct drm_device *dev, |
3507 | struct i915_error_state_file_priv *error_priv); | |
3508 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3509 | void i915_destroy_error_state(struct drm_device *dev); | |
3510 | ||
c033666a | 3511 | void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone); |
0a4cd7c8 | 3512 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3513 | |
351e3db2 | 3514 | /* i915_cmd_parser.c */ |
1ca3712c | 3515 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
33a051a5 CW |
3516 | int intel_engine_init_cmd_parser(struct intel_engine_cs *engine); |
3517 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); | |
3518 | bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine); | |
3519 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, | |
3520 | struct drm_i915_gem_object *batch_obj, | |
3521 | struct drm_i915_gem_object *shadow_batch_obj, | |
3522 | u32 batch_start_offset, | |
3523 | u32 batch_len, | |
3524 | bool is_master); | |
351e3db2 | 3525 | |
317c35d1 JB |
3526 | /* i915_suspend.c */ |
3527 | extern int i915_save_state(struct drm_device *dev); | |
3528 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3529 | |
0136db58 BW |
3530 | /* i915_sysfs.c */ |
3531 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3532 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3533 | ||
f899fc64 CW |
3534 | /* intel_i2c.c */ |
3535 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3536 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3537 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3538 | unsigned int pin); | |
3bd7d909 | 3539 | |
0184df46 JN |
3540 | extern struct i2c_adapter * |
3541 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3542 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3543 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3544 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3545 | { |
3546 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3547 | } | |
f899fc64 CW |
3548 | extern void intel_i2c_reset(struct drm_device *dev); |
3549 | ||
8b8e1a89 | 3550 | /* intel_bios.c */ |
98f3a1dc | 3551 | int intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3552 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 3553 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 3554 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
22f35042 | 3555 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
951d9efe | 3556 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 3557 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 3558 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
3559 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
3560 | enum port port); | |
8b8e1a89 | 3561 | |
3b617967 | 3562 | /* intel_opregion.c */ |
44834a67 | 3563 | #ifdef CONFIG_ACPI |
6f9f4b7a | 3564 | extern int intel_opregion_setup(struct drm_i915_private *dev_priv); |
03d92e47 CW |
3565 | extern void intel_opregion_register(struct drm_i915_private *dev_priv); |
3566 | extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); | |
91d14251 | 3567 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); |
9c4b0a68 JN |
3568 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3569 | bool enable); | |
6f9f4b7a | 3570 | extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, |
ecbc5cf3 | 3571 | pci_power_t state); |
6f9f4b7a | 3572 | extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); |
65e082c9 | 3573 | #else |
6f9f4b7a | 3574 | static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } |
bdaa2dfb RD |
3575 | static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } |
3576 | static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } | |
91d14251 TU |
3577 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) |
3578 | { | |
3579 | } | |
9c4b0a68 JN |
3580 | static inline int |
3581 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3582 | { | |
3583 | return 0; | |
3584 | } | |
ecbc5cf3 | 3585 | static inline int |
6f9f4b7a | 3586 | intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) |
ecbc5cf3 JN |
3587 | { |
3588 | return 0; | |
3589 | } | |
6f9f4b7a | 3590 | static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) |
a0562819 VS |
3591 | { |
3592 | return -ENODEV; | |
3593 | } | |
65e082c9 | 3594 | #endif |
8ee1c3db | 3595 | |
723bfd70 JB |
3596 | /* intel_acpi.c */ |
3597 | #ifdef CONFIG_ACPI | |
3598 | extern void intel_register_dsm_handler(void); | |
3599 | extern void intel_unregister_dsm_handler(void); | |
3600 | #else | |
3601 | static inline void intel_register_dsm_handler(void) { return; } | |
3602 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3603 | #endif /* CONFIG_ACPI */ | |
3604 | ||
94b4f3ba CW |
3605 | /* intel_device_info.c */ |
3606 | static inline struct intel_device_info * | |
3607 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
3608 | { | |
3609 | return (struct intel_device_info *)&dev_priv->info; | |
3610 | } | |
3611 | ||
3612 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); | |
3613 | void intel_device_info_dump(struct drm_i915_private *dev_priv); | |
3614 | ||
79e53945 | 3615 | /* modesetting */ |
f817586c | 3616 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3617 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3618 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3619 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1ebaa0b9 | 3620 | extern int intel_connector_register(struct drm_connector *); |
c191eca1 | 3621 | extern void intel_connector_unregister(struct drm_connector *); |
28d52043 | 3622 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3623 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3624 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3625 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
91d14251 | 3626 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
dde86e2d | 3627 | extern void intel_init_pch_refclk(struct drm_device *dev); |
dc97997a | 3628 | extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val); |
5209b1f4 ID |
3629 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3630 | bool enable); | |
3bad0781 | 3631 | |
c0c7babc BW |
3632 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3633 | struct drm_file *file); | |
575155a9 | 3634 | |
6ef3d427 | 3635 | /* overlay */ |
c033666a CW |
3636 | extern struct intel_overlay_error_state * |
3637 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 MK |
3638 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3639 | struct intel_overlay_error_state *error); | |
c4a1d9e4 | 3640 | |
c033666a CW |
3641 | extern struct intel_display_error_state * |
3642 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 | 3643 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3644 | struct drm_device *dev, |
3645 | struct intel_display_error_state *error); | |
6ef3d427 | 3646 | |
151a49d0 TR |
3647 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3648 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3649 | |
3650 | /* intel_sideband.c */ | |
707b6e3d D |
3651 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3652 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3653 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3654 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3655 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3656 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3657 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3658 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3659 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3660 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3661 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3662 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3663 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3664 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3665 | enum intel_sbi_destination destination); | |
3666 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3667 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3668 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3669 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3670 | |
b7fa22d8 ACO |
3671 | /* intel_dpio_phy.c */ |
3672 | void chv_set_phy_signal_level(struct intel_encoder *encoder, | |
3673 | u32 deemph_reg_value, u32 margin_reg_value, | |
3674 | bool uniq_trans_scale); | |
844b2f9a ACO |
3675 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
3676 | bool reset); | |
419b1b7a | 3677 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); |
e7d2a717 ACO |
3678 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
3679 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
204970b5 | 3680 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); |
b7fa22d8 | 3681 | |
53d98725 ACO |
3682 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
3683 | u32 demph_reg_value, u32 preemph_reg_value, | |
3684 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
6da2e616 | 3685 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); |
5f68c275 | 3686 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
0f572ebe | 3687 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); |
53d98725 | 3688 | |
616bc820 VS |
3689 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3690 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3691 | |
0b274481 BW |
3692 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3693 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3694 | ||
3695 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3696 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3697 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3698 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3699 | ||
3700 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3701 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3702 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3703 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3704 | ||
698b3135 CW |
3705 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3706 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3707 | * an arbitrary delay between them. This can cause the hardware to | |
3708 | * act upon the intermediate value, possibly leading to corruption and | |
3709 | * machine death. You have been warned. | |
3710 | */ | |
0b274481 BW |
3711 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3712 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3713 | |
50877445 | 3714 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3715 | u32 upper, lower, old_upper, loop = 0; \ |
3716 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3717 | do { \ |
acd29f7b | 3718 | old_upper = upper; \ |
ee0a227b | 3719 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3720 | upper = I915_READ(upper_reg); \ |
3721 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3722 | (u64)upper << 32 | lower; }) |
50877445 | 3723 | |
cae5852d ZN |
3724 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3725 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3726 | ||
75aa3f63 VS |
3727 | #define __raw_read(x, s) \ |
3728 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3729 | i915_reg_t reg) \ |
75aa3f63 | 3730 | { \ |
f0f59a00 | 3731 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3732 | } |
3733 | ||
3734 | #define __raw_write(x, s) \ | |
3735 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3736 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3737 | { \ |
f0f59a00 | 3738 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3739 | } |
3740 | __raw_read(8, b) | |
3741 | __raw_read(16, w) | |
3742 | __raw_read(32, l) | |
3743 | __raw_read(64, q) | |
3744 | ||
3745 | __raw_write(8, b) | |
3746 | __raw_write(16, w) | |
3747 | __raw_write(32, l) | |
3748 | __raw_write(64, q) | |
3749 | ||
3750 | #undef __raw_read | |
3751 | #undef __raw_write | |
3752 | ||
a6111f7b CW |
3753 | /* These are untraced mmio-accessors that are only valid to be used inside |
3754 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3755 | * controlled. | |
3756 | * Think twice, and think again, before using these. | |
3757 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3758 | * intel_uncore_forcewake_irqunlock(). | |
3759 | */ | |
75aa3f63 VS |
3760 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3761 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
76f8421f | 3762 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) |
a6111f7b CW |
3763 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3764 | ||
55bc60db VS |
3765 | /* "Broadcast RGB" property */ |
3766 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3767 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3768 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3769 | |
f0f59a00 | 3770 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
766aa1c4 | 3771 | { |
666a4537 | 3772 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
766aa1c4 | 3773 | return VLV_VGACNTRL; |
92e23b99 SJ |
3774 | else if (INTEL_INFO(dev)->gen >= 5) |
3775 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3776 | else |
3777 | return VGACNTRL; | |
3778 | } | |
3779 | ||
df97729f ID |
3780 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3781 | { | |
3782 | unsigned long j = msecs_to_jiffies(m); | |
3783 | ||
3784 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3785 | } | |
3786 | ||
7bd0e226 DV |
3787 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3788 | { | |
3789 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3790 | } | |
3791 | ||
df97729f ID |
3792 | static inline unsigned long |
3793 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3794 | { | |
3795 | unsigned long j = timespec_to_jiffies(value); | |
3796 | ||
3797 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3798 | } | |
3799 | ||
dce56b3c PZ |
3800 | /* |
3801 | * If you need to wait X milliseconds between events A and B, but event B | |
3802 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3803 | * when event A happened, then just before event B you call this function and | |
3804 | * pass the timestamp as the first argument, and X as the second argument. | |
3805 | */ | |
3806 | static inline void | |
3807 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3808 | { | |
ec5e0cfb | 3809 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3810 | |
3811 | /* | |
3812 | * Don't re-read the value of "jiffies" every time since it may change | |
3813 | * behind our back and break the math. | |
3814 | */ | |
3815 | tmp_jiffies = jiffies; | |
3816 | target_jiffies = timestamp_jiffies + | |
3817 | msecs_to_jiffies_timeout(to_wait_ms); | |
3818 | ||
3819 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3820 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3821 | while (remaining_jiffies) | |
3822 | remaining_jiffies = | |
3823 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3824 | } |
3825 | } | |
688e6c72 CW |
3826 | static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req) |
3827 | { | |
f69a02c9 CW |
3828 | struct intel_engine_cs *engine = req->engine; |
3829 | ||
7ec2c73b CW |
3830 | /* Before we do the heavier coherent read of the seqno, |
3831 | * check the value (hopefully) in the CPU cacheline. | |
3832 | */ | |
3833 | if (i915_gem_request_completed(req)) | |
3834 | return true; | |
3835 | ||
688e6c72 CW |
3836 | /* Ensure our read of the seqno is coherent so that we |
3837 | * do not "miss an interrupt" (i.e. if this is the last | |
3838 | * request and the seqno write from the GPU is not visible | |
3839 | * by the time the interrupt fires, we will see that the | |
3840 | * request is incomplete and go back to sleep awaiting | |
3841 | * another interrupt that will never come.) | |
3842 | * | |
3843 | * Strictly, we only need to do this once after an interrupt, | |
3844 | * but it is easier and safer to do it every time the waiter | |
3845 | * is woken. | |
3846 | */ | |
3d5564e9 | 3847 | if (engine->irq_seqno_barrier && |
dbd6ef29 | 3848 | rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current && |
aca34b6e | 3849 | cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) { |
99fe4a5f CW |
3850 | struct task_struct *tsk; |
3851 | ||
3d5564e9 CW |
3852 | /* The ordering of irq_posted versus applying the barrier |
3853 | * is crucial. The clearing of the current irq_posted must | |
3854 | * be visible before we perform the barrier operation, | |
3855 | * such that if a subsequent interrupt arrives, irq_posted | |
3856 | * is reasserted and our task rewoken (which causes us to | |
3857 | * do another __i915_request_irq_complete() immediately | |
3858 | * and reapply the barrier). Conversely, if the clear | |
3859 | * occurs after the barrier, then an interrupt that arrived | |
3860 | * whilst we waited on the barrier would not trigger a | |
3861 | * barrier on the next pass, and the read may not see the | |
3862 | * seqno update. | |
3863 | */ | |
f69a02c9 | 3864 | engine->irq_seqno_barrier(engine); |
99fe4a5f CW |
3865 | |
3866 | /* If we consume the irq, but we are no longer the bottom-half, | |
3867 | * the real bottom-half may not have serialised their own | |
3868 | * seqno check with the irq-barrier (i.e. may have inspected | |
3869 | * the seqno before we believe it coherent since they see | |
3870 | * irq_posted == false but we are still running). | |
3871 | */ | |
3872 | rcu_read_lock(); | |
dbd6ef29 | 3873 | tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh); |
99fe4a5f CW |
3874 | if (tsk && tsk != current) |
3875 | /* Note that if the bottom-half is changed as we | |
3876 | * are sending the wake-up, the new bottom-half will | |
3877 | * be woken by whomever made the change. We only have | |
3878 | * to worry about when we steal the irq-posted for | |
3879 | * ourself. | |
3880 | */ | |
3881 | wake_up_process(tsk); | |
3882 | rcu_read_unlock(); | |
3883 | ||
7ec2c73b CW |
3884 | if (i915_gem_request_completed(req)) |
3885 | return true; | |
3886 | } | |
688e6c72 CW |
3887 | |
3888 | /* We need to check whether any gpu reset happened in between | |
3889 | * the request being submitted and now. If a reset has occurred, | |
3890 | * the seqno will have been advance past ours and our request | |
3891 | * is complete. If we are in the process of handling a reset, | |
3892 | * the request is effectively complete as the rendering will | |
3893 | * be discarded, but we need to return in order to drop the | |
3894 | * struct_mutex. | |
3895 | */ | |
3896 | if (i915_reset_in_progress(&req->i915->gpu_error)) | |
3897 | return true; | |
3898 | ||
3899 | return false; | |
3900 | } | |
3901 | ||
1da177e4 | 3902 | #endif |