Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
ba4f01a3 | 35 | #include "i915_trace.h" |
8187a2b7 | 36 | #include "intel_ringbuffer.h" |
0839ccb8 | 37 | #include <linux/io-mapping.h> |
f899fc64 | 38 | #include <linux/i2c.h> |
0ade6386 | 39 | #include <drm/intel-gtt.h> |
585fb111 | 40 | |
1da177e4 LT |
41 | /* General customization: |
42 | */ | |
43 | ||
44 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
45 | ||
46 | #define DRIVER_NAME "i915" | |
47 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 48 | #define DRIVER_DATE "20080730" |
1da177e4 | 49 | |
317c35d1 JB |
50 | enum pipe { |
51 | PIPE_A = 0, | |
52 | PIPE_B, | |
53 | }; | |
54 | ||
80824003 JB |
55 | enum plane { |
56 | PLANE_A = 0, | |
57 | PLANE_B, | |
58 | }; | |
59 | ||
52440211 KP |
60 | #define I915_NUM_PIPE 2 |
61 | ||
62fdfeaf EA |
62 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
63 | ||
1da177e4 LT |
64 | /* Interface history: |
65 | * | |
66 | * 1.1: Original. | |
0d6aa60b DA |
67 | * 1.2: Add Power Management |
68 | * 1.3: Add vblank support | |
de227f5f | 69 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 70 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
71 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
72 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
73 | */ |
74 | #define DRIVER_MAJOR 1 | |
2228ed67 | 75 | #define DRIVER_MINOR 6 |
1da177e4 LT |
76 | #define DRIVER_PATCHLEVEL 0 |
77 | ||
673a394b | 78 | #define WATCH_COHERENCY 0 |
673a394b | 79 | #define WATCH_EXEC 0 |
673a394b | 80 | #define WATCH_RELOC 0 |
23bc5982 | 81 | #define WATCH_LISTS 0 |
673a394b EA |
82 | #define WATCH_PWRITE 0 |
83 | ||
71acb5eb DA |
84 | #define I915_GEM_PHYS_CURSOR_0 1 |
85 | #define I915_GEM_PHYS_CURSOR_1 2 | |
86 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
87 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
88 | ||
89 | struct drm_i915_gem_phys_object { | |
90 | int id; | |
91 | struct page **page_list; | |
92 | drm_dma_handle_t *handle; | |
93 | struct drm_gem_object *cur_obj; | |
94 | }; | |
95 | ||
1da177e4 LT |
96 | struct mem_block { |
97 | struct mem_block *next; | |
98 | struct mem_block *prev; | |
99 | int start; | |
100 | int size; | |
6c340eac | 101 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
102 | }; |
103 | ||
0a3e67a4 JB |
104 | struct opregion_header; |
105 | struct opregion_acpi; | |
106 | struct opregion_swsci; | |
107 | struct opregion_asle; | |
108 | ||
8ee1c3db MG |
109 | struct intel_opregion { |
110 | struct opregion_header *header; | |
111 | struct opregion_acpi *acpi; | |
112 | struct opregion_swsci *swsci; | |
113 | struct opregion_asle *asle; | |
44834a67 | 114 | void *vbt; |
8ee1c3db | 115 | }; |
44834a67 | 116 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 117 | |
6ef3d427 CW |
118 | struct intel_overlay; |
119 | struct intel_overlay_error_state; | |
120 | ||
7c1c2871 DA |
121 | struct drm_i915_master_private { |
122 | drm_local_map_t *sarea; | |
123 | struct _drm_i915_sarea *sarea_priv; | |
124 | }; | |
de151cf6 JB |
125 | #define I915_FENCE_REG_NONE -1 |
126 | ||
127 | struct drm_i915_fence_reg { | |
128 | struct drm_gem_object *obj; | |
007cc8ac | 129 | struct list_head lru_list; |
53640e1d | 130 | bool gpu; |
de151cf6 | 131 | }; |
7c1c2871 | 132 | |
9b9d172d | 133 | struct sdvo_device_mapping { |
e957d772 | 134 | u8 initialized; |
9b9d172d | 135 | u8 dvo_port; |
136 | u8 slave_addr; | |
137 | u8 dvo_wiring; | |
e957d772 CW |
138 | u8 i2c_pin; |
139 | u8 i2c_speed; | |
b1083333 | 140 | u8 ddc_pin; |
9b9d172d | 141 | }; |
142 | ||
c4a1d9e4 CW |
143 | struct intel_display_error_state; |
144 | ||
63eeaf38 JB |
145 | struct drm_i915_error_state { |
146 | u32 eir; | |
147 | u32 pgtbl_er; | |
148 | u32 pipeastat; | |
149 | u32 pipebstat; | |
150 | u32 ipeir; | |
151 | u32 ipehr; | |
152 | u32 instdone; | |
153 | u32 acthd; | |
1d8f38f4 CW |
154 | u32 error; /* gen6+ */ |
155 | u32 bcs_acthd; /* gen6+ blt engine */ | |
156 | u32 bcs_ipehr; | |
157 | u32 bcs_ipeir; | |
158 | u32 bcs_instdone; | |
159 | u32 bcs_seqno; | |
add354dd CW |
160 | u32 vcs_acthd; /* gen6+ bsd engine */ |
161 | u32 vcs_ipehr; | |
162 | u32 vcs_ipeir; | |
163 | u32 vcs_instdone; | |
164 | u32 vcs_seqno; | |
63eeaf38 JB |
165 | u32 instpm; |
166 | u32 instps; | |
167 | u32 instdone1; | |
168 | u32 seqno; | |
9df30794 | 169 | u64 bbaddr; |
63eeaf38 | 170 | struct timeval time; |
9df30794 CW |
171 | struct drm_i915_error_object { |
172 | int page_count; | |
173 | u32 gtt_offset; | |
174 | u32 *pages[0]; | |
175 | } *ringbuffer, *batchbuffer[2]; | |
176 | struct drm_i915_error_buffer { | |
177 | size_t size; | |
178 | u32 name; | |
179 | u32 seqno; | |
180 | u32 gtt_offset; | |
181 | u32 read_domains; | |
182 | u32 write_domain; | |
183 | u32 fence_reg; | |
184 | s32 pinned:2; | |
185 | u32 tiling:2; | |
186 | u32 dirty:1; | |
187 | u32 purgeable:1; | |
e5c65260 | 188 | u32 ring:4; |
c724e8a9 CW |
189 | } *active_bo, *pinned_bo; |
190 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 191 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 192 | struct intel_display_error_state *display; |
63eeaf38 JB |
193 | }; |
194 | ||
e70236a8 JB |
195 | struct drm_i915_display_funcs { |
196 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 197 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
198 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
199 | void (*disable_fbc)(struct drm_device *dev); | |
200 | int (*get_display_clock_speed)(struct drm_device *dev); | |
201 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
202 | void (*update_wm)(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
203 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
204 | int pixel_size); | |
e70236a8 JB |
205 | /* clock updates for mode set */ |
206 | /* cursor updates */ | |
207 | /* render clock increase/decrease */ | |
208 | /* display clock increase/decrease */ | |
209 | /* pll clock increase/decrease */ | |
210 | /* clock gating init */ | |
211 | }; | |
212 | ||
cfdf1fa2 | 213 | struct intel_device_info { |
c96c3a8c | 214 | u8 gen; |
cfdf1fa2 | 215 | u8 is_mobile : 1; |
5ce8ba7c | 216 | u8 is_i85x : 1; |
cfdf1fa2 | 217 | u8 is_i915g : 1; |
cfdf1fa2 | 218 | u8 is_i945gm : 1; |
cfdf1fa2 KH |
219 | u8 is_g33 : 1; |
220 | u8 need_gfx_hws : 1; | |
221 | u8 is_g4x : 1; | |
222 | u8 is_pineview : 1; | |
534843da CW |
223 | u8 is_broadwater : 1; |
224 | u8 is_crestline : 1; | |
cfdf1fa2 KH |
225 | u8 has_fbc : 1; |
226 | u8 has_rc6 : 1; | |
227 | u8 has_pipe_cxsr : 1; | |
228 | u8 has_hotplug : 1; | |
b295d1b6 | 229 | u8 cursor_needs_physical : 1; |
31578148 CW |
230 | u8 has_overlay : 1; |
231 | u8 overlay_needs_physical : 1; | |
a6c45cf0 | 232 | u8 supports_tv : 1; |
92f49d9c | 233 | u8 has_bsd_ring : 1; |
549f7365 | 234 | u8 has_blt_ring : 1; |
cfdf1fa2 KH |
235 | }; |
236 | ||
b5e50c3f | 237 | enum no_fbc_reason { |
bed4a673 | 238 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
239 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
240 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
241 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
242 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
243 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 244 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
b5e50c3f JB |
245 | }; |
246 | ||
3bad0781 ZW |
247 | enum intel_pch { |
248 | PCH_IBX, /* Ibexpeak PCH */ | |
249 | PCH_CPT, /* Cougarpoint PCH */ | |
250 | }; | |
251 | ||
b690e96c JB |
252 | #define QUIRK_PIPEA_FORCE (1<<0) |
253 | ||
8be48d92 | 254 | struct intel_fbdev; |
38651674 | 255 | |
1da177e4 | 256 | typedef struct drm_i915_private { |
673a394b EA |
257 | struct drm_device *dev; |
258 | ||
cfdf1fa2 KH |
259 | const struct intel_device_info *info; |
260 | ||
ac5c4e76 DA |
261 | int has_gem; |
262 | ||
3043c60c | 263 | void __iomem *regs; |
1da177e4 | 264 | |
f899fc64 CW |
265 | struct intel_gmbus { |
266 | struct i2c_adapter adapter; | |
e957d772 CW |
267 | struct i2c_adapter *force_bit; |
268 | u32 reg0; | |
f899fc64 CW |
269 | } *gmbus; |
270 | ||
ec2a4c3f | 271 | struct pci_dev *bridge_dev; |
8187a2b7 | 272 | struct intel_ring_buffer render_ring; |
d1b851fc | 273 | struct intel_ring_buffer bsd_ring; |
549f7365 | 274 | struct intel_ring_buffer blt_ring; |
6f392d54 | 275 | uint32_t next_seqno; |
1da177e4 | 276 | |
9c8da5eb | 277 | drm_dma_handle_t *status_page_dmah; |
e552eb70 | 278 | void *seqno_page; |
1da177e4 | 279 | dma_addr_t dma_status_page; |
0a3e67a4 | 280 | uint32_t counter; |
e552eb70 | 281 | unsigned int seqno_gfx_addr; |
dc7a9319 | 282 | drm_local_map_t hws_map; |
e552eb70 | 283 | struct drm_gem_object *seqno_obj; |
97f5ab66 | 284 | struct drm_gem_object *pwrctx; |
aa40d6bb | 285 | struct drm_gem_object *renderctx; |
1da177e4 | 286 | |
d7658989 JB |
287 | struct resource mch_res; |
288 | ||
a6b54f3f | 289 | unsigned int cpp; |
1da177e4 LT |
290 | int back_offset; |
291 | int front_offset; | |
292 | int current_page; | |
293 | int page_flipping; | |
1da177e4 | 294 | |
1da177e4 | 295 | atomic_t irq_received; |
ed4cb414 EA |
296 | /** Protects user_irq_refcount and irq_mask_reg */ |
297 | spinlock_t user_irq_lock; | |
9d34e5db | 298 | u32 trace_irq_seqno; |
ed4cb414 EA |
299 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
300 | u32 irq_mask_reg; | |
7c463586 | 301 | u32 pipestat[2]; |
f2b115e6 | 302 | /** splitted irq regs for graphics and display engine on Ironlake, |
036a4a7d ZW |
303 | irq_mask_reg is still used for display irq. */ |
304 | u32 gt_irq_mask_reg; | |
305 | u32 gt_irq_enable_reg; | |
306 | u32 de_irq_enable_reg; | |
c650156a ZW |
307 | u32 pch_irq_mask_reg; |
308 | u32 pch_irq_enable_reg; | |
1da177e4 | 309 | |
5ca58282 JB |
310 | u32 hotplug_supported_mask; |
311 | struct work_struct hotplug_work; | |
312 | ||
1da177e4 LT |
313 | int tex_lru_log_granularity; |
314 | int allow_batchbuffer; | |
315 | struct mem_block *agp_heap; | |
0d6aa60b | 316 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 317 | int vblank_pipe; |
a3524f1b | 318 | int num_pipe; |
a6b54f3f | 319 | |
f65d9421 | 320 | /* For hangcheck timer */ |
b3b079db | 321 | #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */ |
f65d9421 BG |
322 | struct timer_list hangcheck_timer; |
323 | int hangcheck_count; | |
324 | uint32_t last_acthd; | |
cbb465e7 CW |
325 | uint32_t last_instdone; |
326 | uint32_t last_instdone1; | |
f65d9421 | 327 | |
80824003 JB |
328 | unsigned long cfb_size; |
329 | unsigned long cfb_pitch; | |
bed4a673 | 330 | unsigned long cfb_offset; |
80824003 JB |
331 | int cfb_fence; |
332 | int cfb_plane; | |
bed4a673 | 333 | int cfb_y; |
80824003 | 334 | |
79e53945 JB |
335 | int irq_enabled; |
336 | ||
8ee1c3db MG |
337 | struct intel_opregion opregion; |
338 | ||
02e792fb DV |
339 | /* overlay */ |
340 | struct intel_overlay *overlay; | |
341 | ||
79e53945 | 342 | /* LVDS info */ |
a9573556 | 343 | int backlight_level; /* restore backlight to this value */ |
79e53945 | 344 | struct drm_display_mode *panel_fixed_mode; |
88631706 ML |
345 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
346 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
347 | |
348 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
349 | unsigned int int_tv_support:1; |
350 | unsigned int lvds_dither:1; | |
351 | unsigned int lvds_vbt:1; | |
352 | unsigned int int_crt_support:1; | |
43565a06 KH |
353 | unsigned int lvds_use_ssc:1; |
354 | int lvds_ssc_freq; | |
5ceb0f9b | 355 | struct { |
9f0e7ff4 JB |
356 | int rate; |
357 | int lanes; | |
358 | int preemphasis; | |
359 | int vswing; | |
360 | ||
361 | bool initialized; | |
362 | bool support; | |
363 | int bpp; | |
364 | struct edp_power_seq pps; | |
5ceb0f9b | 365 | } edp; |
89667383 | 366 | bool no_aux_handshake; |
79e53945 | 367 | |
c1c7af60 JB |
368 | struct notifier_block lid_notifier; |
369 | ||
f899fc64 | 370 | int crt_ddc_pin; |
de151cf6 JB |
371 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
372 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
373 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
374 | ||
95534263 | 375 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 376 | |
63eeaf38 JB |
377 | spinlock_t error_lock; |
378 | struct drm_i915_error_state *first_error; | |
8a905236 | 379 | struct work_struct error_work; |
30dbf0c0 | 380 | struct completion error_completion; |
9c9fe1f8 | 381 | struct workqueue_struct *wq; |
63eeaf38 | 382 | |
e70236a8 JB |
383 | /* Display functions */ |
384 | struct drm_i915_display_funcs display; | |
385 | ||
3bad0781 ZW |
386 | /* PCH chipset type */ |
387 | enum intel_pch pch_type; | |
388 | ||
b690e96c JB |
389 | unsigned long quirks; |
390 | ||
ba8bbcf6 | 391 | /* Register state */ |
c9354c85 | 392 | bool modeset_on_lid; |
ba8bbcf6 JB |
393 | u8 saveLBB; |
394 | u32 saveDSPACNTR; | |
395 | u32 saveDSPBCNTR; | |
e948e994 | 396 | u32 saveDSPARB; |
461cba2d | 397 | u32 saveHWS; |
ba8bbcf6 JB |
398 | u32 savePIPEACONF; |
399 | u32 savePIPEBCONF; | |
400 | u32 savePIPEASRC; | |
401 | u32 savePIPEBSRC; | |
402 | u32 saveFPA0; | |
403 | u32 saveFPA1; | |
404 | u32 saveDPLL_A; | |
405 | u32 saveDPLL_A_MD; | |
406 | u32 saveHTOTAL_A; | |
407 | u32 saveHBLANK_A; | |
408 | u32 saveHSYNC_A; | |
409 | u32 saveVTOTAL_A; | |
410 | u32 saveVBLANK_A; | |
411 | u32 saveVSYNC_A; | |
412 | u32 saveBCLRPAT_A; | |
5586c8bc | 413 | u32 saveTRANSACONF; |
42048781 ZW |
414 | u32 saveTRANS_HTOTAL_A; |
415 | u32 saveTRANS_HBLANK_A; | |
416 | u32 saveTRANS_HSYNC_A; | |
417 | u32 saveTRANS_VTOTAL_A; | |
418 | u32 saveTRANS_VBLANK_A; | |
419 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 420 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
421 | u32 saveDSPASTRIDE; |
422 | u32 saveDSPASIZE; | |
423 | u32 saveDSPAPOS; | |
585fb111 | 424 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
425 | u32 saveDSPASURF; |
426 | u32 saveDSPATILEOFF; | |
427 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 428 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
429 | u32 saveBLC_PWM_CTL; |
430 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
431 | u32 saveBLC_CPU_PWM_CTL; |
432 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
433 | u32 saveFPB0; |
434 | u32 saveFPB1; | |
435 | u32 saveDPLL_B; | |
436 | u32 saveDPLL_B_MD; | |
437 | u32 saveHTOTAL_B; | |
438 | u32 saveHBLANK_B; | |
439 | u32 saveHSYNC_B; | |
440 | u32 saveVTOTAL_B; | |
441 | u32 saveVBLANK_B; | |
442 | u32 saveVSYNC_B; | |
443 | u32 saveBCLRPAT_B; | |
5586c8bc | 444 | u32 saveTRANSBCONF; |
42048781 ZW |
445 | u32 saveTRANS_HTOTAL_B; |
446 | u32 saveTRANS_HBLANK_B; | |
447 | u32 saveTRANS_HSYNC_B; | |
448 | u32 saveTRANS_VTOTAL_B; | |
449 | u32 saveTRANS_VBLANK_B; | |
450 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 451 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
452 | u32 saveDSPBSTRIDE; |
453 | u32 saveDSPBSIZE; | |
454 | u32 saveDSPBPOS; | |
585fb111 | 455 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
456 | u32 saveDSPBSURF; |
457 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
458 | u32 saveVGA0; |
459 | u32 saveVGA1; | |
460 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
461 | u32 saveVGACNTRL; |
462 | u32 saveADPA; | |
463 | u32 saveLVDS; | |
585fb111 JB |
464 | u32 savePP_ON_DELAYS; |
465 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
466 | u32 saveDVOA; |
467 | u32 saveDVOB; | |
468 | u32 saveDVOC; | |
469 | u32 savePP_ON; | |
470 | u32 savePP_OFF; | |
471 | u32 savePP_CONTROL; | |
585fb111 | 472 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
473 | u32 savePFIT_CONTROL; |
474 | u32 save_palette_a[256]; | |
475 | u32 save_palette_b[256]; | |
06027f91 | 476 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
477 | u32 saveFBC_CFB_BASE; |
478 | u32 saveFBC_LL_BASE; | |
479 | u32 saveFBC_CONTROL; | |
480 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
481 | u32 saveIER; |
482 | u32 saveIIR; | |
483 | u32 saveIMR; | |
42048781 ZW |
484 | u32 saveDEIER; |
485 | u32 saveDEIMR; | |
486 | u32 saveGTIER; | |
487 | u32 saveGTIMR; | |
488 | u32 saveFDI_RXA_IMR; | |
489 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 490 | u32 saveCACHE_MODE_0; |
1f84e550 | 491 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
492 | u32 saveSWF0[16]; |
493 | u32 saveSWF1[16]; | |
494 | u32 saveSWF2[3]; | |
495 | u8 saveMSR; | |
496 | u8 saveSR[8]; | |
123f794f | 497 | u8 saveGR[25]; |
ba8bbcf6 | 498 | u8 saveAR_INDEX; |
a59e122a | 499 | u8 saveAR[21]; |
ba8bbcf6 | 500 | u8 saveDACMASK; |
a59e122a | 501 | u8 saveCR[37]; |
79f11c19 | 502 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
503 | u32 saveCURACNTR; |
504 | u32 saveCURAPOS; | |
505 | u32 saveCURABASE; | |
506 | u32 saveCURBCNTR; | |
507 | u32 saveCURBPOS; | |
508 | u32 saveCURBBASE; | |
509 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
510 | u32 saveDP_B; |
511 | u32 saveDP_C; | |
512 | u32 saveDP_D; | |
513 | u32 savePIPEA_GMCH_DATA_M; | |
514 | u32 savePIPEB_GMCH_DATA_M; | |
515 | u32 savePIPEA_GMCH_DATA_N; | |
516 | u32 savePIPEB_GMCH_DATA_N; | |
517 | u32 savePIPEA_DP_LINK_M; | |
518 | u32 savePIPEB_DP_LINK_M; | |
519 | u32 savePIPEA_DP_LINK_N; | |
520 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
521 | u32 saveFDI_RXA_CTL; |
522 | u32 saveFDI_TXA_CTL; | |
523 | u32 saveFDI_RXB_CTL; | |
524 | u32 saveFDI_TXB_CTL; | |
525 | u32 savePFA_CTL_1; | |
526 | u32 savePFB_CTL_1; | |
527 | u32 savePFA_WIN_SZ; | |
528 | u32 savePFB_WIN_SZ; | |
529 | u32 savePFA_WIN_POS; | |
530 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
531 | u32 savePCH_DREF_CONTROL; |
532 | u32 saveDISP_ARB_CTL; | |
533 | u32 savePIPEA_DATA_M1; | |
534 | u32 savePIPEA_DATA_N1; | |
535 | u32 savePIPEA_LINK_M1; | |
536 | u32 savePIPEA_LINK_N1; | |
537 | u32 savePIPEB_DATA_M1; | |
538 | u32 savePIPEB_DATA_N1; | |
539 | u32 savePIPEB_LINK_M1; | |
540 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 541 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
542 | |
543 | struct { | |
19966754 DV |
544 | /** Bridge to intel-gtt-ko */ |
545 | struct intel_gtt *gtt; | |
546 | /** Memory allocator for GTT stolen memory */ | |
547 | struct drm_mm vram; | |
548 | /** Memory allocator for GTT */ | |
673a394b | 549 | struct drm_mm gtt_space; |
a6e0aa42 DV |
550 | /** End of mappable part of GTT */ |
551 | unsigned long gtt_mappable_end; | |
673a394b | 552 | |
0839ccb8 | 553 | struct io_mapping *gtt_mapping; |
ab657db1 | 554 | int gtt_mtrr; |
0839ccb8 | 555 | |
17250b71 | 556 | struct shrinker inactive_shrinker; |
31169714 | 557 | |
69dc4987 CW |
558 | /** |
559 | * List of objects currently involved in rendering. | |
560 | * | |
561 | * Includes buffers having the contents of their GPU caches | |
562 | * flushed, not necessarily primitives. last_rendering_seqno | |
563 | * represents when the rendering involved will be completed. | |
564 | * | |
565 | * A reference is held on the buffer while on this list. | |
566 | */ | |
567 | struct list_head active_list; | |
568 | ||
673a394b EA |
569 | /** |
570 | * List of objects which are not in the ringbuffer but which | |
571 | * still have a write_domain which needs to be flushed before | |
572 | * unbinding. | |
573 | * | |
ce44b0ea EA |
574 | * last_rendering_seqno is 0 while an object is in this list. |
575 | * | |
673a394b EA |
576 | * A reference is held on the buffer while on this list. |
577 | */ | |
578 | struct list_head flushing_list; | |
579 | ||
580 | /** | |
581 | * LRU list of objects which are not in the ringbuffer and | |
582 | * are ready to unbind, but are still in the GTT. | |
583 | * | |
ce44b0ea EA |
584 | * last_rendering_seqno is 0 while an object is in this list. |
585 | * | |
673a394b EA |
586 | * A reference is not held on the buffer while on this list, |
587 | * as merely being GTT-bound shouldn't prevent its being | |
588 | * freed, and we'll pull it off the list in the free path. | |
589 | */ | |
590 | struct list_head inactive_list; | |
591 | ||
f13d3f73 CW |
592 | /** |
593 | * LRU list of objects which are not in the ringbuffer but | |
594 | * are still pinned in the GTT. | |
595 | */ | |
596 | struct list_head pinned_list; | |
597 | ||
a09ba7fa EA |
598 | /** LRU list of objects with fence regs on them. */ |
599 | struct list_head fence_list; | |
600 | ||
be72615b CW |
601 | /** |
602 | * List of objects currently pending being freed. | |
603 | * | |
604 | * These objects are no longer in use, but due to a signal | |
605 | * we were prevented from freeing them at the appointed time. | |
606 | */ | |
607 | struct list_head deferred_free_list; | |
608 | ||
673a394b EA |
609 | /** |
610 | * We leave the user IRQ off as much as possible, | |
611 | * but this means that requests will finish and never | |
612 | * be retired once the system goes idle. Set a timer to | |
613 | * fire periodically while the ring is running. When it | |
614 | * fires, go retire requests. | |
615 | */ | |
616 | struct delayed_work retire_work; | |
617 | ||
673a394b EA |
618 | /** |
619 | * Flag if the X Server, and thus DRM, is not currently in | |
620 | * control of the device. | |
621 | * | |
622 | * This is set between LeaveVT and EnterVT. It needs to be | |
623 | * replaced with a semaphore. It also needs to be | |
624 | * transitioned away from for kernel modesetting. | |
625 | */ | |
626 | int suspended; | |
627 | ||
628 | /** | |
629 | * Flag if the hardware appears to be wedged. | |
630 | * | |
631 | * This is set when attempts to idle the device timeout. | |
632 | * It prevents command submission from occuring and makes | |
633 | * every pending request fail | |
634 | */ | |
ba1234d1 | 635 | atomic_t wedged; |
673a394b EA |
636 | |
637 | /** Bit 6 swizzling required for X tiling */ | |
638 | uint32_t bit_6_swizzle_x; | |
639 | /** Bit 6 swizzling required for Y tiling */ | |
640 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
641 | |
642 | /* storage for physical objects */ | |
643 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 644 | |
73aa808f CW |
645 | /* accounting, useful for userland debugging */ |
646 | size_t object_memory; | |
647 | size_t pin_memory; | |
648 | size_t gtt_memory; | |
fb7d516a DV |
649 | size_t gtt_mappable_memory; |
650 | size_t mappable_gtt_used; | |
651 | size_t mappable_gtt_total; | |
73aa808f CW |
652 | size_t gtt_total; |
653 | u32 object_count; | |
654 | u32 pin_count; | |
fb7d516a | 655 | u32 gtt_mappable_count; |
73aa808f | 656 | u32 gtt_count; |
673a394b | 657 | } mm; |
9b9d172d | 658 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
659 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
660 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
661 | /* Panel fitter placement and size for Ironlake+ */ |
662 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 663 | |
6b95a207 KH |
664 | struct drm_crtc *plane_to_crtc_mapping[2]; |
665 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
666 | wait_queue_head_t pending_flip_queue; | |
1afe3e9d | 667 | bool flip_pending_is_done; |
6b95a207 | 668 | |
652c393a JB |
669 | /* Reclocking support */ |
670 | bool render_reclock_avail; | |
671 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
672 | /* indicates the reduced downclock for LVDS*/ |
673 | int lvds_downclock; | |
652c393a JB |
674 | struct work_struct idle_work; |
675 | struct timer_list idle_timer; | |
676 | bool busy; | |
677 | u16 orig_clock; | |
6363ee6f ZY |
678 | int child_dev_num; |
679 | struct child_device_config *child_dev; | |
a2565377 | 680 | struct drm_connector *int_lvds_connector; |
f97108d1 | 681 | |
c4804411 | 682 | bool mchbar_need_disable; |
f97108d1 JB |
683 | |
684 | u8 cur_delay; | |
685 | u8 min_delay; | |
686 | u8 max_delay; | |
7648fa99 JB |
687 | u8 fmax; |
688 | u8 fstart; | |
689 | ||
690 | u64 last_count1; | |
691 | unsigned long last_time1; | |
692 | u64 last_count2; | |
693 | struct timespec last_time2; | |
694 | unsigned long gfx_power; | |
695 | int c_m; | |
696 | int r_t; | |
697 | u8 corr; | |
698 | spinlock_t *mchdev_lock; | |
b5e50c3f JB |
699 | |
700 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 701 | |
20bf377e JB |
702 | struct drm_mm_node *compressed_fb; |
703 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 704 | |
ae681d96 CW |
705 | unsigned long last_gpu_reset; |
706 | ||
8be48d92 DA |
707 | /* list of fbdev register on this device */ |
708 | struct intel_fbdev *fbdev; | |
1da177e4 LT |
709 | } drm_i915_private_t; |
710 | ||
673a394b EA |
711 | /** driver private structure attached to each drm_gem_object */ |
712 | struct drm_i915_gem_object { | |
c397b908 | 713 | struct drm_gem_object base; |
673a394b EA |
714 | |
715 | /** Current space allocated to this object in the GTT, if any. */ | |
716 | struct drm_mm_node *gtt_space; | |
717 | ||
718 | /** This object's place on the active/flushing/inactive lists */ | |
69dc4987 CW |
719 | struct list_head ring_list; |
720 | struct list_head mm_list; | |
99fcb766 DV |
721 | /** This object's place on GPU write list */ |
722 | struct list_head gpu_write_list; | |
cd377ea9 CW |
723 | /** This object's place on eviction list */ |
724 | struct list_head evict_list; | |
673a394b EA |
725 | |
726 | /** | |
727 | * This is set if the object is on the active or flushing lists | |
728 | * (has pending rendering), and is not set if it's on inactive (ready | |
729 | * to be unbound). | |
730 | */ | |
778c3544 | 731 | unsigned int active : 1; |
673a394b EA |
732 | |
733 | /** | |
734 | * This is set if the object has been written to since last bound | |
735 | * to the GTT | |
736 | */ | |
778c3544 DV |
737 | unsigned int dirty : 1; |
738 | ||
739 | /** | |
740 | * Fence register bits (if any) for this object. Will be set | |
741 | * as needed when mapped into the GTT. | |
742 | * Protected by dev->struct_mutex. | |
743 | * | |
744 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) | |
745 | */ | |
11824e8c | 746 | signed int fence_reg : 5; |
778c3544 DV |
747 | |
748 | /** | |
749 | * Used for checking the object doesn't appear more than once | |
750 | * in an execbuffer object list. | |
751 | */ | |
752 | unsigned int in_execbuffer : 1; | |
753 | ||
754 | /** | |
755 | * Advice: are the backing pages purgeable? | |
756 | */ | |
757 | unsigned int madv : 2; | |
758 | ||
778c3544 DV |
759 | /** |
760 | * Current tiling mode for the object. | |
761 | */ | |
762 | unsigned int tiling_mode : 2; | |
763 | ||
764 | /** How many users have pinned this object in GTT space. The following | |
765 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
766 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
767 | * times for the same batchbuffer), and the framebuffer code. When | |
768 | * switching/pageflipping, the framebuffer code has at most two buffers | |
769 | * pinned per crtc. | |
770 | * | |
771 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
772 | * bits with absolutely no headroom. So use 4 bits. */ | |
11824e8c | 773 | unsigned int pin_count : 4; |
778c3544 | 774 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 775 | |
75e9e915 DV |
776 | /** |
777 | * Is the object at the current location in the gtt mappable and | |
778 | * fenceable? Used to avoid costly recalculations. | |
779 | */ | |
780 | unsigned int map_and_fenceable : 1; | |
781 | ||
fb7d516a DV |
782 | /** |
783 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
784 | * mappable by accident). Track pin and fault separate for a more | |
785 | * accurate mappable working set. | |
786 | */ | |
787 | unsigned int fault_mappable : 1; | |
788 | unsigned int pin_mappable : 1; | |
789 | ||
673a394b EA |
790 | /** AGP memory structure for our GTT binding. */ |
791 | DRM_AGP_MEM *agp_mem; | |
792 | ||
856fa198 | 793 | struct page **pages; |
673a394b EA |
794 | |
795 | /** | |
796 | * Current offset of the object in GTT space. | |
797 | * | |
798 | * This is the same as gtt_space->start | |
799 | */ | |
800 | uint32_t gtt_offset; | |
e67b8ce1 | 801 | |
852835f3 ZN |
802 | /* Which ring is refering to is this object */ |
803 | struct intel_ring_buffer *ring; | |
804 | ||
673a394b EA |
805 | /** Breadcrumb of last rendering to the buffer. */ |
806 | uint32_t last_rendering_seqno; | |
807 | ||
778c3544 | 808 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 809 | uint32_t stride; |
673a394b | 810 | |
280b713b | 811 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 812 | unsigned long *bit_17; |
280b713b | 813 | |
ba1eb1d8 KP |
814 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
815 | uint32_t agp_type; | |
816 | ||
673a394b | 817 | /** |
e47c68e9 EA |
818 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
819 | * flags which individual pages are valid. | |
673a394b EA |
820 | */ |
821 | uint8_t *page_cpu_valid; | |
79e53945 JB |
822 | |
823 | /** User space pin count and filp owning the pin */ | |
824 | uint32_t user_pin_count; | |
825 | struct drm_file *pin_filp; | |
71acb5eb DA |
826 | |
827 | /** for phy allocated objects */ | |
828 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 829 | |
6b95a207 KH |
830 | /** |
831 | * Number of crtcs where this object is currently the fb, but | |
832 | * will be page flipped away on the next vblank. When it | |
833 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
834 | */ | |
835 | atomic_t pending_flip; | |
673a394b EA |
836 | }; |
837 | ||
62b8b215 | 838 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 839 | |
673a394b EA |
840 | /** |
841 | * Request queue structure. | |
842 | * | |
843 | * The request queue allows us to note sequence numbers that have been emitted | |
844 | * and may be associated with active buffers to be retired. | |
845 | * | |
846 | * By keeping this list, we can avoid having to do questionable | |
847 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
848 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
849 | */ | |
850 | struct drm_i915_gem_request { | |
852835f3 ZN |
851 | /** On Which ring this request was generated */ |
852 | struct intel_ring_buffer *ring; | |
853 | ||
673a394b EA |
854 | /** GEM sequence number associated with this request. */ |
855 | uint32_t seqno; | |
856 | ||
857 | /** Time at which this request was emitted, in jiffies. */ | |
858 | unsigned long emitted_jiffies; | |
859 | ||
b962442e | 860 | /** global list entry for this request */ |
673a394b | 861 | struct list_head list; |
b962442e | 862 | |
f787a5f5 | 863 | struct drm_i915_file_private *file_priv; |
b962442e EA |
864 | /** file_priv list entry for this request */ |
865 | struct list_head client_list; | |
673a394b EA |
866 | }; |
867 | ||
868 | struct drm_i915_file_private { | |
869 | struct { | |
1c25595f | 870 | struct spinlock lock; |
b962442e | 871 | struct list_head request_list; |
673a394b EA |
872 | } mm; |
873 | }; | |
874 | ||
79e53945 JB |
875 | enum intel_chip_family { |
876 | CHIP_I8XX = 0x01, | |
877 | CHIP_I9XX = 0x02, | |
878 | CHIP_I915 = 0x04, | |
879 | CHIP_I965 = 0x08, | |
880 | }; | |
881 | ||
cae5852d ZN |
882 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
883 | ||
884 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
885 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
886 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
887 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
888 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
889 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
890 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
891 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
892 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
893 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
894 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
895 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
896 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
897 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
898 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
899 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
900 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
901 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
902 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) | |
903 | ||
904 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) | |
905 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
906 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
907 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
908 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
909 | ||
910 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
911 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
912 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) | |
913 | ||
914 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) | |
915 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) | |
916 | ||
917 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
918 | * rows, which changed the alignment requirements and fence programming. | |
919 | */ | |
920 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
921 | IS_I915GM(dev))) | |
922 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
923 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
924 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
925 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
926 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
927 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
928 | /* dsparb controlled by hw only */ | |
929 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
930 | ||
931 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
932 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
933 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
934 | #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) | |
935 | ||
936 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev)) | |
937 | #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev)) | |
938 | ||
939 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
940 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
941 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
942 | ||
c153f45f | 943 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 944 | extern int i915_max_ioctl; |
79e53945 | 945 | extern unsigned int i915_fbpercrtc; |
652c393a | 946 | extern unsigned int i915_powersave; |
33814341 | 947 | extern unsigned int i915_lvds_downclock; |
b3a83639 | 948 | |
6a9ee8af DA |
949 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
950 | extern int i915_resume(struct drm_device *dev); | |
1341d655 BG |
951 | extern void i915_save_display(struct drm_device *dev); |
952 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
953 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
954 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
955 | ||
1da177e4 | 956 | /* i915_dma.c */ |
84b1fd10 | 957 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 958 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 959 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 960 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 961 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
962 | extern void i915_driver_preclose(struct drm_device *dev, |
963 | struct drm_file *file_priv); | |
673a394b EA |
964 | extern void i915_driver_postclose(struct drm_device *dev, |
965 | struct drm_file *file_priv); | |
84b1fd10 | 966 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
967 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
968 | unsigned long arg); | |
673a394b | 969 | extern int i915_emit_box(struct drm_device *dev, |
201361a5 | 970 | struct drm_clip_rect *boxes, |
673a394b | 971 | int i, int DR1, int DR4); |
f803aa55 | 972 | extern int i915_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
973 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
974 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
975 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
976 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
977 | ||
af6061af | 978 | |
1da177e4 | 979 | /* i915_irq.c */ |
f65d9421 | 980 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 981 | void i915_handle_error(struct drm_device *dev, bool wedged); |
c153f45f EA |
982 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
983 | struct drm_file *file_priv); | |
984 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
985 | struct drm_file *file_priv); | |
9d34e5db | 986 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno); |
79e53945 | 987 | extern void i915_enable_interrupt (struct drm_device *dev); |
1da177e4 LT |
988 | |
989 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 990 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 991 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 992 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
993 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
994 | struct drm_file *file_priv); | |
995 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
996 | struct drm_file *file_priv); | |
0a3e67a4 JB |
997 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
998 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
999 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 1000 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
1001 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
1002 | struct drm_file *file_priv); | |
8ee1c3db | 1003 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
62fdfeaf | 1004 | extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask); |
8187a2b7 ZN |
1005 | extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, |
1006 | u32 mask); | |
1007 | extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, | |
1008 | u32 mask); | |
1da177e4 | 1009 | |
7c463586 KP |
1010 | void |
1011 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1012 | ||
1013 | void | |
1014 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1015 | ||
01c66889 ZY |
1016 | void intel_enable_asle (struct drm_device *dev); |
1017 | ||
3bd3c932 CW |
1018 | #ifdef CONFIG_DEBUG_FS |
1019 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1020 | #else | |
1021 | #define i915_destroy_error_state(x) | |
1022 | #endif | |
1023 | ||
7c463586 | 1024 | |
1da177e4 | 1025 | /* i915_mem.c */ |
c153f45f EA |
1026 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
1027 | struct drm_file *file_priv); | |
1028 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
1029 | struct drm_file *file_priv); | |
1030 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
1031 | struct drm_file *file_priv); | |
1032 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
1033 | struct drm_file *file_priv); | |
1da177e4 | 1034 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 1035 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 1036 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b | 1037 | /* i915_gem.c */ |
30dbf0c0 | 1038 | int i915_gem_check_is_wedged(struct drm_device *dev); |
673a394b EA |
1039 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
1040 | struct drm_file *file_priv); | |
1041 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1042 | struct drm_file *file_priv); | |
1043 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1044 | struct drm_file *file_priv); | |
1045 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1046 | struct drm_file *file_priv); | |
1047 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1048 | struct drm_file *file_priv); | |
de151cf6 JB |
1049 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1050 | struct drm_file *file_priv); | |
673a394b EA |
1051 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1052 | struct drm_file *file_priv); | |
1053 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1054 | struct drm_file *file_priv); | |
1055 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1056 | struct drm_file *file_priv); | |
76446cac JB |
1057 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1058 | struct drm_file *file_priv); | |
673a394b EA |
1059 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1060 | struct drm_file *file_priv); | |
1061 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1062 | struct drm_file *file_priv); | |
1063 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1064 | struct drm_file *file_priv); | |
1065 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
1066 | struct drm_file *file_priv); | |
3ef94daa CW |
1067 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1068 | struct drm_file *file_priv); | |
673a394b EA |
1069 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1070 | struct drm_file *file_priv); | |
1071 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1072 | struct drm_file *file_priv); | |
1073 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1074 | struct drm_file *file_priv); | |
1075 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1076 | struct drm_file *file_priv); | |
5a125c3c EA |
1077 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1078 | struct drm_file *file_priv); | |
673a394b | 1079 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1080 | int i915_gem_init_object(struct drm_gem_object *obj); |
ac52bc56 DV |
1081 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
1082 | size_t size); | |
673a394b | 1083 | void i915_gem_free_object(struct drm_gem_object *obj); |
920afa77 | 1084 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
75e9e915 | 1085 | bool map_and_fenceable); |
673a394b | 1086 | void i915_gem_object_unpin(struct drm_gem_object *obj); |
0f973f27 | 1087 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
d05ca301 | 1088 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
673a394b | 1089 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 CW |
1090 | |
1091 | /** | |
1092 | * Returns true if seq1 is later than seq2. | |
1093 | */ | |
1094 | static inline bool | |
1095 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1096 | { | |
1097 | return (int32_t)(seq1 - seq2) >= 0; | |
1098 | } | |
1099 | ||
2cf34d7b CW |
1100 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
1101 | bool interruptible); | |
1102 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj, | |
1103 | bool interruptible); | |
b09a1fec | 1104 | void i915_gem_retire_requests(struct drm_device *dev); |
069efc1d | 1105 | void i915_gem_reset(struct drm_device *dev); |
673a394b | 1106 | void i915_gem_clflush_object(struct drm_gem_object *obj); |
79e53945 JB |
1107 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
1108 | uint32_t read_domains, | |
1109 | uint32_t write_domain); | |
85345517 CW |
1110 | int i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, |
1111 | bool interruptible); | |
79e53945 JB |
1112 | int i915_gem_init_ringbuffer(struct drm_device *dev); |
1113 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
1114 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, | |
53984635 | 1115 | unsigned long mappable_end, unsigned long end); |
b47eb4a2 | 1116 | int i915_gpu_idle(struct drm_device *dev); |
5669fcac | 1117 | int i915_gem_idle(struct drm_device *dev); |
3cce469c CW |
1118 | int i915_add_request(struct drm_device *dev, |
1119 | struct drm_file *file_priv, | |
1120 | struct drm_i915_gem_request *request, | |
1121 | struct intel_ring_buffer *ring); | |
852835f3 | 1122 | int i915_do_wait_request(struct drm_device *dev, |
8a1a49f9 DV |
1123 | uint32_t seqno, |
1124 | bool interruptible, | |
1125 | struct intel_ring_buffer *ring); | |
de151cf6 | 1126 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
79e53945 JB |
1127 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
1128 | int write); | |
48b956c5 CW |
1129 | int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
1130 | bool pipelined); | |
71acb5eb | 1131 | int i915_gem_attach_phys_object(struct drm_device *dev, |
6eeefaf3 CW |
1132 | struct drm_gem_object *obj, |
1133 | int id, | |
1134 | int align); | |
71acb5eb DA |
1135 | void i915_gem_detach_phys_object(struct drm_device *dev, |
1136 | struct drm_gem_object *obj); | |
1137 | void i915_gem_free_all_phys_object(struct drm_device *dev); | |
1fd1c624 | 1138 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
673a394b | 1139 | |
b47eb4a2 | 1140 | /* i915_gem_evict.c */ |
a6e0aa42 DV |
1141 | int i915_gem_evict_something(struct drm_device *dev, int min_size, |
1142 | unsigned alignment, bool mappable); | |
5eac3ab4 CW |
1143 | int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); |
1144 | int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only); | |
b47eb4a2 | 1145 | |
673a394b EA |
1146 | /* i915_gem_tiling.c */ |
1147 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
280b713b EA |
1148 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
1149 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); | |
673a394b EA |
1150 | |
1151 | /* i915_gem_debug.c */ | |
1152 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1153 | const char *where, uint32_t mark); | |
23bc5982 CW |
1154 | #if WATCH_LISTS |
1155 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1156 | #else |
23bc5982 | 1157 | #define i915_verify_lists(dev) 0 |
673a394b EA |
1158 | #endif |
1159 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
1160 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1161 | const char *where, uint32_t mark); | |
1da177e4 | 1162 | |
2017263e | 1163 | /* i915_debugfs.c */ |
27c202ad BG |
1164 | int i915_debugfs_init(struct drm_minor *minor); |
1165 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1166 | |
317c35d1 JB |
1167 | /* i915_suspend.c */ |
1168 | extern int i915_save_state(struct drm_device *dev); | |
1169 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1170 | |
1171 | /* i915_suspend.c */ | |
1172 | extern int i915_save_state(struct drm_device *dev); | |
1173 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1174 | |
f899fc64 CW |
1175 | /* intel_i2c.c */ |
1176 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1177 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
e957d772 CW |
1178 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1179 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1180 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1181 | { | |
1182 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1183 | } | |
f899fc64 CW |
1184 | extern void intel_i2c_reset(struct drm_device *dev); |
1185 | ||
3b617967 | 1186 | /* intel_opregion.c */ |
44834a67 CW |
1187 | extern int intel_opregion_setup(struct drm_device *dev); |
1188 | #ifdef CONFIG_ACPI | |
1189 | extern void intel_opregion_init(struct drm_device *dev); | |
1190 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1191 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1192 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1193 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1194 | #else |
44834a67 CW |
1195 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1196 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1197 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1198 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1199 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1200 | #endif |
8ee1c3db | 1201 | |
723bfd70 JB |
1202 | /* intel_acpi.c */ |
1203 | #ifdef CONFIG_ACPI | |
1204 | extern void intel_register_dsm_handler(void); | |
1205 | extern void intel_unregister_dsm_handler(void); | |
1206 | #else | |
1207 | static inline void intel_register_dsm_handler(void) { return; } | |
1208 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1209 | #endif /* CONFIG_ACPI */ | |
1210 | ||
79e53945 JB |
1211 | /* modesetting */ |
1212 | extern void intel_modeset_init(struct drm_device *dev); | |
1213 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
28d52043 | 1214 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
80824003 | 1215 | extern void i8xx_disable_fbc(struct drm_device *dev); |
74dff282 | 1216 | extern void g4x_disable_fbc(struct drm_device *dev); |
b52eb4dc | 1217 | extern void ironlake_disable_fbc(struct drm_device *dev); |
ee5382ae AJ |
1218 | extern void intel_disable_fbc(struct drm_device *dev); |
1219 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
1220 | extern bool intel_fbc_enabled(struct drm_device *dev); | |
7648fa99 | 1221 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
3bad0781 | 1222 | extern void intel_detect_pch (struct drm_device *dev); |
e3421a18 | 1223 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
3bad0781 | 1224 | |
6ef3d427 | 1225 | /* overlay */ |
3bd3c932 | 1226 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1227 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1228 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1229 | |
1230 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1231 | extern void intel_display_print_error_state(struct seq_file *m, | |
1232 | struct drm_device *dev, | |
1233 | struct intel_display_error_state *error); | |
3bd3c932 | 1234 | #endif |
6ef3d427 | 1235 | |
546b0974 EA |
1236 | /** |
1237 | * Lock test for when it's just for synchronization of ring access. | |
1238 | * | |
1239 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1240 | * has access to the ring. | |
1241 | */ | |
1242 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
8187a2b7 ZN |
1243 | if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \ |
1244 | == NULL) \ | |
546b0974 EA |
1245 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ |
1246 | } while (0) | |
1247 | ||
cae5852d ZN |
1248 | #define I915_READ(reg) i915_read(dev_priv, (reg), 4) |
1249 | #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val), 4) | |
1250 | #define I915_READ16(reg) i915_read(dev_priv, (reg), 2) | |
1251 | #define I915_WRITE16(reg, val) i915_write(dev_priv, (reg), (val), 2) | |
1252 | #define I915_READ8(reg) i915_read(dev_priv, (reg), 1) | |
1253 | #define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1) | |
1254 | #define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8) | |
1255 | #define I915_READ64(reg) i915_read(dev_priv, (reg), 8) | |
1256 | ||
1257 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) | |
1258 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
1259 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1260 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1261 | ||
1262 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1263 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1264 | ||
ba4f01a3 YL |
1265 | static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg, int len) |
1266 | { | |
1267 | u64 val = 0; | |
1268 | ||
1269 | switch (len) { | |
1270 | case 8: | |
1271 | val = readq(dev_priv->regs + reg); | |
1272 | break; | |
1273 | case 4: | |
1274 | val = readl(dev_priv->regs + reg); | |
1275 | break; | |
1276 | case 2: | |
1277 | val = readw(dev_priv->regs + reg); | |
1278 | break; | |
1279 | case 1: | |
1280 | val = readb(dev_priv->regs + reg); | |
1281 | break; | |
1282 | } | |
1283 | trace_i915_reg_rw('R', reg, val, len); | |
1284 | ||
1285 | return val; | |
1286 | } | |
1287 | ||
cae5852d ZN |
1288 | /* On SNB platform, before reading ring registers forcewake bit |
1289 | * must be set to prevent GT core from power down and stale values being | |
1290 | * returned. | |
1291 | */ | |
1292 | static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg) | |
1293 | { | |
1294 | if (IS_GEN6(dev_priv->dev)) { | |
1295 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
1296 | POSTING_READ(FORCEWAKE); | |
1297 | /* XXX How long do we really need to wait here? | |
1298 | * Will different registers/engines require different periods? | |
1299 | */ | |
1300 | udelay(100); | |
1301 | } | |
1302 | return I915_READ(reg); | |
1303 | } | |
1304 | ||
ba4f01a3 YL |
1305 | static inline void |
1306 | i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len) | |
1307 | { | |
1308 | /* Trace down the write operation before the real write */ | |
1309 | trace_i915_reg_rw('W', reg, val, len); | |
1310 | switch (len) { | |
1311 | case 8: | |
1312 | writeq(val, dev_priv->regs + reg); | |
1313 | break; | |
1314 | case 4: | |
1315 | writel(val, dev_priv->regs + reg); | |
1316 | break; | |
1317 | case 2: | |
1318 | writew(val, dev_priv->regs + reg); | |
1319 | break; | |
1320 | case 1: | |
1321 | writeb(val, dev_priv->regs + reg); | |
1322 | break; | |
1323 | } | |
1324 | } | |
1325 | ||
e1f99ce6 CW |
1326 | #define BEGIN_LP_RING(n) \ |
1327 | intel_ring_begin(&dev_priv->render_ring, (n)) | |
1da177e4 | 1328 | |
e1f99ce6 CW |
1329 | #define OUT_RING(x) \ |
1330 | intel_ring_emit(&dev_priv->render_ring, x) | |
1da177e4 | 1331 | |
e1f99ce6 CW |
1332 | #define ADVANCE_LP_RING() \ |
1333 | intel_ring_advance(&dev_priv->render_ring) | |
1da177e4 | 1334 | |
ba8bbcf6 | 1335 | /** |
585fb111 JB |
1336 | * Reads a dword out of the status page, which is written to from the command |
1337 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
1338 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 1339 | * |
585fb111 | 1340 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
1341 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
1342 | * 0x04: ring 0 head pointer | |
1343 | * 0x05: ring 1 head pointer (915-class) | |
1344 | * 0x06: ring 2 head pointer (915-class) | |
1345 | * 0x10-0x1b: Context status DWords (GM45) | |
1346 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 1347 | * |
0cdad7e8 | 1348 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 1349 | */ |
8187a2b7 ZN |
1350 | #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\ |
1351 | (dev_priv->render_ring.status_page.page_addr))[reg]) | |
0baf823a | 1352 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 1353 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 1354 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 1355 | |
1da177e4 | 1356 | #endif |