Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
e23ceb83 | 36 | #include <drm/drmP.h> |
c838d719 | 37 | #include "i915_params.h" |
585fb111 | 38 | #include "i915_reg.h" |
79e53945 | 39 | #include "intel_bios.h" |
8187a2b7 | 40 | #include "intel_ringbuffer.h" |
b20385f1 | 41 | #include "intel_lrc.h" |
0260c420 | 42 | #include "i915_gem_gtt.h" |
564ddb2f | 43 | #include "i915_gem_render_state.h" |
0839ccb8 | 44 | #include <linux/io-mapping.h> |
f899fc64 | 45 | #include <linux/i2c.h> |
c167a6fc | 46 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 47 | #include <drm/intel-gtt.h> |
ba8286fa | 48 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
d9fc9413 | 49 | #include <drm/drm_gem.h> |
aaa6fd2a | 50 | #include <linux/backlight.h> |
5cc9ed4b | 51 | #include <linux/hashtable.h> |
2911a35b | 52 | #include <linux/intel-iommu.h> |
742cbee8 | 53 | #include <linux/kref.h> |
9ee32fea | 54 | #include <linux/pm_qos.h> |
33a732f4 | 55 | #include "intel_guc.h" |
585fb111 | 56 | |
1da177e4 LT |
57 | /* General customization: |
58 | */ | |
59 | ||
1da177e4 LT |
60 | #define DRIVER_NAME "i915" |
61 | #define DRIVER_DESC "Intel Graphics" | |
947eaebc | 62 | #define DRIVER_DATE "20160124" |
1da177e4 | 63 | |
c883ef1b | 64 | #undef WARN_ON |
5f77eeb0 DV |
65 | /* Many gcc seem to no see through this and fall over :( */ |
66 | #if 0 | |
67 | #define WARN_ON(x) ({ \ | |
68 | bool __i915_warn_cond = (x); \ | |
69 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
70 | BUILD_BUG_ON(__i915_warn_cond); \ | |
71 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
72 | #else | |
152b2262 | 73 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") |
5f77eeb0 DV |
74 | #endif |
75 | ||
cd9bfacb | 76 | #undef WARN_ON_ONCE |
152b2262 | 77 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") |
cd9bfacb | 78 | |
5f77eeb0 DV |
79 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
80 | (long) (x), __func__); | |
c883ef1b | 81 | |
e2c719b7 RC |
82 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
83 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
84 | * which may not necessarily be a user visible problem. This will either | |
85 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
86 | * enable distros and users to tailor their preferred amount of i915 abrt | |
87 | * spam. | |
88 | */ | |
89 | #define I915_STATE_WARN(condition, format...) ({ \ | |
90 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
91 | if (unlikely(__ret_warn_on)) \ |
92 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 93 | DRM_ERROR(format); \ |
e2c719b7 RC |
94 | unlikely(__ret_warn_on); \ |
95 | }) | |
96 | ||
152b2262 JL |
97 | #define I915_STATE_WARN_ON(x) \ |
98 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 99 | |
42a8ca4c JN |
100 | static inline const char *yesno(bool v) |
101 | { | |
102 | return v ? "yes" : "no"; | |
103 | } | |
104 | ||
87ad3212 JN |
105 | static inline const char *onoff(bool v) |
106 | { | |
107 | return v ? "on" : "off"; | |
108 | } | |
109 | ||
317c35d1 | 110 | enum pipe { |
752aa88a | 111 | INVALID_PIPE = -1, |
317c35d1 JB |
112 | PIPE_A = 0, |
113 | PIPE_B, | |
9db4a9c7 | 114 | PIPE_C, |
a57c774a AK |
115 | _PIPE_EDP, |
116 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 117 | }; |
9db4a9c7 | 118 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 119 | |
a5c961d1 PZ |
120 | enum transcoder { |
121 | TRANSCODER_A = 0, | |
122 | TRANSCODER_B, | |
123 | TRANSCODER_C, | |
a57c774a AK |
124 | TRANSCODER_EDP, |
125 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
126 | }; |
127 | #define transcoder_name(t) ((t) + 'A') | |
128 | ||
84139d1e | 129 | /* |
31409e97 MR |
130 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
131 | * number of planes per CRTC. Not all platforms really have this many planes, | |
132 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
133 | * between the topmost sprite plane and the cursor plane. | |
84139d1e | 134 | */ |
80824003 JB |
135 | enum plane { |
136 | PLANE_A = 0, | |
137 | PLANE_B, | |
9db4a9c7 | 138 | PLANE_C, |
31409e97 MR |
139 | PLANE_CURSOR, |
140 | I915_MAX_PLANES, | |
80824003 | 141 | }; |
9db4a9c7 | 142 | #define plane_name(p) ((p) + 'A') |
52440211 | 143 | |
d615a166 | 144 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 145 | |
2b139522 ED |
146 | enum port { |
147 | PORT_A = 0, | |
148 | PORT_B, | |
149 | PORT_C, | |
150 | PORT_D, | |
151 | PORT_E, | |
152 | I915_MAX_PORTS | |
153 | }; | |
154 | #define port_name(p) ((p) + 'A') | |
155 | ||
a09caddd | 156 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
157 | |
158 | enum dpio_channel { | |
159 | DPIO_CH0, | |
160 | DPIO_CH1 | |
161 | }; | |
162 | ||
163 | enum dpio_phy { | |
164 | DPIO_PHY0, | |
165 | DPIO_PHY1 | |
166 | }; | |
167 | ||
b97186f0 PZ |
168 | enum intel_display_power_domain { |
169 | POWER_DOMAIN_PIPE_A, | |
170 | POWER_DOMAIN_PIPE_B, | |
171 | POWER_DOMAIN_PIPE_C, | |
172 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
173 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
174 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
175 | POWER_DOMAIN_TRANSCODER_A, | |
176 | POWER_DOMAIN_TRANSCODER_B, | |
177 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 178 | POWER_DOMAIN_TRANSCODER_EDP, |
6331a704 PJ |
179 | POWER_DOMAIN_PORT_DDI_A_LANES, |
180 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
181 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
182 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
183 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
319be8ae ID |
184 | POWER_DOMAIN_PORT_DSI, |
185 | POWER_DOMAIN_PORT_CRT, | |
186 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 187 | POWER_DOMAIN_VGA, |
fbeeaa23 | 188 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 189 | POWER_DOMAIN_PLLS, |
1407121a S |
190 | POWER_DOMAIN_AUX_A, |
191 | POWER_DOMAIN_AUX_B, | |
192 | POWER_DOMAIN_AUX_C, | |
193 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 194 | POWER_DOMAIN_GMBUS, |
dfa57627 | 195 | POWER_DOMAIN_MODESET, |
baa70707 | 196 | POWER_DOMAIN_INIT, |
bddc7645 ID |
197 | |
198 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
199 | }; |
200 | ||
201 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
202 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
203 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
204 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
205 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
206 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 207 | |
1d843f9d EE |
208 | enum hpd_pin { |
209 | HPD_NONE = 0, | |
1d843f9d EE |
210 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
211 | HPD_CRT, | |
212 | HPD_SDVO_B, | |
213 | HPD_SDVO_C, | |
cc24fcdc | 214 | HPD_PORT_A, |
1d843f9d EE |
215 | HPD_PORT_B, |
216 | HPD_PORT_C, | |
217 | HPD_PORT_D, | |
26951caf | 218 | HPD_PORT_E, |
1d843f9d EE |
219 | HPD_NUM_PINS |
220 | }; | |
221 | ||
c91711f9 JN |
222 | #define for_each_hpd_pin(__pin) \ |
223 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
224 | ||
5fcece80 JN |
225 | struct i915_hotplug { |
226 | struct work_struct hotplug_work; | |
227 | ||
228 | struct { | |
229 | unsigned long last_jiffies; | |
230 | int count; | |
231 | enum { | |
232 | HPD_ENABLED = 0, | |
233 | HPD_DISABLED = 1, | |
234 | HPD_MARK_DISABLED = 2 | |
235 | } state; | |
236 | } stats[HPD_NUM_PINS]; | |
237 | u32 event_bits; | |
238 | struct delayed_work reenable_work; | |
239 | ||
240 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
241 | u32 long_port_mask; | |
242 | u32 short_port_mask; | |
243 | struct work_struct dig_port_work; | |
244 | ||
245 | /* | |
246 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
247 | * the non-DP HPD could block the workqueue on a mode config | |
248 | * mutex getting, that userspace may have taken. However | |
249 | * userspace is waiting on the DP workqueue to run which is | |
250 | * blocked behind the non-DP one. | |
251 | */ | |
252 | struct workqueue_struct *dp_wq; | |
253 | }; | |
254 | ||
2a2d5482 CW |
255 | #define I915_GEM_GPU_DOMAINS \ |
256 | (I915_GEM_DOMAIN_RENDER | \ | |
257 | I915_GEM_DOMAIN_SAMPLER | \ | |
258 | I915_GEM_DOMAIN_COMMAND | \ | |
259 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
260 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 261 | |
055e393f DL |
262 | #define for_each_pipe(__dev_priv, __p) \ |
263 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
dd740780 DL |
264 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
265 | for ((__p) = 0; \ | |
266 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
267 | (__p)++) | |
3bdcfc0c DL |
268 | #define for_each_sprite(__dev_priv, __p, __s) \ |
269 | for ((__s) = 0; \ | |
270 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
271 | (__s)++) | |
9db4a9c7 | 272 | |
d79b814d DL |
273 | #define for_each_crtc(dev, crtc) \ |
274 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
275 | ||
27321ae8 ML |
276 | #define for_each_intel_plane(dev, intel_plane) \ |
277 | list_for_each_entry(intel_plane, \ | |
278 | &dev->mode_config.plane_list, \ | |
279 | base.head) | |
280 | ||
262cd2e1 VS |
281 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
282 | list_for_each_entry(intel_plane, \ | |
283 | &(dev)->mode_config.plane_list, \ | |
284 | base.head) \ | |
95150bdf | 285 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 286 | |
d063ae48 DL |
287 | #define for_each_intel_crtc(dev, intel_crtc) \ |
288 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
289 | ||
b2784e15 DL |
290 | #define for_each_intel_encoder(dev, intel_encoder) \ |
291 | list_for_each_entry(intel_encoder, \ | |
292 | &(dev)->mode_config.encoder_list, \ | |
293 | base.head) | |
294 | ||
3a3371ff ACO |
295 | #define for_each_intel_connector(dev, intel_connector) \ |
296 | list_for_each_entry(intel_connector, \ | |
297 | &dev->mode_config.connector_list, \ | |
298 | base.head) | |
299 | ||
6c2b7c12 DV |
300 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
301 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 302 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 303 | |
53f5e3ca JB |
304 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
305 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 306 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 307 | |
b04c5bd6 BF |
308 | #define for_each_power_domain(domain, mask) \ |
309 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
95150bdf | 310 | for_each_if ((1 << (domain)) & (mask)) |
b04c5bd6 | 311 | |
e7b903d2 | 312 | struct drm_i915_private; |
ad46cb53 | 313 | struct i915_mm_struct; |
5cc9ed4b | 314 | struct i915_mmu_object; |
e7b903d2 | 315 | |
a6f766f3 CW |
316 | struct drm_i915_file_private { |
317 | struct drm_i915_private *dev_priv; | |
318 | struct drm_file *file; | |
319 | ||
320 | struct { | |
321 | spinlock_t lock; | |
322 | struct list_head request_list; | |
d0bc54f2 CW |
323 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
324 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
325 | * (when using lax throttling for the frontbuffer). We also use it to | |
326 | * offer free GPU waitboosts for severely congested workloads. | |
327 | */ | |
328 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
329 | } mm; |
330 | struct idr context_idr; | |
331 | ||
2e1b8730 CW |
332 | struct intel_rps_client { |
333 | struct list_head link; | |
334 | unsigned boosts; | |
335 | } rps; | |
a6f766f3 | 336 | |
de1add36 | 337 | unsigned int bsd_ring; |
a6f766f3 CW |
338 | }; |
339 | ||
46edb027 DV |
340 | enum intel_dpll_id { |
341 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
342 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
343 | DPLL_ID_PCH_PLL_A = 0, |
344 | DPLL_ID_PCH_PLL_B = 1, | |
429d47d5 | 345 | /* hsw/bdw */ |
9cd86933 DV |
346 | DPLL_ID_WRPLL1 = 0, |
347 | DPLL_ID_WRPLL2 = 1, | |
00490c22 ML |
348 | DPLL_ID_SPLL = 2, |
349 | ||
429d47d5 S |
350 | /* skl */ |
351 | DPLL_ID_SKL_DPLL1 = 0, | |
352 | DPLL_ID_SKL_DPLL2 = 1, | |
353 | DPLL_ID_SKL_DPLL3 = 2, | |
46edb027 | 354 | }; |
429d47d5 | 355 | #define I915_NUM_PLLS 3 |
46edb027 | 356 | |
5358901f | 357 | struct intel_dpll_hw_state { |
dcfc3552 | 358 | /* i9xx, pch plls */ |
66e985c0 | 359 | uint32_t dpll; |
8bcc2795 | 360 | uint32_t dpll_md; |
66e985c0 DV |
361 | uint32_t fp0; |
362 | uint32_t fp1; | |
dcfc3552 DL |
363 | |
364 | /* hsw, bdw */ | |
d452c5b6 | 365 | uint32_t wrpll; |
00490c22 | 366 | uint32_t spll; |
d1a2dc78 S |
367 | |
368 | /* skl */ | |
369 | /* | |
370 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in | |
71cd8423 | 371 | * lower part of ctrl1 and they get shifted into position when writing |
d1a2dc78 S |
372 | * the register. This allows us to easily compare the state to share |
373 | * the DPLL. | |
374 | */ | |
375 | uint32_t ctrl1; | |
376 | /* HDMI only, 0 when used for DP */ | |
377 | uint32_t cfgcr1, cfgcr2; | |
dfb82408 S |
378 | |
379 | /* bxt */ | |
05712c15 ID |
380 | uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, |
381 | pcsdw12; | |
5358901f DV |
382 | }; |
383 | ||
3e369b76 | 384 | struct intel_shared_dpll_config { |
1e6f2ddc | 385 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
3e369b76 ACO |
386 | struct intel_dpll_hw_state hw_state; |
387 | }; | |
388 | ||
389 | struct intel_shared_dpll { | |
390 | struct intel_shared_dpll_config config; | |
8bd31e67 | 391 | |
ee7b9f93 JB |
392 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
393 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
394 | const char *name; |
395 | /* should match the index in the dev_priv->shared_dplls array */ | |
396 | enum intel_dpll_id id; | |
96f6128c DV |
397 | /* The mode_set hook is optional and should be used together with the |
398 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
399 | void (*mode_set)(struct drm_i915_private *dev_priv, |
400 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
401 | void (*enable)(struct drm_i915_private *dev_priv, |
402 | struct intel_shared_dpll *pll); | |
403 | void (*disable)(struct drm_i915_private *dev_priv, | |
404 | struct intel_shared_dpll *pll); | |
5358901f DV |
405 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
406 | struct intel_shared_dpll *pll, | |
407 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 408 | }; |
ee7b9f93 | 409 | |
429d47d5 S |
410 | #define SKL_DPLL0 0 |
411 | #define SKL_DPLL1 1 | |
412 | #define SKL_DPLL2 2 | |
413 | #define SKL_DPLL3 3 | |
414 | ||
e69d0bc1 DV |
415 | /* Used by dp and fdi links */ |
416 | struct intel_link_m_n { | |
417 | uint32_t tu; | |
418 | uint32_t gmch_m; | |
419 | uint32_t gmch_n; | |
420 | uint32_t link_m; | |
421 | uint32_t link_n; | |
422 | }; | |
423 | ||
424 | void intel_link_compute_m_n(int bpp, int nlanes, | |
425 | int pixel_clock, int link_clock, | |
426 | struct intel_link_m_n *m_n); | |
427 | ||
1da177e4 LT |
428 | /* Interface history: |
429 | * | |
430 | * 1.1: Original. | |
0d6aa60b DA |
431 | * 1.2: Add Power Management |
432 | * 1.3: Add vblank support | |
de227f5f | 433 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 434 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
435 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
436 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
437 | */ |
438 | #define DRIVER_MAJOR 1 | |
2228ed67 | 439 | #define DRIVER_MINOR 6 |
1da177e4 LT |
440 | #define DRIVER_PATCHLEVEL 0 |
441 | ||
23bc5982 | 442 | #define WATCH_LISTS 0 |
673a394b | 443 | |
0a3e67a4 JB |
444 | struct opregion_header; |
445 | struct opregion_acpi; | |
446 | struct opregion_swsci; | |
447 | struct opregion_asle; | |
448 | ||
8ee1c3db | 449 | struct intel_opregion { |
115719fc WD |
450 | struct opregion_header *header; |
451 | struct opregion_acpi *acpi; | |
452 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
453 | u32 swsci_gbda_sub_functions; |
454 | u32 swsci_sbcb_sub_functions; | |
115719fc | 455 | struct opregion_asle *asle; |
04ebaadb | 456 | void *rvda; |
82730385 | 457 | const void *vbt; |
ada8f955 | 458 | u32 vbt_size; |
115719fc | 459 | u32 *lid_state; |
91a60f20 | 460 | struct work_struct asle_work; |
8ee1c3db | 461 | }; |
44834a67 | 462 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 463 | |
6ef3d427 CW |
464 | struct intel_overlay; |
465 | struct intel_overlay_error_state; | |
466 | ||
de151cf6 | 467 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
468 | #define I915_MAX_NUM_FENCES 32 |
469 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
470 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
471 | |
472 | struct drm_i915_fence_reg { | |
007cc8ac | 473 | struct list_head lru_list; |
caea7476 | 474 | struct drm_i915_gem_object *obj; |
1690e1eb | 475 | int pin_count; |
de151cf6 | 476 | }; |
7c1c2871 | 477 | |
9b9d172d | 478 | struct sdvo_device_mapping { |
e957d772 | 479 | u8 initialized; |
9b9d172d | 480 | u8 dvo_port; |
481 | u8 slave_addr; | |
482 | u8 dvo_wiring; | |
e957d772 | 483 | u8 i2c_pin; |
b1083333 | 484 | u8 ddc_pin; |
9b9d172d | 485 | }; |
486 | ||
c4a1d9e4 CW |
487 | struct intel_display_error_state; |
488 | ||
63eeaf38 | 489 | struct drm_i915_error_state { |
742cbee8 | 490 | struct kref ref; |
585b0288 BW |
491 | struct timeval time; |
492 | ||
cb383002 | 493 | char error_msg[128]; |
eb5be9d0 | 494 | int iommu; |
48b031e3 | 495 | u32 reset_count; |
62d5d69b | 496 | u32 suspend_count; |
cb383002 | 497 | |
585b0288 | 498 | /* Generic register state */ |
63eeaf38 JB |
499 | u32 eir; |
500 | u32 pgtbl_er; | |
be998e2e | 501 | u32 ier; |
885ea5a8 | 502 | u32 gtier[4]; |
b9a3906b | 503 | u32 ccid; |
0f3b6849 CW |
504 | u32 derrmr; |
505 | u32 forcewake; | |
585b0288 BW |
506 | u32 error; /* gen6+ */ |
507 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
508 | u32 fault_data0; /* gen8, gen9 */ |
509 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 510 | u32 done_reg; |
91ec5d11 BW |
511 | u32 gac_eco; |
512 | u32 gam_ecochk; | |
513 | u32 gab_ctl; | |
514 | u32 gfx_mode; | |
585b0288 | 515 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
516 | u64 fence[I915_MAX_NUM_FENCES]; |
517 | struct intel_overlay_error_state *overlay; | |
518 | struct intel_display_error_state *display; | |
0ca36d78 | 519 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 520 | |
52d39a21 | 521 | struct drm_i915_error_ring { |
372fbb8e | 522 | bool valid; |
362b8af7 BW |
523 | /* Software tracked state */ |
524 | bool waiting; | |
525 | int hangcheck_score; | |
526 | enum intel_ring_hangcheck_action hangcheck_action; | |
527 | int num_requests; | |
528 | ||
529 | /* our own tracking of ring head and tail */ | |
530 | u32 cpu_ring_head; | |
531 | u32 cpu_ring_tail; | |
532 | ||
533 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
534 | ||
535 | /* Register state */ | |
94f8cf10 | 536 | u32 start; |
362b8af7 BW |
537 | u32 tail; |
538 | u32 head; | |
539 | u32 ctl; | |
540 | u32 hws; | |
541 | u32 ipeir; | |
542 | u32 ipehr; | |
543 | u32 instdone; | |
362b8af7 BW |
544 | u32 bbstate; |
545 | u32 instpm; | |
546 | u32 instps; | |
547 | u32 seqno; | |
548 | u64 bbaddr; | |
50877445 | 549 | u64 acthd; |
362b8af7 | 550 | u32 fault_reg; |
13ffadd1 | 551 | u64 faddr; |
362b8af7 BW |
552 | u32 rc_psmi; /* sleep state */ |
553 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
554 | ||
52d39a21 CW |
555 | struct drm_i915_error_object { |
556 | int page_count; | |
e1f12325 | 557 | u64 gtt_offset; |
52d39a21 | 558 | u32 *pages[0]; |
ab0e7ff9 | 559 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 560 | |
52d39a21 CW |
561 | struct drm_i915_error_request { |
562 | long jiffies; | |
563 | u32 seqno; | |
ee4f42b1 | 564 | u32 tail; |
52d39a21 | 565 | } *requests; |
6c7a01ec BW |
566 | |
567 | struct { | |
568 | u32 gfx_mode; | |
569 | union { | |
570 | u64 pdp[4]; | |
571 | u32 pp_dir_base; | |
572 | }; | |
573 | } vm_info; | |
ab0e7ff9 CW |
574 | |
575 | pid_t pid; | |
576 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 577 | } ring[I915_NUM_RINGS]; |
3a448734 | 578 | |
9df30794 | 579 | struct drm_i915_error_buffer { |
a779e5ab | 580 | u32 size; |
9df30794 | 581 | u32 name; |
b4716185 | 582 | u32 rseqno[I915_NUM_RINGS], wseqno; |
e1f12325 | 583 | u64 gtt_offset; |
9df30794 CW |
584 | u32 read_domains; |
585 | u32 write_domain; | |
4b9de737 | 586 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
587 | s32 pinned:2; |
588 | u32 tiling:2; | |
589 | u32 dirty:1; | |
590 | u32 purgeable:1; | |
5cc9ed4b | 591 | u32 userptr:1; |
5d1333fc | 592 | s32 ring:4; |
f56383cb | 593 | u32 cache_level:3; |
95f5301d | 594 | } **active_bo, **pinned_bo; |
6c7a01ec | 595 | |
95f5301d | 596 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 597 | u32 vm_count; |
63eeaf38 JB |
598 | }; |
599 | ||
7bd688cd | 600 | struct intel_connector; |
820d2d77 | 601 | struct intel_encoder; |
5cec258b | 602 | struct intel_crtc_state; |
5724dbd1 | 603 | struct intel_initial_plane_config; |
0e8ffe1b | 604 | struct intel_crtc; |
ee9300bb DV |
605 | struct intel_limit; |
606 | struct dpll; | |
b8cecdf5 | 607 | |
e70236a8 | 608 | struct drm_i915_display_funcs { |
e70236a8 JB |
609 | int (*get_display_clock_speed)(struct drm_device *dev); |
610 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
611 | /** |
612 | * find_dpll() - Find the best values for the PLL | |
613 | * @limit: limits for the PLL | |
614 | * @crtc: current CRTC | |
615 | * @target: target frequency in kHz | |
616 | * @refclk: reference clock frequency in kHz | |
617 | * @match_clock: if provided, @best_clock P divider must | |
618 | * match the P divider from @match_clock | |
619 | * used for LVDS downclocking | |
620 | * @best_clock: best PLL values found | |
621 | * | |
622 | * Returns true on success, false on failure. | |
623 | */ | |
624 | bool (*find_dpll)(const struct intel_limit *limit, | |
a93e255f | 625 | struct intel_crtc_state *crtc_state, |
ee9300bb DV |
626 | int target, int refclk, |
627 | struct dpll *match_clock, | |
628 | struct dpll *best_clock); | |
86c8bbbe MR |
629 | int (*compute_pipe_wm)(struct intel_crtc *crtc, |
630 | struct drm_atomic_state *state); | |
bf220452 | 631 | void (*program_watermarks)(struct intel_crtc_state *cstate); |
46ba614c | 632 | void (*update_wm)(struct drm_crtc *crtc); |
27c329ed ML |
633 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
634 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
635 | /* Returns the active state of the crtc, and if the crtc is active, |
636 | * fills out the pipe-config with the hw state. */ | |
637 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 638 | struct intel_crtc_state *); |
5724dbd1 DL |
639 | void (*get_initial_plane_config)(struct intel_crtc *, |
640 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
641 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
642 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
643 | void (*crtc_enable)(struct drm_crtc *crtc); |
644 | void (*crtc_disable)(struct drm_crtc *crtc); | |
69bfe1a9 JN |
645 | void (*audio_codec_enable)(struct drm_connector *connector, |
646 | struct intel_encoder *encoder, | |
5e7234c9 | 647 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 648 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 649 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 650 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
651 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
652 | struct drm_framebuffer *fb, | |
ed8d1975 | 653 | struct drm_i915_gem_object *obj, |
6258fbe2 | 654 | struct drm_i915_gem_request *req, |
ed8d1975 | 655 | uint32_t flags); |
20afbda2 | 656 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
657 | /* clock updates for mode set */ |
658 | /* cursor updates */ | |
659 | /* render clock increase/decrease */ | |
660 | /* display clock increase/decrease */ | |
661 | /* pll clock increase/decrease */ | |
e70236a8 JB |
662 | }; |
663 | ||
48c1026a MK |
664 | enum forcewake_domain_id { |
665 | FW_DOMAIN_ID_RENDER = 0, | |
666 | FW_DOMAIN_ID_BLITTER, | |
667 | FW_DOMAIN_ID_MEDIA, | |
668 | ||
669 | FW_DOMAIN_ID_COUNT | |
670 | }; | |
671 | ||
672 | enum forcewake_domains { | |
673 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
674 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
675 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
676 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
677 | FORCEWAKE_BLITTER | | |
678 | FORCEWAKE_MEDIA) | |
679 | }; | |
680 | ||
907b28c5 | 681 | struct intel_uncore_funcs { |
c8d9a590 | 682 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 683 | enum forcewake_domains domains); |
c8d9a590 | 684 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 685 | enum forcewake_domains domains); |
0b274481 | 686 | |
f0f59a00 VS |
687 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
688 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
689 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
690 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
0b274481 | 691 | |
f0f59a00 | 692 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 693 | uint8_t val, bool trace); |
f0f59a00 | 694 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 695 | uint16_t val, bool trace); |
f0f59a00 | 696 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 697 | uint32_t val, bool trace); |
f0f59a00 | 698 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, |
0b274481 | 699 | uint64_t val, bool trace); |
990bbdad CW |
700 | }; |
701 | ||
907b28c5 CW |
702 | struct intel_uncore { |
703 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
704 | ||
705 | struct intel_uncore_funcs funcs; | |
706 | ||
707 | unsigned fifo_count; | |
48c1026a | 708 | enum forcewake_domains fw_domains; |
b2cff0db CW |
709 | |
710 | struct intel_uncore_forcewake_domain { | |
711 | struct drm_i915_private *i915; | |
48c1026a | 712 | enum forcewake_domain_id id; |
b2cff0db CW |
713 | unsigned wake_count; |
714 | struct timer_list timer; | |
f0f59a00 | 715 | i915_reg_t reg_set; |
05a2fb15 MK |
716 | u32 val_set; |
717 | u32 val_clear; | |
f0f59a00 VS |
718 | i915_reg_t reg_ack; |
719 | i915_reg_t reg_post; | |
05a2fb15 | 720 | u32 val_reset; |
b2cff0db | 721 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
75714940 MK |
722 | |
723 | int unclaimed_mmio_check; | |
b2cff0db CW |
724 | }; |
725 | ||
726 | /* Iterate over initialised fw domains */ | |
727 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ | |
728 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
729 | (i__) < FW_DOMAIN_ID_COUNT; \ | |
730 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ | |
95150bdf | 731 | for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) |
b2cff0db CW |
732 | |
733 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ | |
734 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) | |
907b28c5 | 735 | |
b6e7d894 DL |
736 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
737 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
738 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
739 | ||
eb805623 | 740 | struct intel_csr { |
8144ac59 | 741 | struct work_struct work; |
eb805623 | 742 | const char *fw_path; |
a7f749f9 | 743 | uint32_t *dmc_payload; |
eb805623 | 744 | uint32_t dmc_fw_size; |
b6e7d894 | 745 | uint32_t version; |
eb805623 | 746 | uint32_t mmio_count; |
f0f59a00 | 747 | i915_reg_t mmioaddr[8]; |
eb805623 DV |
748 | uint32_t mmiodata[8]; |
749 | }; | |
750 | ||
79fc46df DL |
751 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
752 | func(is_mobile) sep \ | |
753 | func(is_i85x) sep \ | |
754 | func(is_i915g) sep \ | |
755 | func(is_i945gm) sep \ | |
756 | func(is_g33) sep \ | |
757 | func(need_gfx_hws) sep \ | |
758 | func(is_g4x) sep \ | |
759 | func(is_pineview) sep \ | |
760 | func(is_broadwater) sep \ | |
761 | func(is_crestline) sep \ | |
762 | func(is_ivybridge) sep \ | |
763 | func(is_valleyview) sep \ | |
666a4537 | 764 | func(is_cherryview) sep \ |
79fc46df | 765 | func(is_haswell) sep \ |
7201c0b3 | 766 | func(is_skylake) sep \ |
7526ac19 | 767 | func(is_broxton) sep \ |
ef11bdb3 | 768 | func(is_kabylake) sep \ |
b833d685 | 769 | func(is_preliminary) sep \ |
79fc46df DL |
770 | func(has_fbc) sep \ |
771 | func(has_pipe_cxsr) sep \ | |
772 | func(has_hotplug) sep \ | |
773 | func(cursor_needs_physical) sep \ | |
774 | func(has_overlay) sep \ | |
775 | func(overlay_needs_physical) sep \ | |
776 | func(supports_tv) sep \ | |
dd93be58 | 777 | func(has_llc) sep \ |
30568c45 DL |
778 | func(has_ddi) sep \ |
779 | func(has_fpga_dbg) | |
c96ea64e | 780 | |
a587f779 DL |
781 | #define DEFINE_FLAG(name) u8 name:1 |
782 | #define SEP_SEMICOLON ; | |
c96ea64e | 783 | |
cfdf1fa2 | 784 | struct intel_device_info { |
10fce67a | 785 | u32 display_mmio_offset; |
87f1f465 | 786 | u16 device_id; |
7eb552ae | 787 | u8 num_pipes:3; |
d615a166 | 788 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 789 | u8 gen; |
73ae478c | 790 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 791 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
792 | /* Register offsets for the various display pipes and transcoders */ |
793 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
794 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 795 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 796 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
797 | |
798 | /* Slice/subslice/EU info */ | |
799 | u8 slice_total; | |
800 | u8 subslice_total; | |
801 | u8 subslice_per_slice; | |
802 | u8 eu_total; | |
803 | u8 eu_per_subslice; | |
b7668791 DL |
804 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
805 | u8 subslice_7eu[3]; | |
3873218f JM |
806 | u8 has_slice_pg:1; |
807 | u8 has_subslice_pg:1; | |
808 | u8 has_eu_pg:1; | |
cfdf1fa2 KH |
809 | }; |
810 | ||
a587f779 DL |
811 | #undef DEFINE_FLAG |
812 | #undef SEP_SEMICOLON | |
813 | ||
7faf1ab2 DV |
814 | enum i915_cache_level { |
815 | I915_CACHE_NONE = 0, | |
350ec881 CW |
816 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
817 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
818 | caches, eg sampler/render caches, and the | |
819 | large Last-Level-Cache. LLC is coherent with | |
820 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 821 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
822 | }; |
823 | ||
e59ec13d MK |
824 | struct i915_ctx_hang_stats { |
825 | /* This context had batch pending when hang was declared */ | |
826 | unsigned batch_pending; | |
827 | ||
828 | /* This context had batch active when hang was declared */ | |
829 | unsigned batch_active; | |
be62acb4 MK |
830 | |
831 | /* Time when this context was last blamed for a GPU reset */ | |
832 | unsigned long guilty_ts; | |
833 | ||
676fa572 CW |
834 | /* If the contexts causes a second GPU hang within this time, |
835 | * it is permanently banned from submitting any more work. | |
836 | */ | |
837 | unsigned long ban_period_seconds; | |
838 | ||
be62acb4 MK |
839 | /* This context is banned to submit more work */ |
840 | bool banned; | |
e59ec13d | 841 | }; |
40521054 BW |
842 | |
843 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 844 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 DW |
845 | |
846 | #define CONTEXT_NO_ZEROMAP (1<<0) | |
31b7a88d OM |
847 | /** |
848 | * struct intel_context - as the name implies, represents a context. | |
849 | * @ref: reference count. | |
850 | * @user_handle: userspace tracking identity for this context. | |
851 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
852 | * @flags: context specific flags: |
853 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
854 | * @file_priv: filp associated with this context (NULL for global default |
855 | * context). | |
856 | * @hang_stats: information about the role of this context in possible GPU | |
857 | * hangs. | |
7df113e4 | 858 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
859 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
860 | * initialized (legacy ring submission mechanism only). | |
861 | * @link: link in the global list of contexts. | |
862 | * | |
863 | * Contexts are memory images used by the hardware to store copies of their | |
864 | * internal state. | |
865 | */ | |
273497e5 | 866 | struct intel_context { |
dce3271b | 867 | struct kref ref; |
821d66dd | 868 | int user_handle; |
3ccfd19d | 869 | uint8_t remap_slice; |
9ea4feec | 870 | struct drm_i915_private *i915; |
b1b38278 | 871 | int flags; |
40521054 | 872 | struct drm_i915_file_private *file_priv; |
e59ec13d | 873 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 874 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 875 | |
c9e003af | 876 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
877 | struct { |
878 | struct drm_i915_gem_object *rcs_state; | |
879 | bool initialized; | |
880 | } legacy_hw_ctx; | |
881 | ||
c9e003af OM |
882 | /* Execlists */ |
883 | struct { | |
884 | struct drm_i915_gem_object *state; | |
84c2377f | 885 | struct intel_ringbuffer *ringbuf; |
a7cbedec | 886 | int pin_count; |
ca82580c TU |
887 | struct i915_vma *lrc_vma; |
888 | u64 lrc_desc; | |
82352e90 | 889 | uint32_t *lrc_reg_state; |
c9e003af OM |
890 | } engine[I915_NUM_RINGS]; |
891 | ||
a33afea5 | 892 | struct list_head link; |
40521054 BW |
893 | }; |
894 | ||
a4001f1b PZ |
895 | enum fb_op_origin { |
896 | ORIGIN_GTT, | |
897 | ORIGIN_CPU, | |
898 | ORIGIN_CS, | |
899 | ORIGIN_FLIP, | |
74b4ea1e | 900 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
901 | }; |
902 | ||
ab34a7e8 | 903 | struct intel_fbc { |
25ad93fd PZ |
904 | /* This is always the inner lock when overlapping with struct_mutex and |
905 | * it's the outer lock when overlapping with stolen_lock. */ | |
906 | struct mutex lock; | |
5e59f717 | 907 | unsigned threshold; |
dbef0f15 PZ |
908 | unsigned int possible_framebuffer_bits; |
909 | unsigned int busy_bits; | |
010cf73d | 910 | unsigned int visible_pipes_mask; |
e35fef21 | 911 | struct intel_crtc *crtc; |
5c3fe8b0 | 912 | |
c4213885 | 913 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
914 | struct drm_mm_node *compressed_llb; |
915 | ||
da46f936 RV |
916 | bool false_color; |
917 | ||
d029bcad | 918 | bool enabled; |
0e631adc | 919 | bool active; |
9adccc60 | 920 | |
aaf78d27 PZ |
921 | struct intel_fbc_state_cache { |
922 | struct { | |
923 | unsigned int mode_flags; | |
924 | uint32_t hsw_bdw_pixel_rate; | |
925 | } crtc; | |
926 | ||
927 | struct { | |
928 | unsigned int rotation; | |
929 | int src_w; | |
930 | int src_h; | |
931 | bool visible; | |
932 | } plane; | |
933 | ||
934 | struct { | |
935 | u64 ilk_ggtt_offset; | |
aaf78d27 PZ |
936 | uint32_t pixel_format; |
937 | unsigned int stride; | |
938 | int fence_reg; | |
939 | unsigned int tiling_mode; | |
940 | } fb; | |
941 | } state_cache; | |
942 | ||
b183b3f1 PZ |
943 | struct intel_fbc_reg_params { |
944 | struct { | |
945 | enum pipe pipe; | |
946 | enum plane plane; | |
947 | unsigned int fence_y_offset; | |
948 | } crtc; | |
949 | ||
950 | struct { | |
951 | u64 ggtt_offset; | |
b183b3f1 PZ |
952 | uint32_t pixel_format; |
953 | unsigned int stride; | |
954 | int fence_reg; | |
955 | } fb; | |
956 | ||
957 | int cfb_size; | |
958 | } params; | |
959 | ||
5c3fe8b0 | 960 | struct intel_fbc_work { |
128d7356 | 961 | bool scheduled; |
ca18d51d | 962 | u32 scheduled_vblank; |
128d7356 | 963 | struct work_struct work; |
128d7356 | 964 | } work; |
5c3fe8b0 | 965 | |
bf6189c6 | 966 | const char *no_fbc_reason; |
ff2a3117 | 967 | |
0e631adc | 968 | bool (*is_active)(struct drm_i915_private *dev_priv); |
b183b3f1 | 969 | void (*activate)(struct drm_i915_private *dev_priv); |
0e631adc | 970 | void (*deactivate)(struct drm_i915_private *dev_priv); |
b5e50c3f JB |
971 | }; |
972 | ||
96178eeb VK |
973 | /** |
974 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
975 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
976 | * parsing for same resolution. | |
977 | */ | |
978 | enum drrs_refresh_rate_type { | |
979 | DRRS_HIGH_RR, | |
980 | DRRS_LOW_RR, | |
981 | DRRS_MAX_RR, /* RR count */ | |
982 | }; | |
983 | ||
984 | enum drrs_support_type { | |
985 | DRRS_NOT_SUPPORTED = 0, | |
986 | STATIC_DRRS_SUPPORT = 1, | |
987 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
988 | }; |
989 | ||
2807cf69 | 990 | struct intel_dp; |
96178eeb VK |
991 | struct i915_drrs { |
992 | struct mutex mutex; | |
993 | struct delayed_work work; | |
994 | struct intel_dp *dp; | |
995 | unsigned busy_frontbuffer_bits; | |
996 | enum drrs_refresh_rate_type refresh_rate_type; | |
997 | enum drrs_support_type type; | |
998 | }; | |
999 | ||
a031d709 | 1000 | struct i915_psr { |
f0355c4a | 1001 | struct mutex lock; |
a031d709 RV |
1002 | bool sink_support; |
1003 | bool source_ok; | |
2807cf69 | 1004 | struct intel_dp *enabled; |
7c8f8a70 RV |
1005 | bool active; |
1006 | struct delayed_work work; | |
9ca15301 | 1007 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
1008 | bool psr2_support; |
1009 | bool aux_frame_sync; | |
3f51e471 | 1010 | }; |
5c3fe8b0 | 1011 | |
3bad0781 | 1012 | enum intel_pch { |
f0350830 | 1013 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
1014 | PCH_IBX, /* Ibexpeak PCH */ |
1015 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 1016 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 1017 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 1018 | PCH_NOP, |
3bad0781 ZW |
1019 | }; |
1020 | ||
988d6ee8 PZ |
1021 | enum intel_sbi_destination { |
1022 | SBI_ICLK, | |
1023 | SBI_MPHY, | |
1024 | }; | |
1025 | ||
b690e96c | 1026 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 1027 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1028 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1029 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 1030 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 1031 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 1032 | |
8be48d92 | 1033 | struct intel_fbdev; |
1630fe75 | 1034 | struct intel_fbc_work; |
38651674 | 1035 | |
c2b9152f DV |
1036 | struct intel_gmbus { |
1037 | struct i2c_adapter adapter; | |
f2ce9faf | 1038 | u32 force_bit; |
c2b9152f | 1039 | u32 reg0; |
f0f59a00 | 1040 | i915_reg_t gpio_reg; |
c167a6fc | 1041 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1042 | struct drm_i915_private *dev_priv; |
1043 | }; | |
1044 | ||
f4c956ad | 1045 | struct i915_suspend_saved_registers { |
e948e994 | 1046 | u32 saveDSPARB; |
ba8bbcf6 | 1047 | u32 saveLVDS; |
585fb111 JB |
1048 | u32 savePP_ON_DELAYS; |
1049 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
1050 | u32 savePP_ON; |
1051 | u32 savePP_OFF; | |
1052 | u32 savePP_CONTROL; | |
585fb111 | 1053 | u32 savePP_DIVISOR; |
ba8bbcf6 | 1054 | u32 saveFBC_CONTROL; |
1f84e550 | 1055 | u32 saveCACHE_MODE_0; |
1f84e550 | 1056 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1057 | u32 saveSWF0[16]; |
1058 | u32 saveSWF1[16]; | |
85fa792b | 1059 | u32 saveSWF3[3]; |
4b9de737 | 1060 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1061 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1062 | u16 saveGCDGMBUS; |
f4c956ad | 1063 | }; |
c85aa885 | 1064 | |
ddeea5b0 ID |
1065 | struct vlv_s0ix_state { |
1066 | /* GAM */ | |
1067 | u32 wr_watermark; | |
1068 | u32 gfx_prio_ctrl; | |
1069 | u32 arb_mode; | |
1070 | u32 gfx_pend_tlb0; | |
1071 | u32 gfx_pend_tlb1; | |
1072 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1073 | u32 media_max_req_count; | |
1074 | u32 gfx_max_req_count; | |
1075 | u32 render_hwsp; | |
1076 | u32 ecochk; | |
1077 | u32 bsd_hwsp; | |
1078 | u32 blt_hwsp; | |
1079 | u32 tlb_rd_addr; | |
1080 | ||
1081 | /* MBC */ | |
1082 | u32 g3dctl; | |
1083 | u32 gsckgctl; | |
1084 | u32 mbctl; | |
1085 | ||
1086 | /* GCP */ | |
1087 | u32 ucgctl1; | |
1088 | u32 ucgctl3; | |
1089 | u32 rcgctl1; | |
1090 | u32 rcgctl2; | |
1091 | u32 rstctl; | |
1092 | u32 misccpctl; | |
1093 | ||
1094 | /* GPM */ | |
1095 | u32 gfxpause; | |
1096 | u32 rpdeuhwtc; | |
1097 | u32 rpdeuc; | |
1098 | u32 ecobus; | |
1099 | u32 pwrdwnupctl; | |
1100 | u32 rp_down_timeout; | |
1101 | u32 rp_deucsw; | |
1102 | u32 rcubmabdtmr; | |
1103 | u32 rcedata; | |
1104 | u32 spare2gh; | |
1105 | ||
1106 | /* Display 1 CZ domain */ | |
1107 | u32 gt_imr; | |
1108 | u32 gt_ier; | |
1109 | u32 pm_imr; | |
1110 | u32 pm_ier; | |
1111 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1112 | ||
1113 | /* GT SA CZ domain */ | |
1114 | u32 tilectl; | |
1115 | u32 gt_fifoctl; | |
1116 | u32 gtlc_wake_ctrl; | |
1117 | u32 gtlc_survive; | |
1118 | u32 pmwgicz; | |
1119 | ||
1120 | /* Display 2 CZ domain */ | |
1121 | u32 gu_ctl0; | |
1122 | u32 gu_ctl1; | |
9c25210f | 1123 | u32 pcbr; |
ddeea5b0 ID |
1124 | u32 clock_gate_dis2; |
1125 | }; | |
1126 | ||
bf225f20 CW |
1127 | struct intel_rps_ei { |
1128 | u32 cz_clock; | |
1129 | u32 render_c0; | |
1130 | u32 media_c0; | |
31685c25 D |
1131 | }; |
1132 | ||
c85aa885 | 1133 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1134 | /* |
1135 | * work, interrupts_enabled and pm_iir are protected by | |
1136 | * dev_priv->irq_lock | |
1137 | */ | |
c85aa885 | 1138 | struct work_struct work; |
d4d70aa5 | 1139 | bool interrupts_enabled; |
c85aa885 | 1140 | u32 pm_iir; |
59cdb63d | 1141 | |
b39fb297 BW |
1142 | /* Frequencies are stored in potentially platform dependent multiples. |
1143 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1144 | * Soft limits are those which are used for the dynamic reclocking done | |
1145 | * by the driver (raise frequencies under heavy loads, and lower for | |
1146 | * lighter loads). Hard limits are those imposed by the hardware. | |
1147 | * | |
1148 | * A distinction is made for overclocking, which is never enabled by | |
1149 | * default, and is considered to be above the hard limit if it's | |
1150 | * possible at all. | |
1151 | */ | |
1152 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1153 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1154 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1155 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1156 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
aed242ff | 1157 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1158 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1159 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1160 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
1a01ab3b | 1161 | |
8fb55197 CW |
1162 | u8 up_threshold; /* Current %busy required to uplock */ |
1163 | u8 down_threshold; /* Current %busy required to downclock */ | |
1164 | ||
dd75fdc8 CW |
1165 | int last_adj; |
1166 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1167 | ||
8d3afd7d CW |
1168 | spinlock_t client_lock; |
1169 | struct list_head clients; | |
1170 | bool client_boost; | |
1171 | ||
c0951f0c | 1172 | bool enabled; |
1a01ab3b | 1173 | struct delayed_work delayed_resume_work; |
1854d5ca | 1174 | unsigned boosts; |
4fc688ce | 1175 | |
2e1b8730 | 1176 | struct intel_rps_client semaphores, mmioflips; |
a6f766f3 | 1177 | |
bf225f20 CW |
1178 | /* manual wa residency calculations */ |
1179 | struct intel_rps_ei up_ei, down_ei; | |
1180 | ||
4fc688ce JB |
1181 | /* |
1182 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1183 | * Must be taken after struct_mutex if nested. Note that |
1184 | * this lock may be held for long periods of time when | |
1185 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1186 | */ |
1187 | struct mutex hw_lock; | |
c85aa885 DV |
1188 | }; |
1189 | ||
1a240d4d DV |
1190 | /* defined intel_pm.c */ |
1191 | extern spinlock_t mchdev_lock; | |
1192 | ||
c85aa885 DV |
1193 | struct intel_ilk_power_mgmt { |
1194 | u8 cur_delay; | |
1195 | u8 min_delay; | |
1196 | u8 max_delay; | |
1197 | u8 fmax; | |
1198 | u8 fstart; | |
1199 | ||
1200 | u64 last_count1; | |
1201 | unsigned long last_time1; | |
1202 | unsigned long chipset_power; | |
1203 | u64 last_count2; | |
5ed0bdf2 | 1204 | u64 last_time2; |
c85aa885 DV |
1205 | unsigned long gfx_power; |
1206 | u8 corr; | |
1207 | ||
1208 | int c_m; | |
1209 | int r_t; | |
1210 | }; | |
1211 | ||
c6cb582e ID |
1212 | struct drm_i915_private; |
1213 | struct i915_power_well; | |
1214 | ||
1215 | struct i915_power_well_ops { | |
1216 | /* | |
1217 | * Synchronize the well's hw state to match the current sw state, for | |
1218 | * example enable/disable it based on the current refcount. Called | |
1219 | * during driver init and resume time, possibly after first calling | |
1220 | * the enable/disable handlers. | |
1221 | */ | |
1222 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1223 | struct i915_power_well *power_well); | |
1224 | /* | |
1225 | * Enable the well and resources that depend on it (for example | |
1226 | * interrupts located on the well). Called after the 0->1 refcount | |
1227 | * transition. | |
1228 | */ | |
1229 | void (*enable)(struct drm_i915_private *dev_priv, | |
1230 | struct i915_power_well *power_well); | |
1231 | /* | |
1232 | * Disable the well and resources that depend on it. Called after | |
1233 | * the 1->0 refcount transition. | |
1234 | */ | |
1235 | void (*disable)(struct drm_i915_private *dev_priv, | |
1236 | struct i915_power_well *power_well); | |
1237 | /* Returns the hw enabled state. */ | |
1238 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1239 | struct i915_power_well *power_well); | |
1240 | }; | |
1241 | ||
a38911a3 WX |
1242 | /* Power well structure for haswell */ |
1243 | struct i915_power_well { | |
c1ca727f | 1244 | const char *name; |
6f3ef5dd | 1245 | bool always_on; |
a38911a3 WX |
1246 | /* power well enable/disable usage count */ |
1247 | int count; | |
bfafe93a ID |
1248 | /* cached hw enabled state */ |
1249 | bool hw_enabled; | |
c1ca727f | 1250 | unsigned long domains; |
77961eb9 | 1251 | unsigned long data; |
c6cb582e | 1252 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1253 | }; |
1254 | ||
83c00f55 | 1255 | struct i915_power_domains { |
baa70707 ID |
1256 | /* |
1257 | * Power wells needed for initialization at driver init and suspend | |
1258 | * time are on. They are kept on until after the first modeset. | |
1259 | */ | |
1260 | bool init_power_on; | |
0d116a29 | 1261 | bool initializing; |
c1ca727f | 1262 | int power_well_count; |
baa70707 | 1263 | |
83c00f55 | 1264 | struct mutex lock; |
1da51581 | 1265 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1266 | struct i915_power_well *power_wells; |
83c00f55 ID |
1267 | }; |
1268 | ||
35a85ac6 | 1269 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1270 | struct intel_l3_parity { |
35a85ac6 | 1271 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1272 | struct work_struct error_work; |
35a85ac6 | 1273 | int which_slice; |
a4da4fa4 DV |
1274 | }; |
1275 | ||
4b5aed62 | 1276 | struct i915_gem_mm { |
4b5aed62 DV |
1277 | /** Memory allocator for GTT stolen memory */ |
1278 | struct drm_mm stolen; | |
92e97d2f PZ |
1279 | /** Protects the usage of the GTT stolen memory allocator. This is |
1280 | * always the inner lock when overlapping with struct_mutex. */ | |
1281 | struct mutex stolen_lock; | |
1282 | ||
4b5aed62 DV |
1283 | /** List of all objects in gtt_space. Used to restore gtt |
1284 | * mappings on resume */ | |
1285 | struct list_head bound_list; | |
1286 | /** | |
1287 | * List of objects which are not bound to the GTT (thus | |
1288 | * are idle and not used by the GPU) but still have | |
1289 | * (presumably uncached) pages still attached. | |
1290 | */ | |
1291 | struct list_head unbound_list; | |
1292 | ||
1293 | /** Usable portion of the GTT for GEM */ | |
1294 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1295 | ||
4b5aed62 DV |
1296 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1297 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1298 | ||
2cfcd32a | 1299 | struct notifier_block oom_notifier; |
ceabbba5 | 1300 | struct shrinker shrinker; |
4b5aed62 DV |
1301 | bool shrinker_no_lock_stealing; |
1302 | ||
4b5aed62 DV |
1303 | /** LRU list of objects with fence regs on them. */ |
1304 | struct list_head fence_list; | |
1305 | ||
1306 | /** | |
1307 | * We leave the user IRQ off as much as possible, | |
1308 | * but this means that requests will finish and never | |
1309 | * be retired once the system goes idle. Set a timer to | |
1310 | * fire periodically while the ring is running. When it | |
1311 | * fires, go retire requests. | |
1312 | */ | |
1313 | struct delayed_work retire_work; | |
1314 | ||
b29c19b6 CW |
1315 | /** |
1316 | * When we detect an idle GPU, we want to turn on | |
1317 | * powersaving features. So once we see that there | |
1318 | * are no more requests outstanding and no more | |
1319 | * arrive within a small period of time, we fire | |
1320 | * off the idle_work. | |
1321 | */ | |
1322 | struct delayed_work idle_work; | |
1323 | ||
4b5aed62 DV |
1324 | /** |
1325 | * Are we in a non-interruptible section of code like | |
1326 | * modesetting? | |
1327 | */ | |
1328 | bool interruptible; | |
1329 | ||
f62a0076 CW |
1330 | /** |
1331 | * Is the GPU currently considered idle, or busy executing userspace | |
1332 | * requests? Whilst idle, we attempt to power down the hardware and | |
1333 | * display clocks. In order to reduce the effect on performance, there | |
1334 | * is a slight delay before we do so. | |
1335 | */ | |
1336 | bool busy; | |
1337 | ||
bdf1e7e3 | 1338 | /* the indicator for dispatch video commands on two BSD rings */ |
de1add36 | 1339 | unsigned int bsd_ring_dispatch_index; |
bdf1e7e3 | 1340 | |
4b5aed62 DV |
1341 | /** Bit 6 swizzling required for X tiling */ |
1342 | uint32_t bit_6_swizzle_x; | |
1343 | /** Bit 6 swizzling required for Y tiling */ | |
1344 | uint32_t bit_6_swizzle_y; | |
1345 | ||
4b5aed62 | 1346 | /* accounting, useful for userland debugging */ |
c20e8355 | 1347 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1348 | size_t object_memory; |
1349 | u32 object_count; | |
1350 | }; | |
1351 | ||
edc3d884 | 1352 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1353 | struct drm_i915_private *i915; |
edc3d884 MK |
1354 | unsigned bytes; |
1355 | unsigned size; | |
1356 | int err; | |
1357 | u8 *buf; | |
1358 | loff_t start; | |
1359 | loff_t pos; | |
1360 | }; | |
1361 | ||
fc16b48b MK |
1362 | struct i915_error_state_file_priv { |
1363 | struct drm_device *dev; | |
1364 | struct drm_i915_error_state *error; | |
1365 | }; | |
1366 | ||
99584db3 DV |
1367 | struct i915_gpu_error { |
1368 | /* For hangcheck timer */ | |
1369 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1370 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1371 | /* Hang gpu twice in this window and your context gets banned */ |
1372 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1373 | ||
737b1506 CW |
1374 | struct workqueue_struct *hangcheck_wq; |
1375 | struct delayed_work hangcheck_work; | |
99584db3 DV |
1376 | |
1377 | /* For reset and error_state handling. */ | |
1378 | spinlock_t lock; | |
1379 | /* Protected by the above dev->gpu_error.lock. */ | |
1380 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1381 | |
1382 | unsigned long missed_irq_rings; | |
1383 | ||
1f83fee0 | 1384 | /** |
2ac0f450 | 1385 | * State variable controlling the reset flow and count |
1f83fee0 | 1386 | * |
2ac0f450 MK |
1387 | * This is a counter which gets incremented when reset is triggered, |
1388 | * and again when reset has been handled. So odd values (lowest bit set) | |
1389 | * means that reset is in progress and even values that | |
1390 | * (reset_counter >> 1):th reset was successfully completed. | |
1391 | * | |
1392 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1393 | * set meaning that hardware is terminally sour and there is no | |
1394 | * recovery. All waiters on the reset_queue will be woken when | |
1395 | * that happens. | |
1396 | * | |
1397 | * This counter is used by the wait_seqno code to notice that reset | |
1398 | * event happened and it needs to restart the entire ioctl (since most | |
1399 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1400 | * |
1401 | * This is important for lock-free wait paths, where no contended lock | |
1402 | * naturally enforces the correct ordering between the bail-out of the | |
1403 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1404 | */ |
1405 | atomic_t reset_counter; | |
1406 | ||
1f83fee0 | 1407 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1408 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1409 | |
1410 | /** | |
1411 | * Waitqueue to signal when the reset has completed. Used by clients | |
1412 | * that wait for dev_priv->mm.wedged to settle. | |
1413 | */ | |
1414 | wait_queue_head_t reset_queue; | |
33196ded | 1415 | |
88b4aa87 MK |
1416 | /* Userspace knobs for gpu hang simulation; |
1417 | * combines both a ring mask, and extra flags | |
1418 | */ | |
1419 | u32 stop_rings; | |
1420 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1421 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1422 | |
1423 | /* For missed irq/seqno simulation. */ | |
1424 | unsigned int test_irq_rings; | |
6689c167 MA |
1425 | |
1426 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1427 | bool reload_in_reset; | |
99584db3 DV |
1428 | }; |
1429 | ||
b8efb17b ZR |
1430 | enum modeset_restore { |
1431 | MODESET_ON_LID_OPEN, | |
1432 | MODESET_DONE, | |
1433 | MODESET_SUSPENDED, | |
1434 | }; | |
1435 | ||
500ea70d RV |
1436 | #define DP_AUX_A 0x40 |
1437 | #define DP_AUX_B 0x10 | |
1438 | #define DP_AUX_C 0x20 | |
1439 | #define DP_AUX_D 0x30 | |
1440 | ||
11c1b657 XZ |
1441 | #define DDC_PIN_B 0x05 |
1442 | #define DDC_PIN_C 0x04 | |
1443 | #define DDC_PIN_D 0x06 | |
1444 | ||
6acab15a | 1445 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1446 | /* |
1447 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1448 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1449 | * populate this field. | |
1450 | */ | |
1451 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1452 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1453 | |
1454 | uint8_t supports_dvi:1; | |
1455 | uint8_t supports_hdmi:1; | |
1456 | uint8_t supports_dp:1; | |
500ea70d RV |
1457 | |
1458 | uint8_t alternate_aux_channel; | |
11c1b657 | 1459 | uint8_t alternate_ddc_pin; |
75067dde AK |
1460 | |
1461 | uint8_t dp_boost_level; | |
1462 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1463 | }; |
1464 | ||
bfd7ebda RV |
1465 | enum psr_lines_to_wait { |
1466 | PSR_0_LINES_TO_WAIT = 0, | |
1467 | PSR_1_LINE_TO_WAIT, | |
1468 | PSR_4_LINES_TO_WAIT, | |
1469 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1470 | }; |
1471 | ||
41aa3448 RV |
1472 | struct intel_vbt_data { |
1473 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1474 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1475 | ||
1476 | /* Feature bits */ | |
1477 | unsigned int int_tv_support:1; | |
1478 | unsigned int lvds_dither:1; | |
1479 | unsigned int lvds_vbt:1; | |
1480 | unsigned int int_crt_support:1; | |
1481 | unsigned int lvds_use_ssc:1; | |
1482 | unsigned int display_clock_mode:1; | |
1483 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1484 | unsigned int has_mipi:1; |
41aa3448 RV |
1485 | int lvds_ssc_freq; |
1486 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1487 | ||
83a7280e PB |
1488 | enum drrs_support_type drrs_type; |
1489 | ||
41aa3448 RV |
1490 | /* eDP */ |
1491 | int edp_rate; | |
1492 | int edp_lanes; | |
1493 | int edp_preemphasis; | |
1494 | int edp_vswing; | |
1495 | bool edp_initialized; | |
1496 | bool edp_support; | |
1497 | int edp_bpp; | |
1498 | struct edp_power_seq edp_pps; | |
1499 | ||
bfd7ebda RV |
1500 | struct { |
1501 | bool full_link; | |
1502 | bool require_aux_wakeup; | |
1503 | int idle_frames; | |
1504 | enum psr_lines_to_wait lines_to_wait; | |
1505 | int tp1_wakeup_time; | |
1506 | int tp2_tp3_wakeup_time; | |
1507 | } psr; | |
1508 | ||
f00076d2 JN |
1509 | struct { |
1510 | u16 pwm_freq_hz; | |
39fbc9c8 | 1511 | bool present; |
f00076d2 | 1512 | bool active_low_pwm; |
1de6068e | 1513 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1514 | } backlight; |
1515 | ||
d17c5443 SK |
1516 | /* MIPI DSI */ |
1517 | struct { | |
3e6bd011 | 1518 | u16 port; |
d17c5443 | 1519 | u16 panel_id; |
d3b542fc SK |
1520 | struct mipi_config *config; |
1521 | struct mipi_pps_data *pps; | |
1522 | u8 seq_version; | |
1523 | u32 size; | |
1524 | u8 *data; | |
8d3ed2f3 | 1525 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1526 | } dsi; |
1527 | ||
41aa3448 RV |
1528 | int crt_ddc_pin; |
1529 | ||
1530 | int child_dev_num; | |
768f69c9 | 1531 | union child_device_config *child_dev; |
6acab15a PZ |
1532 | |
1533 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1534 | }; |
1535 | ||
77c122bc VS |
1536 | enum intel_ddb_partitioning { |
1537 | INTEL_DDB_PART_1_2, | |
1538 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1539 | }; | |
1540 | ||
1fd527cc VS |
1541 | struct intel_wm_level { |
1542 | bool enable; | |
1543 | uint32_t pri_val; | |
1544 | uint32_t spr_val; | |
1545 | uint32_t cur_val; | |
1546 | uint32_t fbc_val; | |
1547 | }; | |
1548 | ||
820c1980 | 1549 | struct ilk_wm_values { |
609cedef VS |
1550 | uint32_t wm_pipe[3]; |
1551 | uint32_t wm_lp[3]; | |
1552 | uint32_t wm_lp_spr[3]; | |
1553 | uint32_t wm_linetime[3]; | |
1554 | bool enable_fbc_wm; | |
1555 | enum intel_ddb_partitioning partitioning; | |
1556 | }; | |
1557 | ||
262cd2e1 VS |
1558 | struct vlv_pipe_wm { |
1559 | uint16_t primary; | |
1560 | uint16_t sprite[2]; | |
1561 | uint8_t cursor; | |
1562 | }; | |
ae80152d | 1563 | |
262cd2e1 VS |
1564 | struct vlv_sr_wm { |
1565 | uint16_t plane; | |
1566 | uint8_t cursor; | |
1567 | }; | |
ae80152d | 1568 | |
262cd2e1 VS |
1569 | struct vlv_wm_values { |
1570 | struct vlv_pipe_wm pipe[3]; | |
1571 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1572 | struct { |
1573 | uint8_t cursor; | |
1574 | uint8_t sprite[2]; | |
1575 | uint8_t primary; | |
1576 | } ddl[3]; | |
6eb1a681 VS |
1577 | uint8_t level; |
1578 | bool cxsr; | |
0018fda1 VS |
1579 | }; |
1580 | ||
c193924e | 1581 | struct skl_ddb_entry { |
16160e3d | 1582 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1583 | }; |
1584 | ||
1585 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1586 | { | |
16160e3d | 1587 | return entry->end - entry->start; |
c193924e DL |
1588 | } |
1589 | ||
08db6652 DL |
1590 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1591 | const struct skl_ddb_entry *e2) | |
1592 | { | |
1593 | if (e1->start == e2->start && e1->end == e2->end) | |
1594 | return true; | |
1595 | ||
1596 | return false; | |
1597 | } | |
1598 | ||
c193924e | 1599 | struct skl_ddb_allocation { |
34bb56af | 1600 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 | 1601 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1602 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1603 | }; |
1604 | ||
2ac96d2a PB |
1605 | struct skl_wm_values { |
1606 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1607 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1608 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1609 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
2ac96d2a | 1610 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
2ac96d2a PB |
1611 | }; |
1612 | ||
1613 | struct skl_wm_level { | |
1614 | bool plane_en[I915_MAX_PLANES]; | |
1615 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1616 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1617 | }; |
1618 | ||
c67a470b | 1619 | /* |
765dab67 PZ |
1620 | * This struct helps tracking the state needed for runtime PM, which puts the |
1621 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1622 | * graphics device works, even register access, so we don't get interrupts nor | |
1623 | * anything else. | |
c67a470b | 1624 | * |
765dab67 PZ |
1625 | * Every piece of our code that needs to actually touch the hardware needs to |
1626 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1627 | * appropriate power domain. | |
a8a8bd54 | 1628 | * |
765dab67 PZ |
1629 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1630 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1631 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1632 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1633 | * |
1634 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1635 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1636 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1637 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1638 | * case it happens. |
c67a470b | 1639 | * |
765dab67 | 1640 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1641 | */ |
5d584b2e | 1642 | struct i915_runtime_pm { |
1f814dac | 1643 | atomic_t wakeref_count; |
2b19efeb | 1644 | atomic_t atomic_seq; |
5d584b2e | 1645 | bool suspended; |
2aeb7d3a | 1646 | bool irqs_enabled; |
c67a470b PZ |
1647 | }; |
1648 | ||
926321d5 DV |
1649 | enum intel_pipe_crc_source { |
1650 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1651 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1652 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1653 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1654 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1655 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1656 | INTEL_PIPE_CRC_SOURCE_TV, | |
1657 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1658 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1659 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1660 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1661 | INTEL_PIPE_CRC_SOURCE_MAX, |
1662 | }; | |
1663 | ||
8bf1e9f1 | 1664 | struct intel_pipe_crc_entry { |
ac2300d4 | 1665 | uint32_t frame; |
8bf1e9f1 SH |
1666 | uint32_t crc[5]; |
1667 | }; | |
1668 | ||
b2c88f5b | 1669 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1670 | struct intel_pipe_crc { |
d538bbdf DL |
1671 | spinlock_t lock; |
1672 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1673 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1674 | enum intel_pipe_crc_source source; |
d538bbdf | 1675 | int head, tail; |
07144428 | 1676 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1677 | }; |
1678 | ||
f99d7069 DV |
1679 | struct i915_frontbuffer_tracking { |
1680 | struct mutex lock; | |
1681 | ||
1682 | /* | |
1683 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1684 | * scheduled flips. | |
1685 | */ | |
1686 | unsigned busy_bits; | |
1687 | unsigned flip_bits; | |
1688 | }; | |
1689 | ||
7225342a | 1690 | struct i915_wa_reg { |
f0f59a00 | 1691 | i915_reg_t addr; |
7225342a MK |
1692 | u32 value; |
1693 | /* bitmask representing WA bits */ | |
1694 | u32 mask; | |
1695 | }; | |
1696 | ||
33136b06 AS |
1697 | /* |
1698 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1699 | * allowing it for RCS as we don't foresee any requirement of having | |
1700 | * a whitelist for other engines. When it is really required for | |
1701 | * other engines then the limit need to be increased. | |
1702 | */ | |
1703 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
7225342a MK |
1704 | |
1705 | struct i915_workarounds { | |
1706 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1707 | u32 count; | |
33136b06 | 1708 | u32 hw_whitelist_count[I915_NUM_RINGS]; |
7225342a MK |
1709 | }; |
1710 | ||
cf9d2890 YZ |
1711 | struct i915_virtual_gpu { |
1712 | bool active; | |
1713 | }; | |
1714 | ||
5f19e2bf JH |
1715 | struct i915_execbuffer_params { |
1716 | struct drm_device *dev; | |
1717 | struct drm_file *file; | |
1718 | uint32_t dispatch_flags; | |
1719 | uint32_t args_batch_start_offset; | |
af98714e | 1720 | uint64_t batch_obj_vm_offset; |
5f19e2bf JH |
1721 | struct intel_engine_cs *ring; |
1722 | struct drm_i915_gem_object *batch_obj; | |
1723 | struct intel_context *ctx; | |
6a6ae79a | 1724 | struct drm_i915_gem_request *request; |
5f19e2bf JH |
1725 | }; |
1726 | ||
aa363136 MR |
1727 | /* used in computing the new watermarks state */ |
1728 | struct intel_wm_config { | |
1729 | unsigned int num_pipes_active; | |
1730 | bool sprites_enabled; | |
1731 | bool sprites_scaled; | |
1732 | }; | |
1733 | ||
77fec556 | 1734 | struct drm_i915_private { |
f4c956ad | 1735 | struct drm_device *dev; |
efab6d8d | 1736 | struct kmem_cache *objects; |
e20d2ab7 | 1737 | struct kmem_cache *vmas; |
efab6d8d | 1738 | struct kmem_cache *requests; |
f4c956ad | 1739 | |
5c969aa7 | 1740 | const struct intel_device_info info; |
f4c956ad DV |
1741 | |
1742 | int relative_constants_mode; | |
1743 | ||
1744 | void __iomem *regs; | |
1745 | ||
907b28c5 | 1746 | struct intel_uncore uncore; |
f4c956ad | 1747 | |
cf9d2890 YZ |
1748 | struct i915_virtual_gpu vgpu; |
1749 | ||
33a732f4 AD |
1750 | struct intel_guc guc; |
1751 | ||
eb805623 DV |
1752 | struct intel_csr csr; |
1753 | ||
5ea6e5e3 | 1754 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1755 | |
f4c956ad DV |
1756 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1757 | * controller on different i2c buses. */ | |
1758 | struct mutex gmbus_mutex; | |
1759 | ||
1760 | /** | |
1761 | * Base address of the gmbus and gpio block. | |
1762 | */ | |
1763 | uint32_t gpio_mmio_base; | |
1764 | ||
b6fdd0f2 SS |
1765 | /* MMIO base address for MIPI regs */ |
1766 | uint32_t mipi_mmio_base; | |
1767 | ||
443a389f VS |
1768 | uint32_t psr_mmio_base; |
1769 | ||
28c70f16 DV |
1770 | wait_queue_head_t gmbus_wait_queue; |
1771 | ||
f4c956ad | 1772 | struct pci_dev *bridge_dev; |
a4872ba6 | 1773 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1774 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1775 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1776 | |
ba8286fa | 1777 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1778 | struct resource mch_res; |
1779 | ||
f4c956ad DV |
1780 | /* protects the irq masks */ |
1781 | spinlock_t irq_lock; | |
1782 | ||
84c33a64 SG |
1783 | /* protects the mmio flip data */ |
1784 | spinlock_t mmio_flip_lock; | |
1785 | ||
f8b79e58 ID |
1786 | bool display_irqs_enabled; |
1787 | ||
9ee32fea DV |
1788 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1789 | struct pm_qos_request pm_qos; | |
1790 | ||
a580516d VS |
1791 | /* Sideband mailbox protection */ |
1792 | struct mutex sb_lock; | |
f4c956ad DV |
1793 | |
1794 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1795 | union { |
1796 | u32 irq_mask; | |
1797 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1798 | }; | |
f4c956ad | 1799 | u32 gt_irq_mask; |
605cd25b | 1800 | u32 pm_irq_mask; |
a6706b45 | 1801 | u32 pm_rps_events; |
91d181dd | 1802 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1803 | |
5fcece80 | 1804 | struct i915_hotplug hotplug; |
ab34a7e8 | 1805 | struct intel_fbc fbc; |
439d7ac0 | 1806 | struct i915_drrs drrs; |
f4c956ad | 1807 | struct intel_opregion opregion; |
41aa3448 | 1808 | struct intel_vbt_data vbt; |
f4c956ad | 1809 | |
d9ceb816 JB |
1810 | bool preserve_bios_swizzle; |
1811 | ||
f4c956ad DV |
1812 | /* overlay */ |
1813 | struct intel_overlay *overlay; | |
f4c956ad | 1814 | |
58c68779 | 1815 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1816 | struct mutex backlight_lock; |
31ad8ec6 | 1817 | |
f4c956ad | 1818 | /* LVDS info */ |
f4c956ad DV |
1819 | bool no_aux_handshake; |
1820 | ||
e39b999a VS |
1821 | /* protects panel power sequencer state */ |
1822 | struct mutex pps_mutex; | |
1823 | ||
f4c956ad | 1824 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1825 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1826 | ||
1827 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
5d96d8af | 1828 | unsigned int skl_boot_cdclk; |
1a617b77 | 1829 | unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; |
adafdc6f | 1830 | unsigned int max_dotclk_freq; |
6bcda4f0 | 1831 | unsigned int hpll_freq; |
bfa7df01 | 1832 | unsigned int czclk_freq; |
f4c956ad | 1833 | |
645416f5 DV |
1834 | /** |
1835 | * wq - Driver workqueue for GEM. | |
1836 | * | |
1837 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1838 | * locks, for otherwise the flushing done in the pageflip code will | |
1839 | * result in deadlocks. | |
1840 | */ | |
f4c956ad DV |
1841 | struct workqueue_struct *wq; |
1842 | ||
1843 | /* Display functions */ | |
1844 | struct drm_i915_display_funcs display; | |
1845 | ||
1846 | /* PCH chipset type */ | |
1847 | enum intel_pch pch_type; | |
17a303ec | 1848 | unsigned short pch_id; |
f4c956ad DV |
1849 | |
1850 | unsigned long quirks; | |
1851 | ||
b8efb17b ZR |
1852 | enum modeset_restore modeset_restore; |
1853 | struct mutex modeset_restore_lock; | |
673a394b | 1854 | |
a7bbbd63 | 1855 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1856 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1857 | |
4b5aed62 | 1858 | struct i915_gem_mm mm; |
ad46cb53 CW |
1859 | DECLARE_HASHTABLE(mm_structs, 7); |
1860 | struct mutex mm_lock; | |
8781342d | 1861 | |
8781342d DV |
1862 | /* Kernel Modesetting */ |
1863 | ||
9b9d172d | 1864 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1865 | |
76c4ac04 DL |
1866 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1867 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1868 | wait_queue_head_t pending_flip_queue; |
1869 | ||
c4597872 DV |
1870 | #ifdef CONFIG_DEBUG_FS |
1871 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1872 | #endif | |
1873 | ||
565602d7 | 1874 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
1875 | int num_shared_dpll; |
1876 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
565602d7 ML |
1877 | |
1878 | unsigned int active_crtcs; | |
1879 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
1880 | ||
e4607fcf | 1881 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1882 | |
7225342a | 1883 | struct i915_workarounds workarounds; |
888b5995 | 1884 | |
652c393a JB |
1885 | /* Reclocking support */ |
1886 | bool render_reclock_avail; | |
f99d7069 DV |
1887 | |
1888 | struct i915_frontbuffer_tracking fb_tracking; | |
1889 | ||
652c393a | 1890 | u16 orig_clock; |
f97108d1 | 1891 | |
c4804411 | 1892 | bool mchbar_need_disable; |
f97108d1 | 1893 | |
a4da4fa4 DV |
1894 | struct intel_l3_parity l3_parity; |
1895 | ||
59124506 BW |
1896 | /* Cannot be determined by PCIID. You must always read a register. */ |
1897 | size_t ellc_size; | |
1898 | ||
c6a828d3 | 1899 | /* gen6+ rps state */ |
c85aa885 | 1900 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1901 | |
20e4d407 DV |
1902 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1903 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1904 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1905 | |
83c00f55 | 1906 | struct i915_power_domains power_domains; |
a38911a3 | 1907 | |
a031d709 | 1908 | struct i915_psr psr; |
3f51e471 | 1909 | |
99584db3 | 1910 | struct i915_gpu_error gpu_error; |
ae681d96 | 1911 | |
c9cddffc JB |
1912 | struct drm_i915_gem_object *vlv_pctx; |
1913 | ||
0695726e | 1914 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
1915 | /* list of fbdev register on this device */ |
1916 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1917 | struct work_struct fbdev_suspend_work; |
4520f53a | 1918 | #endif |
e953fd7b CW |
1919 | |
1920 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1921 | struct drm_property *force_audio_property; |
e3689190 | 1922 | |
58fddc28 | 1923 | /* hda/i915 audio component */ |
51e1d83c | 1924 | struct i915_audio_component *audio_component; |
58fddc28 | 1925 | bool audio_component_registered; |
4a21ef7d LY |
1926 | /** |
1927 | * av_mutex - mutex for audio/video sync | |
1928 | * | |
1929 | */ | |
1930 | struct mutex av_mutex; | |
58fddc28 | 1931 | |
254f965c | 1932 | uint32_t hw_context_size; |
a33afea5 | 1933 | struct list_head context_list; |
f4c956ad | 1934 | |
3e68320e | 1935 | u32 fdi_rx_config; |
68d18ad7 | 1936 | |
70722468 VS |
1937 | u32 chv_phy_control; |
1938 | ||
842f1c8b | 1939 | u32 suspend_count; |
bc87229f | 1940 | bool suspended_to_idle; |
f4c956ad | 1941 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1942 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1943 | |
53615a5e VS |
1944 | struct { |
1945 | /* | |
1946 | * Raw watermark latency values: | |
1947 | * in 0.1us units for WM0, | |
1948 | * in 0.5us units for WM1+. | |
1949 | */ | |
1950 | /* primary */ | |
1951 | uint16_t pri_latency[5]; | |
1952 | /* sprite */ | |
1953 | uint16_t spr_latency[5]; | |
1954 | /* cursor */ | |
1955 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1956 | /* |
1957 | * Raw watermark memory latency values | |
1958 | * for SKL for all 8 levels | |
1959 | * in 1us units. | |
1960 | */ | |
1961 | uint16_t skl_latency[8]; | |
609cedef | 1962 | |
aa363136 MR |
1963 | /* Committed wm config */ |
1964 | struct intel_wm_config config; | |
1965 | ||
2d41c0b5 PB |
1966 | /* |
1967 | * The skl_wm_values structure is a bit too big for stack | |
1968 | * allocation, so we keep the staging struct where we store | |
1969 | * intermediate results here instead. | |
1970 | */ | |
1971 | struct skl_wm_values skl_results; | |
1972 | ||
609cedef | 1973 | /* current hardware state */ |
2d41c0b5 PB |
1974 | union { |
1975 | struct ilk_wm_values hw; | |
1976 | struct skl_wm_values skl_hw; | |
0018fda1 | 1977 | struct vlv_wm_values vlv; |
2d41c0b5 | 1978 | }; |
58590c14 VS |
1979 | |
1980 | uint8_t max_level; | |
53615a5e VS |
1981 | } wm; |
1982 | ||
8a187455 PZ |
1983 | struct i915_runtime_pm pm; |
1984 | ||
a83014d3 OM |
1985 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1986 | struct { | |
5f19e2bf | 1987 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
f3dc74c0 | 1988 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1989 | struct list_head *vmas); |
a83014d3 OM |
1990 | int (*init_rings)(struct drm_device *dev); |
1991 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1992 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1993 | } gt; | |
1994 | ||
ed54c1a1 DG |
1995 | struct intel_context *kernel_context; |
1996 | ||
9e458034 SJ |
1997 | bool edp_low_vswing; |
1998 | ||
3be60de9 VS |
1999 | /* perform PHY state sanity checks? */ |
2000 | bool chv_phy_assert[2]; | |
2001 | ||
0bdf5a05 TI |
2002 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
2003 | ||
bdf1e7e3 DV |
2004 | /* |
2005 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2006 | * will be rejected. Instead look for a better place. | |
2007 | */ | |
77fec556 | 2008 | }; |
1da177e4 | 2009 | |
2c1792a1 CW |
2010 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2011 | { | |
2012 | return dev->dev_private; | |
2013 | } | |
2014 | ||
888d0d42 ID |
2015 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
2016 | { | |
2017 | return to_i915(dev_get_drvdata(dev)); | |
2018 | } | |
2019 | ||
33a732f4 AD |
2020 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2021 | { | |
2022 | return container_of(guc, struct drm_i915_private, guc); | |
2023 | } | |
2024 | ||
b4519513 CW |
2025 | /* Iterate over initialised rings */ |
2026 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
2027 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
95150bdf | 2028 | for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))) |
b4519513 | 2029 | |
b1d7e4b4 WF |
2030 | enum hdmi_force_audio { |
2031 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2032 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2033 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2034 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2035 | }; | |
2036 | ||
190d6cd5 | 2037 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2038 | |
37e680a1 CW |
2039 | struct drm_i915_gem_object_ops { |
2040 | /* Interface between the GEM object and its backing storage. | |
2041 | * get_pages() is called once prior to the use of the associated set | |
2042 | * of pages before to binding them into the GTT, and put_pages() is | |
2043 | * called after we no longer need them. As we expect there to be | |
2044 | * associated cost with migrating pages between the backing storage | |
2045 | * and making them available for the GPU (e.g. clflush), we may hold | |
2046 | * onto the pages after they are no longer referenced by the GPU | |
2047 | * in case they may be used again shortly (for example migrating the | |
2048 | * pages to a different memory domain within the GTT). put_pages() | |
2049 | * will therefore most likely be called when the object itself is | |
2050 | * being released or under memory pressure (where we attempt to | |
2051 | * reap pages for the shrinker). | |
2052 | */ | |
2053 | int (*get_pages)(struct drm_i915_gem_object *); | |
2054 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
2055 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2056 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
2057 | }; |
2058 | ||
a071fa00 DV |
2059 | /* |
2060 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2061 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2062 | * doesn't mean that the hw necessarily already scans it out, but that any |
2063 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2064 | * | |
2065 | * We have one bit per pipe and per scanout plane type. | |
2066 | */ | |
d1b9d039 SAK |
2067 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2068 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2069 | #define INTEL_FRONTBUFFER_BITS \ |
2070 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
2071 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
2072 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2073 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2074 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2075 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2076 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2077 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2078 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2079 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2080 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2081 | |
673a394b | 2082 | struct drm_i915_gem_object { |
c397b908 | 2083 | struct drm_gem_object base; |
673a394b | 2084 | |
37e680a1 CW |
2085 | const struct drm_i915_gem_object_ops *ops; |
2086 | ||
2f633156 BW |
2087 | /** List of VMAs backed by this object */ |
2088 | struct list_head vma_list; | |
2089 | ||
c1ad11fc CW |
2090 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2091 | struct drm_mm_node *stolen; | |
35c20a60 | 2092 | struct list_head global_list; |
673a394b | 2093 | |
b4716185 | 2094 | struct list_head ring_list[I915_NUM_RINGS]; |
b25cb2f8 BW |
2095 | /** Used in execbuf to temporarily hold a ref */ |
2096 | struct list_head obj_exec_link; | |
673a394b | 2097 | |
8d9d5744 | 2098 | struct list_head batch_pool_link; |
493018dc | 2099 | |
673a394b | 2100 | /** |
65ce3027 CW |
2101 | * This is set if the object is on the active lists (has pending |
2102 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2103 | * inactive (ready to be unbound) list. | |
673a394b | 2104 | */ |
b4716185 | 2105 | unsigned int active:I915_NUM_RINGS; |
673a394b EA |
2106 | |
2107 | /** | |
2108 | * This is set if the object has been written to since last bound | |
2109 | * to the GTT | |
2110 | */ | |
0206e353 | 2111 | unsigned int dirty:1; |
778c3544 DV |
2112 | |
2113 | /** | |
2114 | * Fence register bits (if any) for this object. Will be set | |
2115 | * as needed when mapped into the GTT. | |
2116 | * Protected by dev->struct_mutex. | |
778c3544 | 2117 | */ |
4b9de737 | 2118 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 2119 | |
778c3544 DV |
2120 | /** |
2121 | * Advice: are the backing pages purgeable? | |
2122 | */ | |
0206e353 | 2123 | unsigned int madv:2; |
778c3544 | 2124 | |
778c3544 DV |
2125 | /** |
2126 | * Current tiling mode for the object. | |
2127 | */ | |
0206e353 | 2128 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
2129 | /** |
2130 | * Whether the tiling parameters for the currently associated fence | |
2131 | * register have changed. Note that for the purposes of tracking | |
2132 | * tiling changes we also treat the unfenced register, the register | |
2133 | * slot that the object occupies whilst it executes a fenced | |
2134 | * command (such as BLT on gen2/3), as a "fence". | |
2135 | */ | |
2136 | unsigned int fence_dirty:1; | |
778c3544 | 2137 | |
75e9e915 DV |
2138 | /** |
2139 | * Is the object at the current location in the gtt mappable and | |
2140 | * fenceable? Used to avoid costly recalculations. | |
2141 | */ | |
0206e353 | 2142 | unsigned int map_and_fenceable:1; |
75e9e915 | 2143 | |
fb7d516a DV |
2144 | /** |
2145 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2146 | * mappable by accident). Track pin and fault separate for a more | |
2147 | * accurate mappable working set. | |
2148 | */ | |
0206e353 | 2149 | unsigned int fault_mappable:1; |
fb7d516a | 2150 | |
24f3a8cf AG |
2151 | /* |
2152 | * Is the object to be mapped as read-only to the GPU | |
2153 | * Only honoured if hardware has relevant pte bit | |
2154 | */ | |
2155 | unsigned long gt_ro:1; | |
651d794f | 2156 | unsigned int cache_level:3; |
0f71979a | 2157 | unsigned int cache_dirty:1; |
93dfb40c | 2158 | |
a071fa00 DV |
2159 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2160 | ||
8a0c39b1 TU |
2161 | unsigned int pin_display; |
2162 | ||
9da3da66 | 2163 | struct sg_table *pages; |
a5570178 | 2164 | int pages_pin_count; |
ee286370 CW |
2165 | struct get_page { |
2166 | struct scatterlist *sg; | |
2167 | int last; | |
2168 | } get_page; | |
673a394b | 2169 | |
1286ff73 | 2170 | /* prime dma-buf support */ |
9a70cc2a DA |
2171 | void *dma_buf_vmapping; |
2172 | int vmapping_count; | |
2173 | ||
b4716185 CW |
2174 | /** Breadcrumb of last rendering to the buffer. |
2175 | * There can only be one writer, but we allow for multiple readers. | |
2176 | * If there is a writer that necessarily implies that all other | |
2177 | * read requests are complete - but we may only be lazily clearing | |
2178 | * the read requests. A read request is naturally the most recent | |
2179 | * request on a ring, so we may have two different write and read | |
2180 | * requests on one ring where the write request is older than the | |
2181 | * read request. This allows for the CPU to read from an active | |
2182 | * buffer by only waiting for the write to complete. | |
2183 | * */ | |
2184 | struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; | |
97b2a6a1 | 2185 | struct drm_i915_gem_request *last_write_req; |
caea7476 | 2186 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 2187 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 2188 | |
778c3544 | 2189 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 2190 | uint32_t stride; |
673a394b | 2191 | |
80075d49 DV |
2192 | /** References from framebuffers, locks out tiling changes. */ |
2193 | unsigned long framebuffer_references; | |
2194 | ||
280b713b | 2195 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2196 | unsigned long *bit_17; |
280b713b | 2197 | |
5cc9ed4b | 2198 | union { |
6a2c4232 CW |
2199 | /** for phy allocated objects */ |
2200 | struct drm_dma_handle *phys_handle; | |
2201 | ||
5cc9ed4b CW |
2202 | struct i915_gem_userptr { |
2203 | uintptr_t ptr; | |
2204 | unsigned read_only :1; | |
2205 | unsigned workers :4; | |
2206 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2207 | ||
ad46cb53 CW |
2208 | struct i915_mm_struct *mm; |
2209 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2210 | struct work_struct *work; |
2211 | } userptr; | |
2212 | }; | |
2213 | }; | |
62b8b215 | 2214 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 2215 | |
a071fa00 DV |
2216 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2217 | struct drm_i915_gem_object *new, | |
2218 | unsigned frontbuffer_bits); | |
2219 | ||
673a394b EA |
2220 | /** |
2221 | * Request queue structure. | |
2222 | * | |
2223 | * The request queue allows us to note sequence numbers that have been emitted | |
2224 | * and may be associated with active buffers to be retired. | |
2225 | * | |
97b2a6a1 JH |
2226 | * By keeping this list, we can avoid having to do questionable sequence |
2227 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2228 | * emission time to be associated with the request for tracking how far ahead | |
2229 | * of the GPU the submission is. | |
b3a38998 NH |
2230 | * |
2231 | * The requests are reference counted, so upon creation they should have an | |
2232 | * initial reference taken using kref_init | |
673a394b EA |
2233 | */ |
2234 | struct drm_i915_gem_request { | |
abfe262a JH |
2235 | struct kref ref; |
2236 | ||
852835f3 | 2237 | /** On Which ring this request was generated */ |
efab6d8d | 2238 | struct drm_i915_private *i915; |
a4872ba6 | 2239 | struct intel_engine_cs *ring; |
852835f3 | 2240 | |
821485dc CW |
2241 | /** GEM sequence number associated with the previous request, |
2242 | * when the HWS breadcrumb is equal to this the GPU is processing | |
2243 | * this request. | |
2244 | */ | |
2245 | u32 previous_seqno; | |
2246 | ||
2247 | /** GEM sequence number associated with this request, | |
2248 | * when the HWS breadcrumb is equal or greater than this the GPU | |
2249 | * has finished processing this request. | |
2250 | */ | |
2251 | u32 seqno; | |
673a394b | 2252 | |
7d736f4f MK |
2253 | /** Position in the ringbuffer of the start of the request */ |
2254 | u32 head; | |
2255 | ||
72f95afa NH |
2256 | /** |
2257 | * Position in the ringbuffer of the start of the postfix. | |
2258 | * This is required to calculate the maximum available ringbuffer | |
2259 | * space without overwriting the postfix. | |
2260 | */ | |
2261 | u32 postfix; | |
2262 | ||
2263 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2264 | u32 tail; |
2265 | ||
b3a38998 | 2266 | /** |
a8c6ecb3 | 2267 | * Context and ring buffer related to this request |
b3a38998 NH |
2268 | * Contexts are refcounted, so when this request is associated with a |
2269 | * context, we must increment the context's refcount, to guarantee that | |
2270 | * it persists while any request is linked to it. Requests themselves | |
2271 | * are also refcounted, so the request will only be freed when the last | |
2272 | * reference to it is dismissed, and the code in | |
2273 | * i915_gem_request_free() will then decrement the refcount on the | |
2274 | * context. | |
2275 | */ | |
273497e5 | 2276 | struct intel_context *ctx; |
98e1bd4a | 2277 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2278 | |
dc4be607 JH |
2279 | /** Batch buffer related to this request if any (used for |
2280 | error state dump only) */ | |
7d736f4f MK |
2281 | struct drm_i915_gem_object *batch_obj; |
2282 | ||
673a394b EA |
2283 | /** Time at which this request was emitted, in jiffies. */ |
2284 | unsigned long emitted_jiffies; | |
2285 | ||
b962442e | 2286 | /** global list entry for this request */ |
673a394b | 2287 | struct list_head list; |
b962442e | 2288 | |
f787a5f5 | 2289 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2290 | /** file_priv list entry for this request */ |
2291 | struct list_head client_list; | |
67e2937b | 2292 | |
071c92de MK |
2293 | /** process identifier submitting this request */ |
2294 | struct pid *pid; | |
2295 | ||
6d3d8274 NH |
2296 | /** |
2297 | * The ELSP only accepts two elements at a time, so we queue | |
2298 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2299 | * hardware is available. The queue serves a double purpose: we also use | |
2300 | * it to keep track of the up to 2 contexts currently in the hardware | |
2301 | * (usually one in execution and the other queued up by the GPU): We | |
2302 | * only remove elements from the head of the queue when the hardware | |
2303 | * informs us that an element has been completed. | |
2304 | * | |
2305 | * All accesses to the queue are mediated by a spinlock | |
2306 | * (ring->execlist_lock). | |
2307 | */ | |
2308 | ||
2309 | /** Execlist link in the submission queue.*/ | |
2310 | struct list_head execlist_link; | |
2311 | ||
2312 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2313 | int elsp_submitted; | |
2314 | ||
673a394b EA |
2315 | }; |
2316 | ||
26827088 DG |
2317 | struct drm_i915_gem_request * __must_check |
2318 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
2319 | struct intel_context *ctx); | |
29b1b415 | 2320 | void i915_gem_request_cancel(struct drm_i915_gem_request *req); |
abfe262a | 2321 | void i915_gem_request_free(struct kref *req_ref); |
fcfa423c JH |
2322 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
2323 | struct drm_file *file); | |
abfe262a | 2324 | |
b793a00a JH |
2325 | static inline uint32_t |
2326 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2327 | { | |
2328 | return req ? req->seqno : 0; | |
2329 | } | |
2330 | ||
2331 | static inline struct intel_engine_cs * | |
2332 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2333 | { | |
2334 | return req ? req->ring : NULL; | |
2335 | } | |
2336 | ||
b2cfe0ab | 2337 | static inline struct drm_i915_gem_request * |
abfe262a JH |
2338 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2339 | { | |
b2cfe0ab CW |
2340 | if (req) |
2341 | kref_get(&req->ref); | |
2342 | return req; | |
abfe262a JH |
2343 | } |
2344 | ||
2345 | static inline void | |
2346 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2347 | { | |
f245860e | 2348 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
abfe262a JH |
2349 | kref_put(&req->ref, i915_gem_request_free); |
2350 | } | |
2351 | ||
41037f9f CW |
2352 | static inline void |
2353 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) | |
2354 | { | |
b833bb61 ML |
2355 | struct drm_device *dev; |
2356 | ||
2357 | if (!req) | |
2358 | return; | |
41037f9f | 2359 | |
b833bb61 ML |
2360 | dev = req->ring->dev; |
2361 | if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) | |
41037f9f | 2362 | mutex_unlock(&dev->struct_mutex); |
41037f9f CW |
2363 | } |
2364 | ||
abfe262a JH |
2365 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
2366 | struct drm_i915_gem_request *src) | |
2367 | { | |
2368 | if (src) | |
2369 | i915_gem_request_reference(src); | |
2370 | ||
2371 | if (*pdst) | |
2372 | i915_gem_request_unreference(*pdst); | |
2373 | ||
2374 | *pdst = src; | |
2375 | } | |
2376 | ||
1b5a433a JH |
2377 | /* |
2378 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2379 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2380 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2381 | */ | |
2382 | ||
351e3db2 BV |
2383 | /* |
2384 | * A command that requires special handling by the command parser. | |
2385 | */ | |
2386 | struct drm_i915_cmd_descriptor { | |
2387 | /* | |
2388 | * Flags describing how the command parser processes the command. | |
2389 | * | |
2390 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2391 | * a length mask if not set | |
2392 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2393 | * standard length encoding for the opcode range in | |
2394 | * which it falls | |
2395 | * CMD_DESC_REJECT: The command is never allowed | |
2396 | * CMD_DESC_REGISTER: The command should be checked against the | |
2397 | * register whitelist for the appropriate ring | |
2398 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2399 | * is the DRM master | |
2400 | */ | |
2401 | u32 flags; | |
2402 | #define CMD_DESC_FIXED (1<<0) | |
2403 | #define CMD_DESC_SKIP (1<<1) | |
2404 | #define CMD_DESC_REJECT (1<<2) | |
2405 | #define CMD_DESC_REGISTER (1<<3) | |
2406 | #define CMD_DESC_BITMASK (1<<4) | |
2407 | #define CMD_DESC_MASTER (1<<5) | |
2408 | ||
2409 | /* | |
2410 | * The command's unique identification bits and the bitmask to get them. | |
2411 | * This isn't strictly the opcode field as defined in the spec and may | |
2412 | * also include type, subtype, and/or subop fields. | |
2413 | */ | |
2414 | struct { | |
2415 | u32 value; | |
2416 | u32 mask; | |
2417 | } cmd; | |
2418 | ||
2419 | /* | |
2420 | * The command's length. The command is either fixed length (i.e. does | |
2421 | * not include a length field) or has a length field mask. The flag | |
2422 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2423 | * a length mask. All command entries in a command table must include | |
2424 | * length information. | |
2425 | */ | |
2426 | union { | |
2427 | u32 fixed; | |
2428 | u32 mask; | |
2429 | } length; | |
2430 | ||
2431 | /* | |
2432 | * Describes where to find a register address in the command to check | |
2433 | * against the ring's register whitelist. Only valid if flags has the | |
2434 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2435 | * |
2436 | * A non-zero step value implies that the command may access multiple | |
2437 | * registers in sequence (e.g. LRI), in that case step gives the | |
2438 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2439 | */ |
2440 | struct { | |
2441 | u32 offset; | |
2442 | u32 mask; | |
6a65c5b9 | 2443 | u32 step; |
351e3db2 BV |
2444 | } reg; |
2445 | ||
2446 | #define MAX_CMD_DESC_BITMASKS 3 | |
2447 | /* | |
2448 | * Describes command checks where a particular dword is masked and | |
2449 | * compared against an expected value. If the command does not match | |
2450 | * the expected value, the parser rejects it. Only valid if flags has | |
2451 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2452 | * are valid. | |
d4d48035 BV |
2453 | * |
2454 | * If the check specifies a non-zero condition_mask then the parser | |
2455 | * only performs the check when the bits specified by condition_mask | |
2456 | * are non-zero. | |
351e3db2 BV |
2457 | */ |
2458 | struct { | |
2459 | u32 offset; | |
2460 | u32 mask; | |
2461 | u32 expected; | |
d4d48035 BV |
2462 | u32 condition_offset; |
2463 | u32 condition_mask; | |
351e3db2 BV |
2464 | } bits[MAX_CMD_DESC_BITMASKS]; |
2465 | }; | |
2466 | ||
2467 | /* | |
2468 | * A table of commands requiring special handling by the command parser. | |
2469 | * | |
2470 | * Each ring has an array of tables. Each table consists of an array of command | |
2471 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2472 | */ | |
2473 | struct drm_i915_cmd_table { | |
2474 | const struct drm_i915_cmd_descriptor *table; | |
2475 | int count; | |
2476 | }; | |
2477 | ||
dbbe9127 | 2478 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2479 | #define __I915__(p) ({ \ |
2480 | struct drm_i915_private *__p; \ | |
2481 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2482 | __p = (struct drm_i915_private *)p; \ | |
2483 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2484 | __p = to_i915((struct drm_device *)p); \ | |
2485 | else \ | |
2486 | BUILD_BUG(); \ | |
2487 | __p; \ | |
2488 | }) | |
dbbe9127 | 2489 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2490 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
e90a21d4 | 2491 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
cae5852d | 2492 | |
e87a005d JN |
2493 | #define REVID_FOREVER 0xff |
2494 | /* | |
2495 | * Return true if revision is in range [since,until] inclusive. | |
2496 | * | |
2497 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2498 | */ | |
2499 | #define IS_REVID(p, since, until) \ | |
2500 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2501 | ||
87f1f465 CW |
2502 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2503 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2504 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2505 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2506 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2507 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2508 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2509 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2510 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2511 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2512 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2513 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2514 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2515 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2516 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2517 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2518 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2519 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2520 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2521 | INTEL_DEVID(dev) == 0x0152 || \ | |
2522 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2523 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
666a4537 | 2524 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
4cae9ae0 | 2525 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
666a4537 | 2526 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev)) |
7201c0b3 | 2527 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
7526ac19 | 2528 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
ef11bdb3 | 2529 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
cae5852d | 2530 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2531 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2532 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2533 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2534 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2535 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2536 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2537 | /* ULX machines are also considered ULT. */ |
2538 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2539 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2540 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2541 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2542 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2543 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2544 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2545 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2546 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2547 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2548 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2549 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2550 | INTEL_DEVID(dev) == 0x1913 || \ | |
2551 | INTEL_DEVID(dev) == 0x1916 || \ | |
2552 | INTEL_DEVID(dev) == 0x1921 || \ | |
2553 | INTEL_DEVID(dev) == 0x1926) | |
2554 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2555 | INTEL_DEVID(dev) == 0x1915 || \ | |
2556 | INTEL_DEVID(dev) == 0x191E) | |
a5b7991c RV |
2557 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
2558 | INTEL_DEVID(dev) == 0x5913 || \ | |
2559 | INTEL_DEVID(dev) == 0x5916 || \ | |
2560 | INTEL_DEVID(dev) == 0x5921 || \ | |
2561 | INTEL_DEVID(dev) == 0x5926) | |
2562 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ | |
2563 | INTEL_DEVID(dev) == 0x5915 || \ | |
2564 | INTEL_DEVID(dev) == 0x591E) | |
7a58bad0 SAK |
2565 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2566 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2567 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2568 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2569 | ||
b833d685 | 2570 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2571 | |
ef712bb4 JN |
2572 | #define SKL_REVID_A0 0x0 |
2573 | #define SKL_REVID_B0 0x1 | |
2574 | #define SKL_REVID_C0 0x2 | |
2575 | #define SKL_REVID_D0 0x3 | |
2576 | #define SKL_REVID_E0 0x4 | |
2577 | #define SKL_REVID_F0 0x5 | |
2578 | ||
e87a005d JN |
2579 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2580 | ||
ef712bb4 | 2581 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2582 | #define BXT_REVID_A1 0x1 |
ef712bb4 JN |
2583 | #define BXT_REVID_B0 0x3 |
2584 | #define BXT_REVID_C0 0x9 | |
6c74c87f | 2585 | |
e87a005d JN |
2586 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2587 | ||
85436696 JB |
2588 | /* |
2589 | * The genX designation typically refers to the render engine, so render | |
2590 | * capability related checks should use IS_GEN, while display and other checks | |
2591 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2592 | * chips, etc.). | |
2593 | */ | |
cae5852d ZN |
2594 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2595 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2596 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2597 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2598 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2599 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2600 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2601 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2602 | |
73ae478c BW |
2603 | #define RENDER_RING (1<<RCS) |
2604 | #define BSD_RING (1<<VCS) | |
2605 | #define BLT_RING (1<<BCS) | |
2606 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2607 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2608 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2609 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2610 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2611 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2612 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2613 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
f2fbc690 | 2614 | __I915__(dev)->ellc_size) |
cae5852d ZN |
2615 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2616 | ||
254f965c | 2617 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2618 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c | 2619 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2620 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2621 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2622 | |
05394f39 | 2623 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2624 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2625 | ||
b45305fc DV |
2626 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2627 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
06e668ac MK |
2628 | |
2629 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
2630 | #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \ | |
2631 | ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \ | |
2632 | IS_SKL_REVID(dev, 0, SKL_REVID_F0))) | |
4e6b788c DV |
2633 | /* |
2634 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2635 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2636 | * legacy irq no. is shared with another device. The kernel then disables that | |
2637 | * interrupt source and so prevents the other device from working properly. | |
2638 | */ | |
2639 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2640 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2641 | |
cae5852d ZN |
2642 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2643 | * rows, which changed the alignment requirements and fence programming. | |
2644 | */ | |
2645 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2646 | IS_I915GM(dev))) | |
cae5852d ZN |
2647 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2648 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2649 | |
2650 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2651 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2652 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2653 | |
dbf7786e | 2654 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2655 | |
0c9b3715 JN |
2656 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2657 | INTEL_INFO(dev)->gen >= 9) | |
2658 | ||
dd93be58 | 2659 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2660 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2661 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 | 2662 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
ef11bdb3 | 2663 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
6157d3c8 | 2664 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 | 2665 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
666a4537 WB |
2666 | IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \ |
2667 | IS_KABYLAKE(dev)) | |
58abf1da RV |
2668 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2669 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2670 | |
7b403ffb | 2671 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
eb805623 | 2672 | |
2b81b844 RV |
2673 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) |
2674 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) | |
33a732f4 | 2675 | |
a9ed33ca AJ |
2676 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2677 | INTEL_INFO(dev)->gen >= 8) | |
2678 | ||
97d3308a | 2679 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
666a4537 WB |
2680 | !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ |
2681 | !IS_BROXTON(dev)) | |
97d3308a | 2682 | |
17a303ec PZ |
2683 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2684 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2685 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2686 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2687 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2688 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2689 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2690 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
30c964a6 | 2691 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
39bfcd52 | 2692 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2693 | |
f2fbc690 | 2694 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2695 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2696 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
c2699524 | 2697 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
56f5f700 | 2698 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
cae5852d ZN |
2699 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2700 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2701 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2702 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2703 | |
666a4537 WB |
2704 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ |
2705 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
5fafe292 | 2706 | |
040d2baa BW |
2707 | /* DPF == dynamic parity feature */ |
2708 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2709 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2710 | |
c8735b0c | 2711 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2712 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2713 | |
05394f39 CW |
2714 | #include "i915_trace.h" |
2715 | ||
baa70943 | 2716 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2717 | extern int i915_max_ioctl; |
2718 | ||
1751fcf9 ML |
2719 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2720 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2721 | |
c838d719 | 2722 | /* i915_dma.c */ |
22eae947 | 2723 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2724 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2725 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2726 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2727 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2728 | struct drm_file *file); |
673a394b | 2729 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2730 | struct drm_file *file); |
c43b5634 | 2731 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2732 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2733 | unsigned long arg); | |
c43b5634 | 2734 | #endif |
8e96d9c4 | 2735 | extern int intel_gpu_reset(struct drm_device *dev); |
49e4d842 | 2736 | extern bool intel_has_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2737 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2738 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2739 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2740 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2741 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2742 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2743 | |
77913b39 JN |
2744 | /* intel_hotplug.c */ |
2745 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); | |
2746 | void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2747 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2748 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2749 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
77913b39 | 2750 | |
1da177e4 | 2751 | /* i915_irq.c */ |
10cd45b6 | 2752 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2753 | __printf(3, 4) |
2754 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2755 | const char *fmt, ...); | |
1da177e4 | 2756 | |
b963291c | 2757 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2758 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2759 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2760 | |
2761 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2762 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2763 | bool restore_forcewake); | |
907b28c5 | 2764 | extern void intel_uncore_init(struct drm_device *dev); |
fc97618b | 2765 | extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); |
bc3b9346 | 2766 | extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); |
aec347ab | 2767 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2768 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
48c1026a | 2769 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2770 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2771 | enum forcewake_domains domains); |
59bad947 | 2772 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2773 | enum forcewake_domains domains); |
a6111f7b CW |
2774 | /* Like above but the caller must manage the uncore.lock itself. |
2775 | * Must be used with I915_READ_FW and friends. | |
2776 | */ | |
2777 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2778 | enum forcewake_domains domains); | |
2779 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2780 | enum forcewake_domains domains); | |
59bad947 | 2781 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
cf9d2890 YZ |
2782 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2783 | { | |
2784 | return to_i915(dev)->vgpu.active; | |
2785 | } | |
b1f14ad0 | 2786 | |
7c463586 | 2787 | void |
50227e1c | 2788 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2789 | u32 status_mask); |
7c463586 KP |
2790 | |
2791 | void | |
50227e1c | 2792 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2793 | u32 status_mask); |
7c463586 | 2794 | |
f8b79e58 ID |
2795 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2796 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2797 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2798 | uint32_t mask, | |
2799 | uint32_t bits); | |
fbdedaea VS |
2800 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2801 | uint32_t interrupt_mask, | |
2802 | uint32_t enabled_irq_mask); | |
2803 | static inline void | |
2804 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2805 | { | |
2806 | ilk_update_display_irq(dev_priv, bits, bits); | |
2807 | } | |
2808 | static inline void | |
2809 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2810 | { | |
2811 | ilk_update_display_irq(dev_priv, bits, 0); | |
2812 | } | |
013d3752 VS |
2813 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
2814 | enum pipe pipe, | |
2815 | uint32_t interrupt_mask, | |
2816 | uint32_t enabled_irq_mask); | |
2817 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
2818 | enum pipe pipe, uint32_t bits) | |
2819 | { | |
2820 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
2821 | } | |
2822 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
2823 | enum pipe pipe, uint32_t bits) | |
2824 | { | |
2825 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
2826 | } | |
47339cd9 DV |
2827 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2828 | uint32_t interrupt_mask, | |
2829 | uint32_t enabled_irq_mask); | |
14443261 VS |
2830 | static inline void |
2831 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2832 | { | |
2833 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
2834 | } | |
2835 | static inline void | |
2836 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2837 | { | |
2838 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
2839 | } | |
2840 | ||
f8b79e58 | 2841 | |
673a394b | 2842 | /* i915_gem.c */ |
673a394b EA |
2843 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2844 | struct drm_file *file_priv); | |
2845 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2846 | struct drm_file *file_priv); | |
2847 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2848 | struct drm_file *file_priv); | |
2849 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2850 | struct drm_file *file_priv); | |
de151cf6 JB |
2851 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2852 | struct drm_file *file_priv); | |
673a394b EA |
2853 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2854 | struct drm_file *file_priv); | |
2855 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2856 | struct drm_file *file_priv); | |
ba8b7ccb | 2857 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 2858 | struct drm_i915_gem_request *req); |
adeca76d | 2859 | void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params); |
5f19e2bf | 2860 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 2861 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 2862 | struct list_head *vmas); |
673a394b EA |
2863 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2864 | struct drm_file *file_priv); | |
76446cac JB |
2865 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2866 | struct drm_file *file_priv); | |
673a394b EA |
2867 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2868 | struct drm_file *file_priv); | |
199adf40 BW |
2869 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2870 | struct drm_file *file); | |
2871 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2872 | struct drm_file *file); | |
673a394b EA |
2873 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2874 | struct drm_file *file_priv); | |
3ef94daa CW |
2875 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2876 | struct drm_file *file_priv); | |
673a394b EA |
2877 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2878 | struct drm_file *file_priv); | |
2879 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2880 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2881 | int i915_gem_init_userptr(struct drm_device *dev); |
2882 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2883 | struct drm_file *file); | |
5a125c3c EA |
2884 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2885 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2886 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2887 | struct drm_file *file_priv); | |
d64aa096 ID |
2888 | void i915_gem_load_init(struct drm_device *dev); |
2889 | void i915_gem_load_cleanup(struct drm_device *dev); | |
42dcedd4 CW |
2890 | void *i915_gem_object_alloc(struct drm_device *dev); |
2891 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2892 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2893 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2894 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2895 | size_t size); | |
ea70299d DG |
2896 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
2897 | struct drm_device *dev, const void *data, size_t size); | |
673a394b | 2898 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2899 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2900 | |
0875546c DV |
2901 | /* Flags used by pin/bind&friends. */ |
2902 | #define PIN_MAPPABLE (1<<0) | |
2903 | #define PIN_NONBLOCK (1<<1) | |
2904 | #define PIN_GLOBAL (1<<2) | |
2905 | #define PIN_OFFSET_BIAS (1<<3) | |
2906 | #define PIN_USER (1<<4) | |
2907 | #define PIN_UPDATE (1<<5) | |
101b506a MT |
2908 | #define PIN_ZONE_4G (1<<6) |
2909 | #define PIN_HIGH (1<<7) | |
506a8e87 | 2910 | #define PIN_OFFSET_FIXED (1<<8) |
d23db88c | 2911 | #define PIN_OFFSET_MASK (~4095) |
ec7adb6e JL |
2912 | int __must_check |
2913 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
2914 | struct i915_address_space *vm, | |
2915 | uint32_t alignment, | |
2916 | uint64_t flags); | |
2917 | int __must_check | |
2918 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
2919 | const struct i915_ggtt_view *view, | |
2920 | uint32_t alignment, | |
2921 | uint64_t flags); | |
fe14d5f4 TU |
2922 | |
2923 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2924 | u32 flags); | |
d0710abb | 2925 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
07fe0b12 | 2926 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
e9f24d5f TU |
2927 | /* |
2928 | * BEWARE: Do not use the function below unless you can _absolutely_ | |
2929 | * _guarantee_ VMA in question is _not in use_ anywhere. | |
2930 | */ | |
2931 | int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); | |
dd624afd | 2932 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2933 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2934 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2935 | |
4c914c0c BV |
2936 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2937 | int *needs_clflush); | |
2938 | ||
37e680a1 | 2939 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
2940 | |
2941 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 2942 | { |
ee286370 CW |
2943 | return sg->length >> PAGE_SHIFT; |
2944 | } | |
67d5a50c | 2945 | |
033908ae DG |
2946 | struct page * |
2947 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); | |
2948 | ||
ee286370 CW |
2949 | static inline struct page * |
2950 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 2951 | { |
ee286370 CW |
2952 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2953 | return NULL; | |
67d5a50c | 2954 | |
ee286370 CW |
2955 | if (n < obj->get_page.last) { |
2956 | obj->get_page.sg = obj->pages->sgl; | |
2957 | obj->get_page.last = 0; | |
2958 | } | |
67d5a50c | 2959 | |
ee286370 CW |
2960 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
2961 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
2962 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
2963 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
2964 | } | |
67d5a50c | 2965 | |
ee286370 | 2966 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 2967 | } |
ee286370 | 2968 | |
a5570178 CW |
2969 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2970 | { | |
2971 | BUG_ON(obj->pages == NULL); | |
2972 | obj->pages_pin_count++; | |
2973 | } | |
2974 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2975 | { | |
2976 | BUG_ON(obj->pages_pin_count == 0); | |
2977 | obj->pages_pin_count--; | |
2978 | } | |
2979 | ||
54cf91dc | 2980 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2981 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
91af127f JH |
2982 | struct intel_engine_cs *to, |
2983 | struct drm_i915_gem_request **to_req); | |
e2d05a8b | 2984 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2985 | struct drm_i915_gem_request *req); |
ff72145b DA |
2986 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2987 | struct drm_device *dev, | |
2988 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
2989 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2990 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2991 | /** |
2992 | * Returns true if seq1 is later than seq2. | |
2993 | */ | |
2994 | static inline bool | |
2995 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2996 | { | |
2997 | return (int32_t)(seq1 - seq2) >= 0; | |
2998 | } | |
2999 | ||
821485dc CW |
3000 | static inline bool i915_gem_request_started(struct drm_i915_gem_request *req, |
3001 | bool lazy_coherency) | |
3002 | { | |
3003 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); | |
3004 | return i915_seqno_passed(seqno, req->previous_seqno); | |
3005 | } | |
3006 | ||
1b5a433a JH |
3007 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
3008 | bool lazy_coherency) | |
3009 | { | |
821485dc | 3010 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); |
1b5a433a JH |
3011 | return i915_seqno_passed(seqno, req->seqno); |
3012 | } | |
3013 | ||
fca26bb4 MK |
3014 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
3015 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
1690e1eb | 3016 | |
8d9fc7fd | 3017 | struct drm_i915_gem_request * |
a4872ba6 | 3018 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 3019 | |
b29c19b6 | 3020 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 3021 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 3022 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 3023 | bool interruptible); |
84c33a64 | 3024 | |
1f83fee0 DV |
3025 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
3026 | { | |
3027 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 3028 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
3029 | } |
3030 | ||
3031 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
3032 | { | |
2ac0f450 MK |
3033 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
3034 | } | |
3035 | ||
3036 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3037 | { | |
3038 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 3039 | } |
a71d8d94 | 3040 | |
88b4aa87 MK |
3041 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
3042 | { | |
3043 | return dev_priv->gpu_error.stop_rings == 0 || | |
3044 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
3045 | } | |
3046 | ||
3047 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
3048 | { | |
3049 | return dev_priv->gpu_error.stop_rings == 0 || | |
3050 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
3051 | } | |
3052 | ||
069efc1d | 3053 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 3054 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 3055 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 3056 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 3057 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
6909a666 | 3058 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice); |
f691e2f4 | 3059 | void i915_gem_init_swizzling(struct drm_device *dev); |
9a15a873 | 3060 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 3061 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 3062 | int __must_check i915_gem_suspend(struct drm_device *dev); |
75289874 | 3063 | void __i915_add_request(struct drm_i915_gem_request *req, |
5b4a60c2 JH |
3064 | struct drm_i915_gem_object *batch_obj, |
3065 | bool flush_caches); | |
75289874 | 3066 | #define i915_add_request(req) \ |
fcfa423c | 3067 | __i915_add_request(req, NULL, true) |
75289874 | 3068 | #define i915_add_request_no_flush(req) \ |
fcfa423c | 3069 | __i915_add_request(req, NULL, false) |
9c654818 | 3070 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
3071 | unsigned reset_counter, |
3072 | bool interruptible, | |
3073 | s64 *timeout, | |
2e1b8730 | 3074 | struct intel_rps_client *rps); |
a4b3a571 | 3075 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 3076 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 3077 | int __must_check |
2e2f351d CW |
3078 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3079 | bool readonly); | |
3080 | int __must_check | |
2021746e CW |
3081 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3082 | bool write); | |
3083 | int __must_check | |
dabdfe02 CW |
3084 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3085 | int __must_check | |
2da3b9b9 CW |
3086 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3087 | u32 alignment, | |
e6617330 TU |
3088 | const struct i915_ggtt_view *view); |
3089 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
3090 | const struct i915_ggtt_view *view); | |
00731155 | 3091 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3092 | int align); |
b29c19b6 | 3093 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3094 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3095 | |
0fa87796 ID |
3096 | uint32_t |
3097 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 3098 | uint32_t |
d865110c ID |
3099 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
3100 | int tiling_mode, bool fenced); | |
467cffba | 3101 | |
e4ffd173 CW |
3102 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3103 | enum i915_cache_level cache_level); | |
3104 | ||
1286ff73 DV |
3105 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3106 | struct dma_buf *dma_buf); | |
3107 | ||
3108 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3109 | struct drm_gem_object *gem_obj, int flags); | |
3110 | ||
088e0df4 MT |
3111 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
3112 | const struct i915_ggtt_view *view); | |
3113 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
3114 | struct i915_address_space *vm); | |
3115 | static inline u64 | |
ec7adb6e | 3116 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
fe14d5f4 | 3117 | { |
9abc4648 | 3118 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 3119 | } |
ec7adb6e | 3120 | |
a70a3148 | 3121 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
ec7adb6e | 3122 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 3123 | const struct i915_ggtt_view *view); |
a70a3148 | 3124 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 3125 | struct i915_address_space *vm); |
fe14d5f4 | 3126 | |
a70a3148 BW |
3127 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
3128 | struct i915_address_space *vm); | |
fe14d5f4 | 3129 | struct i915_vma * |
ec7adb6e JL |
3130 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3131 | struct i915_address_space *vm); | |
3132 | struct i915_vma * | |
3133 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
3134 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3135 | |
accfef2e BW |
3136 | struct i915_vma * |
3137 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
3138 | struct i915_address_space *vm); |
3139 | struct i915_vma * | |
3140 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
3141 | const struct i915_ggtt_view *view); | |
5c2abbea | 3142 | |
ec7adb6e JL |
3143 | static inline struct i915_vma * |
3144 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
3145 | { | |
3146 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 3147 | } |
ec7adb6e | 3148 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 3149 | |
a70a3148 | 3150 | /* Some GGTT VM helpers */ |
5dc383b0 | 3151 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 BW |
3152 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
3153 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
3154 | { | |
3155 | struct i915_address_space *ggtt = | |
3156 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
3157 | return vm == ggtt; | |
3158 | } | |
3159 | ||
841cd773 DV |
3160 | static inline struct i915_hw_ppgtt * |
3161 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3162 | { | |
3163 | WARN_ON(i915_is_ggtt(vm)); | |
3164 | ||
3165 | return container_of(vm, struct i915_hw_ppgtt, base); | |
3166 | } | |
3167 | ||
3168 | ||
a70a3148 BW |
3169 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3170 | { | |
9abc4648 | 3171 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
3172 | } |
3173 | ||
3174 | static inline unsigned long | |
3175 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
3176 | { | |
5dc383b0 | 3177 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 3178 | } |
c37e2204 BW |
3179 | |
3180 | static inline int __must_check | |
3181 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
3182 | uint32_t alignment, | |
1ec9e26d | 3183 | unsigned flags) |
c37e2204 | 3184 | { |
5dc383b0 DV |
3185 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
3186 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 3187 | } |
a70a3148 | 3188 | |
b287110e DV |
3189 | static inline int |
3190 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
3191 | { | |
3192 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
3193 | } | |
3194 | ||
e6617330 TU |
3195 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3196 | const struct i915_ggtt_view *view); | |
3197 | static inline void | |
3198 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3199 | { | |
3200 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3201 | } | |
b287110e | 3202 | |
41a36b73 DV |
3203 | /* i915_gem_fence.c */ |
3204 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
3205 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
3206 | ||
3207 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
3208 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
3209 | ||
3210 | void i915_gem_restore_fences(struct drm_device *dev); | |
3211 | ||
7f96ecaf DV |
3212 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3213 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3214 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3215 | ||
254f965c | 3216 | /* i915_gem_context.c */ |
8245be31 | 3217 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 3218 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3219 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3220 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
b3dd6b96 | 3221 | int i915_gem_context_enable(struct drm_i915_gem_request *req); |
254f965c | 3222 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3223 | int i915_switch_context(struct drm_i915_gem_request *req); |
273497e5 | 3224 | struct intel_context * |
41bde553 | 3225 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 3226 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3227 | struct drm_i915_gem_object * |
3228 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 3229 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 3230 | { |
691e6415 | 3231 | kref_get(&ctx->ref); |
dce3271b MK |
3232 | } |
3233 | ||
273497e5 | 3234 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 3235 | { |
691e6415 | 3236 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3237 | } |
3238 | ||
273497e5 | 3239 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 3240 | { |
821d66dd | 3241 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3242 | } |
3243 | ||
84624813 BW |
3244 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3245 | struct drm_file *file); | |
3246 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3247 | struct drm_file *file); | |
c9dc0f35 CW |
3248 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3249 | struct drm_file *file_priv); | |
3250 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3251 | struct drm_file *file_priv); | |
1286ff73 | 3252 | |
679845ed BW |
3253 | /* i915_gem_evict.c */ |
3254 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3255 | struct i915_address_space *vm, | |
3256 | int min_size, | |
3257 | unsigned alignment, | |
3258 | unsigned cache_level, | |
d23db88c CW |
3259 | unsigned long start, |
3260 | unsigned long end, | |
1ec9e26d | 3261 | unsigned flags); |
506a8e87 | 3262 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
679845ed | 3263 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3264 | |
0260c420 | 3265 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 3266 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
3267 | { |
3268 | if (INTEL_INFO(dev)->gen < 6) | |
3269 | intel_gtt_chipset_flush(); | |
3270 | } | |
246cbfb5 | 3271 | |
9797fbfb | 3272 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3273 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3274 | struct drm_mm_node *node, u64 size, | |
3275 | unsigned alignment); | |
a9da512b PZ |
3276 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3277 | struct drm_mm_node *node, u64 size, | |
3278 | unsigned alignment, u64 start, | |
3279 | u64 end); | |
d713fd49 PZ |
3280 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3281 | struct drm_mm_node *node); | |
9797fbfb CW |
3282 | int i915_gem_init_stolen(struct drm_device *dev); |
3283 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3284 | struct drm_i915_gem_object * |
3285 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3286 | struct drm_i915_gem_object * |
3287 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3288 | u32 stolen_offset, | |
3289 | u32 gtt_offset, | |
3290 | u32 size); | |
9797fbfb | 3291 | |
be6a0376 DV |
3292 | /* i915_gem_shrinker.c */ |
3293 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3294 | unsigned long target, |
be6a0376 DV |
3295 | unsigned flags); |
3296 | #define I915_SHRINK_PURGEABLE 0x1 | |
3297 | #define I915_SHRINK_UNBOUND 0x2 | |
3298 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3299 | #define I915_SHRINK_ACTIVE 0x8 |
be6a0376 DV |
3300 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3301 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3302 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3303 | |
3304 | ||
673a394b | 3305 | /* i915_gem_tiling.c */ |
2c1792a1 | 3306 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3307 | { |
50227e1c | 3308 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
3309 | |
3310 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3311 | obj->tiling_mode != I915_TILING_NONE; | |
3312 | } | |
3313 | ||
673a394b | 3314 | /* i915_gem_debug.c */ |
23bc5982 CW |
3315 | #if WATCH_LISTS |
3316 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 3317 | #else |
23bc5982 | 3318 | #define i915_verify_lists(dev) 0 |
673a394b | 3319 | #endif |
1da177e4 | 3320 | |
2017263e | 3321 | /* i915_debugfs.c */ |
27c202ad BG |
3322 | int i915_debugfs_init(struct drm_minor *minor); |
3323 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 3324 | #ifdef CONFIG_DEBUG_FS |
249e87de | 3325 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3326 | void intel_display_crc_init(struct drm_device *dev); |
3327 | #else | |
101057fa DV |
3328 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3329 | { return 0; } | |
f8c168fa | 3330 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3331 | #endif |
84734a04 MK |
3332 | |
3333 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3334 | __printf(2, 3) |
3335 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3336 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3337 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3338 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3339 | struct drm_i915_private *i915, |
4dc955f7 MK |
3340 | size_t count, loff_t pos); |
3341 | static inline void i915_error_state_buf_release( | |
3342 | struct drm_i915_error_state_buf *eb) | |
3343 | { | |
3344 | kfree(eb->buf); | |
3345 | } | |
58174462 MK |
3346 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
3347 | const char *error_msg); | |
84734a04 MK |
3348 | void i915_error_state_get(struct drm_device *dev, |
3349 | struct i915_error_state_file_priv *error_priv); | |
3350 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3351 | void i915_destroy_error_state(struct drm_device *dev); | |
3352 | ||
3353 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 3354 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3355 | |
351e3db2 | 3356 | /* i915_cmd_parser.c */ |
d728c8ef | 3357 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
3358 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
3359 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
3360 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
3361 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 | 3362 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3363 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3364 | u32 batch_start_offset, |
b9ffd80e | 3365 | u32 batch_len, |
351e3db2 BV |
3366 | bool is_master); |
3367 | ||
317c35d1 JB |
3368 | /* i915_suspend.c */ |
3369 | extern int i915_save_state(struct drm_device *dev); | |
3370 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3371 | |
0136db58 BW |
3372 | /* i915_sysfs.c */ |
3373 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3374 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3375 | ||
f899fc64 CW |
3376 | /* intel_i2c.c */ |
3377 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3378 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3379 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3380 | unsigned int pin); | |
3bd7d909 | 3381 | |
0184df46 JN |
3382 | extern struct i2c_adapter * |
3383 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3384 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3385 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3386 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3387 | { |
3388 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3389 | } | |
f899fc64 CW |
3390 | extern void intel_i2c_reset(struct drm_device *dev); |
3391 | ||
8b8e1a89 | 3392 | /* intel_bios.c */ |
98f3a1dc | 3393 | int intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3394 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
8b8e1a89 | 3395 | |
3b617967 | 3396 | /* intel_opregion.c */ |
44834a67 | 3397 | #ifdef CONFIG_ACPI |
27d50c82 | 3398 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
3399 | extern void intel_opregion_init(struct drm_device *dev); |
3400 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 3401 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
3402 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3403 | bool enable); | |
ecbc5cf3 JN |
3404 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3405 | pci_power_t state); | |
65e082c9 | 3406 | #else |
27d50c82 | 3407 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
3408 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3409 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 3410 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
3411 | static inline int |
3412 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3413 | { | |
3414 | return 0; | |
3415 | } | |
ecbc5cf3 JN |
3416 | static inline int |
3417 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3418 | { | |
3419 | return 0; | |
3420 | } | |
65e082c9 | 3421 | #endif |
8ee1c3db | 3422 | |
723bfd70 JB |
3423 | /* intel_acpi.c */ |
3424 | #ifdef CONFIG_ACPI | |
3425 | extern void intel_register_dsm_handler(void); | |
3426 | extern void intel_unregister_dsm_handler(void); | |
3427 | #else | |
3428 | static inline void intel_register_dsm_handler(void) { return; } | |
3429 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3430 | #endif /* CONFIG_ACPI */ | |
3431 | ||
79e53945 | 3432 | /* modesetting */ |
f817586c | 3433 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3434 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3435 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3436 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 3437 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 3438 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3439 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3440 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3441 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
7648fa99 | 3442 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 3443 | extern void intel_init_pch_refclk(struct drm_device *dev); |
ffe02b40 | 3444 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
3445 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3446 | bool enable); | |
0206e353 | 3447 | extern void intel_detect_pch(struct drm_device *dev); |
0136db58 | 3448 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 3449 | |
2911a35b | 3450 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
3451 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3452 | struct drm_file *file); | |
b6359918 MK |
3453 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3454 | struct drm_file *file); | |
575155a9 | 3455 | |
6ef3d427 CW |
3456 | /* overlay */ |
3457 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
3458 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3459 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
3460 | |
3461 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 3462 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3463 | struct drm_device *dev, |
3464 | struct intel_display_error_state *error); | |
6ef3d427 | 3465 | |
151a49d0 TR |
3466 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3467 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3468 | |
3469 | /* intel_sideband.c */ | |
707b6e3d D |
3470 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3471 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3472 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
e9f882a3 JN |
3473 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
3474 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3475 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
3476 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3477 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3478 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3479 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3480 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
3481 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3482 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3483 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3484 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3485 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3486 | enum intel_sbi_destination destination); | |
3487 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3488 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3489 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3490 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3491 | |
616bc820 VS |
3492 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3493 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3494 | |
0b274481 BW |
3495 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3496 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3497 | ||
3498 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3499 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3500 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3501 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3502 | ||
3503 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3504 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3505 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3506 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3507 | ||
698b3135 CW |
3508 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3509 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3510 | * an arbitrary delay between them. This can cause the hardware to | |
3511 | * act upon the intermediate value, possibly leading to corruption and | |
3512 | * machine death. You have been warned. | |
3513 | */ | |
0b274481 BW |
3514 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3515 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3516 | |
50877445 | 3517 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3518 | u32 upper, lower, old_upper, loop = 0; \ |
3519 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3520 | do { \ |
acd29f7b | 3521 | old_upper = upper; \ |
ee0a227b | 3522 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3523 | upper = I915_READ(upper_reg); \ |
3524 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3525 | (u64)upper << 32 | lower; }) |
50877445 | 3526 | |
cae5852d ZN |
3527 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3528 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3529 | ||
75aa3f63 VS |
3530 | #define __raw_read(x, s) \ |
3531 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3532 | i915_reg_t reg) \ |
75aa3f63 | 3533 | { \ |
f0f59a00 | 3534 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3535 | } |
3536 | ||
3537 | #define __raw_write(x, s) \ | |
3538 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 3539 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3540 | { \ |
f0f59a00 | 3541 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3542 | } |
3543 | __raw_read(8, b) | |
3544 | __raw_read(16, w) | |
3545 | __raw_read(32, l) | |
3546 | __raw_read(64, q) | |
3547 | ||
3548 | __raw_write(8, b) | |
3549 | __raw_write(16, w) | |
3550 | __raw_write(32, l) | |
3551 | __raw_write(64, q) | |
3552 | ||
3553 | #undef __raw_read | |
3554 | #undef __raw_write | |
3555 | ||
a6111f7b CW |
3556 | /* These are untraced mmio-accessors that are only valid to be used inside |
3557 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3558 | * controlled. | |
3559 | * Think twice, and think again, before using these. | |
3560 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3561 | * intel_uncore_forcewake_irqunlock(). | |
3562 | */ | |
75aa3f63 VS |
3563 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3564 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
a6111f7b CW |
3565 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3566 | ||
55bc60db VS |
3567 | /* "Broadcast RGB" property */ |
3568 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3569 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3570 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3571 | |
f0f59a00 | 3572 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
766aa1c4 | 3573 | { |
666a4537 | 3574 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
766aa1c4 | 3575 | return VLV_VGACNTRL; |
92e23b99 SJ |
3576 | else if (INTEL_INFO(dev)->gen >= 5) |
3577 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3578 | else |
3579 | return VGACNTRL; | |
3580 | } | |
3581 | ||
2bb4629a VS |
3582 | static inline void __user *to_user_ptr(u64 address) |
3583 | { | |
3584 | return (void __user *)(uintptr_t)address; | |
3585 | } | |
3586 | ||
df97729f ID |
3587 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3588 | { | |
3589 | unsigned long j = msecs_to_jiffies(m); | |
3590 | ||
3591 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3592 | } | |
3593 | ||
7bd0e226 DV |
3594 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3595 | { | |
3596 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3597 | } | |
3598 | ||
df97729f ID |
3599 | static inline unsigned long |
3600 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3601 | { | |
3602 | unsigned long j = timespec_to_jiffies(value); | |
3603 | ||
3604 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3605 | } | |
3606 | ||
dce56b3c PZ |
3607 | /* |
3608 | * If you need to wait X milliseconds between events A and B, but event B | |
3609 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3610 | * when event A happened, then just before event B you call this function and | |
3611 | * pass the timestamp as the first argument, and X as the second argument. | |
3612 | */ | |
3613 | static inline void | |
3614 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3615 | { | |
ec5e0cfb | 3616 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3617 | |
3618 | /* | |
3619 | * Don't re-read the value of "jiffies" every time since it may change | |
3620 | * behind our back and break the math. | |
3621 | */ | |
3622 | tmp_jiffies = jiffies; | |
3623 | target_jiffies = timestamp_jiffies + | |
3624 | msecs_to_jiffies_timeout(to_wait_ms); | |
3625 | ||
3626 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3627 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3628 | while (remaining_jiffies) | |
3629 | remaining_jiffies = | |
3630 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3631 | } |
3632 | } | |
3633 | ||
581c26e8 JH |
3634 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3635 | struct drm_i915_gem_request *req) | |
3636 | { | |
3637 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) | |
3638 | i915_gem_request_assign(&ring->trace_irq_req, req); | |
3639 | } | |
3640 | ||
1da177e4 | 3641 | #endif |