Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
0839ccb8 | 38 | #include <linux/io-mapping.h> |
f899fc64 | 39 | #include <linux/i2c.h> |
c167a6fc | 40 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 41 | #include <drm/intel-gtt.h> |
aaa6fd2a | 42 | #include <linux/backlight.h> |
2911a35b | 43 | #include <linux/intel-iommu.h> |
742cbee8 | 44 | #include <linux/kref.h> |
9ee32fea | 45 | #include <linux/pm_qos.h> |
585fb111 | 46 | |
1da177e4 LT |
47 | /* General customization: |
48 | */ | |
49 | ||
50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
51 | ||
52 | #define DRIVER_NAME "i915" | |
53 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 54 | #define DRIVER_DATE "20080730" |
1da177e4 | 55 | |
317c35d1 JB |
56 | enum pipe { |
57 | PIPE_A = 0, | |
58 | PIPE_B, | |
9db4a9c7 JB |
59 | PIPE_C, |
60 | I915_MAX_PIPES | |
317c35d1 | 61 | }; |
9db4a9c7 | 62 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 63 | |
a5c961d1 PZ |
64 | enum transcoder { |
65 | TRANSCODER_A = 0, | |
66 | TRANSCODER_B, | |
67 | TRANSCODER_C, | |
68 | TRANSCODER_EDP = 0xF, | |
69 | }; | |
70 | #define transcoder_name(t) ((t) + 'A') | |
71 | ||
80824003 JB |
72 | enum plane { |
73 | PLANE_A = 0, | |
74 | PLANE_B, | |
9db4a9c7 | 75 | PLANE_C, |
80824003 | 76 | }; |
9db4a9c7 | 77 | #define plane_name(p) ((p) + 'A') |
52440211 | 78 | |
06da8da2 VS |
79 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
80 | ||
2b139522 ED |
81 | enum port { |
82 | PORT_A = 0, | |
83 | PORT_B, | |
84 | PORT_C, | |
85 | PORT_D, | |
86 | PORT_E, | |
87 | I915_MAX_PORTS | |
88 | }; | |
89 | #define port_name(p) ((p) + 'A') | |
90 | ||
1d843f9d EE |
91 | enum hpd_pin { |
92 | HPD_NONE = 0, | |
93 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
94 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
95 | HPD_CRT, | |
96 | HPD_SDVO_B, | |
97 | HPD_SDVO_C, | |
98 | HPD_PORT_B, | |
99 | HPD_PORT_C, | |
100 | HPD_PORT_D, | |
101 | HPD_NUM_PINS | |
102 | }; | |
103 | ||
2a2d5482 CW |
104 | #define I915_GEM_GPU_DOMAINS \ |
105 | (I915_GEM_DOMAIN_RENDER | \ | |
106 | I915_GEM_DOMAIN_SAMPLER | \ | |
107 | I915_GEM_DOMAIN_COMMAND | \ | |
108 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
109 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 110 | |
7eb552ae | 111 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
9db4a9c7 | 112 | |
6c2b7c12 DV |
113 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
114 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
115 | if ((intel_encoder)->base.crtc == (__crtc)) | |
116 | ||
ee7b9f93 JB |
117 | struct intel_pch_pll { |
118 | int refcount; /* count of number of CRTCs sharing this PLL */ | |
119 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
120 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
121 | int pll_reg; | |
122 | int fp0_reg; | |
123 | int fp1_reg; | |
124 | }; | |
125 | #define I915_NUM_PLLS 2 | |
126 | ||
e69d0bc1 DV |
127 | /* Used by dp and fdi links */ |
128 | struct intel_link_m_n { | |
129 | uint32_t tu; | |
130 | uint32_t gmch_m; | |
131 | uint32_t gmch_n; | |
132 | uint32_t link_m; | |
133 | uint32_t link_n; | |
134 | }; | |
135 | ||
136 | void intel_link_compute_m_n(int bpp, int nlanes, | |
137 | int pixel_clock, int link_clock, | |
138 | struct intel_link_m_n *m_n); | |
139 | ||
6441ab5f PZ |
140 | struct intel_ddi_plls { |
141 | int spll_refcount; | |
142 | int wrpll1_refcount; | |
143 | int wrpll2_refcount; | |
144 | }; | |
145 | ||
1da177e4 LT |
146 | /* Interface history: |
147 | * | |
148 | * 1.1: Original. | |
0d6aa60b DA |
149 | * 1.2: Add Power Management |
150 | * 1.3: Add vblank support | |
de227f5f | 151 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 152 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
153 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
154 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
155 | */ |
156 | #define DRIVER_MAJOR 1 | |
2228ed67 | 157 | #define DRIVER_MINOR 6 |
1da177e4 LT |
158 | #define DRIVER_PATCHLEVEL 0 |
159 | ||
673a394b | 160 | #define WATCH_COHERENCY 0 |
23bc5982 | 161 | #define WATCH_LISTS 0 |
42d6ab48 | 162 | #define WATCH_GTT 0 |
673a394b | 163 | |
71acb5eb DA |
164 | #define I915_GEM_PHYS_CURSOR_0 1 |
165 | #define I915_GEM_PHYS_CURSOR_1 2 | |
166 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
167 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
168 | ||
169 | struct drm_i915_gem_phys_object { | |
170 | int id; | |
171 | struct page **page_list; | |
172 | drm_dma_handle_t *handle; | |
05394f39 | 173 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
174 | }; |
175 | ||
0a3e67a4 JB |
176 | struct opregion_header; |
177 | struct opregion_acpi; | |
178 | struct opregion_swsci; | |
179 | struct opregion_asle; | |
8d715f00 | 180 | struct drm_i915_private; |
0a3e67a4 | 181 | |
8ee1c3db | 182 | struct intel_opregion { |
5bc4418b BW |
183 | struct opregion_header __iomem *header; |
184 | struct opregion_acpi __iomem *acpi; | |
185 | struct opregion_swsci __iomem *swsci; | |
186 | struct opregion_asle __iomem *asle; | |
187 | void __iomem *vbt; | |
01fe9dbd | 188 | u32 __iomem *lid_state; |
8ee1c3db | 189 | }; |
44834a67 | 190 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 191 | |
6ef3d427 CW |
192 | struct intel_overlay; |
193 | struct intel_overlay_error_state; | |
194 | ||
7c1c2871 DA |
195 | struct drm_i915_master_private { |
196 | drm_local_map_t *sarea; | |
197 | struct _drm_i915_sarea *sarea_priv; | |
198 | }; | |
de151cf6 | 199 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
200 | #define I915_MAX_NUM_FENCES 32 |
201 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
202 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
203 | |
204 | struct drm_i915_fence_reg { | |
007cc8ac | 205 | struct list_head lru_list; |
caea7476 | 206 | struct drm_i915_gem_object *obj; |
1690e1eb | 207 | int pin_count; |
de151cf6 | 208 | }; |
7c1c2871 | 209 | |
9b9d172d | 210 | struct sdvo_device_mapping { |
e957d772 | 211 | u8 initialized; |
9b9d172d | 212 | u8 dvo_port; |
213 | u8 slave_addr; | |
214 | u8 dvo_wiring; | |
e957d772 | 215 | u8 i2c_pin; |
b1083333 | 216 | u8 ddc_pin; |
9b9d172d | 217 | }; |
218 | ||
c4a1d9e4 CW |
219 | struct intel_display_error_state; |
220 | ||
63eeaf38 | 221 | struct drm_i915_error_state { |
742cbee8 | 222 | struct kref ref; |
63eeaf38 JB |
223 | u32 eir; |
224 | u32 pgtbl_er; | |
be998e2e | 225 | u32 ier; |
b9a3906b | 226 | u32 ccid; |
0f3b6849 CW |
227 | u32 derrmr; |
228 | u32 forcewake; | |
9574b3fe | 229 | bool waiting[I915_NUM_RINGS]; |
9db4a9c7 | 230 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
231 | u32 tail[I915_NUM_RINGS]; |
232 | u32 head[I915_NUM_RINGS]; | |
0f3b6849 | 233 | u32 ctl[I915_NUM_RINGS]; |
d27b1e0e DV |
234 | u32 ipeir[I915_NUM_RINGS]; |
235 | u32 ipehr[I915_NUM_RINGS]; | |
236 | u32 instdone[I915_NUM_RINGS]; | |
237 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 | 238 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
df2b23d9 | 239 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
12f55818 | 240 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
7e3b8737 DV |
241 | /* our own tracking of ring head and tail */ |
242 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
243 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 244 | u32 error; /* gen6+ */ |
71e172e8 | 245 | u32 err_int; /* gen7 */ |
c1cd90ed DV |
246 | u32 instpm[I915_NUM_RINGS]; |
247 | u32 instps[I915_NUM_RINGS]; | |
050ee91f | 248 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
d27b1e0e | 249 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 250 | u64 bbaddr; |
33f3f518 DV |
251 | u32 fault_reg[I915_NUM_RINGS]; |
252 | u32 done_reg; | |
c1cd90ed | 253 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 254 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 255 | struct timeval time; |
52d39a21 CW |
256 | struct drm_i915_error_ring { |
257 | struct drm_i915_error_object { | |
258 | int page_count; | |
259 | u32 gtt_offset; | |
260 | u32 *pages[0]; | |
8c123e54 | 261 | } *ringbuffer, *batchbuffer, *ctx; |
52d39a21 CW |
262 | struct drm_i915_error_request { |
263 | long jiffies; | |
264 | u32 seqno; | |
ee4f42b1 | 265 | u32 tail; |
52d39a21 CW |
266 | } *requests; |
267 | int num_requests; | |
268 | } ring[I915_NUM_RINGS]; | |
9df30794 | 269 | struct drm_i915_error_buffer { |
a779e5ab | 270 | u32 size; |
9df30794 | 271 | u32 name; |
0201f1ec | 272 | u32 rseqno, wseqno; |
9df30794 CW |
273 | u32 gtt_offset; |
274 | u32 read_domains; | |
275 | u32 write_domain; | |
4b9de737 | 276 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
277 | s32 pinned:2; |
278 | u32 tiling:2; | |
279 | u32 dirty:1; | |
280 | u32 purgeable:1; | |
5d1333fc | 281 | s32 ring:4; |
93dfb40c | 282 | u32 cache_level:2; |
c724e8a9 CW |
283 | } *active_bo, *pinned_bo; |
284 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 285 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 286 | struct intel_display_error_state *display; |
63eeaf38 JB |
287 | }; |
288 | ||
b8cecdf5 | 289 | struct intel_crtc_config; |
0e8ffe1b | 290 | struct intel_crtc; |
b8cecdf5 | 291 | |
e70236a8 | 292 | struct drm_i915_display_funcs { |
ee5382ae | 293 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
294 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
295 | void (*disable_fbc)(struct drm_device *dev); | |
296 | int (*get_display_clock_speed)(struct drm_device *dev); | |
297 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 298 | void (*update_wm)(struct drm_device *dev); |
b840d907 JB |
299 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
300 | uint32_t sprite_width, int pixel_size); | |
1f8eeabf ED |
301 | void (*update_linetime_wm)(struct drm_device *dev, int pipe, |
302 | struct drm_display_mode *mode); | |
47fab737 | 303 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
304 | /* Returns the active state of the crtc, and if the crtc is active, |
305 | * fills out the pipe-config with the hw state. */ | |
306 | bool (*get_pipe_config)(struct intel_crtc *, | |
307 | struct intel_crtc_config *); | |
f564048e | 308 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
f564048e EA |
309 | int x, int y, |
310 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
311 | void (*crtc_enable)(struct drm_crtc *crtc); |
312 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 313 | void (*off)(struct drm_crtc *crtc); |
e0dac65e WF |
314 | void (*write_eld)(struct drm_connector *connector, |
315 | struct drm_crtc *crtc); | |
674cf967 | 316 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 317 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
318 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
319 | struct drm_framebuffer *fb, | |
320 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
321 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
322 | int x, int y); | |
20afbda2 | 323 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
324 | /* clock updates for mode set */ |
325 | /* cursor updates */ | |
326 | /* render clock increase/decrease */ | |
327 | /* display clock increase/decrease */ | |
328 | /* pll clock increase/decrease */ | |
e70236a8 JB |
329 | }; |
330 | ||
990bbdad CW |
331 | struct drm_i915_gt_funcs { |
332 | void (*force_wake_get)(struct drm_i915_private *dev_priv); | |
333 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
334 | }; | |
335 | ||
79fc46df DL |
336 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
337 | func(is_mobile) sep \ | |
338 | func(is_i85x) sep \ | |
339 | func(is_i915g) sep \ | |
340 | func(is_i945gm) sep \ | |
341 | func(is_g33) sep \ | |
342 | func(need_gfx_hws) sep \ | |
343 | func(is_g4x) sep \ | |
344 | func(is_pineview) sep \ | |
345 | func(is_broadwater) sep \ | |
346 | func(is_crestline) sep \ | |
347 | func(is_ivybridge) sep \ | |
348 | func(is_valleyview) sep \ | |
349 | func(is_haswell) sep \ | |
350 | func(has_force_wake) sep \ | |
351 | func(has_fbc) sep \ | |
352 | func(has_pipe_cxsr) sep \ | |
353 | func(has_hotplug) sep \ | |
354 | func(cursor_needs_physical) sep \ | |
355 | func(has_overlay) sep \ | |
356 | func(overlay_needs_physical) sep \ | |
357 | func(supports_tv) sep \ | |
358 | func(has_bsd_ring) sep \ | |
359 | func(has_blt_ring) sep \ | |
360 | func(has_llc) | |
c96ea64e | 361 | |
cfdf1fa2 | 362 | struct intel_device_info { |
10fce67a | 363 | u32 display_mmio_offset; |
7eb552ae | 364 | u8 num_pipes:3; |
c96c3a8c | 365 | u8 gen; |
0206e353 AJ |
366 | u8 is_mobile:1; |
367 | u8 is_i85x:1; | |
368 | u8 is_i915g:1; | |
369 | u8 is_i945gm:1; | |
370 | u8 is_g33:1; | |
371 | u8 need_gfx_hws:1; | |
372 | u8 is_g4x:1; | |
373 | u8 is_pineview:1; | |
374 | u8 is_broadwater:1; | |
375 | u8 is_crestline:1; | |
376 | u8 is_ivybridge:1; | |
70a3eb7a | 377 | u8 is_valleyview:1; |
b7884eb4 | 378 | u8 has_force_wake:1; |
4cae9ae0 | 379 | u8 is_haswell:1; |
0206e353 AJ |
380 | u8 has_fbc:1; |
381 | u8 has_pipe_cxsr:1; | |
382 | u8 has_hotplug:1; | |
383 | u8 cursor_needs_physical:1; | |
384 | u8 has_overlay:1; | |
385 | u8 overlay_needs_physical:1; | |
386 | u8 supports_tv:1; | |
387 | u8 has_bsd_ring:1; | |
388 | u8 has_blt_ring:1; | |
3d29b842 | 389 | u8 has_llc:1; |
cfdf1fa2 KH |
390 | }; |
391 | ||
7faf1ab2 DV |
392 | enum i915_cache_level { |
393 | I915_CACHE_NONE = 0, | |
394 | I915_CACHE_LLC, | |
395 | I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ | |
396 | }; | |
397 | ||
2d04befb KG |
398 | typedef uint32_t gen6_gtt_pte_t; |
399 | ||
5d4545ae BW |
400 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
401 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
402 | * collateral associated with any va->pa translations GEN hardware also has a | |
403 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
404 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
405 | * the spec. | |
406 | */ | |
407 | struct i915_gtt { | |
408 | unsigned long start; /* Start offset of used GTT */ | |
409 | size_t total; /* Total size GTT can map */ | |
baa09f5f | 410 | size_t stolen_size; /* Total size of stolen memory */ |
5d4545ae BW |
411 | |
412 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
413 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
414 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
415 | ||
416 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
417 | void __iomem *gsm; | |
a81cc00c BW |
418 | |
419 | bool do_idle_maps; | |
9c61a32d BW |
420 | dma_addr_t scratch_page_dma; |
421 | struct page *scratch_page; | |
7faf1ab2 DV |
422 | |
423 | /* global gtt ops */ | |
baa09f5f | 424 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
41907ddc BW |
425 | size_t *stolen, phys_addr_t *mappable_base, |
426 | unsigned long *mappable_end); | |
baa09f5f | 427 | void (*gtt_remove)(struct drm_device *dev); |
7faf1ab2 DV |
428 | void (*gtt_clear_range)(struct drm_device *dev, |
429 | unsigned int first_entry, | |
430 | unsigned int num_entries); | |
431 | void (*gtt_insert_entries)(struct drm_device *dev, | |
432 | struct sg_table *st, | |
433 | unsigned int pg_start, | |
434 | enum i915_cache_level cache_level); | |
2d04befb KG |
435 | gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, |
436 | dma_addr_t addr, | |
437 | enum i915_cache_level level); | |
5d4545ae | 438 | }; |
a54c0c27 | 439 | #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT) |
5d4545ae | 440 | |
1d2a314c DV |
441 | #define I915_PPGTT_PD_ENTRIES 512 |
442 | #define I915_PPGTT_PT_ENTRIES 1024 | |
443 | struct i915_hw_ppgtt { | |
8f2c59f0 | 444 | struct drm_device *dev; |
1d2a314c DV |
445 | unsigned num_pd_entries; |
446 | struct page **pt_pages; | |
447 | uint32_t pd_offset; | |
448 | dma_addr_t *pt_dma_addr; | |
449 | dma_addr_t scratch_page_dma_addr; | |
def886c3 DV |
450 | |
451 | /* pte functions, mirroring the interface of the global gtt. */ | |
452 | void (*clear_range)(struct i915_hw_ppgtt *ppgtt, | |
453 | unsigned int first_entry, | |
454 | unsigned int num_entries); | |
455 | void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, | |
456 | struct sg_table *st, | |
457 | unsigned int pg_start, | |
458 | enum i915_cache_level cache_level); | |
2d04befb KG |
459 | gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, |
460 | dma_addr_t addr, | |
461 | enum i915_cache_level level); | |
b7c36d25 | 462 | int (*enable)(struct drm_device *dev); |
3440d265 | 463 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
1d2a314c DV |
464 | }; |
465 | ||
40521054 BW |
466 | |
467 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
468 | #define DEFAULT_CONTEXT_ID 0 | |
469 | struct i915_hw_context { | |
470 | int id; | |
e0556841 | 471 | bool is_initialized; |
40521054 BW |
472 | struct drm_i915_file_private *file_priv; |
473 | struct intel_ring_buffer *ring; | |
474 | struct drm_i915_gem_object *obj; | |
475 | }; | |
476 | ||
b5e50c3f | 477 | enum no_fbc_reason { |
bed4a673 | 478 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
479 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
480 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
481 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
482 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
483 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 484 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 485 | FBC_MODULE_PARAM, |
b5e50c3f JB |
486 | }; |
487 | ||
3bad0781 | 488 | enum intel_pch { |
f0350830 | 489 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
490 | PCH_IBX, /* Ibexpeak PCH */ |
491 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 492 | PCH_LPT, /* Lynxpoint PCH */ |
40c7ead9 | 493 | PCH_NOP, |
3bad0781 ZW |
494 | }; |
495 | ||
988d6ee8 PZ |
496 | enum intel_sbi_destination { |
497 | SBI_ICLK, | |
498 | SBI_MPHY, | |
499 | }; | |
500 | ||
b690e96c | 501 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 502 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 503 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 504 | |
8be48d92 | 505 | struct intel_fbdev; |
1630fe75 | 506 | struct intel_fbc_work; |
38651674 | 507 | |
c2b9152f DV |
508 | struct intel_gmbus { |
509 | struct i2c_adapter adapter; | |
f2ce9faf | 510 | u32 force_bit; |
c2b9152f | 511 | u32 reg0; |
36c785f0 | 512 | u32 gpio_reg; |
c167a6fc | 513 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
514 | struct drm_i915_private *dev_priv; |
515 | }; | |
516 | ||
f4c956ad | 517 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
518 | u8 saveLBB; |
519 | u32 saveDSPACNTR; | |
520 | u32 saveDSPBCNTR; | |
e948e994 | 521 | u32 saveDSPARB; |
ba8bbcf6 JB |
522 | u32 savePIPEACONF; |
523 | u32 savePIPEBCONF; | |
524 | u32 savePIPEASRC; | |
525 | u32 savePIPEBSRC; | |
526 | u32 saveFPA0; | |
527 | u32 saveFPA1; | |
528 | u32 saveDPLL_A; | |
529 | u32 saveDPLL_A_MD; | |
530 | u32 saveHTOTAL_A; | |
531 | u32 saveHBLANK_A; | |
532 | u32 saveHSYNC_A; | |
533 | u32 saveVTOTAL_A; | |
534 | u32 saveVBLANK_A; | |
535 | u32 saveVSYNC_A; | |
536 | u32 saveBCLRPAT_A; | |
5586c8bc | 537 | u32 saveTRANSACONF; |
42048781 ZW |
538 | u32 saveTRANS_HTOTAL_A; |
539 | u32 saveTRANS_HBLANK_A; | |
540 | u32 saveTRANS_HSYNC_A; | |
541 | u32 saveTRANS_VTOTAL_A; | |
542 | u32 saveTRANS_VBLANK_A; | |
543 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 544 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
545 | u32 saveDSPASTRIDE; |
546 | u32 saveDSPASIZE; | |
547 | u32 saveDSPAPOS; | |
585fb111 | 548 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
549 | u32 saveDSPASURF; |
550 | u32 saveDSPATILEOFF; | |
551 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 552 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
553 | u32 saveBLC_PWM_CTL; |
554 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
555 | u32 saveBLC_CPU_PWM_CTL; |
556 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
557 | u32 saveFPB0; |
558 | u32 saveFPB1; | |
559 | u32 saveDPLL_B; | |
560 | u32 saveDPLL_B_MD; | |
561 | u32 saveHTOTAL_B; | |
562 | u32 saveHBLANK_B; | |
563 | u32 saveHSYNC_B; | |
564 | u32 saveVTOTAL_B; | |
565 | u32 saveVBLANK_B; | |
566 | u32 saveVSYNC_B; | |
567 | u32 saveBCLRPAT_B; | |
5586c8bc | 568 | u32 saveTRANSBCONF; |
42048781 ZW |
569 | u32 saveTRANS_HTOTAL_B; |
570 | u32 saveTRANS_HBLANK_B; | |
571 | u32 saveTRANS_HSYNC_B; | |
572 | u32 saveTRANS_VTOTAL_B; | |
573 | u32 saveTRANS_VBLANK_B; | |
574 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 575 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
576 | u32 saveDSPBSTRIDE; |
577 | u32 saveDSPBSIZE; | |
578 | u32 saveDSPBPOS; | |
585fb111 | 579 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
580 | u32 saveDSPBSURF; |
581 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
582 | u32 saveVGA0; |
583 | u32 saveVGA1; | |
584 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
585 | u32 saveVGACNTRL; |
586 | u32 saveADPA; | |
587 | u32 saveLVDS; | |
585fb111 JB |
588 | u32 savePP_ON_DELAYS; |
589 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
590 | u32 saveDVOA; |
591 | u32 saveDVOB; | |
592 | u32 saveDVOC; | |
593 | u32 savePP_ON; | |
594 | u32 savePP_OFF; | |
595 | u32 savePP_CONTROL; | |
585fb111 | 596 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
597 | u32 savePFIT_CONTROL; |
598 | u32 save_palette_a[256]; | |
599 | u32 save_palette_b[256]; | |
06027f91 | 600 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
601 | u32 saveFBC_CFB_BASE; |
602 | u32 saveFBC_LL_BASE; | |
603 | u32 saveFBC_CONTROL; | |
604 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
605 | u32 saveIER; |
606 | u32 saveIIR; | |
607 | u32 saveIMR; | |
42048781 ZW |
608 | u32 saveDEIER; |
609 | u32 saveDEIMR; | |
610 | u32 saveGTIER; | |
611 | u32 saveGTIMR; | |
612 | u32 saveFDI_RXA_IMR; | |
613 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 614 | u32 saveCACHE_MODE_0; |
1f84e550 | 615 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
616 | u32 saveSWF0[16]; |
617 | u32 saveSWF1[16]; | |
618 | u32 saveSWF2[3]; | |
619 | u8 saveMSR; | |
620 | u8 saveSR[8]; | |
123f794f | 621 | u8 saveGR[25]; |
ba8bbcf6 | 622 | u8 saveAR_INDEX; |
a59e122a | 623 | u8 saveAR[21]; |
ba8bbcf6 | 624 | u8 saveDACMASK; |
a59e122a | 625 | u8 saveCR[37]; |
4b9de737 | 626 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
627 | u32 saveCURACNTR; |
628 | u32 saveCURAPOS; | |
629 | u32 saveCURABASE; | |
630 | u32 saveCURBCNTR; | |
631 | u32 saveCURBPOS; | |
632 | u32 saveCURBBASE; | |
633 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
634 | u32 saveDP_B; |
635 | u32 saveDP_C; | |
636 | u32 saveDP_D; | |
637 | u32 savePIPEA_GMCH_DATA_M; | |
638 | u32 savePIPEB_GMCH_DATA_M; | |
639 | u32 savePIPEA_GMCH_DATA_N; | |
640 | u32 savePIPEB_GMCH_DATA_N; | |
641 | u32 savePIPEA_DP_LINK_M; | |
642 | u32 savePIPEB_DP_LINK_M; | |
643 | u32 savePIPEA_DP_LINK_N; | |
644 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
645 | u32 saveFDI_RXA_CTL; |
646 | u32 saveFDI_TXA_CTL; | |
647 | u32 saveFDI_RXB_CTL; | |
648 | u32 saveFDI_TXB_CTL; | |
649 | u32 savePFA_CTL_1; | |
650 | u32 savePFB_CTL_1; | |
651 | u32 savePFA_WIN_SZ; | |
652 | u32 savePFB_WIN_SZ; | |
653 | u32 savePFA_WIN_POS; | |
654 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
655 | u32 savePCH_DREF_CONTROL; |
656 | u32 saveDISP_ARB_CTL; | |
657 | u32 savePIPEA_DATA_M1; | |
658 | u32 savePIPEA_DATA_N1; | |
659 | u32 savePIPEA_LINK_M1; | |
660 | u32 savePIPEA_LINK_N1; | |
661 | u32 savePIPEB_DATA_M1; | |
662 | u32 savePIPEB_DATA_N1; | |
663 | u32 savePIPEB_LINK_M1; | |
664 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 665 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 666 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 667 | }; |
c85aa885 DV |
668 | |
669 | struct intel_gen6_power_mgmt { | |
670 | struct work_struct work; | |
671 | u32 pm_iir; | |
672 | /* lock - irqsave spinlock that protectects the work_struct and | |
673 | * pm_iir. */ | |
674 | spinlock_t lock; | |
675 | ||
676 | /* The below variables an all the rps hw state are protected by | |
677 | * dev->struct mutext. */ | |
678 | u8 cur_delay; | |
679 | u8 min_delay; | |
680 | u8 max_delay; | |
31c77388 | 681 | u8 hw_max; |
1a01ab3b JB |
682 | |
683 | struct delayed_work delayed_resume_work; | |
4fc688ce JB |
684 | |
685 | /* | |
686 | * Protects RPS/RC6 register access and PCU communication. | |
687 | * Must be taken after struct_mutex if nested. | |
688 | */ | |
689 | struct mutex hw_lock; | |
c85aa885 DV |
690 | }; |
691 | ||
1a240d4d DV |
692 | /* defined intel_pm.c */ |
693 | extern spinlock_t mchdev_lock; | |
694 | ||
c85aa885 DV |
695 | struct intel_ilk_power_mgmt { |
696 | u8 cur_delay; | |
697 | u8 min_delay; | |
698 | u8 max_delay; | |
699 | u8 fmax; | |
700 | u8 fstart; | |
701 | ||
702 | u64 last_count1; | |
703 | unsigned long last_time1; | |
704 | unsigned long chipset_power; | |
705 | u64 last_count2; | |
706 | struct timespec last_time2; | |
707 | unsigned long gfx_power; | |
708 | u8 corr; | |
709 | ||
710 | int c_m; | |
711 | int r_t; | |
3e373948 DV |
712 | |
713 | struct drm_i915_gem_object *pwrctx; | |
714 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
715 | }; |
716 | ||
231f42a4 DV |
717 | struct i915_dri1_state { |
718 | unsigned allow_batchbuffer : 1; | |
719 | u32 __iomem *gfx_hws_cpu_addr; | |
720 | ||
721 | unsigned int cpp; | |
722 | int back_offset; | |
723 | int front_offset; | |
724 | int current_page; | |
725 | int page_flipping; | |
726 | ||
727 | uint32_t counter; | |
728 | }; | |
729 | ||
a4da4fa4 DV |
730 | struct intel_l3_parity { |
731 | u32 *remap_info; | |
732 | struct work_struct error_work; | |
733 | }; | |
734 | ||
4b5aed62 | 735 | struct i915_gem_mm { |
4b5aed62 DV |
736 | /** Memory allocator for GTT stolen memory */ |
737 | struct drm_mm stolen; | |
738 | /** Memory allocator for GTT */ | |
739 | struct drm_mm gtt_space; | |
740 | /** List of all objects in gtt_space. Used to restore gtt | |
741 | * mappings on resume */ | |
742 | struct list_head bound_list; | |
743 | /** | |
744 | * List of objects which are not bound to the GTT (thus | |
745 | * are idle and not used by the GPU) but still have | |
746 | * (presumably uncached) pages still attached. | |
747 | */ | |
748 | struct list_head unbound_list; | |
749 | ||
750 | /** Usable portion of the GTT for GEM */ | |
751 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
752 | ||
753 | int gtt_mtrr; | |
754 | ||
755 | /** PPGTT used for aliasing the PPGTT with the GTT */ | |
756 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
757 | ||
758 | struct shrinker inactive_shrinker; | |
759 | bool shrinker_no_lock_stealing; | |
760 | ||
761 | /** | |
762 | * List of objects currently involved in rendering. | |
763 | * | |
764 | * Includes buffers having the contents of their GPU caches | |
765 | * flushed, not necessarily primitives. last_rendering_seqno | |
766 | * represents when the rendering involved will be completed. | |
767 | * | |
768 | * A reference is held on the buffer while on this list. | |
769 | */ | |
770 | struct list_head active_list; | |
771 | ||
772 | /** | |
773 | * LRU list of objects which are not in the ringbuffer and | |
774 | * are ready to unbind, but are still in the GTT. | |
775 | * | |
776 | * last_rendering_seqno is 0 while an object is in this list. | |
777 | * | |
778 | * A reference is not held on the buffer while on this list, | |
779 | * as merely being GTT-bound shouldn't prevent its being | |
780 | * freed, and we'll pull it off the list in the free path. | |
781 | */ | |
782 | struct list_head inactive_list; | |
783 | ||
784 | /** LRU list of objects with fence regs on them. */ | |
785 | struct list_head fence_list; | |
786 | ||
787 | /** | |
788 | * We leave the user IRQ off as much as possible, | |
789 | * but this means that requests will finish and never | |
790 | * be retired once the system goes idle. Set a timer to | |
791 | * fire periodically while the ring is running. When it | |
792 | * fires, go retire requests. | |
793 | */ | |
794 | struct delayed_work retire_work; | |
795 | ||
796 | /** | |
797 | * Are we in a non-interruptible section of code like | |
798 | * modesetting? | |
799 | */ | |
800 | bool interruptible; | |
801 | ||
802 | /** | |
803 | * Flag if the X Server, and thus DRM, is not currently in | |
804 | * control of the device. | |
805 | * | |
806 | * This is set between LeaveVT and EnterVT. It needs to be | |
807 | * replaced with a semaphore. It also needs to be | |
808 | * transitioned away from for kernel modesetting. | |
809 | */ | |
810 | int suspended; | |
811 | ||
4b5aed62 DV |
812 | /** Bit 6 swizzling required for X tiling */ |
813 | uint32_t bit_6_swizzle_x; | |
814 | /** Bit 6 swizzling required for Y tiling */ | |
815 | uint32_t bit_6_swizzle_y; | |
816 | ||
817 | /* storage for physical objects */ | |
818 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
819 | ||
820 | /* accounting, useful for userland debugging */ | |
821 | size_t object_memory; | |
822 | u32 object_count; | |
823 | }; | |
824 | ||
99584db3 DV |
825 | struct i915_gpu_error { |
826 | /* For hangcheck timer */ | |
827 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
828 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
829 | struct timer_list hangcheck_timer; | |
830 | int hangcheck_count; | |
831 | uint32_t last_acthd[I915_NUM_RINGS]; | |
832 | uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; | |
833 | ||
834 | /* For reset and error_state handling. */ | |
835 | spinlock_t lock; | |
836 | /* Protected by the above dev->gpu_error.lock. */ | |
837 | struct drm_i915_error_state *first_error; | |
838 | struct work_struct work; | |
99584db3 DV |
839 | |
840 | unsigned long last_reset; | |
841 | ||
1f83fee0 | 842 | /** |
f69061be | 843 | * State variable and reset counter controlling the reset flow |
1f83fee0 | 844 | * |
f69061be DV |
845 | * Upper bits are for the reset counter. This counter is used by the |
846 | * wait_seqno code to race-free noticed that a reset event happened and | |
847 | * that it needs to restart the entire ioctl (since most likely the | |
848 | * seqno it waited for won't ever signal anytime soon). | |
849 | * | |
850 | * This is important for lock-free wait paths, where no contended lock | |
851 | * naturally enforces the correct ordering between the bail-out of the | |
852 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
853 | * |
854 | * Lowest bit controls the reset state machine: Set means a reset is in | |
855 | * progress. This state will (presuming we don't have any bugs) decay | |
856 | * into either unset (successful reset) or the special WEDGED value (hw | |
857 | * terminally sour). All waiters on the reset_queue will be woken when | |
858 | * that happens. | |
859 | */ | |
860 | atomic_t reset_counter; | |
861 | ||
862 | /** | |
863 | * Special values/flags for reset_counter | |
864 | * | |
865 | * Note that the code relies on | |
866 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG | |
867 | * being true. | |
868 | */ | |
869 | #define I915_RESET_IN_PROGRESS_FLAG 1 | |
870 | #define I915_WEDGED 0xffffffff | |
871 | ||
872 | /** | |
873 | * Waitqueue to signal when the reset has completed. Used by clients | |
874 | * that wait for dev_priv->mm.wedged to settle. | |
875 | */ | |
876 | wait_queue_head_t reset_queue; | |
33196ded | 877 | |
99584db3 DV |
878 | /* For gpu hang simulation. */ |
879 | unsigned int stop_rings; | |
880 | }; | |
881 | ||
b8efb17b ZR |
882 | enum modeset_restore { |
883 | MODESET_ON_LID_OPEN, | |
884 | MODESET_DONE, | |
885 | MODESET_SUSPENDED, | |
886 | }; | |
887 | ||
f4c956ad DV |
888 | typedef struct drm_i915_private { |
889 | struct drm_device *dev; | |
42dcedd4 | 890 | struct kmem_cache *slab; |
f4c956ad DV |
891 | |
892 | const struct intel_device_info *info; | |
893 | ||
894 | int relative_constants_mode; | |
895 | ||
896 | void __iomem *regs; | |
897 | ||
898 | struct drm_i915_gt_funcs gt; | |
899 | /** gt_fifo_count and the subsequent register write are synchronized | |
900 | * with dev->struct_mutex. */ | |
901 | unsigned gt_fifo_count; | |
902 | /** forcewake_count is protected by gt_lock */ | |
903 | unsigned forcewake_count; | |
904 | /** gt_lock is also taken in irq contexts. */ | |
99057c81 | 905 | spinlock_t gt_lock; |
f4c956ad DV |
906 | |
907 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
908 | ||
28c70f16 | 909 | |
f4c956ad DV |
910 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
911 | * controller on different i2c buses. */ | |
912 | struct mutex gmbus_mutex; | |
913 | ||
914 | /** | |
915 | * Base address of the gmbus and gpio block. | |
916 | */ | |
917 | uint32_t gpio_mmio_base; | |
918 | ||
28c70f16 DV |
919 | wait_queue_head_t gmbus_wait_queue; |
920 | ||
f4c956ad DV |
921 | struct pci_dev *bridge_dev; |
922 | struct intel_ring_buffer ring[I915_NUM_RINGS]; | |
f72b3435 | 923 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
924 | |
925 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
926 | struct resource mch_res; |
927 | ||
928 | atomic_t irq_received; | |
929 | ||
930 | /* protects the irq masks */ | |
931 | spinlock_t irq_lock; | |
932 | ||
9ee32fea DV |
933 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
934 | struct pm_qos_request pm_qos; | |
935 | ||
f4c956ad | 936 | /* DPIO indirect register protection */ |
09153000 | 937 | struct mutex dpio_lock; |
f4c956ad DV |
938 | |
939 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
f4c956ad DV |
940 | u32 irq_mask; |
941 | u32 gt_irq_mask; | |
f4c956ad | 942 | |
f4c956ad | 943 | struct work_struct hotplug_work; |
52d7eced | 944 | bool enable_hotplug_processing; |
b543fb04 EE |
945 | struct { |
946 | unsigned long hpd_last_jiffies; | |
947 | int hpd_cnt; | |
948 | enum { | |
949 | HPD_ENABLED = 0, | |
950 | HPD_DISABLED = 1, | |
951 | HPD_MARK_DISABLED = 2 | |
952 | } hpd_mark; | |
953 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 954 | u32 hpd_event_bits; |
ac4c16c5 | 955 | struct timer_list hotplug_reenable_timer; |
f4c956ad | 956 | |
f4c956ad | 957 | int num_pch_pll; |
7f1f3851 | 958 | int num_plane; |
f4c956ad | 959 | |
f4c956ad DV |
960 | unsigned long cfb_size; |
961 | unsigned int cfb_fb; | |
962 | enum plane cfb_plane; | |
963 | int cfb_y; | |
964 | struct intel_fbc_work *fbc_work; | |
965 | ||
966 | struct intel_opregion opregion; | |
967 | ||
968 | /* overlay */ | |
969 | struct intel_overlay *overlay; | |
2c6602df | 970 | unsigned int sprite_scaling_enabled; |
f4c956ad | 971 | |
31ad8ec6 JN |
972 | /* backlight */ |
973 | struct { | |
974 | int level; | |
975 | bool enabled; | |
976 | struct backlight_device *device; | |
977 | } backlight; | |
978 | ||
f4c956ad | 979 | /* LVDS info */ |
f4c956ad DV |
980 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
981 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
982 | ||
983 | /* Feature bits from the VBIOS */ | |
984 | unsigned int int_tv_support:1; | |
985 | unsigned int lvds_dither:1; | |
986 | unsigned int lvds_vbt:1; | |
987 | unsigned int int_crt_support:1; | |
988 | unsigned int lvds_use_ssc:1; | |
989 | unsigned int display_clock_mode:1; | |
3f704fa2 | 990 | unsigned int fdi_rx_polarity_inverted:1; |
f4c956ad DV |
991 | int lvds_ssc_freq; |
992 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
f4c956ad DV |
993 | struct { |
994 | int rate; | |
995 | int lanes; | |
996 | int preemphasis; | |
997 | int vswing; | |
998 | ||
999 | bool initialized; | |
1000 | bool support; | |
1001 | int bpp; | |
1002 | struct edp_power_seq pps; | |
1003 | } edp; | |
1004 | bool no_aux_handshake; | |
1005 | ||
1006 | int crt_ddc_pin; | |
1007 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ | |
1008 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1009 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1010 | ||
1011 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
1012 | ||
f4c956ad DV |
1013 | struct workqueue_struct *wq; |
1014 | ||
1015 | /* Display functions */ | |
1016 | struct drm_i915_display_funcs display; | |
1017 | ||
1018 | /* PCH chipset type */ | |
1019 | enum intel_pch pch_type; | |
17a303ec | 1020 | unsigned short pch_id; |
f4c956ad DV |
1021 | |
1022 | unsigned long quirks; | |
1023 | ||
b8efb17b ZR |
1024 | enum modeset_restore modeset_restore; |
1025 | struct mutex modeset_restore_lock; | |
673a394b | 1026 | |
5d4545ae BW |
1027 | struct i915_gtt gtt; |
1028 | ||
4b5aed62 | 1029 | struct i915_gem_mm mm; |
8781342d | 1030 | |
8781342d DV |
1031 | /* Kernel Modesetting */ |
1032 | ||
9b9d172d | 1033 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
1034 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
1035 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
1036 | /* Panel fitter placement and size for Ironlake+ */ |
1037 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 1038 | |
27f8227b JB |
1039 | struct drm_crtc *plane_to_crtc_mapping[3]; |
1040 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
1041 | wait_queue_head_t pending_flip_queue; |
1042 | ||
ee7b9f93 | 1043 | struct intel_pch_pll pch_plls[I915_NUM_PLLS]; |
6441ab5f | 1044 | struct intel_ddi_plls ddi_plls; |
ee7b9f93 | 1045 | |
652c393a JB |
1046 | /* Reclocking support */ |
1047 | bool render_reclock_avail; | |
1048 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1049 | /* indicates the reduced downclock for LVDS*/ |
1050 | int lvds_downclock; | |
652c393a | 1051 | u16 orig_clock; |
6363ee6f ZY |
1052 | int child_dev_num; |
1053 | struct child_device_config *child_dev; | |
f97108d1 | 1054 | |
c4804411 | 1055 | bool mchbar_need_disable; |
f97108d1 | 1056 | |
a4da4fa4 DV |
1057 | struct intel_l3_parity l3_parity; |
1058 | ||
c6a828d3 | 1059 | /* gen6+ rps state */ |
c85aa885 | 1060 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1061 | |
20e4d407 DV |
1062 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1063 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1064 | struct intel_ilk_power_mgmt ips; |
b5e50c3f JB |
1065 | |
1066 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 1067 | |
20bf377e JB |
1068 | struct drm_mm_node *compressed_fb; |
1069 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 1070 | |
99584db3 | 1071 | struct i915_gpu_error gpu_error; |
ae681d96 | 1072 | |
8be48d92 DA |
1073 | /* list of fbdev register on this device */ |
1074 | struct intel_fbdev *fbdev; | |
e953fd7b | 1075 | |
073f34d9 JB |
1076 | /* |
1077 | * The console may be contended at resume, but we don't | |
1078 | * want it to block on it. | |
1079 | */ | |
1080 | struct work_struct console_resume_work; | |
1081 | ||
e953fd7b | 1082 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1083 | struct drm_property *force_audio_property; |
e3689190 | 1084 | |
254f965c BW |
1085 | bool hw_contexts_disabled; |
1086 | uint32_t hw_context_size; | |
f4c956ad | 1087 | |
3e68320e | 1088 | u32 fdi_rx_config; |
68d18ad7 | 1089 | |
f4c956ad | 1090 | struct i915_suspend_saved_registers regfile; |
231f42a4 DV |
1091 | |
1092 | /* Old dri1 support infrastructure, beware the dragons ya fools entering | |
1093 | * here! */ | |
1094 | struct i915_dri1_state dri1; | |
1da177e4 LT |
1095 | } drm_i915_private_t; |
1096 | ||
b4519513 CW |
1097 | /* Iterate over initialised rings */ |
1098 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1099 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1100 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1101 | ||
b1d7e4b4 WF |
1102 | enum hdmi_force_audio { |
1103 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1104 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1105 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1106 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1107 | }; | |
1108 | ||
ed2f3452 CW |
1109 | #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) |
1110 | ||
37e680a1 CW |
1111 | struct drm_i915_gem_object_ops { |
1112 | /* Interface between the GEM object and its backing storage. | |
1113 | * get_pages() is called once prior to the use of the associated set | |
1114 | * of pages before to binding them into the GTT, and put_pages() is | |
1115 | * called after we no longer need them. As we expect there to be | |
1116 | * associated cost with migrating pages between the backing storage | |
1117 | * and making them available for the GPU (e.g. clflush), we may hold | |
1118 | * onto the pages after they are no longer referenced by the GPU | |
1119 | * in case they may be used again shortly (for example migrating the | |
1120 | * pages to a different memory domain within the GTT). put_pages() | |
1121 | * will therefore most likely be called when the object itself is | |
1122 | * being released or under memory pressure (where we attempt to | |
1123 | * reap pages for the shrinker). | |
1124 | */ | |
1125 | int (*get_pages)(struct drm_i915_gem_object *); | |
1126 | void (*put_pages)(struct drm_i915_gem_object *); | |
1127 | }; | |
1128 | ||
673a394b | 1129 | struct drm_i915_gem_object { |
c397b908 | 1130 | struct drm_gem_object base; |
673a394b | 1131 | |
37e680a1 CW |
1132 | const struct drm_i915_gem_object_ops *ops; |
1133 | ||
673a394b EA |
1134 | /** Current space allocated to this object in the GTT, if any. */ |
1135 | struct drm_mm_node *gtt_space; | |
c1ad11fc CW |
1136 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1137 | struct drm_mm_node *stolen; | |
93a37f20 | 1138 | struct list_head gtt_list; |
673a394b | 1139 | |
65ce3027 | 1140 | /** This object's place on the active/inactive lists */ |
69dc4987 CW |
1141 | struct list_head ring_list; |
1142 | struct list_head mm_list; | |
432e58ed CW |
1143 | /** This object's place in the batchbuffer or on the eviction list */ |
1144 | struct list_head exec_list; | |
673a394b EA |
1145 | |
1146 | /** | |
65ce3027 CW |
1147 | * This is set if the object is on the active lists (has pending |
1148 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1149 | * inactive (ready to be unbound) list. | |
673a394b | 1150 | */ |
0206e353 | 1151 | unsigned int active:1; |
673a394b EA |
1152 | |
1153 | /** | |
1154 | * This is set if the object has been written to since last bound | |
1155 | * to the GTT | |
1156 | */ | |
0206e353 | 1157 | unsigned int dirty:1; |
778c3544 DV |
1158 | |
1159 | /** | |
1160 | * Fence register bits (if any) for this object. Will be set | |
1161 | * as needed when mapped into the GTT. | |
1162 | * Protected by dev->struct_mutex. | |
778c3544 | 1163 | */ |
4b9de737 | 1164 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1165 | |
778c3544 DV |
1166 | /** |
1167 | * Advice: are the backing pages purgeable? | |
1168 | */ | |
0206e353 | 1169 | unsigned int madv:2; |
778c3544 | 1170 | |
778c3544 DV |
1171 | /** |
1172 | * Current tiling mode for the object. | |
1173 | */ | |
0206e353 | 1174 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1175 | /** |
1176 | * Whether the tiling parameters for the currently associated fence | |
1177 | * register have changed. Note that for the purposes of tracking | |
1178 | * tiling changes we also treat the unfenced register, the register | |
1179 | * slot that the object occupies whilst it executes a fenced | |
1180 | * command (such as BLT on gen2/3), as a "fence". | |
1181 | */ | |
1182 | unsigned int fence_dirty:1; | |
778c3544 DV |
1183 | |
1184 | /** How many users have pinned this object in GTT space. The following | |
1185 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
1186 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
1187 | * times for the same batchbuffer), and the framebuffer code. When | |
1188 | * switching/pageflipping, the framebuffer code has at most two buffers | |
1189 | * pinned per crtc. | |
1190 | * | |
1191 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
1192 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 1193 | unsigned int pin_count:4; |
778c3544 | 1194 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 1195 | |
75e9e915 DV |
1196 | /** |
1197 | * Is the object at the current location in the gtt mappable and | |
1198 | * fenceable? Used to avoid costly recalculations. | |
1199 | */ | |
0206e353 | 1200 | unsigned int map_and_fenceable:1; |
75e9e915 | 1201 | |
fb7d516a DV |
1202 | /** |
1203 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1204 | * mappable by accident). Track pin and fault separate for a more | |
1205 | * accurate mappable working set. | |
1206 | */ | |
0206e353 AJ |
1207 | unsigned int fault_mappable:1; |
1208 | unsigned int pin_mappable:1; | |
fb7d516a | 1209 | |
caea7476 CW |
1210 | /* |
1211 | * Is the GPU currently using a fence to access this buffer, | |
1212 | */ | |
1213 | unsigned int pending_fenced_gpu_access:1; | |
1214 | unsigned int fenced_gpu_access:1; | |
1215 | ||
93dfb40c CW |
1216 | unsigned int cache_level:2; |
1217 | ||
7bddb01f | 1218 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1219 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1220 | unsigned int has_dma_mapping:1; |
7bddb01f | 1221 | |
9da3da66 | 1222 | struct sg_table *pages; |
a5570178 | 1223 | int pages_pin_count; |
673a394b | 1224 | |
1286ff73 | 1225 | /* prime dma-buf support */ |
9a70cc2a DA |
1226 | void *dma_buf_vmapping; |
1227 | int vmapping_count; | |
1228 | ||
67731b87 CW |
1229 | /** |
1230 | * Used for performing relocations during execbuffer insertion. | |
1231 | */ | |
1232 | struct hlist_node exec_node; | |
1233 | unsigned long exec_handle; | |
6fe4f140 | 1234 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 1235 | |
673a394b EA |
1236 | /** |
1237 | * Current offset of the object in GTT space. | |
1238 | * | |
1239 | * This is the same as gtt_space->start | |
1240 | */ | |
1241 | uint32_t gtt_offset; | |
e67b8ce1 | 1242 | |
caea7476 CW |
1243 | struct intel_ring_buffer *ring; |
1244 | ||
1c293ea3 | 1245 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1246 | uint32_t last_read_seqno; |
1247 | uint32_t last_write_seqno; | |
caea7476 CW |
1248 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1249 | uint32_t last_fenced_seqno; | |
673a394b | 1250 | |
778c3544 | 1251 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1252 | uint32_t stride; |
673a394b | 1253 | |
280b713b | 1254 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1255 | unsigned long *bit_17; |
280b713b | 1256 | |
79e53945 JB |
1257 | /** User space pin count and filp owning the pin */ |
1258 | uint32_t user_pin_count; | |
1259 | struct drm_file *pin_filp; | |
71acb5eb DA |
1260 | |
1261 | /** for phy allocated objects */ | |
1262 | struct drm_i915_gem_phys_object *phys_obj; | |
673a394b | 1263 | }; |
b45305fc | 1264 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
673a394b | 1265 | |
62b8b215 | 1266 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1267 | |
673a394b EA |
1268 | /** |
1269 | * Request queue structure. | |
1270 | * | |
1271 | * The request queue allows us to note sequence numbers that have been emitted | |
1272 | * and may be associated with active buffers to be retired. | |
1273 | * | |
1274 | * By keeping this list, we can avoid having to do questionable | |
1275 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1276 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1277 | */ | |
1278 | struct drm_i915_gem_request { | |
852835f3 ZN |
1279 | /** On Which ring this request was generated */ |
1280 | struct intel_ring_buffer *ring; | |
1281 | ||
673a394b EA |
1282 | /** GEM sequence number associated with this request. */ |
1283 | uint32_t seqno; | |
1284 | ||
a71d8d94 CW |
1285 | /** Postion in the ringbuffer of the end of the request */ |
1286 | u32 tail; | |
1287 | ||
673a394b EA |
1288 | /** Time at which this request was emitted, in jiffies. */ |
1289 | unsigned long emitted_jiffies; | |
1290 | ||
b962442e | 1291 | /** global list entry for this request */ |
673a394b | 1292 | struct list_head list; |
b962442e | 1293 | |
f787a5f5 | 1294 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1295 | /** file_priv list entry for this request */ |
1296 | struct list_head client_list; | |
673a394b EA |
1297 | }; |
1298 | ||
1299 | struct drm_i915_file_private { | |
1300 | struct { | |
99057c81 | 1301 | spinlock_t lock; |
b962442e | 1302 | struct list_head request_list; |
673a394b | 1303 | } mm; |
40521054 | 1304 | struct idr context_idr; |
673a394b EA |
1305 | }; |
1306 | ||
cae5852d ZN |
1307 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1308 | ||
1309 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1310 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1311 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
1312 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1313 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1314 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1315 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1316 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1317 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1318 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
1319 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1320 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1321 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1322 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1323 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1324 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
1325 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
1326 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 1327 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
8ab43976 JB |
1328 | #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ |
1329 | (dev)->pci_device == 0x0152 || \ | |
1330 | (dev)->pci_device == 0x015a) | |
6547fbdb DV |
1331 | #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ |
1332 | (dev)->pci_device == 0x0106 || \ | |
1333 | (dev)->pci_device == 0x010A) | |
70a3eb7a | 1334 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1335 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
cae5852d | 1336 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
d567b07f PZ |
1337 | #define IS_ULT(dev) (IS_HASWELL(dev) && \ |
1338 | ((dev)->pci_device & 0xFF00) == 0x0A00) | |
cae5852d | 1339 | |
85436696 JB |
1340 | /* |
1341 | * The genX designation typically refers to the render engine, so render | |
1342 | * capability related checks should use IS_GEN, while display and other checks | |
1343 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1344 | * chips, etc.). | |
1345 | */ | |
cae5852d ZN |
1346 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1347 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1348 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1349 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1350 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1351 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
1352 | |
1353 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
1354 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
3d29b842 | 1355 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
cae5852d ZN |
1356 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1357 | ||
254f965c | 1358 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
93553609 | 1359 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
1d2a314c | 1360 | |
05394f39 | 1361 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1362 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1363 | ||
b45305fc DV |
1364 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1365 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
1366 | ||
cae5852d ZN |
1367 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1368 | * rows, which changed the alignment requirements and fence programming. | |
1369 | */ | |
1370 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1371 | IS_I915GM(dev))) | |
1372 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1373 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1374 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1375 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
1376 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
1377 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
1378 | /* dsparb controlled by hw only */ | |
1379 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1380 | ||
1381 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1382 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1383 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1384 | |
eceae481 | 1385 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
cae5852d | 1386 | |
affa9354 | 1387 | #define HAS_DDI(dev) (IS_HASWELL(dev)) |
86d52df6 | 1388 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) |
affa9354 | 1389 | |
17a303ec PZ |
1390 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1391 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
1392 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
1393 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
1394 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
1395 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
1396 | ||
cae5852d | 1397 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
eb877ebf | 1398 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1399 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1400 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 1401 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 1402 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1403 | |
b7884eb4 DV |
1404 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
1405 | ||
f27b9265 | 1406 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
e1ef7cc2 | 1407 | |
c8735b0c BW |
1408 | #define GT_FREQUENCY_MULTIPLIER 50 |
1409 | ||
05394f39 CW |
1410 | #include "i915_trace.h" |
1411 | ||
83b7f9ac ED |
1412 | /** |
1413 | * RC6 is a special power stage which allows the GPU to enter an very | |
1414 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
1415 | * stage is entered automatically when the GPU is idle when RC6 support is | |
1416 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
1417 | * | |
1418 | * There are different RC6 modes available in Intel GPU, which differentiate | |
1419 | * among each other with the latency required to enter and leave RC6 and | |
1420 | * voltage consumed by the GPU in different states. | |
1421 | * | |
1422 | * The combination of the following flags define which states GPU is allowed | |
1423 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
1424 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
1425 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
1426 | * which brings the most power savings; deeper states save more power, but | |
1427 | * require higher latency to switch to and wake up. | |
1428 | */ | |
1429 | #define INTEL_RC6_ENABLE (1<<0) | |
1430 | #define INTEL_RC6p_ENABLE (1<<1) | |
1431 | #define INTEL_RC6pp_ENABLE (1<<2) | |
1432 | ||
c153f45f | 1433 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1434 | extern int i915_max_ioctl; |
a35d9d3c BW |
1435 | extern unsigned int i915_fbpercrtc __always_unused; |
1436 | extern int i915_panel_ignore_lid __read_mostly; | |
1437 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1438 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1439 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1440 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1441 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1442 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1443 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1444 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1445 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1446 | extern int i915_enable_ppgtt __read_mostly; |
0a3af268 | 1447 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
2124b72e | 1448 | extern int i915_disable_power_well __read_mostly; |
b3a83639 | 1449 | |
6a9ee8af DA |
1450 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1451 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1452 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1453 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1454 | ||
1da177e4 | 1455 | /* i915_dma.c */ |
d05c617e | 1456 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1457 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1458 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1459 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1460 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1461 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1462 | extern void i915_driver_preclose(struct drm_device *dev, |
1463 | struct drm_file *file_priv); | |
673a394b EA |
1464 | extern void i915_driver_postclose(struct drm_device *dev, |
1465 | struct drm_file *file_priv); | |
84b1fd10 | 1466 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1467 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1468 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1469 | unsigned long arg); | |
c43b5634 | 1470 | #endif |
673a394b | 1471 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1472 | struct drm_clip_rect *box, |
1473 | int DR1, int DR4); | |
8e96d9c4 | 1474 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1475 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
1476 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1477 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1478 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1479 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1480 | ||
073f34d9 | 1481 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 1482 | |
1da177e4 | 1483 | /* i915_irq.c */ |
f65d9421 | 1484 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1485 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 1486 | |
f71d4af4 | 1487 | extern void intel_irq_init(struct drm_device *dev); |
20afbda2 | 1488 | extern void intel_hpd_init(struct drm_device *dev); |
990bbdad | 1489 | extern void intel_gt_init(struct drm_device *dev); |
16995a9f | 1490 | extern void intel_gt_reset(struct drm_device *dev); |
b1f14ad0 | 1491 | |
742cbee8 DV |
1492 | void i915_error_state_free(struct kref *error_ref); |
1493 | ||
7c463586 KP |
1494 | void |
1495 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1496 | ||
1497 | void | |
1498 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1499 | ||
0206e353 | 1500 | void intel_enable_asle(struct drm_device *dev); |
01c66889 | 1501 | |
3bd3c932 CW |
1502 | #ifdef CONFIG_DEBUG_FS |
1503 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1504 | #else | |
1505 | #define i915_destroy_error_state(x) | |
1506 | #endif | |
1507 | ||
7c463586 | 1508 | |
673a394b EA |
1509 | /* i915_gem.c */ |
1510 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1511 | struct drm_file *file_priv); | |
1512 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1513 | struct drm_file *file_priv); | |
1514 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1515 | struct drm_file *file_priv); | |
1516 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1517 | struct drm_file *file_priv); | |
1518 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1519 | struct drm_file *file_priv); | |
de151cf6 JB |
1520 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1521 | struct drm_file *file_priv); | |
673a394b EA |
1522 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1523 | struct drm_file *file_priv); | |
1524 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1525 | struct drm_file *file_priv); | |
1526 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1527 | struct drm_file *file_priv); | |
76446cac JB |
1528 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1529 | struct drm_file *file_priv); | |
673a394b EA |
1530 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1531 | struct drm_file *file_priv); | |
1532 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1533 | struct drm_file *file_priv); | |
1534 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1535 | struct drm_file *file_priv); | |
199adf40 BW |
1536 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1537 | struct drm_file *file); | |
1538 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
1539 | struct drm_file *file); | |
673a394b EA |
1540 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1541 | struct drm_file *file_priv); | |
3ef94daa CW |
1542 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1543 | struct drm_file *file_priv); | |
673a394b EA |
1544 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1545 | struct drm_file *file_priv); | |
1546 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1547 | struct drm_file *file_priv); | |
1548 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1549 | struct drm_file *file_priv); | |
1550 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1551 | struct drm_file *file_priv); | |
5a125c3c EA |
1552 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1553 | struct drm_file *file_priv); | |
23ba4fd0 BW |
1554 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1555 | struct drm_file *file_priv); | |
673a394b | 1556 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
1557 | void *i915_gem_object_alloc(struct drm_device *dev); |
1558 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
673a394b | 1559 | int i915_gem_init_object(struct drm_gem_object *obj); |
37e680a1 CW |
1560 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1561 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
1562 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1563 | size_t size); | |
673a394b | 1564 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 1565 | |
2021746e CW |
1566 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1567 | uint32_t alignment, | |
86a1ee26 CW |
1568 | bool map_and_fenceable, |
1569 | bool nonblocking); | |
05394f39 | 1570 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1571 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
dd624afd | 1572 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
05394f39 | 1573 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1574 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1575 | |
37e680a1 | 1576 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
1577 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
1578 | { | |
67d5a50c ID |
1579 | struct sg_page_iter sg_iter; |
1580 | ||
1581 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 1582 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
1583 | |
1584 | return NULL; | |
9da3da66 | 1585 | } |
a5570178 CW |
1586 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
1587 | { | |
1588 | BUG_ON(obj->pages == NULL); | |
1589 | obj->pages_pin_count++; | |
1590 | } | |
1591 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
1592 | { | |
1593 | BUG_ON(obj->pages_pin_count == 0); | |
1594 | obj->pages_pin_count--; | |
1595 | } | |
1596 | ||
54cf91dc | 1597 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
1598 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
1599 | struct intel_ring_buffer *to); | |
54cf91dc | 1600 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1601 | struct intel_ring_buffer *ring); |
54cf91dc | 1602 | |
ff72145b DA |
1603 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1604 | struct drm_device *dev, | |
1605 | struct drm_mode_create_dumb *args); | |
1606 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1607 | uint32_t handle, uint64_t *offset); | |
1608 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
0206e353 | 1609 | uint32_t handle); |
f787a5f5 CW |
1610 | /** |
1611 | * Returns true if seq1 is later than seq2. | |
1612 | */ | |
1613 | static inline bool | |
1614 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1615 | { | |
1616 | return (int32_t)(seq1 - seq2) >= 0; | |
1617 | } | |
1618 | ||
fca26bb4 MK |
1619 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
1620 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 1621 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 1622 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1623 | |
9a5a53b3 | 1624 | static inline bool |
1690e1eb CW |
1625 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
1626 | { | |
1627 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1628 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1629 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
1630 | return true; |
1631 | } else | |
1632 | return false; | |
1690e1eb CW |
1633 | } |
1634 | ||
1635 | static inline void | |
1636 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
1637 | { | |
1638 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1639 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1640 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
1641 | } | |
1642 | } | |
1643 | ||
b09a1fec | 1644 | void i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 1645 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
33196ded | 1646 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 1647 | bool interruptible); |
1f83fee0 DV |
1648 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
1649 | { | |
1650 | return unlikely(atomic_read(&error->reset_counter) | |
1651 | & I915_RESET_IN_PROGRESS_FLAG); | |
1652 | } | |
1653 | ||
1654 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
1655 | { | |
1656 | return atomic_read(&error->reset_counter) == I915_WEDGED; | |
1657 | } | |
a71d8d94 | 1658 | |
069efc1d | 1659 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1660 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1661 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1662 | uint32_t read_domains, | |
1663 | uint32_t write_domain); | |
a8198eea | 1664 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 1665 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 1666 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
b9524a1e | 1667 | void i915_gem_l3_remap(struct drm_device *dev); |
f691e2f4 | 1668 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 1669 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 1670 | int __must_check i915_gpu_idle(struct drm_device *dev); |
2021746e | 1671 | int __must_check i915_gem_idle(struct drm_device *dev); |
3bb73aba CW |
1672 | int i915_add_request(struct intel_ring_buffer *ring, |
1673 | struct drm_file *file, | |
acb868d3 | 1674 | u32 *seqno); |
199b2bc2 BW |
1675 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
1676 | uint32_t seqno); | |
de151cf6 | 1677 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1678 | int __must_check |
1679 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1680 | bool write); | |
1681 | int __must_check | |
dabdfe02 CW |
1682 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
1683 | int __must_check | |
2da3b9b9 CW |
1684 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1685 | u32 alignment, | |
2021746e | 1686 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1687 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1688 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1689 | int id, |
1690 | int align); | |
71acb5eb | 1691 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1692 | struct drm_i915_gem_object *obj); |
71acb5eb | 1693 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1694 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1695 | |
0fa87796 ID |
1696 | uint32_t |
1697 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 1698 | uint32_t |
d865110c ID |
1699 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
1700 | int tiling_mode, bool fenced); | |
467cffba | 1701 | |
e4ffd173 CW |
1702 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1703 | enum i915_cache_level cache_level); | |
1704 | ||
1286ff73 DV |
1705 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
1706 | struct dma_buf *dma_buf); | |
1707 | ||
1708 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
1709 | struct drm_gem_object *gem_obj, int flags); | |
1710 | ||
254f965c BW |
1711 | /* i915_gem_context.c */ |
1712 | void i915_gem_context_init(struct drm_device *dev); | |
1713 | void i915_gem_context_fini(struct drm_device *dev); | |
254f965c | 1714 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 BW |
1715 | int i915_switch_context(struct intel_ring_buffer *ring, |
1716 | struct drm_file *file, int to_id); | |
84624813 BW |
1717 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
1718 | struct drm_file *file); | |
1719 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
1720 | struct drm_file *file); | |
1286ff73 | 1721 | |
76aaf220 | 1722 | /* i915_gem_gtt.c */ |
1d2a314c | 1723 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
7bddb01f DV |
1724 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
1725 | struct drm_i915_gem_object *obj, | |
1726 | enum i915_cache_level cache_level); | |
1727 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
1728 | struct drm_i915_gem_object *obj); | |
1d2a314c | 1729 | |
76aaf220 | 1730 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
1731 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
1732 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 1733 | enum i915_cache_level cache_level); |
05394f39 | 1734 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 1735 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
d7e5008f BW |
1736 | void i915_gem_init_global_gtt(struct drm_device *dev); |
1737 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, | |
1738 | unsigned long mappable_end, unsigned long end); | |
e76e9aeb | 1739 | int i915_gem_gtt_init(struct drm_device *dev); |
d09105c6 | 1740 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
1741 | { |
1742 | if (INTEL_INFO(dev)->gen < 6) | |
1743 | intel_gtt_chipset_flush(); | |
1744 | } | |
1745 | ||
76aaf220 | 1746 | |
b47eb4a2 | 1747 | /* i915_gem_evict.c */ |
2021746e | 1748 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
42d6ab48 CW |
1749 | unsigned alignment, |
1750 | unsigned cache_level, | |
86a1ee26 CW |
1751 | bool mappable, |
1752 | bool nonblock); | |
6c085a72 | 1753 | int i915_gem_evict_everything(struct drm_device *dev); |
b47eb4a2 | 1754 | |
9797fbfb CW |
1755 | /* i915_gem_stolen.c */ |
1756 | int i915_gem_init_stolen(struct drm_device *dev); | |
11be49eb CW |
1757 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
1758 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); | |
9797fbfb | 1759 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
1760 | struct drm_i915_gem_object * |
1761 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
1762 | struct drm_i915_gem_object * |
1763 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
1764 | u32 stolen_offset, | |
1765 | u32 gtt_offset, | |
1766 | u32 size); | |
0104fdbb | 1767 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
9797fbfb | 1768 | |
673a394b | 1769 | /* i915_gem_tiling.c */ |
e9b73c67 CW |
1770 | inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
1771 | { | |
1772 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; | |
1773 | ||
1774 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
1775 | obj->tiling_mode != I915_TILING_NONE; | |
1776 | } | |
1777 | ||
673a394b | 1778 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
1779 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1780 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1781 | |
1782 | /* i915_gem_debug.c */ | |
05394f39 | 1783 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1784 | const char *where, uint32_t mark); |
23bc5982 CW |
1785 | #if WATCH_LISTS |
1786 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1787 | #else |
23bc5982 | 1788 | #define i915_verify_lists(dev) 0 |
673a394b | 1789 | #endif |
05394f39 CW |
1790 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1791 | int handle); | |
1792 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1793 | const char *where, uint32_t mark); |
1da177e4 | 1794 | |
2017263e | 1795 | /* i915_debugfs.c */ |
27c202ad BG |
1796 | int i915_debugfs_init(struct drm_minor *minor); |
1797 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1798 | |
317c35d1 JB |
1799 | /* i915_suspend.c */ |
1800 | extern int i915_save_state(struct drm_device *dev); | |
1801 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 1802 | |
d8157a36 DV |
1803 | /* i915_ums.c */ |
1804 | void i915_save_display_reg(struct drm_device *dev); | |
1805 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 1806 | |
0136db58 BW |
1807 | /* i915_sysfs.c */ |
1808 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
1809 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
1810 | ||
f899fc64 CW |
1811 | /* intel_i2c.c */ |
1812 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1813 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
3bd7d909 DK |
1814 | extern inline bool intel_gmbus_is_port_valid(unsigned port) |
1815 | { | |
2ed06c93 | 1816 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
1817 | } |
1818 | ||
1819 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
1820 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
1821 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1822 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1823 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1824 | { | |
1825 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1826 | } | |
f899fc64 CW |
1827 | extern void intel_i2c_reset(struct drm_device *dev); |
1828 | ||
3b617967 | 1829 | /* intel_opregion.c */ |
44834a67 CW |
1830 | extern int intel_opregion_setup(struct drm_device *dev); |
1831 | #ifdef CONFIG_ACPI | |
1832 | extern void intel_opregion_init(struct drm_device *dev); | |
1833 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1834 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1835 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1836 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1837 | #else |
44834a67 CW |
1838 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1839 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1840 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1841 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1842 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1843 | #endif |
8ee1c3db | 1844 | |
723bfd70 JB |
1845 | /* intel_acpi.c */ |
1846 | #ifdef CONFIG_ACPI | |
1847 | extern void intel_register_dsm_handler(void); | |
1848 | extern void intel_unregister_dsm_handler(void); | |
1849 | #else | |
1850 | static inline void intel_register_dsm_handler(void) { return; } | |
1851 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1852 | #endif /* CONFIG_ACPI */ | |
1853 | ||
79e53945 | 1854 | /* modesetting */ |
f817586c | 1855 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 1856 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 1857 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1858 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1859 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
1860 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
1861 | bool force_restore); | |
44cec740 | 1862 | extern void i915_redisable_vga(struct drm_device *dev); |
ee5382ae | 1863 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1864 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1865 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 1866 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 1867 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 JB |
1868 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
1869 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); | |
1870 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); | |
0206e353 AJ |
1871 | extern void intel_detect_pch(struct drm_device *dev); |
1872 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 1873 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 1874 | |
2911a35b | 1875 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
1876 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
1877 | struct drm_file *file); | |
575155a9 | 1878 | |
6ef3d427 | 1879 | /* overlay */ |
3bd3c932 | 1880 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1881 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1882 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1883 | |
1884 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1885 | extern void intel_display_print_error_state(struct seq_file *m, | |
1886 | struct drm_device *dev, | |
1887 | struct intel_display_error_state *error); | |
3bd3c932 | 1888 | #endif |
6ef3d427 | 1889 | |
b7287d80 BW |
1890 | /* On SNB platform, before reading ring registers forcewake bit |
1891 | * must be set to prevent GT core from power down and stale values being | |
1892 | * returned. | |
1893 | */ | |
fcca7926 BW |
1894 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1895 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
67a3744f | 1896 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
b7287d80 | 1897 | |
42c0526c BW |
1898 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
1899 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
a0e4e199 JB |
1900 | int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); |
1901 | int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
0a073b84 JB |
1902 | int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); |
1903 | ||
855ba3be JB |
1904 | int vlv_gpu_freq(int ddr_freq, int val); |
1905 | int vlv_freq_opcode(int ddr_freq, int val); | |
42c0526c | 1906 | |
5f75377d | 1907 | #define __i915_read(x, y) \ |
f7000883 | 1908 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
fcca7926 | 1909 | |
5f75377d KP |
1910 | __i915_read(8, b) |
1911 | __i915_read(16, w) | |
1912 | __i915_read(32, l) | |
1913 | __i915_read(64, q) | |
1914 | #undef __i915_read | |
1915 | ||
1916 | #define __i915_write(x, y) \ | |
f7000883 AK |
1917 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1918 | ||
5f75377d KP |
1919 | __i915_write(8, b) |
1920 | __i915_write(16, w) | |
1921 | __i915_write(32, l) | |
1922 | __i915_write(64, q) | |
1923 | #undef __i915_write | |
1924 | ||
1925 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1926 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1927 | ||
1928 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1929 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1930 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1931 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1932 | ||
1933 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1934 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1935 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1936 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1937 | |
1938 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1939 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1940 | |
1941 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1942 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1943 | ||
55bc60db VS |
1944 | /* "Broadcast RGB" property */ |
1945 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
1946 | #define INTEL_BROADCAST_RGB_FULL 1 | |
1947 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 1948 | |
766aa1c4 VS |
1949 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
1950 | { | |
1951 | if (HAS_PCH_SPLIT(dev)) | |
1952 | return CPU_VGACNTRL; | |
1953 | else if (IS_VALLEYVIEW(dev)) | |
1954 | return VLV_VGACNTRL; | |
1955 | else | |
1956 | return VGACNTRL; | |
1957 | } | |
1958 | ||
2bb4629a VS |
1959 | static inline void __user *to_user_ptr(u64 address) |
1960 | { | |
1961 | return (void __user *)(uintptr_t)address; | |
1962 | } | |
1963 | ||
1da177e4 | 1964 | #endif |