Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
43 | bool write); | |
44 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, | |
45 | uint64_t offset, | |
46 | uint64_t size); | |
05394f39 | 47 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
88241785 CW |
48 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
49 | unsigned alignment, | |
50 | bool map_and_fenceable); | |
d9e86c0e CW |
51 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
52 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
53 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
54 | struct drm_i915_gem_object *obj, | |
71acb5eb | 55 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
56 | struct drm_file *file); |
57 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 58 | |
17250b71 | 59 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 60 | struct shrink_control *sc); |
31169714 | 61 | |
73aa808f CW |
62 | /* some bookkeeping */ |
63 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
64 | size_t size) | |
65 | { | |
66 | dev_priv->mm.object_count++; | |
67 | dev_priv->mm.object_memory += size; | |
68 | } | |
69 | ||
70 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
71 | size_t size) | |
72 | { | |
73 | dev_priv->mm.object_count--; | |
74 | dev_priv->mm.object_memory -= size; | |
75 | } | |
76 | ||
21dd3734 CW |
77 | static int |
78 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
79 | { |
80 | struct drm_i915_private *dev_priv = dev->dev_private; | |
81 | struct completion *x = &dev_priv->error_completion; | |
82 | unsigned long flags; | |
83 | int ret; | |
84 | ||
85 | if (!atomic_read(&dev_priv->mm.wedged)) | |
86 | return 0; | |
87 | ||
88 | ret = wait_for_completion_interruptible(x); | |
89 | if (ret) | |
90 | return ret; | |
91 | ||
21dd3734 CW |
92 | if (atomic_read(&dev_priv->mm.wedged)) { |
93 | /* GPU is hung, bump the completion count to account for | |
94 | * the token we just consumed so that we never hit zero and | |
95 | * end up waiting upon a subsequent completion event that | |
96 | * will never happen. | |
97 | */ | |
98 | spin_lock_irqsave(&x->wait.lock, flags); | |
99 | x->done++; | |
100 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
101 | } | |
102 | return 0; | |
30dbf0c0 CW |
103 | } |
104 | ||
54cf91dc | 105 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 106 | { |
76c1dec1 CW |
107 | int ret; |
108 | ||
21dd3734 | 109 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
110 | if (ret) |
111 | return ret; | |
112 | ||
113 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
114 | if (ret) | |
115 | return ret; | |
116 | ||
23bc5982 | 117 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
118 | return 0; |
119 | } | |
30dbf0c0 | 120 | |
7d1c4804 | 121 | static inline bool |
05394f39 | 122 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 123 | { |
05394f39 | 124 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
125 | } |
126 | ||
2021746e CW |
127 | void i915_gem_do_init(struct drm_device *dev, |
128 | unsigned long start, | |
129 | unsigned long mappable_end, | |
130 | unsigned long end) | |
673a394b EA |
131 | { |
132 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 133 | |
bee4a186 | 134 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
673a394b | 135 | |
bee4a186 CW |
136 | dev_priv->mm.gtt_start = start; |
137 | dev_priv->mm.gtt_mappable_end = mappable_end; | |
138 | dev_priv->mm.gtt_end = end; | |
73aa808f | 139 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 140 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
bee4a186 CW |
141 | |
142 | /* Take over this portion of the GTT */ | |
143 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); | |
79e53945 | 144 | } |
673a394b | 145 | |
79e53945 JB |
146 | int |
147 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 148 | struct drm_file *file) |
79e53945 JB |
149 | { |
150 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
151 | |
152 | if (args->gtt_start >= args->gtt_end || | |
153 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
154 | return -EINVAL; | |
79e53945 JB |
155 | |
156 | mutex_lock(&dev->struct_mutex); | |
2021746e | 157 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
158 | mutex_unlock(&dev->struct_mutex); |
159 | ||
2021746e | 160 | return 0; |
673a394b EA |
161 | } |
162 | ||
5a125c3c EA |
163 | int |
164 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 165 | struct drm_file *file) |
5a125c3c | 166 | { |
73aa808f | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 168 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
169 | struct drm_i915_gem_object *obj; |
170 | size_t pinned; | |
5a125c3c EA |
171 | |
172 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
173 | return -ENODEV; | |
174 | ||
6299f992 | 175 | pinned = 0; |
73aa808f | 176 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
177 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
178 | pinned += obj->gtt_space->size; | |
73aa808f | 179 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 180 | |
6299f992 | 181 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 182 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 183 | |
5a125c3c EA |
184 | return 0; |
185 | } | |
186 | ||
ff72145b DA |
187 | static int |
188 | i915_gem_create(struct drm_file *file, | |
189 | struct drm_device *dev, | |
190 | uint64_t size, | |
191 | uint32_t *handle_p) | |
673a394b | 192 | { |
05394f39 | 193 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
194 | int ret; |
195 | u32 handle; | |
673a394b | 196 | |
ff72145b | 197 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
198 | if (size == 0) |
199 | return -EINVAL; | |
673a394b EA |
200 | |
201 | /* Allocate the new object */ | |
ff72145b | 202 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
203 | if (obj == NULL) |
204 | return -ENOMEM; | |
205 | ||
05394f39 | 206 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 207 | if (ret) { |
05394f39 CW |
208 | drm_gem_object_release(&obj->base); |
209 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 210 | kfree(obj); |
673a394b | 211 | return ret; |
1dfd9754 | 212 | } |
673a394b | 213 | |
202f2fef | 214 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 215 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
216 | trace_i915_gem_object_create(obj); |
217 | ||
ff72145b | 218 | *handle_p = handle; |
673a394b EA |
219 | return 0; |
220 | } | |
221 | ||
ff72145b DA |
222 | int |
223 | i915_gem_dumb_create(struct drm_file *file, | |
224 | struct drm_device *dev, | |
225 | struct drm_mode_create_dumb *args) | |
226 | { | |
227 | /* have to work out size/pitch and return them */ | |
ed0291fd | 228 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
229 | args->size = args->pitch * args->height; |
230 | return i915_gem_create(file, dev, | |
231 | args->size, &args->handle); | |
232 | } | |
233 | ||
234 | int i915_gem_dumb_destroy(struct drm_file *file, | |
235 | struct drm_device *dev, | |
236 | uint32_t handle) | |
237 | { | |
238 | return drm_gem_handle_delete(file, handle); | |
239 | } | |
240 | ||
241 | /** | |
242 | * Creates a new mm object and returns a handle to it. | |
243 | */ | |
244 | int | |
245 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
246 | struct drm_file *file) | |
247 | { | |
248 | struct drm_i915_gem_create *args = data; | |
249 | return i915_gem_create(file, dev, | |
250 | args->size, &args->handle); | |
251 | } | |
252 | ||
05394f39 | 253 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 254 | { |
05394f39 | 255 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
256 | |
257 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 258 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
259 | } |
260 | ||
99a03df5 | 261 | static inline void |
40123c1f EA |
262 | slow_shmem_copy(struct page *dst_page, |
263 | int dst_offset, | |
264 | struct page *src_page, | |
265 | int src_offset, | |
266 | int length) | |
267 | { | |
268 | char *dst_vaddr, *src_vaddr; | |
269 | ||
99a03df5 CW |
270 | dst_vaddr = kmap(dst_page); |
271 | src_vaddr = kmap(src_page); | |
40123c1f EA |
272 | |
273 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
274 | ||
99a03df5 CW |
275 | kunmap(src_page); |
276 | kunmap(dst_page); | |
40123c1f EA |
277 | } |
278 | ||
99a03df5 | 279 | static inline void |
280b713b EA |
280 | slow_shmem_bit17_copy(struct page *gpu_page, |
281 | int gpu_offset, | |
282 | struct page *cpu_page, | |
283 | int cpu_offset, | |
284 | int length, | |
285 | int is_read) | |
286 | { | |
287 | char *gpu_vaddr, *cpu_vaddr; | |
288 | ||
289 | /* Use the unswizzled path if this page isn't affected. */ | |
290 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
291 | if (is_read) | |
292 | return slow_shmem_copy(cpu_page, cpu_offset, | |
293 | gpu_page, gpu_offset, length); | |
294 | else | |
295 | return slow_shmem_copy(gpu_page, gpu_offset, | |
296 | cpu_page, cpu_offset, length); | |
297 | } | |
298 | ||
99a03df5 CW |
299 | gpu_vaddr = kmap(gpu_page); |
300 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
301 | |
302 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
303 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
304 | */ | |
305 | while (length > 0) { | |
306 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
307 | int this_length = min(cacheline_end - gpu_offset, length); | |
308 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
309 | ||
310 | if (is_read) { | |
311 | memcpy(cpu_vaddr + cpu_offset, | |
312 | gpu_vaddr + swizzled_gpu_offset, | |
313 | this_length); | |
314 | } else { | |
315 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
316 | cpu_vaddr + cpu_offset, | |
317 | this_length); | |
318 | } | |
319 | cpu_offset += this_length; | |
320 | gpu_offset += this_length; | |
321 | length -= this_length; | |
322 | } | |
323 | ||
99a03df5 CW |
324 | kunmap(cpu_page); |
325 | kunmap(gpu_page); | |
280b713b EA |
326 | } |
327 | ||
eb01459f EA |
328 | /** |
329 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
330 | * from the backing pages of the object to the user's address space. On a | |
331 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
332 | */ | |
333 | static int | |
05394f39 CW |
334 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
335 | struct drm_i915_gem_object *obj, | |
eb01459f | 336 | struct drm_i915_gem_pread *args, |
05394f39 | 337 | struct drm_file *file) |
eb01459f | 338 | { |
05394f39 | 339 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 340 | ssize_t remain; |
e5281ccd | 341 | loff_t offset; |
eb01459f EA |
342 | char __user *user_data; |
343 | int page_offset, page_length; | |
eb01459f EA |
344 | |
345 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
346 | remain = args->size; | |
347 | ||
eb01459f EA |
348 | offset = args->offset; |
349 | ||
350 | while (remain > 0) { | |
e5281ccd CW |
351 | struct page *page; |
352 | char *vaddr; | |
353 | int ret; | |
354 | ||
eb01459f EA |
355 | /* Operation in this page |
356 | * | |
eb01459f EA |
357 | * page_offset = offset within page |
358 | * page_length = bytes to copy for this page | |
359 | */ | |
c8cbbb8b | 360 | page_offset = offset_in_page(offset); |
eb01459f EA |
361 | page_length = remain; |
362 | if ((page_offset + remain) > PAGE_SIZE) | |
363 | page_length = PAGE_SIZE - page_offset; | |
364 | ||
5949eac4 | 365 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
366 | if (IS_ERR(page)) |
367 | return PTR_ERR(page); | |
368 | ||
369 | vaddr = kmap_atomic(page); | |
370 | ret = __copy_to_user_inatomic(user_data, | |
371 | vaddr + page_offset, | |
372 | page_length); | |
373 | kunmap_atomic(vaddr); | |
374 | ||
375 | mark_page_accessed(page); | |
376 | page_cache_release(page); | |
377 | if (ret) | |
4f27b75d | 378 | return -EFAULT; |
eb01459f EA |
379 | |
380 | remain -= page_length; | |
381 | user_data += page_length; | |
382 | offset += page_length; | |
383 | } | |
384 | ||
4f27b75d | 385 | return 0; |
eb01459f EA |
386 | } |
387 | ||
388 | /** | |
389 | * This is the fallback shmem pread path, which allocates temporary storage | |
390 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
391 | * can copy out of the object's backing pages while holding the struct mutex | |
392 | * and not take page faults. | |
393 | */ | |
394 | static int | |
05394f39 CW |
395 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
396 | struct drm_i915_gem_object *obj, | |
eb01459f | 397 | struct drm_i915_gem_pread *args, |
05394f39 | 398 | struct drm_file *file) |
eb01459f | 399 | { |
05394f39 | 400 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f EA |
401 | struct mm_struct *mm = current->mm; |
402 | struct page **user_pages; | |
403 | ssize_t remain; | |
404 | loff_t offset, pinned_pages, i; | |
405 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
406 | int shmem_page_offset; |
407 | int data_page_index, data_page_offset; | |
eb01459f EA |
408 | int page_length; |
409 | int ret; | |
410 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 411 | int do_bit17_swizzling; |
eb01459f EA |
412 | |
413 | remain = args->size; | |
414 | ||
415 | /* Pin the user pages containing the data. We can't fault while | |
416 | * holding the struct mutex, yet we want to hold it while | |
417 | * dereferencing the user data. | |
418 | */ | |
419 | first_data_page = data_ptr / PAGE_SIZE; | |
420 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
421 | num_pages = last_data_page - first_data_page + 1; | |
422 | ||
4f27b75d | 423 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
424 | if (user_pages == NULL) |
425 | return -ENOMEM; | |
426 | ||
4f27b75d | 427 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
428 | down_read(&mm->mmap_sem); |
429 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 430 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 431 | up_read(&mm->mmap_sem); |
4f27b75d | 432 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
433 | if (pinned_pages < num_pages) { |
434 | ret = -EFAULT; | |
4f27b75d | 435 | goto out; |
eb01459f EA |
436 | } |
437 | ||
4f27b75d CW |
438 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
439 | args->offset, | |
440 | args->size); | |
07f73f69 | 441 | if (ret) |
4f27b75d | 442 | goto out; |
eb01459f | 443 | |
4f27b75d | 444 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 445 | |
eb01459f EA |
446 | offset = args->offset; |
447 | ||
448 | while (remain > 0) { | |
e5281ccd CW |
449 | struct page *page; |
450 | ||
eb01459f EA |
451 | /* Operation in this page |
452 | * | |
eb01459f EA |
453 | * shmem_page_offset = offset within page in shmem file |
454 | * data_page_index = page number in get_user_pages return | |
455 | * data_page_offset = offset with data_page_index page. | |
456 | * page_length = bytes to copy for this page | |
457 | */ | |
c8cbbb8b | 458 | shmem_page_offset = offset_in_page(offset); |
eb01459f | 459 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 460 | data_page_offset = offset_in_page(data_ptr); |
eb01459f EA |
461 | |
462 | page_length = remain; | |
463 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
464 | page_length = PAGE_SIZE - shmem_page_offset; | |
465 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
466 | page_length = PAGE_SIZE - data_page_offset; | |
467 | ||
5949eac4 | 468 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
b65552f0 JJ |
469 | if (IS_ERR(page)) { |
470 | ret = PTR_ERR(page); | |
471 | goto out; | |
472 | } | |
e5281ccd | 473 | |
280b713b | 474 | if (do_bit17_swizzling) { |
e5281ccd | 475 | slow_shmem_bit17_copy(page, |
280b713b | 476 | shmem_page_offset, |
99a03df5 CW |
477 | user_pages[data_page_index], |
478 | data_page_offset, | |
479 | page_length, | |
480 | 1); | |
481 | } else { | |
482 | slow_shmem_copy(user_pages[data_page_index], | |
483 | data_page_offset, | |
e5281ccd | 484 | page, |
99a03df5 CW |
485 | shmem_page_offset, |
486 | page_length); | |
280b713b | 487 | } |
eb01459f | 488 | |
e5281ccd CW |
489 | mark_page_accessed(page); |
490 | page_cache_release(page); | |
491 | ||
eb01459f EA |
492 | remain -= page_length; |
493 | data_ptr += page_length; | |
494 | offset += page_length; | |
495 | } | |
496 | ||
4f27b75d | 497 | out: |
eb01459f EA |
498 | for (i = 0; i < pinned_pages; i++) { |
499 | SetPageDirty(user_pages[i]); | |
e5281ccd | 500 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
501 | page_cache_release(user_pages[i]); |
502 | } | |
8e7d2b2c | 503 | drm_free_large(user_pages); |
eb01459f EA |
504 | |
505 | return ret; | |
506 | } | |
507 | ||
673a394b EA |
508 | /** |
509 | * Reads data from the object referenced by handle. | |
510 | * | |
511 | * On error, the contents of *data are undefined. | |
512 | */ | |
513 | int | |
514 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 515 | struct drm_file *file) |
673a394b EA |
516 | { |
517 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 518 | struct drm_i915_gem_object *obj; |
35b62a89 | 519 | int ret = 0; |
673a394b | 520 | |
51311d0a CW |
521 | if (args->size == 0) |
522 | return 0; | |
523 | ||
524 | if (!access_ok(VERIFY_WRITE, | |
525 | (char __user *)(uintptr_t)args->data_ptr, | |
526 | args->size)) | |
527 | return -EFAULT; | |
528 | ||
529 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
530 | args->size); | |
531 | if (ret) | |
532 | return -EFAULT; | |
533 | ||
4f27b75d | 534 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 535 | if (ret) |
4f27b75d | 536 | return ret; |
673a394b | 537 | |
05394f39 | 538 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 539 | if (&obj->base == NULL) { |
1d7cfea1 CW |
540 | ret = -ENOENT; |
541 | goto unlock; | |
4f27b75d | 542 | } |
673a394b | 543 | |
7dcd2499 | 544 | /* Bounds check source. */ |
05394f39 CW |
545 | if (args->offset > obj->base.size || |
546 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 547 | ret = -EINVAL; |
35b62a89 | 548 | goto out; |
ce9d419d CW |
549 | } |
550 | ||
db53a302 CW |
551 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
552 | ||
4f27b75d CW |
553 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
554 | args->offset, | |
555 | args->size); | |
556 | if (ret) | |
e5281ccd | 557 | goto out; |
4f27b75d CW |
558 | |
559 | ret = -EFAULT; | |
560 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 561 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 562 | if (ret == -EFAULT) |
05394f39 | 563 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 564 | |
35b62a89 | 565 | out: |
05394f39 | 566 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 567 | unlock: |
4f27b75d | 568 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 569 | return ret; |
673a394b EA |
570 | } |
571 | ||
0839ccb8 KP |
572 | /* This is the fast write path which cannot handle |
573 | * page faults in the source data | |
9b7530cc | 574 | */ |
0839ccb8 KP |
575 | |
576 | static inline int | |
577 | fast_user_write(struct io_mapping *mapping, | |
578 | loff_t page_base, int page_offset, | |
579 | char __user *user_data, | |
580 | int length) | |
9b7530cc | 581 | { |
9b7530cc | 582 | char *vaddr_atomic; |
0839ccb8 | 583 | unsigned long unwritten; |
9b7530cc | 584 | |
3e4d3af5 | 585 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
586 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
587 | user_data, length); | |
3e4d3af5 | 588 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 589 | return unwritten; |
0839ccb8 KP |
590 | } |
591 | ||
592 | /* Here's the write path which can sleep for | |
593 | * page faults | |
594 | */ | |
595 | ||
ab34c226 | 596 | static inline void |
3de09aa3 EA |
597 | slow_kernel_write(struct io_mapping *mapping, |
598 | loff_t gtt_base, int gtt_offset, | |
599 | struct page *user_page, int user_offset, | |
600 | int length) | |
0839ccb8 | 601 | { |
ab34c226 CW |
602 | char __iomem *dst_vaddr; |
603 | char *src_vaddr; | |
0839ccb8 | 604 | |
ab34c226 CW |
605 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
606 | src_vaddr = kmap(user_page); | |
607 | ||
608 | memcpy_toio(dst_vaddr + gtt_offset, | |
609 | src_vaddr + user_offset, | |
610 | length); | |
611 | ||
612 | kunmap(user_page); | |
613 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
614 | } |
615 | ||
3de09aa3 EA |
616 | /** |
617 | * This is the fast pwrite path, where we copy the data directly from the | |
618 | * user into the GTT, uncached. | |
619 | */ | |
673a394b | 620 | static int |
05394f39 CW |
621 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
622 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 623 | struct drm_i915_gem_pwrite *args, |
05394f39 | 624 | struct drm_file *file) |
673a394b | 625 | { |
0839ccb8 | 626 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 627 | ssize_t remain; |
0839ccb8 | 628 | loff_t offset, page_base; |
673a394b | 629 | char __user *user_data; |
0839ccb8 | 630 | int page_offset, page_length; |
673a394b EA |
631 | |
632 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
633 | remain = args->size; | |
673a394b | 634 | |
05394f39 | 635 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
636 | |
637 | while (remain > 0) { | |
638 | /* Operation in this page | |
639 | * | |
0839ccb8 KP |
640 | * page_base = page offset within aperture |
641 | * page_offset = offset within page | |
642 | * page_length = bytes to copy for this page | |
673a394b | 643 | */ |
c8cbbb8b CW |
644 | page_base = offset & PAGE_MASK; |
645 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
646 | page_length = remain; |
647 | if ((page_offset + remain) > PAGE_SIZE) | |
648 | page_length = PAGE_SIZE - page_offset; | |
649 | ||
0839ccb8 | 650 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
651 | * source page isn't available. Return the error and we'll |
652 | * retry in the slow path. | |
0839ccb8 | 653 | */ |
fbd5a26d CW |
654 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
655 | page_offset, user_data, page_length)) | |
fbd5a26d | 656 | return -EFAULT; |
673a394b | 657 | |
0839ccb8 KP |
658 | remain -= page_length; |
659 | user_data += page_length; | |
660 | offset += page_length; | |
673a394b | 661 | } |
673a394b | 662 | |
fbd5a26d | 663 | return 0; |
673a394b EA |
664 | } |
665 | ||
3de09aa3 EA |
666 | /** |
667 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
668 | * the memory and maps it using kmap_atomic for copying. | |
669 | * | |
670 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
671 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
672 | */ | |
3043c60c | 673 | static int |
05394f39 CW |
674 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
675 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 676 | struct drm_i915_gem_pwrite *args, |
05394f39 | 677 | struct drm_file *file) |
673a394b | 678 | { |
3de09aa3 EA |
679 | drm_i915_private_t *dev_priv = dev->dev_private; |
680 | ssize_t remain; | |
681 | loff_t gtt_page_base, offset; | |
682 | loff_t first_data_page, last_data_page, num_pages; | |
683 | loff_t pinned_pages, i; | |
684 | struct page **user_pages; | |
685 | struct mm_struct *mm = current->mm; | |
686 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 687 | int ret; |
3de09aa3 EA |
688 | uint64_t data_ptr = args->data_ptr; |
689 | ||
690 | remain = args->size; | |
691 | ||
692 | /* Pin the user pages containing the data. We can't fault while | |
693 | * holding the struct mutex, and all of the pwrite implementations | |
694 | * want to hold it while dereferencing the user data. | |
695 | */ | |
696 | first_data_page = data_ptr / PAGE_SIZE; | |
697 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
698 | num_pages = last_data_page - first_data_page + 1; | |
699 | ||
fbd5a26d | 700 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
701 | if (user_pages == NULL) |
702 | return -ENOMEM; | |
703 | ||
fbd5a26d | 704 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
705 | down_read(&mm->mmap_sem); |
706 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
707 | num_pages, 0, 0, user_pages, NULL); | |
708 | up_read(&mm->mmap_sem); | |
fbd5a26d | 709 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
710 | if (pinned_pages < num_pages) { |
711 | ret = -EFAULT; | |
712 | goto out_unpin_pages; | |
713 | } | |
673a394b | 714 | |
d9e86c0e CW |
715 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
716 | if (ret) | |
717 | goto out_unpin_pages; | |
718 | ||
719 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 720 | if (ret) |
fbd5a26d | 721 | goto out_unpin_pages; |
3de09aa3 | 722 | |
05394f39 | 723 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
724 | |
725 | while (remain > 0) { | |
726 | /* Operation in this page | |
727 | * | |
728 | * gtt_page_base = page offset within aperture | |
729 | * gtt_page_offset = offset within page in aperture | |
730 | * data_page_index = page number in get_user_pages return | |
731 | * data_page_offset = offset with data_page_index page. | |
732 | * page_length = bytes to copy for this page | |
733 | */ | |
734 | gtt_page_base = offset & PAGE_MASK; | |
c8cbbb8b | 735 | gtt_page_offset = offset_in_page(offset); |
3de09aa3 | 736 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 737 | data_page_offset = offset_in_page(data_ptr); |
3de09aa3 EA |
738 | |
739 | page_length = remain; | |
740 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
741 | page_length = PAGE_SIZE - gtt_page_offset; | |
742 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
743 | page_length = PAGE_SIZE - data_page_offset; | |
744 | ||
ab34c226 CW |
745 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
746 | gtt_page_base, gtt_page_offset, | |
747 | user_pages[data_page_index], | |
748 | data_page_offset, | |
749 | page_length); | |
3de09aa3 EA |
750 | |
751 | remain -= page_length; | |
752 | offset += page_length; | |
753 | data_ptr += page_length; | |
754 | } | |
755 | ||
3de09aa3 EA |
756 | out_unpin_pages: |
757 | for (i = 0; i < pinned_pages; i++) | |
758 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 759 | drm_free_large(user_pages); |
3de09aa3 EA |
760 | |
761 | return ret; | |
762 | } | |
763 | ||
40123c1f EA |
764 | /** |
765 | * This is the fast shmem pwrite path, which attempts to directly | |
766 | * copy_from_user into the kmapped pages backing the object. | |
767 | */ | |
3043c60c | 768 | static int |
05394f39 CW |
769 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
770 | struct drm_i915_gem_object *obj, | |
40123c1f | 771 | struct drm_i915_gem_pwrite *args, |
05394f39 | 772 | struct drm_file *file) |
673a394b | 773 | { |
05394f39 | 774 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 775 | ssize_t remain; |
e5281ccd | 776 | loff_t offset; |
40123c1f EA |
777 | char __user *user_data; |
778 | int page_offset, page_length; | |
40123c1f EA |
779 | |
780 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
781 | remain = args->size; | |
673a394b | 782 | |
40123c1f | 783 | offset = args->offset; |
05394f39 | 784 | obj->dirty = 1; |
40123c1f EA |
785 | |
786 | while (remain > 0) { | |
e5281ccd CW |
787 | struct page *page; |
788 | char *vaddr; | |
789 | int ret; | |
790 | ||
40123c1f EA |
791 | /* Operation in this page |
792 | * | |
40123c1f EA |
793 | * page_offset = offset within page |
794 | * page_length = bytes to copy for this page | |
795 | */ | |
c8cbbb8b | 796 | page_offset = offset_in_page(offset); |
40123c1f EA |
797 | page_length = remain; |
798 | if ((page_offset + remain) > PAGE_SIZE) | |
799 | page_length = PAGE_SIZE - page_offset; | |
800 | ||
5949eac4 | 801 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
802 | if (IS_ERR(page)) |
803 | return PTR_ERR(page); | |
804 | ||
130c2561 | 805 | vaddr = kmap_atomic(page); |
e5281ccd CW |
806 | ret = __copy_from_user_inatomic(vaddr + page_offset, |
807 | user_data, | |
808 | page_length); | |
130c2561 | 809 | kunmap_atomic(vaddr); |
e5281ccd CW |
810 | |
811 | set_page_dirty(page); | |
812 | mark_page_accessed(page); | |
813 | page_cache_release(page); | |
814 | ||
815 | /* If we get a fault while copying data, then (presumably) our | |
816 | * source page isn't available. Return the error and we'll | |
817 | * retry in the slow path. | |
818 | */ | |
819 | if (ret) | |
fbd5a26d | 820 | return -EFAULT; |
40123c1f EA |
821 | |
822 | remain -= page_length; | |
823 | user_data += page_length; | |
824 | offset += page_length; | |
825 | } | |
826 | ||
fbd5a26d | 827 | return 0; |
40123c1f EA |
828 | } |
829 | ||
830 | /** | |
831 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
832 | * the memory and maps it using kmap_atomic for copying. | |
833 | * | |
834 | * This avoids taking mmap_sem for faulting on the user's address while the | |
835 | * struct_mutex is held. | |
836 | */ | |
837 | static int | |
05394f39 CW |
838 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
839 | struct drm_i915_gem_object *obj, | |
40123c1f | 840 | struct drm_i915_gem_pwrite *args, |
05394f39 | 841 | struct drm_file *file) |
40123c1f | 842 | { |
05394f39 | 843 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f EA |
844 | struct mm_struct *mm = current->mm; |
845 | struct page **user_pages; | |
846 | ssize_t remain; | |
847 | loff_t offset, pinned_pages, i; | |
848 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 849 | int shmem_page_offset; |
40123c1f EA |
850 | int data_page_index, data_page_offset; |
851 | int page_length; | |
852 | int ret; | |
853 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 854 | int do_bit17_swizzling; |
40123c1f EA |
855 | |
856 | remain = args->size; | |
857 | ||
858 | /* Pin the user pages containing the data. We can't fault while | |
859 | * holding the struct mutex, and all of the pwrite implementations | |
860 | * want to hold it while dereferencing the user data. | |
861 | */ | |
862 | first_data_page = data_ptr / PAGE_SIZE; | |
863 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
864 | num_pages = last_data_page - first_data_page + 1; | |
865 | ||
4f27b75d | 866 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
867 | if (user_pages == NULL) |
868 | return -ENOMEM; | |
869 | ||
fbd5a26d | 870 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
871 | down_read(&mm->mmap_sem); |
872 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
873 | num_pages, 0, 0, user_pages, NULL); | |
874 | up_read(&mm->mmap_sem); | |
fbd5a26d | 875 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
876 | if (pinned_pages < num_pages) { |
877 | ret = -EFAULT; | |
fbd5a26d | 878 | goto out; |
673a394b EA |
879 | } |
880 | ||
fbd5a26d | 881 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 882 | if (ret) |
fbd5a26d | 883 | goto out; |
40123c1f | 884 | |
fbd5a26d | 885 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 886 | |
673a394b | 887 | offset = args->offset; |
05394f39 | 888 | obj->dirty = 1; |
673a394b | 889 | |
40123c1f | 890 | while (remain > 0) { |
e5281ccd CW |
891 | struct page *page; |
892 | ||
40123c1f EA |
893 | /* Operation in this page |
894 | * | |
40123c1f EA |
895 | * shmem_page_offset = offset within page in shmem file |
896 | * data_page_index = page number in get_user_pages return | |
897 | * data_page_offset = offset with data_page_index page. | |
898 | * page_length = bytes to copy for this page | |
899 | */ | |
c8cbbb8b | 900 | shmem_page_offset = offset_in_page(offset); |
40123c1f | 901 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 902 | data_page_offset = offset_in_page(data_ptr); |
40123c1f EA |
903 | |
904 | page_length = remain; | |
905 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
906 | page_length = PAGE_SIZE - shmem_page_offset; | |
907 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
908 | page_length = PAGE_SIZE - data_page_offset; | |
909 | ||
5949eac4 | 910 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
911 | if (IS_ERR(page)) { |
912 | ret = PTR_ERR(page); | |
913 | goto out; | |
914 | } | |
915 | ||
280b713b | 916 | if (do_bit17_swizzling) { |
e5281ccd | 917 | slow_shmem_bit17_copy(page, |
280b713b EA |
918 | shmem_page_offset, |
919 | user_pages[data_page_index], | |
920 | data_page_offset, | |
99a03df5 CW |
921 | page_length, |
922 | 0); | |
923 | } else { | |
e5281ccd | 924 | slow_shmem_copy(page, |
99a03df5 CW |
925 | shmem_page_offset, |
926 | user_pages[data_page_index], | |
927 | data_page_offset, | |
928 | page_length); | |
280b713b | 929 | } |
40123c1f | 930 | |
e5281ccd CW |
931 | set_page_dirty(page); |
932 | mark_page_accessed(page); | |
933 | page_cache_release(page); | |
934 | ||
40123c1f EA |
935 | remain -= page_length; |
936 | data_ptr += page_length; | |
937 | offset += page_length; | |
673a394b EA |
938 | } |
939 | ||
fbd5a26d | 940 | out: |
40123c1f EA |
941 | for (i = 0; i < pinned_pages; i++) |
942 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 943 | drm_free_large(user_pages); |
673a394b | 944 | |
40123c1f | 945 | return ret; |
673a394b EA |
946 | } |
947 | ||
948 | /** | |
949 | * Writes data to the object referenced by handle. | |
950 | * | |
951 | * On error, the contents of the buffer that were to be modified are undefined. | |
952 | */ | |
953 | int | |
954 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 955 | struct drm_file *file) |
673a394b EA |
956 | { |
957 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 958 | struct drm_i915_gem_object *obj; |
51311d0a CW |
959 | int ret; |
960 | ||
961 | if (args->size == 0) | |
962 | return 0; | |
963 | ||
964 | if (!access_ok(VERIFY_READ, | |
965 | (char __user *)(uintptr_t)args->data_ptr, | |
966 | args->size)) | |
967 | return -EFAULT; | |
968 | ||
969 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
970 | args->size); | |
971 | if (ret) | |
972 | return -EFAULT; | |
673a394b | 973 | |
fbd5a26d | 974 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 975 | if (ret) |
fbd5a26d | 976 | return ret; |
1d7cfea1 | 977 | |
05394f39 | 978 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 979 | if (&obj->base == NULL) { |
1d7cfea1 CW |
980 | ret = -ENOENT; |
981 | goto unlock; | |
fbd5a26d | 982 | } |
673a394b | 983 | |
7dcd2499 | 984 | /* Bounds check destination. */ |
05394f39 CW |
985 | if (args->offset > obj->base.size || |
986 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 987 | ret = -EINVAL; |
35b62a89 | 988 | goto out; |
ce9d419d CW |
989 | } |
990 | ||
db53a302 CW |
991 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
992 | ||
673a394b EA |
993 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
994 | * it would end up going through the fenced access, and we'll get | |
995 | * different detiling behavior between reading and writing. | |
996 | * pread/pwrite currently are reading and writing from the CPU | |
997 | * perspective, requiring manual detiling by the client. | |
998 | */ | |
05394f39 | 999 | if (obj->phys_obj) |
fbd5a26d | 1000 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
d9e86c0e | 1001 | else if (obj->gtt_space && |
05394f39 | 1002 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 1003 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1004 | if (ret) |
1005 | goto out; | |
1006 | ||
d9e86c0e CW |
1007 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1008 | if (ret) | |
1009 | goto out_unpin; | |
1010 | ||
1011 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
1012 | if (ret) |
1013 | goto out_unpin; | |
1014 | ||
1015 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1016 | if (ret == -EFAULT) | |
1017 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1018 | ||
1019 | out_unpin: | |
1020 | i915_gem_object_unpin(obj); | |
40123c1f | 1021 | } else { |
fbd5a26d CW |
1022 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1023 | if (ret) | |
e5281ccd | 1024 | goto out; |
673a394b | 1025 | |
fbd5a26d CW |
1026 | ret = -EFAULT; |
1027 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1028 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1029 | if (ret == -EFAULT) | |
1030 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1031 | } |
673a394b | 1032 | |
35b62a89 | 1033 | out: |
05394f39 | 1034 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1035 | unlock: |
fbd5a26d | 1036 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1037 | return ret; |
1038 | } | |
1039 | ||
1040 | /** | |
2ef7eeaa EA |
1041 | * Called when user space prepares to use an object with the CPU, either |
1042 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1043 | */ |
1044 | int | |
1045 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1046 | struct drm_file *file) |
673a394b EA |
1047 | { |
1048 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1049 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1050 | uint32_t read_domains = args->read_domains; |
1051 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1052 | int ret; |
1053 | ||
1054 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1055 | return -ENODEV; | |
1056 | ||
2ef7eeaa | 1057 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1058 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1059 | return -EINVAL; |
1060 | ||
21d509e3 | 1061 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1062 | return -EINVAL; |
1063 | ||
1064 | /* Having something in the write domain implies it's in the read | |
1065 | * domain, and only that read domain. Enforce that in the request. | |
1066 | */ | |
1067 | if (write_domain != 0 && read_domains != write_domain) | |
1068 | return -EINVAL; | |
1069 | ||
76c1dec1 | 1070 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1071 | if (ret) |
76c1dec1 | 1072 | return ret; |
1d7cfea1 | 1073 | |
05394f39 | 1074 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1075 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1076 | ret = -ENOENT; |
1077 | goto unlock; | |
76c1dec1 | 1078 | } |
673a394b | 1079 | |
2ef7eeaa EA |
1080 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1081 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1082 | |
1083 | /* Silently promote "you're not bound, there was nothing to do" | |
1084 | * to success, since the client was just asking us to | |
1085 | * make sure everything was done. | |
1086 | */ | |
1087 | if (ret == -EINVAL) | |
1088 | ret = 0; | |
2ef7eeaa | 1089 | } else { |
e47c68e9 | 1090 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1091 | } |
1092 | ||
05394f39 | 1093 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1094 | unlock: |
673a394b EA |
1095 | mutex_unlock(&dev->struct_mutex); |
1096 | return ret; | |
1097 | } | |
1098 | ||
1099 | /** | |
1100 | * Called when user space has done writes to this buffer | |
1101 | */ | |
1102 | int | |
1103 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1104 | struct drm_file *file) |
673a394b EA |
1105 | { |
1106 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1107 | struct drm_i915_gem_object *obj; |
673a394b EA |
1108 | int ret = 0; |
1109 | ||
1110 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1111 | return -ENODEV; | |
1112 | ||
76c1dec1 | 1113 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1114 | if (ret) |
76c1dec1 | 1115 | return ret; |
1d7cfea1 | 1116 | |
05394f39 | 1117 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1118 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1119 | ret = -ENOENT; |
1120 | goto unlock; | |
673a394b EA |
1121 | } |
1122 | ||
673a394b | 1123 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1124 | if (obj->pin_count) |
e47c68e9 EA |
1125 | i915_gem_object_flush_cpu_write_domain(obj); |
1126 | ||
05394f39 | 1127 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1128 | unlock: |
673a394b EA |
1129 | mutex_unlock(&dev->struct_mutex); |
1130 | return ret; | |
1131 | } | |
1132 | ||
1133 | /** | |
1134 | * Maps the contents of an object, returning the address it is mapped | |
1135 | * into. | |
1136 | * | |
1137 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1138 | * imply a ref on the object itself. | |
1139 | */ | |
1140 | int | |
1141 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1142 | struct drm_file *file) |
673a394b | 1143 | { |
da761a6e | 1144 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1145 | struct drm_i915_gem_mmap *args = data; |
1146 | struct drm_gem_object *obj; | |
673a394b EA |
1147 | unsigned long addr; |
1148 | ||
1149 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1150 | return -ENODEV; | |
1151 | ||
05394f39 | 1152 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1153 | if (obj == NULL) |
bf79cb91 | 1154 | return -ENOENT; |
673a394b | 1155 | |
da761a6e CW |
1156 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1157 | drm_gem_object_unreference_unlocked(obj); | |
1158 | return -E2BIG; | |
1159 | } | |
1160 | ||
673a394b EA |
1161 | down_write(¤t->mm->mmap_sem); |
1162 | addr = do_mmap(obj->filp, 0, args->size, | |
1163 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1164 | args->offset); | |
1165 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1166 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1167 | if (IS_ERR((void *)addr)) |
1168 | return addr; | |
1169 | ||
1170 | args->addr_ptr = (uint64_t) addr; | |
1171 | ||
1172 | return 0; | |
1173 | } | |
1174 | ||
de151cf6 JB |
1175 | /** |
1176 | * i915_gem_fault - fault a page into the GTT | |
1177 | * vma: VMA in question | |
1178 | * vmf: fault info | |
1179 | * | |
1180 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1181 | * from userspace. The fault handler takes care of binding the object to | |
1182 | * the GTT (if needed), allocating and programming a fence register (again, | |
1183 | * only if needed based on whether the old reg is still valid or the object | |
1184 | * is tiled) and inserting a new PTE into the faulting process. | |
1185 | * | |
1186 | * Note that the faulting process may involve evicting existing objects | |
1187 | * from the GTT and/or fence registers to make room. So performance may | |
1188 | * suffer if the GTT working set is large or there are few fence registers | |
1189 | * left. | |
1190 | */ | |
1191 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1192 | { | |
05394f39 CW |
1193 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1194 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1195 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1196 | pgoff_t page_offset; |
1197 | unsigned long pfn; | |
1198 | int ret = 0; | |
0f973f27 | 1199 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1200 | |
1201 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1202 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1203 | PAGE_SHIFT; | |
1204 | ||
d9bc7e9f CW |
1205 | ret = i915_mutex_lock_interruptible(dev); |
1206 | if (ret) | |
1207 | goto out; | |
a00b10c3 | 1208 | |
db53a302 CW |
1209 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1210 | ||
d9bc7e9f | 1211 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1212 | if (!obj->map_and_fenceable) { |
1213 | ret = i915_gem_object_unbind(obj); | |
1214 | if (ret) | |
1215 | goto unlock; | |
a00b10c3 | 1216 | } |
05394f39 | 1217 | if (!obj->gtt_space) { |
75e9e915 | 1218 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1219 | if (ret) |
1220 | goto unlock; | |
de151cf6 | 1221 | |
e92d03bf EA |
1222 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1223 | if (ret) | |
1224 | goto unlock; | |
1225 | } | |
4a684a41 | 1226 | |
d9e86c0e CW |
1227 | if (obj->tiling_mode == I915_TILING_NONE) |
1228 | ret = i915_gem_object_put_fence(obj); | |
1229 | else | |
ce453d81 | 1230 | ret = i915_gem_object_get_fence(obj, NULL); |
d9e86c0e CW |
1231 | if (ret) |
1232 | goto unlock; | |
de151cf6 | 1233 | |
05394f39 CW |
1234 | if (i915_gem_object_is_inactive(obj)) |
1235 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1236 | |
6299f992 CW |
1237 | obj->fault_mappable = true; |
1238 | ||
05394f39 | 1239 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1240 | page_offset; |
1241 | ||
1242 | /* Finally, remap it using the new GTT offset */ | |
1243 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1244 | unlock: |
de151cf6 | 1245 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1246 | out: |
de151cf6 | 1247 | switch (ret) { |
d9bc7e9f | 1248 | case -EIO: |
045e769a | 1249 | case -EAGAIN: |
d9bc7e9f CW |
1250 | /* Give the error handler a chance to run and move the |
1251 | * objects off the GPU active list. Next time we service the | |
1252 | * fault, we should be able to transition the page into the | |
1253 | * GTT without touching the GPU (and so avoid further | |
1254 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1255 | * with coherency, just lost writes. | |
1256 | */ | |
045e769a | 1257 | set_need_resched(); |
c715089f CW |
1258 | case 0: |
1259 | case -ERESTARTSYS: | |
bed636ab | 1260 | case -EINTR: |
c715089f | 1261 | return VM_FAULT_NOPAGE; |
de151cf6 | 1262 | case -ENOMEM: |
de151cf6 | 1263 | return VM_FAULT_OOM; |
de151cf6 | 1264 | default: |
c715089f | 1265 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1266 | } |
1267 | } | |
1268 | ||
901782b2 CW |
1269 | /** |
1270 | * i915_gem_release_mmap - remove physical page mappings | |
1271 | * @obj: obj in question | |
1272 | * | |
af901ca1 | 1273 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1274 | * relinquish ownership of the pages back to the system. |
1275 | * | |
1276 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1277 | * object through the GTT and then lose the fence register due to | |
1278 | * resource pressure. Similarly if the object has been moved out of the | |
1279 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1280 | * mapping will then trigger a page fault on the next user access, allowing | |
1281 | * fixup by i915_gem_fault(). | |
1282 | */ | |
d05ca301 | 1283 | void |
05394f39 | 1284 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1285 | { |
6299f992 CW |
1286 | if (!obj->fault_mappable) |
1287 | return; | |
901782b2 | 1288 | |
f6e47884 CW |
1289 | if (obj->base.dev->dev_mapping) |
1290 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1291 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1292 | obj->base.size, 1); | |
fb7d516a | 1293 | |
6299f992 | 1294 | obj->fault_mappable = false; |
901782b2 CW |
1295 | } |
1296 | ||
92b88aeb | 1297 | static uint32_t |
e28f8711 | 1298 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1299 | { |
e28f8711 | 1300 | uint32_t gtt_size; |
92b88aeb CW |
1301 | |
1302 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1303 | tiling_mode == I915_TILING_NONE) |
1304 | return size; | |
92b88aeb CW |
1305 | |
1306 | /* Previous chips need a power-of-two fence region when tiling */ | |
1307 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1308 | gtt_size = 1024*1024; |
92b88aeb | 1309 | else |
e28f8711 | 1310 | gtt_size = 512*1024; |
92b88aeb | 1311 | |
e28f8711 CW |
1312 | while (gtt_size < size) |
1313 | gtt_size <<= 1; | |
92b88aeb | 1314 | |
e28f8711 | 1315 | return gtt_size; |
92b88aeb CW |
1316 | } |
1317 | ||
de151cf6 JB |
1318 | /** |
1319 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1320 | * @obj: object to check | |
1321 | * | |
1322 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1323 | * potential fence register mapping. |
de151cf6 JB |
1324 | */ |
1325 | static uint32_t | |
e28f8711 CW |
1326 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1327 | uint32_t size, | |
1328 | int tiling_mode) | |
de151cf6 | 1329 | { |
de151cf6 JB |
1330 | /* |
1331 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1332 | * if a fence register is needed for the object. | |
1333 | */ | |
a00b10c3 | 1334 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1335 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1336 | return 4096; |
1337 | ||
a00b10c3 CW |
1338 | /* |
1339 | * Previous chips need to be aligned to the size of the smallest | |
1340 | * fence register that can contain the object. | |
1341 | */ | |
e28f8711 | 1342 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1343 | } |
1344 | ||
5e783301 DV |
1345 | /** |
1346 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1347 | * unfenced object | |
e28f8711 CW |
1348 | * @dev: the device |
1349 | * @size: size of the object | |
1350 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1351 | * |
1352 | * Return the required GTT alignment for an object, only taking into account | |
1353 | * unfenced tiled surface requirements. | |
1354 | */ | |
467cffba | 1355 | uint32_t |
e28f8711 CW |
1356 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1357 | uint32_t size, | |
1358 | int tiling_mode) | |
5e783301 | 1359 | { |
5e783301 DV |
1360 | /* |
1361 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1362 | */ | |
1363 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1364 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1365 | return 4096; |
1366 | ||
e28f8711 CW |
1367 | /* Previous hardware however needs to be aligned to a power-of-two |
1368 | * tile height. The simplest method for determining this is to reuse | |
1369 | * the power-of-tile object size. | |
5e783301 | 1370 | */ |
e28f8711 | 1371 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1372 | } |
1373 | ||
de151cf6 | 1374 | int |
ff72145b DA |
1375 | i915_gem_mmap_gtt(struct drm_file *file, |
1376 | struct drm_device *dev, | |
1377 | uint32_t handle, | |
1378 | uint64_t *offset) | |
de151cf6 | 1379 | { |
da761a6e | 1380 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1381 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1382 | int ret; |
1383 | ||
1384 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1385 | return -ENODEV; | |
1386 | ||
76c1dec1 | 1387 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1388 | if (ret) |
76c1dec1 | 1389 | return ret; |
de151cf6 | 1390 | |
ff72145b | 1391 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1392 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1393 | ret = -ENOENT; |
1394 | goto unlock; | |
1395 | } | |
de151cf6 | 1396 | |
05394f39 | 1397 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e CW |
1398 | ret = -E2BIG; |
1399 | goto unlock; | |
1400 | } | |
1401 | ||
05394f39 | 1402 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1403 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1404 | ret = -EINVAL; |
1405 | goto out; | |
ab18282d CW |
1406 | } |
1407 | ||
05394f39 | 1408 | if (!obj->base.map_list.map) { |
b464e9a2 | 1409 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1410 | if (ret) |
1411 | goto out; | |
de151cf6 JB |
1412 | } |
1413 | ||
ff72145b | 1414 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1415 | |
1d7cfea1 | 1416 | out: |
05394f39 | 1417 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1418 | unlock: |
de151cf6 | 1419 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1420 | return ret; |
de151cf6 JB |
1421 | } |
1422 | ||
ff72145b DA |
1423 | /** |
1424 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1425 | * @dev: DRM device | |
1426 | * @data: GTT mapping ioctl data | |
1427 | * @file: GEM object info | |
1428 | * | |
1429 | * Simply returns the fake offset to userspace so it can mmap it. | |
1430 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1431 | * up so we can get faults in the handler above. | |
1432 | * | |
1433 | * The fault handler will take care of binding the object into the GTT | |
1434 | * (since it may have been evicted to make room for something), allocating | |
1435 | * a fence register, and mapping the appropriate aperture address into | |
1436 | * userspace. | |
1437 | */ | |
1438 | int | |
1439 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1440 | struct drm_file *file) | |
1441 | { | |
1442 | struct drm_i915_gem_mmap_gtt *args = data; | |
1443 | ||
1444 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1445 | return -ENODEV; | |
1446 | ||
1447 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1448 | } | |
1449 | ||
1450 | ||
e5281ccd | 1451 | static int |
05394f39 | 1452 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1453 | gfp_t gfpmask) |
1454 | { | |
e5281ccd CW |
1455 | int page_count, i; |
1456 | struct address_space *mapping; | |
1457 | struct inode *inode; | |
1458 | struct page *page; | |
1459 | ||
1460 | /* Get the list of pages out of our struct file. They'll be pinned | |
1461 | * at this point until we release them. | |
1462 | */ | |
05394f39 CW |
1463 | page_count = obj->base.size / PAGE_SIZE; |
1464 | BUG_ON(obj->pages != NULL); | |
1465 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1466 | if (obj->pages == NULL) | |
e5281ccd CW |
1467 | return -ENOMEM; |
1468 | ||
05394f39 | 1469 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1470 | mapping = inode->i_mapping; |
5949eac4 HD |
1471 | gfpmask |= mapping_gfp_mask(mapping); |
1472 | ||
e5281ccd | 1473 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1474 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1475 | if (IS_ERR(page)) |
1476 | goto err_pages; | |
1477 | ||
05394f39 | 1478 | obj->pages[i] = page; |
e5281ccd CW |
1479 | } |
1480 | ||
6dacfd2f | 1481 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1482 | i915_gem_object_do_bit_17_swizzle(obj); |
1483 | ||
1484 | return 0; | |
1485 | ||
1486 | err_pages: | |
1487 | while (i--) | |
05394f39 | 1488 | page_cache_release(obj->pages[i]); |
e5281ccd | 1489 | |
05394f39 CW |
1490 | drm_free_large(obj->pages); |
1491 | obj->pages = NULL; | |
e5281ccd CW |
1492 | return PTR_ERR(page); |
1493 | } | |
1494 | ||
5cdf5881 | 1495 | static void |
05394f39 | 1496 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1497 | { |
05394f39 | 1498 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1499 | int i; |
1500 | ||
05394f39 | 1501 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1502 | |
6dacfd2f | 1503 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1504 | i915_gem_object_save_bit_17_swizzle(obj); |
1505 | ||
05394f39 CW |
1506 | if (obj->madv == I915_MADV_DONTNEED) |
1507 | obj->dirty = 0; | |
3ef94daa CW |
1508 | |
1509 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1510 | if (obj->dirty) |
1511 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1512 | |
05394f39 CW |
1513 | if (obj->madv == I915_MADV_WILLNEED) |
1514 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1515 | |
05394f39 | 1516 | page_cache_release(obj->pages[i]); |
3ef94daa | 1517 | } |
05394f39 | 1518 | obj->dirty = 0; |
673a394b | 1519 | |
05394f39 CW |
1520 | drm_free_large(obj->pages); |
1521 | obj->pages = NULL; | |
673a394b EA |
1522 | } |
1523 | ||
54cf91dc | 1524 | void |
05394f39 | 1525 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1526 | struct intel_ring_buffer *ring, |
1527 | u32 seqno) | |
673a394b | 1528 | { |
05394f39 | 1529 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1530 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1531 | |
852835f3 | 1532 | BUG_ON(ring == NULL); |
05394f39 | 1533 | obj->ring = ring; |
673a394b EA |
1534 | |
1535 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1536 | if (!obj->active) { |
1537 | drm_gem_object_reference(&obj->base); | |
1538 | obj->active = 1; | |
673a394b | 1539 | } |
e35a41de | 1540 | |
673a394b | 1541 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1542 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1543 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1544 | |
05394f39 | 1545 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1546 | if (obj->fenced_gpu_access) { |
1547 | struct drm_i915_fence_reg *reg; | |
1548 | ||
1549 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1550 | ||
1551 | obj->last_fenced_seqno = seqno; | |
1552 | obj->last_fenced_ring = ring; | |
1553 | ||
1554 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1555 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1556 | } | |
1557 | } | |
1558 | ||
1559 | static void | |
1560 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1561 | { | |
1562 | list_del_init(&obj->ring_list); | |
1563 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1564 | } |
1565 | ||
ce44b0ea | 1566 | static void |
05394f39 | 1567 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1568 | { |
05394f39 | 1569 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1570 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1571 | |
05394f39 CW |
1572 | BUG_ON(!obj->active); |
1573 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1574 | |
1575 | i915_gem_object_move_off_active(obj); | |
1576 | } | |
1577 | ||
1578 | static void | |
1579 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1580 | { | |
1581 | struct drm_device *dev = obj->base.dev; | |
1582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1583 | ||
1584 | if (obj->pin_count != 0) | |
1585 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1586 | else | |
1587 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1588 | ||
1589 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1590 | BUG_ON(!obj->active); | |
1591 | obj->ring = NULL; | |
1592 | ||
1593 | i915_gem_object_move_off_active(obj); | |
1594 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1595 | |
1596 | obj->active = 0; | |
87ca9c8a | 1597 | obj->pending_gpu_write = false; |
caea7476 CW |
1598 | drm_gem_object_unreference(&obj->base); |
1599 | ||
1600 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1601 | } |
673a394b | 1602 | |
963b4836 CW |
1603 | /* Immediately discard the backing storage */ |
1604 | static void | |
05394f39 | 1605 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1606 | { |
bb6baf76 | 1607 | struct inode *inode; |
963b4836 | 1608 | |
ae9fed6b CW |
1609 | /* Our goal here is to return as much of the memory as |
1610 | * is possible back to the system as we are called from OOM. | |
1611 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1612 | * backing pages, *now*. |
ae9fed6b | 1613 | */ |
05394f39 | 1614 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1615 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1616 | |
05394f39 | 1617 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1618 | } |
1619 | ||
1620 | static inline int | |
05394f39 | 1621 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1622 | { |
05394f39 | 1623 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1624 | } |
1625 | ||
63560396 | 1626 | static void |
db53a302 CW |
1627 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1628 | uint32_t flush_domains) | |
63560396 | 1629 | { |
05394f39 | 1630 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1631 | |
05394f39 | 1632 | list_for_each_entry_safe(obj, next, |
64193406 | 1633 | &ring->gpu_write_list, |
63560396 | 1634 | gpu_write_list) { |
05394f39 CW |
1635 | if (obj->base.write_domain & flush_domains) { |
1636 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1637 | |
05394f39 CW |
1638 | obj->base.write_domain = 0; |
1639 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1640 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1641 | i915_gem_next_request_seqno(ring)); |
63560396 | 1642 | |
63560396 | 1643 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1644 | obj->base.read_domains, |
63560396 DV |
1645 | old_write_domain); |
1646 | } | |
1647 | } | |
1648 | } | |
8187a2b7 | 1649 | |
3cce469c | 1650 | int |
db53a302 | 1651 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1652 | struct drm_file *file, |
db53a302 | 1653 | struct drm_i915_gem_request *request) |
673a394b | 1654 | { |
db53a302 | 1655 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b EA |
1656 | uint32_t seqno; |
1657 | int was_empty; | |
3cce469c CW |
1658 | int ret; |
1659 | ||
1660 | BUG_ON(request == NULL); | |
673a394b | 1661 | |
3cce469c CW |
1662 | ret = ring->add_request(ring, &seqno); |
1663 | if (ret) | |
1664 | return ret; | |
673a394b | 1665 | |
db53a302 | 1666 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1667 | |
1668 | request->seqno = seqno; | |
852835f3 | 1669 | request->ring = ring; |
673a394b | 1670 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1671 | was_empty = list_empty(&ring->request_list); |
1672 | list_add_tail(&request->list, &ring->request_list); | |
1673 | ||
db53a302 CW |
1674 | if (file) { |
1675 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1676 | ||
1c25595f | 1677 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1678 | request->file_priv = file_priv; |
b962442e | 1679 | list_add_tail(&request->client_list, |
f787a5f5 | 1680 | &file_priv->mm.request_list); |
1c25595f | 1681 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1682 | } |
673a394b | 1683 | |
db53a302 CW |
1684 | ring->outstanding_lazy_request = false; |
1685 | ||
f65d9421 | 1686 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1687 | if (i915_enable_hangcheck) { |
1688 | mod_timer(&dev_priv->hangcheck_timer, | |
1689 | jiffies + | |
1690 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1691 | } | |
f65d9421 | 1692 | if (was_empty) |
b3b079db CW |
1693 | queue_delayed_work(dev_priv->wq, |
1694 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1695 | } |
3cce469c | 1696 | return 0; |
673a394b EA |
1697 | } |
1698 | ||
f787a5f5 CW |
1699 | static inline void |
1700 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1701 | { |
1c25595f | 1702 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1703 | |
1c25595f CW |
1704 | if (!file_priv) |
1705 | return; | |
1c5d22f7 | 1706 | |
1c25595f | 1707 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1708 | if (request->file_priv) { |
1709 | list_del(&request->client_list); | |
1710 | request->file_priv = NULL; | |
1711 | } | |
1c25595f | 1712 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1713 | } |
673a394b | 1714 | |
dfaae392 CW |
1715 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1716 | struct intel_ring_buffer *ring) | |
9375e446 | 1717 | { |
dfaae392 CW |
1718 | while (!list_empty(&ring->request_list)) { |
1719 | struct drm_i915_gem_request *request; | |
673a394b | 1720 | |
dfaae392 CW |
1721 | request = list_first_entry(&ring->request_list, |
1722 | struct drm_i915_gem_request, | |
1723 | list); | |
de151cf6 | 1724 | |
dfaae392 | 1725 | list_del(&request->list); |
f787a5f5 | 1726 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1727 | kfree(request); |
1728 | } | |
673a394b | 1729 | |
dfaae392 | 1730 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1731 | struct drm_i915_gem_object *obj; |
9375e446 | 1732 | |
05394f39 CW |
1733 | obj = list_first_entry(&ring->active_list, |
1734 | struct drm_i915_gem_object, | |
1735 | ring_list); | |
9375e446 | 1736 | |
05394f39 CW |
1737 | obj->base.write_domain = 0; |
1738 | list_del_init(&obj->gpu_write_list); | |
1739 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1740 | } |
1741 | } | |
1742 | ||
312817a3 CW |
1743 | static void i915_gem_reset_fences(struct drm_device *dev) |
1744 | { | |
1745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1746 | int i; | |
1747 | ||
1748 | for (i = 0; i < 16; i++) { | |
1749 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
7d2cb39c CW |
1750 | struct drm_i915_gem_object *obj = reg->obj; |
1751 | ||
1752 | if (!obj) | |
1753 | continue; | |
1754 | ||
1755 | if (obj->tiling_mode) | |
1756 | i915_gem_release_mmap(obj); | |
1757 | ||
d9e86c0e CW |
1758 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1759 | reg->obj->fenced_gpu_access = false; | |
1760 | reg->obj->last_fenced_seqno = 0; | |
1761 | reg->obj->last_fenced_ring = NULL; | |
1762 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1763 | } |
1764 | } | |
1765 | ||
069efc1d | 1766 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1767 | { |
77f01230 | 1768 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1769 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1770 | int i; |
673a394b | 1771 | |
1ec14ad3 CW |
1772 | for (i = 0; i < I915_NUM_RINGS; i++) |
1773 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1774 | |
1775 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1776 | * to be lost on reset along with the data, so simply move the | |
1777 | * lost bo to the inactive list. | |
1778 | */ | |
1779 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1780 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1781 | struct drm_i915_gem_object, |
1782 | mm_list); | |
dfaae392 | 1783 | |
05394f39 CW |
1784 | obj->base.write_domain = 0; |
1785 | list_del_init(&obj->gpu_write_list); | |
1786 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1787 | } |
1788 | ||
1789 | /* Move everything out of the GPU domains to ensure we do any | |
1790 | * necessary invalidation upon reuse. | |
1791 | */ | |
05394f39 | 1792 | list_for_each_entry(obj, |
77f01230 | 1793 | &dev_priv->mm.inactive_list, |
69dc4987 | 1794 | mm_list) |
77f01230 | 1795 | { |
05394f39 | 1796 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1797 | } |
069efc1d CW |
1798 | |
1799 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1800 | i915_gem_reset_fences(dev); |
673a394b EA |
1801 | } |
1802 | ||
1803 | /** | |
1804 | * This function clears the request list as sequence numbers are passed. | |
1805 | */ | |
b09a1fec | 1806 | static void |
db53a302 | 1807 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1808 | { |
673a394b | 1809 | uint32_t seqno; |
1ec14ad3 | 1810 | int i; |
673a394b | 1811 | |
db53a302 | 1812 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1813 | return; |
1814 | ||
db53a302 | 1815 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1816 | |
78501eac | 1817 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1818 | |
076e2c0e | 1819 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1820 | if (seqno >= ring->sync_seqno[i]) |
1821 | ring->sync_seqno[i] = 0; | |
1822 | ||
852835f3 | 1823 | while (!list_empty(&ring->request_list)) { |
673a394b | 1824 | struct drm_i915_gem_request *request; |
673a394b | 1825 | |
852835f3 | 1826 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1827 | struct drm_i915_gem_request, |
1828 | list); | |
673a394b | 1829 | |
dfaae392 | 1830 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1831 | break; |
1832 | ||
db53a302 | 1833 | trace_i915_gem_request_retire(ring, request->seqno); |
b84d5f0c CW |
1834 | |
1835 | list_del(&request->list); | |
f787a5f5 | 1836 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1837 | kfree(request); |
1838 | } | |
673a394b | 1839 | |
b84d5f0c CW |
1840 | /* Move any buffers on the active list that are no longer referenced |
1841 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1842 | */ | |
1843 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1844 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1845 | |
0206e353 | 1846 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1847 | struct drm_i915_gem_object, |
1848 | ring_list); | |
673a394b | 1849 | |
05394f39 | 1850 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1851 | break; |
b84d5f0c | 1852 | |
05394f39 | 1853 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1854 | i915_gem_object_move_to_flushing(obj); |
1855 | else | |
1856 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1857 | } |
9d34e5db | 1858 | |
db53a302 CW |
1859 | if (unlikely(ring->trace_irq_seqno && |
1860 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1861 | ring->irq_put(ring); |
db53a302 | 1862 | ring->trace_irq_seqno = 0; |
9d34e5db | 1863 | } |
23bc5982 | 1864 | |
db53a302 | 1865 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1866 | } |
1867 | ||
b09a1fec CW |
1868 | void |
1869 | i915_gem_retire_requests(struct drm_device *dev) | |
1870 | { | |
1871 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1872 | int i; |
b09a1fec | 1873 | |
be72615b | 1874 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1875 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1876 | |
1877 | /* We must be careful that during unbind() we do not | |
1878 | * accidentally infinitely recurse into retire requests. | |
1879 | * Currently: | |
1880 | * retire -> free -> unbind -> wait -> retire_ring | |
1881 | */ | |
05394f39 | 1882 | list_for_each_entry_safe(obj, next, |
be72615b | 1883 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1884 | mm_list) |
05394f39 | 1885 | i915_gem_free_object_tail(obj); |
be72615b CW |
1886 | } |
1887 | ||
1ec14ad3 | 1888 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1889 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1890 | } |
1891 | ||
75ef9da2 | 1892 | static void |
673a394b EA |
1893 | i915_gem_retire_work_handler(struct work_struct *work) |
1894 | { | |
1895 | drm_i915_private_t *dev_priv; | |
1896 | struct drm_device *dev; | |
0a58705b CW |
1897 | bool idle; |
1898 | int i; | |
673a394b EA |
1899 | |
1900 | dev_priv = container_of(work, drm_i915_private_t, | |
1901 | mm.retire_work.work); | |
1902 | dev = dev_priv->dev; | |
1903 | ||
891b48cf CW |
1904 | /* Come back later if the device is busy... */ |
1905 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1906 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1907 | return; | |
1908 | } | |
1909 | ||
b09a1fec | 1910 | i915_gem_retire_requests(dev); |
d1b851fc | 1911 | |
0a58705b CW |
1912 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1913 | * objects indefinitely. | |
1914 | */ | |
1915 | idle = true; | |
1916 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1917 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1918 | ||
1919 | if (!list_empty(&ring->gpu_write_list)) { | |
1920 | struct drm_i915_gem_request *request; | |
1921 | int ret; | |
1922 | ||
db53a302 CW |
1923 | ret = i915_gem_flush_ring(ring, |
1924 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1925 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1926 | if (ret || request == NULL || | |
db53a302 | 1927 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1928 | kfree(request); |
1929 | } | |
1930 | ||
1931 | idle &= list_empty(&ring->request_list); | |
1932 | } | |
1933 | ||
1934 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1935 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1936 | |
673a394b EA |
1937 | mutex_unlock(&dev->struct_mutex); |
1938 | } | |
1939 | ||
db53a302 CW |
1940 | /** |
1941 | * Waits for a sequence number to be signaled, and cleans up the | |
1942 | * request and object lists appropriately for that event. | |
1943 | */ | |
5a5a0c64 | 1944 | int |
db53a302 | 1945 | i915_wait_request(struct intel_ring_buffer *ring, |
ce453d81 | 1946 | uint32_t seqno) |
673a394b | 1947 | { |
db53a302 | 1948 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1949 | u32 ier; |
673a394b EA |
1950 | int ret = 0; |
1951 | ||
1952 | BUG_ON(seqno == 0); | |
1953 | ||
d9bc7e9f CW |
1954 | if (atomic_read(&dev_priv->mm.wedged)) { |
1955 | struct completion *x = &dev_priv->error_completion; | |
1956 | bool recovery_complete; | |
1957 | unsigned long flags; | |
1958 | ||
1959 | /* Give the error handler a chance to run. */ | |
1960 | spin_lock_irqsave(&x->wait.lock, flags); | |
1961 | recovery_complete = x->done > 0; | |
1962 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1963 | ||
1964 | return recovery_complete ? -EIO : -EAGAIN; | |
1965 | } | |
30dbf0c0 | 1966 | |
5d97eb69 | 1967 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1968 | struct drm_i915_gem_request *request; |
1969 | ||
1970 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1971 | if (request == NULL) | |
e35a41de | 1972 | return -ENOMEM; |
3cce469c | 1973 | |
db53a302 | 1974 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1975 | if (ret) { |
1976 | kfree(request); | |
1977 | return ret; | |
1978 | } | |
1979 | ||
1980 | seqno = request->seqno; | |
e35a41de | 1981 | } |
ffed1d09 | 1982 | |
78501eac | 1983 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 1984 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
1985 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1986 | else | |
1987 | ier = I915_READ(IER); | |
802c7eb6 JB |
1988 | if (!ier) { |
1989 | DRM_ERROR("something (likely vbetool) disabled " | |
1990 | "interrupts, re-enabling\n"); | |
f01c22fd CW |
1991 | ring->dev->driver->irq_preinstall(ring->dev); |
1992 | ring->dev->driver->irq_postinstall(ring->dev); | |
802c7eb6 JB |
1993 | } |
1994 | ||
db53a302 | 1995 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 1996 | |
b2223497 | 1997 | ring->waiting_seqno = seqno; |
b13c2b96 | 1998 | if (ring->irq_get(ring)) { |
ce453d81 | 1999 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
2000 | ret = wait_event_interruptible(ring->irq_queue, |
2001 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2002 | || atomic_read(&dev_priv->mm.wedged)); | |
2003 | else | |
2004 | wait_event(ring->irq_queue, | |
2005 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2006 | || atomic_read(&dev_priv->mm.wedged)); | |
2007 | ||
2008 | ring->irq_put(ring); | |
b5ba177d CW |
2009 | } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring), |
2010 | seqno) || | |
2011 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
2012 | ret = -EBUSY; | |
b2223497 | 2013 | ring->waiting_seqno = 0; |
1c5d22f7 | 2014 | |
db53a302 | 2015 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 2016 | } |
ba1234d1 | 2017 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2018 | ret = -EAGAIN; |
673a394b EA |
2019 | |
2020 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2021 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2022 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2023 | dev_priv->next_seqno); |
673a394b EA |
2024 | |
2025 | /* Directly dispatch request retiring. While we have the work queue | |
2026 | * to handle this, the waiter on a request often wants an associated | |
2027 | * buffer to have made it to the inactive list, and we would need | |
2028 | * a separate wait queue to handle that. | |
2029 | */ | |
2030 | if (ret == 0) | |
db53a302 | 2031 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
2032 | |
2033 | return ret; | |
2034 | } | |
2035 | ||
673a394b EA |
2036 | /** |
2037 | * Ensures that all rendering to the object has completed and the object is | |
2038 | * safe to unbind from the GTT or access from the CPU. | |
2039 | */ | |
54cf91dc | 2040 | int |
ce453d81 | 2041 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 2042 | { |
673a394b EA |
2043 | int ret; |
2044 | ||
e47c68e9 EA |
2045 | /* This function only exists to support waiting for existing rendering, |
2046 | * not for emitting required flushes. | |
673a394b | 2047 | */ |
05394f39 | 2048 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2049 | |
2050 | /* If there is rendering queued on the buffer being evicted, wait for | |
2051 | * it. | |
2052 | */ | |
05394f39 | 2053 | if (obj->active) { |
ce453d81 | 2054 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno); |
2cf34d7b | 2055 | if (ret) |
673a394b EA |
2056 | return ret; |
2057 | } | |
2058 | ||
2059 | return 0; | |
2060 | } | |
2061 | ||
b5ffc9bc CW |
2062 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2063 | { | |
2064 | u32 old_write_domain, old_read_domains; | |
2065 | ||
b5ffc9bc CW |
2066 | /* Act a barrier for all accesses through the GTT */ |
2067 | mb(); | |
2068 | ||
2069 | /* Force a pagefault for domain tracking on next user access */ | |
2070 | i915_gem_release_mmap(obj); | |
2071 | ||
b97c3d9c KP |
2072 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2073 | return; | |
2074 | ||
b5ffc9bc CW |
2075 | old_read_domains = obj->base.read_domains; |
2076 | old_write_domain = obj->base.write_domain; | |
2077 | ||
2078 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2079 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2080 | ||
2081 | trace_i915_gem_object_change_domain(obj, | |
2082 | old_read_domains, | |
2083 | old_write_domain); | |
2084 | } | |
2085 | ||
673a394b EA |
2086 | /** |
2087 | * Unbinds an object from the GTT aperture. | |
2088 | */ | |
0f973f27 | 2089 | int |
05394f39 | 2090 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2091 | { |
673a394b EA |
2092 | int ret = 0; |
2093 | ||
05394f39 | 2094 | if (obj->gtt_space == NULL) |
673a394b EA |
2095 | return 0; |
2096 | ||
05394f39 | 2097 | if (obj->pin_count != 0) { |
673a394b EA |
2098 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2099 | return -EINVAL; | |
2100 | } | |
2101 | ||
a8198eea CW |
2102 | ret = i915_gem_object_finish_gpu(obj); |
2103 | if (ret == -ERESTARTSYS) | |
2104 | return ret; | |
2105 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2106 | * should be safe and we need to cleanup or else we might | |
2107 | * cause memory corruption through use-after-free. | |
2108 | */ | |
2109 | ||
b5ffc9bc | 2110 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2111 | |
673a394b EA |
2112 | /* Move the object to the CPU domain to ensure that |
2113 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2114 | * are flushed when we go to remap it. |
673a394b | 2115 | */ |
a8198eea CW |
2116 | if (ret == 0) |
2117 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2118 | if (ret == -ERESTARTSYS) |
673a394b | 2119 | return ret; |
812ed492 | 2120 | if (ret) { |
a8198eea CW |
2121 | /* In the event of a disaster, abandon all caches and |
2122 | * hope for the best. | |
2123 | */ | |
812ed492 | 2124 | i915_gem_clflush_object(obj); |
05394f39 | 2125 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2126 | } |
673a394b | 2127 | |
96b47b65 | 2128 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2129 | ret = i915_gem_object_put_fence(obj); |
2130 | if (ret == -ERESTARTSYS) | |
2131 | return ret; | |
96b47b65 | 2132 | |
db53a302 CW |
2133 | trace_i915_gem_object_unbind(obj); |
2134 | ||
7c2e6fdf | 2135 | i915_gem_gtt_unbind_object(obj); |
e5281ccd | 2136 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2137 | |
6299f992 | 2138 | list_del_init(&obj->gtt_list); |
05394f39 | 2139 | list_del_init(&obj->mm_list); |
75e9e915 | 2140 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2141 | obj->map_and_fenceable = true; |
673a394b | 2142 | |
05394f39 CW |
2143 | drm_mm_put_block(obj->gtt_space); |
2144 | obj->gtt_space = NULL; | |
2145 | obj->gtt_offset = 0; | |
673a394b | 2146 | |
05394f39 | 2147 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2148 | i915_gem_object_truncate(obj); |
2149 | ||
8dc1775d | 2150 | return ret; |
673a394b EA |
2151 | } |
2152 | ||
88241785 | 2153 | int |
db53a302 | 2154 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2155 | uint32_t invalidate_domains, |
2156 | uint32_t flush_domains) | |
2157 | { | |
88241785 CW |
2158 | int ret; |
2159 | ||
36d527de CW |
2160 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2161 | return 0; | |
2162 | ||
db53a302 CW |
2163 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2164 | ||
88241785 CW |
2165 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2166 | if (ret) | |
2167 | return ret; | |
2168 | ||
36d527de CW |
2169 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2170 | i915_gem_process_flushing_list(ring, flush_domains); | |
2171 | ||
88241785 | 2172 | return 0; |
54cf91dc CW |
2173 | } |
2174 | ||
db53a302 | 2175 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2176 | { |
88241785 CW |
2177 | int ret; |
2178 | ||
395b70be | 2179 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2180 | return 0; |
2181 | ||
88241785 | 2182 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2183 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2184 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2185 | if (ret) |
2186 | return ret; | |
2187 | } | |
2188 | ||
ce453d81 | 2189 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2190 | } |
2191 | ||
b47eb4a2 | 2192 | int |
4df2faf4 DV |
2193 | i915_gpu_idle(struct drm_device *dev) |
2194 | { | |
2195 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2196 | int ret, i; |
4df2faf4 | 2197 | |
4df2faf4 | 2198 | /* Flush everything onto the inactive list. */ |
1ec14ad3 | 2199 | for (i = 0; i < I915_NUM_RINGS; i++) { |
db53a302 | 2200 | ret = i915_ring_idle(&dev_priv->ring[i]); |
1ec14ad3 CW |
2201 | if (ret) |
2202 | return ret; | |
2203 | } | |
4df2faf4 | 2204 | |
8a1a49f9 | 2205 | return 0; |
4df2faf4 DV |
2206 | } |
2207 | ||
c6642782 DV |
2208 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2209 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2210 | { |
05394f39 | 2211 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2212 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2213 | u32 size = obj->gtt_space->size; |
2214 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2215 | uint64_t val; |
2216 | ||
05394f39 | 2217 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2218 | 0xfffff000) << 32; |
05394f39 CW |
2219 | val |= obj->gtt_offset & 0xfffff000; |
2220 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2221 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2222 | ||
05394f39 | 2223 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2224 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2225 | val |= I965_FENCE_REG_VALID; | |
2226 | ||
c6642782 DV |
2227 | if (pipelined) { |
2228 | int ret = intel_ring_begin(pipelined, 6); | |
2229 | if (ret) | |
2230 | return ret; | |
2231 | ||
2232 | intel_ring_emit(pipelined, MI_NOOP); | |
2233 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2234 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2235 | intel_ring_emit(pipelined, (u32)val); | |
2236 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2237 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2238 | intel_ring_advance(pipelined); | |
2239 | } else | |
2240 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2241 | ||
2242 | return 0; | |
4e901fdc EA |
2243 | } |
2244 | ||
c6642782 DV |
2245 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2246 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2247 | { |
05394f39 | 2248 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2249 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2250 | u32 size = obj->gtt_space->size; |
2251 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2252 | uint64_t val; |
2253 | ||
05394f39 | 2254 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2255 | 0xfffff000) << 32; |
05394f39 CW |
2256 | val |= obj->gtt_offset & 0xfffff000; |
2257 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2258 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2259 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2260 | val |= I965_FENCE_REG_VALID; | |
2261 | ||
c6642782 DV |
2262 | if (pipelined) { |
2263 | int ret = intel_ring_begin(pipelined, 6); | |
2264 | if (ret) | |
2265 | return ret; | |
2266 | ||
2267 | intel_ring_emit(pipelined, MI_NOOP); | |
2268 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2269 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2270 | intel_ring_emit(pipelined, (u32)val); | |
2271 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2272 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2273 | intel_ring_advance(pipelined); | |
2274 | } else | |
2275 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2276 | ||
2277 | return 0; | |
de151cf6 JB |
2278 | } |
2279 | ||
c6642782 DV |
2280 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2281 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2282 | { |
05394f39 | 2283 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2284 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2285 | u32 size = obj->gtt_space->size; |
c6642782 | 2286 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2287 | int tile_width; |
de151cf6 | 2288 | |
c6642782 DV |
2289 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2290 | (size & -size) != size || | |
2291 | (obj->gtt_offset & (size - 1)), | |
2292 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2293 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2294 | return -EINVAL; | |
de151cf6 | 2295 | |
c6642782 | 2296 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2297 | tile_width = 128; |
de151cf6 | 2298 | else |
0f973f27 JB |
2299 | tile_width = 512; |
2300 | ||
2301 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2302 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2303 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2304 | |
05394f39 CW |
2305 | val = obj->gtt_offset; |
2306 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2307 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2308 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2309 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2310 | val |= I830_FENCE_REG_VALID; | |
2311 | ||
05394f39 | 2312 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2313 | if (fence_reg < 8) |
2314 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2315 | else |
a00b10c3 | 2316 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2317 | |
2318 | if (pipelined) { | |
2319 | int ret = intel_ring_begin(pipelined, 4); | |
2320 | if (ret) | |
2321 | return ret; | |
2322 | ||
2323 | intel_ring_emit(pipelined, MI_NOOP); | |
2324 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2325 | intel_ring_emit(pipelined, fence_reg); | |
2326 | intel_ring_emit(pipelined, val); | |
2327 | intel_ring_advance(pipelined); | |
2328 | } else | |
2329 | I915_WRITE(fence_reg, val); | |
2330 | ||
2331 | return 0; | |
de151cf6 JB |
2332 | } |
2333 | ||
c6642782 DV |
2334 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2335 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2336 | { |
05394f39 | 2337 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2338 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2339 | u32 size = obj->gtt_space->size; |
2340 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2341 | uint32_t val; |
2342 | uint32_t pitch_val; | |
2343 | ||
c6642782 DV |
2344 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2345 | (size & -size) != size || | |
2346 | (obj->gtt_offset & (size - 1)), | |
2347 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2348 | obj->gtt_offset, size)) | |
2349 | return -EINVAL; | |
de151cf6 | 2350 | |
05394f39 | 2351 | pitch_val = obj->stride / 128; |
e76a16de | 2352 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2353 | |
05394f39 CW |
2354 | val = obj->gtt_offset; |
2355 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2356 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2357 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2358 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2359 | val |= I830_FENCE_REG_VALID; | |
2360 | ||
c6642782 DV |
2361 | if (pipelined) { |
2362 | int ret = intel_ring_begin(pipelined, 4); | |
2363 | if (ret) | |
2364 | return ret; | |
2365 | ||
2366 | intel_ring_emit(pipelined, MI_NOOP); | |
2367 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2368 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2369 | intel_ring_emit(pipelined, val); | |
2370 | intel_ring_advance(pipelined); | |
2371 | } else | |
2372 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2373 | ||
2374 | return 0; | |
de151cf6 JB |
2375 | } |
2376 | ||
d9e86c0e CW |
2377 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2378 | { | |
2379 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2380 | } | |
2381 | ||
2382 | static int | |
2383 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
ce453d81 | 2384 | struct intel_ring_buffer *pipelined) |
d9e86c0e CW |
2385 | { |
2386 | int ret; | |
2387 | ||
2388 | if (obj->fenced_gpu_access) { | |
88241785 | 2389 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2390 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2391 | 0, obj->base.write_domain); |
2392 | if (ret) | |
2393 | return ret; | |
2394 | } | |
d9e86c0e CW |
2395 | |
2396 | obj->fenced_gpu_access = false; | |
2397 | } | |
2398 | ||
2399 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2400 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2401 | obj->last_fenced_seqno)) { | |
db53a302 | 2402 | ret = i915_wait_request(obj->last_fenced_ring, |
ce453d81 | 2403 | obj->last_fenced_seqno); |
d9e86c0e CW |
2404 | if (ret) |
2405 | return ret; | |
2406 | } | |
2407 | ||
2408 | obj->last_fenced_seqno = 0; | |
2409 | obj->last_fenced_ring = NULL; | |
2410 | } | |
2411 | ||
63256ec5 CW |
2412 | /* Ensure that all CPU reads are completed before installing a fence |
2413 | * and all writes before removing the fence. | |
2414 | */ | |
2415 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2416 | mb(); | |
2417 | ||
d9e86c0e CW |
2418 | return 0; |
2419 | } | |
2420 | ||
2421 | int | |
2422 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2423 | { | |
2424 | int ret; | |
2425 | ||
2426 | if (obj->tiling_mode) | |
2427 | i915_gem_release_mmap(obj); | |
2428 | ||
ce453d81 | 2429 | ret = i915_gem_object_flush_fence(obj, NULL); |
d9e86c0e CW |
2430 | if (ret) |
2431 | return ret; | |
2432 | ||
2433 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2434 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2435 | i915_gem_clear_fence_reg(obj->base.dev, | |
2436 | &dev_priv->fence_regs[obj->fence_reg]); | |
2437 | ||
2438 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2439 | } | |
2440 | ||
2441 | return 0; | |
2442 | } | |
2443 | ||
2444 | static struct drm_i915_fence_reg * | |
2445 | i915_find_fence_reg(struct drm_device *dev, | |
2446 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2447 | { |
ae3db24a | 2448 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2449 | struct drm_i915_fence_reg *reg, *first, *avail; |
2450 | int i; | |
ae3db24a DV |
2451 | |
2452 | /* First try to find a free reg */ | |
d9e86c0e | 2453 | avail = NULL; |
ae3db24a DV |
2454 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2455 | reg = &dev_priv->fence_regs[i]; | |
2456 | if (!reg->obj) | |
d9e86c0e | 2457 | return reg; |
ae3db24a | 2458 | |
05394f39 | 2459 | if (!reg->obj->pin_count) |
d9e86c0e | 2460 | avail = reg; |
ae3db24a DV |
2461 | } |
2462 | ||
d9e86c0e CW |
2463 | if (avail == NULL) |
2464 | return NULL; | |
ae3db24a DV |
2465 | |
2466 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2467 | avail = first = NULL; |
2468 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
2469 | if (reg->obj->pin_count) | |
ae3db24a DV |
2470 | continue; |
2471 | ||
d9e86c0e CW |
2472 | if (first == NULL) |
2473 | first = reg; | |
2474 | ||
2475 | if (!pipelined || | |
2476 | !reg->obj->last_fenced_ring || | |
2477 | reg->obj->last_fenced_ring == pipelined) { | |
2478 | avail = reg; | |
2479 | break; | |
2480 | } | |
ae3db24a DV |
2481 | } |
2482 | ||
d9e86c0e CW |
2483 | if (avail == NULL) |
2484 | avail = first; | |
ae3db24a | 2485 | |
a00b10c3 | 2486 | return avail; |
ae3db24a DV |
2487 | } |
2488 | ||
de151cf6 | 2489 | /** |
d9e86c0e | 2490 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2491 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2492 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2493 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2494 | * |
2495 | * When mapping objects through the GTT, userspace wants to be able to write | |
2496 | * to them without having to worry about swizzling if the object is tiled. | |
2497 | * | |
2498 | * This function walks the fence regs looking for a free one for @obj, | |
2499 | * stealing one if it can't find any. | |
2500 | * | |
2501 | * It then sets up the reg based on the object's properties: address, pitch | |
2502 | * and tiling format. | |
2503 | */ | |
8c4b8c3f | 2504 | int |
d9e86c0e | 2505 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 2506 | struct intel_ring_buffer *pipelined) |
de151cf6 | 2507 | { |
05394f39 | 2508 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2509 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2510 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2511 | int ret; |
de151cf6 | 2512 | |
6bda10d1 CW |
2513 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2514 | pipelined = NULL; | |
2515 | ||
d9e86c0e | 2516 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2517 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2518 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2519 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e | 2520 | |
29c5a587 CW |
2521 | if (obj->tiling_changed) { |
2522 | ret = i915_gem_object_flush_fence(obj, pipelined); | |
2523 | if (ret) | |
2524 | return ret; | |
2525 | ||
2526 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2527 | pipelined = NULL; | |
2528 | ||
2529 | if (pipelined) { | |
2530 | reg->setup_seqno = | |
2531 | i915_gem_next_request_seqno(pipelined); | |
2532 | obj->last_fenced_seqno = reg->setup_seqno; | |
2533 | obj->last_fenced_ring = pipelined; | |
2534 | } | |
2535 | ||
2536 | goto update; | |
2537 | } | |
d9e86c0e CW |
2538 | |
2539 | if (!pipelined) { | |
2540 | if (reg->setup_seqno) { | |
2541 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2542 | reg->setup_seqno)) { | |
db53a302 | 2543 | ret = i915_wait_request(obj->last_fenced_ring, |
ce453d81 | 2544 | reg->setup_seqno); |
d9e86c0e CW |
2545 | if (ret) |
2546 | return ret; | |
2547 | } | |
2548 | ||
2549 | reg->setup_seqno = 0; | |
2550 | } | |
2551 | } else if (obj->last_fenced_ring && | |
2552 | obj->last_fenced_ring != pipelined) { | |
ce453d81 | 2553 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e CW |
2554 | if (ret) |
2555 | return ret; | |
d9e86c0e CW |
2556 | } |
2557 | ||
a09ba7fa EA |
2558 | return 0; |
2559 | } | |
2560 | ||
d9e86c0e CW |
2561 | reg = i915_find_fence_reg(dev, pipelined); |
2562 | if (reg == NULL) | |
2563 | return -ENOSPC; | |
de151cf6 | 2564 | |
ce453d81 | 2565 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e | 2566 | if (ret) |
ae3db24a | 2567 | return ret; |
de151cf6 | 2568 | |
d9e86c0e CW |
2569 | if (reg->obj) { |
2570 | struct drm_i915_gem_object *old = reg->obj; | |
2571 | ||
2572 | drm_gem_object_reference(&old->base); | |
2573 | ||
2574 | if (old->tiling_mode) | |
2575 | i915_gem_release_mmap(old); | |
2576 | ||
ce453d81 | 2577 | ret = i915_gem_object_flush_fence(old, pipelined); |
d9e86c0e CW |
2578 | if (ret) { |
2579 | drm_gem_object_unreference(&old->base); | |
2580 | return ret; | |
2581 | } | |
2582 | ||
2583 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2584 | pipelined = NULL; | |
2585 | ||
2586 | old->fence_reg = I915_FENCE_REG_NONE; | |
2587 | old->last_fenced_ring = pipelined; | |
2588 | old->last_fenced_seqno = | |
db53a302 | 2589 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2590 | |
2591 | drm_gem_object_unreference(&old->base); | |
2592 | } else if (obj->last_fenced_seqno == 0) | |
2593 | pipelined = NULL; | |
a09ba7fa | 2594 | |
de151cf6 | 2595 | reg->obj = obj; |
d9e86c0e CW |
2596 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2597 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2598 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2599 | |
d9e86c0e | 2600 | reg->setup_seqno = |
db53a302 | 2601 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2602 | obj->last_fenced_seqno = reg->setup_seqno; |
2603 | ||
2604 | update: | |
2605 | obj->tiling_changed = false; | |
e259befd | 2606 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2607 | case 7: |
e259befd | 2608 | case 6: |
c6642782 | 2609 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2610 | break; |
2611 | case 5: | |
2612 | case 4: | |
c6642782 | 2613 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2614 | break; |
2615 | case 3: | |
c6642782 | 2616 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2617 | break; |
2618 | case 2: | |
c6642782 | 2619 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2620 | break; |
2621 | } | |
d9ddcb96 | 2622 | |
c6642782 | 2623 | return ret; |
de151cf6 JB |
2624 | } |
2625 | ||
2626 | /** | |
2627 | * i915_gem_clear_fence_reg - clear out fence register info | |
2628 | * @obj: object to clear | |
2629 | * | |
2630 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2631 | * data structures in dev_priv and obj. |
de151cf6 JB |
2632 | */ |
2633 | static void | |
d9e86c0e CW |
2634 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2635 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2636 | { |
79e53945 | 2637 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2638 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2639 | |
e259befd | 2640 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2641 | case 7: |
e259befd | 2642 | case 6: |
d9e86c0e | 2643 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2644 | break; |
2645 | case 5: | |
2646 | case 4: | |
d9e86c0e | 2647 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2648 | break; |
2649 | case 3: | |
d9e86c0e CW |
2650 | if (fence_reg >= 8) |
2651 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2652 | else |
e259befd | 2653 | case 2: |
d9e86c0e | 2654 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2655 | |
2656 | I915_WRITE(fence_reg, 0); | |
e259befd | 2657 | break; |
dc529a4f | 2658 | } |
de151cf6 | 2659 | |
007cc8ac | 2660 | list_del_init(®->lru_list); |
d9e86c0e CW |
2661 | reg->obj = NULL; |
2662 | reg->setup_seqno = 0; | |
52dc7d32 CW |
2663 | } |
2664 | ||
673a394b EA |
2665 | /** |
2666 | * Finds free space in the GTT aperture and binds the object there. | |
2667 | */ | |
2668 | static int | |
05394f39 | 2669 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2670 | unsigned alignment, |
75e9e915 | 2671 | bool map_and_fenceable) |
673a394b | 2672 | { |
05394f39 | 2673 | struct drm_device *dev = obj->base.dev; |
673a394b | 2674 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2675 | struct drm_mm_node *free_space; |
a00b10c3 | 2676 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2677 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2678 | bool mappable, fenceable; |
07f73f69 | 2679 | int ret; |
673a394b | 2680 | |
05394f39 | 2681 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2682 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2683 | return -EINVAL; | |
2684 | } | |
2685 | ||
e28f8711 CW |
2686 | fence_size = i915_gem_get_gtt_size(dev, |
2687 | obj->base.size, | |
2688 | obj->tiling_mode); | |
2689 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2690 | obj->base.size, | |
2691 | obj->tiling_mode); | |
2692 | unfenced_alignment = | |
2693 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2694 | obj->base.size, | |
2695 | obj->tiling_mode); | |
a00b10c3 | 2696 | |
673a394b | 2697 | if (alignment == 0) |
5e783301 DV |
2698 | alignment = map_and_fenceable ? fence_alignment : |
2699 | unfenced_alignment; | |
75e9e915 | 2700 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2701 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2702 | return -EINVAL; | |
2703 | } | |
2704 | ||
05394f39 | 2705 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2706 | |
654fc607 CW |
2707 | /* If the object is bigger than the entire aperture, reject it early |
2708 | * before evicting everything in a vain attempt to find space. | |
2709 | */ | |
05394f39 | 2710 | if (obj->base.size > |
75e9e915 | 2711 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2712 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2713 | return -E2BIG; | |
2714 | } | |
2715 | ||
673a394b | 2716 | search_free: |
75e9e915 | 2717 | if (map_and_fenceable) |
920afa77 DV |
2718 | free_space = |
2719 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2720 | size, alignment, 0, |
920afa77 DV |
2721 | dev_priv->mm.gtt_mappable_end, |
2722 | 0); | |
2723 | else | |
2724 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2725 | size, alignment, 0); |
920afa77 DV |
2726 | |
2727 | if (free_space != NULL) { | |
75e9e915 | 2728 | if (map_and_fenceable) |
05394f39 | 2729 | obj->gtt_space = |
920afa77 | 2730 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2731 | size, alignment, 0, |
920afa77 DV |
2732 | dev_priv->mm.gtt_mappable_end, |
2733 | 0); | |
2734 | else | |
05394f39 | 2735 | obj->gtt_space = |
a00b10c3 | 2736 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2737 | } |
05394f39 | 2738 | if (obj->gtt_space == NULL) { |
673a394b EA |
2739 | /* If the gtt is empty and we're still having trouble |
2740 | * fitting our object in, we're out of memory. | |
2741 | */ | |
75e9e915 DV |
2742 | ret = i915_gem_evict_something(dev, size, alignment, |
2743 | map_and_fenceable); | |
9731129c | 2744 | if (ret) |
673a394b | 2745 | return ret; |
9731129c | 2746 | |
673a394b EA |
2747 | goto search_free; |
2748 | } | |
2749 | ||
e5281ccd | 2750 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2751 | if (ret) { |
05394f39 CW |
2752 | drm_mm_put_block(obj->gtt_space); |
2753 | obj->gtt_space = NULL; | |
07f73f69 CW |
2754 | |
2755 | if (ret == -ENOMEM) { | |
809b6334 CW |
2756 | /* first try to reclaim some memory by clearing the GTT */ |
2757 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2758 | if (ret) { |
07f73f69 | 2759 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2760 | if (gfpmask) { |
2761 | gfpmask = 0; | |
2762 | goto search_free; | |
07f73f69 CW |
2763 | } |
2764 | ||
809b6334 | 2765 | return -ENOMEM; |
07f73f69 CW |
2766 | } |
2767 | ||
2768 | goto search_free; | |
2769 | } | |
2770 | ||
673a394b EA |
2771 | return ret; |
2772 | } | |
2773 | ||
7c2e6fdf DV |
2774 | ret = i915_gem_gtt_bind_object(obj); |
2775 | if (ret) { | |
e5281ccd | 2776 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2777 | drm_mm_put_block(obj->gtt_space); |
2778 | obj->gtt_space = NULL; | |
07f73f69 | 2779 | |
809b6334 | 2780 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2781 | return ret; |
07f73f69 CW |
2782 | |
2783 | goto search_free; | |
673a394b | 2784 | } |
673a394b | 2785 | |
6299f992 | 2786 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2787 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2788 | |
673a394b EA |
2789 | /* Assert that the object is not currently in any GPU domain. As it |
2790 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2791 | * a GPU cache | |
2792 | */ | |
05394f39 CW |
2793 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2794 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2795 | |
6299f992 | 2796 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2797 | |
75e9e915 | 2798 | fenceable = |
05394f39 | 2799 | obj->gtt_space->size == fence_size && |
0206e353 | 2800 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2801 | |
75e9e915 | 2802 | mappable = |
05394f39 | 2803 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2804 | |
05394f39 | 2805 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2806 | |
db53a302 | 2807 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2808 | return 0; |
2809 | } | |
2810 | ||
2811 | void | |
05394f39 | 2812 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2813 | { |
673a394b EA |
2814 | /* If we don't have a page list set up, then we're not pinned |
2815 | * to GPU, and we can ignore the cache flush because it'll happen | |
2816 | * again at bind time. | |
2817 | */ | |
05394f39 | 2818 | if (obj->pages == NULL) |
673a394b EA |
2819 | return; |
2820 | ||
9c23f7fc CW |
2821 | /* If the GPU is snooping the contents of the CPU cache, |
2822 | * we do not need to manually clear the CPU cache lines. However, | |
2823 | * the caches are only snooped when the render cache is | |
2824 | * flushed/invalidated. As we always have to emit invalidations | |
2825 | * and flushes when moving into and out of the RENDER domain, correct | |
2826 | * snooping behaviour occurs naturally as the result of our domain | |
2827 | * tracking. | |
2828 | */ | |
2829 | if (obj->cache_level != I915_CACHE_NONE) | |
2830 | return; | |
2831 | ||
1c5d22f7 | 2832 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2833 | |
05394f39 | 2834 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2835 | } |
2836 | ||
e47c68e9 | 2837 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2838 | static int |
3619df03 | 2839 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2840 | { |
05394f39 | 2841 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2842 | return 0; |
e47c68e9 EA |
2843 | |
2844 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2845 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2846 | } |
2847 | ||
2848 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2849 | static void | |
05394f39 | 2850 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2851 | { |
1c5d22f7 CW |
2852 | uint32_t old_write_domain; |
2853 | ||
05394f39 | 2854 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2855 | return; |
2856 | ||
63256ec5 | 2857 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2858 | * to it immediately go to main memory as far as we know, so there's |
2859 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2860 | * |
2861 | * However, we do have to enforce the order so that all writes through | |
2862 | * the GTT land before any writes to the device, such as updates to | |
2863 | * the GATT itself. | |
e47c68e9 | 2864 | */ |
63256ec5 CW |
2865 | wmb(); |
2866 | ||
05394f39 CW |
2867 | old_write_domain = obj->base.write_domain; |
2868 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2869 | |
2870 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2871 | obj->base.read_domains, |
1c5d22f7 | 2872 | old_write_domain); |
e47c68e9 EA |
2873 | } |
2874 | ||
2875 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2876 | static void | |
05394f39 | 2877 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2878 | { |
1c5d22f7 | 2879 | uint32_t old_write_domain; |
e47c68e9 | 2880 | |
05394f39 | 2881 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2882 | return; |
2883 | ||
2884 | i915_gem_clflush_object(obj); | |
40ce6575 | 2885 | intel_gtt_chipset_flush(); |
05394f39 CW |
2886 | old_write_domain = obj->base.write_domain; |
2887 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2888 | |
2889 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2890 | obj->base.read_domains, |
1c5d22f7 | 2891 | old_write_domain); |
e47c68e9 EA |
2892 | } |
2893 | ||
2ef7eeaa EA |
2894 | /** |
2895 | * Moves a single object to the GTT read, and possibly write domain. | |
2896 | * | |
2897 | * This function returns when the move is complete, including waiting on | |
2898 | * flushes to occur. | |
2899 | */ | |
79e53945 | 2900 | int |
2021746e | 2901 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2902 | { |
1c5d22f7 | 2903 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2904 | int ret; |
2ef7eeaa | 2905 | |
02354392 | 2906 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2907 | if (obj->gtt_space == NULL) |
02354392 EA |
2908 | return -EINVAL; |
2909 | ||
8d7e3de1 CW |
2910 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2911 | return 0; | |
2912 | ||
88241785 CW |
2913 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2914 | if (ret) | |
2915 | return ret; | |
2916 | ||
87ca9c8a | 2917 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2918 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2919 | if (ret) |
2920 | return ret; | |
2921 | } | |
2dafb1e0 | 2922 | |
7213342d | 2923 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2924 | |
05394f39 CW |
2925 | old_write_domain = obj->base.write_domain; |
2926 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2927 | |
e47c68e9 EA |
2928 | /* It should now be out of any other write domains, and we can update |
2929 | * the domain values for our changes. | |
2930 | */ | |
05394f39 CW |
2931 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2932 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2933 | if (write) { |
05394f39 CW |
2934 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2935 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2936 | obj->dirty = 1; | |
2ef7eeaa EA |
2937 | } |
2938 | ||
1c5d22f7 CW |
2939 | trace_i915_gem_object_change_domain(obj, |
2940 | old_read_domains, | |
2941 | old_write_domain); | |
2942 | ||
e47c68e9 EA |
2943 | return 0; |
2944 | } | |
2945 | ||
e4ffd173 CW |
2946 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2947 | enum i915_cache_level cache_level) | |
2948 | { | |
2949 | int ret; | |
2950 | ||
2951 | if (obj->cache_level == cache_level) | |
2952 | return 0; | |
2953 | ||
2954 | if (obj->pin_count) { | |
2955 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2956 | return -EBUSY; | |
2957 | } | |
2958 | ||
2959 | if (obj->gtt_space) { | |
2960 | ret = i915_gem_object_finish_gpu(obj); | |
2961 | if (ret) | |
2962 | return ret; | |
2963 | ||
2964 | i915_gem_object_finish_gtt(obj); | |
2965 | ||
2966 | /* Before SandyBridge, you could not use tiling or fence | |
2967 | * registers with snooped memory, so relinquish any fences | |
2968 | * currently pointing to our region in the aperture. | |
2969 | */ | |
2970 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2971 | ret = i915_gem_object_put_fence(obj); | |
2972 | if (ret) | |
2973 | return ret; | |
2974 | } | |
2975 | ||
2976 | i915_gem_gtt_rebind_object(obj, cache_level); | |
2977 | } | |
2978 | ||
2979 | if (cache_level == I915_CACHE_NONE) { | |
2980 | u32 old_read_domains, old_write_domain; | |
2981 | ||
2982 | /* If we're coming from LLC cached, then we haven't | |
2983 | * actually been tracking whether the data is in the | |
2984 | * CPU cache or not, since we only allow one bit set | |
2985 | * in obj->write_domain and have been skipping the clflushes. | |
2986 | * Just set it to the CPU cache for now. | |
2987 | */ | |
2988 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2989 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2990 | ||
2991 | old_read_domains = obj->base.read_domains; | |
2992 | old_write_domain = obj->base.write_domain; | |
2993 | ||
2994 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2995 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2996 | ||
2997 | trace_i915_gem_object_change_domain(obj, | |
2998 | old_read_domains, | |
2999 | old_write_domain); | |
3000 | } | |
3001 | ||
3002 | obj->cache_level = cache_level; | |
3003 | return 0; | |
3004 | } | |
3005 | ||
b9241ea3 | 3006 | /* |
2da3b9b9 CW |
3007 | * Prepare buffer for display plane (scanout, cursors, etc). |
3008 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3009 | * any flushes to be pipelined (for pageflips). | |
3010 | * | |
3011 | * For the display plane, we want to be in the GTT but out of any write | |
3012 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the | |
3013 | * ability to pipeline the waits, pinning and any additional subtleties | |
3014 | * that may differentiate the display plane from ordinary buffers. | |
b9241ea3 ZW |
3015 | */ |
3016 | int | |
2da3b9b9 CW |
3017 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3018 | u32 alignment, | |
919926ae | 3019 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3020 | { |
2da3b9b9 | 3021 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3022 | int ret; |
3023 | ||
88241785 CW |
3024 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3025 | if (ret) | |
3026 | return ret; | |
3027 | ||
0be73284 | 3028 | if (pipelined != obj->ring) { |
ce453d81 | 3029 | ret = i915_gem_object_wait_rendering(obj); |
f0b69efc | 3030 | if (ret == -ERESTARTSYS) |
b9241ea3 ZW |
3031 | return ret; |
3032 | } | |
3033 | ||
a7ef0640 EA |
3034 | /* The display engine is not coherent with the LLC cache on gen6. As |
3035 | * a result, we make sure that the pinning that is about to occur is | |
3036 | * done with uncached PTEs. This is lowest common denominator for all | |
3037 | * chipsets. | |
3038 | * | |
3039 | * However for gen6+, we could do better by using the GFDT bit instead | |
3040 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3041 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3042 | */ | |
3043 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3044 | if (ret) | |
3045 | return ret; | |
3046 | ||
2da3b9b9 CW |
3047 | /* As the user may map the buffer once pinned in the display plane |
3048 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3049 | * always use map_and_fenceable for all scanout buffers. | |
3050 | */ | |
3051 | ret = i915_gem_object_pin(obj, alignment, true); | |
3052 | if (ret) | |
3053 | return ret; | |
3054 | ||
b118c1e3 CW |
3055 | i915_gem_object_flush_cpu_write_domain(obj); |
3056 | ||
2da3b9b9 | 3057 | old_write_domain = obj->base.write_domain; |
05394f39 | 3058 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3059 | |
3060 | /* It should now be out of any other write domains, and we can update | |
3061 | * the domain values for our changes. | |
3062 | */ | |
3063 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 3064 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3065 | |
3066 | trace_i915_gem_object_change_domain(obj, | |
3067 | old_read_domains, | |
2da3b9b9 | 3068 | old_write_domain); |
b9241ea3 ZW |
3069 | |
3070 | return 0; | |
3071 | } | |
3072 | ||
85345517 | 3073 | int |
a8198eea | 3074 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3075 | { |
88241785 CW |
3076 | int ret; |
3077 | ||
a8198eea | 3078 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3079 | return 0; |
3080 | ||
88241785 | 3081 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3082 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
3083 | if (ret) |
3084 | return ret; | |
3085 | } | |
85345517 | 3086 | |
a8198eea CW |
3087 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3088 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
3089 | ||
ce453d81 | 3090 | return i915_gem_object_wait_rendering(obj); |
85345517 CW |
3091 | } |
3092 | ||
e47c68e9 EA |
3093 | /** |
3094 | * Moves a single object to the CPU read, and possibly write domain. | |
3095 | * | |
3096 | * This function returns when the move is complete, including waiting on | |
3097 | * flushes to occur. | |
3098 | */ | |
3099 | static int | |
919926ae | 3100 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3101 | { |
1c5d22f7 | 3102 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3103 | int ret; |
3104 | ||
8d7e3de1 CW |
3105 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3106 | return 0; | |
3107 | ||
88241785 CW |
3108 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3109 | if (ret) | |
3110 | return ret; | |
3111 | ||
ce453d81 | 3112 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3113 | if (ret) |
e47c68e9 | 3114 | return ret; |
2ef7eeaa | 3115 | |
e47c68e9 | 3116 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3117 | |
e47c68e9 EA |
3118 | /* If we have a partially-valid cache of the object in the CPU, |
3119 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3120 | */ |
e47c68e9 | 3121 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3122 | |
05394f39 CW |
3123 | old_write_domain = obj->base.write_domain; |
3124 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3125 | |
e47c68e9 | 3126 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3127 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3128 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3129 | |
05394f39 | 3130 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3131 | } |
3132 | ||
3133 | /* It should now be out of any other write domains, and we can update | |
3134 | * the domain values for our changes. | |
3135 | */ | |
05394f39 | 3136 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3137 | |
3138 | /* If we're writing through the CPU, then the GPU read domains will | |
3139 | * need to be invalidated at next use. | |
3140 | */ | |
3141 | if (write) { | |
05394f39 CW |
3142 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3143 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3144 | } |
2ef7eeaa | 3145 | |
1c5d22f7 CW |
3146 | trace_i915_gem_object_change_domain(obj, |
3147 | old_read_domains, | |
3148 | old_write_domain); | |
3149 | ||
2ef7eeaa EA |
3150 | return 0; |
3151 | } | |
3152 | ||
673a394b | 3153 | /** |
e47c68e9 | 3154 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3155 | * |
e47c68e9 EA |
3156 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3157 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3158 | */ |
e47c68e9 | 3159 | static void |
05394f39 | 3160 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3161 | { |
05394f39 | 3162 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3163 | return; |
3164 | ||
3165 | /* If we're partially in the CPU read domain, finish moving it in. | |
3166 | */ | |
05394f39 | 3167 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3168 | int i; |
3169 | ||
05394f39 CW |
3170 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3171 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3172 | continue; |
05394f39 | 3173 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3174 | } |
e47c68e9 EA |
3175 | } |
3176 | ||
3177 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3178 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3179 | */ | |
05394f39 CW |
3180 | kfree(obj->page_cpu_valid); |
3181 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3182 | } |
3183 | ||
3184 | /** | |
3185 | * Set the CPU read domain on a range of the object. | |
3186 | * | |
3187 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3188 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3189 | * pages have been flushed, and will be respected by | |
3190 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3191 | * of the whole object. | |
3192 | * | |
3193 | * This function returns when the move is complete, including waiting on | |
3194 | * flushes to occur. | |
3195 | */ | |
3196 | static int | |
05394f39 | 3197 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3198 | uint64_t offset, uint64_t size) |
3199 | { | |
1c5d22f7 | 3200 | uint32_t old_read_domains; |
e47c68e9 | 3201 | int i, ret; |
673a394b | 3202 | |
05394f39 | 3203 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3204 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3205 | |
88241785 CW |
3206 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3207 | if (ret) | |
3208 | return ret; | |
3209 | ||
ce453d81 | 3210 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3211 | if (ret) |
6a47baa6 | 3212 | return ret; |
de18a29e | 3213 | |
e47c68e9 EA |
3214 | i915_gem_object_flush_gtt_write_domain(obj); |
3215 | ||
3216 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3217 | if (obj->page_cpu_valid == NULL && |
3218 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3219 | return 0; |
673a394b | 3220 | |
e47c68e9 EA |
3221 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3222 | * newly adding I915_GEM_DOMAIN_CPU | |
3223 | */ | |
05394f39 CW |
3224 | if (obj->page_cpu_valid == NULL) { |
3225 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3226 | GFP_KERNEL); | |
3227 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3228 | return -ENOMEM; |
05394f39 CW |
3229 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3230 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3231 | |
3232 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3233 | * perspective. | |
3234 | */ | |
e47c68e9 EA |
3235 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3236 | i++) { | |
05394f39 | 3237 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3238 | continue; |
3239 | ||
05394f39 | 3240 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3241 | |
05394f39 | 3242 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3243 | } |
3244 | ||
e47c68e9 EA |
3245 | /* It should now be out of any other write domains, and we can update |
3246 | * the domain values for our changes. | |
3247 | */ | |
05394f39 | 3248 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3249 | |
05394f39 CW |
3250 | old_read_domains = obj->base.read_domains; |
3251 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3252 | |
1c5d22f7 CW |
3253 | trace_i915_gem_object_change_domain(obj, |
3254 | old_read_domains, | |
05394f39 | 3255 | obj->base.write_domain); |
1c5d22f7 | 3256 | |
673a394b EA |
3257 | return 0; |
3258 | } | |
3259 | ||
673a394b EA |
3260 | /* Throttle our rendering by waiting until the ring has completed our requests |
3261 | * emitted over 20 msec ago. | |
3262 | * | |
b962442e EA |
3263 | * Note that if we were to use the current jiffies each time around the loop, |
3264 | * we wouldn't escape the function with any frames outstanding if the time to | |
3265 | * render a frame was over 20ms. | |
3266 | * | |
673a394b EA |
3267 | * This should get us reasonable parallelism between CPU and GPU but also |
3268 | * relatively low latency when blocking on a particular request to finish. | |
3269 | */ | |
40a5f0de | 3270 | static int |
f787a5f5 | 3271 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3272 | { |
f787a5f5 CW |
3273 | struct drm_i915_private *dev_priv = dev->dev_private; |
3274 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3275 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3276 | struct drm_i915_gem_request *request; |
3277 | struct intel_ring_buffer *ring = NULL; | |
3278 | u32 seqno = 0; | |
3279 | int ret; | |
93533c29 | 3280 | |
e110e8d6 CW |
3281 | if (atomic_read(&dev_priv->mm.wedged)) |
3282 | return -EIO; | |
3283 | ||
1c25595f | 3284 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3285 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3286 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3287 | break; | |
40a5f0de | 3288 | |
f787a5f5 CW |
3289 | ring = request->ring; |
3290 | seqno = request->seqno; | |
b962442e | 3291 | } |
1c25595f | 3292 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3293 | |
f787a5f5 CW |
3294 | if (seqno == 0) |
3295 | return 0; | |
2bc43b5c | 3296 | |
f787a5f5 | 3297 | ret = 0; |
78501eac | 3298 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3299 | /* And wait for the seqno passing without holding any locks and |
3300 | * causing extra latency for others. This is safe as the irq | |
3301 | * generation is designed to be run atomically and so is | |
3302 | * lockless. | |
3303 | */ | |
b13c2b96 CW |
3304 | if (ring->irq_get(ring)) { |
3305 | ret = wait_event_interruptible(ring->irq_queue, | |
3306 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3307 | || atomic_read(&dev_priv->mm.wedged)); | |
3308 | ring->irq_put(ring); | |
40a5f0de | 3309 | |
b13c2b96 CW |
3310 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3311 | ret = -EIO; | |
3312 | } | |
40a5f0de EA |
3313 | } |
3314 | ||
f787a5f5 CW |
3315 | if (ret == 0) |
3316 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3317 | |
3318 | return ret; | |
3319 | } | |
3320 | ||
673a394b | 3321 | int |
05394f39 CW |
3322 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3323 | uint32_t alignment, | |
75e9e915 | 3324 | bool map_and_fenceable) |
673a394b | 3325 | { |
05394f39 | 3326 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3327 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3328 | int ret; |
3329 | ||
05394f39 | 3330 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3331 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3332 | |
05394f39 CW |
3333 | if (obj->gtt_space != NULL) { |
3334 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3335 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3336 | WARN(obj->pin_count, | |
ae7d49d8 | 3337 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3338 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3339 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3340 | obj->gtt_offset, alignment, |
75e9e915 | 3341 | map_and_fenceable, |
05394f39 | 3342 | obj->map_and_fenceable); |
ac0c6b5a CW |
3343 | ret = i915_gem_object_unbind(obj); |
3344 | if (ret) | |
3345 | return ret; | |
3346 | } | |
3347 | } | |
3348 | ||
05394f39 | 3349 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3350 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3351 | map_and_fenceable); |
9731129c | 3352 | if (ret) |
673a394b | 3353 | return ret; |
22c344e9 | 3354 | } |
76446cac | 3355 | |
05394f39 | 3356 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3357 | if (!obj->active) |
3358 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3359 | &dev_priv->mm.pinned_list); |
673a394b | 3360 | } |
6299f992 | 3361 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3362 | |
23bc5982 | 3363 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3364 | return 0; |
3365 | } | |
3366 | ||
3367 | void | |
05394f39 | 3368 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3369 | { |
05394f39 | 3370 | struct drm_device *dev = obj->base.dev; |
673a394b | 3371 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3372 | |
23bc5982 | 3373 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3374 | BUG_ON(obj->pin_count == 0); |
3375 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3376 | |
05394f39 CW |
3377 | if (--obj->pin_count == 0) { |
3378 | if (!obj->active) | |
3379 | list_move_tail(&obj->mm_list, | |
673a394b | 3380 | &dev_priv->mm.inactive_list); |
6299f992 | 3381 | obj->pin_mappable = false; |
673a394b | 3382 | } |
23bc5982 | 3383 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3384 | } |
3385 | ||
3386 | int | |
3387 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3388 | struct drm_file *file) |
673a394b EA |
3389 | { |
3390 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3391 | struct drm_i915_gem_object *obj; |
673a394b EA |
3392 | int ret; |
3393 | ||
1d7cfea1 CW |
3394 | ret = i915_mutex_lock_interruptible(dev); |
3395 | if (ret) | |
3396 | return ret; | |
673a394b | 3397 | |
05394f39 | 3398 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3399 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3400 | ret = -ENOENT; |
3401 | goto unlock; | |
673a394b | 3402 | } |
673a394b | 3403 | |
05394f39 | 3404 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3405 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3406 | ret = -EINVAL; |
3407 | goto out; | |
3ef94daa CW |
3408 | } |
3409 | ||
05394f39 | 3410 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3411 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3412 | args->handle); | |
1d7cfea1 CW |
3413 | ret = -EINVAL; |
3414 | goto out; | |
79e53945 JB |
3415 | } |
3416 | ||
05394f39 CW |
3417 | obj->user_pin_count++; |
3418 | obj->pin_filp = file; | |
3419 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3420 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3421 | if (ret) |
3422 | goto out; | |
673a394b EA |
3423 | } |
3424 | ||
3425 | /* XXX - flush the CPU caches for pinned objects | |
3426 | * as the X server doesn't manage domains yet | |
3427 | */ | |
e47c68e9 | 3428 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3429 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3430 | out: |
05394f39 | 3431 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3432 | unlock: |
673a394b | 3433 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3434 | return ret; |
673a394b EA |
3435 | } |
3436 | ||
3437 | int | |
3438 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3439 | struct drm_file *file) |
673a394b EA |
3440 | { |
3441 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3442 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3443 | int ret; |
673a394b | 3444 | |
1d7cfea1 CW |
3445 | ret = i915_mutex_lock_interruptible(dev); |
3446 | if (ret) | |
3447 | return ret; | |
673a394b | 3448 | |
05394f39 | 3449 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3450 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3451 | ret = -ENOENT; |
3452 | goto unlock; | |
673a394b | 3453 | } |
76c1dec1 | 3454 | |
05394f39 | 3455 | if (obj->pin_filp != file) { |
79e53945 JB |
3456 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3457 | args->handle); | |
1d7cfea1 CW |
3458 | ret = -EINVAL; |
3459 | goto out; | |
79e53945 | 3460 | } |
05394f39 CW |
3461 | obj->user_pin_count--; |
3462 | if (obj->user_pin_count == 0) { | |
3463 | obj->pin_filp = NULL; | |
79e53945 JB |
3464 | i915_gem_object_unpin(obj); |
3465 | } | |
673a394b | 3466 | |
1d7cfea1 | 3467 | out: |
05394f39 | 3468 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3469 | unlock: |
673a394b | 3470 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3471 | return ret; |
673a394b EA |
3472 | } |
3473 | ||
3474 | int | |
3475 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3476 | struct drm_file *file) |
673a394b EA |
3477 | { |
3478 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3479 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3480 | int ret; |
3481 | ||
76c1dec1 | 3482 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3483 | if (ret) |
76c1dec1 | 3484 | return ret; |
673a394b | 3485 | |
05394f39 | 3486 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3487 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3488 | ret = -ENOENT; |
3489 | goto unlock; | |
673a394b | 3490 | } |
d1b851fc | 3491 | |
0be555b6 CW |
3492 | /* Count all active objects as busy, even if they are currently not used |
3493 | * by the gpu. Users of this interface expect objects to eventually | |
3494 | * become non-busy without any further actions, therefore emit any | |
3495 | * necessary flushes here. | |
c4de0a5d | 3496 | */ |
05394f39 | 3497 | args->busy = obj->active; |
0be555b6 CW |
3498 | if (args->busy) { |
3499 | /* Unconditionally flush objects, even when the gpu still uses this | |
3500 | * object. Userspace calling this function indicates that it wants to | |
3501 | * use this buffer rather sooner than later, so issuing the required | |
3502 | * flush earlier is beneficial. | |
3503 | */ | |
1a1c6976 | 3504 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3505 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3506 | 0, obj->base.write_domain); |
1a1c6976 CW |
3507 | } else if (obj->ring->outstanding_lazy_request == |
3508 | obj->last_rendering_seqno) { | |
3509 | struct drm_i915_gem_request *request; | |
3510 | ||
7a194876 CW |
3511 | /* This ring is not being cleared by active usage, |
3512 | * so emit a request to do so. | |
3513 | */ | |
1a1c6976 CW |
3514 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3515 | if (request) | |
0206e353 | 3516 | ret = i915_add_request(obj->ring, NULL, request); |
1a1c6976 | 3517 | else |
7a194876 CW |
3518 | ret = -ENOMEM; |
3519 | } | |
0be555b6 CW |
3520 | |
3521 | /* Update the active list for the hardware's current position. | |
3522 | * Otherwise this only updates on a delayed timer or when irqs | |
3523 | * are actually unmasked, and our working set ends up being | |
3524 | * larger than required. | |
3525 | */ | |
db53a302 | 3526 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3527 | |
05394f39 | 3528 | args->busy = obj->active; |
0be555b6 | 3529 | } |
673a394b | 3530 | |
05394f39 | 3531 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3532 | unlock: |
673a394b | 3533 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3534 | return ret; |
673a394b EA |
3535 | } |
3536 | ||
3537 | int | |
3538 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3539 | struct drm_file *file_priv) | |
3540 | { | |
0206e353 | 3541 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3542 | } |
3543 | ||
3ef94daa CW |
3544 | int |
3545 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3546 | struct drm_file *file_priv) | |
3547 | { | |
3548 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3549 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3550 | int ret; |
3ef94daa CW |
3551 | |
3552 | switch (args->madv) { | |
3553 | case I915_MADV_DONTNEED: | |
3554 | case I915_MADV_WILLNEED: | |
3555 | break; | |
3556 | default: | |
3557 | return -EINVAL; | |
3558 | } | |
3559 | ||
1d7cfea1 CW |
3560 | ret = i915_mutex_lock_interruptible(dev); |
3561 | if (ret) | |
3562 | return ret; | |
3563 | ||
05394f39 | 3564 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3565 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3566 | ret = -ENOENT; |
3567 | goto unlock; | |
3ef94daa | 3568 | } |
3ef94daa | 3569 | |
05394f39 | 3570 | if (obj->pin_count) { |
1d7cfea1 CW |
3571 | ret = -EINVAL; |
3572 | goto out; | |
3ef94daa CW |
3573 | } |
3574 | ||
05394f39 CW |
3575 | if (obj->madv != __I915_MADV_PURGED) |
3576 | obj->madv = args->madv; | |
3ef94daa | 3577 | |
2d7ef395 | 3578 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3579 | if (i915_gem_object_is_purgeable(obj) && |
3580 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3581 | i915_gem_object_truncate(obj); |
3582 | ||
05394f39 | 3583 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3584 | |
1d7cfea1 | 3585 | out: |
05394f39 | 3586 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3587 | unlock: |
3ef94daa | 3588 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3589 | return ret; |
3ef94daa CW |
3590 | } |
3591 | ||
05394f39 CW |
3592 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3593 | size_t size) | |
ac52bc56 | 3594 | { |
73aa808f | 3595 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3596 | struct drm_i915_gem_object *obj; |
5949eac4 | 3597 | struct address_space *mapping; |
ac52bc56 | 3598 | |
c397b908 DV |
3599 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3600 | if (obj == NULL) | |
3601 | return NULL; | |
673a394b | 3602 | |
c397b908 DV |
3603 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3604 | kfree(obj); | |
3605 | return NULL; | |
3606 | } | |
673a394b | 3607 | |
5949eac4 HD |
3608 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3609 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3610 | ||
73aa808f CW |
3611 | i915_gem_info_add_obj(dev_priv, size); |
3612 | ||
c397b908 DV |
3613 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3614 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3615 | |
a1871112 EA |
3616 | if (IS_GEN6(dev)) { |
3617 | /* On Gen6, we can have the GPU use the LLC (the CPU | |
3618 | * cache) for about a 10% performance improvement | |
3619 | * compared to uncached. Graphics requests other than | |
3620 | * display scanout are coherent with the CPU in | |
3621 | * accessing this cache. This means in this mode we | |
3622 | * don't need to clflush on the CPU side, and on the | |
3623 | * GPU side we only need to flush internal caches to | |
3624 | * get data visible to the CPU. | |
3625 | * | |
3626 | * However, we maintain the display planes as UC, and so | |
3627 | * need to rebind when first used as such. | |
3628 | */ | |
3629 | obj->cache_level = I915_CACHE_LLC; | |
3630 | } else | |
3631 | obj->cache_level = I915_CACHE_NONE; | |
3632 | ||
62b8b215 | 3633 | obj->base.driver_private = NULL; |
c397b908 | 3634 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3635 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3636 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3637 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3638 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3639 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3640 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3641 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3642 | obj->map_and_fenceable = true; | |
de151cf6 | 3643 | |
05394f39 | 3644 | return obj; |
c397b908 DV |
3645 | } |
3646 | ||
3647 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3648 | { | |
3649 | BUG(); | |
de151cf6 | 3650 | |
673a394b EA |
3651 | return 0; |
3652 | } | |
3653 | ||
05394f39 | 3654 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3655 | { |
05394f39 | 3656 | struct drm_device *dev = obj->base.dev; |
be72615b | 3657 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3658 | int ret; |
673a394b | 3659 | |
be72615b CW |
3660 | ret = i915_gem_object_unbind(obj); |
3661 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3662 | list_move(&obj->mm_list, |
be72615b CW |
3663 | &dev_priv->mm.deferred_free_list); |
3664 | return; | |
3665 | } | |
673a394b | 3666 | |
26e12f89 CW |
3667 | trace_i915_gem_object_destroy(obj); |
3668 | ||
05394f39 | 3669 | if (obj->base.map_list.map) |
b464e9a2 | 3670 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3671 | |
05394f39 CW |
3672 | drm_gem_object_release(&obj->base); |
3673 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3674 | |
05394f39 CW |
3675 | kfree(obj->page_cpu_valid); |
3676 | kfree(obj->bit_17); | |
3677 | kfree(obj); | |
673a394b EA |
3678 | } |
3679 | ||
05394f39 | 3680 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3681 | { |
05394f39 CW |
3682 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3683 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3684 | |
05394f39 | 3685 | while (obj->pin_count > 0) |
be72615b CW |
3686 | i915_gem_object_unpin(obj); |
3687 | ||
05394f39 | 3688 | if (obj->phys_obj) |
be72615b CW |
3689 | i915_gem_detach_phys_object(dev, obj); |
3690 | ||
3691 | i915_gem_free_object_tail(obj); | |
3692 | } | |
3693 | ||
29105ccc CW |
3694 | int |
3695 | i915_gem_idle(struct drm_device *dev) | |
3696 | { | |
3697 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3698 | int ret; | |
28dfe52a | 3699 | |
29105ccc | 3700 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3701 | |
87acb0a5 | 3702 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3703 | mutex_unlock(&dev->struct_mutex); |
3704 | return 0; | |
28dfe52a EA |
3705 | } |
3706 | ||
29105ccc | 3707 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3708 | if (ret) { |
3709 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3710 | return ret; |
6dbe2772 | 3711 | } |
673a394b | 3712 | |
29105ccc CW |
3713 | /* Under UMS, be paranoid and evict. */ |
3714 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3715 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3716 | if (ret) { |
3717 | mutex_unlock(&dev->struct_mutex); | |
3718 | return ret; | |
3719 | } | |
3720 | } | |
3721 | ||
312817a3 CW |
3722 | i915_gem_reset_fences(dev); |
3723 | ||
29105ccc CW |
3724 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3725 | * We need to replace this with a semaphore, or something. | |
3726 | * And not confound mm.suspended! | |
3727 | */ | |
3728 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3729 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3730 | |
3731 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3732 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3733 | |
6dbe2772 KP |
3734 | mutex_unlock(&dev->struct_mutex); |
3735 | ||
29105ccc CW |
3736 | /* Cancel the retire work handler, which should be idle now. */ |
3737 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3738 | ||
673a394b EA |
3739 | return 0; |
3740 | } | |
3741 | ||
8187a2b7 ZN |
3742 | int |
3743 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
3744 | { | |
3745 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3746 | int ret; | |
68f95ba9 | 3747 | |
5c1143bb | 3748 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3749 | if (ret) |
b6913e4b | 3750 | return ret; |
68f95ba9 CW |
3751 | |
3752 | if (HAS_BSD(dev)) { | |
5c1143bb | 3753 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3754 | if (ret) |
3755 | goto cleanup_render_ring; | |
d1b851fc | 3756 | } |
68f95ba9 | 3757 | |
549f7365 CW |
3758 | if (HAS_BLT(dev)) { |
3759 | ret = intel_init_blt_ring_buffer(dev); | |
3760 | if (ret) | |
3761 | goto cleanup_bsd_ring; | |
3762 | } | |
3763 | ||
6f392d54 CW |
3764 | dev_priv->next_seqno = 1; |
3765 | ||
68f95ba9 CW |
3766 | return 0; |
3767 | ||
549f7365 | 3768 | cleanup_bsd_ring: |
1ec14ad3 | 3769 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3770 | cleanup_render_ring: |
1ec14ad3 | 3771 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3772 | return ret; |
3773 | } | |
3774 | ||
3775 | void | |
3776 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3777 | { | |
3778 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3779 | int i; |
8187a2b7 | 3780 | |
1ec14ad3 CW |
3781 | for (i = 0; i < I915_NUM_RINGS; i++) |
3782 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3783 | } |
3784 | ||
673a394b EA |
3785 | int |
3786 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3787 | struct drm_file *file_priv) | |
3788 | { | |
3789 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3790 | int ret, i; |
673a394b | 3791 | |
79e53945 JB |
3792 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3793 | return 0; | |
3794 | ||
ba1234d1 | 3795 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3796 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3797 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3798 | } |
3799 | ||
673a394b | 3800 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3801 | dev_priv->mm.suspended = 0; |
3802 | ||
3803 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
3804 | if (ret != 0) { |
3805 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3806 | return ret; |
d816f6ac | 3807 | } |
9bb2d6f9 | 3808 | |
69dc4987 | 3809 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3810 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3811 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3812 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3813 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3814 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3815 | } | |
673a394b | 3816 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3817 | |
5f35308b CW |
3818 | ret = drm_irq_install(dev); |
3819 | if (ret) | |
3820 | goto cleanup_ringbuffer; | |
dbb19d30 | 3821 | |
673a394b | 3822 | return 0; |
5f35308b CW |
3823 | |
3824 | cleanup_ringbuffer: | |
3825 | mutex_lock(&dev->struct_mutex); | |
3826 | i915_gem_cleanup_ringbuffer(dev); | |
3827 | dev_priv->mm.suspended = 1; | |
3828 | mutex_unlock(&dev->struct_mutex); | |
3829 | ||
3830 | return ret; | |
673a394b EA |
3831 | } |
3832 | ||
3833 | int | |
3834 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3835 | struct drm_file *file_priv) | |
3836 | { | |
79e53945 JB |
3837 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3838 | return 0; | |
3839 | ||
dbb19d30 | 3840 | drm_irq_uninstall(dev); |
e6890f6f | 3841 | return i915_gem_idle(dev); |
673a394b EA |
3842 | } |
3843 | ||
3844 | void | |
3845 | i915_gem_lastclose(struct drm_device *dev) | |
3846 | { | |
3847 | int ret; | |
673a394b | 3848 | |
e806b495 EA |
3849 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3850 | return; | |
3851 | ||
6dbe2772 KP |
3852 | ret = i915_gem_idle(dev); |
3853 | if (ret) | |
3854 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3855 | } |
3856 | ||
64193406 CW |
3857 | static void |
3858 | init_ring_lists(struct intel_ring_buffer *ring) | |
3859 | { | |
3860 | INIT_LIST_HEAD(&ring->active_list); | |
3861 | INIT_LIST_HEAD(&ring->request_list); | |
3862 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3863 | } | |
3864 | ||
673a394b EA |
3865 | void |
3866 | i915_gem_load(struct drm_device *dev) | |
3867 | { | |
b5aa8a0f | 3868 | int i; |
673a394b EA |
3869 | drm_i915_private_t *dev_priv = dev->dev_private; |
3870 | ||
69dc4987 | 3871 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3872 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3873 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3874 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3875 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3876 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3877 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3878 | for (i = 0; i < I915_NUM_RINGS; i++) |
3879 | init_ring_lists(&dev_priv->ring[i]); | |
007cc8ac DV |
3880 | for (i = 0; i < 16; i++) |
3881 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
3882 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3883 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3884 | init_completion(&dev_priv->error_completion); |
31169714 | 3885 | |
94400120 DA |
3886 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3887 | if (IS_GEN3(dev)) { | |
3888 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3889 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3890 | /* arb state is a masked write, so set bit + bit in mask */ | |
3891 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3892 | I915_WRITE(MI_ARB_STATE, tmp); | |
3893 | } | |
3894 | } | |
3895 | ||
72bfa19c CW |
3896 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3897 | ||
de151cf6 | 3898 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3899 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3900 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3901 | |
a6c45cf0 | 3902 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3903 | dev_priv->num_fence_regs = 16; |
3904 | else | |
3905 | dev_priv->num_fence_regs = 8; | |
3906 | ||
b5aa8a0f | 3907 | /* Initialize fence registers to zero */ |
10ed13e4 EA |
3908 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
3909 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); | |
b5aa8a0f | 3910 | } |
10ed13e4 | 3911 | |
673a394b | 3912 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3913 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3914 | |
ce453d81 CW |
3915 | dev_priv->mm.interruptible = true; |
3916 | ||
17250b71 CW |
3917 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3918 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3919 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3920 | } |
71acb5eb DA |
3921 | |
3922 | /* | |
3923 | * Create a physically contiguous memory object for this object | |
3924 | * e.g. for cursor + overlay regs | |
3925 | */ | |
995b6762 CW |
3926 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3927 | int id, int size, int align) | |
71acb5eb DA |
3928 | { |
3929 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3930 | struct drm_i915_gem_phys_object *phys_obj; | |
3931 | int ret; | |
3932 | ||
3933 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3934 | return 0; | |
3935 | ||
9a298b2a | 3936 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3937 | if (!phys_obj) |
3938 | return -ENOMEM; | |
3939 | ||
3940 | phys_obj->id = id; | |
3941 | ||
6eeefaf3 | 3942 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3943 | if (!phys_obj->handle) { |
3944 | ret = -ENOMEM; | |
3945 | goto kfree_obj; | |
3946 | } | |
3947 | #ifdef CONFIG_X86 | |
3948 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3949 | #endif | |
3950 | ||
3951 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3952 | ||
3953 | return 0; | |
3954 | kfree_obj: | |
9a298b2a | 3955 | kfree(phys_obj); |
71acb5eb DA |
3956 | return ret; |
3957 | } | |
3958 | ||
995b6762 | 3959 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3960 | { |
3961 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3962 | struct drm_i915_gem_phys_object *phys_obj; | |
3963 | ||
3964 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3965 | return; | |
3966 | ||
3967 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3968 | if (phys_obj->cur_obj) { | |
3969 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3970 | } | |
3971 | ||
3972 | #ifdef CONFIG_X86 | |
3973 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3974 | #endif | |
3975 | drm_pci_free(dev, phys_obj->handle); | |
3976 | kfree(phys_obj); | |
3977 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3978 | } | |
3979 | ||
3980 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3981 | { | |
3982 | int i; | |
3983 | ||
260883c8 | 3984 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3985 | i915_gem_free_phys_object(dev, i); |
3986 | } | |
3987 | ||
3988 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3989 | struct drm_i915_gem_object *obj) |
71acb5eb | 3990 | { |
05394f39 | 3991 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3992 | char *vaddr; |
71acb5eb | 3993 | int i; |
71acb5eb DA |
3994 | int page_count; |
3995 | ||
05394f39 | 3996 | if (!obj->phys_obj) |
71acb5eb | 3997 | return; |
05394f39 | 3998 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3999 | |
05394f39 | 4000 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4001 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4002 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4003 | if (!IS_ERR(page)) { |
4004 | char *dst = kmap_atomic(page); | |
4005 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4006 | kunmap_atomic(dst); | |
4007 | ||
4008 | drm_clflush_pages(&page, 1); | |
4009 | ||
4010 | set_page_dirty(page); | |
4011 | mark_page_accessed(page); | |
4012 | page_cache_release(page); | |
4013 | } | |
71acb5eb | 4014 | } |
40ce6575 | 4015 | intel_gtt_chipset_flush(); |
d78b47b9 | 4016 | |
05394f39 CW |
4017 | obj->phys_obj->cur_obj = NULL; |
4018 | obj->phys_obj = NULL; | |
71acb5eb DA |
4019 | } |
4020 | ||
4021 | int | |
4022 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4023 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4024 | int id, |
4025 | int align) | |
71acb5eb | 4026 | { |
05394f39 | 4027 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4028 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4029 | int ret = 0; |
4030 | int page_count; | |
4031 | int i; | |
4032 | ||
4033 | if (id > I915_MAX_PHYS_OBJECT) | |
4034 | return -EINVAL; | |
4035 | ||
05394f39 CW |
4036 | if (obj->phys_obj) { |
4037 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4038 | return 0; |
4039 | i915_gem_detach_phys_object(dev, obj); | |
4040 | } | |
4041 | ||
71acb5eb DA |
4042 | /* create a new object */ |
4043 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4044 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4045 | obj->base.size, align); |
71acb5eb | 4046 | if (ret) { |
05394f39 CW |
4047 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4048 | id, obj->base.size); | |
e5281ccd | 4049 | return ret; |
71acb5eb DA |
4050 | } |
4051 | } | |
4052 | ||
4053 | /* bind to the object */ | |
05394f39 CW |
4054 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4055 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4056 | |
05394f39 | 4057 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4058 | |
4059 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4060 | struct page *page; |
4061 | char *dst, *src; | |
4062 | ||
5949eac4 | 4063 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4064 | if (IS_ERR(page)) |
4065 | return PTR_ERR(page); | |
71acb5eb | 4066 | |
ff75b9bc | 4067 | src = kmap_atomic(page); |
05394f39 | 4068 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4069 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4070 | kunmap_atomic(src); |
71acb5eb | 4071 | |
e5281ccd CW |
4072 | mark_page_accessed(page); |
4073 | page_cache_release(page); | |
4074 | } | |
d78b47b9 | 4075 | |
71acb5eb | 4076 | return 0; |
71acb5eb DA |
4077 | } |
4078 | ||
4079 | static int | |
05394f39 CW |
4080 | i915_gem_phys_pwrite(struct drm_device *dev, |
4081 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4082 | struct drm_i915_gem_pwrite *args, |
4083 | struct drm_file *file_priv) | |
4084 | { | |
05394f39 | 4085 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4086 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4087 | |
b47b30cc CW |
4088 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4089 | unsigned long unwritten; | |
4090 | ||
4091 | /* The physical object once assigned is fixed for the lifetime | |
4092 | * of the obj, so we can safely drop the lock and continue | |
4093 | * to access vaddr. | |
4094 | */ | |
4095 | mutex_unlock(&dev->struct_mutex); | |
4096 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4097 | mutex_lock(&dev->struct_mutex); | |
4098 | if (unwritten) | |
4099 | return -EFAULT; | |
4100 | } | |
71acb5eb | 4101 | |
40ce6575 | 4102 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4103 | return 0; |
4104 | } | |
b962442e | 4105 | |
f787a5f5 | 4106 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4107 | { |
f787a5f5 | 4108 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4109 | |
4110 | /* Clean up our request list when the client is going away, so that | |
4111 | * later retire_requests won't dereference our soon-to-be-gone | |
4112 | * file_priv. | |
4113 | */ | |
1c25595f | 4114 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4115 | while (!list_empty(&file_priv->mm.request_list)) { |
4116 | struct drm_i915_gem_request *request; | |
4117 | ||
4118 | request = list_first_entry(&file_priv->mm.request_list, | |
4119 | struct drm_i915_gem_request, | |
4120 | client_list); | |
4121 | list_del(&request->client_list); | |
4122 | request->file_priv = NULL; | |
4123 | } | |
1c25595f | 4124 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4125 | } |
31169714 | 4126 | |
1637ef41 CW |
4127 | static int |
4128 | i915_gpu_is_active(struct drm_device *dev) | |
4129 | { | |
4130 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4131 | int lists_empty; | |
4132 | ||
1637ef41 | 4133 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4134 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4135 | |
4136 | return !lists_empty; | |
4137 | } | |
4138 | ||
31169714 | 4139 | static int |
1495f230 | 4140 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4141 | { |
17250b71 CW |
4142 | struct drm_i915_private *dev_priv = |
4143 | container_of(shrinker, | |
4144 | struct drm_i915_private, | |
4145 | mm.inactive_shrinker); | |
4146 | struct drm_device *dev = dev_priv->dev; | |
4147 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 4148 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4149 | int cnt; |
4150 | ||
4151 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4152 | return 0; |
31169714 CW |
4153 | |
4154 | /* "fast-path" to count number of available objects */ | |
4155 | if (nr_to_scan == 0) { | |
17250b71 CW |
4156 | cnt = 0; |
4157 | list_for_each_entry(obj, | |
4158 | &dev_priv->mm.inactive_list, | |
4159 | mm_list) | |
4160 | cnt++; | |
4161 | mutex_unlock(&dev->struct_mutex); | |
4162 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4163 | } |
4164 | ||
1637ef41 | 4165 | rescan: |
31169714 | 4166 | /* first scan for clean buffers */ |
17250b71 | 4167 | i915_gem_retire_requests(dev); |
31169714 | 4168 | |
17250b71 CW |
4169 | list_for_each_entry_safe(obj, next, |
4170 | &dev_priv->mm.inactive_list, | |
4171 | mm_list) { | |
4172 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4173 | if (i915_gem_object_unbind(obj) == 0 && |
4174 | --nr_to_scan == 0) | |
17250b71 | 4175 | break; |
31169714 | 4176 | } |
31169714 CW |
4177 | } |
4178 | ||
4179 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4180 | cnt = 0; |
4181 | list_for_each_entry_safe(obj, next, | |
4182 | &dev_priv->mm.inactive_list, | |
4183 | mm_list) { | |
2021746e CW |
4184 | if (nr_to_scan && |
4185 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4186 | nr_to_scan--; |
2021746e | 4187 | else |
17250b71 CW |
4188 | cnt++; |
4189 | } | |
4190 | ||
4191 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4192 | /* |
4193 | * We are desperate for pages, so as a last resort, wait | |
4194 | * for the GPU to finish and discard whatever we can. | |
4195 | * This has a dramatic impact to reduce the number of | |
4196 | * OOM-killer events whilst running the GPU aggressively. | |
4197 | */ | |
17250b71 | 4198 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
4199 | goto rescan; |
4200 | } | |
17250b71 CW |
4201 | mutex_unlock(&dev->struct_mutex); |
4202 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4203 | } |