Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
42 | bool force); | |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
673a394b | 46 | |
61050808 CW |
47 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
48 | struct drm_i915_gem_object *obj); | |
49 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
50 | struct drm_i915_fence_reg *fence, | |
51 | bool enable); | |
52 | ||
7dc19d5a DC |
53 | static unsigned long i915_gem_inactive_count(struct shrinker *shrinker, |
54 | struct shrink_control *sc); | |
55 | static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker, | |
56 | struct shrink_control *sc); | |
d9973b43 CW |
57 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
58 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 59 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
cb216aa8 | 60 | static void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
31169714 | 61 | |
c76ce038 CW |
62 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
63 | enum i915_cache_level level) | |
64 | { | |
65 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
66 | } | |
67 | ||
2c22569b CW |
68 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
69 | { | |
70 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
71 | return true; | |
72 | ||
73 | return obj->pin_display; | |
74 | } | |
75 | ||
61050808 CW |
76 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
77 | { | |
78 | if (obj->tiling_mode) | |
79 | i915_gem_release_mmap(obj); | |
80 | ||
81 | /* As we do not have an associated fence register, we will force | |
82 | * a tiling change if we ever need to acquire one. | |
83 | */ | |
5d82e3e6 | 84 | obj->fence_dirty = false; |
61050808 CW |
85 | obj->fence_reg = I915_FENCE_REG_NONE; |
86 | } | |
87 | ||
73aa808f CW |
88 | /* some bookkeeping */ |
89 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
90 | size_t size) | |
91 | { | |
c20e8355 | 92 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
93 | dev_priv->mm.object_count++; |
94 | dev_priv->mm.object_memory += size; | |
c20e8355 | 95 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
96 | } |
97 | ||
98 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
99 | size_t size) | |
100 | { | |
c20e8355 | 101 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
102 | dev_priv->mm.object_count--; |
103 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 104 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | } |
106 | ||
21dd3734 | 107 | static int |
33196ded | 108 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 109 | { |
30dbf0c0 CW |
110 | int ret; |
111 | ||
7abb690a DV |
112 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
113 | i915_terminally_wedged(error)) | |
1f83fee0 | 114 | if (EXIT_COND) |
30dbf0c0 CW |
115 | return 0; |
116 | ||
0a6759c6 DV |
117 | /* |
118 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
119 | * userspace. If it takes that long something really bad is going on and | |
120 | * we should simply try to bail out and fail as gracefully as possible. | |
121 | */ | |
1f83fee0 DV |
122 | ret = wait_event_interruptible_timeout(error->reset_queue, |
123 | EXIT_COND, | |
124 | 10*HZ); | |
0a6759c6 DV |
125 | if (ret == 0) { |
126 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
127 | return -EIO; | |
128 | } else if (ret < 0) { | |
30dbf0c0 | 129 | return ret; |
0a6759c6 | 130 | } |
1f83fee0 | 131 | #undef EXIT_COND |
30dbf0c0 | 132 | |
21dd3734 | 133 | return 0; |
30dbf0c0 CW |
134 | } |
135 | ||
54cf91dc | 136 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 137 | { |
33196ded | 138 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
139 | int ret; |
140 | ||
33196ded | 141 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
142 | if (ret) |
143 | return ret; | |
144 | ||
145 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
146 | if (ret) | |
147 | return ret; | |
148 | ||
23bc5982 | 149 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
150 | return 0; |
151 | } | |
30dbf0c0 | 152 | |
7d1c4804 | 153 | static inline bool |
05394f39 | 154 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 155 | { |
9843877d | 156 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
157 | } |
158 | ||
79e53945 JB |
159 | int |
160 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 161 | struct drm_file *file) |
79e53945 | 162 | { |
93d18799 | 163 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 164 | struct drm_i915_gem_init *args = data; |
2021746e | 165 | |
7bb6fb8d DV |
166 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
167 | return -ENODEV; | |
168 | ||
2021746e CW |
169 | if (args->gtt_start >= args->gtt_end || |
170 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
171 | return -EINVAL; | |
79e53945 | 172 | |
f534bc0b DV |
173 | /* GEM with user mode setting was never supported on ilk and later. */ |
174 | if (INTEL_INFO(dev)->gen >= 5) | |
175 | return -ENODEV; | |
176 | ||
79e53945 | 177 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
178 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
179 | args->gtt_end); | |
93d18799 | 180 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
181 | mutex_unlock(&dev->struct_mutex); |
182 | ||
2021746e | 183 | return 0; |
673a394b EA |
184 | } |
185 | ||
5a125c3c EA |
186 | int |
187 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 188 | struct drm_file *file) |
5a125c3c | 189 | { |
73aa808f | 190 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 191 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
192 | struct drm_i915_gem_object *obj; |
193 | size_t pinned; | |
5a125c3c | 194 | |
6299f992 | 195 | pinned = 0; |
73aa808f | 196 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 197 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 198 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 199 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 200 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 201 | |
853ba5d2 | 202 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 203 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 204 | |
5a125c3c EA |
205 | return 0; |
206 | } | |
207 | ||
00731155 CW |
208 | static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj) |
209 | { | |
210 | drm_dma_handle_t *phys = obj->phys_handle; | |
211 | ||
212 | if (!phys) | |
213 | return; | |
214 | ||
215 | if (obj->madv == I915_MADV_WILLNEED) { | |
216 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; | |
217 | char *vaddr = phys->vaddr; | |
218 | int i; | |
219 | ||
220 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
221 | struct page *page = shmem_read_mapping_page(mapping, i); | |
222 | if (!IS_ERR(page)) { | |
223 | char *dst = kmap_atomic(page); | |
224 | memcpy(dst, vaddr, PAGE_SIZE); | |
225 | drm_clflush_virt_range(dst, PAGE_SIZE); | |
226 | kunmap_atomic(dst); | |
227 | ||
228 | set_page_dirty(page); | |
229 | mark_page_accessed(page); | |
230 | page_cache_release(page); | |
231 | } | |
232 | vaddr += PAGE_SIZE; | |
233 | } | |
234 | i915_gem_chipset_flush(obj->base.dev); | |
235 | } | |
236 | ||
237 | #ifdef CONFIG_X86 | |
238 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); | |
239 | #endif | |
240 | drm_pci_free(obj->base.dev, phys); | |
241 | obj->phys_handle = NULL; | |
242 | } | |
243 | ||
244 | int | |
245 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
246 | int align) | |
247 | { | |
248 | drm_dma_handle_t *phys; | |
249 | struct address_space *mapping; | |
250 | char *vaddr; | |
251 | int i; | |
252 | ||
253 | if (obj->phys_handle) { | |
254 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
255 | return -EBUSY; | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
260 | if (obj->madv != I915_MADV_WILLNEED) | |
261 | return -EFAULT; | |
262 | ||
263 | if (obj->base.filp == NULL) | |
264 | return -EINVAL; | |
265 | ||
266 | /* create a new object */ | |
267 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
268 | if (!phys) | |
269 | return -ENOMEM; | |
270 | ||
271 | vaddr = phys->vaddr; | |
272 | #ifdef CONFIG_X86 | |
273 | set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE); | |
274 | #endif | |
275 | mapping = file_inode(obj->base.filp)->i_mapping; | |
276 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
277 | struct page *page; | |
278 | char *src; | |
279 | ||
280 | page = shmem_read_mapping_page(mapping, i); | |
281 | if (IS_ERR(page)) { | |
282 | #ifdef CONFIG_X86 | |
283 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); | |
284 | #endif | |
285 | drm_pci_free(obj->base.dev, phys); | |
286 | return PTR_ERR(page); | |
287 | } | |
288 | ||
289 | src = kmap_atomic(page); | |
290 | memcpy(vaddr, src, PAGE_SIZE); | |
291 | kunmap_atomic(src); | |
292 | ||
293 | mark_page_accessed(page); | |
294 | page_cache_release(page); | |
295 | ||
296 | vaddr += PAGE_SIZE; | |
297 | } | |
298 | ||
299 | obj->phys_handle = phys; | |
300 | return 0; | |
301 | } | |
302 | ||
303 | static int | |
304 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
305 | struct drm_i915_gem_pwrite *args, | |
306 | struct drm_file *file_priv) | |
307 | { | |
308 | struct drm_device *dev = obj->base.dev; | |
309 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
310 | char __user *user_data = to_user_ptr(args->data_ptr); | |
311 | ||
312 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
313 | unsigned long unwritten; | |
314 | ||
315 | /* The physical object once assigned is fixed for the lifetime | |
316 | * of the obj, so we can safely drop the lock and continue | |
317 | * to access vaddr. | |
318 | */ | |
319 | mutex_unlock(&dev->struct_mutex); | |
320 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
321 | mutex_lock(&dev->struct_mutex); | |
322 | if (unwritten) | |
323 | return -EFAULT; | |
324 | } | |
325 | ||
326 | i915_gem_chipset_flush(dev); | |
327 | return 0; | |
328 | } | |
329 | ||
42dcedd4 CW |
330 | void *i915_gem_object_alloc(struct drm_device *dev) |
331 | { | |
332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 333 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
334 | } |
335 | ||
336 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
337 | { | |
338 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
339 | kmem_cache_free(dev_priv->slab, obj); | |
340 | } | |
341 | ||
ff72145b DA |
342 | static int |
343 | i915_gem_create(struct drm_file *file, | |
344 | struct drm_device *dev, | |
345 | uint64_t size, | |
346 | uint32_t *handle_p) | |
673a394b | 347 | { |
05394f39 | 348 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
349 | int ret; |
350 | u32 handle; | |
673a394b | 351 | |
ff72145b | 352 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
353 | if (size == 0) |
354 | return -EINVAL; | |
673a394b EA |
355 | |
356 | /* Allocate the new object */ | |
ff72145b | 357 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
358 | if (obj == NULL) |
359 | return -ENOMEM; | |
360 | ||
05394f39 | 361 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 362 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
363 | drm_gem_object_unreference_unlocked(&obj->base); |
364 | if (ret) | |
365 | return ret; | |
202f2fef | 366 | |
ff72145b | 367 | *handle_p = handle; |
673a394b EA |
368 | return 0; |
369 | } | |
370 | ||
ff72145b DA |
371 | int |
372 | i915_gem_dumb_create(struct drm_file *file, | |
373 | struct drm_device *dev, | |
374 | struct drm_mode_create_dumb *args) | |
375 | { | |
376 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 377 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
378 | args->size = args->pitch * args->height; |
379 | return i915_gem_create(file, dev, | |
380 | args->size, &args->handle); | |
381 | } | |
382 | ||
ff72145b DA |
383 | /** |
384 | * Creates a new mm object and returns a handle to it. | |
385 | */ | |
386 | int | |
387 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
388 | struct drm_file *file) | |
389 | { | |
390 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 391 | |
ff72145b DA |
392 | return i915_gem_create(file, dev, |
393 | args->size, &args->handle); | |
394 | } | |
395 | ||
8461d226 DV |
396 | static inline int |
397 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
398 | const char *gpu_vaddr, int gpu_offset, | |
399 | int length) | |
400 | { | |
401 | int ret, cpu_offset = 0; | |
402 | ||
403 | while (length > 0) { | |
404 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
405 | int this_length = min(cacheline_end - gpu_offset, length); | |
406 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
407 | ||
408 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
409 | gpu_vaddr + swizzled_gpu_offset, | |
410 | this_length); | |
411 | if (ret) | |
412 | return ret + length; | |
413 | ||
414 | cpu_offset += this_length; | |
415 | gpu_offset += this_length; | |
416 | length -= this_length; | |
417 | } | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
8c59967c | 422 | static inline int |
4f0c7cfb BW |
423 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
424 | const char __user *cpu_vaddr, | |
8c59967c DV |
425 | int length) |
426 | { | |
427 | int ret, cpu_offset = 0; | |
428 | ||
429 | while (length > 0) { | |
430 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
431 | int this_length = min(cacheline_end - gpu_offset, length); | |
432 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
433 | ||
434 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
435 | cpu_vaddr + cpu_offset, | |
436 | this_length); | |
437 | if (ret) | |
438 | return ret + length; | |
439 | ||
440 | cpu_offset += this_length; | |
441 | gpu_offset += this_length; | |
442 | length -= this_length; | |
443 | } | |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
4c914c0c BV |
448 | /* |
449 | * Pins the specified object's pages and synchronizes the object with | |
450 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
451 | * flush the object from the CPU cache. | |
452 | */ | |
453 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
454 | int *needs_clflush) | |
455 | { | |
456 | int ret; | |
457 | ||
458 | *needs_clflush = 0; | |
459 | ||
460 | if (!obj->base.filp) | |
461 | return -EINVAL; | |
462 | ||
463 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
464 | /* If we're not in the cpu read domain, set ourself into the gtt | |
465 | * read domain and manually flush cachelines (if required). This | |
466 | * optimizes for the case when the gpu will dirty the data | |
467 | * anyway again before the next pread happens. */ | |
468 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
469 | obj->cache_level); | |
470 | ret = i915_gem_object_wait_rendering(obj, true); | |
471 | if (ret) | |
472 | return ret; | |
473 | } | |
474 | ||
475 | ret = i915_gem_object_get_pages(obj); | |
476 | if (ret) | |
477 | return ret; | |
478 | ||
479 | i915_gem_object_pin_pages(obj); | |
480 | ||
481 | return ret; | |
482 | } | |
483 | ||
d174bd64 DV |
484 | /* Per-page copy function for the shmem pread fastpath. |
485 | * Flushes invalid cachelines before reading the target if | |
486 | * needs_clflush is set. */ | |
eb01459f | 487 | static int |
d174bd64 DV |
488 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
489 | char __user *user_data, | |
490 | bool page_do_bit17_swizzling, bool needs_clflush) | |
491 | { | |
492 | char *vaddr; | |
493 | int ret; | |
494 | ||
e7e58eb5 | 495 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
496 | return -EINVAL; |
497 | ||
498 | vaddr = kmap_atomic(page); | |
499 | if (needs_clflush) | |
500 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
501 | page_length); | |
502 | ret = __copy_to_user_inatomic(user_data, | |
503 | vaddr + shmem_page_offset, | |
504 | page_length); | |
505 | kunmap_atomic(vaddr); | |
506 | ||
f60d7f0c | 507 | return ret ? -EFAULT : 0; |
d174bd64 DV |
508 | } |
509 | ||
23c18c71 DV |
510 | static void |
511 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
512 | bool swizzled) | |
513 | { | |
e7e58eb5 | 514 | if (unlikely(swizzled)) { |
23c18c71 DV |
515 | unsigned long start = (unsigned long) addr; |
516 | unsigned long end = (unsigned long) addr + length; | |
517 | ||
518 | /* For swizzling simply ensure that we always flush both | |
519 | * channels. Lame, but simple and it works. Swizzled | |
520 | * pwrite/pread is far from a hotpath - current userspace | |
521 | * doesn't use it at all. */ | |
522 | start = round_down(start, 128); | |
523 | end = round_up(end, 128); | |
524 | ||
525 | drm_clflush_virt_range((void *)start, end - start); | |
526 | } else { | |
527 | drm_clflush_virt_range(addr, length); | |
528 | } | |
529 | ||
530 | } | |
531 | ||
d174bd64 DV |
532 | /* Only difference to the fast-path function is that this can handle bit17 |
533 | * and uses non-atomic copy and kmap functions. */ | |
534 | static int | |
535 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
536 | char __user *user_data, | |
537 | bool page_do_bit17_swizzling, bool needs_clflush) | |
538 | { | |
539 | char *vaddr; | |
540 | int ret; | |
541 | ||
542 | vaddr = kmap(page); | |
543 | if (needs_clflush) | |
23c18c71 DV |
544 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
545 | page_length, | |
546 | page_do_bit17_swizzling); | |
d174bd64 DV |
547 | |
548 | if (page_do_bit17_swizzling) | |
549 | ret = __copy_to_user_swizzled(user_data, | |
550 | vaddr, shmem_page_offset, | |
551 | page_length); | |
552 | else | |
553 | ret = __copy_to_user(user_data, | |
554 | vaddr + shmem_page_offset, | |
555 | page_length); | |
556 | kunmap(page); | |
557 | ||
f60d7f0c | 558 | return ret ? - EFAULT : 0; |
d174bd64 DV |
559 | } |
560 | ||
eb01459f | 561 | static int |
dbf7bff0 DV |
562 | i915_gem_shmem_pread(struct drm_device *dev, |
563 | struct drm_i915_gem_object *obj, | |
564 | struct drm_i915_gem_pread *args, | |
565 | struct drm_file *file) | |
eb01459f | 566 | { |
8461d226 | 567 | char __user *user_data; |
eb01459f | 568 | ssize_t remain; |
8461d226 | 569 | loff_t offset; |
eb2c0c81 | 570 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 571 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 572 | int prefaulted = 0; |
8489731c | 573 | int needs_clflush = 0; |
67d5a50c | 574 | struct sg_page_iter sg_iter; |
eb01459f | 575 | |
2bb4629a | 576 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
577 | remain = args->size; |
578 | ||
8461d226 | 579 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 580 | |
4c914c0c | 581 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
582 | if (ret) |
583 | return ret; | |
584 | ||
8461d226 | 585 | offset = args->offset; |
eb01459f | 586 | |
67d5a50c ID |
587 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
588 | offset >> PAGE_SHIFT) { | |
2db76d7c | 589 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
590 | |
591 | if (remain <= 0) | |
592 | break; | |
593 | ||
eb01459f EA |
594 | /* Operation in this page |
595 | * | |
eb01459f | 596 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
597 | * page_length = bytes to copy for this page |
598 | */ | |
c8cbbb8b | 599 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
600 | page_length = remain; |
601 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
602 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 603 | |
8461d226 DV |
604 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
605 | (page_to_phys(page) & (1 << 17)) != 0; | |
606 | ||
d174bd64 DV |
607 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
608 | user_data, page_do_bit17_swizzling, | |
609 | needs_clflush); | |
610 | if (ret == 0) | |
611 | goto next_page; | |
dbf7bff0 | 612 | |
dbf7bff0 DV |
613 | mutex_unlock(&dev->struct_mutex); |
614 | ||
d330a953 | 615 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 616 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
617 | /* Userspace is tricking us, but we've already clobbered |
618 | * its pages with the prefault and promised to write the | |
619 | * data up to the first fault. Hence ignore any errors | |
620 | * and just continue. */ | |
621 | (void)ret; | |
622 | prefaulted = 1; | |
623 | } | |
eb01459f | 624 | |
d174bd64 DV |
625 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
626 | user_data, page_do_bit17_swizzling, | |
627 | needs_clflush); | |
eb01459f | 628 | |
dbf7bff0 | 629 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 630 | |
f60d7f0c | 631 | if (ret) |
8461d226 | 632 | goto out; |
8461d226 | 633 | |
17793c9a | 634 | next_page: |
eb01459f | 635 | remain -= page_length; |
8461d226 | 636 | user_data += page_length; |
eb01459f EA |
637 | offset += page_length; |
638 | } | |
639 | ||
4f27b75d | 640 | out: |
f60d7f0c CW |
641 | i915_gem_object_unpin_pages(obj); |
642 | ||
eb01459f EA |
643 | return ret; |
644 | } | |
645 | ||
673a394b EA |
646 | /** |
647 | * Reads data from the object referenced by handle. | |
648 | * | |
649 | * On error, the contents of *data are undefined. | |
650 | */ | |
651 | int | |
652 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 653 | struct drm_file *file) |
673a394b EA |
654 | { |
655 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 656 | struct drm_i915_gem_object *obj; |
35b62a89 | 657 | int ret = 0; |
673a394b | 658 | |
51311d0a CW |
659 | if (args->size == 0) |
660 | return 0; | |
661 | ||
662 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 663 | to_user_ptr(args->data_ptr), |
51311d0a CW |
664 | args->size)) |
665 | return -EFAULT; | |
666 | ||
4f27b75d | 667 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 668 | if (ret) |
4f27b75d | 669 | return ret; |
673a394b | 670 | |
05394f39 | 671 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 672 | if (&obj->base == NULL) { |
1d7cfea1 CW |
673 | ret = -ENOENT; |
674 | goto unlock; | |
4f27b75d | 675 | } |
673a394b | 676 | |
7dcd2499 | 677 | /* Bounds check source. */ |
05394f39 CW |
678 | if (args->offset > obj->base.size || |
679 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 680 | ret = -EINVAL; |
35b62a89 | 681 | goto out; |
ce9d419d CW |
682 | } |
683 | ||
1286ff73 DV |
684 | /* prime objects have no backing filp to GEM pread/pwrite |
685 | * pages from. | |
686 | */ | |
687 | if (!obj->base.filp) { | |
688 | ret = -EINVAL; | |
689 | goto out; | |
690 | } | |
691 | ||
db53a302 CW |
692 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
693 | ||
dbf7bff0 | 694 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 695 | |
35b62a89 | 696 | out: |
05394f39 | 697 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 698 | unlock: |
4f27b75d | 699 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 700 | return ret; |
673a394b EA |
701 | } |
702 | ||
0839ccb8 KP |
703 | /* This is the fast write path which cannot handle |
704 | * page faults in the source data | |
9b7530cc | 705 | */ |
0839ccb8 KP |
706 | |
707 | static inline int | |
708 | fast_user_write(struct io_mapping *mapping, | |
709 | loff_t page_base, int page_offset, | |
710 | char __user *user_data, | |
711 | int length) | |
9b7530cc | 712 | { |
4f0c7cfb BW |
713 | void __iomem *vaddr_atomic; |
714 | void *vaddr; | |
0839ccb8 | 715 | unsigned long unwritten; |
9b7530cc | 716 | |
3e4d3af5 | 717 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
718 | /* We can use the cpu mem copy function because this is X86. */ |
719 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
720 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 721 | user_data, length); |
3e4d3af5 | 722 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 723 | return unwritten; |
0839ccb8 KP |
724 | } |
725 | ||
3de09aa3 EA |
726 | /** |
727 | * This is the fast pwrite path, where we copy the data directly from the | |
728 | * user into the GTT, uncached. | |
729 | */ | |
673a394b | 730 | static int |
05394f39 CW |
731 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
732 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 733 | struct drm_i915_gem_pwrite *args, |
05394f39 | 734 | struct drm_file *file) |
673a394b | 735 | { |
3e31c6c0 | 736 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 737 | ssize_t remain; |
0839ccb8 | 738 | loff_t offset, page_base; |
673a394b | 739 | char __user *user_data; |
935aaa69 DV |
740 | int page_offset, page_length, ret; |
741 | ||
1ec9e26d | 742 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
743 | if (ret) |
744 | goto out; | |
745 | ||
746 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
747 | if (ret) | |
748 | goto out_unpin; | |
749 | ||
750 | ret = i915_gem_object_put_fence(obj); | |
751 | if (ret) | |
752 | goto out_unpin; | |
673a394b | 753 | |
2bb4629a | 754 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 755 | remain = args->size; |
673a394b | 756 | |
f343c5f6 | 757 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
758 | |
759 | while (remain > 0) { | |
760 | /* Operation in this page | |
761 | * | |
0839ccb8 KP |
762 | * page_base = page offset within aperture |
763 | * page_offset = offset within page | |
764 | * page_length = bytes to copy for this page | |
673a394b | 765 | */ |
c8cbbb8b CW |
766 | page_base = offset & PAGE_MASK; |
767 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
768 | page_length = remain; |
769 | if ((page_offset + remain) > PAGE_SIZE) | |
770 | page_length = PAGE_SIZE - page_offset; | |
771 | ||
0839ccb8 | 772 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
773 | * source page isn't available. Return the error and we'll |
774 | * retry in the slow path. | |
0839ccb8 | 775 | */ |
5d4545ae | 776 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
777 | page_offset, user_data, page_length)) { |
778 | ret = -EFAULT; | |
779 | goto out_unpin; | |
780 | } | |
673a394b | 781 | |
0839ccb8 KP |
782 | remain -= page_length; |
783 | user_data += page_length; | |
784 | offset += page_length; | |
673a394b | 785 | } |
673a394b | 786 | |
935aaa69 | 787 | out_unpin: |
d7f46fc4 | 788 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 789 | out: |
3de09aa3 | 790 | return ret; |
673a394b EA |
791 | } |
792 | ||
d174bd64 DV |
793 | /* Per-page copy function for the shmem pwrite fastpath. |
794 | * Flushes invalid cachelines before writing to the target if | |
795 | * needs_clflush_before is set and flushes out any written cachelines after | |
796 | * writing if needs_clflush is set. */ | |
3043c60c | 797 | static int |
d174bd64 DV |
798 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
799 | char __user *user_data, | |
800 | bool page_do_bit17_swizzling, | |
801 | bool needs_clflush_before, | |
802 | bool needs_clflush_after) | |
673a394b | 803 | { |
d174bd64 | 804 | char *vaddr; |
673a394b | 805 | int ret; |
3de09aa3 | 806 | |
e7e58eb5 | 807 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 808 | return -EINVAL; |
3de09aa3 | 809 | |
d174bd64 DV |
810 | vaddr = kmap_atomic(page); |
811 | if (needs_clflush_before) | |
812 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
813 | page_length); | |
c2831a94 CW |
814 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
815 | user_data, page_length); | |
d174bd64 DV |
816 | if (needs_clflush_after) |
817 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
818 | page_length); | |
819 | kunmap_atomic(vaddr); | |
3de09aa3 | 820 | |
755d2218 | 821 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
822 | } |
823 | ||
d174bd64 DV |
824 | /* Only difference to the fast-path function is that this can handle bit17 |
825 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 826 | static int |
d174bd64 DV |
827 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
828 | char __user *user_data, | |
829 | bool page_do_bit17_swizzling, | |
830 | bool needs_clflush_before, | |
831 | bool needs_clflush_after) | |
673a394b | 832 | { |
d174bd64 DV |
833 | char *vaddr; |
834 | int ret; | |
e5281ccd | 835 | |
d174bd64 | 836 | vaddr = kmap(page); |
e7e58eb5 | 837 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
838 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
839 | page_length, | |
840 | page_do_bit17_swizzling); | |
d174bd64 DV |
841 | if (page_do_bit17_swizzling) |
842 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
843 | user_data, |
844 | page_length); | |
d174bd64 DV |
845 | else |
846 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
847 | user_data, | |
848 | page_length); | |
849 | if (needs_clflush_after) | |
23c18c71 DV |
850 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
851 | page_length, | |
852 | page_do_bit17_swizzling); | |
d174bd64 | 853 | kunmap(page); |
40123c1f | 854 | |
755d2218 | 855 | return ret ? -EFAULT : 0; |
40123c1f EA |
856 | } |
857 | ||
40123c1f | 858 | static int |
e244a443 DV |
859 | i915_gem_shmem_pwrite(struct drm_device *dev, |
860 | struct drm_i915_gem_object *obj, | |
861 | struct drm_i915_gem_pwrite *args, | |
862 | struct drm_file *file) | |
40123c1f | 863 | { |
40123c1f | 864 | ssize_t remain; |
8c59967c DV |
865 | loff_t offset; |
866 | char __user *user_data; | |
eb2c0c81 | 867 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 868 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 869 | int hit_slowpath = 0; |
58642885 DV |
870 | int needs_clflush_after = 0; |
871 | int needs_clflush_before = 0; | |
67d5a50c | 872 | struct sg_page_iter sg_iter; |
40123c1f | 873 | |
2bb4629a | 874 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
875 | remain = args->size; |
876 | ||
8c59967c | 877 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 878 | |
58642885 DV |
879 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
880 | /* If we're not in the cpu write domain, set ourself into the gtt | |
881 | * write domain and manually flush cachelines (if required). This | |
882 | * optimizes for the case when the gpu will use the data | |
883 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 884 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
885 | ret = i915_gem_object_wait_rendering(obj, false); |
886 | if (ret) | |
887 | return ret; | |
58642885 | 888 | } |
c76ce038 CW |
889 | /* Same trick applies to invalidate partially written cachelines read |
890 | * before writing. */ | |
891 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
892 | needs_clflush_before = | |
893 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 894 | |
755d2218 CW |
895 | ret = i915_gem_object_get_pages(obj); |
896 | if (ret) | |
897 | return ret; | |
898 | ||
899 | i915_gem_object_pin_pages(obj); | |
900 | ||
673a394b | 901 | offset = args->offset; |
05394f39 | 902 | obj->dirty = 1; |
673a394b | 903 | |
67d5a50c ID |
904 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
905 | offset >> PAGE_SHIFT) { | |
2db76d7c | 906 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 907 | int partial_cacheline_write; |
e5281ccd | 908 | |
9da3da66 CW |
909 | if (remain <= 0) |
910 | break; | |
911 | ||
40123c1f EA |
912 | /* Operation in this page |
913 | * | |
40123c1f | 914 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
915 | * page_length = bytes to copy for this page |
916 | */ | |
c8cbbb8b | 917 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
918 | |
919 | page_length = remain; | |
920 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
921 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 922 | |
58642885 DV |
923 | /* If we don't overwrite a cacheline completely we need to be |
924 | * careful to have up-to-date data by first clflushing. Don't | |
925 | * overcomplicate things and flush the entire patch. */ | |
926 | partial_cacheline_write = needs_clflush_before && | |
927 | ((shmem_page_offset | page_length) | |
928 | & (boot_cpu_data.x86_clflush_size - 1)); | |
929 | ||
8c59967c DV |
930 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
931 | (page_to_phys(page) & (1 << 17)) != 0; | |
932 | ||
d174bd64 DV |
933 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
934 | user_data, page_do_bit17_swizzling, | |
935 | partial_cacheline_write, | |
936 | needs_clflush_after); | |
937 | if (ret == 0) | |
938 | goto next_page; | |
e244a443 DV |
939 | |
940 | hit_slowpath = 1; | |
e244a443 | 941 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
942 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
943 | user_data, page_do_bit17_swizzling, | |
944 | partial_cacheline_write, | |
945 | needs_clflush_after); | |
40123c1f | 946 | |
e244a443 | 947 | mutex_lock(&dev->struct_mutex); |
755d2218 | 948 | |
755d2218 | 949 | if (ret) |
8c59967c | 950 | goto out; |
8c59967c | 951 | |
17793c9a | 952 | next_page: |
40123c1f | 953 | remain -= page_length; |
8c59967c | 954 | user_data += page_length; |
40123c1f | 955 | offset += page_length; |
673a394b EA |
956 | } |
957 | ||
fbd5a26d | 958 | out: |
755d2218 CW |
959 | i915_gem_object_unpin_pages(obj); |
960 | ||
e244a443 | 961 | if (hit_slowpath) { |
8dcf015e DV |
962 | /* |
963 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
964 | * cachelines in-line while writing and the object moved | |
965 | * out of the cpu write domain while we've dropped the lock. | |
966 | */ | |
967 | if (!needs_clflush_after && | |
968 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
969 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
970 | i915_gem_chipset_flush(dev); | |
e244a443 | 971 | } |
8c59967c | 972 | } |
673a394b | 973 | |
58642885 | 974 | if (needs_clflush_after) |
e76e9aeb | 975 | i915_gem_chipset_flush(dev); |
58642885 | 976 | |
40123c1f | 977 | return ret; |
673a394b EA |
978 | } |
979 | ||
980 | /** | |
981 | * Writes data to the object referenced by handle. | |
982 | * | |
983 | * On error, the contents of the buffer that were to be modified are undefined. | |
984 | */ | |
985 | int | |
986 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 987 | struct drm_file *file) |
673a394b EA |
988 | { |
989 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 990 | struct drm_i915_gem_object *obj; |
51311d0a CW |
991 | int ret; |
992 | ||
993 | if (args->size == 0) | |
994 | return 0; | |
995 | ||
996 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 997 | to_user_ptr(args->data_ptr), |
51311d0a CW |
998 | args->size)) |
999 | return -EFAULT; | |
1000 | ||
d330a953 | 1001 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1002 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1003 | args->size); | |
1004 | if (ret) | |
1005 | return -EFAULT; | |
1006 | } | |
673a394b | 1007 | |
fbd5a26d | 1008 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1009 | if (ret) |
fbd5a26d | 1010 | return ret; |
1d7cfea1 | 1011 | |
05394f39 | 1012 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1013 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1014 | ret = -ENOENT; |
1015 | goto unlock; | |
fbd5a26d | 1016 | } |
673a394b | 1017 | |
7dcd2499 | 1018 | /* Bounds check destination. */ |
05394f39 CW |
1019 | if (args->offset > obj->base.size || |
1020 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1021 | ret = -EINVAL; |
35b62a89 | 1022 | goto out; |
ce9d419d CW |
1023 | } |
1024 | ||
1286ff73 DV |
1025 | /* prime objects have no backing filp to GEM pread/pwrite |
1026 | * pages from. | |
1027 | */ | |
1028 | if (!obj->base.filp) { | |
1029 | ret = -EINVAL; | |
1030 | goto out; | |
1031 | } | |
1032 | ||
db53a302 CW |
1033 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1034 | ||
935aaa69 | 1035 | ret = -EFAULT; |
673a394b EA |
1036 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1037 | * it would end up going through the fenced access, and we'll get | |
1038 | * different detiling behavior between reading and writing. | |
1039 | * pread/pwrite currently are reading and writing from the CPU | |
1040 | * perspective, requiring manual detiling by the client. | |
1041 | */ | |
00731155 CW |
1042 | if (obj->phys_handle) { |
1043 | ret = i915_gem_phys_pwrite(obj, args, file); | |
5c0480f2 DV |
1044 | goto out; |
1045 | } | |
1046 | ||
2c22569b CW |
1047 | if (obj->tiling_mode == I915_TILING_NONE && |
1048 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1049 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1050 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1051 | /* Note that the gtt paths might fail with non-page-backed user |
1052 | * pointers (e.g. gtt mappings when moving data between | |
1053 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1054 | } |
673a394b | 1055 | |
86a1ee26 | 1056 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 1057 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 1058 | |
35b62a89 | 1059 | out: |
05394f39 | 1060 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1061 | unlock: |
fbd5a26d | 1062 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1063 | return ret; |
1064 | } | |
1065 | ||
b361237b | 1066 | int |
33196ded | 1067 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1068 | bool interruptible) |
1069 | { | |
1f83fee0 | 1070 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1071 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1072 | * -EIO unconditionally for these. */ | |
1073 | if (!interruptible) | |
1074 | return -EIO; | |
1075 | ||
1f83fee0 DV |
1076 | /* Recovery complete, but the reset failed ... */ |
1077 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1078 | return -EIO; |
1079 | ||
1080 | return -EAGAIN; | |
1081 | } | |
1082 | ||
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | /* | |
1087 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
1088 | * equal. | |
1089 | */ | |
1090 | static int | |
1091 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
1092 | { | |
1093 | int ret; | |
1094 | ||
1095 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
1096 | ||
1097 | ret = 0; | |
1823521d | 1098 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 1099 | ret = i915_add_request(ring, NULL); |
b361237b CW |
1100 | |
1101 | return ret; | |
1102 | } | |
1103 | ||
094f9a54 CW |
1104 | static void fake_irq(unsigned long data) |
1105 | { | |
1106 | wake_up_process((struct task_struct *)data); | |
1107 | } | |
1108 | ||
1109 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
1110 | struct intel_ring_buffer *ring) | |
1111 | { | |
1112 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1113 | } | |
1114 | ||
b29c19b6 CW |
1115 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1116 | { | |
1117 | if (file_priv == NULL) | |
1118 | return true; | |
1119 | ||
1120 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1121 | } | |
1122 | ||
b361237b CW |
1123 | /** |
1124 | * __wait_seqno - wait until execution of seqno has finished | |
1125 | * @ring: the ring expected to report seqno | |
1126 | * @seqno: duh! | |
f69061be | 1127 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
1128 | * @interruptible: do an interruptible wait (normally yes) |
1129 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1130 | * | |
f69061be DV |
1131 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1132 | * values have been read by the caller in an smp safe manner. Where read-side | |
1133 | * locks are involved, it is sufficient to read the reset_counter before | |
1134 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1135 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1136 | * inserted. | |
1137 | * | |
b361237b CW |
1138 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1139 | * errno with remaining time filled in timeout argument. | |
1140 | */ | |
1141 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 1142 | unsigned reset_counter, |
b29c19b6 CW |
1143 | bool interruptible, |
1144 | struct timespec *timeout, | |
1145 | struct drm_i915_file_private *file_priv) | |
b361237b | 1146 | { |
3d13ef2e | 1147 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1148 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1149 | const bool irq_test_in_progress = |
1150 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 CW |
1151 | struct timespec before, now; |
1152 | DEFINE_WAIT(wait); | |
47e9766d | 1153 | unsigned long timeout_expire; |
b361237b CW |
1154 | int ret; |
1155 | ||
5d584b2e | 1156 | WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n"); |
c67a470b | 1157 | |
b361237b CW |
1158 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1159 | return 0; | |
1160 | ||
47e9766d | 1161 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
b361237b | 1162 | |
3d13ef2e | 1163 | if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1164 | gen6_rps_boost(dev_priv); |
1165 | if (file_priv) | |
1166 | mod_delayed_work(dev_priv->wq, | |
1167 | &file_priv->mm.idle_work, | |
1168 | msecs_to_jiffies(100)); | |
1169 | } | |
1170 | ||
168c3f21 | 1171 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1172 | return -ENODEV; |
1173 | ||
094f9a54 CW |
1174 | /* Record current time in case interrupted by signal, or wedged */ |
1175 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1176 | getrawmonotonic(&before); |
094f9a54 CW |
1177 | for (;;) { |
1178 | struct timer_list timer; | |
b361237b | 1179 | |
094f9a54 CW |
1180 | prepare_to_wait(&ring->irq_queue, &wait, |
1181 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1182 | |
f69061be DV |
1183 | /* We need to check whether any gpu reset happened in between |
1184 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1185 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1186 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1187 | * is truely gone. */ | |
1188 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1189 | if (ret == 0) | |
1190 | ret = -EAGAIN; | |
1191 | break; | |
1192 | } | |
f69061be | 1193 | |
094f9a54 CW |
1194 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1195 | ret = 0; | |
1196 | break; | |
1197 | } | |
b361237b | 1198 | |
094f9a54 CW |
1199 | if (interruptible && signal_pending(current)) { |
1200 | ret = -ERESTARTSYS; | |
1201 | break; | |
1202 | } | |
1203 | ||
47e9766d | 1204 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1205 | ret = -ETIME; |
1206 | break; | |
1207 | } | |
1208 | ||
1209 | timer.function = NULL; | |
1210 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1211 | unsigned long expire; |
1212 | ||
094f9a54 | 1213 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1214 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1215 | mod_timer(&timer, expire); |
1216 | } | |
1217 | ||
5035c275 | 1218 | io_schedule(); |
094f9a54 | 1219 | |
094f9a54 CW |
1220 | if (timer.function) { |
1221 | del_singleshot_timer_sync(&timer); | |
1222 | destroy_timer_on_stack(&timer); | |
1223 | } | |
1224 | } | |
b361237b | 1225 | getrawmonotonic(&now); |
094f9a54 | 1226 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1227 | |
168c3f21 MK |
1228 | if (!irq_test_in_progress) |
1229 | ring->irq_put(ring); | |
094f9a54 CW |
1230 | |
1231 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1232 | |
1233 | if (timeout) { | |
1234 | struct timespec sleep_time = timespec_sub(now, before); | |
1235 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1236 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1237 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1238 | } |
1239 | ||
094f9a54 | 1240 | return ret; |
b361237b CW |
1241 | } |
1242 | ||
1243 | /** | |
1244 | * Waits for a sequence number to be signaled, and cleans up the | |
1245 | * request and object lists appropriately for that event. | |
1246 | */ | |
1247 | int | |
1248 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1249 | { | |
1250 | struct drm_device *dev = ring->dev; | |
1251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1252 | bool interruptible = dev_priv->mm.interruptible; | |
1253 | int ret; | |
1254 | ||
1255 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1256 | BUG_ON(seqno == 0); | |
1257 | ||
33196ded | 1258 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1259 | if (ret) |
1260 | return ret; | |
1261 | ||
1262 | ret = i915_gem_check_olr(ring, seqno); | |
1263 | if (ret) | |
1264 | return ret; | |
1265 | ||
f69061be DV |
1266 | return __wait_seqno(ring, seqno, |
1267 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1268 | interruptible, NULL, NULL); |
b361237b CW |
1269 | } |
1270 | ||
d26e3af8 CW |
1271 | static int |
1272 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1273 | struct intel_ring_buffer *ring) | |
1274 | { | |
1275 | i915_gem_retire_requests_ring(ring); | |
1276 | ||
1277 | /* Manually manage the write flush as we may have not yet | |
1278 | * retired the buffer. | |
1279 | * | |
1280 | * Note that the last_write_seqno is always the earlier of | |
1281 | * the two (read/write) seqno, so if we haved successfully waited, | |
1282 | * we know we have passed the last write. | |
1283 | */ | |
1284 | obj->last_write_seqno = 0; | |
1285 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
b361237b CW |
1290 | /** |
1291 | * Ensures that all rendering to the object has completed and the object is | |
1292 | * safe to unbind from the GTT or access from the CPU. | |
1293 | */ | |
1294 | static __must_check int | |
1295 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1296 | bool readonly) | |
1297 | { | |
1298 | struct intel_ring_buffer *ring = obj->ring; | |
1299 | u32 seqno; | |
1300 | int ret; | |
1301 | ||
1302 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1303 | if (seqno == 0) | |
1304 | return 0; | |
1305 | ||
1306 | ret = i915_wait_seqno(ring, seqno); | |
1307 | if (ret) | |
1308 | return ret; | |
1309 | ||
d26e3af8 | 1310 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1311 | } |
1312 | ||
3236f57a CW |
1313 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1314 | * as the object state may change during this call. | |
1315 | */ | |
1316 | static __must_check int | |
1317 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1318 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1319 | bool readonly) |
1320 | { | |
1321 | struct drm_device *dev = obj->base.dev; | |
1322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1323 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1324 | unsigned reset_counter; |
3236f57a CW |
1325 | u32 seqno; |
1326 | int ret; | |
1327 | ||
1328 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1329 | BUG_ON(!dev_priv->mm.interruptible); | |
1330 | ||
1331 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1332 | if (seqno == 0) | |
1333 | return 0; | |
1334 | ||
33196ded | 1335 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1336 | if (ret) |
1337 | return ret; | |
1338 | ||
1339 | ret = i915_gem_check_olr(ring, seqno); | |
1340 | if (ret) | |
1341 | return ret; | |
1342 | ||
f69061be | 1343 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1344 | mutex_unlock(&dev->struct_mutex); |
6e4930f6 | 1345 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
3236f57a | 1346 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1347 | if (ret) |
1348 | return ret; | |
3236f57a | 1349 | |
d26e3af8 | 1350 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1351 | } |
1352 | ||
673a394b | 1353 | /** |
2ef7eeaa EA |
1354 | * Called when user space prepares to use an object with the CPU, either |
1355 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1356 | */ |
1357 | int | |
1358 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1359 | struct drm_file *file) |
673a394b EA |
1360 | { |
1361 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1362 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1363 | uint32_t read_domains = args->read_domains; |
1364 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1365 | int ret; |
1366 | ||
2ef7eeaa | 1367 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1368 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1369 | return -EINVAL; |
1370 | ||
21d509e3 | 1371 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1372 | return -EINVAL; |
1373 | ||
1374 | /* Having something in the write domain implies it's in the read | |
1375 | * domain, and only that read domain. Enforce that in the request. | |
1376 | */ | |
1377 | if (write_domain != 0 && read_domains != write_domain) | |
1378 | return -EINVAL; | |
1379 | ||
76c1dec1 | 1380 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1381 | if (ret) |
76c1dec1 | 1382 | return ret; |
1d7cfea1 | 1383 | |
05394f39 | 1384 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1385 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1386 | ret = -ENOENT; |
1387 | goto unlock; | |
76c1dec1 | 1388 | } |
673a394b | 1389 | |
3236f57a CW |
1390 | /* Try to flush the object off the GPU without holding the lock. |
1391 | * We will repeat the flush holding the lock in the normal manner | |
1392 | * to catch cases where we are gazumped. | |
1393 | */ | |
6e4930f6 CW |
1394 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1395 | file->driver_priv, | |
1396 | !write_domain); | |
3236f57a CW |
1397 | if (ret) |
1398 | goto unref; | |
1399 | ||
2ef7eeaa EA |
1400 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1401 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1402 | |
1403 | /* Silently promote "you're not bound, there was nothing to do" | |
1404 | * to success, since the client was just asking us to | |
1405 | * make sure everything was done. | |
1406 | */ | |
1407 | if (ret == -EINVAL) | |
1408 | ret = 0; | |
2ef7eeaa | 1409 | } else { |
e47c68e9 | 1410 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1411 | } |
1412 | ||
3236f57a | 1413 | unref: |
05394f39 | 1414 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1415 | unlock: |
673a394b EA |
1416 | mutex_unlock(&dev->struct_mutex); |
1417 | return ret; | |
1418 | } | |
1419 | ||
1420 | /** | |
1421 | * Called when user space has done writes to this buffer | |
1422 | */ | |
1423 | int | |
1424 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1425 | struct drm_file *file) |
673a394b EA |
1426 | { |
1427 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1428 | struct drm_i915_gem_object *obj; |
673a394b EA |
1429 | int ret = 0; |
1430 | ||
76c1dec1 | 1431 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1432 | if (ret) |
76c1dec1 | 1433 | return ret; |
1d7cfea1 | 1434 | |
05394f39 | 1435 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1436 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1437 | ret = -ENOENT; |
1438 | goto unlock; | |
673a394b EA |
1439 | } |
1440 | ||
673a394b | 1441 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1442 | if (obj->pin_display) |
1443 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1444 | |
05394f39 | 1445 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1446 | unlock: |
673a394b EA |
1447 | mutex_unlock(&dev->struct_mutex); |
1448 | return ret; | |
1449 | } | |
1450 | ||
1451 | /** | |
1452 | * Maps the contents of an object, returning the address it is mapped | |
1453 | * into. | |
1454 | * | |
1455 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1456 | * imply a ref on the object itself. | |
1457 | */ | |
1458 | int | |
1459 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1460 | struct drm_file *file) |
673a394b EA |
1461 | { |
1462 | struct drm_i915_gem_mmap *args = data; | |
1463 | struct drm_gem_object *obj; | |
673a394b EA |
1464 | unsigned long addr; |
1465 | ||
05394f39 | 1466 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1467 | if (obj == NULL) |
bf79cb91 | 1468 | return -ENOENT; |
673a394b | 1469 | |
1286ff73 DV |
1470 | /* prime objects have no backing filp to GEM mmap |
1471 | * pages from. | |
1472 | */ | |
1473 | if (!obj->filp) { | |
1474 | drm_gem_object_unreference_unlocked(obj); | |
1475 | return -EINVAL; | |
1476 | } | |
1477 | ||
6be5ceb0 | 1478 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1479 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1480 | args->offset); | |
bc9025bd | 1481 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1482 | if (IS_ERR((void *)addr)) |
1483 | return addr; | |
1484 | ||
1485 | args->addr_ptr = (uint64_t) addr; | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
de151cf6 JB |
1490 | /** |
1491 | * i915_gem_fault - fault a page into the GTT | |
1492 | * vma: VMA in question | |
1493 | * vmf: fault info | |
1494 | * | |
1495 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1496 | * from userspace. The fault handler takes care of binding the object to | |
1497 | * the GTT (if needed), allocating and programming a fence register (again, | |
1498 | * only if needed based on whether the old reg is still valid or the object | |
1499 | * is tiled) and inserting a new PTE into the faulting process. | |
1500 | * | |
1501 | * Note that the faulting process may involve evicting existing objects | |
1502 | * from the GTT and/or fence registers to make room. So performance may | |
1503 | * suffer if the GTT working set is large or there are few fence registers | |
1504 | * left. | |
1505 | */ | |
1506 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1507 | { | |
05394f39 CW |
1508 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1509 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1510 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1511 | pgoff_t page_offset; |
1512 | unsigned long pfn; | |
1513 | int ret = 0; | |
0f973f27 | 1514 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1515 | |
f65c9168 PZ |
1516 | intel_runtime_pm_get(dev_priv); |
1517 | ||
de151cf6 JB |
1518 | /* We don't use vmf->pgoff since that has the fake offset */ |
1519 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1520 | PAGE_SHIFT; | |
1521 | ||
d9bc7e9f CW |
1522 | ret = i915_mutex_lock_interruptible(dev); |
1523 | if (ret) | |
1524 | goto out; | |
a00b10c3 | 1525 | |
db53a302 CW |
1526 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1527 | ||
6e4930f6 CW |
1528 | /* Try to flush the object off the GPU first without holding the lock. |
1529 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1530 | * repeat the flush holding the lock in the normal manner to catch cases | |
1531 | * where we are gazumped. | |
1532 | */ | |
1533 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1534 | if (ret) | |
1535 | goto unlock; | |
1536 | ||
eb119bd6 CW |
1537 | /* Access to snoopable pages through the GTT is incoherent. */ |
1538 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1539 | ret = -EINVAL; | |
1540 | goto unlock; | |
1541 | } | |
1542 | ||
d9bc7e9f | 1543 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1544 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1545 | if (ret) |
1546 | goto unlock; | |
4a684a41 | 1547 | |
c9839303 CW |
1548 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1549 | if (ret) | |
1550 | goto unpin; | |
74898d7e | 1551 | |
06d98131 | 1552 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1553 | if (ret) |
c9839303 | 1554 | goto unpin; |
7d1c4804 | 1555 | |
6299f992 CW |
1556 | obj->fault_mappable = true; |
1557 | ||
f343c5f6 BW |
1558 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1559 | pfn >>= PAGE_SHIFT; | |
1560 | pfn += page_offset; | |
de151cf6 JB |
1561 | |
1562 | /* Finally, remap it using the new GTT offset */ | |
1563 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 | 1564 | unpin: |
d7f46fc4 | 1565 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1566 | unlock: |
de151cf6 | 1567 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1568 | out: |
de151cf6 | 1569 | switch (ret) { |
d9bc7e9f | 1570 | case -EIO: |
a9340cca DV |
1571 | /* If this -EIO is due to a gpu hang, give the reset code a |
1572 | * chance to clean up the mess. Otherwise return the proper | |
1573 | * SIGBUS. */ | |
f65c9168 PZ |
1574 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
1575 | ret = VM_FAULT_SIGBUS; | |
1576 | break; | |
1577 | } | |
045e769a | 1578 | case -EAGAIN: |
571c608d DV |
1579 | /* |
1580 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1581 | * handler to reset everything when re-faulting in | |
1582 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1583 | */ |
c715089f CW |
1584 | case 0: |
1585 | case -ERESTARTSYS: | |
bed636ab | 1586 | case -EINTR: |
e79e0fe3 DR |
1587 | case -EBUSY: |
1588 | /* | |
1589 | * EBUSY is ok: this just means that another thread | |
1590 | * already did the job. | |
1591 | */ | |
f65c9168 PZ |
1592 | ret = VM_FAULT_NOPAGE; |
1593 | break; | |
de151cf6 | 1594 | case -ENOMEM: |
f65c9168 PZ |
1595 | ret = VM_FAULT_OOM; |
1596 | break; | |
a7c2e1aa | 1597 | case -ENOSPC: |
45d67817 | 1598 | case -EFAULT: |
f65c9168 PZ |
1599 | ret = VM_FAULT_SIGBUS; |
1600 | break; | |
de151cf6 | 1601 | default: |
a7c2e1aa | 1602 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1603 | ret = VM_FAULT_SIGBUS; |
1604 | break; | |
de151cf6 | 1605 | } |
f65c9168 PZ |
1606 | |
1607 | intel_runtime_pm_put(dev_priv); | |
1608 | return ret; | |
de151cf6 JB |
1609 | } |
1610 | ||
48018a57 PZ |
1611 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
1612 | { | |
1613 | struct i915_vma *vma; | |
1614 | ||
1615 | /* | |
1616 | * Only the global gtt is relevant for gtt memory mappings, so restrict | |
1617 | * list traversal to objects bound into the global address space. Note | |
1618 | * that the active list should be empty, but better safe than sorry. | |
1619 | */ | |
1620 | WARN_ON(!list_empty(&dev_priv->gtt.base.active_list)); | |
1621 | list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list) | |
1622 | i915_gem_release_mmap(vma->obj); | |
1623 | list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list) | |
1624 | i915_gem_release_mmap(vma->obj); | |
1625 | } | |
1626 | ||
901782b2 CW |
1627 | /** |
1628 | * i915_gem_release_mmap - remove physical page mappings | |
1629 | * @obj: obj in question | |
1630 | * | |
af901ca1 | 1631 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1632 | * relinquish ownership of the pages back to the system. |
1633 | * | |
1634 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1635 | * object through the GTT and then lose the fence register due to | |
1636 | * resource pressure. Similarly if the object has been moved out of the | |
1637 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1638 | * mapping will then trigger a page fault on the next user access, allowing | |
1639 | * fixup by i915_gem_fault(). | |
1640 | */ | |
d05ca301 | 1641 | void |
05394f39 | 1642 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1643 | { |
6299f992 CW |
1644 | if (!obj->fault_mappable) |
1645 | return; | |
901782b2 | 1646 | |
6796cb16 DH |
1647 | drm_vma_node_unmap(&obj->base.vma_node, |
1648 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1649 | obj->fault_mappable = false; |
901782b2 CW |
1650 | } |
1651 | ||
0fa87796 | 1652 | uint32_t |
e28f8711 | 1653 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1654 | { |
e28f8711 | 1655 | uint32_t gtt_size; |
92b88aeb CW |
1656 | |
1657 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1658 | tiling_mode == I915_TILING_NONE) |
1659 | return size; | |
92b88aeb CW |
1660 | |
1661 | /* Previous chips need a power-of-two fence region when tiling */ | |
1662 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1663 | gtt_size = 1024*1024; |
92b88aeb | 1664 | else |
e28f8711 | 1665 | gtt_size = 512*1024; |
92b88aeb | 1666 | |
e28f8711 CW |
1667 | while (gtt_size < size) |
1668 | gtt_size <<= 1; | |
92b88aeb | 1669 | |
e28f8711 | 1670 | return gtt_size; |
92b88aeb CW |
1671 | } |
1672 | ||
de151cf6 JB |
1673 | /** |
1674 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1675 | * @obj: object to check | |
1676 | * | |
1677 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1678 | * potential fence register mapping. |
de151cf6 | 1679 | */ |
d865110c ID |
1680 | uint32_t |
1681 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1682 | int tiling_mode, bool fenced) | |
de151cf6 | 1683 | { |
de151cf6 JB |
1684 | /* |
1685 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1686 | * if a fence register is needed for the object. | |
1687 | */ | |
d865110c | 1688 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1689 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1690 | return 4096; |
1691 | ||
a00b10c3 CW |
1692 | /* |
1693 | * Previous chips need to be aligned to the size of the smallest | |
1694 | * fence register that can contain the object. | |
1695 | */ | |
e28f8711 | 1696 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1697 | } |
1698 | ||
d8cb5086 CW |
1699 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1700 | { | |
1701 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1702 | int ret; | |
1703 | ||
0de23977 | 1704 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1705 | return 0; |
1706 | ||
da494d7c DV |
1707 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1708 | ||
d8cb5086 CW |
1709 | ret = drm_gem_create_mmap_offset(&obj->base); |
1710 | if (ret != -ENOSPC) | |
da494d7c | 1711 | goto out; |
d8cb5086 CW |
1712 | |
1713 | /* Badly fragmented mmap space? The only way we can recover | |
1714 | * space is by destroying unwanted objects. We can't randomly release | |
1715 | * mmap_offsets as userspace expects them to be persistent for the | |
1716 | * lifetime of the objects. The closest we can is to release the | |
1717 | * offsets on purgeable objects by truncating it and marking it purged, | |
1718 | * which prevents userspace from ever using that object again. | |
1719 | */ | |
1720 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1721 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1722 | if (ret != -ENOSPC) | |
da494d7c | 1723 | goto out; |
d8cb5086 CW |
1724 | |
1725 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1726 | ret = drm_gem_create_mmap_offset(&obj->base); |
1727 | out: | |
1728 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1729 | ||
1730 | return ret; | |
d8cb5086 CW |
1731 | } |
1732 | ||
1733 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1734 | { | |
d8cb5086 CW |
1735 | drm_gem_free_mmap_offset(&obj->base); |
1736 | } | |
1737 | ||
de151cf6 | 1738 | int |
ff72145b DA |
1739 | i915_gem_mmap_gtt(struct drm_file *file, |
1740 | struct drm_device *dev, | |
1741 | uint32_t handle, | |
1742 | uint64_t *offset) | |
de151cf6 | 1743 | { |
da761a6e | 1744 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1745 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1746 | int ret; |
1747 | ||
76c1dec1 | 1748 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1749 | if (ret) |
76c1dec1 | 1750 | return ret; |
de151cf6 | 1751 | |
ff72145b | 1752 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1753 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1754 | ret = -ENOENT; |
1755 | goto unlock; | |
1756 | } | |
de151cf6 | 1757 | |
5d4545ae | 1758 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1759 | ret = -E2BIG; |
ff56b0bc | 1760 | goto out; |
da761a6e CW |
1761 | } |
1762 | ||
05394f39 | 1763 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1764 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1765 | ret = -EFAULT; |
1d7cfea1 | 1766 | goto out; |
ab18282d CW |
1767 | } |
1768 | ||
d8cb5086 CW |
1769 | ret = i915_gem_object_create_mmap_offset(obj); |
1770 | if (ret) | |
1771 | goto out; | |
de151cf6 | 1772 | |
0de23977 | 1773 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1774 | |
1d7cfea1 | 1775 | out: |
05394f39 | 1776 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1777 | unlock: |
de151cf6 | 1778 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1779 | return ret; |
de151cf6 JB |
1780 | } |
1781 | ||
ff72145b DA |
1782 | /** |
1783 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1784 | * @dev: DRM device | |
1785 | * @data: GTT mapping ioctl data | |
1786 | * @file: GEM object info | |
1787 | * | |
1788 | * Simply returns the fake offset to userspace so it can mmap it. | |
1789 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1790 | * up so we can get faults in the handler above. | |
1791 | * | |
1792 | * The fault handler will take care of binding the object into the GTT | |
1793 | * (since it may have been evicted to make room for something), allocating | |
1794 | * a fence register, and mapping the appropriate aperture address into | |
1795 | * userspace. | |
1796 | */ | |
1797 | int | |
1798 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1799 | struct drm_file *file) | |
1800 | { | |
1801 | struct drm_i915_gem_mmap_gtt *args = data; | |
1802 | ||
ff72145b DA |
1803 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1804 | } | |
1805 | ||
225067ee DV |
1806 | /* Immediately discard the backing storage */ |
1807 | static void | |
1808 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1809 | { |
e5281ccd | 1810 | struct inode *inode; |
e5281ccd | 1811 | |
4d6294bf | 1812 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1813 | |
4d6294bf CW |
1814 | if (obj->base.filp == NULL) |
1815 | return; | |
e5281ccd | 1816 | |
225067ee DV |
1817 | /* Our goal here is to return as much of the memory as |
1818 | * is possible back to the system as we are called from OOM. | |
1819 | * To do this we must instruct the shmfs to drop all of its | |
1820 | * backing pages, *now*. | |
1821 | */ | |
496ad9aa | 1822 | inode = file_inode(obj->base.filp); |
225067ee | 1823 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1824 | |
225067ee DV |
1825 | obj->madv = __I915_MADV_PURGED; |
1826 | } | |
e5281ccd | 1827 | |
225067ee DV |
1828 | static inline int |
1829 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1830 | { | |
1831 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1832 | } |
1833 | ||
5cdf5881 | 1834 | static void |
05394f39 | 1835 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1836 | { |
90797e6d ID |
1837 | struct sg_page_iter sg_iter; |
1838 | int ret; | |
1286ff73 | 1839 | |
05394f39 | 1840 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1841 | |
6c085a72 CW |
1842 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1843 | if (ret) { | |
1844 | /* In the event of a disaster, abandon all caches and | |
1845 | * hope for the best. | |
1846 | */ | |
1847 | WARN_ON(ret != -EIO); | |
2c22569b | 1848 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1849 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1850 | } | |
1851 | ||
6dacfd2f | 1852 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1853 | i915_gem_object_save_bit_17_swizzle(obj); |
1854 | ||
05394f39 CW |
1855 | if (obj->madv == I915_MADV_DONTNEED) |
1856 | obj->dirty = 0; | |
3ef94daa | 1857 | |
90797e6d | 1858 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1859 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1860 | |
05394f39 | 1861 | if (obj->dirty) |
9da3da66 | 1862 | set_page_dirty(page); |
3ef94daa | 1863 | |
05394f39 | 1864 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1865 | mark_page_accessed(page); |
3ef94daa | 1866 | |
9da3da66 | 1867 | page_cache_release(page); |
3ef94daa | 1868 | } |
05394f39 | 1869 | obj->dirty = 0; |
673a394b | 1870 | |
9da3da66 CW |
1871 | sg_free_table(obj->pages); |
1872 | kfree(obj->pages); | |
37e680a1 | 1873 | } |
6c085a72 | 1874 | |
dd624afd | 1875 | int |
37e680a1 CW |
1876 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1877 | { | |
1878 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1879 | ||
2f745ad3 | 1880 | if (obj->pages == NULL) |
37e680a1 CW |
1881 | return 0; |
1882 | ||
a5570178 CW |
1883 | if (obj->pages_pin_count) |
1884 | return -EBUSY; | |
1885 | ||
9843877d | 1886 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1887 | |
a2165e31 CW |
1888 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1889 | * array, hence protect them from being reaped by removing them from gtt | |
1890 | * lists early. */ | |
35c20a60 | 1891 | list_del(&obj->global_list); |
a2165e31 | 1892 | |
37e680a1 | 1893 | ops->put_pages(obj); |
05394f39 | 1894 | obj->pages = NULL; |
37e680a1 | 1895 | |
6c085a72 CW |
1896 | if (i915_gem_object_is_purgeable(obj)) |
1897 | i915_gem_object_truncate(obj); | |
1898 | ||
1899 | return 0; | |
1900 | } | |
1901 | ||
d9973b43 | 1902 | static unsigned long |
93927ca5 DV |
1903 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1904 | bool purgeable_only) | |
6c085a72 | 1905 | { |
57094f82 | 1906 | struct list_head still_bound_list; |
6c085a72 | 1907 | struct drm_i915_gem_object *obj, *next; |
d9973b43 | 1908 | unsigned long count = 0; |
6c085a72 CW |
1909 | |
1910 | list_for_each_entry_safe(obj, next, | |
1911 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1912 | global_list) { |
93927ca5 | 1913 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1914 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1915 | count += obj->base.size >> PAGE_SHIFT; |
1916 | if (count >= target) | |
1917 | return count; | |
1918 | } | |
1919 | } | |
1920 | ||
57094f82 CW |
1921 | /* |
1922 | * As we may completely rewrite the bound list whilst unbinding | |
1923 | * (due to retiring requests) we have to strictly process only | |
1924 | * one element of the list at the time, and recheck the list | |
1925 | * on every iteration. | |
1926 | */ | |
1927 | INIT_LIST_HEAD(&still_bound_list); | |
1928 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { | |
07fe0b12 | 1929 | struct i915_vma *vma, *v; |
80dcfdbd | 1930 | |
57094f82 CW |
1931 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1932 | typeof(*obj), global_list); | |
1933 | list_move_tail(&obj->global_list, &still_bound_list); | |
1934 | ||
80dcfdbd BW |
1935 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1936 | continue; | |
1937 | ||
57094f82 CW |
1938 | /* |
1939 | * Hold a reference whilst we unbind this object, as we may | |
1940 | * end up waiting for and retiring requests. This might | |
1941 | * release the final reference (held by the active list) | |
1942 | * and result in the object being freed from under us. | |
1943 | * in this object being freed. | |
1944 | * | |
1945 | * Note 1: Shrinking the bound list is special since only active | |
1946 | * (and hence bound objects) can contain such limbo objects, so | |
1947 | * we don't need special tricks for shrinking the unbound list. | |
1948 | * The only other place where we have to be careful with active | |
1949 | * objects suddenly disappearing due to retiring requests is the | |
1950 | * eviction code. | |
1951 | * | |
1952 | * Note 2: Even though the bound list doesn't hold a reference | |
1953 | * to the object we can safely grab one here: The final object | |
1954 | * unreferencing and the bound_list are both protected by the | |
1955 | * dev->struct_mutex and so we won't ever be able to observe an | |
1956 | * object on the bound_list with a reference count equals 0. | |
1957 | */ | |
1958 | drm_gem_object_reference(&obj->base); | |
1959 | ||
07fe0b12 BW |
1960 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1961 | if (i915_vma_unbind(vma)) | |
1962 | break; | |
80dcfdbd | 1963 | |
57094f82 | 1964 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1965 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1966 | |
1967 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1968 | } |
57094f82 | 1969 | list_splice(&still_bound_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1970 | |
1971 | return count; | |
1972 | } | |
1973 | ||
d9973b43 | 1974 | static unsigned long |
93927ca5 DV |
1975 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
1976 | { | |
1977 | return __i915_gem_shrink(dev_priv, target, true); | |
1978 | } | |
1979 | ||
d9973b43 | 1980 | static unsigned long |
6c085a72 CW |
1981 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
1982 | { | |
1983 | struct drm_i915_gem_object *obj, *next; | |
7dc19d5a | 1984 | long freed = 0; |
6c085a72 CW |
1985 | |
1986 | i915_gem_evict_everything(dev_priv->dev); | |
1987 | ||
35c20a60 | 1988 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
7dc19d5a | 1989 | global_list) { |
d9973b43 | 1990 | if (i915_gem_object_put_pages(obj) == 0) |
7dc19d5a | 1991 | freed += obj->base.size >> PAGE_SHIFT; |
7dc19d5a DC |
1992 | } |
1993 | return freed; | |
225067ee DV |
1994 | } |
1995 | ||
37e680a1 | 1996 | static int |
6c085a72 | 1997 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1998 | { |
6c085a72 | 1999 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2000 | int page_count, i; |
2001 | struct address_space *mapping; | |
9da3da66 CW |
2002 | struct sg_table *st; |
2003 | struct scatterlist *sg; | |
90797e6d | 2004 | struct sg_page_iter sg_iter; |
e5281ccd | 2005 | struct page *page; |
90797e6d | 2006 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2007 | gfp_t gfp; |
e5281ccd | 2008 | |
6c085a72 CW |
2009 | /* Assert that the object is not currently in any GPU domain. As it |
2010 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2011 | * a GPU cache | |
2012 | */ | |
2013 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2014 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2015 | ||
9da3da66 CW |
2016 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2017 | if (st == NULL) | |
2018 | return -ENOMEM; | |
2019 | ||
05394f39 | 2020 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2021 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2022 | kfree(st); |
e5281ccd | 2023 | return -ENOMEM; |
9da3da66 | 2024 | } |
e5281ccd | 2025 | |
9da3da66 CW |
2026 | /* Get the list of pages out of our struct file. They'll be pinned |
2027 | * at this point until we release them. | |
2028 | * | |
2029 | * Fail silently without starting the shrinker | |
2030 | */ | |
496ad9aa | 2031 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2032 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2033 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2034 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2035 | sg = st->sgl; |
2036 | st->nents = 0; | |
2037 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2038 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2039 | if (IS_ERR(page)) { | |
2040 | i915_gem_purge(dev_priv, page_count); | |
2041 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
2042 | } | |
2043 | if (IS_ERR(page)) { | |
2044 | /* We've tried hard to allocate the memory by reaping | |
2045 | * our own buffer, now let the real VM do its job and | |
2046 | * go down in flames if truly OOM. | |
2047 | */ | |
caf49191 | 2048 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
2049 | gfp |= __GFP_IO | __GFP_WAIT; |
2050 | ||
2051 | i915_gem_shrink_all(dev_priv); | |
2052 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
2053 | if (IS_ERR(page)) | |
2054 | goto err_pages; | |
2055 | ||
caf49191 | 2056 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
2057 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
2058 | } | |
426729dc KRW |
2059 | #ifdef CONFIG_SWIOTLB |
2060 | if (swiotlb_nr_tbl()) { | |
2061 | st->nents++; | |
2062 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2063 | sg = sg_next(sg); | |
2064 | continue; | |
2065 | } | |
2066 | #endif | |
90797e6d ID |
2067 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2068 | if (i) | |
2069 | sg = sg_next(sg); | |
2070 | st->nents++; | |
2071 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2072 | } else { | |
2073 | sg->length += PAGE_SIZE; | |
2074 | } | |
2075 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2076 | |
2077 | /* Check that the i965g/gm workaround works. */ | |
2078 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2079 | } |
426729dc KRW |
2080 | #ifdef CONFIG_SWIOTLB |
2081 | if (!swiotlb_nr_tbl()) | |
2082 | #endif | |
2083 | sg_mark_end(sg); | |
74ce6b6c CW |
2084 | obj->pages = st; |
2085 | ||
6dacfd2f | 2086 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2087 | i915_gem_object_do_bit_17_swizzle(obj); |
2088 | ||
2089 | return 0; | |
2090 | ||
2091 | err_pages: | |
90797e6d ID |
2092 | sg_mark_end(sg); |
2093 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2094 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2095 | sg_free_table(st); |
2096 | kfree(st); | |
e5281ccd | 2097 | return PTR_ERR(page); |
673a394b EA |
2098 | } |
2099 | ||
37e680a1 CW |
2100 | /* Ensure that the associated pages are gathered from the backing storage |
2101 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2102 | * multiple times before they are released by a single call to | |
2103 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2104 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2105 | * or as the object is itself released. | |
2106 | */ | |
2107 | int | |
2108 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2109 | { | |
2110 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2111 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2112 | int ret; | |
2113 | ||
2f745ad3 | 2114 | if (obj->pages) |
37e680a1 CW |
2115 | return 0; |
2116 | ||
43e28f09 | 2117 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2118 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2119 | return -EFAULT; |
43e28f09 CW |
2120 | } |
2121 | ||
a5570178 CW |
2122 | BUG_ON(obj->pages_pin_count); |
2123 | ||
37e680a1 CW |
2124 | ret = ops->get_pages(obj); |
2125 | if (ret) | |
2126 | return ret; | |
2127 | ||
35c20a60 | 2128 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2129 | return 0; |
673a394b EA |
2130 | } |
2131 | ||
e2d05a8b | 2132 | static void |
05394f39 | 2133 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 2134 | struct intel_ring_buffer *ring) |
673a394b | 2135 | { |
05394f39 | 2136 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 2137 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 2138 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 2139 | |
852835f3 | 2140 | BUG_ON(ring == NULL); |
02978ff5 CW |
2141 | if (obj->ring != ring && obj->last_write_seqno) { |
2142 | /* Keep the seqno relative to the current ring */ | |
2143 | obj->last_write_seqno = seqno; | |
2144 | } | |
05394f39 | 2145 | obj->ring = ring; |
673a394b EA |
2146 | |
2147 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2148 | if (!obj->active) { |
2149 | drm_gem_object_reference(&obj->base); | |
2150 | obj->active = 1; | |
673a394b | 2151 | } |
e35a41de | 2152 | |
05394f39 | 2153 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2154 | |
0201f1ec | 2155 | obj->last_read_seqno = seqno; |
caea7476 | 2156 | |
7dd49065 | 2157 | if (obj->fenced_gpu_access) { |
caea7476 | 2158 | obj->last_fenced_seqno = seqno; |
caea7476 | 2159 | |
7dd49065 CW |
2160 | /* Bump MRU to take account of the delayed flush */ |
2161 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2162 | struct drm_i915_fence_reg *reg; | |
2163 | ||
2164 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
2165 | list_move_tail(®->lru_list, | |
2166 | &dev_priv->mm.fence_list); | |
2167 | } | |
caea7476 CW |
2168 | } |
2169 | } | |
2170 | ||
e2d05a8b BW |
2171 | void i915_vma_move_to_active(struct i915_vma *vma, |
2172 | struct intel_ring_buffer *ring) | |
2173 | { | |
2174 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2175 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2176 | } | |
2177 | ||
caea7476 | 2178 | static void |
caea7476 | 2179 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2180 | { |
ca191b13 | 2181 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2182 | struct i915_address_space *vm; |
2183 | struct i915_vma *vma; | |
ce44b0ea | 2184 | |
65ce3027 | 2185 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2186 | BUG_ON(!obj->active); |
caea7476 | 2187 | |
feb822cf BW |
2188 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2189 | vma = i915_gem_obj_to_vma(obj, vm); | |
2190 | if (vma && !list_empty(&vma->mm_list)) | |
2191 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2192 | } | |
caea7476 | 2193 | |
65ce3027 | 2194 | list_del_init(&obj->ring_list); |
caea7476 CW |
2195 | obj->ring = NULL; |
2196 | ||
65ce3027 CW |
2197 | obj->last_read_seqno = 0; |
2198 | obj->last_write_seqno = 0; | |
2199 | obj->base.write_domain = 0; | |
2200 | ||
2201 | obj->last_fenced_seqno = 0; | |
caea7476 | 2202 | obj->fenced_gpu_access = false; |
caea7476 CW |
2203 | |
2204 | obj->active = 0; | |
2205 | drm_gem_object_unreference(&obj->base); | |
2206 | ||
2207 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2208 | } |
673a394b | 2209 | |
9d773091 | 2210 | static int |
fca26bb4 | 2211 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2212 | { |
9d773091 CW |
2213 | struct drm_i915_private *dev_priv = dev->dev_private; |
2214 | struct intel_ring_buffer *ring; | |
2215 | int ret, i, j; | |
53d227f2 | 2216 | |
107f27a5 | 2217 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2218 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2219 | ret = intel_ring_idle(ring); |
2220 | if (ret) | |
2221 | return ret; | |
9d773091 | 2222 | } |
9d773091 | 2223 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2224 | |
2225 | /* Finally reset hw state */ | |
9d773091 | 2226 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2227 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2228 | |
9d773091 CW |
2229 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
2230 | ring->sync_seqno[j] = 0; | |
2231 | } | |
53d227f2 | 2232 | |
9d773091 | 2233 | return 0; |
53d227f2 DV |
2234 | } |
2235 | ||
fca26bb4 MK |
2236 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2237 | { | |
2238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2239 | int ret; | |
2240 | ||
2241 | if (seqno == 0) | |
2242 | return -EINVAL; | |
2243 | ||
2244 | /* HWS page needs to be set less than what we | |
2245 | * will inject to ring | |
2246 | */ | |
2247 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2248 | if (ret) | |
2249 | return ret; | |
2250 | ||
2251 | /* Carefully set the last_seqno value so that wrap | |
2252 | * detection still works | |
2253 | */ | |
2254 | dev_priv->next_seqno = seqno; | |
2255 | dev_priv->last_seqno = seqno - 1; | |
2256 | if (dev_priv->last_seqno == 0) | |
2257 | dev_priv->last_seqno--; | |
2258 | ||
2259 | return 0; | |
2260 | } | |
2261 | ||
9d773091 CW |
2262 | int |
2263 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2264 | { |
9d773091 CW |
2265 | struct drm_i915_private *dev_priv = dev->dev_private; |
2266 | ||
2267 | /* reserve 0 for non-seqno */ | |
2268 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2269 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2270 | if (ret) |
2271 | return ret; | |
53d227f2 | 2272 | |
9d773091 CW |
2273 | dev_priv->next_seqno = 1; |
2274 | } | |
53d227f2 | 2275 | |
f72b3435 | 2276 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2277 | return 0; |
53d227f2 DV |
2278 | } |
2279 | ||
0025c077 MK |
2280 | int __i915_add_request(struct intel_ring_buffer *ring, |
2281 | struct drm_file *file, | |
7d736f4f | 2282 | struct drm_i915_gem_object *obj, |
0025c077 | 2283 | u32 *out_seqno) |
673a394b | 2284 | { |
3e31c6c0 | 2285 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2286 | struct drm_i915_gem_request *request; |
7d736f4f | 2287 | u32 request_ring_position, request_start; |
3cce469c CW |
2288 | int ret; |
2289 | ||
7d736f4f | 2290 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2291 | /* |
2292 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2293 | * after having emitted the batchbuffer command. Hence we need to fix | |
2294 | * things up similar to emitting the lazy request. The difference here | |
2295 | * is that the flush _must_ happen before the next request, no matter | |
2296 | * what. | |
2297 | */ | |
a7b9761d CW |
2298 | ret = intel_ring_flush_all_caches(ring); |
2299 | if (ret) | |
2300 | return ret; | |
cc889e0f | 2301 | |
3c0e234c CW |
2302 | request = ring->preallocated_lazy_request; |
2303 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2304 | return -ENOMEM; |
cc889e0f | 2305 | |
a71d8d94 CW |
2306 | /* Record the position of the start of the request so that |
2307 | * should we detect the updated seqno part-way through the | |
2308 | * GPU processing the request, we never over-estimate the | |
2309 | * position of the head. | |
2310 | */ | |
2311 | request_ring_position = intel_ring_get_tail(ring); | |
2312 | ||
9d773091 | 2313 | ret = ring->add_request(ring); |
3c0e234c | 2314 | if (ret) |
3bb73aba | 2315 | return ret; |
673a394b | 2316 | |
9d773091 | 2317 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2318 | request->ring = ring; |
7d736f4f | 2319 | request->head = request_start; |
a71d8d94 | 2320 | request->tail = request_ring_position; |
7d736f4f MK |
2321 | |
2322 | /* Whilst this request exists, batch_obj will be on the | |
2323 | * active_list, and so will hold the active reference. Only when this | |
2324 | * request is retired will the the batch_obj be moved onto the | |
2325 | * inactive_list and lose its active reference. Hence we do not need | |
2326 | * to explicitly hold another reference here. | |
2327 | */ | |
9a7e0c2a | 2328 | request->batch_obj = obj; |
0e50e96b | 2329 | |
9a7e0c2a CW |
2330 | /* Hold a reference to the current context so that we can inspect |
2331 | * it later in case a hangcheck error event fires. | |
2332 | */ | |
2333 | request->ctx = ring->last_context; | |
0e50e96b MK |
2334 | if (request->ctx) |
2335 | i915_gem_context_reference(request->ctx); | |
2336 | ||
673a394b | 2337 | request->emitted_jiffies = jiffies; |
852835f3 | 2338 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2339 | request->file_priv = NULL; |
852835f3 | 2340 | |
db53a302 CW |
2341 | if (file) { |
2342 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2343 | ||
1c25595f | 2344 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2345 | request->file_priv = file_priv; |
b962442e | 2346 | list_add_tail(&request->client_list, |
f787a5f5 | 2347 | &file_priv->mm.request_list); |
1c25595f | 2348 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2349 | } |
673a394b | 2350 | |
9d773091 | 2351 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2352 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2353 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2354 | |
db1b76ca | 2355 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2356 | i915_queue_hangcheck(ring->dev); |
2357 | ||
f62a0076 CW |
2358 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2359 | queue_delayed_work(dev_priv->wq, | |
2360 | &dev_priv->mm.retire_work, | |
2361 | round_jiffies_up_relative(HZ)); | |
2362 | intel_mark_busy(dev_priv->dev); | |
f65d9421 | 2363 | } |
cc889e0f | 2364 | |
acb868d3 | 2365 | if (out_seqno) |
9d773091 | 2366 | *out_seqno = request->seqno; |
3cce469c | 2367 | return 0; |
673a394b EA |
2368 | } |
2369 | ||
f787a5f5 CW |
2370 | static inline void |
2371 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2372 | { |
1c25595f | 2373 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2374 | |
1c25595f CW |
2375 | if (!file_priv) |
2376 | return; | |
1c5d22f7 | 2377 | |
1c25595f | 2378 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2379 | list_del(&request->client_list); |
2380 | request->file_priv = NULL; | |
1c25595f | 2381 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2382 | } |
673a394b | 2383 | |
939fd762 | 2384 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
44e2c070 | 2385 | const struct i915_hw_context *ctx) |
be62acb4 | 2386 | { |
44e2c070 | 2387 | unsigned long elapsed; |
be62acb4 | 2388 | |
44e2c070 MK |
2389 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2390 | ||
2391 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2392 | return true; |
2393 | ||
2394 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2395 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2396 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 VS |
2397 | return true; |
2398 | } else if (dev_priv->gpu_error.stop_rings == 0) { | |
2399 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
2400 | return true; | |
3fac8978 | 2401 | } |
be62acb4 MK |
2402 | } |
2403 | ||
2404 | return false; | |
2405 | } | |
2406 | ||
939fd762 MK |
2407 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
2408 | struct i915_hw_context *ctx, | |
b6b0fac0 | 2409 | const bool guilty) |
aa60c664 | 2410 | { |
44e2c070 MK |
2411 | struct i915_ctx_hang_stats *hs; |
2412 | ||
2413 | if (WARN_ON(!ctx)) | |
2414 | return; | |
aa60c664 | 2415 | |
44e2c070 MK |
2416 | hs = &ctx->hang_stats; |
2417 | ||
2418 | if (guilty) { | |
939fd762 | 2419 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2420 | hs->batch_active++; |
2421 | hs->guilty_ts = get_seconds(); | |
2422 | } else { | |
2423 | hs->batch_pending++; | |
aa60c664 MK |
2424 | } |
2425 | } | |
2426 | ||
0e50e96b MK |
2427 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2428 | { | |
2429 | list_del(&request->list); | |
2430 | i915_gem_request_remove_from_client(request); | |
2431 | ||
2432 | if (request->ctx) | |
2433 | i915_gem_context_unreference(request->ctx); | |
2434 | ||
2435 | kfree(request); | |
2436 | } | |
2437 | ||
8d9fc7fd CW |
2438 | struct drm_i915_gem_request * |
2439 | i915_gem_find_active_request(struct intel_ring_buffer *ring) | |
9375e446 | 2440 | { |
4db080f9 | 2441 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2442 | u32 completed_seqno; |
2443 | ||
2444 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2445 | |
2446 | list_for_each_entry(request, &ring->request_list, list) { | |
2447 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2448 | continue; | |
aa60c664 | 2449 | |
b6b0fac0 | 2450 | return request; |
4db080f9 | 2451 | } |
b6b0fac0 MK |
2452 | |
2453 | return NULL; | |
2454 | } | |
2455 | ||
2456 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
2457 | struct intel_ring_buffer *ring) | |
2458 | { | |
2459 | struct drm_i915_gem_request *request; | |
2460 | bool ring_hung; | |
2461 | ||
8d9fc7fd | 2462 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2463 | |
2464 | if (request == NULL) | |
2465 | return; | |
2466 | ||
2467 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2468 | ||
939fd762 | 2469 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2470 | |
2471 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2472 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2473 | } |
aa60c664 | 2474 | |
4db080f9 CW |
2475 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
2476 | struct intel_ring_buffer *ring) | |
2477 | { | |
dfaae392 | 2478 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2479 | struct drm_i915_gem_object *obj; |
9375e446 | 2480 | |
05394f39 CW |
2481 | obj = list_first_entry(&ring->active_list, |
2482 | struct drm_i915_gem_object, | |
2483 | ring_list); | |
9375e446 | 2484 | |
05394f39 | 2485 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2486 | } |
1d62beea BW |
2487 | |
2488 | /* | |
2489 | * We must free the requests after all the corresponding objects have | |
2490 | * been moved off active lists. Which is the same order as the normal | |
2491 | * retire_requests function does. This is important if object hold | |
2492 | * implicit references on things like e.g. ppgtt address spaces through | |
2493 | * the request. | |
2494 | */ | |
2495 | while (!list_empty(&ring->request_list)) { | |
2496 | struct drm_i915_gem_request *request; | |
2497 | ||
2498 | request = list_first_entry(&ring->request_list, | |
2499 | struct drm_i915_gem_request, | |
2500 | list); | |
2501 | ||
2502 | i915_gem_free_request(request); | |
2503 | } | |
673a394b EA |
2504 | } |
2505 | ||
19b2dbde | 2506 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2507 | { |
2508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2509 | int i; | |
2510 | ||
4b9de737 | 2511 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2512 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2513 | |
94a335db DV |
2514 | /* |
2515 | * Commit delayed tiling changes if we have an object still | |
2516 | * attached to the fence, otherwise just clear the fence. | |
2517 | */ | |
2518 | if (reg->obj) { | |
2519 | i915_gem_object_update_fence(reg->obj, reg, | |
2520 | reg->obj->tiling_mode); | |
2521 | } else { | |
2522 | i915_gem_write_fence(dev, i, NULL); | |
2523 | } | |
312817a3 CW |
2524 | } |
2525 | } | |
2526 | ||
069efc1d | 2527 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2528 | { |
77f01230 | 2529 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2530 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2531 | int i; |
673a394b | 2532 | |
4db080f9 CW |
2533 | /* |
2534 | * Before we free the objects from the requests, we need to inspect | |
2535 | * them for finding the guilty party. As the requests only borrow | |
2536 | * their reference to the objects, the inspection must be done first. | |
2537 | */ | |
2538 | for_each_ring(ring, dev_priv, i) | |
2539 | i915_gem_reset_ring_status(dev_priv, ring); | |
2540 | ||
b4519513 | 2541 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2542 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2543 | |
3d57e5bd BW |
2544 | i915_gem_cleanup_ringbuffer(dev); |
2545 | ||
acce9ffa BW |
2546 | i915_gem_context_reset(dev); |
2547 | ||
19b2dbde | 2548 | i915_gem_restore_fences(dev); |
673a394b EA |
2549 | } |
2550 | ||
2551 | /** | |
2552 | * This function clears the request list as sequence numbers are passed. | |
2553 | */ | |
cb216aa8 | 2554 | static void |
db53a302 | 2555 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2556 | { |
673a394b EA |
2557 | uint32_t seqno; |
2558 | ||
db53a302 | 2559 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2560 | return; |
2561 | ||
db53a302 | 2562 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2563 | |
b2eadbc8 | 2564 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2565 | |
e9103038 CW |
2566 | /* Move any buffers on the active list that are no longer referenced |
2567 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2568 | * before we free the context associated with the requests. | |
2569 | */ | |
2570 | while (!list_empty(&ring->active_list)) { | |
2571 | struct drm_i915_gem_object *obj; | |
2572 | ||
2573 | obj = list_first_entry(&ring->active_list, | |
2574 | struct drm_i915_gem_object, | |
2575 | ring_list); | |
2576 | ||
2577 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) | |
2578 | break; | |
2579 | ||
2580 | i915_gem_object_move_to_inactive(obj); | |
2581 | } | |
2582 | ||
2583 | ||
852835f3 | 2584 | while (!list_empty(&ring->request_list)) { |
673a394b | 2585 | struct drm_i915_gem_request *request; |
673a394b | 2586 | |
852835f3 | 2587 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2588 | struct drm_i915_gem_request, |
2589 | list); | |
673a394b | 2590 | |
dfaae392 | 2591 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2592 | break; |
2593 | ||
db53a302 | 2594 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2595 | /* We know the GPU must have read the request to have |
2596 | * sent us the seqno + interrupt, so use the position | |
2597 | * of tail of the request to update the last known position | |
2598 | * of the GPU head. | |
2599 | */ | |
2600 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2601 | |
0e50e96b | 2602 | i915_gem_free_request(request); |
b84d5f0c | 2603 | } |
673a394b | 2604 | |
db53a302 CW |
2605 | if (unlikely(ring->trace_irq_seqno && |
2606 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2607 | ring->irq_put(ring); |
db53a302 | 2608 | ring->trace_irq_seqno = 0; |
9d34e5db | 2609 | } |
23bc5982 | 2610 | |
db53a302 | 2611 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2612 | } |
2613 | ||
b29c19b6 | 2614 | bool |
b09a1fec CW |
2615 | i915_gem_retire_requests(struct drm_device *dev) |
2616 | { | |
3e31c6c0 | 2617 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2618 | struct intel_ring_buffer *ring; |
b29c19b6 | 2619 | bool idle = true; |
1ec14ad3 | 2620 | int i; |
b09a1fec | 2621 | |
b29c19b6 | 2622 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2623 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2624 | idle &= list_empty(&ring->request_list); |
2625 | } | |
2626 | ||
2627 | if (idle) | |
2628 | mod_delayed_work(dev_priv->wq, | |
2629 | &dev_priv->mm.idle_work, | |
2630 | msecs_to_jiffies(100)); | |
2631 | ||
2632 | return idle; | |
b09a1fec CW |
2633 | } |
2634 | ||
75ef9da2 | 2635 | static void |
673a394b EA |
2636 | i915_gem_retire_work_handler(struct work_struct *work) |
2637 | { | |
b29c19b6 CW |
2638 | struct drm_i915_private *dev_priv = |
2639 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2640 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2641 | bool idle; |
673a394b | 2642 | |
891b48cf | 2643 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2644 | idle = false; |
2645 | if (mutex_trylock(&dev->struct_mutex)) { | |
2646 | idle = i915_gem_retire_requests(dev); | |
2647 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2648 | } |
b29c19b6 | 2649 | if (!idle) |
bcb45086 CW |
2650 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2651 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2652 | } |
0a58705b | 2653 | |
b29c19b6 CW |
2654 | static void |
2655 | i915_gem_idle_work_handler(struct work_struct *work) | |
2656 | { | |
2657 | struct drm_i915_private *dev_priv = | |
2658 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2659 | ||
2660 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2661 | } |
2662 | ||
30dfebf3 DV |
2663 | /** |
2664 | * Ensures that an object will eventually get non-busy by flushing any required | |
2665 | * write domains, emitting any outstanding lazy request and retiring and | |
2666 | * completed requests. | |
2667 | */ | |
2668 | static int | |
2669 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2670 | { | |
2671 | int ret; | |
2672 | ||
2673 | if (obj->active) { | |
0201f1ec | 2674 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2675 | if (ret) |
2676 | return ret; | |
2677 | ||
30dfebf3 DV |
2678 | i915_gem_retire_requests_ring(obj->ring); |
2679 | } | |
2680 | ||
2681 | return 0; | |
2682 | } | |
2683 | ||
23ba4fd0 BW |
2684 | /** |
2685 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2686 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2687 | * | |
2688 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2689 | * the timeout parameter. | |
2690 | * -ETIME: object is still busy after timeout | |
2691 | * -ERESTARTSYS: signal interrupted the wait | |
2692 | * -ENONENT: object doesn't exist | |
2693 | * Also possible, but rare: | |
2694 | * -EAGAIN: GPU wedged | |
2695 | * -ENOMEM: damn | |
2696 | * -ENODEV: Internal IRQ fail | |
2697 | * -E?: The add request failed | |
2698 | * | |
2699 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2700 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2701 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2702 | * without holding struct_mutex the object may become re-busied before this | |
2703 | * function completes. A similar but shorter * race condition exists in the busy | |
2704 | * ioctl | |
2705 | */ | |
2706 | int | |
2707 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2708 | { | |
3e31c6c0 | 2709 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2710 | struct drm_i915_gem_wait *args = data; |
2711 | struct drm_i915_gem_object *obj; | |
2712 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2713 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2714 | unsigned reset_counter; |
23ba4fd0 BW |
2715 | u32 seqno = 0; |
2716 | int ret = 0; | |
2717 | ||
eac1f14f BW |
2718 | if (args->timeout_ns >= 0) { |
2719 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2720 | timeout = &timeout_stack; | |
2721 | } | |
23ba4fd0 BW |
2722 | |
2723 | ret = i915_mutex_lock_interruptible(dev); | |
2724 | if (ret) | |
2725 | return ret; | |
2726 | ||
2727 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2728 | if (&obj->base == NULL) { | |
2729 | mutex_unlock(&dev->struct_mutex); | |
2730 | return -ENOENT; | |
2731 | } | |
2732 | ||
30dfebf3 DV |
2733 | /* Need to make sure the object gets inactive eventually. */ |
2734 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2735 | if (ret) |
2736 | goto out; | |
2737 | ||
2738 | if (obj->active) { | |
0201f1ec | 2739 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2740 | ring = obj->ring; |
2741 | } | |
2742 | ||
2743 | if (seqno == 0) | |
2744 | goto out; | |
2745 | ||
23ba4fd0 BW |
2746 | /* Do this after OLR check to make sure we make forward progress polling |
2747 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2748 | */ | |
2749 | if (!args->timeout_ns) { | |
2750 | ret = -ETIME; | |
2751 | goto out; | |
2752 | } | |
2753 | ||
2754 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2755 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2756 | mutex_unlock(&dev->struct_mutex); |
2757 | ||
b29c19b6 | 2758 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2759 | if (timeout) |
eac1f14f | 2760 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2761 | return ret; |
2762 | ||
2763 | out: | |
2764 | drm_gem_object_unreference(&obj->base); | |
2765 | mutex_unlock(&dev->struct_mutex); | |
2766 | return ret; | |
2767 | } | |
2768 | ||
5816d648 BW |
2769 | /** |
2770 | * i915_gem_object_sync - sync an object to a ring. | |
2771 | * | |
2772 | * @obj: object which may be in use on another ring. | |
2773 | * @to: ring we wish to use the object on. May be NULL. | |
2774 | * | |
2775 | * This code is meant to abstract object synchronization with the GPU. | |
2776 | * Calling with NULL implies synchronizing the object with the CPU | |
2777 | * rather than a particular GPU ring. | |
2778 | * | |
2779 | * Returns 0 if successful, else propagates up the lower layer error. | |
2780 | */ | |
2911a35b BW |
2781 | int |
2782 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2783 | struct intel_ring_buffer *to) | |
2784 | { | |
2785 | struct intel_ring_buffer *from = obj->ring; | |
2786 | u32 seqno; | |
2787 | int ret, idx; | |
2788 | ||
2789 | if (from == NULL || to == from) | |
2790 | return 0; | |
2791 | ||
5816d648 | 2792 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2793 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2794 | |
2795 | idx = intel_ring_sync_index(from, to); | |
2796 | ||
0201f1ec | 2797 | seqno = obj->last_read_seqno; |
2911a35b BW |
2798 | if (seqno <= from->sync_seqno[idx]) |
2799 | return 0; | |
2800 | ||
b4aca010 BW |
2801 | ret = i915_gem_check_olr(obj->ring, seqno); |
2802 | if (ret) | |
2803 | return ret; | |
2911a35b | 2804 | |
b52b89da | 2805 | trace_i915_gem_ring_sync_to(from, to, seqno); |
1500f7ea | 2806 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2807 | if (!ret) |
7b01e260 MK |
2808 | /* We use last_read_seqno because sync_to() |
2809 | * might have just caused seqno wrap under | |
2810 | * the radar. | |
2811 | */ | |
2812 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2813 | |
e3a5a225 | 2814 | return ret; |
2911a35b BW |
2815 | } |
2816 | ||
b5ffc9bc CW |
2817 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2818 | { | |
2819 | u32 old_write_domain, old_read_domains; | |
2820 | ||
b5ffc9bc CW |
2821 | /* Force a pagefault for domain tracking on next user access */ |
2822 | i915_gem_release_mmap(obj); | |
2823 | ||
b97c3d9c KP |
2824 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2825 | return; | |
2826 | ||
97c809fd CW |
2827 | /* Wait for any direct GTT access to complete */ |
2828 | mb(); | |
2829 | ||
b5ffc9bc CW |
2830 | old_read_domains = obj->base.read_domains; |
2831 | old_write_domain = obj->base.write_domain; | |
2832 | ||
2833 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2834 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2835 | ||
2836 | trace_i915_gem_object_change_domain(obj, | |
2837 | old_read_domains, | |
2838 | old_write_domain); | |
2839 | } | |
2840 | ||
07fe0b12 | 2841 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2842 | { |
07fe0b12 | 2843 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 2844 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2845 | int ret; |
673a394b | 2846 | |
07fe0b12 | 2847 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2848 | return 0; |
2849 | ||
0ff501cb DV |
2850 | if (!drm_mm_node_allocated(&vma->node)) { |
2851 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
2852 | return 0; |
2853 | } | |
433544bd | 2854 | |
d7f46fc4 | 2855 | if (vma->pin_count) |
31d8d651 | 2856 | return -EBUSY; |
673a394b | 2857 | |
c4670ad0 CW |
2858 | BUG_ON(obj->pages == NULL); |
2859 | ||
a8198eea | 2860 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2861 | if (ret) |
a8198eea CW |
2862 | return ret; |
2863 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2864 | * should be safe and we need to cleanup or else we might | |
2865 | * cause memory corruption through use-after-free. | |
2866 | */ | |
2867 | ||
b5ffc9bc | 2868 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2869 | |
96b47b65 | 2870 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2871 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2872 | if (ret) |
d9e86c0e | 2873 | return ret; |
96b47b65 | 2874 | |
07fe0b12 | 2875 | trace_i915_vma_unbind(vma); |
db53a302 | 2876 | |
6f65e29a BW |
2877 | vma->unbind_vma(vma); |
2878 | ||
74163907 | 2879 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2880 | |
64bf9303 | 2881 | list_del_init(&vma->mm_list); |
75e9e915 | 2882 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2883 | if (i915_is_ggtt(vma->vm)) |
2884 | obj->map_and_fenceable = true; | |
673a394b | 2885 | |
2f633156 BW |
2886 | drm_mm_remove_node(&vma->node); |
2887 | i915_gem_vma_destroy(vma); | |
2888 | ||
2889 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2890 | * no more VMAs exist. */ |
2f633156 BW |
2891 | if (list_empty(&obj->vma_list)) |
2892 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2893 | |
70903c3b CW |
2894 | /* And finally now the object is completely decoupled from this vma, |
2895 | * we can drop its hold on the backing storage and allow it to be | |
2896 | * reaped by the shrinker. | |
2897 | */ | |
2898 | i915_gem_object_unpin_pages(obj); | |
2899 | ||
88241785 | 2900 | return 0; |
54cf91dc CW |
2901 | } |
2902 | ||
b2da9fe5 | 2903 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 2904 | { |
3e31c6c0 | 2905 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2906 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2907 | int ret, i; |
4df2faf4 | 2908 | |
4df2faf4 | 2909 | /* Flush everything onto the inactive list. */ |
b4519513 | 2910 | for_each_ring(ring, dev_priv, i) { |
691e6415 | 2911 | ret = i915_switch_context(ring, ring->default_context); |
b6c7488d BW |
2912 | if (ret) |
2913 | return ret; | |
2914 | ||
3e960501 | 2915 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2916 | if (ret) |
2917 | return ret; | |
2918 | } | |
4df2faf4 | 2919 | |
8a1a49f9 | 2920 | return 0; |
4df2faf4 DV |
2921 | } |
2922 | ||
9ce079e4 CW |
2923 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2924 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2925 | { |
3e31c6c0 | 2926 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
2927 | int fence_reg; |
2928 | int fence_pitch_shift; | |
de151cf6 | 2929 | |
56c844e5 ID |
2930 | if (INTEL_INFO(dev)->gen >= 6) { |
2931 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2932 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2933 | } else { | |
2934 | fence_reg = FENCE_REG_965_0; | |
2935 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2936 | } | |
2937 | ||
d18b9619 CW |
2938 | fence_reg += reg * 8; |
2939 | ||
2940 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2941 | * we split the 64-bit update into two 32-bit writes. In order | |
2942 | * for a partial fence not to be evaluated between writes, we | |
2943 | * precede the update with write to turn off the fence register, | |
2944 | * and only enable the fence as the last step. | |
2945 | * | |
2946 | * For extra levels of paranoia, we make sure each step lands | |
2947 | * before applying the next step. | |
2948 | */ | |
2949 | I915_WRITE(fence_reg, 0); | |
2950 | POSTING_READ(fence_reg); | |
2951 | ||
9ce079e4 | 2952 | if (obj) { |
f343c5f6 | 2953 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2954 | uint64_t val; |
de151cf6 | 2955 | |
f343c5f6 | 2956 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2957 | 0xfffff000) << 32; |
f343c5f6 | 2958 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2959 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2960 | if (obj->tiling_mode == I915_TILING_Y) |
2961 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2962 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2963 | |
d18b9619 CW |
2964 | I915_WRITE(fence_reg + 4, val >> 32); |
2965 | POSTING_READ(fence_reg + 4); | |
2966 | ||
2967 | I915_WRITE(fence_reg + 0, val); | |
2968 | POSTING_READ(fence_reg); | |
2969 | } else { | |
2970 | I915_WRITE(fence_reg + 4, 0); | |
2971 | POSTING_READ(fence_reg + 4); | |
2972 | } | |
de151cf6 JB |
2973 | } |
2974 | ||
9ce079e4 CW |
2975 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2976 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2977 | { |
3e31c6c0 | 2978 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 2979 | u32 val; |
de151cf6 | 2980 | |
9ce079e4 | 2981 | if (obj) { |
f343c5f6 | 2982 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2983 | int pitch_val; |
2984 | int tile_width; | |
c6642782 | 2985 | |
f343c5f6 | 2986 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2987 | (size & -size) != size || |
f343c5f6 BW |
2988 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2989 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2990 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2991 | |
9ce079e4 CW |
2992 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2993 | tile_width = 128; | |
2994 | else | |
2995 | tile_width = 512; | |
2996 | ||
2997 | /* Note: pitch better be a power of two tile widths */ | |
2998 | pitch_val = obj->stride / tile_width; | |
2999 | pitch_val = ffs(pitch_val) - 1; | |
3000 | ||
f343c5f6 | 3001 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3002 | if (obj->tiling_mode == I915_TILING_Y) |
3003 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3004 | val |= I915_FENCE_SIZE_BITS(size); | |
3005 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3006 | val |= I830_FENCE_REG_VALID; | |
3007 | } else | |
3008 | val = 0; | |
3009 | ||
3010 | if (reg < 8) | |
3011 | reg = FENCE_REG_830_0 + reg * 4; | |
3012 | else | |
3013 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3014 | ||
3015 | I915_WRITE(reg, val); | |
3016 | POSTING_READ(reg); | |
de151cf6 JB |
3017 | } |
3018 | ||
9ce079e4 CW |
3019 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3020 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3021 | { |
3e31c6c0 | 3022 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3023 | uint32_t val; |
de151cf6 | 3024 | |
9ce079e4 | 3025 | if (obj) { |
f343c5f6 | 3026 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3027 | uint32_t pitch_val; |
de151cf6 | 3028 | |
f343c5f6 | 3029 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3030 | (size & -size) != size || |
f343c5f6 BW |
3031 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3032 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3033 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3034 | |
9ce079e4 CW |
3035 | pitch_val = obj->stride / 128; |
3036 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3037 | |
f343c5f6 | 3038 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3039 | if (obj->tiling_mode == I915_TILING_Y) |
3040 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3041 | val |= I830_FENCE_SIZE_BITS(size); | |
3042 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3043 | val |= I830_FENCE_REG_VALID; | |
3044 | } else | |
3045 | val = 0; | |
c6642782 | 3046 | |
9ce079e4 CW |
3047 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3048 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3049 | } | |
3050 | ||
d0a57789 CW |
3051 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3052 | { | |
3053 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3054 | } | |
3055 | ||
9ce079e4 CW |
3056 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3057 | struct drm_i915_gem_object *obj) | |
3058 | { | |
d0a57789 CW |
3059 | struct drm_i915_private *dev_priv = dev->dev_private; |
3060 | ||
3061 | /* Ensure that all CPU reads are completed before installing a fence | |
3062 | * and all writes before removing the fence. | |
3063 | */ | |
3064 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3065 | mb(); | |
3066 | ||
94a335db DV |
3067 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3068 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3069 | obj->stride, obj->tiling_mode); | |
3070 | ||
9ce079e4 | 3071 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 3072 | case 8: |
9ce079e4 | 3073 | case 7: |
56c844e5 | 3074 | case 6: |
9ce079e4 CW |
3075 | case 5: |
3076 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
3077 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
3078 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 3079 | default: BUG(); |
9ce079e4 | 3080 | } |
d0a57789 CW |
3081 | |
3082 | /* And similarly be paranoid that no direct access to this region | |
3083 | * is reordered to before the fence is installed. | |
3084 | */ | |
3085 | if (i915_gem_object_needs_mb(obj)) | |
3086 | mb(); | |
de151cf6 JB |
3087 | } |
3088 | ||
61050808 CW |
3089 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3090 | struct drm_i915_fence_reg *fence) | |
3091 | { | |
3092 | return fence - dev_priv->fence_regs; | |
3093 | } | |
3094 | ||
3095 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3096 | struct drm_i915_fence_reg *fence, | |
3097 | bool enable) | |
3098 | { | |
2dc8aae0 | 3099 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3100 | int reg = fence_number(dev_priv, fence); |
3101 | ||
3102 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3103 | |
3104 | if (enable) { | |
46a0b638 | 3105 | obj->fence_reg = reg; |
61050808 CW |
3106 | fence->obj = obj; |
3107 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3108 | } else { | |
3109 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3110 | fence->obj = NULL; | |
3111 | list_del_init(&fence->lru_list); | |
3112 | } | |
94a335db | 3113 | obj->fence_dirty = false; |
61050808 CW |
3114 | } |
3115 | ||
d9e86c0e | 3116 | static int |
d0a57789 | 3117 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3118 | { |
1c293ea3 | 3119 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3120 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3121 | if (ret) |
3122 | return ret; | |
d9e86c0e CW |
3123 | |
3124 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3125 | } |
3126 | ||
86d5bc37 | 3127 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3128 | return 0; |
3129 | } | |
3130 | ||
3131 | int | |
3132 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3133 | { | |
61050808 | 3134 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3135 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3136 | int ret; |
3137 | ||
d0a57789 | 3138 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3139 | if (ret) |
3140 | return ret; | |
3141 | ||
61050808 CW |
3142 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3143 | return 0; | |
d9e86c0e | 3144 | |
f9c513e9 CW |
3145 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3146 | ||
61050808 | 3147 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3148 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3149 | |
3150 | return 0; | |
3151 | } | |
3152 | ||
3153 | static struct drm_i915_fence_reg * | |
a360bb1a | 3154 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3155 | { |
ae3db24a | 3156 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3157 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3158 | int i; |
ae3db24a DV |
3159 | |
3160 | /* First try to find a free reg */ | |
d9e86c0e | 3161 | avail = NULL; |
ae3db24a DV |
3162 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3163 | reg = &dev_priv->fence_regs[i]; | |
3164 | if (!reg->obj) | |
d9e86c0e | 3165 | return reg; |
ae3db24a | 3166 | |
1690e1eb | 3167 | if (!reg->pin_count) |
d9e86c0e | 3168 | avail = reg; |
ae3db24a DV |
3169 | } |
3170 | ||
d9e86c0e | 3171 | if (avail == NULL) |
5dce5b93 | 3172 | goto deadlock; |
ae3db24a DV |
3173 | |
3174 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3175 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3176 | if (reg->pin_count) |
ae3db24a DV |
3177 | continue; |
3178 | ||
8fe301ad | 3179 | return reg; |
ae3db24a DV |
3180 | } |
3181 | ||
5dce5b93 CW |
3182 | deadlock: |
3183 | /* Wait for completion of pending flips which consume fences */ | |
3184 | if (intel_has_pending_fb_unpin(dev)) | |
3185 | return ERR_PTR(-EAGAIN); | |
3186 | ||
3187 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3188 | } |
3189 | ||
de151cf6 | 3190 | /** |
9a5a53b3 | 3191 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3192 | * @obj: object to map through a fence reg |
3193 | * | |
3194 | * When mapping objects through the GTT, userspace wants to be able to write | |
3195 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3196 | * This function walks the fence regs looking for a free one for @obj, |
3197 | * stealing one if it can't find any. | |
3198 | * | |
3199 | * It then sets up the reg based on the object's properties: address, pitch | |
3200 | * and tiling format. | |
9a5a53b3 CW |
3201 | * |
3202 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3203 | */ |
8c4b8c3f | 3204 | int |
06d98131 | 3205 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3206 | { |
05394f39 | 3207 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3208 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3209 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3210 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3211 | int ret; |
de151cf6 | 3212 | |
14415745 CW |
3213 | /* Have we updated the tiling parameters upon the object and so |
3214 | * will need to serialise the write to the associated fence register? | |
3215 | */ | |
5d82e3e6 | 3216 | if (obj->fence_dirty) { |
d0a57789 | 3217 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3218 | if (ret) |
3219 | return ret; | |
3220 | } | |
9a5a53b3 | 3221 | |
d9e86c0e | 3222 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3223 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3224 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3225 | if (!obj->fence_dirty) { |
14415745 CW |
3226 | list_move_tail(®->lru_list, |
3227 | &dev_priv->mm.fence_list); | |
3228 | return 0; | |
3229 | } | |
3230 | } else if (enable) { | |
3231 | reg = i915_find_fence_reg(dev); | |
5dce5b93 CW |
3232 | if (IS_ERR(reg)) |
3233 | return PTR_ERR(reg); | |
d9e86c0e | 3234 | |
14415745 CW |
3235 | if (reg->obj) { |
3236 | struct drm_i915_gem_object *old = reg->obj; | |
3237 | ||
d0a57789 | 3238 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3239 | if (ret) |
3240 | return ret; | |
3241 | ||
14415745 | 3242 | i915_gem_object_fence_lost(old); |
29c5a587 | 3243 | } |
14415745 | 3244 | } else |
a09ba7fa | 3245 | return 0; |
a09ba7fa | 3246 | |
14415745 | 3247 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3248 | |
9ce079e4 | 3249 | return 0; |
de151cf6 JB |
3250 | } |
3251 | ||
42d6ab48 CW |
3252 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3253 | struct drm_mm_node *gtt_space, | |
3254 | unsigned long cache_level) | |
3255 | { | |
3256 | struct drm_mm_node *other; | |
3257 | ||
3258 | /* On non-LLC machines we have to be careful when putting differing | |
3259 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3260 | * crossing memory domains and dying. |
42d6ab48 CW |
3261 | */ |
3262 | if (HAS_LLC(dev)) | |
3263 | return true; | |
3264 | ||
c6cfb325 | 3265 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3266 | return true; |
3267 | ||
3268 | if (list_empty(>t_space->node_list)) | |
3269 | return true; | |
3270 | ||
3271 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3272 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3273 | return false; | |
3274 | ||
3275 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3276 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3277 | return false; | |
3278 | ||
3279 | return true; | |
3280 | } | |
3281 | ||
3282 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3283 | { | |
3284 | #if WATCH_GTT | |
3285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3286 | struct drm_i915_gem_object *obj; | |
3287 | int err = 0; | |
3288 | ||
35c20a60 | 3289 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3290 | if (obj->gtt_space == NULL) { |
3291 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3292 | err++; | |
3293 | continue; | |
3294 | } | |
3295 | ||
3296 | if (obj->cache_level != obj->gtt_space->color) { | |
3297 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3298 | i915_gem_obj_ggtt_offset(obj), |
3299 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3300 | obj->cache_level, |
3301 | obj->gtt_space->color); | |
3302 | err++; | |
3303 | continue; | |
3304 | } | |
3305 | ||
3306 | if (!i915_gem_valid_gtt_space(dev, | |
3307 | obj->gtt_space, | |
3308 | obj->cache_level)) { | |
3309 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3310 | i915_gem_obj_ggtt_offset(obj), |
3311 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3312 | obj->cache_level); |
3313 | err++; | |
3314 | continue; | |
3315 | } | |
3316 | } | |
3317 | ||
3318 | WARN_ON(err); | |
3319 | #endif | |
3320 | } | |
3321 | ||
673a394b EA |
3322 | /** |
3323 | * Finds free space in the GTT aperture and binds the object there. | |
3324 | */ | |
262de145 | 3325 | static struct i915_vma * |
07fe0b12 BW |
3326 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3327 | struct i915_address_space *vm, | |
3328 | unsigned alignment, | |
1ec9e26d | 3329 | unsigned flags) |
673a394b | 3330 | { |
05394f39 | 3331 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3332 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3333 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 | 3334 | size_t gtt_max = |
1ec9e26d | 3335 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3336 | struct i915_vma *vma; |
07f73f69 | 3337 | int ret; |
673a394b | 3338 | |
e28f8711 CW |
3339 | fence_size = i915_gem_get_gtt_size(dev, |
3340 | obj->base.size, | |
3341 | obj->tiling_mode); | |
3342 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3343 | obj->base.size, | |
d865110c | 3344 | obj->tiling_mode, true); |
e28f8711 | 3345 | unfenced_alignment = |
d865110c | 3346 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3347 | obj->base.size, |
3348 | obj->tiling_mode, false); | |
a00b10c3 | 3349 | |
673a394b | 3350 | if (alignment == 0) |
1ec9e26d | 3351 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3352 | unfenced_alignment; |
1ec9e26d | 3353 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3354 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3355 | return ERR_PTR(-EINVAL); |
673a394b EA |
3356 | } |
3357 | ||
1ec9e26d | 3358 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3359 | |
654fc607 CW |
3360 | /* If the object is bigger than the entire aperture, reject it early |
3361 | * before evicting everything in a vain attempt to find space. | |
3362 | */ | |
0a9ae0d7 | 3363 | if (obj->base.size > gtt_max) { |
bd9b6a4e | 3364 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb | 3365 | obj->base.size, |
1ec9e26d | 3366 | flags & PIN_MAPPABLE ? "mappable" : "total", |
0a9ae0d7 | 3367 | gtt_max); |
262de145 | 3368 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3369 | } |
3370 | ||
37e680a1 | 3371 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3372 | if (ret) |
262de145 | 3373 | return ERR_PTR(ret); |
6c085a72 | 3374 | |
fbdda6fb CW |
3375 | i915_gem_object_pin_pages(obj); |
3376 | ||
accfef2e | 3377 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3378 | if (IS_ERR(vma)) |
bc6bc15b | 3379 | goto err_unpin; |
2f633156 | 3380 | |
0a9ae0d7 | 3381 | search_free: |
07fe0b12 | 3382 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3383 | size, alignment, |
31e5d7c6 | 3384 | obj->cache_level, 0, gtt_max, |
62347f9e LK |
3385 | DRM_MM_SEARCH_DEFAULT, |
3386 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3387 | if (ret) { |
f6cd1f15 | 3388 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
1ec9e26d | 3389 | obj->cache_level, flags); |
dc9dd7a2 CW |
3390 | if (ret == 0) |
3391 | goto search_free; | |
9731129c | 3392 | |
bc6bc15b | 3393 | goto err_free_vma; |
673a394b | 3394 | } |
2f633156 | 3395 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3396 | obj->cache_level))) { |
2f633156 | 3397 | ret = -EINVAL; |
bc6bc15b | 3398 | goto err_remove_node; |
673a394b EA |
3399 | } |
3400 | ||
74163907 | 3401 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3402 | if (ret) |
bc6bc15b | 3403 | goto err_remove_node; |
673a394b | 3404 | |
35c20a60 | 3405 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3406 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3407 | |
4bd561b3 BW |
3408 | if (i915_is_ggtt(vm)) { |
3409 | bool mappable, fenceable; | |
a00b10c3 | 3410 | |
49987099 DV |
3411 | fenceable = (vma->node.size == fence_size && |
3412 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3413 | |
49987099 DV |
3414 | mappable = (vma->node.start + obj->base.size <= |
3415 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3416 | |
5cacaac7 | 3417 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3418 | } |
75e9e915 | 3419 | |
1ec9e26d | 3420 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
75e9e915 | 3421 | |
1ec9e26d | 3422 | trace_i915_vma_bind(vma, flags); |
8ea99c92 DV |
3423 | vma->bind_vma(vma, obj->cache_level, |
3424 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); | |
3425 | ||
42d6ab48 | 3426 | i915_gem_verify_gtt(dev); |
262de145 | 3427 | return vma; |
2f633156 | 3428 | |
bc6bc15b | 3429 | err_remove_node: |
6286ef9b | 3430 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3431 | err_free_vma: |
2f633156 | 3432 | i915_gem_vma_destroy(vma); |
262de145 | 3433 | vma = ERR_PTR(ret); |
bc6bc15b | 3434 | err_unpin: |
2f633156 | 3435 | i915_gem_object_unpin_pages(obj); |
262de145 | 3436 | return vma; |
673a394b EA |
3437 | } |
3438 | ||
000433b6 | 3439 | bool |
2c22569b CW |
3440 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3441 | bool force) | |
673a394b | 3442 | { |
673a394b EA |
3443 | /* If we don't have a page list set up, then we're not pinned |
3444 | * to GPU, and we can ignore the cache flush because it'll happen | |
3445 | * again at bind time. | |
3446 | */ | |
05394f39 | 3447 | if (obj->pages == NULL) |
000433b6 | 3448 | return false; |
673a394b | 3449 | |
769ce464 ID |
3450 | /* |
3451 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3452 | * marked as wc by the system, or the system is cache-coherent. | |
3453 | */ | |
3454 | if (obj->stolen) | |
000433b6 | 3455 | return false; |
769ce464 | 3456 | |
9c23f7fc CW |
3457 | /* If the GPU is snooping the contents of the CPU cache, |
3458 | * we do not need to manually clear the CPU cache lines. However, | |
3459 | * the caches are only snooped when the render cache is | |
3460 | * flushed/invalidated. As we always have to emit invalidations | |
3461 | * and flushes when moving into and out of the RENDER domain, correct | |
3462 | * snooping behaviour occurs naturally as the result of our domain | |
3463 | * tracking. | |
3464 | */ | |
2c22569b | 3465 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3466 | return false; |
9c23f7fc | 3467 | |
1c5d22f7 | 3468 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3469 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3470 | |
3471 | return true; | |
e47c68e9 EA |
3472 | } |
3473 | ||
3474 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3475 | static void | |
05394f39 | 3476 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3477 | { |
1c5d22f7 CW |
3478 | uint32_t old_write_domain; |
3479 | ||
05394f39 | 3480 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3481 | return; |
3482 | ||
63256ec5 | 3483 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3484 | * to it immediately go to main memory as far as we know, so there's |
3485 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3486 | * |
3487 | * However, we do have to enforce the order so that all writes through | |
3488 | * the GTT land before any writes to the device, such as updates to | |
3489 | * the GATT itself. | |
e47c68e9 | 3490 | */ |
63256ec5 CW |
3491 | wmb(); |
3492 | ||
05394f39 CW |
3493 | old_write_domain = obj->base.write_domain; |
3494 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3495 | |
3496 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3497 | obj->base.read_domains, |
1c5d22f7 | 3498 | old_write_domain); |
e47c68e9 EA |
3499 | } |
3500 | ||
3501 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3502 | static void | |
2c22569b CW |
3503 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3504 | bool force) | |
e47c68e9 | 3505 | { |
1c5d22f7 | 3506 | uint32_t old_write_domain; |
e47c68e9 | 3507 | |
05394f39 | 3508 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3509 | return; |
3510 | ||
000433b6 CW |
3511 | if (i915_gem_clflush_object(obj, force)) |
3512 | i915_gem_chipset_flush(obj->base.dev); | |
3513 | ||
05394f39 CW |
3514 | old_write_domain = obj->base.write_domain; |
3515 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3516 | |
3517 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3518 | obj->base.read_domains, |
1c5d22f7 | 3519 | old_write_domain); |
e47c68e9 EA |
3520 | } |
3521 | ||
2ef7eeaa EA |
3522 | /** |
3523 | * Moves a single object to the GTT read, and possibly write domain. | |
3524 | * | |
3525 | * This function returns when the move is complete, including waiting on | |
3526 | * flushes to occur. | |
3527 | */ | |
79e53945 | 3528 | int |
2021746e | 3529 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3530 | { |
3e31c6c0 | 3531 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3532 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3533 | int ret; |
2ef7eeaa | 3534 | |
02354392 | 3535 | /* Not valid to be called on unbound objects. */ |
9843877d | 3536 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3537 | return -EINVAL; |
3538 | ||
8d7e3de1 CW |
3539 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3540 | return 0; | |
3541 | ||
0201f1ec | 3542 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3543 | if (ret) |
3544 | return ret; | |
3545 | ||
2c22569b | 3546 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3547 | |
d0a57789 CW |
3548 | /* Serialise direct access to this object with the barriers for |
3549 | * coherent writes from the GPU, by effectively invalidating the | |
3550 | * GTT domain upon first access. | |
3551 | */ | |
3552 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3553 | mb(); | |
3554 | ||
05394f39 CW |
3555 | old_write_domain = obj->base.write_domain; |
3556 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3557 | |
e47c68e9 EA |
3558 | /* It should now be out of any other write domains, and we can update |
3559 | * the domain values for our changes. | |
3560 | */ | |
05394f39 CW |
3561 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3562 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3563 | if (write) { |
05394f39 CW |
3564 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3565 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3566 | obj->dirty = 1; | |
2ef7eeaa EA |
3567 | } |
3568 | ||
1c5d22f7 CW |
3569 | trace_i915_gem_object_change_domain(obj, |
3570 | old_read_domains, | |
3571 | old_write_domain); | |
3572 | ||
8325a09d | 3573 | /* And bump the LRU for this access */ |
ca191b13 | 3574 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3575 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3576 | if (vma) |
3577 | list_move_tail(&vma->mm_list, | |
3578 | &dev_priv->gtt.base.inactive_list); | |
3579 | ||
3580 | } | |
8325a09d | 3581 | |
e47c68e9 EA |
3582 | return 0; |
3583 | } | |
3584 | ||
e4ffd173 CW |
3585 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3586 | enum i915_cache_level cache_level) | |
3587 | { | |
7bddb01f | 3588 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3589 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3590 | int ret; |
3591 | ||
3592 | if (obj->cache_level == cache_level) | |
3593 | return 0; | |
3594 | ||
d7f46fc4 | 3595 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3596 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3597 | return -EBUSY; | |
3598 | } | |
3599 | ||
df6f783a | 3600 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
3089c6f2 | 3601 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
07fe0b12 | 3602 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3603 | if (ret) |
3604 | return ret; | |
3089c6f2 | 3605 | } |
42d6ab48 CW |
3606 | } |
3607 | ||
3089c6f2 | 3608 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3609 | ret = i915_gem_object_finish_gpu(obj); |
3610 | if (ret) | |
3611 | return ret; | |
3612 | ||
3613 | i915_gem_object_finish_gtt(obj); | |
3614 | ||
3615 | /* Before SandyBridge, you could not use tiling or fence | |
3616 | * registers with snooped memory, so relinquish any fences | |
3617 | * currently pointing to our region in the aperture. | |
3618 | */ | |
42d6ab48 | 3619 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3620 | ret = i915_gem_object_put_fence(obj); |
3621 | if (ret) | |
3622 | return ret; | |
3623 | } | |
3624 | ||
6f65e29a | 3625 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3626 | if (drm_mm_node_allocated(&vma->node)) |
3627 | vma->bind_vma(vma, cache_level, | |
3628 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); | |
e4ffd173 CW |
3629 | } |
3630 | ||
2c22569b CW |
3631 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3632 | vma->node.color = cache_level; | |
3633 | obj->cache_level = cache_level; | |
3634 | ||
3635 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3636 | u32 old_read_domains, old_write_domain; |
3637 | ||
3638 | /* If we're coming from LLC cached, then we haven't | |
3639 | * actually been tracking whether the data is in the | |
3640 | * CPU cache or not, since we only allow one bit set | |
3641 | * in obj->write_domain and have been skipping the clflushes. | |
3642 | * Just set it to the CPU cache for now. | |
3643 | */ | |
3644 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
e4ffd173 CW |
3645 | |
3646 | old_read_domains = obj->base.read_domains; | |
3647 | old_write_domain = obj->base.write_domain; | |
3648 | ||
3649 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3650 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3651 | ||
3652 | trace_i915_gem_object_change_domain(obj, | |
3653 | old_read_domains, | |
3654 | old_write_domain); | |
3655 | } | |
3656 | ||
42d6ab48 | 3657 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3658 | return 0; |
3659 | } | |
3660 | ||
199adf40 BW |
3661 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3662 | struct drm_file *file) | |
e6994aee | 3663 | { |
199adf40 | 3664 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3665 | struct drm_i915_gem_object *obj; |
3666 | int ret; | |
3667 | ||
3668 | ret = i915_mutex_lock_interruptible(dev); | |
3669 | if (ret) | |
3670 | return ret; | |
3671 | ||
3672 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3673 | if (&obj->base == NULL) { | |
3674 | ret = -ENOENT; | |
3675 | goto unlock; | |
3676 | } | |
3677 | ||
651d794f CW |
3678 | switch (obj->cache_level) { |
3679 | case I915_CACHE_LLC: | |
3680 | case I915_CACHE_L3_LLC: | |
3681 | args->caching = I915_CACHING_CACHED; | |
3682 | break; | |
3683 | ||
4257d3ba CW |
3684 | case I915_CACHE_WT: |
3685 | args->caching = I915_CACHING_DISPLAY; | |
3686 | break; | |
3687 | ||
651d794f CW |
3688 | default: |
3689 | args->caching = I915_CACHING_NONE; | |
3690 | break; | |
3691 | } | |
e6994aee CW |
3692 | |
3693 | drm_gem_object_unreference(&obj->base); | |
3694 | unlock: | |
3695 | mutex_unlock(&dev->struct_mutex); | |
3696 | return ret; | |
3697 | } | |
3698 | ||
199adf40 BW |
3699 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3700 | struct drm_file *file) | |
e6994aee | 3701 | { |
199adf40 | 3702 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3703 | struct drm_i915_gem_object *obj; |
3704 | enum i915_cache_level level; | |
3705 | int ret; | |
3706 | ||
199adf40 BW |
3707 | switch (args->caching) { |
3708 | case I915_CACHING_NONE: | |
e6994aee CW |
3709 | level = I915_CACHE_NONE; |
3710 | break; | |
199adf40 | 3711 | case I915_CACHING_CACHED: |
e6994aee CW |
3712 | level = I915_CACHE_LLC; |
3713 | break; | |
4257d3ba CW |
3714 | case I915_CACHING_DISPLAY: |
3715 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3716 | break; | |
e6994aee CW |
3717 | default: |
3718 | return -EINVAL; | |
3719 | } | |
3720 | ||
3bc2913e BW |
3721 | ret = i915_mutex_lock_interruptible(dev); |
3722 | if (ret) | |
3723 | return ret; | |
3724 | ||
e6994aee CW |
3725 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3726 | if (&obj->base == NULL) { | |
3727 | ret = -ENOENT; | |
3728 | goto unlock; | |
3729 | } | |
3730 | ||
3731 | ret = i915_gem_object_set_cache_level(obj, level); | |
3732 | ||
3733 | drm_gem_object_unreference(&obj->base); | |
3734 | unlock: | |
3735 | mutex_unlock(&dev->struct_mutex); | |
3736 | return ret; | |
3737 | } | |
3738 | ||
cc98b413 CW |
3739 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3740 | { | |
3741 | /* There are 3 sources that pin objects: | |
3742 | * 1. The display engine (scanouts, sprites, cursors); | |
3743 | * 2. Reservations for execbuffer; | |
3744 | * 3. The user. | |
3745 | * | |
3746 | * We can ignore reservations as we hold the struct_mutex and | |
3747 | * are only called outside of the reservation path. The user | |
3748 | * can only increment pin_count once, and so if after | |
3749 | * subtracting the potential reference by the user, any pin_count | |
3750 | * remains, it must be due to another use by the display engine. | |
3751 | */ | |
d7f46fc4 | 3752 | return i915_gem_obj_to_ggtt(obj)->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3753 | } |
3754 | ||
b9241ea3 | 3755 | /* |
2da3b9b9 CW |
3756 | * Prepare buffer for display plane (scanout, cursors, etc). |
3757 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3758 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3759 | */ |
3760 | int | |
2da3b9b9 CW |
3761 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3762 | u32 alignment, | |
919926ae | 3763 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3764 | { |
2da3b9b9 | 3765 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3766 | int ret; |
3767 | ||
0be73284 | 3768 | if (pipelined != obj->ring) { |
2911a35b BW |
3769 | ret = i915_gem_object_sync(obj, pipelined); |
3770 | if (ret) | |
b9241ea3 ZW |
3771 | return ret; |
3772 | } | |
3773 | ||
cc98b413 CW |
3774 | /* Mark the pin_display early so that we account for the |
3775 | * display coherency whilst setting up the cache domains. | |
3776 | */ | |
3777 | obj->pin_display = true; | |
3778 | ||
a7ef0640 EA |
3779 | /* The display engine is not coherent with the LLC cache on gen6. As |
3780 | * a result, we make sure that the pinning that is about to occur is | |
3781 | * done with uncached PTEs. This is lowest common denominator for all | |
3782 | * chipsets. | |
3783 | * | |
3784 | * However for gen6+, we could do better by using the GFDT bit instead | |
3785 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3786 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3787 | */ | |
651d794f CW |
3788 | ret = i915_gem_object_set_cache_level(obj, |
3789 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3790 | if (ret) |
cc98b413 | 3791 | goto err_unpin_display; |
a7ef0640 | 3792 | |
2da3b9b9 CW |
3793 | /* As the user may map the buffer once pinned in the display plane |
3794 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3795 | * always use map_and_fenceable for all scanout buffers. | |
3796 | */ | |
1ec9e26d | 3797 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3798 | if (ret) |
cc98b413 | 3799 | goto err_unpin_display; |
2da3b9b9 | 3800 | |
2c22569b | 3801 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3802 | |
2da3b9b9 | 3803 | old_write_domain = obj->base.write_domain; |
05394f39 | 3804 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3805 | |
3806 | /* It should now be out of any other write domains, and we can update | |
3807 | * the domain values for our changes. | |
3808 | */ | |
e5f1d962 | 3809 | obj->base.write_domain = 0; |
05394f39 | 3810 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3811 | |
3812 | trace_i915_gem_object_change_domain(obj, | |
3813 | old_read_domains, | |
2da3b9b9 | 3814 | old_write_domain); |
b9241ea3 ZW |
3815 | |
3816 | return 0; | |
cc98b413 CW |
3817 | |
3818 | err_unpin_display: | |
3819 | obj->pin_display = is_pin_display(obj); | |
3820 | return ret; | |
3821 | } | |
3822 | ||
3823 | void | |
3824 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3825 | { | |
d7f46fc4 | 3826 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3827 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3828 | } |
3829 | ||
85345517 | 3830 | int |
a8198eea | 3831 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3832 | { |
88241785 CW |
3833 | int ret; |
3834 | ||
a8198eea | 3835 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3836 | return 0; |
3837 | ||
0201f1ec | 3838 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3839 | if (ret) |
3840 | return ret; | |
3841 | ||
a8198eea CW |
3842 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3843 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3844 | return 0; |
85345517 CW |
3845 | } |
3846 | ||
e47c68e9 EA |
3847 | /** |
3848 | * Moves a single object to the CPU read, and possibly write domain. | |
3849 | * | |
3850 | * This function returns when the move is complete, including waiting on | |
3851 | * flushes to occur. | |
3852 | */ | |
dabdfe02 | 3853 | int |
919926ae | 3854 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3855 | { |
1c5d22f7 | 3856 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3857 | int ret; |
3858 | ||
8d7e3de1 CW |
3859 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3860 | return 0; | |
3861 | ||
0201f1ec | 3862 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3863 | if (ret) |
3864 | return ret; | |
3865 | ||
e47c68e9 | 3866 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3867 | |
05394f39 CW |
3868 | old_write_domain = obj->base.write_domain; |
3869 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3870 | |
e47c68e9 | 3871 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3872 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3873 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3874 | |
05394f39 | 3875 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3876 | } |
3877 | ||
3878 | /* It should now be out of any other write domains, and we can update | |
3879 | * the domain values for our changes. | |
3880 | */ | |
05394f39 | 3881 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3882 | |
3883 | /* If we're writing through the CPU, then the GPU read domains will | |
3884 | * need to be invalidated at next use. | |
3885 | */ | |
3886 | if (write) { | |
05394f39 CW |
3887 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3888 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3889 | } |
2ef7eeaa | 3890 | |
1c5d22f7 CW |
3891 | trace_i915_gem_object_change_domain(obj, |
3892 | old_read_domains, | |
3893 | old_write_domain); | |
3894 | ||
2ef7eeaa EA |
3895 | return 0; |
3896 | } | |
3897 | ||
673a394b EA |
3898 | /* Throttle our rendering by waiting until the ring has completed our requests |
3899 | * emitted over 20 msec ago. | |
3900 | * | |
b962442e EA |
3901 | * Note that if we were to use the current jiffies each time around the loop, |
3902 | * we wouldn't escape the function with any frames outstanding if the time to | |
3903 | * render a frame was over 20ms. | |
3904 | * | |
673a394b EA |
3905 | * This should get us reasonable parallelism between CPU and GPU but also |
3906 | * relatively low latency when blocking on a particular request to finish. | |
3907 | */ | |
40a5f0de | 3908 | static int |
f787a5f5 | 3909 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3910 | { |
f787a5f5 CW |
3911 | struct drm_i915_private *dev_priv = dev->dev_private; |
3912 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3913 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3914 | struct drm_i915_gem_request *request; |
3915 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3916 | unsigned reset_counter; |
f787a5f5 CW |
3917 | u32 seqno = 0; |
3918 | int ret; | |
93533c29 | 3919 | |
308887aa DV |
3920 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3921 | if (ret) | |
3922 | return ret; | |
3923 | ||
3924 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3925 | if (ret) | |
3926 | return ret; | |
e110e8d6 | 3927 | |
1c25595f | 3928 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3929 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3930 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3931 | break; | |
40a5f0de | 3932 | |
f787a5f5 CW |
3933 | ring = request->ring; |
3934 | seqno = request->seqno; | |
b962442e | 3935 | } |
f69061be | 3936 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3937 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3938 | |
f787a5f5 CW |
3939 | if (seqno == 0) |
3940 | return 0; | |
2bc43b5c | 3941 | |
b29c19b6 | 3942 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
3943 | if (ret == 0) |
3944 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3945 | |
3946 | return ret; | |
3947 | } | |
3948 | ||
673a394b | 3949 | int |
05394f39 | 3950 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3951 | struct i915_address_space *vm, |
05394f39 | 3952 | uint32_t alignment, |
1ec9e26d | 3953 | unsigned flags) |
673a394b | 3954 | { |
07fe0b12 | 3955 | struct i915_vma *vma; |
673a394b EA |
3956 | int ret; |
3957 | ||
bf3d149b | 3958 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 3959 | return -EINVAL; |
07fe0b12 BW |
3960 | |
3961 | vma = i915_gem_obj_to_vma(obj, vm); | |
07fe0b12 | 3962 | if (vma) { |
d7f46fc4 BW |
3963 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3964 | return -EBUSY; | |
3965 | ||
07fe0b12 BW |
3966 | if ((alignment && |
3967 | vma->node.start & (alignment - 1)) || | |
1ec9e26d | 3968 | (flags & PIN_MAPPABLE && !obj->map_and_fenceable)) { |
d7f46fc4 | 3969 | WARN(vma->pin_count, |
ae7d49d8 | 3970 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3971 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3972 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3973 | i915_gem_obj_offset(obj, vm), alignment, |
1ec9e26d | 3974 | flags & PIN_MAPPABLE, |
05394f39 | 3975 | obj->map_and_fenceable); |
07fe0b12 | 3976 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3977 | if (ret) |
3978 | return ret; | |
8ea99c92 DV |
3979 | |
3980 | vma = NULL; | |
ac0c6b5a CW |
3981 | } |
3982 | } | |
3983 | ||
8ea99c92 | 3984 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
3985 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
3986 | if (IS_ERR(vma)) | |
3987 | return PTR_ERR(vma); | |
22c344e9 | 3988 | } |
76446cac | 3989 | |
8ea99c92 DV |
3990 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
3991 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
74898d7e | 3992 | |
8ea99c92 | 3993 | vma->pin_count++; |
1ec9e26d DV |
3994 | if (flags & PIN_MAPPABLE) |
3995 | obj->pin_mappable |= true; | |
673a394b EA |
3996 | |
3997 | return 0; | |
3998 | } | |
3999 | ||
4000 | void | |
d7f46fc4 | 4001 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4002 | { |
d7f46fc4 | 4003 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 4004 | |
d7f46fc4 BW |
4005 | BUG_ON(!vma); |
4006 | BUG_ON(vma->pin_count == 0); | |
4007 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
4008 | ||
4009 | if (--vma->pin_count == 0) | |
6299f992 | 4010 | obj->pin_mappable = false; |
673a394b EA |
4011 | } |
4012 | ||
4013 | int | |
4014 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4015 | struct drm_file *file) |
673a394b EA |
4016 | { |
4017 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4018 | struct drm_i915_gem_object *obj; |
673a394b EA |
4019 | int ret; |
4020 | ||
02f6bccc DV |
4021 | if (INTEL_INFO(dev)->gen >= 6) |
4022 | return -ENODEV; | |
4023 | ||
1d7cfea1 CW |
4024 | ret = i915_mutex_lock_interruptible(dev); |
4025 | if (ret) | |
4026 | return ret; | |
673a394b | 4027 | |
05394f39 | 4028 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4029 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4030 | ret = -ENOENT; |
4031 | goto unlock; | |
673a394b | 4032 | } |
673a394b | 4033 | |
05394f39 | 4034 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 4035 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
8c99e57d | 4036 | ret = -EFAULT; |
1d7cfea1 | 4037 | goto out; |
3ef94daa CW |
4038 | } |
4039 | ||
05394f39 | 4040 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
bd9b6a4e | 4041 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4042 | args->handle); |
1d7cfea1 CW |
4043 | ret = -EINVAL; |
4044 | goto out; | |
79e53945 JB |
4045 | } |
4046 | ||
aa5f8021 DV |
4047 | if (obj->user_pin_count == ULONG_MAX) { |
4048 | ret = -EBUSY; | |
4049 | goto out; | |
4050 | } | |
4051 | ||
93be8788 | 4052 | if (obj->user_pin_count == 0) { |
1ec9e26d | 4053 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
1d7cfea1 CW |
4054 | if (ret) |
4055 | goto out; | |
673a394b EA |
4056 | } |
4057 | ||
93be8788 CW |
4058 | obj->user_pin_count++; |
4059 | obj->pin_filp = file; | |
4060 | ||
f343c5f6 | 4061 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 4062 | out: |
05394f39 | 4063 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4064 | unlock: |
673a394b | 4065 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4066 | return ret; |
673a394b EA |
4067 | } |
4068 | ||
4069 | int | |
4070 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4071 | struct drm_file *file) |
673a394b EA |
4072 | { |
4073 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4074 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4075 | int ret; |
673a394b | 4076 | |
1d7cfea1 CW |
4077 | ret = i915_mutex_lock_interruptible(dev); |
4078 | if (ret) | |
4079 | return ret; | |
673a394b | 4080 | |
05394f39 | 4081 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4082 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4083 | ret = -ENOENT; |
4084 | goto unlock; | |
673a394b | 4085 | } |
76c1dec1 | 4086 | |
05394f39 | 4087 | if (obj->pin_filp != file) { |
bd9b6a4e | 4088 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4089 | args->handle); |
1d7cfea1 CW |
4090 | ret = -EINVAL; |
4091 | goto out; | |
79e53945 | 4092 | } |
05394f39 CW |
4093 | obj->user_pin_count--; |
4094 | if (obj->user_pin_count == 0) { | |
4095 | obj->pin_filp = NULL; | |
d7f46fc4 | 4096 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 4097 | } |
673a394b | 4098 | |
1d7cfea1 | 4099 | out: |
05394f39 | 4100 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4101 | unlock: |
673a394b | 4102 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4103 | return ret; |
673a394b EA |
4104 | } |
4105 | ||
4106 | int | |
4107 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4108 | struct drm_file *file) |
673a394b EA |
4109 | { |
4110 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4111 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4112 | int ret; |
4113 | ||
76c1dec1 | 4114 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4115 | if (ret) |
76c1dec1 | 4116 | return ret; |
673a394b | 4117 | |
05394f39 | 4118 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4119 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4120 | ret = -ENOENT; |
4121 | goto unlock; | |
673a394b | 4122 | } |
d1b851fc | 4123 | |
0be555b6 CW |
4124 | /* Count all active objects as busy, even if they are currently not used |
4125 | * by the gpu. Users of this interface expect objects to eventually | |
4126 | * become non-busy without any further actions, therefore emit any | |
4127 | * necessary flushes here. | |
c4de0a5d | 4128 | */ |
30dfebf3 | 4129 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4130 | |
30dfebf3 | 4131 | args->busy = obj->active; |
e9808edd CW |
4132 | if (obj->ring) { |
4133 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4134 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4135 | } | |
673a394b | 4136 | |
05394f39 | 4137 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4138 | unlock: |
673a394b | 4139 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4140 | return ret; |
673a394b EA |
4141 | } |
4142 | ||
4143 | int | |
4144 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4145 | struct drm_file *file_priv) | |
4146 | { | |
0206e353 | 4147 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4148 | } |
4149 | ||
3ef94daa CW |
4150 | int |
4151 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4152 | struct drm_file *file_priv) | |
4153 | { | |
4154 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4155 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4156 | int ret; |
3ef94daa CW |
4157 | |
4158 | switch (args->madv) { | |
4159 | case I915_MADV_DONTNEED: | |
4160 | case I915_MADV_WILLNEED: | |
4161 | break; | |
4162 | default: | |
4163 | return -EINVAL; | |
4164 | } | |
4165 | ||
1d7cfea1 CW |
4166 | ret = i915_mutex_lock_interruptible(dev); |
4167 | if (ret) | |
4168 | return ret; | |
4169 | ||
05394f39 | 4170 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4171 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4172 | ret = -ENOENT; |
4173 | goto unlock; | |
3ef94daa | 4174 | } |
3ef94daa | 4175 | |
d7f46fc4 | 4176 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4177 | ret = -EINVAL; |
4178 | goto out; | |
3ef94daa CW |
4179 | } |
4180 | ||
05394f39 CW |
4181 | if (obj->madv != __I915_MADV_PURGED) |
4182 | obj->madv = args->madv; | |
3ef94daa | 4183 | |
6c085a72 CW |
4184 | /* if the object is no longer attached, discard its backing storage */ |
4185 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4186 | i915_gem_object_truncate(obj); |
4187 | ||
05394f39 | 4188 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4189 | |
1d7cfea1 | 4190 | out: |
05394f39 | 4191 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4192 | unlock: |
3ef94daa | 4193 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4194 | return ret; |
3ef94daa CW |
4195 | } |
4196 | ||
37e680a1 CW |
4197 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4198 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4199 | { |
35c20a60 | 4200 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4201 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4202 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4203 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4204 | |
37e680a1 CW |
4205 | obj->ops = ops; |
4206 | ||
0327d6ba CW |
4207 | obj->fence_reg = I915_FENCE_REG_NONE; |
4208 | obj->madv = I915_MADV_WILLNEED; | |
4209 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4210 | obj->map_and_fenceable = true; | |
4211 | ||
4212 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4213 | } | |
4214 | ||
37e680a1 CW |
4215 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4216 | .get_pages = i915_gem_object_get_pages_gtt, | |
4217 | .put_pages = i915_gem_object_put_pages_gtt, | |
4218 | }; | |
4219 | ||
05394f39 CW |
4220 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4221 | size_t size) | |
ac52bc56 | 4222 | { |
c397b908 | 4223 | struct drm_i915_gem_object *obj; |
5949eac4 | 4224 | struct address_space *mapping; |
1a240d4d | 4225 | gfp_t mask; |
ac52bc56 | 4226 | |
42dcedd4 | 4227 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4228 | if (obj == NULL) |
4229 | return NULL; | |
673a394b | 4230 | |
c397b908 | 4231 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4232 | i915_gem_object_free(obj); |
c397b908 DV |
4233 | return NULL; |
4234 | } | |
673a394b | 4235 | |
bed1ea95 CW |
4236 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4237 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4238 | /* 965gm cannot relocate objects above 4GiB. */ | |
4239 | mask &= ~__GFP_HIGHMEM; | |
4240 | mask |= __GFP_DMA32; | |
4241 | } | |
4242 | ||
496ad9aa | 4243 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4244 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4245 | |
37e680a1 | 4246 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4247 | |
c397b908 DV |
4248 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4249 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4250 | |
3d29b842 ED |
4251 | if (HAS_LLC(dev)) { |
4252 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4253 | * cache) for about a 10% performance improvement |
4254 | * compared to uncached. Graphics requests other than | |
4255 | * display scanout are coherent with the CPU in | |
4256 | * accessing this cache. This means in this mode we | |
4257 | * don't need to clflush on the CPU side, and on the | |
4258 | * GPU side we only need to flush internal caches to | |
4259 | * get data visible to the CPU. | |
4260 | * | |
4261 | * However, we maintain the display planes as UC, and so | |
4262 | * need to rebind when first used as such. | |
4263 | */ | |
4264 | obj->cache_level = I915_CACHE_LLC; | |
4265 | } else | |
4266 | obj->cache_level = I915_CACHE_NONE; | |
4267 | ||
d861e338 DV |
4268 | trace_i915_gem_object_create(obj); |
4269 | ||
05394f39 | 4270 | return obj; |
c397b908 DV |
4271 | } |
4272 | ||
1488fc08 | 4273 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4274 | { |
1488fc08 | 4275 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4276 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4277 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4278 | struct i915_vma *vma, *next; |
673a394b | 4279 | |
f65c9168 PZ |
4280 | intel_runtime_pm_get(dev_priv); |
4281 | ||
26e12f89 CW |
4282 | trace_i915_gem_object_destroy(obj); |
4283 | ||
07fe0b12 | 4284 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4285 | int ret; |
4286 | ||
4287 | vma->pin_count = 0; | |
4288 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4289 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4290 | bool was_interruptible; | |
1488fc08 | 4291 | |
07fe0b12 BW |
4292 | was_interruptible = dev_priv->mm.interruptible; |
4293 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4294 | |
07fe0b12 | 4295 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4296 | |
07fe0b12 BW |
4297 | dev_priv->mm.interruptible = was_interruptible; |
4298 | } | |
1488fc08 CW |
4299 | } |
4300 | ||
00731155 CW |
4301 | i915_gem_object_detach_phys(obj); |
4302 | ||
1d64ae71 BW |
4303 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4304 | * before progressing. */ | |
4305 | if (obj->stolen) | |
4306 | i915_gem_object_unpin_pages(obj); | |
4307 | ||
401c29f6 BW |
4308 | if (WARN_ON(obj->pages_pin_count)) |
4309 | obj->pages_pin_count = 0; | |
37e680a1 | 4310 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4311 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4312 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4313 | |
9da3da66 CW |
4314 | BUG_ON(obj->pages); |
4315 | ||
2f745ad3 CW |
4316 | if (obj->base.import_attach) |
4317 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4318 | |
05394f39 CW |
4319 | drm_gem_object_release(&obj->base); |
4320 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4321 | |
05394f39 | 4322 | kfree(obj->bit_17); |
42dcedd4 | 4323 | i915_gem_object_free(obj); |
f65c9168 PZ |
4324 | |
4325 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4326 | } |
4327 | ||
e656a6cb | 4328 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4329 | struct i915_address_space *vm) |
e656a6cb DV |
4330 | { |
4331 | struct i915_vma *vma; | |
4332 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4333 | if (vma->vm == vm) | |
4334 | return vma; | |
4335 | ||
4336 | return NULL; | |
4337 | } | |
4338 | ||
2f633156 BW |
4339 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4340 | { | |
4341 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4342 | |
4343 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4344 | if (!list_empty(&vma->exec_list)) | |
4345 | return; | |
4346 | ||
8b9c2b94 | 4347 | list_del(&vma->vma_link); |
b93dab6e | 4348 | |
2f633156 BW |
4349 | kfree(vma); |
4350 | } | |
4351 | ||
29105ccc | 4352 | int |
45c5f202 | 4353 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4354 | { |
3e31c6c0 | 4355 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4356 | int ret = 0; |
28dfe52a | 4357 | |
45c5f202 | 4358 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4359 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4360 | goto err; |
28dfe52a | 4361 | |
b2da9fe5 | 4362 | ret = i915_gpu_idle(dev); |
f7403347 | 4363 | if (ret) |
45c5f202 | 4364 | goto err; |
f7403347 | 4365 | |
b2da9fe5 | 4366 | i915_gem_retire_requests(dev); |
673a394b | 4367 | |
29105ccc | 4368 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4369 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4370 | i915_gem_evict_everything(dev); |
29105ccc | 4371 | |
29105ccc | 4372 | i915_kernel_lost_context(dev); |
6dbe2772 | 4373 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4374 | |
45c5f202 CW |
4375 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4376 | * We need to replace this with a semaphore, or something. | |
4377 | * And not confound ums.mm_suspended! | |
4378 | */ | |
4379 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4380 | DRIVER_MODESET); | |
4381 | mutex_unlock(&dev->struct_mutex); | |
4382 | ||
4383 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4384 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
b29c19b6 | 4385 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4386 | |
673a394b | 4387 | return 0; |
45c5f202 CW |
4388 | |
4389 | err: | |
4390 | mutex_unlock(&dev->struct_mutex); | |
4391 | return ret; | |
673a394b EA |
4392 | } |
4393 | ||
c3787e2e | 4394 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice) |
b9524a1e | 4395 | { |
c3787e2e | 4396 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4397 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4398 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4399 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4400 | int i, ret; |
b9524a1e | 4401 | |
040d2baa | 4402 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4403 | return 0; |
b9524a1e | 4404 | |
c3787e2e BW |
4405 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4406 | if (ret) | |
4407 | return ret; | |
b9524a1e | 4408 | |
c3787e2e BW |
4409 | /* |
4410 | * Note: We do not worry about the concurrent register cacheline hang | |
4411 | * here because no other code should access these registers other than | |
4412 | * at initialization time. | |
4413 | */ | |
b9524a1e | 4414 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4415 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4416 | intel_ring_emit(ring, reg_base + i); | |
4417 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4418 | } |
4419 | ||
c3787e2e | 4420 | intel_ring_advance(ring); |
b9524a1e | 4421 | |
c3787e2e | 4422 | return ret; |
b9524a1e BW |
4423 | } |
4424 | ||
f691e2f4 DV |
4425 | void i915_gem_init_swizzling(struct drm_device *dev) |
4426 | { | |
3e31c6c0 | 4427 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4428 | |
11782b02 | 4429 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4430 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4431 | return; | |
4432 | ||
4433 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4434 | DISP_TILE_SURFACE_SWIZZLING); | |
4435 | ||
11782b02 DV |
4436 | if (IS_GEN5(dev)) |
4437 | return; | |
4438 | ||
f691e2f4 DV |
4439 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4440 | if (IS_GEN6(dev)) | |
6b26c86d | 4441 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4442 | else if (IS_GEN7(dev)) |
6b26c86d | 4443 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4444 | else if (IS_GEN8(dev)) |
4445 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4446 | else |
4447 | BUG(); | |
f691e2f4 | 4448 | } |
e21af88d | 4449 | |
67b1b571 CW |
4450 | static bool |
4451 | intel_enable_blt(struct drm_device *dev) | |
4452 | { | |
4453 | if (!HAS_BLT(dev)) | |
4454 | return false; | |
4455 | ||
4456 | /* The blitter was dysfunctional on early prototypes */ | |
4457 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4458 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4459 | " graphics performance will be degraded.\n"); | |
4460 | return false; | |
4461 | } | |
4462 | ||
4463 | return true; | |
4464 | } | |
4465 | ||
4fc7c971 | 4466 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4467 | { |
4fc7c971 | 4468 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4469 | int ret; |
68f95ba9 | 4470 | |
5c1143bb | 4471 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4472 | if (ret) |
b6913e4b | 4473 | return ret; |
68f95ba9 CW |
4474 | |
4475 | if (HAS_BSD(dev)) { | |
5c1143bb | 4476 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4477 | if (ret) |
4478 | goto cleanup_render_ring; | |
d1b851fc | 4479 | } |
68f95ba9 | 4480 | |
67b1b571 | 4481 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4482 | ret = intel_init_blt_ring_buffer(dev); |
4483 | if (ret) | |
4484 | goto cleanup_bsd_ring; | |
4485 | } | |
4486 | ||
9a8a2213 BW |
4487 | if (HAS_VEBOX(dev)) { |
4488 | ret = intel_init_vebox_ring_buffer(dev); | |
4489 | if (ret) | |
4490 | goto cleanup_blt_ring; | |
4491 | } | |
4492 | ||
4493 | ||
99433931 | 4494 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4495 | if (ret) |
9a8a2213 | 4496 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4497 | |
4498 | return 0; | |
4499 | ||
9a8a2213 BW |
4500 | cleanup_vebox_ring: |
4501 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4502 | cleanup_blt_ring: |
4503 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4504 | cleanup_bsd_ring: | |
4505 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4506 | cleanup_render_ring: | |
4507 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4508 | ||
4509 | return ret; | |
4510 | } | |
4511 | ||
4512 | int | |
4513 | i915_gem_init_hw(struct drm_device *dev) | |
4514 | { | |
3e31c6c0 | 4515 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4516 | int ret, i; |
4fc7c971 BW |
4517 | |
4518 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4519 | return -EIO; | |
4520 | ||
59124506 | 4521 | if (dev_priv->ellc_size) |
05e21cc4 | 4522 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4523 | |
0bf21347 VS |
4524 | if (IS_HASWELL(dev)) |
4525 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4526 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4527 | |
88a2b2a3 | 4528 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4529 | if (IS_IVYBRIDGE(dev)) { |
4530 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4531 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4532 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4533 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4534 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4535 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4536 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4537 | } | |
88a2b2a3 BW |
4538 | } |
4539 | ||
4fc7c971 BW |
4540 | i915_gem_init_swizzling(dev); |
4541 | ||
4542 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4543 | if (ret) |
4544 | return ret; | |
4545 | ||
c3787e2e BW |
4546 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4547 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4548 | ||
254f965c | 4549 | /* |
2fa48d8d BW |
4550 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4551 | * default context switch however is something we'd like to do after | |
4552 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4553 | * goes with our code better). Context switching requires rings (for | |
4554 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4555 | */ |
2fa48d8d | 4556 | ret = i915_gem_context_enable(dev_priv); |
8245be31 | 4557 | if (ret) { |
2fa48d8d BW |
4558 | DRM_ERROR("Context enable failed %d\n", ret); |
4559 | goto err_out; | |
b7c36d25 | 4560 | } |
e21af88d | 4561 | |
68f95ba9 | 4562 | return 0; |
2fa48d8d BW |
4563 | |
4564 | err_out: | |
4565 | i915_gem_cleanup_ringbuffer(dev); | |
4566 | return ret; | |
8187a2b7 ZN |
4567 | } |
4568 | ||
1070a42b CW |
4569 | int i915_gem_init(struct drm_device *dev) |
4570 | { | |
4571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4572 | int ret; |
4573 | ||
1070a42b | 4574 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4575 | |
4576 | if (IS_VALLEYVIEW(dev)) { | |
4577 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4578 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4579 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4580 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4581 | } | |
4582 | ||
d7e5008f | 4583 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4584 | |
2fa48d8d | 4585 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4586 | if (ret) { |
4587 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4588 | return ret; |
e3848694 | 4589 | } |
2fa48d8d | 4590 | |
1070a42b CW |
4591 | ret = i915_gem_init_hw(dev); |
4592 | mutex_unlock(&dev->struct_mutex); | |
4593 | if (ret) { | |
bdf4fd7e | 4594 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
2fa48d8d | 4595 | i915_gem_context_fini(dev); |
c39538a8 | 4596 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
1070a42b CW |
4597 | return ret; |
4598 | } | |
4599 | ||
53ca26ca DV |
4600 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4601 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4602 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4603 | return 0; |
4604 | } | |
4605 | ||
8187a2b7 ZN |
4606 | void |
4607 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4608 | { | |
3e31c6c0 | 4609 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4610 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4611 | int i; |
8187a2b7 | 4612 | |
b4519513 CW |
4613 | for_each_ring(ring, dev_priv, i) |
4614 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4615 | } |
4616 | ||
673a394b EA |
4617 | int |
4618 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4619 | struct drm_file *file_priv) | |
4620 | { | |
db1b76ca | 4621 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4622 | int ret; |
673a394b | 4623 | |
79e53945 JB |
4624 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4625 | return 0; | |
4626 | ||
1f83fee0 | 4627 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4628 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4629 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4630 | } |
4631 | ||
673a394b | 4632 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4633 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4634 | |
f691e2f4 | 4635 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4636 | if (ret != 0) { |
4637 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4638 | return ret; |
d816f6ac | 4639 | } |
9bb2d6f9 | 4640 | |
5cef07e1 | 4641 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4642 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4643 | |
5f35308b CW |
4644 | ret = drm_irq_install(dev); |
4645 | if (ret) | |
4646 | goto cleanup_ringbuffer; | |
dbb19d30 | 4647 | |
673a394b | 4648 | return 0; |
5f35308b CW |
4649 | |
4650 | cleanup_ringbuffer: | |
4651 | mutex_lock(&dev->struct_mutex); | |
4652 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4653 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4654 | mutex_unlock(&dev->struct_mutex); |
4655 | ||
4656 | return ret; | |
673a394b EA |
4657 | } |
4658 | ||
4659 | int | |
4660 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4661 | struct drm_file *file_priv) | |
4662 | { | |
79e53945 JB |
4663 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4664 | return 0; | |
4665 | ||
dbb19d30 | 4666 | drm_irq_uninstall(dev); |
db1b76ca | 4667 | |
45c5f202 | 4668 | return i915_gem_suspend(dev); |
673a394b EA |
4669 | } |
4670 | ||
4671 | void | |
4672 | i915_gem_lastclose(struct drm_device *dev) | |
4673 | { | |
4674 | int ret; | |
673a394b | 4675 | |
e806b495 EA |
4676 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4677 | return; | |
4678 | ||
45c5f202 | 4679 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4680 | if (ret) |
4681 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4682 | } |
4683 | ||
64193406 CW |
4684 | static void |
4685 | init_ring_lists(struct intel_ring_buffer *ring) | |
4686 | { | |
4687 | INIT_LIST_HEAD(&ring->active_list); | |
4688 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4689 | } |
4690 | ||
7e0d96bc BW |
4691 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4692 | struct i915_address_space *vm) | |
fc8c067e | 4693 | { |
7e0d96bc BW |
4694 | if (!i915_is_ggtt(vm)) |
4695 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4696 | vm->dev = dev_priv->dev; |
4697 | INIT_LIST_HEAD(&vm->active_list); | |
4698 | INIT_LIST_HEAD(&vm->inactive_list); | |
4699 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4700 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4701 | } |
4702 | ||
673a394b EA |
4703 | void |
4704 | i915_gem_load(struct drm_device *dev) | |
4705 | { | |
3e31c6c0 | 4706 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4707 | int i; |
4708 | ||
4709 | dev_priv->slab = | |
4710 | kmem_cache_create("i915_gem_object", | |
4711 | sizeof(struct drm_i915_gem_object), 0, | |
4712 | SLAB_HWCACHE_ALIGN, | |
4713 | NULL); | |
673a394b | 4714 | |
fc8c067e BW |
4715 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4716 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4717 | ||
a33afea5 | 4718 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4719 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4720 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4721 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4722 | for (i = 0; i < I915_NUM_RINGS; i++) |
4723 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4724 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4725 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4726 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4727 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4728 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4729 | i915_gem_idle_work_handler); | |
1f83fee0 | 4730 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4731 | |
94400120 DA |
4732 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4733 | if (IS_GEN3(dev)) { | |
50743298 DV |
4734 | I915_WRITE(MI_ARB_STATE, |
4735 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4736 | } |
4737 | ||
72bfa19c CW |
4738 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4739 | ||
de151cf6 | 4740 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4741 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4742 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4743 | |
42b5aeab VS |
4744 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4745 | dev_priv->num_fence_regs = 32; | |
4746 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4747 | dev_priv->num_fence_regs = 16; |
4748 | else | |
4749 | dev_priv->num_fence_regs = 8; | |
4750 | ||
b5aa8a0f | 4751 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4752 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4753 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4754 | |
673a394b | 4755 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4756 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4757 | |
ce453d81 CW |
4758 | dev_priv->mm.interruptible = true; |
4759 | ||
7dc19d5a DC |
4760 | dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan; |
4761 | dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count; | |
17250b71 CW |
4762 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
4763 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4764 | } |
71acb5eb | 4765 | |
f787a5f5 | 4766 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4767 | { |
f787a5f5 | 4768 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4769 | |
b29c19b6 CW |
4770 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4771 | ||
b962442e EA |
4772 | /* Clean up our request list when the client is going away, so that |
4773 | * later retire_requests won't dereference our soon-to-be-gone | |
4774 | * file_priv. | |
4775 | */ | |
1c25595f | 4776 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4777 | while (!list_empty(&file_priv->mm.request_list)) { |
4778 | struct drm_i915_gem_request *request; | |
4779 | ||
4780 | request = list_first_entry(&file_priv->mm.request_list, | |
4781 | struct drm_i915_gem_request, | |
4782 | client_list); | |
4783 | list_del(&request->client_list); | |
4784 | request->file_priv = NULL; | |
4785 | } | |
1c25595f | 4786 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4787 | } |
31169714 | 4788 | |
b29c19b6 CW |
4789 | static void |
4790 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
4791 | { | |
4792 | struct drm_i915_file_private *file_priv = | |
4793 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
4794 | ||
4795 | atomic_set(&file_priv->rps_wait_boost, false); | |
4796 | } | |
4797 | ||
4798 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4799 | { | |
4800 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4801 | int ret; |
b29c19b6 CW |
4802 | |
4803 | DRM_DEBUG_DRIVER("\n"); | |
4804 | ||
4805 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4806 | if (!file_priv) | |
4807 | return -ENOMEM; | |
4808 | ||
4809 | file->driver_priv = file_priv; | |
4810 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 4811 | file_priv->file = file; |
b29c19b6 CW |
4812 | |
4813 | spin_lock_init(&file_priv->mm.lock); | |
4814 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4815 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
4816 | i915_gem_file_idle_work_handler); | |
4817 | ||
e422b888 BW |
4818 | ret = i915_gem_context_open(dev, file); |
4819 | if (ret) | |
4820 | kfree(file_priv); | |
b29c19b6 | 4821 | |
e422b888 | 4822 | return ret; |
b29c19b6 CW |
4823 | } |
4824 | ||
5774506f CW |
4825 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4826 | { | |
4827 | if (!mutex_is_locked(mutex)) | |
4828 | return false; | |
4829 | ||
4830 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4831 | return mutex->owner == task; | |
4832 | #else | |
4833 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4834 | return false; | |
4835 | #endif | |
4836 | } | |
4837 | ||
7dc19d5a DC |
4838 | static unsigned long |
4839 | i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc) | |
31169714 | 4840 | { |
17250b71 CW |
4841 | struct drm_i915_private *dev_priv = |
4842 | container_of(shrinker, | |
4843 | struct drm_i915_private, | |
4844 | mm.inactive_shrinker); | |
4845 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4846 | struct drm_i915_gem_object *obj; |
5774506f | 4847 | bool unlock = true; |
7dc19d5a | 4848 | unsigned long count; |
17250b71 | 4849 | |
5774506f CW |
4850 | if (!mutex_trylock(&dev->struct_mutex)) { |
4851 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 4852 | return 0; |
5774506f | 4853 | |
677feac2 | 4854 | if (dev_priv->mm.shrinker_no_lock_stealing) |
d3227046 | 4855 | return 0; |
677feac2 | 4856 | |
5774506f CW |
4857 | unlock = false; |
4858 | } | |
31169714 | 4859 | |
7dc19d5a | 4860 | count = 0; |
35c20a60 | 4861 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 4862 | if (obj->pages_pin_count == 0) |
7dc19d5a | 4863 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
4864 | |
4865 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4866 | if (obj->active) | |
4867 | continue; | |
4868 | ||
d7f46fc4 | 4869 | if (!i915_gem_obj_is_pinned(obj) && obj->pages_pin_count == 0) |
7dc19d5a | 4870 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 4871 | } |
17250b71 | 4872 | |
5774506f CW |
4873 | if (unlock) |
4874 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 4875 | |
7dc19d5a | 4876 | return count; |
31169714 | 4877 | } |
a70a3148 BW |
4878 | |
4879 | /* All the new VM stuff */ | |
4880 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4881 | struct i915_address_space *vm) | |
4882 | { | |
4883 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4884 | struct i915_vma *vma; | |
4885 | ||
6f425321 BW |
4886 | if (!dev_priv->mm.aliasing_ppgtt || |
4887 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
4888 | vm = &dev_priv->gtt.base; |
4889 | ||
4890 | BUG_ON(list_empty(&o->vma_list)); | |
4891 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4892 | if (vma->vm == vm) | |
4893 | return vma->node.start; | |
4894 | ||
4895 | } | |
4896 | return -1; | |
4897 | } | |
4898 | ||
4899 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4900 | struct i915_address_space *vm) | |
4901 | { | |
4902 | struct i915_vma *vma; | |
4903 | ||
4904 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 4905 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4906 | return true; |
4907 | ||
4908 | return false; | |
4909 | } | |
4910 | ||
4911 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
4912 | { | |
5a1d5eb0 | 4913 | struct i915_vma *vma; |
a70a3148 | 4914 | |
5a1d5eb0 CW |
4915 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4916 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
4917 | return true; |
4918 | ||
4919 | return false; | |
4920 | } | |
4921 | ||
4922 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
4923 | struct i915_address_space *vm) | |
4924 | { | |
4925 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4926 | struct i915_vma *vma; | |
4927 | ||
6f425321 BW |
4928 | if (!dev_priv->mm.aliasing_ppgtt || |
4929 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
4930 | vm = &dev_priv->gtt.base; |
4931 | ||
4932 | BUG_ON(list_empty(&o->vma_list)); | |
4933 | ||
4934 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
4935 | if (vma->vm == vm) | |
4936 | return vma->node.size; | |
4937 | ||
4938 | return 0; | |
4939 | } | |
4940 | ||
7dc19d5a DC |
4941 | static unsigned long |
4942 | i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc) | |
4943 | { | |
4944 | struct drm_i915_private *dev_priv = | |
4945 | container_of(shrinker, | |
4946 | struct drm_i915_private, | |
4947 | mm.inactive_shrinker); | |
4948 | struct drm_device *dev = dev_priv->dev; | |
7dc19d5a DC |
4949 | unsigned long freed; |
4950 | bool unlock = true; | |
4951 | ||
4952 | if (!mutex_trylock(&dev->struct_mutex)) { | |
4953 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 4954 | return SHRINK_STOP; |
7dc19d5a DC |
4955 | |
4956 | if (dev_priv->mm.shrinker_no_lock_stealing) | |
d3227046 | 4957 | return SHRINK_STOP; |
7dc19d5a DC |
4958 | |
4959 | unlock = false; | |
4960 | } | |
4961 | ||
d9973b43 CW |
4962 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
4963 | if (freed < sc->nr_to_scan) | |
4964 | freed += __i915_gem_shrink(dev_priv, | |
4965 | sc->nr_to_scan - freed, | |
4966 | false); | |
4967 | if (freed < sc->nr_to_scan) | |
7dc19d5a DC |
4968 | freed += i915_gem_shrink_all(dev_priv); |
4969 | ||
4970 | if (unlock) | |
4971 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 4972 | |
7dc19d5a DC |
4973 | return freed; |
4974 | } | |
5c2abbea BW |
4975 | |
4976 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
4977 | { | |
4978 | struct i915_vma *vma; | |
4979 | ||
4980 | if (WARN_ON(list_empty(&obj->vma_list))) | |
4981 | return NULL; | |
4982 | ||
4983 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
6e164c33 | 4984 | if (vma->vm != obj_to_ggtt(obj)) |
5c2abbea BW |
4985 | return NULL; |
4986 | ||
4987 | return vma; | |
4988 | } |