Commit | Line | Data |
---|---|---|
673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
c8725f3d CW |
46 | static void |
47 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
48 | ||
61050808 CW |
49 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
50 | struct drm_i915_gem_object *obj); | |
51 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
52 | struct drm_i915_fence_reg *fence, | |
53 | bool enable); | |
54 | ||
c76ce038 CW |
55 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
56 | enum i915_cache_level level) | |
57 | { | |
58 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
59 | } | |
60 | ||
2c22569b CW |
61 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
62 | { | |
63 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
64 | return true; | |
65 | ||
66 | return obj->pin_display; | |
67 | } | |
68 | ||
61050808 CW |
69 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
70 | { | |
71 | if (obj->tiling_mode) | |
72 | i915_gem_release_mmap(obj); | |
73 | ||
74 | /* As we do not have an associated fence register, we will force | |
75 | * a tiling change if we ever need to acquire one. | |
76 | */ | |
5d82e3e6 | 77 | obj->fence_dirty = false; |
61050808 CW |
78 | obj->fence_reg = I915_FENCE_REG_NONE; |
79 | } | |
80 | ||
73aa808f CW |
81 | /* some bookkeeping */ |
82 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
c20e8355 | 85 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
86 | dev_priv->mm.object_count++; |
87 | dev_priv->mm.object_memory += size; | |
c20e8355 | 88 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
89 | } |
90 | ||
91 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
92 | size_t size) | |
93 | { | |
c20e8355 | 94 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
95 | dev_priv->mm.object_count--; |
96 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 97 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
98 | } |
99 | ||
21dd3734 | 100 | static int |
33196ded | 101 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 102 | { |
30dbf0c0 CW |
103 | int ret; |
104 | ||
7abb690a DV |
105 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
106 | i915_terminally_wedged(error)) | |
1f83fee0 | 107 | if (EXIT_COND) |
30dbf0c0 CW |
108 | return 0; |
109 | ||
0a6759c6 DV |
110 | /* |
111 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
112 | * userspace. If it takes that long something really bad is going on and | |
113 | * we should simply try to bail out and fail as gracefully as possible. | |
114 | */ | |
1f83fee0 DV |
115 | ret = wait_event_interruptible_timeout(error->reset_queue, |
116 | EXIT_COND, | |
117 | 10*HZ); | |
0a6759c6 DV |
118 | if (ret == 0) { |
119 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
120 | return -EIO; | |
121 | } else if (ret < 0) { | |
30dbf0c0 | 122 | return ret; |
0a6759c6 | 123 | } |
1f83fee0 | 124 | #undef EXIT_COND |
30dbf0c0 | 125 | |
21dd3734 | 126 | return 0; |
30dbf0c0 CW |
127 | } |
128 | ||
54cf91dc | 129 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 130 | { |
33196ded | 131 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
132 | int ret; |
133 | ||
33196ded | 134 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
135 | if (ret) |
136 | return ret; | |
137 | ||
138 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
139 | if (ret) | |
140 | return ret; | |
141 | ||
23bc5982 | 142 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
143 | return 0; |
144 | } | |
30dbf0c0 | 145 | |
5a125c3c EA |
146 | int |
147 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 148 | struct drm_file *file) |
5a125c3c | 149 | { |
73aa808f | 150 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 151 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
152 | struct drm_i915_gem_object *obj; |
153 | size_t pinned; | |
5a125c3c | 154 | |
6299f992 | 155 | pinned = 0; |
73aa808f | 156 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 157 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 158 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 159 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 160 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 161 | |
853ba5d2 | 162 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 163 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 164 | |
5a125c3c EA |
165 | return 0; |
166 | } | |
167 | ||
6a2c4232 CW |
168 | static int |
169 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 170 | { |
6a2c4232 CW |
171 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
172 | char *vaddr = obj->phys_handle->vaddr; | |
173 | struct sg_table *st; | |
174 | struct scatterlist *sg; | |
175 | int i; | |
00731155 | 176 | |
6a2c4232 CW |
177 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
178 | return -EINVAL; | |
179 | ||
180 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
181 | struct page *page; | |
182 | char *src; | |
183 | ||
184 | page = shmem_read_mapping_page(mapping, i); | |
185 | if (IS_ERR(page)) | |
186 | return PTR_ERR(page); | |
187 | ||
188 | src = kmap_atomic(page); | |
189 | memcpy(vaddr, src, PAGE_SIZE); | |
190 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
191 | kunmap_atomic(src); | |
192 | ||
193 | page_cache_release(page); | |
194 | vaddr += PAGE_SIZE; | |
195 | } | |
196 | ||
197 | i915_gem_chipset_flush(obj->base.dev); | |
198 | ||
199 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
200 | if (st == NULL) | |
201 | return -ENOMEM; | |
202 | ||
203 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
204 | kfree(st); | |
205 | return -ENOMEM; | |
206 | } | |
207 | ||
208 | sg = st->sgl; | |
209 | sg->offset = 0; | |
210 | sg->length = obj->base.size; | |
00731155 | 211 | |
6a2c4232 CW |
212 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
213 | sg_dma_len(sg) = obj->base.size; | |
214 | ||
215 | obj->pages = st; | |
216 | obj->has_dma_mapping = true; | |
217 | return 0; | |
218 | } | |
219 | ||
220 | static void | |
221 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
222 | { | |
223 | int ret; | |
224 | ||
225 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 226 | |
6a2c4232 CW |
227 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
228 | if (ret) { | |
229 | /* In the event of a disaster, abandon all caches and | |
230 | * hope for the best. | |
231 | */ | |
232 | WARN_ON(ret != -EIO); | |
233 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
234 | } | |
235 | ||
236 | if (obj->madv == I915_MADV_DONTNEED) | |
237 | obj->dirty = 0; | |
238 | ||
239 | if (obj->dirty) { | |
00731155 | 240 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 241 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
242 | int i; |
243 | ||
244 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
245 | struct page *page; |
246 | char *dst; | |
247 | ||
248 | page = shmem_read_mapping_page(mapping, i); | |
249 | if (IS_ERR(page)) | |
250 | continue; | |
251 | ||
252 | dst = kmap_atomic(page); | |
253 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
254 | memcpy(dst, vaddr, PAGE_SIZE); | |
255 | kunmap_atomic(dst); | |
256 | ||
257 | set_page_dirty(page); | |
258 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 259 | mark_page_accessed(page); |
6a2c4232 | 260 | page_cache_release(page); |
00731155 CW |
261 | vaddr += PAGE_SIZE; |
262 | } | |
6a2c4232 | 263 | obj->dirty = 0; |
00731155 CW |
264 | } |
265 | ||
6a2c4232 CW |
266 | sg_free_table(obj->pages); |
267 | kfree(obj->pages); | |
268 | ||
269 | obj->has_dma_mapping = false; | |
270 | } | |
271 | ||
272 | static void | |
273 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
274 | { | |
275 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
276 | } | |
277 | ||
278 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
279 | .get_pages = i915_gem_object_get_pages_phys, | |
280 | .put_pages = i915_gem_object_put_pages_phys, | |
281 | .release = i915_gem_object_release_phys, | |
282 | }; | |
283 | ||
284 | static int | |
285 | drop_pages(struct drm_i915_gem_object *obj) | |
286 | { | |
287 | struct i915_vma *vma, *next; | |
288 | int ret; | |
289 | ||
290 | drm_gem_object_reference(&obj->base); | |
291 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) | |
292 | if (i915_vma_unbind(vma)) | |
293 | break; | |
294 | ||
295 | ret = i915_gem_object_put_pages(obj); | |
296 | drm_gem_object_unreference(&obj->base); | |
297 | ||
298 | return ret; | |
00731155 CW |
299 | } |
300 | ||
301 | int | |
302 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
303 | int align) | |
304 | { | |
305 | drm_dma_handle_t *phys; | |
6a2c4232 | 306 | int ret; |
00731155 CW |
307 | |
308 | if (obj->phys_handle) { | |
309 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
310 | return -EBUSY; | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | if (obj->madv != I915_MADV_WILLNEED) | |
316 | return -EFAULT; | |
317 | ||
318 | if (obj->base.filp == NULL) | |
319 | return -EINVAL; | |
320 | ||
6a2c4232 CW |
321 | ret = drop_pages(obj); |
322 | if (ret) | |
323 | return ret; | |
324 | ||
00731155 CW |
325 | /* create a new object */ |
326 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
327 | if (!phys) | |
328 | return -ENOMEM; | |
329 | ||
00731155 | 330 | obj->phys_handle = phys; |
6a2c4232 CW |
331 | obj->ops = &i915_gem_phys_ops; |
332 | ||
333 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
334 | } |
335 | ||
336 | static int | |
337 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
338 | struct drm_i915_gem_pwrite *args, | |
339 | struct drm_file *file_priv) | |
340 | { | |
341 | struct drm_device *dev = obj->base.dev; | |
342 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
343 | char __user *user_data = to_user_ptr(args->data_ptr); | |
063e4e6b | 344 | int ret = 0; |
6a2c4232 CW |
345 | |
346 | /* We manually control the domain here and pretend that it | |
347 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
348 | */ | |
349 | ret = i915_gem_object_wait_rendering(obj, false); | |
350 | if (ret) | |
351 | return ret; | |
00731155 | 352 | |
063e4e6b | 353 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU); |
00731155 CW |
354 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
355 | unsigned long unwritten; | |
356 | ||
357 | /* The physical object once assigned is fixed for the lifetime | |
358 | * of the obj, so we can safely drop the lock and continue | |
359 | * to access vaddr. | |
360 | */ | |
361 | mutex_unlock(&dev->struct_mutex); | |
362 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
363 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
364 | if (unwritten) { |
365 | ret = -EFAULT; | |
366 | goto out; | |
367 | } | |
00731155 CW |
368 | } |
369 | ||
6a2c4232 | 370 | drm_clflush_virt_range(vaddr, args->size); |
00731155 | 371 | i915_gem_chipset_flush(dev); |
063e4e6b PZ |
372 | |
373 | out: | |
374 | intel_fb_obj_flush(obj, false); | |
375 | return ret; | |
00731155 CW |
376 | } |
377 | ||
42dcedd4 CW |
378 | void *i915_gem_object_alloc(struct drm_device *dev) |
379 | { | |
380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 381 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
382 | } |
383 | ||
384 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
385 | { | |
386 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
387 | kmem_cache_free(dev_priv->slab, obj); | |
388 | } | |
389 | ||
ff72145b DA |
390 | static int |
391 | i915_gem_create(struct drm_file *file, | |
392 | struct drm_device *dev, | |
393 | uint64_t size, | |
394 | uint32_t *handle_p) | |
673a394b | 395 | { |
05394f39 | 396 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
397 | int ret; |
398 | u32 handle; | |
673a394b | 399 | |
ff72145b | 400 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
401 | if (size == 0) |
402 | return -EINVAL; | |
673a394b EA |
403 | |
404 | /* Allocate the new object */ | |
ff72145b | 405 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
406 | if (obj == NULL) |
407 | return -ENOMEM; | |
408 | ||
05394f39 | 409 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 410 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
411 | drm_gem_object_unreference_unlocked(&obj->base); |
412 | if (ret) | |
413 | return ret; | |
202f2fef | 414 | |
ff72145b | 415 | *handle_p = handle; |
673a394b EA |
416 | return 0; |
417 | } | |
418 | ||
ff72145b DA |
419 | int |
420 | i915_gem_dumb_create(struct drm_file *file, | |
421 | struct drm_device *dev, | |
422 | struct drm_mode_create_dumb *args) | |
423 | { | |
424 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 425 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
426 | args->size = args->pitch * args->height; |
427 | return i915_gem_create(file, dev, | |
da6b51d0 | 428 | args->size, &args->handle); |
ff72145b DA |
429 | } |
430 | ||
ff72145b DA |
431 | /** |
432 | * Creates a new mm object and returns a handle to it. | |
433 | */ | |
434 | int | |
435 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
436 | struct drm_file *file) | |
437 | { | |
438 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 439 | |
ff72145b | 440 | return i915_gem_create(file, dev, |
da6b51d0 | 441 | args->size, &args->handle); |
ff72145b DA |
442 | } |
443 | ||
8461d226 DV |
444 | static inline int |
445 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
446 | const char *gpu_vaddr, int gpu_offset, | |
447 | int length) | |
448 | { | |
449 | int ret, cpu_offset = 0; | |
450 | ||
451 | while (length > 0) { | |
452 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
453 | int this_length = min(cacheline_end - gpu_offset, length); | |
454 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
455 | ||
456 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
457 | gpu_vaddr + swizzled_gpu_offset, | |
458 | this_length); | |
459 | if (ret) | |
460 | return ret + length; | |
461 | ||
462 | cpu_offset += this_length; | |
463 | gpu_offset += this_length; | |
464 | length -= this_length; | |
465 | } | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
8c59967c | 470 | static inline int |
4f0c7cfb BW |
471 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
472 | const char __user *cpu_vaddr, | |
8c59967c DV |
473 | int length) |
474 | { | |
475 | int ret, cpu_offset = 0; | |
476 | ||
477 | while (length > 0) { | |
478 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
479 | int this_length = min(cacheline_end - gpu_offset, length); | |
480 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
481 | ||
482 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
483 | cpu_vaddr + cpu_offset, | |
484 | this_length); | |
485 | if (ret) | |
486 | return ret + length; | |
487 | ||
488 | cpu_offset += this_length; | |
489 | gpu_offset += this_length; | |
490 | length -= this_length; | |
491 | } | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
4c914c0c BV |
496 | /* |
497 | * Pins the specified object's pages and synchronizes the object with | |
498 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
499 | * flush the object from the CPU cache. | |
500 | */ | |
501 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
502 | int *needs_clflush) | |
503 | { | |
504 | int ret; | |
505 | ||
506 | *needs_clflush = 0; | |
507 | ||
508 | if (!obj->base.filp) | |
509 | return -EINVAL; | |
510 | ||
511 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
512 | /* If we're not in the cpu read domain, set ourself into the gtt | |
513 | * read domain and manually flush cachelines (if required). This | |
514 | * optimizes for the case when the gpu will dirty the data | |
515 | * anyway again before the next pread happens. */ | |
516 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
517 | obj->cache_level); | |
518 | ret = i915_gem_object_wait_rendering(obj, true); | |
519 | if (ret) | |
520 | return ret; | |
c8725f3d CW |
521 | |
522 | i915_gem_object_retire(obj); | |
4c914c0c BV |
523 | } |
524 | ||
525 | ret = i915_gem_object_get_pages(obj); | |
526 | if (ret) | |
527 | return ret; | |
528 | ||
529 | i915_gem_object_pin_pages(obj); | |
530 | ||
531 | return ret; | |
532 | } | |
533 | ||
d174bd64 DV |
534 | /* Per-page copy function for the shmem pread fastpath. |
535 | * Flushes invalid cachelines before reading the target if | |
536 | * needs_clflush is set. */ | |
eb01459f | 537 | static int |
d174bd64 DV |
538 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
539 | char __user *user_data, | |
540 | bool page_do_bit17_swizzling, bool needs_clflush) | |
541 | { | |
542 | char *vaddr; | |
543 | int ret; | |
544 | ||
e7e58eb5 | 545 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
546 | return -EINVAL; |
547 | ||
548 | vaddr = kmap_atomic(page); | |
549 | if (needs_clflush) | |
550 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
551 | page_length); | |
552 | ret = __copy_to_user_inatomic(user_data, | |
553 | vaddr + shmem_page_offset, | |
554 | page_length); | |
555 | kunmap_atomic(vaddr); | |
556 | ||
f60d7f0c | 557 | return ret ? -EFAULT : 0; |
d174bd64 DV |
558 | } |
559 | ||
23c18c71 DV |
560 | static void |
561 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
562 | bool swizzled) | |
563 | { | |
e7e58eb5 | 564 | if (unlikely(swizzled)) { |
23c18c71 DV |
565 | unsigned long start = (unsigned long) addr; |
566 | unsigned long end = (unsigned long) addr + length; | |
567 | ||
568 | /* For swizzling simply ensure that we always flush both | |
569 | * channels. Lame, but simple and it works. Swizzled | |
570 | * pwrite/pread is far from a hotpath - current userspace | |
571 | * doesn't use it at all. */ | |
572 | start = round_down(start, 128); | |
573 | end = round_up(end, 128); | |
574 | ||
575 | drm_clflush_virt_range((void *)start, end - start); | |
576 | } else { | |
577 | drm_clflush_virt_range(addr, length); | |
578 | } | |
579 | ||
580 | } | |
581 | ||
d174bd64 DV |
582 | /* Only difference to the fast-path function is that this can handle bit17 |
583 | * and uses non-atomic copy and kmap functions. */ | |
584 | static int | |
585 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
586 | char __user *user_data, | |
587 | bool page_do_bit17_swizzling, bool needs_clflush) | |
588 | { | |
589 | char *vaddr; | |
590 | int ret; | |
591 | ||
592 | vaddr = kmap(page); | |
593 | if (needs_clflush) | |
23c18c71 DV |
594 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
595 | page_length, | |
596 | page_do_bit17_swizzling); | |
d174bd64 DV |
597 | |
598 | if (page_do_bit17_swizzling) | |
599 | ret = __copy_to_user_swizzled(user_data, | |
600 | vaddr, shmem_page_offset, | |
601 | page_length); | |
602 | else | |
603 | ret = __copy_to_user(user_data, | |
604 | vaddr + shmem_page_offset, | |
605 | page_length); | |
606 | kunmap(page); | |
607 | ||
f60d7f0c | 608 | return ret ? - EFAULT : 0; |
d174bd64 DV |
609 | } |
610 | ||
eb01459f | 611 | static int |
dbf7bff0 DV |
612 | i915_gem_shmem_pread(struct drm_device *dev, |
613 | struct drm_i915_gem_object *obj, | |
614 | struct drm_i915_gem_pread *args, | |
615 | struct drm_file *file) | |
eb01459f | 616 | { |
8461d226 | 617 | char __user *user_data; |
eb01459f | 618 | ssize_t remain; |
8461d226 | 619 | loff_t offset; |
eb2c0c81 | 620 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 621 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 622 | int prefaulted = 0; |
8489731c | 623 | int needs_clflush = 0; |
67d5a50c | 624 | struct sg_page_iter sg_iter; |
eb01459f | 625 | |
2bb4629a | 626 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
627 | remain = args->size; |
628 | ||
8461d226 | 629 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 630 | |
4c914c0c | 631 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
632 | if (ret) |
633 | return ret; | |
634 | ||
8461d226 | 635 | offset = args->offset; |
eb01459f | 636 | |
67d5a50c ID |
637 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
638 | offset >> PAGE_SHIFT) { | |
2db76d7c | 639 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
640 | |
641 | if (remain <= 0) | |
642 | break; | |
643 | ||
eb01459f EA |
644 | /* Operation in this page |
645 | * | |
eb01459f | 646 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
647 | * page_length = bytes to copy for this page |
648 | */ | |
c8cbbb8b | 649 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
650 | page_length = remain; |
651 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
652 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 653 | |
8461d226 DV |
654 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
655 | (page_to_phys(page) & (1 << 17)) != 0; | |
656 | ||
d174bd64 DV |
657 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
658 | user_data, page_do_bit17_swizzling, | |
659 | needs_clflush); | |
660 | if (ret == 0) | |
661 | goto next_page; | |
dbf7bff0 | 662 | |
dbf7bff0 DV |
663 | mutex_unlock(&dev->struct_mutex); |
664 | ||
d330a953 | 665 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 666 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
667 | /* Userspace is tricking us, but we've already clobbered |
668 | * its pages with the prefault and promised to write the | |
669 | * data up to the first fault. Hence ignore any errors | |
670 | * and just continue. */ | |
671 | (void)ret; | |
672 | prefaulted = 1; | |
673 | } | |
eb01459f | 674 | |
d174bd64 DV |
675 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
676 | user_data, page_do_bit17_swizzling, | |
677 | needs_clflush); | |
eb01459f | 678 | |
dbf7bff0 | 679 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 680 | |
f60d7f0c | 681 | if (ret) |
8461d226 | 682 | goto out; |
8461d226 | 683 | |
17793c9a | 684 | next_page: |
eb01459f | 685 | remain -= page_length; |
8461d226 | 686 | user_data += page_length; |
eb01459f EA |
687 | offset += page_length; |
688 | } | |
689 | ||
4f27b75d | 690 | out: |
f60d7f0c CW |
691 | i915_gem_object_unpin_pages(obj); |
692 | ||
eb01459f EA |
693 | return ret; |
694 | } | |
695 | ||
673a394b EA |
696 | /** |
697 | * Reads data from the object referenced by handle. | |
698 | * | |
699 | * On error, the contents of *data are undefined. | |
700 | */ | |
701 | int | |
702 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 703 | struct drm_file *file) |
673a394b EA |
704 | { |
705 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 706 | struct drm_i915_gem_object *obj; |
35b62a89 | 707 | int ret = 0; |
673a394b | 708 | |
51311d0a CW |
709 | if (args->size == 0) |
710 | return 0; | |
711 | ||
712 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 713 | to_user_ptr(args->data_ptr), |
51311d0a CW |
714 | args->size)) |
715 | return -EFAULT; | |
716 | ||
4f27b75d | 717 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 718 | if (ret) |
4f27b75d | 719 | return ret; |
673a394b | 720 | |
05394f39 | 721 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 722 | if (&obj->base == NULL) { |
1d7cfea1 CW |
723 | ret = -ENOENT; |
724 | goto unlock; | |
4f27b75d | 725 | } |
673a394b | 726 | |
7dcd2499 | 727 | /* Bounds check source. */ |
05394f39 CW |
728 | if (args->offset > obj->base.size || |
729 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 730 | ret = -EINVAL; |
35b62a89 | 731 | goto out; |
ce9d419d CW |
732 | } |
733 | ||
1286ff73 DV |
734 | /* prime objects have no backing filp to GEM pread/pwrite |
735 | * pages from. | |
736 | */ | |
737 | if (!obj->base.filp) { | |
738 | ret = -EINVAL; | |
739 | goto out; | |
740 | } | |
741 | ||
db53a302 CW |
742 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
743 | ||
dbf7bff0 | 744 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 745 | |
35b62a89 | 746 | out: |
05394f39 | 747 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 748 | unlock: |
4f27b75d | 749 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 750 | return ret; |
673a394b EA |
751 | } |
752 | ||
0839ccb8 KP |
753 | /* This is the fast write path which cannot handle |
754 | * page faults in the source data | |
9b7530cc | 755 | */ |
0839ccb8 KP |
756 | |
757 | static inline int | |
758 | fast_user_write(struct io_mapping *mapping, | |
759 | loff_t page_base, int page_offset, | |
760 | char __user *user_data, | |
761 | int length) | |
9b7530cc | 762 | { |
4f0c7cfb BW |
763 | void __iomem *vaddr_atomic; |
764 | void *vaddr; | |
0839ccb8 | 765 | unsigned long unwritten; |
9b7530cc | 766 | |
3e4d3af5 | 767 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
768 | /* We can use the cpu mem copy function because this is X86. */ |
769 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
770 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 771 | user_data, length); |
3e4d3af5 | 772 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 773 | return unwritten; |
0839ccb8 KP |
774 | } |
775 | ||
3de09aa3 EA |
776 | /** |
777 | * This is the fast pwrite path, where we copy the data directly from the | |
778 | * user into the GTT, uncached. | |
779 | */ | |
673a394b | 780 | static int |
05394f39 CW |
781 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
782 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 783 | struct drm_i915_gem_pwrite *args, |
05394f39 | 784 | struct drm_file *file) |
673a394b | 785 | { |
3e31c6c0 | 786 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 787 | ssize_t remain; |
0839ccb8 | 788 | loff_t offset, page_base; |
673a394b | 789 | char __user *user_data; |
935aaa69 DV |
790 | int page_offset, page_length, ret; |
791 | ||
1ec9e26d | 792 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
793 | if (ret) |
794 | goto out; | |
795 | ||
796 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
797 | if (ret) | |
798 | goto out_unpin; | |
799 | ||
800 | ret = i915_gem_object_put_fence(obj); | |
801 | if (ret) | |
802 | goto out_unpin; | |
673a394b | 803 | |
2bb4629a | 804 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 805 | remain = args->size; |
673a394b | 806 | |
f343c5f6 | 807 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b | 808 | |
063e4e6b PZ |
809 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT); |
810 | ||
673a394b EA |
811 | while (remain > 0) { |
812 | /* Operation in this page | |
813 | * | |
0839ccb8 KP |
814 | * page_base = page offset within aperture |
815 | * page_offset = offset within page | |
816 | * page_length = bytes to copy for this page | |
673a394b | 817 | */ |
c8cbbb8b CW |
818 | page_base = offset & PAGE_MASK; |
819 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
820 | page_length = remain; |
821 | if ((page_offset + remain) > PAGE_SIZE) | |
822 | page_length = PAGE_SIZE - page_offset; | |
823 | ||
0839ccb8 | 824 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
825 | * source page isn't available. Return the error and we'll |
826 | * retry in the slow path. | |
0839ccb8 | 827 | */ |
5d4545ae | 828 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
829 | page_offset, user_data, page_length)) { |
830 | ret = -EFAULT; | |
063e4e6b | 831 | goto out_flush; |
935aaa69 | 832 | } |
673a394b | 833 | |
0839ccb8 KP |
834 | remain -= page_length; |
835 | user_data += page_length; | |
836 | offset += page_length; | |
673a394b | 837 | } |
673a394b | 838 | |
063e4e6b PZ |
839 | out_flush: |
840 | intel_fb_obj_flush(obj, false); | |
935aaa69 | 841 | out_unpin: |
d7f46fc4 | 842 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 843 | out: |
3de09aa3 | 844 | return ret; |
673a394b EA |
845 | } |
846 | ||
d174bd64 DV |
847 | /* Per-page copy function for the shmem pwrite fastpath. |
848 | * Flushes invalid cachelines before writing to the target if | |
849 | * needs_clflush_before is set and flushes out any written cachelines after | |
850 | * writing if needs_clflush is set. */ | |
3043c60c | 851 | static int |
d174bd64 DV |
852 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
853 | char __user *user_data, | |
854 | bool page_do_bit17_swizzling, | |
855 | bool needs_clflush_before, | |
856 | bool needs_clflush_after) | |
673a394b | 857 | { |
d174bd64 | 858 | char *vaddr; |
673a394b | 859 | int ret; |
3de09aa3 | 860 | |
e7e58eb5 | 861 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 862 | return -EINVAL; |
3de09aa3 | 863 | |
d174bd64 DV |
864 | vaddr = kmap_atomic(page); |
865 | if (needs_clflush_before) | |
866 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
867 | page_length); | |
c2831a94 CW |
868 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
869 | user_data, page_length); | |
d174bd64 DV |
870 | if (needs_clflush_after) |
871 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
872 | page_length); | |
873 | kunmap_atomic(vaddr); | |
3de09aa3 | 874 | |
755d2218 | 875 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
876 | } |
877 | ||
d174bd64 DV |
878 | /* Only difference to the fast-path function is that this can handle bit17 |
879 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 880 | static int |
d174bd64 DV |
881 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
882 | char __user *user_data, | |
883 | bool page_do_bit17_swizzling, | |
884 | bool needs_clflush_before, | |
885 | bool needs_clflush_after) | |
673a394b | 886 | { |
d174bd64 DV |
887 | char *vaddr; |
888 | int ret; | |
e5281ccd | 889 | |
d174bd64 | 890 | vaddr = kmap(page); |
e7e58eb5 | 891 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
892 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
893 | page_length, | |
894 | page_do_bit17_swizzling); | |
d174bd64 DV |
895 | if (page_do_bit17_swizzling) |
896 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
897 | user_data, |
898 | page_length); | |
d174bd64 DV |
899 | else |
900 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
901 | user_data, | |
902 | page_length); | |
903 | if (needs_clflush_after) | |
23c18c71 DV |
904 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
905 | page_length, | |
906 | page_do_bit17_swizzling); | |
d174bd64 | 907 | kunmap(page); |
40123c1f | 908 | |
755d2218 | 909 | return ret ? -EFAULT : 0; |
40123c1f EA |
910 | } |
911 | ||
40123c1f | 912 | static int |
e244a443 DV |
913 | i915_gem_shmem_pwrite(struct drm_device *dev, |
914 | struct drm_i915_gem_object *obj, | |
915 | struct drm_i915_gem_pwrite *args, | |
916 | struct drm_file *file) | |
40123c1f | 917 | { |
40123c1f | 918 | ssize_t remain; |
8c59967c DV |
919 | loff_t offset; |
920 | char __user *user_data; | |
eb2c0c81 | 921 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 922 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 923 | int hit_slowpath = 0; |
58642885 DV |
924 | int needs_clflush_after = 0; |
925 | int needs_clflush_before = 0; | |
67d5a50c | 926 | struct sg_page_iter sg_iter; |
40123c1f | 927 | |
2bb4629a | 928 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
929 | remain = args->size; |
930 | ||
8c59967c | 931 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 932 | |
58642885 DV |
933 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
934 | /* If we're not in the cpu write domain, set ourself into the gtt | |
935 | * write domain and manually flush cachelines (if required). This | |
936 | * optimizes for the case when the gpu will use the data | |
937 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 938 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
939 | ret = i915_gem_object_wait_rendering(obj, false); |
940 | if (ret) | |
941 | return ret; | |
c8725f3d CW |
942 | |
943 | i915_gem_object_retire(obj); | |
58642885 | 944 | } |
c76ce038 CW |
945 | /* Same trick applies to invalidate partially written cachelines read |
946 | * before writing. */ | |
947 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
948 | needs_clflush_before = | |
949 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 950 | |
755d2218 CW |
951 | ret = i915_gem_object_get_pages(obj); |
952 | if (ret) | |
953 | return ret; | |
954 | ||
063e4e6b PZ |
955 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU); |
956 | ||
755d2218 CW |
957 | i915_gem_object_pin_pages(obj); |
958 | ||
673a394b | 959 | offset = args->offset; |
05394f39 | 960 | obj->dirty = 1; |
673a394b | 961 | |
67d5a50c ID |
962 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
963 | offset >> PAGE_SHIFT) { | |
2db76d7c | 964 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 965 | int partial_cacheline_write; |
e5281ccd | 966 | |
9da3da66 CW |
967 | if (remain <= 0) |
968 | break; | |
969 | ||
40123c1f EA |
970 | /* Operation in this page |
971 | * | |
40123c1f | 972 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
973 | * page_length = bytes to copy for this page |
974 | */ | |
c8cbbb8b | 975 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
976 | |
977 | page_length = remain; | |
978 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
979 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 980 | |
58642885 DV |
981 | /* If we don't overwrite a cacheline completely we need to be |
982 | * careful to have up-to-date data by first clflushing. Don't | |
983 | * overcomplicate things and flush the entire patch. */ | |
984 | partial_cacheline_write = needs_clflush_before && | |
985 | ((shmem_page_offset | page_length) | |
986 | & (boot_cpu_data.x86_clflush_size - 1)); | |
987 | ||
8c59967c DV |
988 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
989 | (page_to_phys(page) & (1 << 17)) != 0; | |
990 | ||
d174bd64 DV |
991 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
992 | user_data, page_do_bit17_swizzling, | |
993 | partial_cacheline_write, | |
994 | needs_clflush_after); | |
995 | if (ret == 0) | |
996 | goto next_page; | |
e244a443 DV |
997 | |
998 | hit_slowpath = 1; | |
e244a443 | 999 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1000 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1001 | user_data, page_do_bit17_swizzling, | |
1002 | partial_cacheline_write, | |
1003 | needs_clflush_after); | |
40123c1f | 1004 | |
e244a443 | 1005 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1006 | |
755d2218 | 1007 | if (ret) |
8c59967c | 1008 | goto out; |
8c59967c | 1009 | |
17793c9a | 1010 | next_page: |
40123c1f | 1011 | remain -= page_length; |
8c59967c | 1012 | user_data += page_length; |
40123c1f | 1013 | offset += page_length; |
673a394b EA |
1014 | } |
1015 | ||
fbd5a26d | 1016 | out: |
755d2218 CW |
1017 | i915_gem_object_unpin_pages(obj); |
1018 | ||
e244a443 | 1019 | if (hit_slowpath) { |
8dcf015e DV |
1020 | /* |
1021 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1022 | * cachelines in-line while writing and the object moved | |
1023 | * out of the cpu write domain while we've dropped the lock. | |
1024 | */ | |
1025 | if (!needs_clflush_after && | |
1026 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
1027 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
1028 | i915_gem_chipset_flush(dev); | |
e244a443 | 1029 | } |
8c59967c | 1030 | } |
673a394b | 1031 | |
58642885 | 1032 | if (needs_clflush_after) |
e76e9aeb | 1033 | i915_gem_chipset_flush(dev); |
58642885 | 1034 | |
063e4e6b | 1035 | intel_fb_obj_flush(obj, false); |
40123c1f | 1036 | return ret; |
673a394b EA |
1037 | } |
1038 | ||
1039 | /** | |
1040 | * Writes data to the object referenced by handle. | |
1041 | * | |
1042 | * On error, the contents of the buffer that were to be modified are undefined. | |
1043 | */ | |
1044 | int | |
1045 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1046 | struct drm_file *file) |
673a394b | 1047 | { |
5d77d9c5 | 1048 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1049 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1050 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1051 | int ret; |
1052 | ||
1053 | if (args->size == 0) | |
1054 | return 0; | |
1055 | ||
1056 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1057 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1058 | args->size)) |
1059 | return -EFAULT; | |
1060 | ||
d330a953 | 1061 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1062 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1063 | args->size); | |
1064 | if (ret) | |
1065 | return -EFAULT; | |
1066 | } | |
673a394b | 1067 | |
5d77d9c5 ID |
1068 | intel_runtime_pm_get(dev_priv); |
1069 | ||
fbd5a26d | 1070 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1071 | if (ret) |
5d77d9c5 | 1072 | goto put_rpm; |
1d7cfea1 | 1073 | |
05394f39 | 1074 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1075 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1076 | ret = -ENOENT; |
1077 | goto unlock; | |
fbd5a26d | 1078 | } |
673a394b | 1079 | |
7dcd2499 | 1080 | /* Bounds check destination. */ |
05394f39 CW |
1081 | if (args->offset > obj->base.size || |
1082 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1083 | ret = -EINVAL; |
35b62a89 | 1084 | goto out; |
ce9d419d CW |
1085 | } |
1086 | ||
1286ff73 DV |
1087 | /* prime objects have no backing filp to GEM pread/pwrite |
1088 | * pages from. | |
1089 | */ | |
1090 | if (!obj->base.filp) { | |
1091 | ret = -EINVAL; | |
1092 | goto out; | |
1093 | } | |
1094 | ||
db53a302 CW |
1095 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1096 | ||
935aaa69 | 1097 | ret = -EFAULT; |
673a394b EA |
1098 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1099 | * it would end up going through the fenced access, and we'll get | |
1100 | * different detiling behavior between reading and writing. | |
1101 | * pread/pwrite currently are reading and writing from the CPU | |
1102 | * perspective, requiring manual detiling by the client. | |
1103 | */ | |
2c22569b CW |
1104 | if (obj->tiling_mode == I915_TILING_NONE && |
1105 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1106 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1107 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1108 | /* Note that the gtt paths might fail with non-page-backed user |
1109 | * pointers (e.g. gtt mappings when moving data between | |
1110 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1111 | } |
673a394b | 1112 | |
6a2c4232 CW |
1113 | if (ret == -EFAULT || ret == -ENOSPC) { |
1114 | if (obj->phys_handle) | |
1115 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1116 | else | |
1117 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1118 | } | |
5c0480f2 | 1119 | |
35b62a89 | 1120 | out: |
05394f39 | 1121 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1122 | unlock: |
fbd5a26d | 1123 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1124 | put_rpm: |
1125 | intel_runtime_pm_put(dev_priv); | |
1126 | ||
673a394b EA |
1127 | return ret; |
1128 | } | |
1129 | ||
b361237b | 1130 | int |
33196ded | 1131 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1132 | bool interruptible) |
1133 | { | |
1f83fee0 | 1134 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1135 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1136 | * -EIO unconditionally for these. */ | |
1137 | if (!interruptible) | |
1138 | return -EIO; | |
1139 | ||
1f83fee0 DV |
1140 | /* Recovery complete, but the reset failed ... */ |
1141 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1142 | return -EIO; |
1143 | ||
6689c167 MA |
1144 | /* |
1145 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1146 | * to work properly to reinit the hw state while the gpu is | |
1147 | * still marked as reset-in-progress. Handle this with a flag. | |
1148 | */ | |
1149 | if (!error->reload_in_reset) | |
1150 | return -EAGAIN; | |
b361237b CW |
1151 | } |
1152 | ||
1153 | return 0; | |
1154 | } | |
1155 | ||
1156 | /* | |
b6660d59 | 1157 | * Compare arbitrary request against outstanding lazy request. Emit on match. |
b361237b | 1158 | */ |
84c33a64 | 1159 | int |
b6660d59 | 1160 | i915_gem_check_olr(struct drm_i915_gem_request *req) |
b361237b CW |
1161 | { |
1162 | int ret; | |
1163 | ||
b6660d59 | 1164 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
b361237b CW |
1165 | |
1166 | ret = 0; | |
b6660d59 | 1167 | if (req == req->ring->outstanding_lazy_request) |
9400ae5c | 1168 | ret = i915_add_request(req->ring); |
b361237b CW |
1169 | |
1170 | return ret; | |
1171 | } | |
1172 | ||
094f9a54 CW |
1173 | static void fake_irq(unsigned long data) |
1174 | { | |
1175 | wake_up_process((struct task_struct *)data); | |
1176 | } | |
1177 | ||
1178 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1179 | struct intel_engine_cs *ring) |
094f9a54 CW |
1180 | { |
1181 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1182 | } | |
1183 | ||
b29c19b6 CW |
1184 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1185 | { | |
1186 | if (file_priv == NULL) | |
1187 | return true; | |
1188 | ||
1189 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1190 | } | |
1191 | ||
b361237b | 1192 | /** |
9c654818 JH |
1193 | * __i915_wait_request - wait until execution of request has finished |
1194 | * @req: duh! | |
1195 | * @reset_counter: reset sequence associated with the given request | |
b361237b CW |
1196 | * @interruptible: do an interruptible wait (normally yes) |
1197 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1198 | * | |
f69061be DV |
1199 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1200 | * values have been read by the caller in an smp safe manner. Where read-side | |
1201 | * locks are involved, it is sufficient to read the reset_counter before | |
1202 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1203 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1204 | * inserted. | |
1205 | * | |
9c654818 | 1206 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1207 | * errno with remaining time filled in timeout argument. |
1208 | */ | |
9c654818 | 1209 | int __i915_wait_request(struct drm_i915_gem_request *req, |
f69061be | 1210 | unsigned reset_counter, |
b29c19b6 | 1211 | bool interruptible, |
5ed0bdf2 | 1212 | s64 *timeout, |
b29c19b6 | 1213 | struct drm_i915_file_private *file_priv) |
b361237b | 1214 | { |
9c654818 | 1215 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
3d13ef2e | 1216 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1217 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1218 | const bool irq_test_in_progress = |
1219 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 | 1220 | DEFINE_WAIT(wait); |
47e9766d | 1221 | unsigned long timeout_expire; |
5ed0bdf2 | 1222 | s64 before, now; |
b361237b CW |
1223 | int ret; |
1224 | ||
9df7575f | 1225 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1226 | |
1b5a433a | 1227 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1228 | return 0; |
1229 | ||
7bd0e226 DV |
1230 | timeout_expire = timeout ? |
1231 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; | |
b361237b | 1232 | |
ec5cc0f9 | 1233 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1234 | gen6_rps_boost(dev_priv); |
1235 | if (file_priv) | |
1236 | mod_delayed_work(dev_priv->wq, | |
1237 | &file_priv->mm.idle_work, | |
1238 | msecs_to_jiffies(100)); | |
1239 | } | |
1240 | ||
168c3f21 | 1241 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1242 | return -ENODEV; |
1243 | ||
094f9a54 | 1244 | /* Record current time in case interrupted by signal, or wedged */ |
74328ee5 | 1245 | trace_i915_gem_request_wait_begin(req); |
5ed0bdf2 | 1246 | before = ktime_get_raw_ns(); |
094f9a54 CW |
1247 | for (;;) { |
1248 | struct timer_list timer; | |
b361237b | 1249 | |
094f9a54 CW |
1250 | prepare_to_wait(&ring->irq_queue, &wait, |
1251 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1252 | |
f69061be DV |
1253 | /* We need to check whether any gpu reset happened in between |
1254 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1255 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1256 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1257 | * is truely gone. */ | |
1258 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1259 | if (ret == 0) | |
1260 | ret = -EAGAIN; | |
1261 | break; | |
1262 | } | |
f69061be | 1263 | |
1b5a433a | 1264 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1265 | ret = 0; |
1266 | break; | |
1267 | } | |
b361237b | 1268 | |
094f9a54 CW |
1269 | if (interruptible && signal_pending(current)) { |
1270 | ret = -ERESTARTSYS; | |
1271 | break; | |
1272 | } | |
1273 | ||
47e9766d | 1274 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1275 | ret = -ETIME; |
1276 | break; | |
1277 | } | |
1278 | ||
1279 | timer.function = NULL; | |
1280 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1281 | unsigned long expire; |
1282 | ||
094f9a54 | 1283 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1284 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1285 | mod_timer(&timer, expire); |
1286 | } | |
1287 | ||
5035c275 | 1288 | io_schedule(); |
094f9a54 | 1289 | |
094f9a54 CW |
1290 | if (timer.function) { |
1291 | del_singleshot_timer_sync(&timer); | |
1292 | destroy_timer_on_stack(&timer); | |
1293 | } | |
1294 | } | |
5ed0bdf2 | 1295 | now = ktime_get_raw_ns(); |
74328ee5 | 1296 | trace_i915_gem_request_wait_end(req); |
b361237b | 1297 | |
168c3f21 MK |
1298 | if (!irq_test_in_progress) |
1299 | ring->irq_put(ring); | |
094f9a54 CW |
1300 | |
1301 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1302 | |
1303 | if (timeout) { | |
5ed0bdf2 TG |
1304 | s64 tres = *timeout - (now - before); |
1305 | ||
1306 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1307 | |
1308 | /* | |
1309 | * Apparently ktime isn't accurate enough and occasionally has a | |
1310 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1311 | * things up to make the test happy. We allow up to 1 jiffy. | |
1312 | * | |
1313 | * This is a regrssion from the timespec->ktime conversion. | |
1314 | */ | |
1315 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1316 | *timeout = 0; | |
b361237b CW |
1317 | } |
1318 | ||
094f9a54 | 1319 | return ret; |
b361237b CW |
1320 | } |
1321 | ||
1322 | /** | |
a4b3a571 | 1323 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1324 | * request and object lists appropriately for that event. |
1325 | */ | |
1326 | int | |
a4b3a571 | 1327 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1328 | { |
a4b3a571 DV |
1329 | struct drm_device *dev; |
1330 | struct drm_i915_private *dev_priv; | |
1331 | bool interruptible; | |
16e9a21f | 1332 | unsigned reset_counter; |
b361237b CW |
1333 | int ret; |
1334 | ||
a4b3a571 DV |
1335 | BUG_ON(req == NULL); |
1336 | ||
1337 | dev = req->ring->dev; | |
1338 | dev_priv = dev->dev_private; | |
1339 | interruptible = dev_priv->mm.interruptible; | |
1340 | ||
b361237b | 1341 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1342 | |
33196ded | 1343 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1344 | if (ret) |
1345 | return ret; | |
1346 | ||
a4b3a571 | 1347 | ret = i915_gem_check_olr(req); |
b361237b CW |
1348 | if (ret) |
1349 | return ret; | |
1350 | ||
16e9a21f | 1351 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
a4b3a571 | 1352 | i915_gem_request_reference(req); |
9c654818 JH |
1353 | ret = __i915_wait_request(req, reset_counter, |
1354 | interruptible, NULL, NULL); | |
a4b3a571 DV |
1355 | i915_gem_request_unreference(req); |
1356 | return ret; | |
b361237b CW |
1357 | } |
1358 | ||
d26e3af8 | 1359 | static int |
8e639549 | 1360 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) |
d26e3af8 | 1361 | { |
c8725f3d CW |
1362 | if (!obj->active) |
1363 | return 0; | |
d26e3af8 CW |
1364 | |
1365 | /* Manually manage the write flush as we may have not yet | |
1366 | * retired the buffer. | |
1367 | * | |
97b2a6a1 JH |
1368 | * Note that the last_write_req is always the earlier of |
1369 | * the two (read/write) requests, so if we haved successfully waited, | |
d26e3af8 CW |
1370 | * we know we have passed the last write. |
1371 | */ | |
97b2a6a1 | 1372 | i915_gem_request_assign(&obj->last_write_req, NULL); |
d26e3af8 CW |
1373 | |
1374 | return 0; | |
1375 | } | |
1376 | ||
b361237b CW |
1377 | /** |
1378 | * Ensures that all rendering to the object has completed and the object is | |
1379 | * safe to unbind from the GTT or access from the CPU. | |
1380 | */ | |
1381 | static __must_check int | |
1382 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1383 | bool readonly) | |
1384 | { | |
97b2a6a1 | 1385 | struct drm_i915_gem_request *req; |
b361237b CW |
1386 | int ret; |
1387 | ||
97b2a6a1 JH |
1388 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1389 | if (!req) | |
b361237b CW |
1390 | return 0; |
1391 | ||
a4b3a571 | 1392 | ret = i915_wait_request(req); |
b361237b CW |
1393 | if (ret) |
1394 | return ret; | |
1395 | ||
8e639549 | 1396 | return i915_gem_object_wait_rendering__tail(obj); |
b361237b CW |
1397 | } |
1398 | ||
3236f57a CW |
1399 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1400 | * as the object state may change during this call. | |
1401 | */ | |
1402 | static __must_check int | |
1403 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1404 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1405 | bool readonly) |
1406 | { | |
97b2a6a1 | 1407 | struct drm_i915_gem_request *req; |
3236f57a CW |
1408 | struct drm_device *dev = obj->base.dev; |
1409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f69061be | 1410 | unsigned reset_counter; |
3236f57a CW |
1411 | int ret; |
1412 | ||
1413 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1414 | BUG_ON(!dev_priv->mm.interruptible); | |
1415 | ||
97b2a6a1 JH |
1416 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1417 | if (!req) | |
3236f57a CW |
1418 | return 0; |
1419 | ||
33196ded | 1420 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1421 | if (ret) |
1422 | return ret; | |
1423 | ||
b6660d59 | 1424 | ret = i915_gem_check_olr(req); |
3236f57a CW |
1425 | if (ret) |
1426 | return ret; | |
1427 | ||
f69061be | 1428 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 1429 | i915_gem_request_reference(req); |
3236f57a | 1430 | mutex_unlock(&dev->struct_mutex); |
9c654818 | 1431 | ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv); |
3236f57a | 1432 | mutex_lock(&dev->struct_mutex); |
ff865885 | 1433 | i915_gem_request_unreference(req); |
d26e3af8 CW |
1434 | if (ret) |
1435 | return ret; | |
3236f57a | 1436 | |
8e639549 | 1437 | return i915_gem_object_wait_rendering__tail(obj); |
3236f57a CW |
1438 | } |
1439 | ||
673a394b | 1440 | /** |
2ef7eeaa EA |
1441 | * Called when user space prepares to use an object with the CPU, either |
1442 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1443 | */ |
1444 | int | |
1445 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1446 | struct drm_file *file) |
673a394b EA |
1447 | { |
1448 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1449 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1450 | uint32_t read_domains = args->read_domains; |
1451 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1452 | int ret; |
1453 | ||
2ef7eeaa | 1454 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1455 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1456 | return -EINVAL; |
1457 | ||
21d509e3 | 1458 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1459 | return -EINVAL; |
1460 | ||
1461 | /* Having something in the write domain implies it's in the read | |
1462 | * domain, and only that read domain. Enforce that in the request. | |
1463 | */ | |
1464 | if (write_domain != 0 && read_domains != write_domain) | |
1465 | return -EINVAL; | |
1466 | ||
76c1dec1 | 1467 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1468 | if (ret) |
76c1dec1 | 1469 | return ret; |
1d7cfea1 | 1470 | |
05394f39 | 1471 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1472 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1473 | ret = -ENOENT; |
1474 | goto unlock; | |
76c1dec1 | 1475 | } |
673a394b | 1476 | |
3236f57a CW |
1477 | /* Try to flush the object off the GPU without holding the lock. |
1478 | * We will repeat the flush holding the lock in the normal manner | |
1479 | * to catch cases where we are gazumped. | |
1480 | */ | |
6e4930f6 CW |
1481 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1482 | file->driver_priv, | |
1483 | !write_domain); | |
3236f57a CW |
1484 | if (ret) |
1485 | goto unref; | |
1486 | ||
43566ded | 1487 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1488 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1489 | else |
e47c68e9 | 1490 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1491 | |
3236f57a | 1492 | unref: |
05394f39 | 1493 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1494 | unlock: |
673a394b EA |
1495 | mutex_unlock(&dev->struct_mutex); |
1496 | return ret; | |
1497 | } | |
1498 | ||
1499 | /** | |
1500 | * Called when user space has done writes to this buffer | |
1501 | */ | |
1502 | int | |
1503 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1504 | struct drm_file *file) |
673a394b EA |
1505 | { |
1506 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1507 | struct drm_i915_gem_object *obj; |
673a394b EA |
1508 | int ret = 0; |
1509 | ||
76c1dec1 | 1510 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1511 | if (ret) |
76c1dec1 | 1512 | return ret; |
1d7cfea1 | 1513 | |
05394f39 | 1514 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1515 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1516 | ret = -ENOENT; |
1517 | goto unlock; | |
673a394b EA |
1518 | } |
1519 | ||
673a394b | 1520 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1521 | if (obj->pin_display) |
e62b59e4 | 1522 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1523 | |
05394f39 | 1524 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1525 | unlock: |
673a394b EA |
1526 | mutex_unlock(&dev->struct_mutex); |
1527 | return ret; | |
1528 | } | |
1529 | ||
1530 | /** | |
1531 | * Maps the contents of an object, returning the address it is mapped | |
1532 | * into. | |
1533 | * | |
1534 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1535 | * imply a ref on the object itself. | |
34367381 DV |
1536 | * |
1537 | * IMPORTANT: | |
1538 | * | |
1539 | * DRM driver writers who look a this function as an example for how to do GEM | |
1540 | * mmap support, please don't implement mmap support like here. The modern way | |
1541 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1542 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1543 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1544 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1545 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1546 | */ |
1547 | int | |
1548 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1549 | struct drm_file *file) |
673a394b EA |
1550 | { |
1551 | struct drm_i915_gem_mmap *args = data; | |
1552 | struct drm_gem_object *obj; | |
673a394b EA |
1553 | unsigned long addr; |
1554 | ||
1816f923 AG |
1555 | if (args->flags & ~(I915_MMAP_WC)) |
1556 | return -EINVAL; | |
1557 | ||
1558 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) | |
1559 | return -ENODEV; | |
1560 | ||
05394f39 | 1561 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1562 | if (obj == NULL) |
bf79cb91 | 1563 | return -ENOENT; |
673a394b | 1564 | |
1286ff73 DV |
1565 | /* prime objects have no backing filp to GEM mmap |
1566 | * pages from. | |
1567 | */ | |
1568 | if (!obj->filp) { | |
1569 | drm_gem_object_unreference_unlocked(obj); | |
1570 | return -EINVAL; | |
1571 | } | |
1572 | ||
6be5ceb0 | 1573 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1574 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1575 | args->offset); | |
1816f923 AG |
1576 | if (args->flags & I915_MMAP_WC) { |
1577 | struct mm_struct *mm = current->mm; | |
1578 | struct vm_area_struct *vma; | |
1579 | ||
1580 | down_write(&mm->mmap_sem); | |
1581 | vma = find_vma(mm, addr); | |
1582 | if (vma) | |
1583 | vma->vm_page_prot = | |
1584 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1585 | else | |
1586 | addr = -ENOMEM; | |
1587 | up_write(&mm->mmap_sem); | |
1588 | } | |
bc9025bd | 1589 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1590 | if (IS_ERR((void *)addr)) |
1591 | return addr; | |
1592 | ||
1593 | args->addr_ptr = (uint64_t) addr; | |
1594 | ||
1595 | return 0; | |
1596 | } | |
1597 | ||
de151cf6 JB |
1598 | /** |
1599 | * i915_gem_fault - fault a page into the GTT | |
1600 | * vma: VMA in question | |
1601 | * vmf: fault info | |
1602 | * | |
1603 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1604 | * from userspace. The fault handler takes care of binding the object to | |
1605 | * the GTT (if needed), allocating and programming a fence register (again, | |
1606 | * only if needed based on whether the old reg is still valid or the object | |
1607 | * is tiled) and inserting a new PTE into the faulting process. | |
1608 | * | |
1609 | * Note that the faulting process may involve evicting existing objects | |
1610 | * from the GTT and/or fence registers to make room. So performance may | |
1611 | * suffer if the GTT working set is large or there are few fence registers | |
1612 | * left. | |
1613 | */ | |
1614 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1615 | { | |
05394f39 CW |
1616 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1617 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1618 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1619 | pgoff_t page_offset; |
1620 | unsigned long pfn; | |
1621 | int ret = 0; | |
0f973f27 | 1622 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1623 | |
f65c9168 PZ |
1624 | intel_runtime_pm_get(dev_priv); |
1625 | ||
de151cf6 JB |
1626 | /* We don't use vmf->pgoff since that has the fake offset */ |
1627 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1628 | PAGE_SHIFT; | |
1629 | ||
d9bc7e9f CW |
1630 | ret = i915_mutex_lock_interruptible(dev); |
1631 | if (ret) | |
1632 | goto out; | |
a00b10c3 | 1633 | |
db53a302 CW |
1634 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1635 | ||
6e4930f6 CW |
1636 | /* Try to flush the object off the GPU first without holding the lock. |
1637 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1638 | * repeat the flush holding the lock in the normal manner to catch cases | |
1639 | * where we are gazumped. | |
1640 | */ | |
1641 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1642 | if (ret) | |
1643 | goto unlock; | |
1644 | ||
eb119bd6 CW |
1645 | /* Access to snoopable pages through the GTT is incoherent. */ |
1646 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1647 | ret = -EFAULT; |
eb119bd6 CW |
1648 | goto unlock; |
1649 | } | |
1650 | ||
d9bc7e9f | 1651 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1652 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1653 | if (ret) |
1654 | goto unlock; | |
4a684a41 | 1655 | |
c9839303 CW |
1656 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1657 | if (ret) | |
1658 | goto unpin; | |
74898d7e | 1659 | |
06d98131 | 1660 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1661 | if (ret) |
c9839303 | 1662 | goto unpin; |
7d1c4804 | 1663 | |
b90b91d8 | 1664 | /* Finally, remap it using the new GTT offset */ |
f343c5f6 BW |
1665 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1666 | pfn >>= PAGE_SHIFT; | |
de151cf6 | 1667 | |
b90b91d8 | 1668 | if (!obj->fault_mappable) { |
beff0d0f VS |
1669 | unsigned long size = min_t(unsigned long, |
1670 | vma->vm_end - vma->vm_start, | |
1671 | obj->base.size); | |
b90b91d8 CW |
1672 | int i; |
1673 | ||
beff0d0f | 1674 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
b90b91d8 CW |
1675 | ret = vm_insert_pfn(vma, |
1676 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1677 | pfn + i); | |
1678 | if (ret) | |
1679 | break; | |
1680 | } | |
1681 | ||
1682 | obj->fault_mappable = true; | |
1683 | } else | |
1684 | ret = vm_insert_pfn(vma, | |
1685 | (unsigned long)vmf->virtual_address, | |
1686 | pfn + page_offset); | |
c9839303 | 1687 | unpin: |
d7f46fc4 | 1688 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1689 | unlock: |
de151cf6 | 1690 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1691 | out: |
de151cf6 | 1692 | switch (ret) { |
d9bc7e9f | 1693 | case -EIO: |
2232f031 DV |
1694 | /* |
1695 | * We eat errors when the gpu is terminally wedged to avoid | |
1696 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1697 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1698 | * and so needs to be reported. | |
1699 | */ | |
1700 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1701 | ret = VM_FAULT_SIGBUS; |
1702 | break; | |
1703 | } | |
045e769a | 1704 | case -EAGAIN: |
571c608d DV |
1705 | /* |
1706 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1707 | * handler to reset everything when re-faulting in | |
1708 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1709 | */ |
c715089f CW |
1710 | case 0: |
1711 | case -ERESTARTSYS: | |
bed636ab | 1712 | case -EINTR: |
e79e0fe3 DR |
1713 | case -EBUSY: |
1714 | /* | |
1715 | * EBUSY is ok: this just means that another thread | |
1716 | * already did the job. | |
1717 | */ | |
f65c9168 PZ |
1718 | ret = VM_FAULT_NOPAGE; |
1719 | break; | |
de151cf6 | 1720 | case -ENOMEM: |
f65c9168 PZ |
1721 | ret = VM_FAULT_OOM; |
1722 | break; | |
a7c2e1aa | 1723 | case -ENOSPC: |
45d67817 | 1724 | case -EFAULT: |
f65c9168 PZ |
1725 | ret = VM_FAULT_SIGBUS; |
1726 | break; | |
de151cf6 | 1727 | default: |
a7c2e1aa | 1728 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1729 | ret = VM_FAULT_SIGBUS; |
1730 | break; | |
de151cf6 | 1731 | } |
f65c9168 PZ |
1732 | |
1733 | intel_runtime_pm_put(dev_priv); | |
1734 | return ret; | |
de151cf6 JB |
1735 | } |
1736 | ||
901782b2 CW |
1737 | /** |
1738 | * i915_gem_release_mmap - remove physical page mappings | |
1739 | * @obj: obj in question | |
1740 | * | |
af901ca1 | 1741 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1742 | * relinquish ownership of the pages back to the system. |
1743 | * | |
1744 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1745 | * object through the GTT and then lose the fence register due to | |
1746 | * resource pressure. Similarly if the object has been moved out of the | |
1747 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1748 | * mapping will then trigger a page fault on the next user access, allowing | |
1749 | * fixup by i915_gem_fault(). | |
1750 | */ | |
d05ca301 | 1751 | void |
05394f39 | 1752 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1753 | { |
6299f992 CW |
1754 | if (!obj->fault_mappable) |
1755 | return; | |
901782b2 | 1756 | |
6796cb16 DH |
1757 | drm_vma_node_unmap(&obj->base.vma_node, |
1758 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1759 | obj->fault_mappable = false; |
901782b2 CW |
1760 | } |
1761 | ||
eedd10f4 CW |
1762 | void |
1763 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1764 | { | |
1765 | struct drm_i915_gem_object *obj; | |
1766 | ||
1767 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1768 | i915_gem_release_mmap(obj); | |
1769 | } | |
1770 | ||
0fa87796 | 1771 | uint32_t |
e28f8711 | 1772 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1773 | { |
e28f8711 | 1774 | uint32_t gtt_size; |
92b88aeb CW |
1775 | |
1776 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1777 | tiling_mode == I915_TILING_NONE) |
1778 | return size; | |
92b88aeb CW |
1779 | |
1780 | /* Previous chips need a power-of-two fence region when tiling */ | |
1781 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1782 | gtt_size = 1024*1024; |
92b88aeb | 1783 | else |
e28f8711 | 1784 | gtt_size = 512*1024; |
92b88aeb | 1785 | |
e28f8711 CW |
1786 | while (gtt_size < size) |
1787 | gtt_size <<= 1; | |
92b88aeb | 1788 | |
e28f8711 | 1789 | return gtt_size; |
92b88aeb CW |
1790 | } |
1791 | ||
de151cf6 JB |
1792 | /** |
1793 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1794 | * @obj: object to check | |
1795 | * | |
1796 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1797 | * potential fence register mapping. |
de151cf6 | 1798 | */ |
d865110c ID |
1799 | uint32_t |
1800 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1801 | int tiling_mode, bool fenced) | |
de151cf6 | 1802 | { |
de151cf6 JB |
1803 | /* |
1804 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1805 | * if a fence register is needed for the object. | |
1806 | */ | |
d865110c | 1807 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1808 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1809 | return 4096; |
1810 | ||
a00b10c3 CW |
1811 | /* |
1812 | * Previous chips need to be aligned to the size of the smallest | |
1813 | * fence register that can contain the object. | |
1814 | */ | |
e28f8711 | 1815 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1816 | } |
1817 | ||
d8cb5086 CW |
1818 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1819 | { | |
1820 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1821 | int ret; | |
1822 | ||
0de23977 | 1823 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1824 | return 0; |
1825 | ||
da494d7c DV |
1826 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1827 | ||
d8cb5086 CW |
1828 | ret = drm_gem_create_mmap_offset(&obj->base); |
1829 | if (ret != -ENOSPC) | |
da494d7c | 1830 | goto out; |
d8cb5086 CW |
1831 | |
1832 | /* Badly fragmented mmap space? The only way we can recover | |
1833 | * space is by destroying unwanted objects. We can't randomly release | |
1834 | * mmap_offsets as userspace expects them to be persistent for the | |
1835 | * lifetime of the objects. The closest we can is to release the | |
1836 | * offsets on purgeable objects by truncating it and marking it purged, | |
1837 | * which prevents userspace from ever using that object again. | |
1838 | */ | |
21ab4e74 CW |
1839 | i915_gem_shrink(dev_priv, |
1840 | obj->base.size >> PAGE_SHIFT, | |
1841 | I915_SHRINK_BOUND | | |
1842 | I915_SHRINK_UNBOUND | | |
1843 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1844 | ret = drm_gem_create_mmap_offset(&obj->base); |
1845 | if (ret != -ENOSPC) | |
da494d7c | 1846 | goto out; |
d8cb5086 CW |
1847 | |
1848 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1849 | ret = drm_gem_create_mmap_offset(&obj->base); |
1850 | out: | |
1851 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1852 | ||
1853 | return ret; | |
d8cb5086 CW |
1854 | } |
1855 | ||
1856 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1857 | { | |
d8cb5086 CW |
1858 | drm_gem_free_mmap_offset(&obj->base); |
1859 | } | |
1860 | ||
da6b51d0 | 1861 | int |
ff72145b DA |
1862 | i915_gem_mmap_gtt(struct drm_file *file, |
1863 | struct drm_device *dev, | |
da6b51d0 | 1864 | uint32_t handle, |
ff72145b | 1865 | uint64_t *offset) |
de151cf6 | 1866 | { |
da761a6e | 1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1868 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1869 | int ret; |
1870 | ||
76c1dec1 | 1871 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1872 | if (ret) |
76c1dec1 | 1873 | return ret; |
de151cf6 | 1874 | |
ff72145b | 1875 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1876 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1877 | ret = -ENOENT; |
1878 | goto unlock; | |
1879 | } | |
de151cf6 | 1880 | |
5d4545ae | 1881 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1882 | ret = -E2BIG; |
ff56b0bc | 1883 | goto out; |
da761a6e CW |
1884 | } |
1885 | ||
05394f39 | 1886 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1887 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1888 | ret = -EFAULT; |
1d7cfea1 | 1889 | goto out; |
ab18282d CW |
1890 | } |
1891 | ||
d8cb5086 CW |
1892 | ret = i915_gem_object_create_mmap_offset(obj); |
1893 | if (ret) | |
1894 | goto out; | |
de151cf6 | 1895 | |
0de23977 | 1896 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1897 | |
1d7cfea1 | 1898 | out: |
05394f39 | 1899 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1900 | unlock: |
de151cf6 | 1901 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1902 | return ret; |
de151cf6 JB |
1903 | } |
1904 | ||
ff72145b DA |
1905 | /** |
1906 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1907 | * @dev: DRM device | |
1908 | * @data: GTT mapping ioctl data | |
1909 | * @file: GEM object info | |
1910 | * | |
1911 | * Simply returns the fake offset to userspace so it can mmap it. | |
1912 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1913 | * up so we can get faults in the handler above. | |
1914 | * | |
1915 | * The fault handler will take care of binding the object into the GTT | |
1916 | * (since it may have been evicted to make room for something), allocating | |
1917 | * a fence register, and mapping the appropriate aperture address into | |
1918 | * userspace. | |
1919 | */ | |
1920 | int | |
1921 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1922 | struct drm_file *file) | |
1923 | { | |
1924 | struct drm_i915_gem_mmap_gtt *args = data; | |
1925 | ||
da6b51d0 | 1926 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
1927 | } |
1928 | ||
225067ee DV |
1929 | /* Immediately discard the backing storage */ |
1930 | static void | |
1931 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1932 | { |
4d6294bf | 1933 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1934 | |
4d6294bf CW |
1935 | if (obj->base.filp == NULL) |
1936 | return; | |
e5281ccd | 1937 | |
225067ee DV |
1938 | /* Our goal here is to return as much of the memory as |
1939 | * is possible back to the system as we are called from OOM. | |
1940 | * To do this we must instruct the shmfs to drop all of its | |
1941 | * backing pages, *now*. | |
1942 | */ | |
5537252b | 1943 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1944 | obj->madv = __I915_MADV_PURGED; |
1945 | } | |
e5281ccd | 1946 | |
5537252b CW |
1947 | /* Try to discard unwanted pages */ |
1948 | static void | |
1949 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1950 | { |
5537252b CW |
1951 | struct address_space *mapping; |
1952 | ||
1953 | switch (obj->madv) { | |
1954 | case I915_MADV_DONTNEED: | |
1955 | i915_gem_object_truncate(obj); | |
1956 | case __I915_MADV_PURGED: | |
1957 | return; | |
1958 | } | |
1959 | ||
1960 | if (obj->base.filp == NULL) | |
1961 | return; | |
1962 | ||
1963 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1964 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1965 | } |
1966 | ||
5cdf5881 | 1967 | static void |
05394f39 | 1968 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1969 | { |
90797e6d ID |
1970 | struct sg_page_iter sg_iter; |
1971 | int ret; | |
1286ff73 | 1972 | |
05394f39 | 1973 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1974 | |
6c085a72 CW |
1975 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1976 | if (ret) { | |
1977 | /* In the event of a disaster, abandon all caches and | |
1978 | * hope for the best. | |
1979 | */ | |
1980 | WARN_ON(ret != -EIO); | |
2c22569b | 1981 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1982 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1983 | } | |
1984 | ||
6dacfd2f | 1985 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1986 | i915_gem_object_save_bit_17_swizzle(obj); |
1987 | ||
05394f39 CW |
1988 | if (obj->madv == I915_MADV_DONTNEED) |
1989 | obj->dirty = 0; | |
3ef94daa | 1990 | |
90797e6d | 1991 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1992 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1993 | |
05394f39 | 1994 | if (obj->dirty) |
9da3da66 | 1995 | set_page_dirty(page); |
3ef94daa | 1996 | |
05394f39 | 1997 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1998 | mark_page_accessed(page); |
3ef94daa | 1999 | |
9da3da66 | 2000 | page_cache_release(page); |
3ef94daa | 2001 | } |
05394f39 | 2002 | obj->dirty = 0; |
673a394b | 2003 | |
9da3da66 CW |
2004 | sg_free_table(obj->pages); |
2005 | kfree(obj->pages); | |
37e680a1 | 2006 | } |
6c085a72 | 2007 | |
dd624afd | 2008 | int |
37e680a1 CW |
2009 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2010 | { | |
2011 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2012 | ||
2f745ad3 | 2013 | if (obj->pages == NULL) |
37e680a1 CW |
2014 | return 0; |
2015 | ||
a5570178 CW |
2016 | if (obj->pages_pin_count) |
2017 | return -EBUSY; | |
2018 | ||
9843877d | 2019 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2020 | |
a2165e31 CW |
2021 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2022 | * array, hence protect them from being reaped by removing them from gtt | |
2023 | * lists early. */ | |
35c20a60 | 2024 | list_del(&obj->global_list); |
a2165e31 | 2025 | |
37e680a1 | 2026 | ops->put_pages(obj); |
05394f39 | 2027 | obj->pages = NULL; |
37e680a1 | 2028 | |
5537252b | 2029 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2030 | |
2031 | return 0; | |
2032 | } | |
2033 | ||
37e680a1 | 2034 | static int |
6c085a72 | 2035 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2036 | { |
6c085a72 | 2037 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2038 | int page_count, i; |
2039 | struct address_space *mapping; | |
9da3da66 CW |
2040 | struct sg_table *st; |
2041 | struct scatterlist *sg; | |
90797e6d | 2042 | struct sg_page_iter sg_iter; |
e5281ccd | 2043 | struct page *page; |
90797e6d | 2044 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2045 | gfp_t gfp; |
e5281ccd | 2046 | |
6c085a72 CW |
2047 | /* Assert that the object is not currently in any GPU domain. As it |
2048 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2049 | * a GPU cache | |
2050 | */ | |
2051 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2052 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2053 | ||
9da3da66 CW |
2054 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2055 | if (st == NULL) | |
2056 | return -ENOMEM; | |
2057 | ||
05394f39 | 2058 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2059 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2060 | kfree(st); |
e5281ccd | 2061 | return -ENOMEM; |
9da3da66 | 2062 | } |
e5281ccd | 2063 | |
9da3da66 CW |
2064 | /* Get the list of pages out of our struct file. They'll be pinned |
2065 | * at this point until we release them. | |
2066 | * | |
2067 | * Fail silently without starting the shrinker | |
2068 | */ | |
496ad9aa | 2069 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2070 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2071 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2072 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2073 | sg = st->sgl; |
2074 | st->nents = 0; | |
2075 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2076 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2077 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2078 | i915_gem_shrink(dev_priv, |
2079 | page_count, | |
2080 | I915_SHRINK_BOUND | | |
2081 | I915_SHRINK_UNBOUND | | |
2082 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2083 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2084 | } | |
2085 | if (IS_ERR(page)) { | |
2086 | /* We've tried hard to allocate the memory by reaping | |
2087 | * our own buffer, now let the real VM do its job and | |
2088 | * go down in flames if truly OOM. | |
2089 | */ | |
6c085a72 | 2090 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2091 | page = shmem_read_mapping_page(mapping, i); |
6c085a72 CW |
2092 | if (IS_ERR(page)) |
2093 | goto err_pages; | |
6c085a72 | 2094 | } |
426729dc KRW |
2095 | #ifdef CONFIG_SWIOTLB |
2096 | if (swiotlb_nr_tbl()) { | |
2097 | st->nents++; | |
2098 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2099 | sg = sg_next(sg); | |
2100 | continue; | |
2101 | } | |
2102 | #endif | |
90797e6d ID |
2103 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2104 | if (i) | |
2105 | sg = sg_next(sg); | |
2106 | st->nents++; | |
2107 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2108 | } else { | |
2109 | sg->length += PAGE_SIZE; | |
2110 | } | |
2111 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2112 | |
2113 | /* Check that the i965g/gm workaround works. */ | |
2114 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2115 | } |
426729dc KRW |
2116 | #ifdef CONFIG_SWIOTLB |
2117 | if (!swiotlb_nr_tbl()) | |
2118 | #endif | |
2119 | sg_mark_end(sg); | |
74ce6b6c CW |
2120 | obj->pages = st; |
2121 | ||
6dacfd2f | 2122 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2123 | i915_gem_object_do_bit_17_swizzle(obj); |
2124 | ||
656bfa3a DV |
2125 | if (obj->tiling_mode != I915_TILING_NONE && |
2126 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2127 | i915_gem_object_pin_pages(obj); | |
2128 | ||
e5281ccd CW |
2129 | return 0; |
2130 | ||
2131 | err_pages: | |
90797e6d ID |
2132 | sg_mark_end(sg); |
2133 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2134 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2135 | sg_free_table(st); |
2136 | kfree(st); | |
0820baf3 CW |
2137 | |
2138 | /* shmemfs first checks if there is enough memory to allocate the page | |
2139 | * and reports ENOSPC should there be insufficient, along with the usual | |
2140 | * ENOMEM for a genuine allocation failure. | |
2141 | * | |
2142 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2143 | * space and so want to translate the error from shmemfs back to our | |
2144 | * usual understanding of ENOMEM. | |
2145 | */ | |
2146 | if (PTR_ERR(page) == -ENOSPC) | |
2147 | return -ENOMEM; | |
2148 | else | |
2149 | return PTR_ERR(page); | |
673a394b EA |
2150 | } |
2151 | ||
37e680a1 CW |
2152 | /* Ensure that the associated pages are gathered from the backing storage |
2153 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2154 | * multiple times before they are released by a single call to | |
2155 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2156 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2157 | * or as the object is itself released. | |
2158 | */ | |
2159 | int | |
2160 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2161 | { | |
2162 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2163 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2164 | int ret; | |
2165 | ||
2f745ad3 | 2166 | if (obj->pages) |
37e680a1 CW |
2167 | return 0; |
2168 | ||
43e28f09 | 2169 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2170 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2171 | return -EFAULT; |
43e28f09 CW |
2172 | } |
2173 | ||
a5570178 CW |
2174 | BUG_ON(obj->pages_pin_count); |
2175 | ||
37e680a1 CW |
2176 | ret = ops->get_pages(obj); |
2177 | if (ret) | |
2178 | return ret; | |
2179 | ||
35c20a60 | 2180 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2181 | return 0; |
673a394b EA |
2182 | } |
2183 | ||
e2d05a8b | 2184 | static void |
05394f39 | 2185 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2186 | struct intel_engine_cs *ring) |
673a394b | 2187 | { |
41c52415 JH |
2188 | struct drm_i915_gem_request *req; |
2189 | struct intel_engine_cs *old_ring; | |
617dbe27 | 2190 | |
852835f3 | 2191 | BUG_ON(ring == NULL); |
41c52415 JH |
2192 | |
2193 | req = intel_ring_get_request(ring); | |
2194 | old_ring = i915_gem_request_get_ring(obj->last_read_req); | |
2195 | ||
2196 | if (old_ring != ring && obj->last_write_req) { | |
97b2a6a1 JH |
2197 | /* Keep the request relative to the current ring */ |
2198 | i915_gem_request_assign(&obj->last_write_req, req); | |
02978ff5 | 2199 | } |
673a394b EA |
2200 | |
2201 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2202 | if (!obj->active) { |
2203 | drm_gem_object_reference(&obj->base); | |
2204 | obj->active = 1; | |
673a394b | 2205 | } |
e35a41de | 2206 | |
05394f39 | 2207 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2208 | |
97b2a6a1 | 2209 | i915_gem_request_assign(&obj->last_read_req, req); |
caea7476 CW |
2210 | } |
2211 | ||
e2d05a8b | 2212 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2213 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2214 | { |
2215 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2216 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2217 | } | |
2218 | ||
caea7476 | 2219 | static void |
caea7476 | 2220 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2221 | { |
feb822cf | 2222 | struct i915_vma *vma; |
ce44b0ea | 2223 | |
65ce3027 | 2224 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2225 | BUG_ON(!obj->active); |
caea7476 | 2226 | |
fe14d5f4 TU |
2227 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
2228 | if (!list_empty(&vma->mm_list)) | |
2229 | list_move_tail(&vma->mm_list, &vma->vm->inactive_list); | |
feb822cf | 2230 | } |
caea7476 | 2231 | |
f99d7069 DV |
2232 | intel_fb_obj_flush(obj, true); |
2233 | ||
65ce3027 | 2234 | list_del_init(&obj->ring_list); |
caea7476 | 2235 | |
97b2a6a1 JH |
2236 | i915_gem_request_assign(&obj->last_read_req, NULL); |
2237 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
65ce3027 CW |
2238 | obj->base.write_domain = 0; |
2239 | ||
97b2a6a1 | 2240 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 CW |
2241 | |
2242 | obj->active = 0; | |
2243 | drm_gem_object_unreference(&obj->base); | |
2244 | ||
2245 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2246 | } |
673a394b | 2247 | |
c8725f3d CW |
2248 | static void |
2249 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2250 | { | |
41c52415 | 2251 | if (obj->last_read_req == NULL) |
c8725f3d CW |
2252 | return; |
2253 | ||
1b5a433a | 2254 | if (i915_gem_request_completed(obj->last_read_req, true)) |
c8725f3d CW |
2255 | i915_gem_object_move_to_inactive(obj); |
2256 | } | |
2257 | ||
9d773091 | 2258 | static int |
fca26bb4 | 2259 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2260 | { |
9d773091 | 2261 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2262 | struct intel_engine_cs *ring; |
9d773091 | 2263 | int ret, i, j; |
53d227f2 | 2264 | |
107f27a5 | 2265 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2266 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2267 | ret = intel_ring_idle(ring); |
2268 | if (ret) | |
2269 | return ret; | |
9d773091 | 2270 | } |
9d773091 | 2271 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2272 | |
2273 | /* Finally reset hw state */ | |
9d773091 | 2274 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2275 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2276 | |
ebc348b2 BW |
2277 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2278 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2279 | } |
53d227f2 | 2280 | |
9d773091 | 2281 | return 0; |
53d227f2 DV |
2282 | } |
2283 | ||
fca26bb4 MK |
2284 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2285 | { | |
2286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2287 | int ret; | |
2288 | ||
2289 | if (seqno == 0) | |
2290 | return -EINVAL; | |
2291 | ||
2292 | /* HWS page needs to be set less than what we | |
2293 | * will inject to ring | |
2294 | */ | |
2295 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2296 | if (ret) | |
2297 | return ret; | |
2298 | ||
2299 | /* Carefully set the last_seqno value so that wrap | |
2300 | * detection still works | |
2301 | */ | |
2302 | dev_priv->next_seqno = seqno; | |
2303 | dev_priv->last_seqno = seqno - 1; | |
2304 | if (dev_priv->last_seqno == 0) | |
2305 | dev_priv->last_seqno--; | |
2306 | ||
2307 | return 0; | |
2308 | } | |
2309 | ||
9d773091 CW |
2310 | int |
2311 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2312 | { |
9d773091 CW |
2313 | struct drm_i915_private *dev_priv = dev->dev_private; |
2314 | ||
2315 | /* reserve 0 for non-seqno */ | |
2316 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2317 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2318 | if (ret) |
2319 | return ret; | |
53d227f2 | 2320 | |
9d773091 CW |
2321 | dev_priv->next_seqno = 1; |
2322 | } | |
53d227f2 | 2323 | |
f72b3435 | 2324 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2325 | return 0; |
53d227f2 DV |
2326 | } |
2327 | ||
a4872ba6 | 2328 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2329 | struct drm_file *file, |
9400ae5c | 2330 | struct drm_i915_gem_object *obj) |
673a394b | 2331 | { |
3e31c6c0 | 2332 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2333 | struct drm_i915_gem_request *request; |
48e29f55 | 2334 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2335 | u32 request_start; |
3cce469c CW |
2336 | int ret; |
2337 | ||
6259cead | 2338 | request = ring->outstanding_lazy_request; |
48e29f55 OM |
2339 | if (WARN_ON(request == NULL)) |
2340 | return -ENOMEM; | |
2341 | ||
2342 | if (i915.enable_execlists) { | |
21076372 | 2343 | ringbuf = request->ctx->engine[ring->id].ringbuf; |
48e29f55 OM |
2344 | } else |
2345 | ringbuf = ring->buffer; | |
2346 | ||
2347 | request_start = intel_ring_get_tail(ringbuf); | |
cc889e0f DV |
2348 | /* |
2349 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2350 | * after having emitted the batchbuffer command. Hence we need to fix | |
2351 | * things up similar to emitting the lazy request. The difference here | |
2352 | * is that the flush _must_ happen before the next request, no matter | |
2353 | * what. | |
2354 | */ | |
48e29f55 | 2355 | if (i915.enable_execlists) { |
21076372 | 2356 | ret = logical_ring_flush_all_caches(ringbuf, request->ctx); |
48e29f55 OM |
2357 | if (ret) |
2358 | return ret; | |
2359 | } else { | |
2360 | ret = intel_ring_flush_all_caches(ring); | |
2361 | if (ret) | |
2362 | return ret; | |
2363 | } | |
cc889e0f | 2364 | |
a71d8d94 CW |
2365 | /* Record the position of the start of the request so that |
2366 | * should we detect the updated seqno part-way through the | |
2367 | * GPU processing the request, we never over-estimate the | |
2368 | * position of the head. | |
2369 | */ | |
6d3d8274 | 2370 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2371 | |
48e29f55 | 2372 | if (i915.enable_execlists) { |
72f95afa | 2373 | ret = ring->emit_request(ringbuf, request); |
48e29f55 OM |
2374 | if (ret) |
2375 | return ret; | |
2376 | } else { | |
2377 | ret = ring->add_request(ring); | |
2378 | if (ret) | |
2379 | return ret; | |
53292cdb MT |
2380 | |
2381 | request->tail = intel_ring_get_tail(ringbuf); | |
48e29f55 | 2382 | } |
673a394b | 2383 | |
7d736f4f | 2384 | request->head = request_start; |
7d736f4f MK |
2385 | |
2386 | /* Whilst this request exists, batch_obj will be on the | |
2387 | * active_list, and so will hold the active reference. Only when this | |
2388 | * request is retired will the the batch_obj be moved onto the | |
2389 | * inactive_list and lose its active reference. Hence we do not need | |
2390 | * to explicitly hold another reference here. | |
2391 | */ | |
9a7e0c2a | 2392 | request->batch_obj = obj; |
0e50e96b | 2393 | |
48e29f55 OM |
2394 | if (!i915.enable_execlists) { |
2395 | /* Hold a reference to the current context so that we can inspect | |
2396 | * it later in case a hangcheck error event fires. | |
2397 | */ | |
2398 | request->ctx = ring->last_context; | |
2399 | if (request->ctx) | |
2400 | i915_gem_context_reference(request->ctx); | |
2401 | } | |
0e50e96b | 2402 | |
673a394b | 2403 | request->emitted_jiffies = jiffies; |
852835f3 | 2404 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2405 | request->file_priv = NULL; |
852835f3 | 2406 | |
db53a302 CW |
2407 | if (file) { |
2408 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2409 | ||
1c25595f | 2410 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2411 | request->file_priv = file_priv; |
b962442e | 2412 | list_add_tail(&request->client_list, |
f787a5f5 | 2413 | &file_priv->mm.request_list); |
1c25595f | 2414 | spin_unlock(&file_priv->mm.lock); |
071c92de MK |
2415 | |
2416 | request->pid = get_pid(task_pid(current)); | |
b962442e | 2417 | } |
673a394b | 2418 | |
74328ee5 | 2419 | trace_i915_gem_request_add(request); |
6259cead | 2420 | ring->outstanding_lazy_request = NULL; |
db53a302 | 2421 | |
87255483 | 2422 | i915_queue_hangcheck(ring->dev); |
10cd45b6 | 2423 | |
87255483 DV |
2424 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2425 | queue_delayed_work(dev_priv->wq, | |
2426 | &dev_priv->mm.retire_work, | |
2427 | round_jiffies_up_relative(HZ)); | |
2428 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2429 | |
3cce469c | 2430 | return 0; |
673a394b EA |
2431 | } |
2432 | ||
f787a5f5 CW |
2433 | static inline void |
2434 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2435 | { |
1c25595f | 2436 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2437 | |
1c25595f CW |
2438 | if (!file_priv) |
2439 | return; | |
1c5d22f7 | 2440 | |
1c25595f | 2441 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2442 | list_del(&request->client_list); |
2443 | request->file_priv = NULL; | |
1c25595f | 2444 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2445 | } |
673a394b | 2446 | |
939fd762 | 2447 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2448 | const struct intel_context *ctx) |
be62acb4 | 2449 | { |
44e2c070 | 2450 | unsigned long elapsed; |
be62acb4 | 2451 | |
44e2c070 MK |
2452 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2453 | ||
2454 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2455 | return true; |
2456 | ||
676fa572 CW |
2457 | if (ctx->hang_stats.ban_period_seconds && |
2458 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
ccc7bed0 | 2459 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2460 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2461 | return true; |
88b4aa87 MK |
2462 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2463 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2464 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2465 | return true; |
3fac8978 | 2466 | } |
be62acb4 MK |
2467 | } |
2468 | ||
2469 | return false; | |
2470 | } | |
2471 | ||
939fd762 | 2472 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2473 | struct intel_context *ctx, |
b6b0fac0 | 2474 | const bool guilty) |
aa60c664 | 2475 | { |
44e2c070 MK |
2476 | struct i915_ctx_hang_stats *hs; |
2477 | ||
2478 | if (WARN_ON(!ctx)) | |
2479 | return; | |
aa60c664 | 2480 | |
44e2c070 MK |
2481 | hs = &ctx->hang_stats; |
2482 | ||
2483 | if (guilty) { | |
939fd762 | 2484 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2485 | hs->batch_active++; |
2486 | hs->guilty_ts = get_seconds(); | |
2487 | } else { | |
2488 | hs->batch_pending++; | |
aa60c664 MK |
2489 | } |
2490 | } | |
2491 | ||
0e50e96b MK |
2492 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2493 | { | |
2494 | list_del(&request->list); | |
2495 | i915_gem_request_remove_from_client(request); | |
2496 | ||
071c92de MK |
2497 | put_pid(request->pid); |
2498 | ||
abfe262a JH |
2499 | i915_gem_request_unreference(request); |
2500 | } | |
2501 | ||
2502 | void i915_gem_request_free(struct kref *req_ref) | |
2503 | { | |
2504 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2505 | typeof(*req), ref); | |
2506 | struct intel_context *ctx = req->ctx; | |
2507 | ||
0794aed3 TD |
2508 | if (ctx) { |
2509 | if (i915.enable_execlists) { | |
abfe262a | 2510 | struct intel_engine_cs *ring = req->ring; |
0e50e96b | 2511 | |
0794aed3 TD |
2512 | if (ctx != ring->default_context) |
2513 | intel_lr_context_unpin(ring, ctx); | |
2514 | } | |
abfe262a | 2515 | |
dcb4c12a OM |
2516 | i915_gem_context_unreference(ctx); |
2517 | } | |
abfe262a JH |
2518 | |
2519 | kfree(req); | |
0e50e96b MK |
2520 | } |
2521 | ||
8d9fc7fd | 2522 | struct drm_i915_gem_request * |
a4872ba6 | 2523 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2524 | { |
4db080f9 CW |
2525 | struct drm_i915_gem_request *request; |
2526 | ||
2527 | list_for_each_entry(request, &ring->request_list, list) { | |
1b5a433a | 2528 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2529 | continue; |
aa60c664 | 2530 | |
b6b0fac0 | 2531 | return request; |
4db080f9 | 2532 | } |
b6b0fac0 MK |
2533 | |
2534 | return NULL; | |
2535 | } | |
2536 | ||
2537 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2538 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2539 | { |
2540 | struct drm_i915_gem_request *request; | |
2541 | bool ring_hung; | |
2542 | ||
8d9fc7fd | 2543 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2544 | |
2545 | if (request == NULL) | |
2546 | return; | |
2547 | ||
2548 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2549 | ||
939fd762 | 2550 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2551 | |
2552 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2553 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2554 | } |
aa60c664 | 2555 | |
4db080f9 | 2556 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2557 | struct intel_engine_cs *ring) |
4db080f9 | 2558 | { |
dfaae392 | 2559 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2560 | struct drm_i915_gem_object *obj; |
9375e446 | 2561 | |
05394f39 CW |
2562 | obj = list_first_entry(&ring->active_list, |
2563 | struct drm_i915_gem_object, | |
2564 | ring_list); | |
9375e446 | 2565 | |
05394f39 | 2566 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2567 | } |
1d62beea | 2568 | |
dcb4c12a OM |
2569 | /* |
2570 | * Clear the execlists queue up before freeing the requests, as those | |
2571 | * are the ones that keep the context and ringbuffer backing objects | |
2572 | * pinned in place. | |
2573 | */ | |
2574 | while (!list_empty(&ring->execlist_queue)) { | |
6d3d8274 | 2575 | struct drm_i915_gem_request *submit_req; |
dcb4c12a OM |
2576 | |
2577 | submit_req = list_first_entry(&ring->execlist_queue, | |
6d3d8274 | 2578 | struct drm_i915_gem_request, |
dcb4c12a OM |
2579 | execlist_link); |
2580 | list_del(&submit_req->execlist_link); | |
2581 | intel_runtime_pm_put(dev_priv); | |
1197b4f2 MK |
2582 | |
2583 | if (submit_req->ctx != ring->default_context) | |
2584 | intel_lr_context_unpin(ring, submit_req->ctx); | |
2585 | ||
b3a38998 | 2586 | i915_gem_request_unreference(submit_req); |
dcb4c12a OM |
2587 | } |
2588 | ||
1d62beea BW |
2589 | /* |
2590 | * We must free the requests after all the corresponding objects have | |
2591 | * been moved off active lists. Which is the same order as the normal | |
2592 | * retire_requests function does. This is important if object hold | |
2593 | * implicit references on things like e.g. ppgtt address spaces through | |
2594 | * the request. | |
2595 | */ | |
2596 | while (!list_empty(&ring->request_list)) { | |
2597 | struct drm_i915_gem_request *request; | |
2598 | ||
2599 | request = list_first_entry(&ring->request_list, | |
2600 | struct drm_i915_gem_request, | |
2601 | list); | |
2602 | ||
2603 | i915_gem_free_request(request); | |
2604 | } | |
e3efda49 | 2605 | |
6259cead JH |
2606 | /* This may not have been flushed before the reset, so clean it now */ |
2607 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); | |
673a394b EA |
2608 | } |
2609 | ||
19b2dbde | 2610 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2611 | { |
2612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2613 | int i; | |
2614 | ||
4b9de737 | 2615 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2616 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2617 | |
94a335db DV |
2618 | /* |
2619 | * Commit delayed tiling changes if we have an object still | |
2620 | * attached to the fence, otherwise just clear the fence. | |
2621 | */ | |
2622 | if (reg->obj) { | |
2623 | i915_gem_object_update_fence(reg->obj, reg, | |
2624 | reg->obj->tiling_mode); | |
2625 | } else { | |
2626 | i915_gem_write_fence(dev, i, NULL); | |
2627 | } | |
312817a3 CW |
2628 | } |
2629 | } | |
2630 | ||
069efc1d | 2631 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2632 | { |
77f01230 | 2633 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2634 | struct intel_engine_cs *ring; |
1ec14ad3 | 2635 | int i; |
673a394b | 2636 | |
4db080f9 CW |
2637 | /* |
2638 | * Before we free the objects from the requests, we need to inspect | |
2639 | * them for finding the guilty party. As the requests only borrow | |
2640 | * their reference to the objects, the inspection must be done first. | |
2641 | */ | |
2642 | for_each_ring(ring, dev_priv, i) | |
2643 | i915_gem_reset_ring_status(dev_priv, ring); | |
2644 | ||
b4519513 | 2645 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2646 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2647 | |
acce9ffa BW |
2648 | i915_gem_context_reset(dev); |
2649 | ||
19b2dbde | 2650 | i915_gem_restore_fences(dev); |
673a394b EA |
2651 | } |
2652 | ||
2653 | /** | |
2654 | * This function clears the request list as sequence numbers are passed. | |
2655 | */ | |
1cf0ba14 | 2656 | void |
a4872ba6 | 2657 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2658 | { |
db53a302 | 2659 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2660 | |
832a3aad CW |
2661 | /* Retire requests first as we use it above for the early return. |
2662 | * If we retire requests last, we may use a later seqno and so clear | |
2663 | * the requests lists without clearing the active list, leading to | |
2664 | * confusion. | |
e9103038 | 2665 | */ |
852835f3 | 2666 | while (!list_empty(&ring->request_list)) { |
673a394b | 2667 | struct drm_i915_gem_request *request; |
673a394b | 2668 | |
852835f3 | 2669 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2670 | struct drm_i915_gem_request, |
2671 | list); | |
673a394b | 2672 | |
1b5a433a | 2673 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
2674 | break; |
2675 | ||
74328ee5 | 2676 | trace_i915_gem_request_retire(request); |
48e29f55 | 2677 | |
a71d8d94 CW |
2678 | /* We know the GPU must have read the request to have |
2679 | * sent us the seqno + interrupt, so use the position | |
2680 | * of tail of the request to update the last known position | |
2681 | * of the GPU head. | |
2682 | */ | |
98e1bd4a | 2683 | request->ringbuf->last_retired_head = request->postfix; |
b84d5f0c | 2684 | |
0e50e96b | 2685 | i915_gem_free_request(request); |
b84d5f0c | 2686 | } |
673a394b | 2687 | |
832a3aad CW |
2688 | /* Move any buffers on the active list that are no longer referenced |
2689 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2690 | * before we free the context associated with the requests. | |
2691 | */ | |
2692 | while (!list_empty(&ring->active_list)) { | |
2693 | struct drm_i915_gem_object *obj; | |
2694 | ||
2695 | obj = list_first_entry(&ring->active_list, | |
2696 | struct drm_i915_gem_object, | |
2697 | ring_list); | |
2698 | ||
2699 | if (!i915_gem_request_completed(obj->last_read_req, true)) | |
2700 | break; | |
2701 | ||
2702 | i915_gem_object_move_to_inactive(obj); | |
2703 | } | |
2704 | ||
581c26e8 JH |
2705 | if (unlikely(ring->trace_irq_req && |
2706 | i915_gem_request_completed(ring->trace_irq_req, true))) { | |
1ec14ad3 | 2707 | ring->irq_put(ring); |
581c26e8 | 2708 | i915_gem_request_assign(&ring->trace_irq_req, NULL); |
9d34e5db | 2709 | } |
23bc5982 | 2710 | |
db53a302 | 2711 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2712 | } |
2713 | ||
b29c19b6 | 2714 | bool |
b09a1fec CW |
2715 | i915_gem_retire_requests(struct drm_device *dev) |
2716 | { | |
3e31c6c0 | 2717 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2718 | struct intel_engine_cs *ring; |
b29c19b6 | 2719 | bool idle = true; |
1ec14ad3 | 2720 | int i; |
b09a1fec | 2721 | |
b29c19b6 | 2722 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2723 | i915_gem_retire_requests_ring(ring); |
b29c19b6 | 2724 | idle &= list_empty(&ring->request_list); |
c86ee3a9 TD |
2725 | if (i915.enable_execlists) { |
2726 | unsigned long flags; | |
2727 | ||
2728 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2729 | idle &= list_empty(&ring->execlist_queue); | |
2730 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
2731 | ||
2732 | intel_execlists_retire_requests(ring); | |
2733 | } | |
b29c19b6 CW |
2734 | } |
2735 | ||
2736 | if (idle) | |
2737 | mod_delayed_work(dev_priv->wq, | |
2738 | &dev_priv->mm.idle_work, | |
2739 | msecs_to_jiffies(100)); | |
2740 | ||
2741 | return idle; | |
b09a1fec CW |
2742 | } |
2743 | ||
75ef9da2 | 2744 | static void |
673a394b EA |
2745 | i915_gem_retire_work_handler(struct work_struct *work) |
2746 | { | |
b29c19b6 CW |
2747 | struct drm_i915_private *dev_priv = |
2748 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2749 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2750 | bool idle; |
673a394b | 2751 | |
891b48cf | 2752 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2753 | idle = false; |
2754 | if (mutex_trylock(&dev->struct_mutex)) { | |
2755 | idle = i915_gem_retire_requests(dev); | |
2756 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2757 | } |
b29c19b6 | 2758 | if (!idle) |
bcb45086 CW |
2759 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2760 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2761 | } |
0a58705b | 2762 | |
b29c19b6 CW |
2763 | static void |
2764 | i915_gem_idle_work_handler(struct work_struct *work) | |
2765 | { | |
2766 | struct drm_i915_private *dev_priv = | |
2767 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2768 | ||
2769 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2770 | } |
2771 | ||
30dfebf3 DV |
2772 | /** |
2773 | * Ensures that an object will eventually get non-busy by flushing any required | |
2774 | * write domains, emitting any outstanding lazy request and retiring and | |
2775 | * completed requests. | |
2776 | */ | |
2777 | static int | |
2778 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2779 | { | |
41c52415 | 2780 | struct intel_engine_cs *ring; |
30dfebf3 DV |
2781 | int ret; |
2782 | ||
2783 | if (obj->active) { | |
41c52415 JH |
2784 | ring = i915_gem_request_get_ring(obj->last_read_req); |
2785 | ||
b6660d59 | 2786 | ret = i915_gem_check_olr(obj->last_read_req); |
30dfebf3 DV |
2787 | if (ret) |
2788 | return ret; | |
2789 | ||
41c52415 | 2790 | i915_gem_retire_requests_ring(ring); |
30dfebf3 DV |
2791 | } |
2792 | ||
2793 | return 0; | |
2794 | } | |
2795 | ||
23ba4fd0 BW |
2796 | /** |
2797 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2798 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2799 | * | |
2800 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2801 | * the timeout parameter. | |
2802 | * -ETIME: object is still busy after timeout | |
2803 | * -ERESTARTSYS: signal interrupted the wait | |
2804 | * -ENONENT: object doesn't exist | |
2805 | * Also possible, but rare: | |
2806 | * -EAGAIN: GPU wedged | |
2807 | * -ENOMEM: damn | |
2808 | * -ENODEV: Internal IRQ fail | |
2809 | * -E?: The add request failed | |
2810 | * | |
2811 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2812 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2813 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2814 | * without holding struct_mutex the object may become re-busied before this | |
2815 | * function completes. A similar but shorter * race condition exists in the busy | |
2816 | * ioctl | |
2817 | */ | |
2818 | int | |
2819 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2820 | { | |
3e31c6c0 | 2821 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2822 | struct drm_i915_gem_wait *args = data; |
2823 | struct drm_i915_gem_object *obj; | |
ff865885 | 2824 | struct drm_i915_gem_request *req; |
f69061be | 2825 | unsigned reset_counter; |
23ba4fd0 BW |
2826 | int ret = 0; |
2827 | ||
11b5d511 DV |
2828 | if (args->flags != 0) |
2829 | return -EINVAL; | |
2830 | ||
23ba4fd0 BW |
2831 | ret = i915_mutex_lock_interruptible(dev); |
2832 | if (ret) | |
2833 | return ret; | |
2834 | ||
2835 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2836 | if (&obj->base == NULL) { | |
2837 | mutex_unlock(&dev->struct_mutex); | |
2838 | return -ENOENT; | |
2839 | } | |
2840 | ||
30dfebf3 DV |
2841 | /* Need to make sure the object gets inactive eventually. */ |
2842 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2843 | if (ret) |
2844 | goto out; | |
2845 | ||
97b2a6a1 JH |
2846 | if (!obj->active || !obj->last_read_req) |
2847 | goto out; | |
23ba4fd0 | 2848 | |
ff865885 | 2849 | req = obj->last_read_req; |
23ba4fd0 | 2850 | |
23ba4fd0 | 2851 | /* Do this after OLR check to make sure we make forward progress polling |
762e4583 | 2852 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
23ba4fd0 | 2853 | */ |
762e4583 | 2854 | if (args->timeout_ns == 0) { |
23ba4fd0 BW |
2855 | ret = -ETIME; |
2856 | goto out; | |
2857 | } | |
2858 | ||
2859 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2860 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 2861 | i915_gem_request_reference(req); |
23ba4fd0 BW |
2862 | mutex_unlock(&dev->struct_mutex); |
2863 | ||
762e4583 CW |
2864 | ret = __i915_wait_request(req, reset_counter, true, |
2865 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, | |
9c654818 | 2866 | file->driver_priv); |
ff865885 JH |
2867 | mutex_lock(&dev->struct_mutex); |
2868 | i915_gem_request_unreference(req); | |
2869 | mutex_unlock(&dev->struct_mutex); | |
2870 | return ret; | |
23ba4fd0 BW |
2871 | |
2872 | out: | |
2873 | drm_gem_object_unreference(&obj->base); | |
2874 | mutex_unlock(&dev->struct_mutex); | |
2875 | return ret; | |
2876 | } | |
2877 | ||
5816d648 BW |
2878 | /** |
2879 | * i915_gem_object_sync - sync an object to a ring. | |
2880 | * | |
2881 | * @obj: object which may be in use on another ring. | |
2882 | * @to: ring we wish to use the object on. May be NULL. | |
2883 | * | |
2884 | * This code is meant to abstract object synchronization with the GPU. | |
2885 | * Calling with NULL implies synchronizing the object with the CPU | |
2886 | * rather than a particular GPU ring. | |
2887 | * | |
2888 | * Returns 0 if successful, else propagates up the lower layer error. | |
2889 | */ | |
2911a35b BW |
2890 | int |
2891 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2892 | struct intel_engine_cs *to) |
2911a35b | 2893 | { |
41c52415 | 2894 | struct intel_engine_cs *from; |
2911a35b BW |
2895 | u32 seqno; |
2896 | int ret, idx; | |
2897 | ||
41c52415 JH |
2898 | from = i915_gem_request_get_ring(obj->last_read_req); |
2899 | ||
2911a35b BW |
2900 | if (from == NULL || to == from) |
2901 | return 0; | |
2902 | ||
5816d648 | 2903 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2904 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2905 | |
2906 | idx = intel_ring_sync_index(from, to); | |
2907 | ||
97b2a6a1 | 2908 | seqno = i915_gem_request_get_seqno(obj->last_read_req); |
ddd4dbc6 RV |
2909 | /* Optimization: Avoid semaphore sync when we are sure we already |
2910 | * waited for an object with higher seqno */ | |
ebc348b2 | 2911 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2912 | return 0; |
2913 | ||
b6660d59 | 2914 | ret = i915_gem_check_olr(obj->last_read_req); |
b4aca010 BW |
2915 | if (ret) |
2916 | return ret; | |
2911a35b | 2917 | |
74328ee5 | 2918 | trace_i915_gem_ring_sync_to(from, to, obj->last_read_req); |
ebc348b2 | 2919 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 2920 | if (!ret) |
97b2a6a1 | 2921 | /* We use last_read_req because sync_to() |
7b01e260 MK |
2922 | * might have just caused seqno wrap under |
2923 | * the radar. | |
2924 | */ | |
97b2a6a1 JH |
2925 | from->semaphore.sync_seqno[idx] = |
2926 | i915_gem_request_get_seqno(obj->last_read_req); | |
2911a35b | 2927 | |
e3a5a225 | 2928 | return ret; |
2911a35b BW |
2929 | } |
2930 | ||
b5ffc9bc CW |
2931 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2932 | { | |
2933 | u32 old_write_domain, old_read_domains; | |
2934 | ||
b5ffc9bc CW |
2935 | /* Force a pagefault for domain tracking on next user access */ |
2936 | i915_gem_release_mmap(obj); | |
2937 | ||
b97c3d9c KP |
2938 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2939 | return; | |
2940 | ||
97c809fd CW |
2941 | /* Wait for any direct GTT access to complete */ |
2942 | mb(); | |
2943 | ||
b5ffc9bc CW |
2944 | old_read_domains = obj->base.read_domains; |
2945 | old_write_domain = obj->base.write_domain; | |
2946 | ||
2947 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2948 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2949 | ||
2950 | trace_i915_gem_object_change_domain(obj, | |
2951 | old_read_domains, | |
2952 | old_write_domain); | |
2953 | } | |
2954 | ||
07fe0b12 | 2955 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2956 | { |
07fe0b12 | 2957 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 2958 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2959 | int ret; |
673a394b | 2960 | |
07fe0b12 | 2961 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2962 | return 0; |
2963 | ||
0ff501cb DV |
2964 | if (!drm_mm_node_allocated(&vma->node)) { |
2965 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
2966 | return 0; |
2967 | } | |
433544bd | 2968 | |
d7f46fc4 | 2969 | if (vma->pin_count) |
31d8d651 | 2970 | return -EBUSY; |
673a394b | 2971 | |
c4670ad0 CW |
2972 | BUG_ON(obj->pages == NULL); |
2973 | ||
a8198eea | 2974 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2975 | if (ret) |
a8198eea CW |
2976 | return ret; |
2977 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2978 | * should be safe and we need to cleanup or else we might | |
2979 | * cause memory corruption through use-after-free. | |
2980 | */ | |
2981 | ||
fe14d5f4 TU |
2982 | if (i915_is_ggtt(vma->vm) && |
2983 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
8b1bc9b4 | 2984 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2985 | |
8b1bc9b4 DV |
2986 | /* release the fence reg _after_ flushing */ |
2987 | ret = i915_gem_object_put_fence(obj); | |
2988 | if (ret) | |
2989 | return ret; | |
2990 | } | |
96b47b65 | 2991 | |
07fe0b12 | 2992 | trace_i915_vma_unbind(vma); |
db53a302 | 2993 | |
6f65e29a BW |
2994 | vma->unbind_vma(vma); |
2995 | ||
64bf9303 | 2996 | list_del_init(&vma->mm_list); |
fe14d5f4 TU |
2997 | if (i915_is_ggtt(vma->vm)) { |
2998 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
2999 | obj->map_and_fenceable = false; | |
3000 | } else if (vma->ggtt_view.pages) { | |
3001 | sg_free_table(vma->ggtt_view.pages); | |
3002 | kfree(vma->ggtt_view.pages); | |
3003 | vma->ggtt_view.pages = NULL; | |
3004 | } | |
3005 | } | |
673a394b | 3006 | |
2f633156 BW |
3007 | drm_mm_remove_node(&vma->node); |
3008 | i915_gem_vma_destroy(vma); | |
3009 | ||
3010 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3011 | * no more VMAs exist. */ |
9490edb5 | 3012 | if (list_empty(&obj->vma_list)) { |
fe14d5f4 TU |
3013 | /* Throw away the active reference before |
3014 | * moving to the unbound list. */ | |
3015 | i915_gem_object_retire(obj); | |
3016 | ||
9490edb5 | 3017 | i915_gem_gtt_finish_object(obj); |
2f633156 | 3018 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
9490edb5 | 3019 | } |
673a394b | 3020 | |
70903c3b CW |
3021 | /* And finally now the object is completely decoupled from this vma, |
3022 | * we can drop its hold on the backing storage and allow it to be | |
3023 | * reaped by the shrinker. | |
3024 | */ | |
3025 | i915_gem_object_unpin_pages(obj); | |
3026 | ||
88241785 | 3027 | return 0; |
54cf91dc CW |
3028 | } |
3029 | ||
b2da9fe5 | 3030 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3031 | { |
3e31c6c0 | 3032 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3033 | struct intel_engine_cs *ring; |
1ec14ad3 | 3034 | int ret, i; |
4df2faf4 | 3035 | |
4df2faf4 | 3036 | /* Flush everything onto the inactive list. */ |
b4519513 | 3037 | for_each_ring(ring, dev_priv, i) { |
ecdb5fd8 TD |
3038 | if (!i915.enable_execlists) { |
3039 | ret = i915_switch_context(ring, ring->default_context); | |
3040 | if (ret) | |
3041 | return ret; | |
3042 | } | |
b6c7488d | 3043 | |
3e960501 | 3044 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
3045 | if (ret) |
3046 | return ret; | |
3047 | } | |
4df2faf4 | 3048 | |
8a1a49f9 | 3049 | return 0; |
4df2faf4 DV |
3050 | } |
3051 | ||
9ce079e4 CW |
3052 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
3053 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3054 | { |
3e31c6c0 | 3055 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
3056 | int fence_reg; |
3057 | int fence_pitch_shift; | |
de151cf6 | 3058 | |
56c844e5 ID |
3059 | if (INTEL_INFO(dev)->gen >= 6) { |
3060 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
3061 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
3062 | } else { | |
3063 | fence_reg = FENCE_REG_965_0; | |
3064 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
3065 | } | |
3066 | ||
d18b9619 CW |
3067 | fence_reg += reg * 8; |
3068 | ||
3069 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
3070 | * we split the 64-bit update into two 32-bit writes. In order | |
3071 | * for a partial fence not to be evaluated between writes, we | |
3072 | * precede the update with write to turn off the fence register, | |
3073 | * and only enable the fence as the last step. | |
3074 | * | |
3075 | * For extra levels of paranoia, we make sure each step lands | |
3076 | * before applying the next step. | |
3077 | */ | |
3078 | I915_WRITE(fence_reg, 0); | |
3079 | POSTING_READ(fence_reg); | |
3080 | ||
9ce079e4 | 3081 | if (obj) { |
f343c5f6 | 3082 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 3083 | uint64_t val; |
de151cf6 | 3084 | |
af1a7301 BP |
3085 | /* Adjust fence size to match tiled area */ |
3086 | if (obj->tiling_mode != I915_TILING_NONE) { | |
3087 | uint32_t row_size = obj->stride * | |
3088 | (obj->tiling_mode == I915_TILING_Y ? 32 : 8); | |
3089 | size = (size / row_size) * row_size; | |
3090 | } | |
3091 | ||
f343c5f6 | 3092 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3093 | 0xfffff000) << 32; |
f343c5f6 | 3094 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3095 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3096 | if (obj->tiling_mode == I915_TILING_Y) |
3097 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3098 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3099 | |
d18b9619 CW |
3100 | I915_WRITE(fence_reg + 4, val >> 32); |
3101 | POSTING_READ(fence_reg + 4); | |
3102 | ||
3103 | I915_WRITE(fence_reg + 0, val); | |
3104 | POSTING_READ(fence_reg); | |
3105 | } else { | |
3106 | I915_WRITE(fence_reg + 4, 0); | |
3107 | POSTING_READ(fence_reg + 4); | |
3108 | } | |
de151cf6 JB |
3109 | } |
3110 | ||
9ce079e4 CW |
3111 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3112 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3113 | { |
3e31c6c0 | 3114 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3115 | u32 val; |
de151cf6 | 3116 | |
9ce079e4 | 3117 | if (obj) { |
f343c5f6 | 3118 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3119 | int pitch_val; |
3120 | int tile_width; | |
c6642782 | 3121 | |
f343c5f6 | 3122 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3123 | (size & -size) != size || |
f343c5f6 BW |
3124 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3125 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3126 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3127 | |
9ce079e4 CW |
3128 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3129 | tile_width = 128; | |
3130 | else | |
3131 | tile_width = 512; | |
3132 | ||
3133 | /* Note: pitch better be a power of two tile widths */ | |
3134 | pitch_val = obj->stride / tile_width; | |
3135 | pitch_val = ffs(pitch_val) - 1; | |
3136 | ||
f343c5f6 | 3137 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3138 | if (obj->tiling_mode == I915_TILING_Y) |
3139 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3140 | val |= I915_FENCE_SIZE_BITS(size); | |
3141 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3142 | val |= I830_FENCE_REG_VALID; | |
3143 | } else | |
3144 | val = 0; | |
3145 | ||
3146 | if (reg < 8) | |
3147 | reg = FENCE_REG_830_0 + reg * 4; | |
3148 | else | |
3149 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3150 | ||
3151 | I915_WRITE(reg, val); | |
3152 | POSTING_READ(reg); | |
de151cf6 JB |
3153 | } |
3154 | ||
9ce079e4 CW |
3155 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3156 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3157 | { |
3e31c6c0 | 3158 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3159 | uint32_t val; |
de151cf6 | 3160 | |
9ce079e4 | 3161 | if (obj) { |
f343c5f6 | 3162 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3163 | uint32_t pitch_val; |
de151cf6 | 3164 | |
f343c5f6 | 3165 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3166 | (size & -size) != size || |
f343c5f6 BW |
3167 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3168 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3169 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3170 | |
9ce079e4 CW |
3171 | pitch_val = obj->stride / 128; |
3172 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3173 | |
f343c5f6 | 3174 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3175 | if (obj->tiling_mode == I915_TILING_Y) |
3176 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3177 | val |= I830_FENCE_SIZE_BITS(size); | |
3178 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3179 | val |= I830_FENCE_REG_VALID; | |
3180 | } else | |
3181 | val = 0; | |
c6642782 | 3182 | |
9ce079e4 CW |
3183 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3184 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3185 | } | |
3186 | ||
d0a57789 CW |
3187 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3188 | { | |
3189 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3190 | } | |
3191 | ||
9ce079e4 CW |
3192 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3193 | struct drm_i915_gem_object *obj) | |
3194 | { | |
d0a57789 CW |
3195 | struct drm_i915_private *dev_priv = dev->dev_private; |
3196 | ||
3197 | /* Ensure that all CPU reads are completed before installing a fence | |
3198 | * and all writes before removing the fence. | |
3199 | */ | |
3200 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3201 | mb(); | |
3202 | ||
94a335db DV |
3203 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3204 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3205 | obj->stride, obj->tiling_mode); | |
3206 | ||
ce38ab05 RV |
3207 | if (IS_GEN2(dev)) |
3208 | i830_write_fence_reg(dev, reg, obj); | |
3209 | else if (IS_GEN3(dev)) | |
3210 | i915_write_fence_reg(dev, reg, obj); | |
3211 | else if (INTEL_INFO(dev)->gen >= 4) | |
3212 | i965_write_fence_reg(dev, reg, obj); | |
d0a57789 CW |
3213 | |
3214 | /* And similarly be paranoid that no direct access to this region | |
3215 | * is reordered to before the fence is installed. | |
3216 | */ | |
3217 | if (i915_gem_object_needs_mb(obj)) | |
3218 | mb(); | |
de151cf6 JB |
3219 | } |
3220 | ||
61050808 CW |
3221 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3222 | struct drm_i915_fence_reg *fence) | |
3223 | { | |
3224 | return fence - dev_priv->fence_regs; | |
3225 | } | |
3226 | ||
3227 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3228 | struct drm_i915_fence_reg *fence, | |
3229 | bool enable) | |
3230 | { | |
2dc8aae0 | 3231 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3232 | int reg = fence_number(dev_priv, fence); |
3233 | ||
3234 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3235 | |
3236 | if (enable) { | |
46a0b638 | 3237 | obj->fence_reg = reg; |
61050808 CW |
3238 | fence->obj = obj; |
3239 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3240 | } else { | |
3241 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3242 | fence->obj = NULL; | |
3243 | list_del_init(&fence->lru_list); | |
3244 | } | |
94a335db | 3245 | obj->fence_dirty = false; |
61050808 CW |
3246 | } |
3247 | ||
d9e86c0e | 3248 | static int |
d0a57789 | 3249 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3250 | { |
97b2a6a1 | 3251 | if (obj->last_fenced_req) { |
a4b3a571 | 3252 | int ret = i915_wait_request(obj->last_fenced_req); |
18991845 CW |
3253 | if (ret) |
3254 | return ret; | |
d9e86c0e | 3255 | |
97b2a6a1 | 3256 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
d9e86c0e CW |
3257 | } |
3258 | ||
3259 | return 0; | |
3260 | } | |
3261 | ||
3262 | int | |
3263 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3264 | { | |
61050808 | 3265 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3266 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3267 | int ret; |
3268 | ||
d0a57789 | 3269 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3270 | if (ret) |
3271 | return ret; | |
3272 | ||
61050808 CW |
3273 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3274 | return 0; | |
d9e86c0e | 3275 | |
f9c513e9 CW |
3276 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3277 | ||
aff10b30 DV |
3278 | if (WARN_ON(fence->pin_count)) |
3279 | return -EBUSY; | |
3280 | ||
61050808 | 3281 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3282 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3283 | |
3284 | return 0; | |
3285 | } | |
3286 | ||
3287 | static struct drm_i915_fence_reg * | |
a360bb1a | 3288 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3289 | { |
ae3db24a | 3290 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3291 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3292 | int i; |
ae3db24a DV |
3293 | |
3294 | /* First try to find a free reg */ | |
d9e86c0e | 3295 | avail = NULL; |
ae3db24a DV |
3296 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3297 | reg = &dev_priv->fence_regs[i]; | |
3298 | if (!reg->obj) | |
d9e86c0e | 3299 | return reg; |
ae3db24a | 3300 | |
1690e1eb | 3301 | if (!reg->pin_count) |
d9e86c0e | 3302 | avail = reg; |
ae3db24a DV |
3303 | } |
3304 | ||
d9e86c0e | 3305 | if (avail == NULL) |
5dce5b93 | 3306 | goto deadlock; |
ae3db24a DV |
3307 | |
3308 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3309 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3310 | if (reg->pin_count) |
ae3db24a DV |
3311 | continue; |
3312 | ||
8fe301ad | 3313 | return reg; |
ae3db24a DV |
3314 | } |
3315 | ||
5dce5b93 CW |
3316 | deadlock: |
3317 | /* Wait for completion of pending flips which consume fences */ | |
3318 | if (intel_has_pending_fb_unpin(dev)) | |
3319 | return ERR_PTR(-EAGAIN); | |
3320 | ||
3321 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3322 | } |
3323 | ||
de151cf6 | 3324 | /** |
9a5a53b3 | 3325 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3326 | * @obj: object to map through a fence reg |
3327 | * | |
3328 | * When mapping objects through the GTT, userspace wants to be able to write | |
3329 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3330 | * This function walks the fence regs looking for a free one for @obj, |
3331 | * stealing one if it can't find any. | |
3332 | * | |
3333 | * It then sets up the reg based on the object's properties: address, pitch | |
3334 | * and tiling format. | |
9a5a53b3 CW |
3335 | * |
3336 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3337 | */ |
8c4b8c3f | 3338 | int |
06d98131 | 3339 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3340 | { |
05394f39 | 3341 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3342 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3343 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3344 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3345 | int ret; |
de151cf6 | 3346 | |
14415745 CW |
3347 | /* Have we updated the tiling parameters upon the object and so |
3348 | * will need to serialise the write to the associated fence register? | |
3349 | */ | |
5d82e3e6 | 3350 | if (obj->fence_dirty) { |
d0a57789 | 3351 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3352 | if (ret) |
3353 | return ret; | |
3354 | } | |
9a5a53b3 | 3355 | |
d9e86c0e | 3356 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3357 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3358 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3359 | if (!obj->fence_dirty) { |
14415745 CW |
3360 | list_move_tail(®->lru_list, |
3361 | &dev_priv->mm.fence_list); | |
3362 | return 0; | |
3363 | } | |
3364 | } else if (enable) { | |
e6a84468 CW |
3365 | if (WARN_ON(!obj->map_and_fenceable)) |
3366 | return -EINVAL; | |
3367 | ||
14415745 | 3368 | reg = i915_find_fence_reg(dev); |
5dce5b93 CW |
3369 | if (IS_ERR(reg)) |
3370 | return PTR_ERR(reg); | |
d9e86c0e | 3371 | |
14415745 CW |
3372 | if (reg->obj) { |
3373 | struct drm_i915_gem_object *old = reg->obj; | |
3374 | ||
d0a57789 | 3375 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3376 | if (ret) |
3377 | return ret; | |
3378 | ||
14415745 | 3379 | i915_gem_object_fence_lost(old); |
29c5a587 | 3380 | } |
14415745 | 3381 | } else |
a09ba7fa | 3382 | return 0; |
a09ba7fa | 3383 | |
14415745 | 3384 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3385 | |
9ce079e4 | 3386 | return 0; |
de151cf6 JB |
3387 | } |
3388 | ||
4144f9b5 | 3389 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3390 | unsigned long cache_level) |
3391 | { | |
4144f9b5 | 3392 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3393 | struct drm_mm_node *other; |
3394 | ||
4144f9b5 CW |
3395 | /* |
3396 | * On some machines we have to be careful when putting differing types | |
3397 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3398 | * domains and dying. During vm initialisation, we decide whether or not | |
3399 | * these constraints apply and set the drm_mm.color_adjust | |
3400 | * appropriately. | |
42d6ab48 | 3401 | */ |
4144f9b5 | 3402 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3403 | return true; |
3404 | ||
c6cfb325 | 3405 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3406 | return true; |
3407 | ||
3408 | if (list_empty(>t_space->node_list)) | |
3409 | return true; | |
3410 | ||
3411 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3412 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3413 | return false; | |
3414 | ||
3415 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3416 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3417 | return false; | |
3418 | ||
3419 | return true; | |
3420 | } | |
3421 | ||
673a394b EA |
3422 | /** |
3423 | * Finds free space in the GTT aperture and binds the object there. | |
3424 | */ | |
262de145 | 3425 | static struct i915_vma * |
07fe0b12 BW |
3426 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3427 | struct i915_address_space *vm, | |
ec7adb6e | 3428 | const struct i915_ggtt_view *ggtt_view, |
07fe0b12 | 3429 | unsigned alignment, |
ec7adb6e | 3430 | uint64_t flags) |
673a394b | 3431 | { |
05394f39 | 3432 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3433 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3434 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3435 | unsigned long start = |
3436 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3437 | unsigned long end = | |
1ec9e26d | 3438 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3439 | struct i915_vma *vma; |
07f73f69 | 3440 | int ret; |
673a394b | 3441 | |
ec7adb6e JL |
3442 | if(WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
3443 | return ERR_PTR(-EINVAL); | |
3444 | ||
e28f8711 CW |
3445 | fence_size = i915_gem_get_gtt_size(dev, |
3446 | obj->base.size, | |
3447 | obj->tiling_mode); | |
3448 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3449 | obj->base.size, | |
d865110c | 3450 | obj->tiling_mode, true); |
e28f8711 | 3451 | unfenced_alignment = |
d865110c | 3452 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3453 | obj->base.size, |
3454 | obj->tiling_mode, false); | |
a00b10c3 | 3455 | |
673a394b | 3456 | if (alignment == 0) |
1ec9e26d | 3457 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3458 | unfenced_alignment; |
1ec9e26d | 3459 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3460 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3461 | return ERR_PTR(-EINVAL); |
673a394b EA |
3462 | } |
3463 | ||
1ec9e26d | 3464 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3465 | |
654fc607 CW |
3466 | /* If the object is bigger than the entire aperture, reject it early |
3467 | * before evicting everything in a vain attempt to find space. | |
3468 | */ | |
d23db88c CW |
3469 | if (obj->base.size > end) { |
3470 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", | |
a36689cb | 3471 | obj->base.size, |
1ec9e26d | 3472 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3473 | end); |
262de145 | 3474 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3475 | } |
3476 | ||
37e680a1 | 3477 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3478 | if (ret) |
262de145 | 3479 | return ERR_PTR(ret); |
6c085a72 | 3480 | |
fbdda6fb CW |
3481 | i915_gem_object_pin_pages(obj); |
3482 | ||
ec7adb6e JL |
3483 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
3484 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3485 | ||
262de145 | 3486 | if (IS_ERR(vma)) |
bc6bc15b | 3487 | goto err_unpin; |
2f633156 | 3488 | |
0a9ae0d7 | 3489 | search_free: |
07fe0b12 | 3490 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3491 | size, alignment, |
d23db88c CW |
3492 | obj->cache_level, |
3493 | start, end, | |
62347f9e LK |
3494 | DRM_MM_SEARCH_DEFAULT, |
3495 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3496 | if (ret) { |
f6cd1f15 | 3497 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3498 | obj->cache_level, |
3499 | start, end, | |
3500 | flags); | |
dc9dd7a2 CW |
3501 | if (ret == 0) |
3502 | goto search_free; | |
9731129c | 3503 | |
bc6bc15b | 3504 | goto err_free_vma; |
673a394b | 3505 | } |
4144f9b5 | 3506 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3507 | ret = -EINVAL; |
bc6bc15b | 3508 | goto err_remove_node; |
673a394b EA |
3509 | } |
3510 | ||
74163907 | 3511 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3512 | if (ret) |
bc6bc15b | 3513 | goto err_remove_node; |
673a394b | 3514 | |
678d96fb BW |
3515 | /* allocate before insert / bind */ |
3516 | if (vma->vm->allocate_va_range) { | |
72744cb1 MT |
3517 | trace_i915_va_alloc(vma->vm, vma->node.start, vma->node.size, |
3518 | VM_TO_TRACE_NAME(vma->vm)); | |
678d96fb BW |
3519 | ret = vma->vm->allocate_va_range(vma->vm, |
3520 | vma->node.start, | |
3521 | vma->node.size); | |
3522 | if (ret) | |
3523 | goto err_remove_node; | |
3524 | } | |
3525 | ||
fe14d5f4 TU |
3526 | trace_i915_vma_bind(vma, flags); |
3527 | ret = i915_vma_bind(vma, obj->cache_level, | |
3528 | flags & PIN_GLOBAL ? GLOBAL_BIND : 0); | |
3529 | if (ret) | |
3530 | goto err_finish_gtt; | |
3531 | ||
35c20a60 | 3532 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3533 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3534 | |
262de145 | 3535 | return vma; |
2f633156 | 3536 | |
fe14d5f4 TU |
3537 | err_finish_gtt: |
3538 | i915_gem_gtt_finish_object(obj); | |
bc6bc15b | 3539 | err_remove_node: |
6286ef9b | 3540 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3541 | err_free_vma: |
2f633156 | 3542 | i915_gem_vma_destroy(vma); |
262de145 | 3543 | vma = ERR_PTR(ret); |
bc6bc15b | 3544 | err_unpin: |
2f633156 | 3545 | i915_gem_object_unpin_pages(obj); |
262de145 | 3546 | return vma; |
673a394b EA |
3547 | } |
3548 | ||
000433b6 | 3549 | bool |
2c22569b CW |
3550 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3551 | bool force) | |
673a394b | 3552 | { |
673a394b EA |
3553 | /* If we don't have a page list set up, then we're not pinned |
3554 | * to GPU, and we can ignore the cache flush because it'll happen | |
3555 | * again at bind time. | |
3556 | */ | |
05394f39 | 3557 | if (obj->pages == NULL) |
000433b6 | 3558 | return false; |
673a394b | 3559 | |
769ce464 ID |
3560 | /* |
3561 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3562 | * marked as wc by the system, or the system is cache-coherent. | |
3563 | */ | |
6a2c4232 | 3564 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3565 | return false; |
769ce464 | 3566 | |
9c23f7fc CW |
3567 | /* If the GPU is snooping the contents of the CPU cache, |
3568 | * we do not need to manually clear the CPU cache lines. However, | |
3569 | * the caches are only snooped when the render cache is | |
3570 | * flushed/invalidated. As we always have to emit invalidations | |
3571 | * and flushes when moving into and out of the RENDER domain, correct | |
3572 | * snooping behaviour occurs naturally as the result of our domain | |
3573 | * tracking. | |
3574 | */ | |
0f71979a CW |
3575 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3576 | obj->cache_dirty = true; | |
000433b6 | 3577 | return false; |
0f71979a | 3578 | } |
9c23f7fc | 3579 | |
1c5d22f7 | 3580 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3581 | drm_clflush_sg(obj->pages); |
0f71979a | 3582 | obj->cache_dirty = false; |
000433b6 CW |
3583 | |
3584 | return true; | |
e47c68e9 EA |
3585 | } |
3586 | ||
3587 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3588 | static void | |
05394f39 | 3589 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3590 | { |
1c5d22f7 CW |
3591 | uint32_t old_write_domain; |
3592 | ||
05394f39 | 3593 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3594 | return; |
3595 | ||
63256ec5 | 3596 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3597 | * to it immediately go to main memory as far as we know, so there's |
3598 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3599 | * |
3600 | * However, we do have to enforce the order so that all writes through | |
3601 | * the GTT land before any writes to the device, such as updates to | |
3602 | * the GATT itself. | |
e47c68e9 | 3603 | */ |
63256ec5 CW |
3604 | wmb(); |
3605 | ||
05394f39 CW |
3606 | old_write_domain = obj->base.write_domain; |
3607 | obj->base.write_domain = 0; | |
1c5d22f7 | 3608 | |
f99d7069 DV |
3609 | intel_fb_obj_flush(obj, false); |
3610 | ||
1c5d22f7 | 3611 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3612 | obj->base.read_domains, |
1c5d22f7 | 3613 | old_write_domain); |
e47c68e9 EA |
3614 | } |
3615 | ||
3616 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3617 | static void | |
e62b59e4 | 3618 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3619 | { |
1c5d22f7 | 3620 | uint32_t old_write_domain; |
e47c68e9 | 3621 | |
05394f39 | 3622 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3623 | return; |
3624 | ||
e62b59e4 | 3625 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
000433b6 CW |
3626 | i915_gem_chipset_flush(obj->base.dev); |
3627 | ||
05394f39 CW |
3628 | old_write_domain = obj->base.write_domain; |
3629 | obj->base.write_domain = 0; | |
1c5d22f7 | 3630 | |
f99d7069 DV |
3631 | intel_fb_obj_flush(obj, false); |
3632 | ||
1c5d22f7 | 3633 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3634 | obj->base.read_domains, |
1c5d22f7 | 3635 | old_write_domain); |
e47c68e9 EA |
3636 | } |
3637 | ||
2ef7eeaa EA |
3638 | /** |
3639 | * Moves a single object to the GTT read, and possibly write domain. | |
3640 | * | |
3641 | * This function returns when the move is complete, including waiting on | |
3642 | * flushes to occur. | |
3643 | */ | |
79e53945 | 3644 | int |
2021746e | 3645 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3646 | { |
1c5d22f7 | 3647 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3648 | struct i915_vma *vma; |
e47c68e9 | 3649 | int ret; |
2ef7eeaa | 3650 | |
8d7e3de1 CW |
3651 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3652 | return 0; | |
3653 | ||
0201f1ec | 3654 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3655 | if (ret) |
3656 | return ret; | |
3657 | ||
c8725f3d | 3658 | i915_gem_object_retire(obj); |
43566ded CW |
3659 | |
3660 | /* Flush and acquire obj->pages so that we are coherent through | |
3661 | * direct access in memory with previous cached writes through | |
3662 | * shmemfs and that our cache domain tracking remains valid. | |
3663 | * For example, if the obj->filp was moved to swap without us | |
3664 | * being notified and releasing the pages, we would mistakenly | |
3665 | * continue to assume that the obj remained out of the CPU cached | |
3666 | * domain. | |
3667 | */ | |
3668 | ret = i915_gem_object_get_pages(obj); | |
3669 | if (ret) | |
3670 | return ret; | |
3671 | ||
e62b59e4 | 3672 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3673 | |
d0a57789 CW |
3674 | /* Serialise direct access to this object with the barriers for |
3675 | * coherent writes from the GPU, by effectively invalidating the | |
3676 | * GTT domain upon first access. | |
3677 | */ | |
3678 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3679 | mb(); | |
3680 | ||
05394f39 CW |
3681 | old_write_domain = obj->base.write_domain; |
3682 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3683 | |
e47c68e9 EA |
3684 | /* It should now be out of any other write domains, and we can update |
3685 | * the domain values for our changes. | |
3686 | */ | |
05394f39 CW |
3687 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3688 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3689 | if (write) { |
05394f39 CW |
3690 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3691 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3692 | obj->dirty = 1; | |
2ef7eeaa EA |
3693 | } |
3694 | ||
f99d7069 | 3695 | if (write) |
a4001f1b | 3696 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT); |
f99d7069 | 3697 | |
1c5d22f7 CW |
3698 | trace_i915_gem_object_change_domain(obj, |
3699 | old_read_domains, | |
3700 | old_write_domain); | |
3701 | ||
8325a09d | 3702 | /* And bump the LRU for this access */ |
43566ded CW |
3703 | vma = i915_gem_obj_to_ggtt(obj); |
3704 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
dc8cd1e7 | 3705 | list_move_tail(&vma->mm_list, |
43566ded | 3706 | &to_i915(obj->base.dev)->gtt.base.inactive_list); |
8325a09d | 3707 | |
e47c68e9 EA |
3708 | return 0; |
3709 | } | |
3710 | ||
e4ffd173 CW |
3711 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3712 | enum i915_cache_level cache_level) | |
3713 | { | |
7bddb01f | 3714 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3715 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3716 | int ret; |
3717 | ||
3718 | if (obj->cache_level == cache_level) | |
3719 | return 0; | |
3720 | ||
d7f46fc4 | 3721 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3722 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3723 | return -EBUSY; | |
3724 | } | |
3725 | ||
df6f783a | 3726 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4144f9b5 | 3727 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3728 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3729 | if (ret) |
3730 | return ret; | |
3089c6f2 | 3731 | } |
42d6ab48 CW |
3732 | } |
3733 | ||
3089c6f2 | 3734 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3735 | ret = i915_gem_object_finish_gpu(obj); |
3736 | if (ret) | |
3737 | return ret; | |
3738 | ||
3739 | i915_gem_object_finish_gtt(obj); | |
3740 | ||
3741 | /* Before SandyBridge, you could not use tiling or fence | |
3742 | * registers with snooped memory, so relinquish any fences | |
3743 | * currently pointing to our region in the aperture. | |
3744 | */ | |
42d6ab48 | 3745 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3746 | ret = i915_gem_object_put_fence(obj); |
3747 | if (ret) | |
3748 | return ret; | |
3749 | } | |
3750 | ||
6f65e29a | 3751 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
fe14d5f4 TU |
3752 | if (drm_mm_node_allocated(&vma->node)) { |
3753 | ret = i915_vma_bind(vma, cache_level, | |
3754 | vma->bound & GLOBAL_BIND); | |
3755 | if (ret) | |
3756 | return ret; | |
3757 | } | |
e4ffd173 CW |
3758 | } |
3759 | ||
2c22569b CW |
3760 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3761 | vma->node.color = cache_level; | |
3762 | obj->cache_level = cache_level; | |
3763 | ||
0f71979a CW |
3764 | if (obj->cache_dirty && |
3765 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
3766 | cpu_write_needs_clflush(obj)) { | |
3767 | if (i915_gem_clflush_object(obj, true)) | |
3768 | i915_gem_chipset_flush(obj->base.dev); | |
e4ffd173 CW |
3769 | } |
3770 | ||
e4ffd173 CW |
3771 | return 0; |
3772 | } | |
3773 | ||
199adf40 BW |
3774 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3775 | struct drm_file *file) | |
e6994aee | 3776 | { |
199adf40 | 3777 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3778 | struct drm_i915_gem_object *obj; |
3779 | int ret; | |
3780 | ||
3781 | ret = i915_mutex_lock_interruptible(dev); | |
3782 | if (ret) | |
3783 | return ret; | |
3784 | ||
3785 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3786 | if (&obj->base == NULL) { | |
3787 | ret = -ENOENT; | |
3788 | goto unlock; | |
3789 | } | |
3790 | ||
651d794f CW |
3791 | switch (obj->cache_level) { |
3792 | case I915_CACHE_LLC: | |
3793 | case I915_CACHE_L3_LLC: | |
3794 | args->caching = I915_CACHING_CACHED; | |
3795 | break; | |
3796 | ||
4257d3ba CW |
3797 | case I915_CACHE_WT: |
3798 | args->caching = I915_CACHING_DISPLAY; | |
3799 | break; | |
3800 | ||
651d794f CW |
3801 | default: |
3802 | args->caching = I915_CACHING_NONE; | |
3803 | break; | |
3804 | } | |
e6994aee CW |
3805 | |
3806 | drm_gem_object_unreference(&obj->base); | |
3807 | unlock: | |
3808 | mutex_unlock(&dev->struct_mutex); | |
3809 | return ret; | |
3810 | } | |
3811 | ||
199adf40 BW |
3812 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3813 | struct drm_file *file) | |
e6994aee | 3814 | { |
199adf40 | 3815 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3816 | struct drm_i915_gem_object *obj; |
3817 | enum i915_cache_level level; | |
3818 | int ret; | |
3819 | ||
199adf40 BW |
3820 | switch (args->caching) { |
3821 | case I915_CACHING_NONE: | |
e6994aee CW |
3822 | level = I915_CACHE_NONE; |
3823 | break; | |
199adf40 | 3824 | case I915_CACHING_CACHED: |
e6994aee CW |
3825 | level = I915_CACHE_LLC; |
3826 | break; | |
4257d3ba CW |
3827 | case I915_CACHING_DISPLAY: |
3828 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3829 | break; | |
e6994aee CW |
3830 | default: |
3831 | return -EINVAL; | |
3832 | } | |
3833 | ||
3bc2913e BW |
3834 | ret = i915_mutex_lock_interruptible(dev); |
3835 | if (ret) | |
3836 | return ret; | |
3837 | ||
e6994aee CW |
3838 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3839 | if (&obj->base == NULL) { | |
3840 | ret = -ENOENT; | |
3841 | goto unlock; | |
3842 | } | |
3843 | ||
3844 | ret = i915_gem_object_set_cache_level(obj, level); | |
3845 | ||
3846 | drm_gem_object_unreference(&obj->base); | |
3847 | unlock: | |
3848 | mutex_unlock(&dev->struct_mutex); | |
3849 | return ret; | |
3850 | } | |
3851 | ||
cc98b413 CW |
3852 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3853 | { | |
19656430 OM |
3854 | struct i915_vma *vma; |
3855 | ||
19656430 OM |
3856 | vma = i915_gem_obj_to_ggtt(obj); |
3857 | if (!vma) | |
3858 | return false; | |
3859 | ||
4feb7659 | 3860 | /* There are 2 sources that pin objects: |
cc98b413 CW |
3861 | * 1. The display engine (scanouts, sprites, cursors); |
3862 | * 2. Reservations for execbuffer; | |
cc98b413 CW |
3863 | * |
3864 | * We can ignore reservations as we hold the struct_mutex and | |
4feb7659 | 3865 | * are only called outside of the reservation path. |
cc98b413 | 3866 | */ |
4feb7659 | 3867 | return vma->pin_count; |
cc98b413 CW |
3868 | } |
3869 | ||
b9241ea3 | 3870 | /* |
2da3b9b9 CW |
3871 | * Prepare buffer for display plane (scanout, cursors, etc). |
3872 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3873 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3874 | */ |
3875 | int | |
2da3b9b9 CW |
3876 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3877 | u32 alignment, | |
e6617330 TU |
3878 | struct intel_engine_cs *pipelined, |
3879 | const struct i915_ggtt_view *view) | |
b9241ea3 | 3880 | { |
2da3b9b9 | 3881 | u32 old_read_domains, old_write_domain; |
19656430 | 3882 | bool was_pin_display; |
b9241ea3 ZW |
3883 | int ret; |
3884 | ||
41c52415 | 3885 | if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) { |
2911a35b BW |
3886 | ret = i915_gem_object_sync(obj, pipelined); |
3887 | if (ret) | |
b9241ea3 ZW |
3888 | return ret; |
3889 | } | |
3890 | ||
cc98b413 CW |
3891 | /* Mark the pin_display early so that we account for the |
3892 | * display coherency whilst setting up the cache domains. | |
3893 | */ | |
19656430 | 3894 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3895 | obj->pin_display = true; |
3896 | ||
a7ef0640 EA |
3897 | /* The display engine is not coherent with the LLC cache on gen6. As |
3898 | * a result, we make sure that the pinning that is about to occur is | |
3899 | * done with uncached PTEs. This is lowest common denominator for all | |
3900 | * chipsets. | |
3901 | * | |
3902 | * However for gen6+, we could do better by using the GFDT bit instead | |
3903 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3904 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3905 | */ | |
651d794f CW |
3906 | ret = i915_gem_object_set_cache_level(obj, |
3907 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3908 | if (ret) |
cc98b413 | 3909 | goto err_unpin_display; |
a7ef0640 | 3910 | |
2da3b9b9 CW |
3911 | /* As the user may map the buffer once pinned in the display plane |
3912 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3913 | * always use map_and_fenceable for all scanout buffers. | |
3914 | */ | |
50470bb0 TU |
3915 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
3916 | view->type == I915_GGTT_VIEW_NORMAL ? | |
3917 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 3918 | if (ret) |
cc98b413 | 3919 | goto err_unpin_display; |
2da3b9b9 | 3920 | |
e62b59e4 | 3921 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3922 | |
2da3b9b9 | 3923 | old_write_domain = obj->base.write_domain; |
05394f39 | 3924 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3925 | |
3926 | /* It should now be out of any other write domains, and we can update | |
3927 | * the domain values for our changes. | |
3928 | */ | |
e5f1d962 | 3929 | obj->base.write_domain = 0; |
05394f39 | 3930 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3931 | |
3932 | trace_i915_gem_object_change_domain(obj, | |
3933 | old_read_domains, | |
2da3b9b9 | 3934 | old_write_domain); |
b9241ea3 ZW |
3935 | |
3936 | return 0; | |
cc98b413 CW |
3937 | |
3938 | err_unpin_display: | |
19656430 OM |
3939 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3940 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
3941 | return ret; |
3942 | } | |
3943 | ||
3944 | void | |
e6617330 TU |
3945 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3946 | const struct i915_ggtt_view *view) | |
cc98b413 | 3947 | { |
e6617330 TU |
3948 | i915_gem_object_ggtt_unpin_view(obj, view); |
3949 | ||
cc98b413 | 3950 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3951 | } |
3952 | ||
85345517 | 3953 | int |
a8198eea | 3954 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3955 | { |
88241785 CW |
3956 | int ret; |
3957 | ||
a8198eea | 3958 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3959 | return 0; |
3960 | ||
0201f1ec | 3961 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3962 | if (ret) |
3963 | return ret; | |
3964 | ||
a8198eea CW |
3965 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3966 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3967 | return 0; |
85345517 CW |
3968 | } |
3969 | ||
e47c68e9 EA |
3970 | /** |
3971 | * Moves a single object to the CPU read, and possibly write domain. | |
3972 | * | |
3973 | * This function returns when the move is complete, including waiting on | |
3974 | * flushes to occur. | |
3975 | */ | |
dabdfe02 | 3976 | int |
919926ae | 3977 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3978 | { |
1c5d22f7 | 3979 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3980 | int ret; |
3981 | ||
8d7e3de1 CW |
3982 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3983 | return 0; | |
3984 | ||
0201f1ec | 3985 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3986 | if (ret) |
3987 | return ret; | |
3988 | ||
c8725f3d | 3989 | i915_gem_object_retire(obj); |
e47c68e9 | 3990 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3991 | |
05394f39 CW |
3992 | old_write_domain = obj->base.write_domain; |
3993 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3994 | |
e47c68e9 | 3995 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3996 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3997 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3998 | |
05394f39 | 3999 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4000 | } |
4001 | ||
4002 | /* It should now be out of any other write domains, and we can update | |
4003 | * the domain values for our changes. | |
4004 | */ | |
05394f39 | 4005 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4006 | |
4007 | /* If we're writing through the CPU, then the GPU read domains will | |
4008 | * need to be invalidated at next use. | |
4009 | */ | |
4010 | if (write) { | |
05394f39 CW |
4011 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4012 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4013 | } |
2ef7eeaa | 4014 | |
f99d7069 | 4015 | if (write) |
a4001f1b | 4016 | intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU); |
f99d7069 | 4017 | |
1c5d22f7 CW |
4018 | trace_i915_gem_object_change_domain(obj, |
4019 | old_read_domains, | |
4020 | old_write_domain); | |
4021 | ||
2ef7eeaa EA |
4022 | return 0; |
4023 | } | |
4024 | ||
673a394b EA |
4025 | /* Throttle our rendering by waiting until the ring has completed our requests |
4026 | * emitted over 20 msec ago. | |
4027 | * | |
b962442e EA |
4028 | * Note that if we were to use the current jiffies each time around the loop, |
4029 | * we wouldn't escape the function with any frames outstanding if the time to | |
4030 | * render a frame was over 20ms. | |
4031 | * | |
673a394b EA |
4032 | * This should get us reasonable parallelism between CPU and GPU but also |
4033 | * relatively low latency when blocking on a particular request to finish. | |
4034 | */ | |
40a5f0de | 4035 | static int |
f787a5f5 | 4036 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4037 | { |
f787a5f5 CW |
4038 | struct drm_i915_private *dev_priv = dev->dev_private; |
4039 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 4040 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
54fb2411 | 4041 | struct drm_i915_gem_request *request, *target = NULL; |
f69061be | 4042 | unsigned reset_counter; |
f787a5f5 | 4043 | int ret; |
93533c29 | 4044 | |
308887aa DV |
4045 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4046 | if (ret) | |
4047 | return ret; | |
4048 | ||
4049 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4050 | if (ret) | |
4051 | return ret; | |
e110e8d6 | 4052 | |
1c25595f | 4053 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4054 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4055 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4056 | break; | |
40a5f0de | 4057 | |
54fb2411 | 4058 | target = request; |
b962442e | 4059 | } |
f69061be | 4060 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 JH |
4061 | if (target) |
4062 | i915_gem_request_reference(target); | |
1c25595f | 4063 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4064 | |
54fb2411 | 4065 | if (target == NULL) |
f787a5f5 | 4066 | return 0; |
2bc43b5c | 4067 | |
9c654818 | 4068 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4069 | if (ret == 0) |
4070 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4071 | |
ff865885 JH |
4072 | mutex_lock(&dev->struct_mutex); |
4073 | i915_gem_request_unreference(target); | |
4074 | mutex_unlock(&dev->struct_mutex); | |
4075 | ||
40a5f0de EA |
4076 | return ret; |
4077 | } | |
4078 | ||
d23db88c CW |
4079 | static bool |
4080 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4081 | { | |
4082 | struct drm_i915_gem_object *obj = vma->obj; | |
4083 | ||
4084 | if (alignment && | |
4085 | vma->node.start & (alignment - 1)) | |
4086 | return true; | |
4087 | ||
4088 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4089 | return true; | |
4090 | ||
4091 | if (flags & PIN_OFFSET_BIAS && | |
4092 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4093 | return true; | |
4094 | ||
4095 | return false; | |
4096 | } | |
4097 | ||
ec7adb6e JL |
4098 | static int |
4099 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
4100 | struct i915_address_space *vm, | |
4101 | const struct i915_ggtt_view *ggtt_view, | |
4102 | uint32_t alignment, | |
4103 | uint64_t flags) | |
673a394b | 4104 | { |
6e7186af | 4105 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4106 | struct i915_vma *vma; |
ef79e17c | 4107 | unsigned bound; |
673a394b EA |
4108 | int ret; |
4109 | ||
6e7186af BW |
4110 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4111 | return -ENODEV; | |
4112 | ||
bf3d149b | 4113 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4114 | return -EINVAL; |
07fe0b12 | 4115 | |
c826c449 CW |
4116 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4117 | return -EINVAL; | |
4118 | ||
ec7adb6e JL |
4119 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
4120 | return -EINVAL; | |
4121 | ||
4122 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
4123 | i915_gem_obj_to_vma(obj, vm); | |
4124 | ||
4125 | if (IS_ERR(vma)) | |
4126 | return PTR_ERR(vma); | |
4127 | ||
07fe0b12 | 4128 | if (vma) { |
d7f46fc4 BW |
4129 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4130 | return -EBUSY; | |
4131 | ||
d23db88c | 4132 | if (i915_vma_misplaced(vma, alignment, flags)) { |
ec7adb6e | 4133 | unsigned long offset; |
9abc4648 | 4134 | offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) : |
ec7adb6e | 4135 | i915_gem_obj_offset(obj, vm); |
d7f46fc4 | 4136 | WARN(vma->pin_count, |
ec7adb6e | 4137 | "bo is already pinned in %s with incorrect alignment:" |
f343c5f6 | 4138 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4139 | " obj->map_and_fenceable=%d\n", |
ec7adb6e JL |
4140 | ggtt_view ? "ggtt" : "ppgtt", |
4141 | offset, | |
fe14d5f4 | 4142 | alignment, |
d23db88c | 4143 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4144 | obj->map_and_fenceable); |
07fe0b12 | 4145 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4146 | if (ret) |
4147 | return ret; | |
8ea99c92 DV |
4148 | |
4149 | vma = NULL; | |
ac0c6b5a CW |
4150 | } |
4151 | } | |
4152 | ||
ef79e17c | 4153 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4154 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
563222a7 BW |
4155 | /* In true PPGTT, bind has possibly changed PDEs, which |
4156 | * means we must do a context switch before the GPU can | |
4157 | * accurately read some of the VMAs. | |
4158 | */ | |
ec7adb6e JL |
4159 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
4160 | flags); | |
262de145 DV |
4161 | if (IS_ERR(vma)) |
4162 | return PTR_ERR(vma); | |
22c344e9 | 4163 | } |
76446cac | 4164 | |
fe14d5f4 TU |
4165 | if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) { |
4166 | ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND); | |
4167 | if (ret) | |
4168 | return ret; | |
4169 | } | |
74898d7e | 4170 | |
ef79e17c CW |
4171 | if ((bound ^ vma->bound) & GLOBAL_BIND) { |
4172 | bool mappable, fenceable; | |
4173 | u32 fence_size, fence_alignment; | |
4174 | ||
4175 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4176 | obj->base.size, | |
4177 | obj->tiling_mode); | |
4178 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4179 | obj->base.size, | |
4180 | obj->tiling_mode, | |
4181 | true); | |
4182 | ||
4183 | fenceable = (vma->node.size == fence_size && | |
4184 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4185 | ||
e8dec1dd | 4186 | mappable = (vma->node.start + fence_size <= |
ef79e17c CW |
4187 | dev_priv->gtt.mappable_end); |
4188 | ||
4189 | obj->map_and_fenceable = mappable && fenceable; | |
4190 | } | |
4191 | ||
4192 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); | |
4193 | ||
8ea99c92 | 4194 | vma->pin_count++; |
1ec9e26d DV |
4195 | if (flags & PIN_MAPPABLE) |
4196 | obj->pin_mappable |= true; | |
673a394b EA |
4197 | |
4198 | return 0; | |
4199 | } | |
4200 | ||
ec7adb6e JL |
4201 | int |
4202 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
4203 | struct i915_address_space *vm, | |
4204 | uint32_t alignment, | |
4205 | uint64_t flags) | |
4206 | { | |
4207 | return i915_gem_object_do_pin(obj, vm, | |
4208 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
4209 | alignment, flags); | |
4210 | } | |
4211 | ||
4212 | int | |
4213 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
4214 | const struct i915_ggtt_view *view, | |
4215 | uint32_t alignment, | |
4216 | uint64_t flags) | |
4217 | { | |
4218 | if (WARN_ONCE(!view, "no view specified")) | |
4219 | return -EINVAL; | |
4220 | ||
4221 | return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view, | |
6fafab76 | 4222 | alignment, flags | PIN_GLOBAL); |
ec7adb6e JL |
4223 | } |
4224 | ||
673a394b | 4225 | void |
e6617330 TU |
4226 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
4227 | const struct i915_ggtt_view *view) | |
673a394b | 4228 | { |
e6617330 | 4229 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 4230 | |
d7f46fc4 | 4231 | BUG_ON(!vma); |
e6617330 | 4232 | WARN_ON(vma->pin_count == 0); |
9abc4648 | 4233 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 4234 | |
e6617330 | 4235 | if (--vma->pin_count == 0 && view->type == I915_GGTT_VIEW_NORMAL) |
6299f992 | 4236 | obj->pin_mappable = false; |
673a394b EA |
4237 | } |
4238 | ||
d8ffa60b DV |
4239 | bool |
4240 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4241 | { | |
4242 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4243 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4244 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4245 | ||
4246 | WARN_ON(!ggtt_vma || | |
4247 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4248 | ggtt_vma->pin_count); | |
4249 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4250 | return true; | |
4251 | } else | |
4252 | return false; | |
4253 | } | |
4254 | ||
4255 | void | |
4256 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4257 | { | |
4258 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4259 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4260 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4261 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4262 | } | |
4263 | } | |
4264 | ||
673a394b EA |
4265 | int |
4266 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4267 | struct drm_file *file) |
673a394b EA |
4268 | { |
4269 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4270 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4271 | int ret; |
4272 | ||
76c1dec1 | 4273 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4274 | if (ret) |
76c1dec1 | 4275 | return ret; |
673a394b | 4276 | |
05394f39 | 4277 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4278 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4279 | ret = -ENOENT; |
4280 | goto unlock; | |
673a394b | 4281 | } |
d1b851fc | 4282 | |
0be555b6 CW |
4283 | /* Count all active objects as busy, even if they are currently not used |
4284 | * by the gpu. Users of this interface expect objects to eventually | |
4285 | * become non-busy without any further actions, therefore emit any | |
4286 | * necessary flushes here. | |
c4de0a5d | 4287 | */ |
30dfebf3 | 4288 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4289 | |
30dfebf3 | 4290 | args->busy = obj->active; |
41c52415 JH |
4291 | if (obj->last_read_req) { |
4292 | struct intel_engine_cs *ring; | |
e9808edd | 4293 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
41c52415 JH |
4294 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4295 | args->busy |= intel_ring_flag(ring) << 16; | |
e9808edd | 4296 | } |
673a394b | 4297 | |
05394f39 | 4298 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4299 | unlock: |
673a394b | 4300 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4301 | return ret; |
673a394b EA |
4302 | } |
4303 | ||
4304 | int | |
4305 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4306 | struct drm_file *file_priv) | |
4307 | { | |
0206e353 | 4308 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4309 | } |
4310 | ||
3ef94daa CW |
4311 | int |
4312 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4313 | struct drm_file *file_priv) | |
4314 | { | |
656bfa3a | 4315 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4316 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4317 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4318 | int ret; |
3ef94daa CW |
4319 | |
4320 | switch (args->madv) { | |
4321 | case I915_MADV_DONTNEED: | |
4322 | case I915_MADV_WILLNEED: | |
4323 | break; | |
4324 | default: | |
4325 | return -EINVAL; | |
4326 | } | |
4327 | ||
1d7cfea1 CW |
4328 | ret = i915_mutex_lock_interruptible(dev); |
4329 | if (ret) | |
4330 | return ret; | |
4331 | ||
05394f39 | 4332 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4333 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4334 | ret = -ENOENT; |
4335 | goto unlock; | |
3ef94daa | 4336 | } |
3ef94daa | 4337 | |
d7f46fc4 | 4338 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4339 | ret = -EINVAL; |
4340 | goto out; | |
3ef94daa CW |
4341 | } |
4342 | ||
656bfa3a DV |
4343 | if (obj->pages && |
4344 | obj->tiling_mode != I915_TILING_NONE && | |
4345 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4346 | if (obj->madv == I915_MADV_WILLNEED) | |
4347 | i915_gem_object_unpin_pages(obj); | |
4348 | if (args->madv == I915_MADV_WILLNEED) | |
4349 | i915_gem_object_pin_pages(obj); | |
4350 | } | |
4351 | ||
05394f39 CW |
4352 | if (obj->madv != __I915_MADV_PURGED) |
4353 | obj->madv = args->madv; | |
3ef94daa | 4354 | |
6c085a72 | 4355 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4356 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4357 | i915_gem_object_truncate(obj); |
4358 | ||
05394f39 | 4359 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4360 | |
1d7cfea1 | 4361 | out: |
05394f39 | 4362 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4363 | unlock: |
3ef94daa | 4364 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4365 | return ret; |
3ef94daa CW |
4366 | } |
4367 | ||
37e680a1 CW |
4368 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4369 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4370 | { |
35c20a60 | 4371 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4372 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4373 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4374 | INIT_LIST_HEAD(&obj->vma_list); |
493018dc | 4375 | INIT_LIST_HEAD(&obj->batch_pool_list); |
0327d6ba | 4376 | |
37e680a1 CW |
4377 | obj->ops = ops; |
4378 | ||
0327d6ba CW |
4379 | obj->fence_reg = I915_FENCE_REG_NONE; |
4380 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4381 | |
4382 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4383 | } | |
4384 | ||
37e680a1 CW |
4385 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4386 | .get_pages = i915_gem_object_get_pages_gtt, | |
4387 | .put_pages = i915_gem_object_put_pages_gtt, | |
4388 | }; | |
4389 | ||
05394f39 CW |
4390 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4391 | size_t size) | |
ac52bc56 | 4392 | { |
c397b908 | 4393 | struct drm_i915_gem_object *obj; |
5949eac4 | 4394 | struct address_space *mapping; |
1a240d4d | 4395 | gfp_t mask; |
ac52bc56 | 4396 | |
42dcedd4 | 4397 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4398 | if (obj == NULL) |
4399 | return NULL; | |
673a394b | 4400 | |
c397b908 | 4401 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4402 | i915_gem_object_free(obj); |
c397b908 DV |
4403 | return NULL; |
4404 | } | |
673a394b | 4405 | |
bed1ea95 CW |
4406 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4407 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4408 | /* 965gm cannot relocate objects above 4GiB. */ | |
4409 | mask &= ~__GFP_HIGHMEM; | |
4410 | mask |= __GFP_DMA32; | |
4411 | } | |
4412 | ||
496ad9aa | 4413 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4414 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4415 | |
37e680a1 | 4416 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4417 | |
c397b908 DV |
4418 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4419 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4420 | |
3d29b842 ED |
4421 | if (HAS_LLC(dev)) { |
4422 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4423 | * cache) for about a 10% performance improvement |
4424 | * compared to uncached. Graphics requests other than | |
4425 | * display scanout are coherent with the CPU in | |
4426 | * accessing this cache. This means in this mode we | |
4427 | * don't need to clflush on the CPU side, and on the | |
4428 | * GPU side we only need to flush internal caches to | |
4429 | * get data visible to the CPU. | |
4430 | * | |
4431 | * However, we maintain the display planes as UC, and so | |
4432 | * need to rebind when first used as such. | |
4433 | */ | |
4434 | obj->cache_level = I915_CACHE_LLC; | |
4435 | } else | |
4436 | obj->cache_level = I915_CACHE_NONE; | |
4437 | ||
d861e338 DV |
4438 | trace_i915_gem_object_create(obj); |
4439 | ||
05394f39 | 4440 | return obj; |
c397b908 DV |
4441 | } |
4442 | ||
340fbd8c CW |
4443 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4444 | { | |
4445 | /* If we are the last user of the backing storage (be it shmemfs | |
4446 | * pages or stolen etc), we know that the pages are going to be | |
4447 | * immediately released. In this case, we can then skip copying | |
4448 | * back the contents from the GPU. | |
4449 | */ | |
4450 | ||
4451 | if (obj->madv != I915_MADV_WILLNEED) | |
4452 | return false; | |
4453 | ||
4454 | if (obj->base.filp == NULL) | |
4455 | return true; | |
4456 | ||
4457 | /* At first glance, this looks racy, but then again so would be | |
4458 | * userspace racing mmap against close. However, the first external | |
4459 | * reference to the filp can only be obtained through the | |
4460 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4461 | * acquiring such a reference whilst we are in the middle of | |
4462 | * freeing the object. | |
4463 | */ | |
4464 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4465 | } | |
4466 | ||
1488fc08 | 4467 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4468 | { |
1488fc08 | 4469 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4470 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4471 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4472 | struct i915_vma *vma, *next; |
673a394b | 4473 | |
f65c9168 PZ |
4474 | intel_runtime_pm_get(dev_priv); |
4475 | ||
26e12f89 CW |
4476 | trace_i915_gem_object_destroy(obj); |
4477 | ||
07fe0b12 | 4478 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4479 | int ret; |
4480 | ||
4481 | vma->pin_count = 0; | |
4482 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4483 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4484 | bool was_interruptible; | |
1488fc08 | 4485 | |
07fe0b12 BW |
4486 | was_interruptible = dev_priv->mm.interruptible; |
4487 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4488 | |
07fe0b12 | 4489 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4490 | |
07fe0b12 BW |
4491 | dev_priv->mm.interruptible = was_interruptible; |
4492 | } | |
1488fc08 CW |
4493 | } |
4494 | ||
1d64ae71 BW |
4495 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4496 | * before progressing. */ | |
4497 | if (obj->stolen) | |
4498 | i915_gem_object_unpin_pages(obj); | |
4499 | ||
a071fa00 DV |
4500 | WARN_ON(obj->frontbuffer_bits); |
4501 | ||
656bfa3a DV |
4502 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4503 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4504 | obj->tiling_mode != I915_TILING_NONE) | |
4505 | i915_gem_object_unpin_pages(obj); | |
4506 | ||
401c29f6 BW |
4507 | if (WARN_ON(obj->pages_pin_count)) |
4508 | obj->pages_pin_count = 0; | |
340fbd8c | 4509 | if (discard_backing_storage(obj)) |
5537252b | 4510 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4511 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4512 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4513 | |
9da3da66 CW |
4514 | BUG_ON(obj->pages); |
4515 | ||
2f745ad3 CW |
4516 | if (obj->base.import_attach) |
4517 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4518 | |
5cc9ed4b CW |
4519 | if (obj->ops->release) |
4520 | obj->ops->release(obj); | |
4521 | ||
05394f39 CW |
4522 | drm_gem_object_release(&obj->base); |
4523 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4524 | |
05394f39 | 4525 | kfree(obj->bit_17); |
42dcedd4 | 4526 | i915_gem_object_free(obj); |
f65c9168 PZ |
4527 | |
4528 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4529 | } |
4530 | ||
ec7adb6e JL |
4531 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4532 | struct i915_address_space *vm) | |
e656a6cb DV |
4533 | { |
4534 | struct i915_vma *vma; | |
ec7adb6e JL |
4535 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
4536 | if (i915_is_ggtt(vma->vm) && | |
4537 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
4538 | continue; | |
4539 | if (vma->vm == vm) | |
e656a6cb | 4540 | return vma; |
ec7adb6e JL |
4541 | } |
4542 | return NULL; | |
4543 | } | |
4544 | ||
4545 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4546 | const struct i915_ggtt_view *view) | |
4547 | { | |
4548 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); | |
4549 | struct i915_vma *vma; | |
e656a6cb | 4550 | |
ec7adb6e JL |
4551 | if (WARN_ONCE(!view, "no view specified")) |
4552 | return ERR_PTR(-EINVAL); | |
4553 | ||
4554 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
9abc4648 JL |
4555 | if (vma->vm == ggtt && |
4556 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e | 4557 | return vma; |
e656a6cb DV |
4558 | return NULL; |
4559 | } | |
4560 | ||
2f633156 BW |
4561 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4562 | { | |
b9d06dd9 | 4563 | struct i915_address_space *vm = NULL; |
2f633156 | 4564 | WARN_ON(vma->node.allocated); |
aaa05667 CW |
4565 | |
4566 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4567 | if (!list_empty(&vma->exec_list)) | |
4568 | return; | |
4569 | ||
b9d06dd9 | 4570 | vm = vma->vm; |
b9d06dd9 | 4571 | |
841cd773 DV |
4572 | if (!i915_is_ggtt(vm)) |
4573 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 4574 | |
8b9c2b94 | 4575 | list_del(&vma->vma_link); |
b93dab6e | 4576 | |
2f633156 BW |
4577 | kfree(vma); |
4578 | } | |
4579 | ||
e3efda49 CW |
4580 | static void |
4581 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4582 | { | |
4583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4584 | struct intel_engine_cs *ring; |
e3efda49 CW |
4585 | int i; |
4586 | ||
4587 | for_each_ring(ring, dev_priv, i) | |
a83014d3 | 4588 | dev_priv->gt.stop_ring(ring); |
e3efda49 CW |
4589 | } |
4590 | ||
29105ccc | 4591 | int |
45c5f202 | 4592 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4593 | { |
3e31c6c0 | 4594 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4595 | int ret = 0; |
28dfe52a | 4596 | |
45c5f202 | 4597 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4598 | ret = i915_gpu_idle(dev); |
f7403347 | 4599 | if (ret) |
45c5f202 | 4600 | goto err; |
f7403347 | 4601 | |
b2da9fe5 | 4602 | i915_gem_retire_requests(dev); |
673a394b | 4603 | |
e3efda49 | 4604 | i915_gem_stop_ringbuffers(dev); |
45c5f202 CW |
4605 | mutex_unlock(&dev->struct_mutex); |
4606 | ||
737b1506 | 4607 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
29105ccc | 4608 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4609 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4610 | |
bdcf120b CW |
4611 | /* Assert that we sucessfully flushed all the work and |
4612 | * reset the GPU back to its idle, low power state. | |
4613 | */ | |
4614 | WARN_ON(dev_priv->mm.busy); | |
4615 | ||
673a394b | 4616 | return 0; |
45c5f202 CW |
4617 | |
4618 | err: | |
4619 | mutex_unlock(&dev->struct_mutex); | |
4620 | return ret; | |
673a394b EA |
4621 | } |
4622 | ||
a4872ba6 | 4623 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4624 | { |
c3787e2e | 4625 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4626 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4627 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4628 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4629 | int i, ret; |
b9524a1e | 4630 | |
040d2baa | 4631 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4632 | return 0; |
b9524a1e | 4633 | |
c3787e2e BW |
4634 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4635 | if (ret) | |
4636 | return ret; | |
b9524a1e | 4637 | |
c3787e2e BW |
4638 | /* |
4639 | * Note: We do not worry about the concurrent register cacheline hang | |
4640 | * here because no other code should access these registers other than | |
4641 | * at initialization time. | |
4642 | */ | |
b9524a1e | 4643 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4644 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4645 | intel_ring_emit(ring, reg_base + i); | |
4646 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4647 | } |
4648 | ||
c3787e2e | 4649 | intel_ring_advance(ring); |
b9524a1e | 4650 | |
c3787e2e | 4651 | return ret; |
b9524a1e BW |
4652 | } |
4653 | ||
f691e2f4 DV |
4654 | void i915_gem_init_swizzling(struct drm_device *dev) |
4655 | { | |
3e31c6c0 | 4656 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4657 | |
11782b02 | 4658 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4659 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4660 | return; | |
4661 | ||
4662 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4663 | DISP_TILE_SURFACE_SWIZZLING); | |
4664 | ||
11782b02 DV |
4665 | if (IS_GEN5(dev)) |
4666 | return; | |
4667 | ||
f691e2f4 DV |
4668 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4669 | if (IS_GEN6(dev)) | |
6b26c86d | 4670 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4671 | else if (IS_GEN7(dev)) |
6b26c86d | 4672 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4673 | else if (IS_GEN8(dev)) |
4674 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4675 | else |
4676 | BUG(); | |
f691e2f4 | 4677 | } |
e21af88d | 4678 | |
67b1b571 CW |
4679 | static bool |
4680 | intel_enable_blt(struct drm_device *dev) | |
4681 | { | |
4682 | if (!HAS_BLT(dev)) | |
4683 | return false; | |
4684 | ||
4685 | /* The blitter was dysfunctional on early prototypes */ | |
4686 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4687 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4688 | " graphics performance will be degraded.\n"); | |
4689 | return false; | |
4690 | } | |
4691 | ||
4692 | return true; | |
4693 | } | |
4694 | ||
81e7f200 VS |
4695 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4696 | { | |
4697 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4698 | ||
4699 | I915_WRITE(RING_CTL(base), 0); | |
4700 | I915_WRITE(RING_HEAD(base), 0); | |
4701 | I915_WRITE(RING_TAIL(base), 0); | |
4702 | I915_WRITE(RING_START(base), 0); | |
4703 | } | |
4704 | ||
4705 | static void init_unused_rings(struct drm_device *dev) | |
4706 | { | |
4707 | if (IS_I830(dev)) { | |
4708 | init_unused_ring(dev, PRB1_BASE); | |
4709 | init_unused_ring(dev, SRB0_BASE); | |
4710 | init_unused_ring(dev, SRB1_BASE); | |
4711 | init_unused_ring(dev, SRB2_BASE); | |
4712 | init_unused_ring(dev, SRB3_BASE); | |
4713 | } else if (IS_GEN2(dev)) { | |
4714 | init_unused_ring(dev, SRB0_BASE); | |
4715 | init_unused_ring(dev, SRB1_BASE); | |
4716 | } else if (IS_GEN3(dev)) { | |
4717 | init_unused_ring(dev, PRB1_BASE); | |
4718 | init_unused_ring(dev, PRB2_BASE); | |
4719 | } | |
4720 | } | |
4721 | ||
a83014d3 | 4722 | int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4723 | { |
4fc7c971 | 4724 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4725 | int ret; |
68f95ba9 | 4726 | |
5c1143bb | 4727 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4728 | if (ret) |
b6913e4b | 4729 | return ret; |
68f95ba9 CW |
4730 | |
4731 | if (HAS_BSD(dev)) { | |
5c1143bb | 4732 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4733 | if (ret) |
4734 | goto cleanup_render_ring; | |
d1b851fc | 4735 | } |
68f95ba9 | 4736 | |
67b1b571 | 4737 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4738 | ret = intel_init_blt_ring_buffer(dev); |
4739 | if (ret) | |
4740 | goto cleanup_bsd_ring; | |
4741 | } | |
4742 | ||
9a8a2213 BW |
4743 | if (HAS_VEBOX(dev)) { |
4744 | ret = intel_init_vebox_ring_buffer(dev); | |
4745 | if (ret) | |
4746 | goto cleanup_blt_ring; | |
4747 | } | |
4748 | ||
845f74a7 ZY |
4749 | if (HAS_BSD2(dev)) { |
4750 | ret = intel_init_bsd2_ring_buffer(dev); | |
4751 | if (ret) | |
4752 | goto cleanup_vebox_ring; | |
4753 | } | |
9a8a2213 | 4754 | |
99433931 | 4755 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4756 | if (ret) |
845f74a7 | 4757 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4758 | |
4759 | return 0; | |
4760 | ||
845f74a7 ZY |
4761 | cleanup_bsd2_ring: |
4762 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4763 | cleanup_vebox_ring: |
4764 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4765 | cleanup_blt_ring: |
4766 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4767 | cleanup_bsd_ring: | |
4768 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4769 | cleanup_render_ring: | |
4770 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4771 | ||
4772 | return ret; | |
4773 | } | |
4774 | ||
4775 | int | |
4776 | i915_gem_init_hw(struct drm_device *dev) | |
4777 | { | |
3e31c6c0 | 4778 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a57ffb | 4779 | struct intel_engine_cs *ring; |
35a85ac6 | 4780 | int ret, i; |
4fc7c971 BW |
4781 | |
4782 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4783 | return -EIO; | |
4784 | ||
5e4f5189 CW |
4785 | /* Double layer security blanket, see i915_gem_init() */ |
4786 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4787 | ||
59124506 | 4788 | if (dev_priv->ellc_size) |
05e21cc4 | 4789 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4790 | |
0bf21347 VS |
4791 | if (IS_HASWELL(dev)) |
4792 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4793 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4794 | |
88a2b2a3 | 4795 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4796 | if (IS_IVYBRIDGE(dev)) { |
4797 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4798 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4799 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4800 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4801 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4802 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4803 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4804 | } | |
88a2b2a3 BW |
4805 | } |
4806 | ||
4fc7c971 BW |
4807 | i915_gem_init_swizzling(dev); |
4808 | ||
d5abdfda DV |
4809 | /* |
4810 | * At least 830 can leave some of the unused rings | |
4811 | * "active" (ie. head != tail) after resume which | |
4812 | * will prevent c3 entry. Makes sure all unused rings | |
4813 | * are totally idle. | |
4814 | */ | |
4815 | init_unused_rings(dev); | |
4816 | ||
35a57ffb DV |
4817 | for_each_ring(ring, dev_priv, i) { |
4818 | ret = ring->init_hw(ring); | |
4819 | if (ret) | |
5e4f5189 | 4820 | goto out; |
35a57ffb | 4821 | } |
99433931 | 4822 | |
c3787e2e BW |
4823 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4824 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4825 | ||
f48a0165 | 4826 | ret = i915_ppgtt_init_hw(dev); |
60990320 | 4827 | if (ret && ret != -EIO) { |
f48a0165 | 4828 | DRM_ERROR("PPGTT enable failed %d\n", ret); |
60990320 | 4829 | i915_gem_cleanup_ringbuffer(dev); |
82460d97 DV |
4830 | } |
4831 | ||
f48a0165 | 4832 | ret = i915_gem_context_enable(dev_priv); |
82460d97 | 4833 | if (ret && ret != -EIO) { |
f48a0165 | 4834 | DRM_ERROR("Context enable failed %d\n", ret); |
82460d97 | 4835 | i915_gem_cleanup_ringbuffer(dev); |
f48a0165 | 4836 | |
5e4f5189 | 4837 | goto out; |
b7c36d25 | 4838 | } |
e21af88d | 4839 | |
5e4f5189 CW |
4840 | out: |
4841 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4842 | return ret; |
8187a2b7 ZN |
4843 | } |
4844 | ||
1070a42b CW |
4845 | int i915_gem_init(struct drm_device *dev) |
4846 | { | |
4847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4848 | int ret; |
4849 | ||
127f1003 OM |
4850 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4851 | i915.enable_execlists); | |
4852 | ||
1070a42b | 4853 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4854 | |
4855 | if (IS_VALLEYVIEW(dev)) { | |
4856 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4857 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4858 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4859 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4860 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4861 | } | |
4862 | ||
a83014d3 OM |
4863 | if (!i915.enable_execlists) { |
4864 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; | |
4865 | dev_priv->gt.init_rings = i915_gem_init_rings; | |
4866 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
4867 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
454afebd OM |
4868 | } else { |
4869 | dev_priv->gt.do_execbuf = intel_execlists_submission; | |
4870 | dev_priv->gt.init_rings = intel_logical_rings_init; | |
4871 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
4872 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
a83014d3 OM |
4873 | } |
4874 | ||
5e4f5189 CW |
4875 | /* This is just a security blanket to placate dragons. |
4876 | * On some systems, we very sporadically observe that the first TLBs | |
4877 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4878 | * we hold the forcewake during initialisation these problems | |
4879 | * just magically go away. | |
4880 | */ | |
4881 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4882 | ||
6c5566a8 | 4883 | ret = i915_gem_init_userptr(dev); |
7bcc3777 JN |
4884 | if (ret) |
4885 | goto out_unlock; | |
6c5566a8 | 4886 | |
d7e5008f | 4887 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4888 | |
2fa48d8d | 4889 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4890 | if (ret) |
4891 | goto out_unlock; | |
2fa48d8d | 4892 | |
35a57ffb DV |
4893 | ret = dev_priv->gt.init_rings(dev); |
4894 | if (ret) | |
7bcc3777 | 4895 | goto out_unlock; |
2fa48d8d | 4896 | |
1070a42b | 4897 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4898 | if (ret == -EIO) { |
4899 | /* Allow ring initialisation to fail by marking the GPU as | |
4900 | * wedged. But we only want to do this where the GPU is angry, | |
4901 | * for all other failure, such as an allocation failure, bail. | |
4902 | */ | |
4903 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4904 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4905 | ret = 0; | |
1070a42b | 4906 | } |
7bcc3777 JN |
4907 | |
4908 | out_unlock: | |
5e4f5189 | 4909 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4910 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4911 | |
60990320 | 4912 | return ret; |
1070a42b CW |
4913 | } |
4914 | ||
8187a2b7 ZN |
4915 | void |
4916 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4917 | { | |
3e31c6c0 | 4918 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4919 | struct intel_engine_cs *ring; |
1ec14ad3 | 4920 | int i; |
8187a2b7 | 4921 | |
b4519513 | 4922 | for_each_ring(ring, dev_priv, i) |
a83014d3 | 4923 | dev_priv->gt.cleanup_ring(ring); |
8187a2b7 ZN |
4924 | } |
4925 | ||
64193406 | 4926 | static void |
a4872ba6 | 4927 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4928 | { |
4929 | INIT_LIST_HEAD(&ring->active_list); | |
4930 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4931 | } |
4932 | ||
7e0d96bc BW |
4933 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4934 | struct i915_address_space *vm) | |
fc8c067e | 4935 | { |
7e0d96bc BW |
4936 | if (!i915_is_ggtt(vm)) |
4937 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4938 | vm->dev = dev_priv->dev; |
4939 | INIT_LIST_HEAD(&vm->active_list); | |
4940 | INIT_LIST_HEAD(&vm->inactive_list); | |
4941 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4942 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4943 | } |
4944 | ||
673a394b EA |
4945 | void |
4946 | i915_gem_load(struct drm_device *dev) | |
4947 | { | |
3e31c6c0 | 4948 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4949 | int i; |
4950 | ||
4951 | dev_priv->slab = | |
4952 | kmem_cache_create("i915_gem_object", | |
4953 | sizeof(struct drm_i915_gem_object), 0, | |
4954 | SLAB_HWCACHE_ALIGN, | |
4955 | NULL); | |
673a394b | 4956 | |
fc8c067e BW |
4957 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4958 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4959 | ||
a33afea5 | 4960 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4961 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4962 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4963 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4964 | for (i = 0; i < I915_NUM_RINGS; i++) |
4965 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4966 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4967 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4968 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4969 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4970 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4971 | i915_gem_idle_work_handler); | |
1f83fee0 | 4972 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4973 | |
72bfa19c CW |
4974 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4975 | ||
42b5aeab VS |
4976 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4977 | dev_priv->num_fence_regs = 32; | |
4978 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4979 | dev_priv->num_fence_regs = 16; |
4980 | else | |
4981 | dev_priv->num_fence_regs = 8; | |
4982 | ||
eb82289a YZ |
4983 | if (intel_vgpu_active(dev)) |
4984 | dev_priv->num_fence_regs = | |
4985 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4986 | ||
b5aa8a0f | 4987 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4988 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4989 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4990 | |
673a394b | 4991 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4992 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4993 | |
ce453d81 CW |
4994 | dev_priv->mm.interruptible = true; |
4995 | ||
be6a0376 | 4996 | i915_gem_shrinker_init(dev_priv); |
f99d7069 | 4997 | |
78a42377 BV |
4998 | i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool); |
4999 | ||
f99d7069 | 5000 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 5001 | } |
71acb5eb | 5002 | |
f787a5f5 | 5003 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5004 | { |
f787a5f5 | 5005 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 5006 | |
b29c19b6 CW |
5007 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
5008 | ||
b962442e EA |
5009 | /* Clean up our request list when the client is going away, so that |
5010 | * later retire_requests won't dereference our soon-to-be-gone | |
5011 | * file_priv. | |
5012 | */ | |
1c25595f | 5013 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5014 | while (!list_empty(&file_priv->mm.request_list)) { |
5015 | struct drm_i915_gem_request *request; | |
5016 | ||
5017 | request = list_first_entry(&file_priv->mm.request_list, | |
5018 | struct drm_i915_gem_request, | |
5019 | client_list); | |
5020 | list_del(&request->client_list); | |
5021 | request->file_priv = NULL; | |
5022 | } | |
1c25595f | 5023 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5024 | } |
31169714 | 5025 | |
b29c19b6 CW |
5026 | static void |
5027 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
5028 | { | |
5029 | struct drm_i915_file_private *file_priv = | |
5030 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
5031 | ||
5032 | atomic_set(&file_priv->rps_wait_boost, false); | |
5033 | } | |
5034 | ||
5035 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5036 | { | |
5037 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5038 | int ret; |
b29c19b6 CW |
5039 | |
5040 | DRM_DEBUG_DRIVER("\n"); | |
5041 | ||
5042 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5043 | if (!file_priv) | |
5044 | return -ENOMEM; | |
5045 | ||
5046 | file->driver_priv = file_priv; | |
5047 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5048 | file_priv->file = file; |
b29c19b6 CW |
5049 | |
5050 | spin_lock_init(&file_priv->mm.lock); | |
5051 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
5052 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
5053 | i915_gem_file_idle_work_handler); | |
5054 | ||
e422b888 BW |
5055 | ret = i915_gem_context_open(dev, file); |
5056 | if (ret) | |
5057 | kfree(file_priv); | |
b29c19b6 | 5058 | |
e422b888 | 5059 | return ret; |
b29c19b6 CW |
5060 | } |
5061 | ||
b680c37a DV |
5062 | /** |
5063 | * i915_gem_track_fb - update frontbuffer tracking | |
5064 | * old: current GEM buffer for the frontbuffer slots | |
5065 | * new: new GEM buffer for the frontbuffer slots | |
5066 | * frontbuffer_bits: bitmask of frontbuffer slots | |
5067 | * | |
5068 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5069 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5070 | */ | |
a071fa00 DV |
5071 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5072 | struct drm_i915_gem_object *new, | |
5073 | unsigned frontbuffer_bits) | |
5074 | { | |
5075 | if (old) { | |
5076 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5077 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5078 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5079 | } | |
5080 | ||
5081 | if (new) { | |
5082 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5083 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5084 | new->frontbuffer_bits |= frontbuffer_bits; | |
5085 | } | |
5086 | } | |
5087 | ||
a70a3148 | 5088 | /* All the new VM stuff */ |
ec7adb6e JL |
5089 | unsigned long |
5090 | i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5091 | struct i915_address_space *vm) | |
a70a3148 BW |
5092 | { |
5093 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5094 | struct i915_vma *vma; | |
5095 | ||
896ab1a5 | 5096 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5097 | |
a70a3148 | 5098 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
ec7adb6e JL |
5099 | if (i915_is_ggtt(vma->vm) && |
5100 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5101 | continue; | |
5102 | if (vma->vm == vm) | |
a70a3148 | 5103 | return vma->node.start; |
a70a3148 | 5104 | } |
ec7adb6e | 5105 | |
f25748ea DV |
5106 | WARN(1, "%s vma for this object not found.\n", |
5107 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5108 | return -1; |
5109 | } | |
5110 | ||
ec7adb6e JL |
5111 | unsigned long |
5112 | i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5113 | const struct i915_ggtt_view *view) |
a70a3148 | 5114 | { |
ec7adb6e | 5115 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); |
a70a3148 BW |
5116 | struct i915_vma *vma; |
5117 | ||
5118 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
9abc4648 JL |
5119 | if (vma->vm == ggtt && |
5120 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e JL |
5121 | return vma->node.start; |
5122 | ||
5123 | WARN(1, "global vma for this object not found.\n"); | |
5124 | return -1; | |
5125 | } | |
5126 | ||
5127 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5128 | struct i915_address_space *vm) | |
5129 | { | |
5130 | struct i915_vma *vma; | |
5131 | ||
5132 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
5133 | if (i915_is_ggtt(vma->vm) && | |
5134 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5135 | continue; | |
5136 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
5137 | return true; | |
5138 | } | |
5139 | ||
5140 | return false; | |
5141 | } | |
5142 | ||
5143 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5144 | const struct i915_ggtt_view *view) |
ec7adb6e JL |
5145 | { |
5146 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); | |
5147 | struct i915_vma *vma; | |
5148 | ||
5149 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5150 | if (vma->vm == ggtt && | |
9abc4648 | 5151 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 5152 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5153 | return true; |
5154 | ||
5155 | return false; | |
5156 | } | |
5157 | ||
5158 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5159 | { | |
5a1d5eb0 | 5160 | struct i915_vma *vma; |
a70a3148 | 5161 | |
5a1d5eb0 CW |
5162 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5163 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5164 | return true; |
5165 | ||
5166 | return false; | |
5167 | } | |
5168 | ||
5169 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5170 | struct i915_address_space *vm) | |
5171 | { | |
5172 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5173 | struct i915_vma *vma; | |
5174 | ||
896ab1a5 | 5175 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5176 | |
5177 | BUG_ON(list_empty(&o->vma_list)); | |
5178 | ||
ec7adb6e JL |
5179 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
5180 | if (i915_is_ggtt(vma->vm) && | |
5181 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5182 | continue; | |
a70a3148 BW |
5183 | if (vma->vm == vm) |
5184 | return vma->node.size; | |
ec7adb6e | 5185 | } |
a70a3148 BW |
5186 | return 0; |
5187 | } | |
5188 | ||
ec7adb6e | 5189 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
5190 | { |
5191 | struct i915_vma *vma; | |
ec7adb6e JL |
5192 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
5193 | if (i915_is_ggtt(vma->vm) && | |
5194 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5195 | continue; | |
5196 | if (vma->pin_count > 0) | |
5197 | return true; | |
5198 | } | |
5199 | return false; | |
5c2abbea | 5200 | } |
ec7adb6e | 5201 |