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drm/i915: Whitespace correction for madv
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
673a394b 34#include <linux/swap.h>
79e53945 35#include <linux/pci.h>
673a394b 36
28dfe52a
EA		 37#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38
e47c68e9
EA		 39static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 42static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 int write);
44static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
47static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 48static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 49static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 unsigned alignment);
de151cf6 51static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 52static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 53static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 54static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
673a394b 57
31169714
CW		 58static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
79e53945
JB		 61int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
673a394b
EA		 63{
64 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 65
79e53945
JB		 66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 69 return -EINVAL;
70 }
71
79e53945
JB		 72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
673a394b 74
79e53945
JB		 75 dev->gtt_total = (uint32_t) (end - start);
76
77 return 0;
78}
673a394b 79
79e53945
JB		 80int
81i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
83{
84 struct drm_i915_gem_init *args = data;
85 int ret;
86
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 89 mutex_unlock(&dev->struct_mutex);
90
79e53945 91 return ret;
673a394b
EA		 92}
93
5a125c3c
EA		 94int
95i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
97{
5a125c3c 98 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 99
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
102
103 args->aper_size = dev->gtt_total;
2678d9d6
KP		 104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
5a125c3c
EA		 106
107 return 0;
108}
109
673a394b
EA		 110
111/**
112 * Creates a new mm object and returns a handle to it.
113 */
114int
115i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
117{
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
a1a2d1d3
PP		 120 int ret;
121 u32 handle;
673a394b
EA		 122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
134
135 if (ret)
136 return ret;
137
138 args->handle = handle;
139
140 return 0;
141}
142
eb01459f
EA		 143static inline int
144fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
146 char __user *data,
147 int length)
148{
149 char __iomem *vaddr;
2bc43b5c 150 int unwritten;
eb01459f
EA		 151
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 if (vaddr == NULL)
154 return -ENOMEM;
2bc43b5c 155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 156 kunmap_atomic(vaddr, KM_USER0);
157
2bc43b5c
FM		 158 if (unwritten)
159 return -EFAULT;
160
161 return 0;
eb01459f
EA		 162}
163
280b713b
EA		 164static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165{
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
171}
172
40123c1f
EA		 173static inline int
174slow_shmem_copy(struct page *dst_page,
175 int dst_offset,
176 struct page *src_page,
177 int src_offset,
178 int length)
179{
180 char *dst_vaddr, *src_vaddr;
181
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
184 return -ENOMEM;
185
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
189 return -ENOMEM;
190 }
191
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
196
197 return 0;
198}
199
280b713b
EA		 200static inline int
201slow_shmem_bit17_copy(struct page *gpu_page,
202 int gpu_offset,
203 struct page *cpu_page,
204 int cpu_offset,
205 int length,
206 int is_read)
207{
208 char *gpu_vaddr, *cpu_vaddr;
209
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 if (is_read)
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
215 else
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
218 }
219
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
222 return -ENOMEM;
223
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
227 return -ENOMEM;
228 }
229
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 */
233 while (length > 0) {
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238 if (is_read) {
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
241 this_length);
242 } else {
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
245 this_length);
246 }
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
250 }
251
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
254
255 return 0;
256}
257
eb01459f
EA		 258/**
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 */
263static int
264i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
267{
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
269 ssize_t remain;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
273 int ret;
274
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 remain = args->size;
277
278 mutex_lock(&dev->struct_mutex);
279
280 ret = i915_gem_object_get_pages(obj);
281 if (ret != 0)
282 goto fail_unlock;
283
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285 args->size);
286 if (ret != 0)
287 goto fail_put_pages;
288
289 obj_priv = obj->driver_private;
290 offset = args->offset;
291
292 while (remain > 0) {
293 /* Operation in this page
294 *
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
298 */
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
304
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
308 if (ret)
309 goto fail_put_pages;
310
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
314 }
315
316fail_put_pages:
317 i915_gem_object_put_pages(obj);
318fail_unlock:
319 mutex_unlock(&dev->struct_mutex);
320
321 return ret;
322}
323
07f73f69
CW		 324static inline gfp_t
325i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
326{
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
328}
329
330static inline void
331i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
332{
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
334}
335
336static int
337i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
338{
339 int ret;
340
341 ret = i915_gem_object_get_pages(obj);
342
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
345 */
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
348 gfp_t gfp;
349
350 ret = i915_gem_evict_something(dev, obj->size);
351 if (ret)
352 return ret;
353
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
358 }
359
360 return ret;
361}
362
eb01459f
EA		 363/**
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
368 */
369static int
370i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
373{
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
377 ssize_t remain;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
382 int page_length;
383 int ret;
384 uint64_t data_ptr = args->data_ptr;
280b713b 385 int do_bit17_swizzling;
eb01459f
EA		 386
387 remain = args->size;
388
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
392 */
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
396
8e7d2b2c 397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 398 if (user_pages == NULL)
399 return -ENOMEM;
400
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 403 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
406 ret = -EFAULT;
407 goto fail_put_user_pages;
408 }
409
280b713b
EA		 410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
411
eb01459f
EA		 412 mutex_lock(&dev->struct_mutex);
413
07f73f69
CW		 414 ret = i915_gem_object_get_pages_or_evict(obj);
415 if (ret)
eb01459f
EA		 416 goto fail_unlock;
417
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
419 args->size);
420 if (ret != 0)
421 goto fail_put_pages;
422
423 obj_priv = obj->driver_private;
424 offset = args->offset;
425
426 while (remain > 0) {
427 /* Operation in this page
428 *
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
434 */
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
439
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
445
280b713b
EA		 446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
448 shmem_page_offset,
449 user_pages[data_page_index],
450 data_page_offset,
451 page_length,
452 1);
453 } else {
454 ret = slow_shmem_copy(user_pages[data_page_index],
455 data_page_offset,
456 obj_priv->pages[shmem_page_index],
457 shmem_page_offset,
458 page_length);
459 }
eb01459f
EA		 460 if (ret)
461 goto fail_put_pages;
462
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
466 }
467
468fail_put_pages:
469 i915_gem_object_put_pages(obj);
470fail_unlock:
471 mutex_unlock(&dev->struct_mutex);
472fail_put_user_pages:
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
476 }
8e7d2b2c 477 drm_free_large(user_pages);
eb01459f
EA		 478
479 return ret;
480}
481
673a394b
EA		 482/**
483 * Reads data from the object referenced by handle.
484 *
485 * On error, the contents of *data are undefined.
486 */
487int
488i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
490{
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 494 int ret;
495
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
497 if (obj == NULL)
498 return -EBADF;
499 obj_priv = obj->driver_private;
500
501 /* Bounds check source.
502 *
503 * XXX: This could use review for overflow issues...
504 */
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
508 return -EINVAL;
509 }
510
280b713b 511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 513 } else {
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
515 if (ret != 0)
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
517 file_priv);
518 }
673a394b
EA		 519
520 drm_gem_object_unreference(obj);
673a394b 521
eb01459f 522 return ret;
673a394b
EA		 523}
524
0839ccb8
KP		 525/* This is the fast write path which cannot handle
526 * page faults in the source data
9b7530cc 527 */
0839ccb8
KP		 528
529static inline int
530fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
533 int length)
9b7530cc 534{
9b7530cc 535 char *vaddr_atomic;
0839ccb8 536 unsigned long unwritten;
9b7530cc 537
0839ccb8
KP		 538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
540 user_data, length);
541 io_mapping_unmap_atomic(vaddr_atomic);
542 if (unwritten)
543 return -EFAULT;
544 return 0;
545}
546
547/* Here's the write path which can sleep for
548 * page faults
549 */
550
551static inline int
3de09aa3
EA		 552slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
555 int length)
0839ccb8 556{
3de09aa3 557 char *src_vaddr, *dst_vaddr;
0839ccb8
KP		 558 unsigned long unwritten;
559
3de09aa3
EA		 560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
564 length);
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
0839ccb8
KP		 567 if (unwritten)
568 return -EFAULT;
9b7530cc 569 return 0;
9b7530cc
LT		 570}
571
40123c1f
EA		 572static inline int
573fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
575 char __user *data,
576 int length)
577{
578 char __iomem *vaddr;
d0088775 579 unsigned long unwritten;
40123c1f
EA		 580
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
582 if (vaddr == NULL)
583 return -ENOMEM;
d0088775 584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 585 kunmap_atomic(vaddr, KM_USER0);
586
d0088775
DA		 587 if (unwritten)
588 return -EFAULT;
40123c1f
EA		 589 return 0;
590}
591
3de09aa3
EA		 592/**
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
595 */
673a394b 596static int
3de09aa3
EA		 597i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
673a394b
EA		 600{
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
0839ccb8 602 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 603 ssize_t remain;
0839ccb8 604 loff_t offset, page_base;
673a394b 605 char __user *user_data;
0839ccb8
KP		 606 int page_offset, page_length;
607 int ret;
673a394b
EA		 608
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
610 remain = args->size;
611 if (!access_ok(VERIFY_READ, user_data, remain))
612 return -EFAULT;
613
614
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
617 if (ret) {
618 mutex_unlock(&dev->struct_mutex);
619 return ret;
620 }
2ef7eeaa 621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 622 if (ret)
623 goto fail;
624
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 627
628 while (remain > 0) {
629 /* Operation in this page
630 *
0839ccb8
KP		 631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
673a394b 634 */
0839ccb8
KP		 635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
640
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
643
644 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
0839ccb8 647 */
3de09aa3
EA		 648 if (ret)
649 goto fail;
673a394b 650
0839ccb8
KP		 651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
673a394b 654 }
673a394b
EA		 655
656fail:
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
659
660 return ret;
661}
662
3de09aa3
EA		 663/**
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
666 *
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
669 */
3043c60c 670static int
3de09aa3
EA		 671i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
673a394b 674{
3de09aa3
EA		 675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
677 ssize_t remain;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 684 int ret;
3de09aa3
EA		 685 uint64_t data_ptr = args->data_ptr;
686
687 remain = args->size;
688
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
692 */
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
696
8e7d2b2c 697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 698 if (user_pages == NULL)
699 return -ENOMEM;
700
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
706 ret = -EFAULT;
707 goto out_unpin_pages;
708 }
673a394b
EA		 709
710 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 711 ret = i915_gem_object_pin(obj, 0);
712 if (ret)
713 goto out_unlock;
714
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
716 if (ret)
717 goto out_unpin_object;
718
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
721
722 while (remain > 0) {
723 /* Operation in this page
724 *
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
730 */
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
735
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
741
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
745 data_page_offset,
746 page_length);
747
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
751 */
752 if (ret)
753 goto out_unpin_object;
754
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
758 }
759
760out_unpin_object:
761 i915_gem_object_unpin(obj);
762out_unlock:
763 mutex_unlock(&dev->struct_mutex);
764out_unpin_pages:
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
8e7d2b2c 767 drm_free_large(user_pages);
3de09aa3
EA		 768
769 return ret;
770}
771
40123c1f
EA		 772/**
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
775 */
3043c60c 776static int
40123c1f
EA		 777i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
673a394b 780{
40123c1f
EA		 781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
782 ssize_t remain;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
673a394b 786 int ret;
40123c1f
EA		 787
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
789 remain = args->size;
673a394b
EA		 790
791 mutex_lock(&dev->struct_mutex);
792
40123c1f
EA		 793 ret = i915_gem_object_get_pages(obj);
794 if (ret != 0)
795 goto fail_unlock;
673a394b 796
e47c68e9 797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 798 if (ret != 0)
799 goto fail_put_pages;
800
801 obj_priv = obj->driver_private;
802 offset = args->offset;
803 obj_priv->dirty = 1;
804
805 while (remain > 0) {
806 /* Operation in this page
807 *
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
811 */
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
817
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
821 if (ret)
822 goto fail_put_pages;
823
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
827 }
828
829fail_put_pages:
830 i915_gem_object_put_pages(obj);
831fail_unlock:
832 mutex_unlock(&dev->struct_mutex);
833
834 return ret;
835}
836
837/**
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
840 *
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
843 */
844static int
845i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
848{
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
852 ssize_t remain;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
857 int page_length;
858 int ret;
859 uint64_t data_ptr = args->data_ptr;
280b713b 860 int do_bit17_swizzling;
40123c1f
EA		 861
862 remain = args->size;
863
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
867 */
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
871
8e7d2b2c 872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 873 if (user_pages == NULL)
874 return -ENOMEM;
875
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
881 ret = -EFAULT;
882 goto fail_put_user_pages;
673a394b
EA		 883 }
884
280b713b
EA		 885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
886
40123c1f
EA		 887 mutex_lock(&dev->struct_mutex);
888
07f73f69
CW		 889 ret = i915_gem_object_get_pages_or_evict(obj);
890 if (ret)
40123c1f
EA		 891 goto fail_unlock;
892
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
894 if (ret != 0)
895 goto fail_put_pages;
896
897 obj_priv = obj->driver_private;
673a394b 898 offset = args->offset;
40123c1f 899 obj_priv->dirty = 1;
673a394b 900
40123c1f
EA		 901 while (remain > 0) {
902 /* Operation in this page
903 *
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
909 */
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
914
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
920
280b713b
EA		 921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
923 shmem_page_offset,
924 user_pages[data_page_index],
925 data_page_offset,
926 page_length,
927 0);
928 } else {
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
930 shmem_page_offset,
931 user_pages[data_page_index],
932 data_page_offset,
933 page_length);
934 }
40123c1f
EA		 935 if (ret)
936 goto fail_put_pages;
937
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
673a394b
EA		 941 }
942
40123c1f
EA		 943fail_put_pages:
944 i915_gem_object_put_pages(obj);
945fail_unlock:
673a394b 946 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 947fail_put_user_pages:
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
8e7d2b2c 950 drm_free_large(user_pages);
673a394b 951
40123c1f 952 return ret;
673a394b
EA		 953}
954
955/**
956 * Writes data to the object referenced by handle.
957 *
958 * On error, the contents of the buffer that were to be modified are undefined.
959 */
960int
961i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
963{
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
967 int ret = 0;
968
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
970 if (obj == NULL)
971 return -EBADF;
972 obj_priv = obj->driver_private;
973
974 /* Bounds check destination.
975 *
976 * XXX: This could use review for overflow issues...
977 */
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
981 return -EINVAL;
982 }
983
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
989 */
71acb5eb
DA		 990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
3de09aa3
EA		 993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
997 file_priv);
998 }
280b713b
EA		 999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 1001 } else {
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1005 file_priv);
1006 }
1007 }
673a394b
EA		 1008
1009#if WATCH_PWRITE
1010 if (ret)
1011 DRM_INFO("pwrite failed %d\n", ret);
1012#endif
1013
1014 drm_gem_object_unreference(obj);
1015
1016 return ret;
1017}
1018
1019/**
2ef7eeaa
EA		 1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1022 */
1023int
1024i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1026{
a09ba7fa 1027 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
652c393a 1030 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
673a394b
EA		 1033 int ret;
1034
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1036 return -ENODEV;
1037
2ef7eeaa 1038 /* Only handle setting domains to types used by the CPU. */
21d509e3 1039 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1040 return -EINVAL;
1041
21d509e3 1042 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1043 return -EINVAL;
1044
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1047 */
1048 if (write_domain != 0 && read_domains != write_domain)
1049 return -EINVAL;
1050
673a394b
EA		 1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1052 if (obj == NULL)
1053 return -EBADF;
652c393a 1054 obj_priv = obj->driver_private;
673a394b
EA		 1055
1056 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1057
1058 intel_mark_busy(dev, obj);
1059
673a394b 1060#if WATCH_BUF
cfd43c02 1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1062 obj, obj->size, read_domains, write_domain);
673a394b 1063#endif
2ef7eeaa
EA		 1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1066
a09ba7fa
EA		 1067 /* Update the LRU on the fence for the CPU access that's
1068 * about to occur.
1069 */
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1073 }
1074
02354392
EA		 1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1078 */
1079 if (ret == -EINVAL)
1080 ret = 0;
2ef7eeaa 1081 } else {
e47c68e9 1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1083 }
1084
673a394b
EA		 1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1087 return ret;
1088}
1089
1090/**
1091 * Called when user space has done writes to this buffer
1092 */
1093int
1094i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1096{
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1100 int ret = 0;
1101
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1103 return -ENODEV;
1104
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1107 if (obj == NULL) {
1108 mutex_unlock(&dev->struct_mutex);
1109 return -EBADF;
1110 }
1111
1112#if WATCH_BUF
cfd43c02 1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1114 __func__, args->handle, obj, obj->size);
1115#endif
1116 obj_priv = obj->driver_private;
1117
1118 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1121
673a394b
EA		 1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1124 return ret;
1125}
1126
1127/**
1128 * Maps the contents of an object, returning the address it is mapped
1129 * into.
1130 *
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1133 */
1134int
1135i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1137{
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1140 loff_t offset;
1141 unsigned long addr;
1142
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1144 return -ENODEV;
1145
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1147 if (obj == NULL)
1148 return -EBADF;
1149
1150 offset = args->offset;
1151
1152 down_write(&current->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1155 args->offset);
1156 up_write(&current->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1161 return addr;
1162
1163 args->addr_ptr = (uint64_t) addr;
1164
1165 return 0;
1166}
1167
de151cf6
JB		 1168/**
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1171 * vmf: fault info
1172 *
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1178 *
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1182 * left.
1183 */
1184int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1185{
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1191 unsigned long pfn;
1192 int ret = 0;
0f973f27 1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1194
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1197 PAGE_SHIFT;
1198
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
e67b8ce1 1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1203 if (ret) {
1204 mutex_unlock(&dev->struct_mutex);
1205 return VM_FAULT_SIGBUS;
1206 }
4960aaca 1207 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1208
1209 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1210 if (ret) {
1211 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_SIGBUS;
1213 }
de151cf6
JB		 1214 }
1215
1216 /* Need a new fence register? */
a09ba7fa 1217 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1218 ret = i915_gem_object_get_fence_reg(obj);
7d8d58b2
CW		 1219 if (ret) {
1220 mutex_unlock(&dev->struct_mutex);
d9ddcb96 1221 return VM_FAULT_SIGBUS;
7d8d58b2 1222 }
d9ddcb96 1223 }
de151cf6
JB		 1224
1225 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1226 page_offset;
1227
1228 /* Finally, remap it using the new GTT offset */
1229 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1230
1231 mutex_unlock(&dev->struct_mutex);
1232
1233 switch (ret) {
1234 case -ENOMEM:
1235 case -EAGAIN:
1236 return VM_FAULT_OOM;
1237 case -EFAULT:
959b887c 1238 case -EINVAL:
de151cf6
JB		 1239 return VM_FAULT_SIGBUS;
1240 default:
1241 return VM_FAULT_NOPAGE;
1242 }
1243}
1244
1245/**
1246 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1247 * @obj: obj in question
1248 *
1249 * GEM memory mapping works by handing back to userspace a fake mmap offset
1250 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1251 * up the object based on the offset and sets up the various memory mapping
1252 * structures.
1253 *
1254 * This routine allocates and attaches a fake offset for @obj.
1255 */
1256static int
1257i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1258{
1259 struct drm_device *dev = obj->dev;
1260 struct drm_gem_mm *mm = dev->mm_private;
1261 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1262 struct drm_map_list *list;
f77d390c 1263 struct drm_local_map *map;
de151cf6
JB		 1264 int ret = 0;
1265
1266 /* Set the object up for mmap'ing */
1267 list = &obj->map_list;
9a298b2a 1268 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1269 if (!list->map)
1270 return -ENOMEM;
1271
1272 map = list->map;
1273 map->type = _DRM_GEM;
1274 map->size = obj->size;
1275 map->handle = obj;
1276
1277 /* Get a DRM GEM mmap offset allocated... */
1278 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1279 obj->size / PAGE_SIZE, 0, 0);
1280 if (!list->file_offset_node) {
1281 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1282 ret = -ENOMEM;
1283 goto out_free_list;
1284 }
1285
1286 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1287 obj->size / PAGE_SIZE, 0);
1288 if (!list->file_offset_node) {
1289 ret = -ENOMEM;
1290 goto out_free_list;
1291 }
1292
1293 list->hash.key = list->file_offset_node->start;
1294 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1295 DRM_ERROR("failed to add to map hash\n");
1296 goto out_free_mm;
1297 }
1298
1299 /* By now we should be all set, any drm_mmap request on the offset
1300 * below will get to our mmap & fault handler */
1301 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1302
1303 return 0;
1304
1305out_free_mm:
1306 drm_mm_put_block(list->file_offset_node);
1307out_free_list:
9a298b2a 1308 kfree(list->map);
de151cf6
JB		 1309
1310 return ret;
1311}
1312
901782b2
CW		 1313/**
1314 * i915_gem_release_mmap - remove physical page mappings
1315 * @obj: obj in question
1316 *
1317 * Preserve the reservation of the mmaping with the DRM core code, but
1318 * relinquish ownership of the pages back to the system.
1319 *
1320 * It is vital that we remove the page mapping if we have mapped a tiled
1321 * object through the GTT and then lose the fence register due to
1322 * resource pressure. Similarly if the object has been moved out of the
1323 * aperture, than pages mapped into userspace must be revoked. Removing the
1324 * mapping will then trigger a page fault on the next user access, allowing
1325 * fixup by i915_gem_fault().
1326 */
d05ca301 1327void
901782b2
CW		 1328i915_gem_release_mmap(struct drm_gem_object *obj)
1329{
1330 struct drm_device *dev = obj->dev;
1331 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1332
1333 if (dev->dev_mapping)
1334 unmap_mapping_range(dev->dev_mapping,
1335 obj_priv->mmap_offset, obj->size, 1);
1336}
1337
ab00b3e5
JB		 1338static void
1339i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1340{
1341 struct drm_device *dev = obj->dev;
1342 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1343 struct drm_gem_mm *mm = dev->mm_private;
1344 struct drm_map_list *list;
1345
1346 list = &obj->map_list;
1347 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1348
1349 if (list->file_offset_node) {
1350 drm_mm_put_block(list->file_offset_node);
1351 list->file_offset_node = NULL;
1352 }
1353
1354 if (list->map) {
9a298b2a 1355 kfree(list->map);
ab00b3e5
JB		 1356 list->map = NULL;
1357 }
1358
1359 obj_priv->mmap_offset = 0;
1360}
1361
de151cf6
JB		 1362/**
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1365 *
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping if needed.
1368 */
1369static uint32_t
1370i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1371{
1372 struct drm_device *dev = obj->dev;
1373 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1374 int start, i;
1375
1376 /*
1377 * Minimum alignment is 4k (GTT page size), but might be greater
1378 * if a fence register is needed for the object.
1379 */
1380 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1381 return 4096;
1382
1383 /*
1384 * Previous chips need to be aligned to the size of the smallest
1385 * fence register that can contain the object.
1386 */
1387 if (IS_I9XX(dev))
1388 start = 1024*1024;
1389 else
1390 start = 512*1024;
1391
1392 for (i = start; i < obj->size; i <<= 1)
1393 ;
1394
1395 return i;
1396}
1397
1398/**
1399 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1400 * @dev: DRM device
1401 * @data: GTT mapping ioctl data
1402 * @file_priv: GEM object info
1403 *
1404 * Simply returns the fake offset to userspace so it can mmap it.
1405 * The mmap call will end up in drm_gem_mmap(), which will set things
1406 * up so we can get faults in the handler above.
1407 *
1408 * The fault handler will take care of binding the object into the GTT
1409 * (since it may have been evicted to make room for something), allocating
1410 * a fence register, and mapping the appropriate aperture address into
1411 * userspace.
1412 */
1413int
1414i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv)
1416{
1417 struct drm_i915_gem_mmap_gtt *args = data;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 struct drm_gem_object *obj;
1420 struct drm_i915_gem_object *obj_priv;
1421 int ret;
1422
1423 if (!(dev->driver->driver_features & DRIVER_GEM))
1424 return -ENODEV;
1425
1426 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1427 if (obj == NULL)
1428 return -EBADF;
1429
1430 mutex_lock(&dev->struct_mutex);
1431
1432 obj_priv = obj->driver_private;
1433
1434 if (!obj_priv->mmap_offset) {
1435 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1436 if (ret) {
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
de151cf6 1439 return ret;
13af1062 1440 }
de151cf6
JB		 1441 }
1442
1443 args->offset = obj_priv->mmap_offset;
1444
de151cf6
JB		 1445 /*
1446 * Pull it into the GTT so that we have a page list (makes the
1447 * initial fault faster and any subsequent flushing possible).
1448 */
1449 if (!obj_priv->agp_mem) {
e67b8ce1 1450 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1451 if (ret) {
1452 drm_gem_object_unreference(obj);
1453 mutex_unlock(&dev->struct_mutex);
1454 return ret;
1455 }
14b60391 1456 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1457 }
1458
1459 drm_gem_object_unreference(obj);
1460 mutex_unlock(&dev->struct_mutex);
1461
1462 return 0;
1463}
1464
6911a9b8 1465void
856fa198 1466i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b
EA		 1467{
1468 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1469 int page_count = obj->size / PAGE_SIZE;
1470 int i;
1471
856fa198 1472 BUG_ON(obj_priv->pages_refcount == 0);
673a394b 1473
856fa198
EA		 1474 if (--obj_priv->pages_refcount != 0)
1475 return;
673a394b 1476
280b713b
EA		 1477 if (obj_priv->tiling_mode != I915_TILING_NONE)
1478 i915_gem_object_save_bit_17_swizzle(obj);
1479
3ef94daa 1480 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1481 obj_priv->dirty = 0;
3ef94daa
CW		 1482
1483 for (i = 0; i < page_count; i++) {
1484 if (obj_priv->pages[i] == NULL)
1485 break;
1486
1487 if (obj_priv->dirty)
1488 set_page_dirty(obj_priv->pages[i]);
1489
1490 if (obj_priv->madv == I915_MADV_WILLNEED)
13a05fd9 1491 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1492
1493 page_cache_release(obj_priv->pages[i]);
1494 }
673a394b
EA		 1495 obj_priv->dirty = 0;
1496
8e7d2b2c 1497 drm_free_large(obj_priv->pages);
856fa198 1498 obj_priv->pages = NULL;
673a394b
EA		 1499}
1500
1501static void
ce44b0ea 1502i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
673a394b
EA		 1503{
1504 struct drm_device *dev = obj->dev;
1505 drm_i915_private_t *dev_priv = dev->dev_private;
1506 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1507
1508 /* Add a reference if we're newly entering the active list. */
1509 if (!obj_priv->active) {
1510 drm_gem_object_reference(obj);
1511 obj_priv->active = 1;
1512 }
1513 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1514 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1515 list_move_tail(&obj_priv->list,
1516 &dev_priv->mm.active_list);
5e118f41 1517 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1518 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1519}
1520
ce44b0ea
EA		 1521static void
1522i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1523{
1524 struct drm_device *dev = obj->dev;
1525 drm_i915_private_t *dev_priv = dev->dev_private;
1526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1527
1528 BUG_ON(!obj_priv->active);
1529 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1530 obj_priv->last_rendering_seqno = 0;
1531}
673a394b
EA		 1532
1533static void
1534i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1535{
1536 struct drm_device *dev = obj->dev;
1537 drm_i915_private_t *dev_priv = dev->dev_private;
1538 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1539
1540 i915_verify_inactive(dev, __FILE__, __LINE__);
1541 if (obj_priv->pin_count != 0)
1542 list_del_init(&obj_priv->list);
1543 else
1544 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1545
ce44b0ea 1546 obj_priv->last_rendering_seqno = 0;
673a394b
EA		 1547 if (obj_priv->active) {
1548 obj_priv->active = 0;
1549 drm_gem_object_unreference(obj);
1550 }
1551 i915_verify_inactive(dev, __FILE__, __LINE__);
1552}
1553
1554/**
1555 * Creates a new sequence number, emitting a write of it to the status page
1556 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1557 *
1558 * Must be called with struct_lock held.
1559 *
1560 * Returned sequence numbers are nonzero on success.
1561 */
1562static uint32_t
b962442e
EA		 1563i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1564 uint32_t flush_domains)
673a394b
EA		 1565{
1566 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1567 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1568 struct drm_i915_gem_request *request;
1569 uint32_t seqno;
1570 int was_empty;
1571 RING_LOCALS;
1572
b962442e
EA		 1573 if (file_priv != NULL)
1574 i915_file_priv = file_priv->driver_priv;
1575
9a298b2a 1576 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1577 if (request == NULL)
1578 return 0;
1579
1580 /* Grab the seqno we're going to make this request be, and bump the
1581 * next (skipping 0 so it can be the reserved no-seqno value).
1582 */
1583 seqno = dev_priv->mm.next_gem_seqno;
1584 dev_priv->mm.next_gem_seqno++;
1585 if (dev_priv->mm.next_gem_seqno == 0)
1586 dev_priv->mm.next_gem_seqno++;
1587
1588 BEGIN_LP_RING(4);
1589 OUT_RING(MI_STORE_DWORD_INDEX);
1590 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1591 OUT_RING(seqno);
1592
1593 OUT_RING(MI_USER_INTERRUPT);
1594 ADVANCE_LP_RING();
1595
1596 DRM_DEBUG("%d\n", seqno);
1597
1598 request->seqno = seqno;
1599 request->emitted_jiffies = jiffies;
673a394b
EA		 1600 was_empty = list_empty(&dev_priv->mm.request_list);
1601 list_add_tail(&request->list, &dev_priv->mm.request_list);
b962442e
EA		 1602 if (i915_file_priv) {
1603 list_add_tail(&request->client_list,
1604 &i915_file_priv->mm.request_list);
1605 } else {
1606 INIT_LIST_HEAD(&request->client_list);
1607 }
673a394b 1608
ce44b0ea
EA		 1609 /* Associate any objects on the flushing list matching the write
1610 * domain we're flushing with our flush.
1611 */
1612 if (flush_domains != 0) {
1613 struct drm_i915_gem_object *obj_priv, *next;
1614
1615 list_for_each_entry_safe(obj_priv, next,
1616 &dev_priv->mm.flushing_list, list) {
1617 struct drm_gem_object *obj = obj_priv->obj;
1618
1619 if ((obj->write_domain & flush_domains) ==
1620 obj->write_domain) {
1c5d22f7
CW		 1621 uint32_t old_write_domain = obj->write_domain;
1622
ce44b0ea
EA		 1623 obj->write_domain = 0;
1624 i915_gem_object_move_to_active(obj, seqno);
1c5d22f7
CW		 1625
1626 trace_i915_gem_object_change_domain(obj,
1627 obj->read_domains,
1628 old_write_domain);
ce44b0ea
EA		 1629 }
1630 }
1631
1632 }
1633
f65d9421
BG		 1634 if (!dev_priv->mm.suspended) {
1635 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1636 if (was_empty)
1637 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1638 }
673a394b
EA		 1639 return seqno;
1640}
1641
1642/**
1643 * Command execution barrier
1644 *
1645 * Ensures that all commands in the ring are finished
1646 * before signalling the CPU
1647 */
3043c60c 1648static uint32_t
673a394b
EA		 1649i915_retire_commands(struct drm_device *dev)
1650{
1651 drm_i915_private_t *dev_priv = dev->dev_private;
1652 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1653 uint32_t flush_domains = 0;
1654 RING_LOCALS;
1655
1656 /* The sampler always gets flushed on i965 (sigh) */
1657 if (IS_I965G(dev))
1658 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1659 BEGIN_LP_RING(2);
1660 OUT_RING(cmd);
1661 OUT_RING(0); /* noop */
1662 ADVANCE_LP_RING();
1663 return flush_domains;
1664}
1665
1666/**
1667 * Moves buffers associated only with the given active seqno from the active
1668 * to inactive list, potentially freeing them.
1669 */
1670static void
1671i915_gem_retire_request(struct drm_device *dev,
1672 struct drm_i915_gem_request *request)
1673{
1674 drm_i915_private_t *dev_priv = dev->dev_private;
1675
1c5d22f7
CW		 1676 trace_i915_gem_request_retire(dev, request->seqno);
1677
673a394b
EA		 1678 /* Move any buffers on the active list that are no longer referenced
1679 * by the ringbuffer to the flushing/inactive lists as appropriate.
1680 */
5e118f41 1681 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1682 while (!list_empty(&dev_priv->mm.active_list)) {
1683 struct drm_gem_object *obj;
1684 struct drm_i915_gem_object *obj_priv;
1685
1686 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1687 struct drm_i915_gem_object,
1688 list);
1689 obj = obj_priv->obj;
1690
1691 /* If the seqno being retired doesn't match the oldest in the
1692 * list, then the oldest in the list must still be newer than
1693 * this seqno.
1694 */
1695 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1696 goto out;
de151cf6 1697
673a394b
EA		 1698#if WATCH_LRU
1699 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1700 __func__, request->seqno, obj);
1701#endif
1702
ce44b0ea
EA		 1703 if (obj->write_domain != 0)
1704 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1705 else {
1706 /* Take a reference on the object so it won't be
1707 * freed while the spinlock is held. The list
1708 * protection for this spinlock is safe when breaking
1709 * the lock like this since the next thing we do
1710 * is just get the head of the list again.
1711 */
1712 drm_gem_object_reference(obj);
673a394b 1713 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1714 spin_unlock(&dev_priv->mm.active_list_lock);
1715 drm_gem_object_unreference(obj);
1716 spin_lock(&dev_priv->mm.active_list_lock);
1717 }
673a394b 1718 }
5e118f41
CW		 1719out:
1720 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1721}
1722
1723/**
1724 * Returns true if seq1 is later than seq2.
1725 */
22be1724 1726bool
673a394b
EA		 1727i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1728{
1729 return (int32_t)(seq1 - seq2) >= 0;
1730}
1731
1732uint32_t
1733i915_get_gem_seqno(struct drm_device *dev)
1734{
1735 drm_i915_private_t *dev_priv = dev->dev_private;
1736
1737 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1738}
1739
1740/**
1741 * This function clears the request list as sequence numbers are passed.
1742 */
1743void
1744i915_gem_retire_requests(struct drm_device *dev)
1745{
1746 drm_i915_private_t *dev_priv = dev->dev_private;
1747 uint32_t seqno;
1748
6c0594a3
KW		 1749 if (!dev_priv->hw_status_page)
1750 return;
1751
673a394b
EA		 1752 seqno = i915_get_gem_seqno(dev);
1753
1754 while (!list_empty(&dev_priv->mm.request_list)) {
1755 struct drm_i915_gem_request *request;
1756 uint32_t retiring_seqno;
1757
1758 request = list_first_entry(&dev_priv->mm.request_list,
1759 struct drm_i915_gem_request,
1760 list);
1761 retiring_seqno = request->seqno;
1762
1763 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1764 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1765 i915_gem_retire_request(dev, request);
1766
1767 list_del(&request->list);
b962442e 1768 list_del(&request->client_list);
9a298b2a 1769 kfree(request);
673a394b
EA		 1770 } else
1771 break;
1772 }
1773}
1774
1775void
1776i915_gem_retire_work_handler(struct work_struct *work)
1777{
1778 drm_i915_private_t *dev_priv;
1779 struct drm_device *dev;
1780
1781 dev_priv = container_of(work, drm_i915_private_t,
1782 mm.retire_work.work);
1783 dev = dev_priv->dev;
1784
1785 mutex_lock(&dev->struct_mutex);
1786 i915_gem_retire_requests(dev);
6dbe2772
KP		 1787 if (!dev_priv->mm.suspended &&
1788 !list_empty(&dev_priv->mm.request_list))
9c9fe1f8 1789 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1790 mutex_unlock(&dev->struct_mutex);
1791}
1792
1793/**
1794 * Waits for a sequence number to be signaled, and cleans up the
1795 * request and object lists appropriately for that event.
1796 */
3043c60c 1797static int
673a394b
EA		 1798i915_wait_request(struct drm_device *dev, uint32_t seqno)
1799{
1800 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1801 u32 ier;
673a394b
EA		 1802 int ret = 0;
1803
1804 BUG_ON(seqno == 0);
1805
ba1234d1 1806 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1807 return -EIO;
1808
673a394b 1809 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
036a4a7d
ZW		 1810 if (IS_IGDNG(dev))
1811 ier = I915_READ(DEIER) | I915_READ(GTIER);
1812 else
1813 ier = I915_READ(IER);
802c7eb6
JB		 1814 if (!ier) {
1815 DRM_ERROR("something (likely vbetool) disabled "
1816 "interrupts, re-enabling\n");
1817 i915_driver_irq_preinstall(dev);
1818 i915_driver_irq_postinstall(dev);
1819 }
1820
1c5d22f7
CW		 1821 trace_i915_gem_request_wait_begin(dev, seqno);
1822
673a394b
EA		 1823 dev_priv->mm.waiting_gem_seqno = seqno;
1824 i915_user_irq_get(dev);
1825 ret = wait_event_interruptible(dev_priv->irq_queue,
1826 i915_seqno_passed(i915_get_gem_seqno(dev),
1827 seqno) ||
ba1234d1 1828 atomic_read(&dev_priv->mm.wedged));
673a394b
EA		 1829 i915_user_irq_put(dev);
1830 dev_priv->mm.waiting_gem_seqno = 0;
1c5d22f7
CW		 1831
1832 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1833 }
ba1234d1 1834 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1835 ret = -EIO;
1836
1837 if (ret && ret != -ERESTARTSYS)
1838 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1839 __func__, ret, seqno, i915_get_gem_seqno(dev));
1840
1841 /* Directly dispatch request retiring. While we have the work queue
1842 * to handle this, the waiter on a request often wants an associated
1843 * buffer to have made it to the inactive list, and we would need
1844 * a separate wait queue to handle that.
1845 */
1846 if (ret == 0)
1847 i915_gem_retire_requests(dev);
1848
1849 return ret;
1850}
1851
1852static void
1853i915_gem_flush(struct drm_device *dev,
1854 uint32_t invalidate_domains,
1855 uint32_t flush_domains)
1856{
1857 drm_i915_private_t *dev_priv = dev->dev_private;
1858 uint32_t cmd;
1859 RING_LOCALS;
1860
1861#if WATCH_EXEC
1862 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1863 invalidate_domains, flush_domains);
1864#endif
1c5d22f7
CW		 1865 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1866 invalidate_domains, flush_domains);
673a394b
EA		 1867
1868 if (flush_domains & I915_GEM_DOMAIN_CPU)
1869 drm_agp_chipset_flush(dev);
1870
21d509e3 1871 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
673a394b
EA		 1872 /*
1873 * read/write caches:
1874 *
1875 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1876 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1877 * also flushed at 2d versus 3d pipeline switches.
1878 *
1879 * read-only caches:
1880 *
1881 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1882 * MI_READ_FLUSH is set, and is always flushed on 965.
1883 *
1884 * I915_GEM_DOMAIN_COMMAND may not exist?
1885 *
1886 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1887 * invalidated when MI_EXE_FLUSH is set.
1888 *
1889 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1890 * invalidated with every MI_FLUSH.
1891 *
1892 * TLBs:
1893 *
1894 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1895 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1896 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1897 * are flushed at any MI_FLUSH.
1898 */
1899
1900 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1901 if ((invalidate_domains|flush_domains) &
1902 I915_GEM_DOMAIN_RENDER)
1903 cmd &= ~MI_NO_WRITE_FLUSH;
1904 if (!IS_I965G(dev)) {
1905 /*
1906 * On the 965, the sampler cache always gets flushed
1907 * and this bit is reserved.
1908 */
1909 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1910 cmd |= MI_READ_FLUSH;
1911 }
1912 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1913 cmd |= MI_EXE_FLUSH;
1914
1915#if WATCH_EXEC
1916 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1917#endif
1918 BEGIN_LP_RING(2);
1919 OUT_RING(cmd);
1920 OUT_RING(0); /* noop */
1921 ADVANCE_LP_RING();
1922 }
1923}
1924
1925/**
1926 * Ensures that all rendering to the object has completed and the object is
1927 * safe to unbind from the GTT or access from the CPU.
1928 */
1929static int
1930i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1931{
1932 struct drm_device *dev = obj->dev;
1933 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1934 int ret;
1935
e47c68e9
EA		 1936 /* This function only exists to support waiting for existing rendering,
1937 * not for emitting required flushes.
673a394b 1938 */
e47c68e9 1939 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1940
1941 /* If there is rendering queued on the buffer being evicted, wait for
1942 * it.
1943 */
1944 if (obj_priv->active) {
1945#if WATCH_BUF
1946 DRM_INFO("%s: object %p wait for seqno %08x\n",
1947 __func__, obj, obj_priv->last_rendering_seqno);
1948#endif
1949 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1950 if (ret != 0)
1951 return ret;
1952 }
1953
1954 return 0;
1955}
1956
1957/**
1958 * Unbinds an object from the GTT aperture.
1959 */
0f973f27 1960int
673a394b
EA		 1961i915_gem_object_unbind(struct drm_gem_object *obj)
1962{
1963 struct drm_device *dev = obj->dev;
1964 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1965 int ret = 0;
1966
1967#if WATCH_BUF
1968 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1969 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1970#endif
1971 if (obj_priv->gtt_space == NULL)
1972 return 0;
1973
1974 if (obj_priv->pin_count != 0) {
1975 DRM_ERROR("Attempting to unbind pinned buffer\n");
1976 return -EINVAL;
1977 }
1978
5323fd04
EA		 1979 /* blow away mappings if mapped through GTT */
1980 i915_gem_release_mmap(obj);
1981
1982 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1983 i915_gem_clear_fence_reg(obj);
1984
673a394b
EA		 1985 /* Move the object to the CPU domain to ensure that
1986 * any possible CPU writes while it's not in the GTT
1987 * are flushed when we go to remap it. This will
1988 * also ensure that all pending GPU writes are finished
1989 * before we unbind.
1990 */
e47c68e9 1991 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 1992 if (ret) {
e47c68e9
EA		 1993 if (ret != -ERESTARTSYS)
1994 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 1995 return ret;
1996 }
1997
5323fd04
EA		 1998 BUG_ON(obj_priv->active);
1999
673a394b
EA		 2000 if (obj_priv->agp_mem != NULL) {
2001 drm_unbind_agp(obj_priv->agp_mem);
2002 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2003 obj_priv->agp_mem = NULL;
2004 }
2005
856fa198 2006 i915_gem_object_put_pages(obj);
a32808c0 2007 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 2008
2009 if (obj_priv->gtt_space) {
2010 atomic_dec(&dev->gtt_count);
2011 atomic_sub(obj->size, &dev->gtt_memory);
2012
2013 drm_mm_put_block(obj_priv->gtt_space);
2014 obj_priv->gtt_space = NULL;
2015 }
2016
2017 /* Remove ourselves from the LRU list if present. */
2018 if (!list_empty(&obj_priv->list))
2019 list_del_init(&obj_priv->list);
2020
1c5d22f7
CW		 2021 trace_i915_gem_object_unbind(obj);
2022
673a394b
EA		 2023 return 0;
2024}
2025
07f73f69
CW		 2026static inline int
2027i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
2028{
2029 return !obj_priv->dirty || obj_priv->madv == I915_MADV_DONTNEED;
2030}
2031
2032static struct drm_gem_object *
2033i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2034{
2035 drm_i915_private_t *dev_priv = dev->dev_private;
2036 struct drm_i915_gem_object *obj_priv;
2037 struct drm_gem_object *best = NULL;
2038 struct drm_gem_object *first = NULL;
2039
2040 /* Try to find the smallest clean object */
2041 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2042 struct drm_gem_object *obj = obj_priv->obj;
2043 if (obj->size >= min_size) {
2044 if (i915_gem_object_is_purgeable(obj_priv) &&
2045 (!best || obj->size < best->size)) {
2046 best = obj;
2047 if (best->size == min_size)
2048 return best;
2049 }
2050 if (!first)
2051 first = obj;
2052 }
2053 }
2054
2055 return best ? best : first;
2056}
2057
2058static int
2059i915_gem_evict_everything(struct drm_device *dev)
2060{
2061 drm_i915_private_t *dev_priv = dev->dev_private;
2062 uint32_t seqno;
2063 int ret;
2064 bool lists_empty;
2065
2066 DRM_INFO("GTT full, evicting everything: "
2067 "%d objects [%d pinned], "
2068 "%d object bytes [%d pinned], "
2069 "%d/%d gtt bytes\n",
2070 atomic_read(&dev->object_count),
2071 atomic_read(&dev->pin_count),
2072 atomic_read(&dev->object_memory),
2073 atomic_read(&dev->pin_memory),
2074 atomic_read(&dev->gtt_memory),
2075 dev->gtt_total);
2076
2077 spin_lock(&dev_priv->mm.active_list_lock);
2078 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2079 list_empty(&dev_priv->mm.flushing_list) &&
2080 list_empty(&dev_priv->mm.active_list));
2081 spin_unlock(&dev_priv->mm.active_list_lock);
2082
2083 if (lists_empty) {
2084 DRM_ERROR("GTT full, but lists empty!\n");
2085 return -ENOSPC;
2086 }
2087
2088 /* Flush everything (on to the inactive lists) and evict */
2089 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2090 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2091 if (seqno == 0)
2092 return -ENOMEM;
2093
2094 ret = i915_wait_request(dev, seqno);
2095 if (ret)
2096 return ret;
2097
ab5ee576 2098 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2099 if (ret)
2100 return ret;
2101
2102 spin_lock(&dev_priv->mm.active_list_lock);
2103 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2104 list_empty(&dev_priv->mm.flushing_list) &&
2105 list_empty(&dev_priv->mm.active_list));
2106 spin_unlock(&dev_priv->mm.active_list_lock);
2107 BUG_ON(!lists_empty);
2108
2109 return 0;
2110}
2111
673a394b 2112static int
07f73f69 2113i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2114{
2115 drm_i915_private_t *dev_priv = dev->dev_private;
2116 struct drm_gem_object *obj;
07f73f69 2117 int ret;
673a394b
EA		 2118
2119 for (;;) {
07f73f69
CW		 2120 i915_gem_retire_requests(dev);
2121
673a394b
EA		 2122 /* If there's an inactive buffer available now, grab it
2123 * and be done.
2124 */
07f73f69
CW		 2125 obj = i915_gem_find_inactive_object(dev, min_size);
2126 if (obj) {
2127 struct drm_i915_gem_object *obj_priv;
2128
673a394b
EA		 2129#if WATCH_LRU
2130 DRM_INFO("%s: evicting %p\n", __func__, obj);
2131#endif
07f73f69
CW		 2132 obj_priv = obj->driver_private;
2133 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2134 BUG_ON(obj_priv->active);
2135
2136 /* Wait on the rendering and unbind the buffer. */
07f73f69 2137 return i915_gem_object_unbind(obj);
673a394b
EA		 2138 }
2139
2140 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2141 * things, wait for the next to finish and hopefully leave us
2142 * a buffer to evict.
673a394b
EA		 2143 */
2144 if (!list_empty(&dev_priv->mm.request_list)) {
2145 struct drm_i915_gem_request *request;
2146
2147 request = list_first_entry(&dev_priv->mm.request_list,
2148 struct drm_i915_gem_request,
2149 list);
2150
2151 ret = i915_wait_request(dev, request->seqno);
2152 if (ret)
07f73f69 2153 return ret;
673a394b 2154
07f73f69 2155 continue;
673a394b
EA		 2156 }
2157
2158 /* If we didn't have anything on the request list but there
2159 * are buffers awaiting a flush, emit one and try again.
2160 * When we wait on it, those buffers waiting for that flush
2161 * will get moved to inactive.
2162 */
2163 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2164 struct drm_i915_gem_object *obj_priv;
07f73f69 2165
9a1e2582
CW		 2166 /* Find an object that we can immediately reuse */
2167 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2168 obj = obj_priv->obj;
2169 if (obj->size >= min_size)
2170 break;
673a394b 2171
9a1e2582
CW		 2172 obj = NULL;
2173 }
07f73f69 2174
9a1e2582
CW		 2175 if (obj != NULL) {
2176 uint32_t seqno;
673a394b 2177
9a1e2582
CW		 2178 i915_gem_flush(dev,
2179 obj->write_domain,
2180 obj->write_domain);
2181 seqno = i915_add_request(dev, NULL, obj->write_domain);
2182 if (seqno == 0)
2183 return -ENOMEM;
2184
2185 ret = i915_wait_request(dev, seqno);
2186 if (ret)
2187 return ret;
2188
2189 continue;
2190 }
673a394b
EA		 2191 }
2192
07f73f69
CW		 2193 /* If we didn't do any of the above, there's no single buffer
2194 * large enough to swap out for the new one, so just evict
2195 * everything and start again. (This should be rare.)
673a394b 2196 */
07f73f69
CW		 2197 if (!list_empty (&dev_priv->mm.inactive_list)) {
2198 DRM_INFO("GTT full, evicting inactive buffers\n");
ab5ee576 2199 return i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2200 } else
2201 return i915_gem_evict_everything(dev);
ac94a962 2202 }
ac94a962
KP		 2203}
2204
6911a9b8 2205int
856fa198 2206i915_gem_object_get_pages(struct drm_gem_object *obj)
673a394b
EA		 2207{
2208 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2209 int page_count, i;
2210 struct address_space *mapping;
2211 struct inode *inode;
2212 struct page *page;
2213 int ret;
2214
856fa198 2215 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2216 return 0;
2217
2218 /* Get the list of pages out of our struct file. They'll be pinned
2219 * at this point until we release them.
2220 */
2221 page_count = obj->size / PAGE_SIZE;
856fa198 2222 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2223 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2224 if (obj_priv->pages == NULL) {
07f73f69 2225 DRM_ERROR("Failed to allocate page list\n");
856fa198 2226 obj_priv->pages_refcount--;
673a394b
EA		 2227 return -ENOMEM;
2228 }
2229
2230 inode = obj->filp->f_path.dentry->d_inode;
2231 mapping = inode->i_mapping;
2232 for (i = 0; i < page_count; i++) {
2233 page = read_mapping_page(mapping, i, NULL);
2234 if (IS_ERR(page)) {
2235 ret = PTR_ERR(page);
856fa198 2236 i915_gem_object_put_pages(obj);
673a394b
EA		 2237 return ret;
2238 }
856fa198 2239 obj_priv->pages[i] = page;
673a394b 2240 }
280b713b
EA		 2241
2242 if (obj_priv->tiling_mode != I915_TILING_NONE)
2243 i915_gem_object_do_bit_17_swizzle(obj);
2244
673a394b
EA		 2245 return 0;
2246}
2247
de151cf6
JB		 2248static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2249{
2250 struct drm_gem_object *obj = reg->obj;
2251 struct drm_device *dev = obj->dev;
2252 drm_i915_private_t *dev_priv = dev->dev_private;
2253 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2254 int regnum = obj_priv->fence_reg;
2255 uint64_t val;
2256
2257 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2258 0xfffff000) << 32;
2259 val |= obj_priv->gtt_offset & 0xfffff000;
2260 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2261 if (obj_priv->tiling_mode == I915_TILING_Y)
2262 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2263 val |= I965_FENCE_REG_VALID;
2264
2265 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2266}
2267
2268static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2269{
2270 struct drm_gem_object *obj = reg->obj;
2271 struct drm_device *dev = obj->dev;
2272 drm_i915_private_t *dev_priv = dev->dev_private;
2273 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2274 int regnum = obj_priv->fence_reg;
0f973f27 2275 int tile_width;
dc529a4f 2276 uint32_t fence_reg, val;
de151cf6
JB		 2277 uint32_t pitch_val;
2278
2279 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2280 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2281 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2282 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2283 return;
2284 }
2285
0f973f27
JB		 2286 if (obj_priv->tiling_mode == I915_TILING_Y &&
2287 HAS_128_BYTE_Y_TILING(dev))
2288 tile_width = 128;
de151cf6 2289 else
0f973f27
JB		 2290 tile_width = 512;
2291
2292 /* Note: pitch better be a power of two tile widths */
2293 pitch_val = obj_priv->stride / tile_width;
2294 pitch_val = ffs(pitch_val) - 1;
de151cf6
JB		 2295
2296 val = obj_priv->gtt_offset;
2297 if (obj_priv->tiling_mode == I915_TILING_Y)
2298 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2299 val |= I915_FENCE_SIZE_BITS(obj->size);
2300 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2301 val |= I830_FENCE_REG_VALID;
2302
dc529a4f
EA		 2303 if (regnum < 8)
2304 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2305 else
2306 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2307 I915_WRITE(fence_reg, val);
de151cf6
JB		 2308}
2309
2310static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2311{
2312 struct drm_gem_object *obj = reg->obj;
2313 struct drm_device *dev = obj->dev;
2314 drm_i915_private_t *dev_priv = dev->dev_private;
2315 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2316 int regnum = obj_priv->fence_reg;
2317 uint32_t val;
2318 uint32_t pitch_val;
8d7773a3 2319 uint32_t fence_size_bits;
de151cf6 2320
8d7773a3 2321 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2322 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2323 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2324 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2325 return;
2326 }
2327
e76a16de
EA		 2328 pitch_val = obj_priv->stride / 128;
2329 pitch_val = ffs(pitch_val) - 1;
2330 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2331
de151cf6
JB		 2332 val = obj_priv->gtt_offset;
2333 if (obj_priv->tiling_mode == I915_TILING_Y)
2334 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2335 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2336 WARN_ON(fence_size_bits & ~0x00000f00);
2337 val |= fence_size_bits;
de151cf6
JB		 2338 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2339 val |= I830_FENCE_REG_VALID;
2340
2341 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2342}
2343
2344/**
2345 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2346 * @obj: object to map through a fence reg
2347 *
2348 * When mapping objects through the GTT, userspace wants to be able to write
2349 * to them without having to worry about swizzling if the object is tiled.
2350 *
2351 * This function walks the fence regs looking for a free one for @obj,
2352 * stealing one if it can't find any.
2353 *
2354 * It then sets up the reg based on the object's properties: address, pitch
2355 * and tiling format.
2356 */
8c4b8c3f
CW		 2357int
2358i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2359{
2360 struct drm_device *dev = obj->dev;
79e53945 2361 struct drm_i915_private *dev_priv = dev->dev_private;
de151cf6
JB		 2362 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2363 struct drm_i915_fence_reg *reg = NULL;
fc7170ba
CW		 2364 struct drm_i915_gem_object *old_obj_priv = NULL;
2365 int i, ret, avail;
de151cf6 2366
a09ba7fa
EA		 2367 /* Just update our place in the LRU if our fence is getting used. */
2368 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2369 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2370 return 0;
2371 }
2372
de151cf6
JB		 2373 switch (obj_priv->tiling_mode) {
2374 case I915_TILING_NONE:
2375 WARN(1, "allocating a fence for non-tiled object?\n");
2376 break;
2377 case I915_TILING_X:
0f973f27
JB		 2378 if (!obj_priv->stride)
2379 return -EINVAL;
2380 WARN((obj_priv->stride & (512 - 1)),
2381 "object 0x%08x is X tiled but has non-512B pitch\n",
2382 obj_priv->gtt_offset);
de151cf6
JB		 2383 break;
2384 case I915_TILING_Y:
0f973f27
JB		 2385 if (!obj_priv->stride)
2386 return -EINVAL;
2387 WARN((obj_priv->stride & (128 - 1)),
2388 "object 0x%08x is Y tiled but has non-128B pitch\n",
2389 obj_priv->gtt_offset);
de151cf6
JB		 2390 break;
2391 }
2392
2393 /* First try to find a free reg */
fc7170ba 2394 avail = 0;
de151cf6
JB		 2395 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2396 reg = &dev_priv->fence_regs[i];
2397 if (!reg->obj)
2398 break;
fc7170ba
CW		 2399
2400 old_obj_priv = reg->obj->driver_private;
2401 if (!old_obj_priv->pin_count)
2402 avail++;
de151cf6
JB		 2403 }
2404
2405 /* None available, try to steal one or wait for a user to finish */
2406 if (i == dev_priv->num_fence_regs) {
a09ba7fa 2407 struct drm_gem_object *old_obj = NULL;
de151cf6 2408
fc7170ba 2409 if (avail == 0)
2939e1f5 2410 return -ENOSPC;
fc7170ba 2411
a09ba7fa
EA		 2412 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2413 fence_list) {
2414 old_obj = old_obj_priv->obj;
d7619c4b
CW		 2415
2416 if (old_obj_priv->pin_count)
2417 continue;
2418
a09ba7fa
EA		 2419 /* Take a reference, as otherwise the wait_rendering
2420 * below may cause the object to get freed out from
2421 * under us.
2422 */
2423 drm_gem_object_reference(old_obj);
2424
d7619c4b
CW		 2425 /* i915 uses fences for GPU access to tiled buffers */
2426 if (IS_I965G(dev) || !old_obj_priv->active)
de151cf6 2427 break;
d7619c4b 2428
a09ba7fa
EA		 2429 /* This brings the object to the head of the LRU if it
2430 * had been written to. The only way this should
2431 * result in us waiting longer than the expected
2432 * optimal amount of time is if there was a
2433 * fence-using buffer later that was read-only.
2434 */
2435 i915_gem_object_flush_gpu_write_domain(old_obj);
2436 ret = i915_gem_object_wait_rendering(old_obj);
58c2fb64
CW		 2437 if (ret != 0) {
2438 drm_gem_object_unreference(old_obj);
d7619c4b 2439 return ret;
de151cf6 2440 }
d7619c4b 2441
a09ba7fa 2442 break;
de151cf6
JB		 2443 }
2444
2445 /*
2446 * Zap this virtual mapping so we can set up a fence again
2447 * for this object next time we need it.
2448 */
58c2fb64
CW		 2449 i915_gem_release_mmap(old_obj);
2450
a09ba7fa 2451 i = old_obj_priv->fence_reg;
58c2fb64
CW		 2452 reg = &dev_priv->fence_regs[i];
2453
de151cf6 2454 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2455 list_del_init(&old_obj_priv->fence_list);
58c2fb64 2456
a09ba7fa 2457 drm_gem_object_unreference(old_obj);
de151cf6
JB		 2458 }
2459
2460 obj_priv->fence_reg = i;
a09ba7fa
EA		 2461 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2462
de151cf6
JB		 2463 reg->obj = obj;
2464
2465 if (IS_I965G(dev))
2466 i965_write_fence_reg(reg);
2467 else if (IS_I9XX(dev))
2468 i915_write_fence_reg(reg);
2469 else
2470 i830_write_fence_reg(reg);
d9ddcb96 2471
1c5d22f7
CW		 2472 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2473
d9ddcb96 2474 return 0;
de151cf6
JB		 2475}
2476
2477/**
2478 * i915_gem_clear_fence_reg - clear out fence register info
2479 * @obj: object to clear
2480 *
2481 * Zeroes out the fence register itself and clears out the associated
2482 * data structures in dev_priv and obj_priv.
2483 */
2484static void
2485i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2486{
2487 struct drm_device *dev = obj->dev;
79e53945 2488 drm_i915_private_t *dev_priv = dev->dev_private;
de151cf6
JB		 2489 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2490
2491 if (IS_I965G(dev))
2492 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
dc529a4f
EA		 2493 else {
2494 uint32_t fence_reg;
2495
2496 if (obj_priv->fence_reg < 8)
2497 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2498 else
2499 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2500 8) * 4;
2501
2502 I915_WRITE(fence_reg, 0);
2503 }
de151cf6
JB		 2504
2505 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2506 obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2507 list_del_init(&obj_priv->fence_list);
de151cf6
JB		 2508}
2509
52dc7d32
CW		 2510/**
2511 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2512 * to the buffer to finish, and then resets the fence register.
2513 * @obj: tiled object holding a fence register.
2514 *
2515 * Zeroes out the fence register itself and clears out the associated
2516 * data structures in dev_priv and obj_priv.
2517 */
2518int
2519i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2520{
2521 struct drm_device *dev = obj->dev;
2522 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2523
2524 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2525 return 0;
2526
2527 /* On the i915, GPU access to tiled buffers is via a fence,
2528 * therefore we must wait for any outstanding access to complete
2529 * before clearing the fence.
2530 */
2531 if (!IS_I965G(dev)) {
2532 int ret;
2533
2534 i915_gem_object_flush_gpu_write_domain(obj);
2535 i915_gem_object_flush_gtt_write_domain(obj);
2536 ret = i915_gem_object_wait_rendering(obj);
2537 if (ret != 0)
2538 return ret;
2539 }
2540
2541 i915_gem_clear_fence_reg (obj);
2542
2543 return 0;
2544}
2545
673a394b
EA		 2546/**
2547 * Finds free space in the GTT aperture and binds the object there.
2548 */
2549static int
2550i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2551{
2552 struct drm_device *dev = obj->dev;
2553 drm_i915_private_t *dev_priv = dev->dev_private;
2554 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2555 struct drm_mm_node *free_space;
07f73f69
CW		 2556 bool retry_alloc = false;
2557 int ret;
673a394b 2558
9bb2d6f9
EA		 2559 if (dev_priv->mm.suspended)
2560 return -EBUSY;
3ef94daa
CW		 2561
2562 if (obj_priv->madv == I915_MADV_DONTNEED) {
2563 DRM_ERROR("Attempting to bind a purgeable object\n");
2564 return -EINVAL;
2565 }
2566
673a394b 2567 if (alignment == 0)
0f973f27 2568 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2569 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2570 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2571 return -EINVAL;
2572 }
2573
2574 search_free:
2575 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2576 obj->size, alignment, 0);
2577 if (free_space != NULL) {
2578 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2579 alignment);
2580 if (obj_priv->gtt_space != NULL) {
2581 obj_priv->gtt_space->private = obj;
2582 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2583 }
2584 }
2585 if (obj_priv->gtt_space == NULL) {
2586 /* If the gtt is empty and we're still having trouble
2587 * fitting our object in, we're out of memory.
2588 */
2589#if WATCH_LRU
2590 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2591#endif
07f73f69 2592 ret = i915_gem_evict_something(dev, obj->size);
673a394b 2593 if (ret != 0) {
ac94a962
KP		 2594 if (ret != -ERESTARTSYS)
2595 DRM_ERROR("Failed to evict a buffer %d\n", ret);
673a394b
EA		 2596 return ret;
2597 }
2598 goto search_free;
2599 }
2600
2601#if WATCH_BUF
cfd43c02 2602 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2603 obj->size, obj_priv->gtt_offset);
2604#endif
07f73f69
CW		 2605 if (retry_alloc) {
2606 i915_gem_object_set_page_gfp_mask (obj,
2607 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2608 }
856fa198 2609 ret = i915_gem_object_get_pages(obj);
07f73f69
CW		 2610 if (retry_alloc) {
2611 i915_gem_object_set_page_gfp_mask (obj,
2612 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2613 }
673a394b
EA		 2614 if (ret) {
2615 drm_mm_put_block(obj_priv->gtt_space);
2616 obj_priv->gtt_space = NULL;
07f73f69
CW		 2617
2618 if (ret == -ENOMEM) {
2619 /* first try to clear up some space from the GTT */
2620 ret = i915_gem_evict_something(dev, obj->size);
2621 if (ret) {
2622 if (ret != -ERESTARTSYS)
2623 DRM_ERROR("Failed to allocate space for backing pages %d\n", ret);
2624
2625 /* now try to shrink everyone else */
2626 if (! retry_alloc) {
2627 retry_alloc = true;
2628 goto search_free;
2629 }
2630
2631 return ret;
2632 }
2633
2634 goto search_free;
2635 }
2636
673a394b
EA		 2637 return ret;
2638 }
2639
673a394b
EA		 2640 /* Create an AGP memory structure pointing at our pages, and bind it
2641 * into the GTT.
2642 */
2643 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2644 obj_priv->pages,
07f73f69 2645 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2646 obj_priv->gtt_offset,
2647 obj_priv->agp_type);
673a394b 2648 if (obj_priv->agp_mem == NULL) {
856fa198 2649 i915_gem_object_put_pages(obj);
673a394b
EA		 2650 drm_mm_put_block(obj_priv->gtt_space);
2651 obj_priv->gtt_space = NULL;
07f73f69
CW		 2652
2653 ret = i915_gem_evict_something(dev, obj->size);
2654 if (ret) {
2655 if (ret != -ERESTARTSYS)
2656 DRM_ERROR("Failed to allocate space to bind AGP: %d\n", ret);
2657 return ret;
2658 }
2659
2660 goto search_free;
673a394b
EA		 2661 }
2662 atomic_inc(&dev->gtt_count);
2663 atomic_add(obj->size, &dev->gtt_memory);
2664
2665 /* Assert that the object is not currently in any GPU domain. As it
2666 * wasn't in the GTT, there shouldn't be any way it could have been in
2667 * a GPU cache
2668 */
21d509e3
CW		 2669 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2670 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2671
1c5d22f7
CW		 2672 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2673
673a394b
EA		 2674 return 0;
2675}
2676
2677void
2678i915_gem_clflush_object(struct drm_gem_object *obj)
2679{
2680 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2681
2682 /* If we don't have a page list set up, then we're not pinned
2683 * to GPU, and we can ignore the cache flush because it'll happen
2684 * again at bind time.
2685 */
856fa198 2686 if (obj_priv->pages == NULL)
673a394b
EA		 2687 return;
2688
1c5d22f7
CW		 2689 trace_i915_gem_object_clflush(obj);
2690
856fa198 2691 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2692}
2693
e47c68e9
EA		 2694/** Flushes any GPU write domain for the object if it's dirty. */
2695static void
2696i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2697{
2698 struct drm_device *dev = obj->dev;
2699 uint32_t seqno;
1c5d22f7 2700 uint32_t old_write_domain;
e47c68e9
EA		 2701
2702 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2703 return;
2704
2705 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2706 old_write_domain = obj->write_domain;
e47c68e9 2707 i915_gem_flush(dev, 0, obj->write_domain);
b962442e 2708 seqno = i915_add_request(dev, NULL, obj->write_domain);
e47c68e9
EA		 2709 obj->write_domain = 0;
2710 i915_gem_object_move_to_active(obj, seqno);
1c5d22f7
CW		 2711
2712 trace_i915_gem_object_change_domain(obj,
2713 obj->read_domains,
2714 old_write_domain);
e47c68e9
EA		 2715}
2716
2717/** Flushes the GTT write domain for the object if it's dirty. */
2718static void
2719i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2720{
1c5d22f7
CW		 2721 uint32_t old_write_domain;
2722
e47c68e9
EA		 2723 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2724 return;
2725
2726 /* No actual flushing is required for the GTT write domain. Writes
2727 * to it immediately go to main memory as far as we know, so there's
2728 * no chipset flush. It also doesn't land in render cache.
2729 */
1c5d22f7 2730 old_write_domain = obj->write_domain;
e47c68e9 2731 obj->write_domain = 0;
1c5d22f7
CW		 2732
2733 trace_i915_gem_object_change_domain(obj,
2734 obj->read_domains,
2735 old_write_domain);
e47c68e9
EA		 2736}
2737
2738/** Flushes the CPU write domain for the object if it's dirty. */
2739static void
2740i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2741{
2742 struct drm_device *dev = obj->dev;
1c5d22f7 2743 uint32_t old_write_domain;
e47c68e9
EA		 2744
2745 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2746 return;
2747
2748 i915_gem_clflush_object(obj);
2749 drm_agp_chipset_flush(dev);
1c5d22f7 2750 old_write_domain = obj->write_domain;
e47c68e9 2751 obj->write_domain = 0;
1c5d22f7
CW		 2752
2753 trace_i915_gem_object_change_domain(obj,
2754 obj->read_domains,
2755 old_write_domain);
e47c68e9
EA		 2756}
2757
2ef7eeaa
EA		 2758/**
2759 * Moves a single object to the GTT read, and possibly write domain.
2760 *
2761 * This function returns when the move is complete, including waiting on
2762 * flushes to occur.
2763 */
79e53945 2764int
2ef7eeaa
EA		 2765i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2766{
2ef7eeaa 2767 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1c5d22f7 2768 uint32_t old_write_domain, old_read_domains;
e47c68e9 2769 int ret;
2ef7eeaa 2770
02354392
EA		 2771 /* Not valid to be called on unbound objects. */
2772 if (obj_priv->gtt_space == NULL)
2773 return -EINVAL;
2774
e47c68e9
EA		 2775 i915_gem_object_flush_gpu_write_domain(obj);
2776 /* Wait on any GPU rendering and flushing to occur. */
2777 ret = i915_gem_object_wait_rendering(obj);
2778 if (ret != 0)
2779 return ret;
2780
1c5d22f7
CW		 2781 old_write_domain = obj->write_domain;
2782 old_read_domains = obj->read_domains;
2783
e47c68e9
EA		 2784 /* If we're writing through the GTT domain, then CPU and GPU caches
2785 * will need to be invalidated at next use.
2ef7eeaa 2786 */
e47c68e9
EA		 2787 if (write)
2788 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2789
e47c68e9 2790 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2791
e47c68e9
EA		 2792 /* It should now be out of any other write domains, and we can update
2793 * the domain values for our changes.
2794 */
2795 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2796 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2797 if (write) {
2798 obj->write_domain = I915_GEM_DOMAIN_GTT;
2799 obj_priv->dirty = 1;
2ef7eeaa
EA		 2800 }
2801
1c5d22f7
CW		 2802 trace_i915_gem_object_change_domain(obj,
2803 old_read_domains,
2804 old_write_domain);
2805
e47c68e9
EA		 2806 return 0;
2807}
2808
2809/**
2810 * Moves a single object to the CPU read, and possibly write domain.
2811 *
2812 * This function returns when the move is complete, including waiting on
2813 * flushes to occur.
2814 */
2815static int
2816i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2817{
1c5d22f7 2818 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2819 int ret;
2820
2821 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2822 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2823 ret = i915_gem_object_wait_rendering(obj);
2824 if (ret != 0)
2825 return ret;
2ef7eeaa 2826
e47c68e9 2827 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2828
e47c68e9
EA		 2829 /* If we have a partially-valid cache of the object in the CPU,
2830 * finish invalidating it and free the per-page flags.
2ef7eeaa 2831 */
e47c68e9 2832 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2833
1c5d22f7
CW		 2834 old_write_domain = obj->write_domain;
2835 old_read_domains = obj->read_domains;
2836
e47c68e9
EA		 2837 /* Flush the CPU cache if it's still invalid. */
2838 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2839 i915_gem_clflush_object(obj);
2ef7eeaa 2840
e47c68e9 2841 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2842 }
2843
2844 /* It should now be out of any other write domains, and we can update
2845 * the domain values for our changes.
2846 */
e47c68e9
EA		 2847 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2848
2849 /* If we're writing through the CPU, then the GPU read domains will
2850 * need to be invalidated at next use.
2851 */
2852 if (write) {
2853 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2854 obj->write_domain = I915_GEM_DOMAIN_CPU;
2855 }
2ef7eeaa 2856
1c5d22f7
CW		 2857 trace_i915_gem_object_change_domain(obj,
2858 old_read_domains,
2859 old_write_domain);
2860
2ef7eeaa
EA		 2861 return 0;
2862}
2863
673a394b
EA		 2864/*
2865 * Set the next domain for the specified object. This
2866 * may not actually perform the necessary flushing/invaliding though,
2867 * as that may want to be batched with other set_domain operations
2868 *
2869 * This is (we hope) the only really tricky part of gem. The goal
2870 * is fairly simple -- track which caches hold bits of the object
2871 * and make sure they remain coherent. A few concrete examples may
2872 * help to explain how it works. For shorthand, we use the notation
2873 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2874 * a pair of read and write domain masks.
2875 *
2876 * Case 1: the batch buffer
2877 *
2878 * 1. Allocated
2879 * 2. Written by CPU
2880 * 3. Mapped to GTT
2881 * 4. Read by GPU
2882 * 5. Unmapped from GTT
2883 * 6. Freed
2884 *
2885 * Let's take these a step at a time
2886 *
2887 * 1. Allocated
2888 * Pages allocated from the kernel may still have
2889 * cache contents, so we set them to (CPU, CPU) always.
2890 * 2. Written by CPU (using pwrite)
2891 * The pwrite function calls set_domain (CPU, CPU) and
2892 * this function does nothing (as nothing changes)
2893 * 3. Mapped by GTT
2894 * This function asserts that the object is not
2895 * currently in any GPU-based read or write domains
2896 * 4. Read by GPU
2897 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2898 * As write_domain is zero, this function adds in the
2899 * current read domains (CPU+COMMAND, 0).
2900 * flush_domains is set to CPU.
2901 * invalidate_domains is set to COMMAND
2902 * clflush is run to get data out of the CPU caches
2903 * then i915_dev_set_domain calls i915_gem_flush to
2904 * emit an MI_FLUSH and drm_agp_chipset_flush
2905 * 5. Unmapped from GTT
2906 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2907 * flush_domains and invalidate_domains end up both zero
2908 * so no flushing/invalidating happens
2909 * 6. Freed
2910 * yay, done
2911 *
2912 * Case 2: The shared render buffer
2913 *
2914 * 1. Allocated
2915 * 2. Mapped to GTT
2916 * 3. Read/written by GPU
2917 * 4. set_domain to (CPU,CPU)
2918 * 5. Read/written by CPU
2919 * 6. Read/written by GPU
2920 *
2921 * 1. Allocated
2922 * Same as last example, (CPU, CPU)
2923 * 2. Mapped to GTT
2924 * Nothing changes (assertions find that it is not in the GPU)
2925 * 3. Read/written by GPU
2926 * execbuffer calls set_domain (RENDER, RENDER)
2927 * flush_domains gets CPU
2928 * invalidate_domains gets GPU
2929 * clflush (obj)
2930 * MI_FLUSH and drm_agp_chipset_flush
2931 * 4. set_domain (CPU, CPU)
2932 * flush_domains gets GPU
2933 * invalidate_domains gets CPU
2934 * wait_rendering (obj) to make sure all drawing is complete.
2935 * This will include an MI_FLUSH to get the data from GPU
2936 * to memory
2937 * clflush (obj) to invalidate the CPU cache
2938 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2939 * 5. Read/written by CPU
2940 * cache lines are loaded and dirtied
2941 * 6. Read written by GPU
2942 * Same as last GPU access
2943 *
2944 * Case 3: The constant buffer
2945 *
2946 * 1. Allocated
2947 * 2. Written by CPU
2948 * 3. Read by GPU
2949 * 4. Updated (written) by CPU again
2950 * 5. Read by GPU
2951 *
2952 * 1. Allocated
2953 * (CPU, CPU)
2954 * 2. Written by CPU
2955 * (CPU, CPU)
2956 * 3. Read by GPU
2957 * (CPU+RENDER, 0)
2958 * flush_domains = CPU
2959 * invalidate_domains = RENDER
2960 * clflush (obj)
2961 * MI_FLUSH
2962 * drm_agp_chipset_flush
2963 * 4. Updated (written) by CPU again
2964 * (CPU, CPU)
2965 * flush_domains = 0 (no previous write domain)
2966 * invalidate_domains = 0 (no new read domains)
2967 * 5. Read by GPU
2968 * (CPU+RENDER, 0)
2969 * flush_domains = CPU
2970 * invalidate_domains = RENDER
2971 * clflush (obj)
2972 * MI_FLUSH
2973 * drm_agp_chipset_flush
2974 */
c0d90829 2975static void
8b0e378a 2976i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 2977{
2978 struct drm_device *dev = obj->dev;
2979 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2980 uint32_t invalidate_domains = 0;
2981 uint32_t flush_domains = 0;
1c5d22f7 2982 uint32_t old_read_domains;
e47c68e9 2983
8b0e378a
EA		 2984 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2985 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 2986
652c393a
JB		 2987 intel_mark_busy(dev, obj);
2988
673a394b
EA		 2989#if WATCH_BUF
2990 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2991 __func__, obj,
8b0e378a
EA		 2992 obj->read_domains, obj->pending_read_domains,
2993 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 2994#endif
2995 /*
2996 * If the object isn't moving to a new write domain,
2997 * let the object stay in multiple read domains
2998 */
8b0e378a
EA		 2999 if (obj->pending_write_domain == 0)
3000 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3001 else
3002 obj_priv->dirty = 1;
3003
3004 /*
3005 * Flush the current write domain if
3006 * the new read domains don't match. Invalidate
3007 * any read domains which differ from the old
3008 * write domain
3009 */
8b0e378a
EA		 3010 if (obj->write_domain &&
3011 obj->write_domain != obj->pending_read_domains) {
673a394b 3012 flush_domains |= obj->write_domain;
8b0e378a
EA		 3013 invalidate_domains |=
3014 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3015 }
3016 /*
3017 * Invalidate any read caches which may have
3018 * stale data. That is, any new read domains.
3019 */
8b0e378a 3020 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3021 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3022#if WATCH_BUF
3023 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3024 __func__, flush_domains, invalidate_domains);
3025#endif
673a394b
EA		 3026 i915_gem_clflush_object(obj);
3027 }
3028
1c5d22f7
CW		 3029 old_read_domains = obj->read_domains;
3030
efbeed96
EA		 3031 /* The actual obj->write_domain will be updated with
3032 * pending_write_domain after we emit the accumulated flush for all
3033 * of our domain changes in execbuffers (which clears objects'
3034 * write_domains). So if we have a current write domain that we
3035 * aren't changing, set pending_write_domain to that.
3036 */
3037 if (flush_domains == 0 && obj->pending_write_domain == 0)
3038 obj->pending_write_domain = obj->write_domain;
8b0e378a 3039 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3040
3041 dev->invalidate_domains |= invalidate_domains;
3042 dev->flush_domains |= flush_domains;
3043#if WATCH_BUF
3044 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3045 __func__,
3046 obj->read_domains, obj->write_domain,
3047 dev->invalidate_domains, dev->flush_domains);
3048#endif
1c5d22f7
CW		 3049
3050 trace_i915_gem_object_change_domain(obj,
3051 old_read_domains,
3052 obj->write_domain);
673a394b
EA		 3053}
3054
3055/**
e47c68e9 3056 * Moves the object from a partially CPU read to a full one.
673a394b 3057 *
e47c68e9
EA		 3058 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3059 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3060 */
e47c68e9
EA		 3061static void
3062i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b
EA		 3063{
3064 struct drm_i915_gem_object *obj_priv = obj->driver_private;
673a394b 3065
e47c68e9
EA		 3066 if (!obj_priv->page_cpu_valid)
3067 return;
3068
3069 /* If we're partially in the CPU read domain, finish moving it in.
3070 */
3071 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3072 int i;
3073
3074 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3075 if (obj_priv->page_cpu_valid[i])
3076 continue;
856fa198 3077 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3078 }
e47c68e9
EA		 3079 }
3080
3081 /* Free the page_cpu_valid mappings which are now stale, whether
3082 * or not we've got I915_GEM_DOMAIN_CPU.
3083 */
9a298b2a 3084 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3085 obj_priv->page_cpu_valid = NULL;
3086}
3087
3088/**
3089 * Set the CPU read domain on a range of the object.
3090 *
3091 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3092 * not entirely valid. The page_cpu_valid member of the object flags which
3093 * pages have been flushed, and will be respected by
3094 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3095 * of the whole object.
3096 *
3097 * This function returns when the move is complete, including waiting on
3098 * flushes to occur.
3099 */
3100static int
3101i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3102 uint64_t offset, uint64_t size)
3103{
3104 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1c5d22f7 3105 uint32_t old_read_domains;
e47c68e9 3106 int i, ret;
673a394b 3107
e47c68e9
EA		 3108 if (offset == 0 && size == obj->size)
3109 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3110
e47c68e9
EA		 3111 i915_gem_object_flush_gpu_write_domain(obj);
3112 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3113 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3114 if (ret != 0)
6a47baa6 3115 return ret;
e47c68e9
EA		 3116 i915_gem_object_flush_gtt_write_domain(obj);
3117
3118 /* If we're already fully in the CPU read domain, we're done. */
3119 if (obj_priv->page_cpu_valid == NULL &&
3120 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3121 return 0;
673a394b 3122
e47c68e9
EA		 3123 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3124 * newly adding I915_GEM_DOMAIN_CPU
3125 */
673a394b 3126 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3127 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3128 GFP_KERNEL);
e47c68e9
EA		 3129 if (obj_priv->page_cpu_valid == NULL)
3130 return -ENOMEM;
3131 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3132 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3133
3134 /* Flush the cache on any pages that are still invalid from the CPU's
3135 * perspective.
3136 */
e47c68e9
EA		 3137 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3138 i++) {
673a394b
EA		 3139 if (obj_priv->page_cpu_valid[i])
3140 continue;
3141
856fa198 3142 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3143
3144 obj_priv->page_cpu_valid[i] = 1;
3145 }
3146
e47c68e9
EA		 3147 /* It should now be out of any other write domains, and we can update
3148 * the domain values for our changes.
3149 */
3150 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3151
1c5d22f7 3152 old_read_domains = obj->read_domains;
e47c68e9
EA		 3153 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3154
1c5d22f7
CW		 3155 trace_i915_gem_object_change_domain(obj,
3156 old_read_domains,
3157 obj->write_domain);
3158
673a394b
EA		 3159 return 0;
3160}
3161
673a394b
EA		 3162/**
3163 * Pin an object to the GTT and evaluate the relocations landing in it.
3164 */
3165static int
3166i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3167 struct drm_file *file_priv,
40a5f0de
EA		 3168 struct drm_i915_gem_exec_object *entry,
3169 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3170{
3171 struct drm_device *dev = obj->dev;
0839ccb8 3172 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3173 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3174 int i, ret;
0839ccb8 3175 void __iomem *reloc_page;
673a394b
EA		 3176
3177 /* Choose the GTT offset for our buffer and put it there. */
3178 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3179 if (ret)
3180 return ret;
3181
3182 entry->offset = obj_priv->gtt_offset;
3183
673a394b
EA		 3184 /* Apply the relocations, using the GTT aperture to avoid cache
3185 * flushing requirements.
3186 */
3187 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3188 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3189 struct drm_gem_object *target_obj;
3190 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3191 uint32_t reloc_val, reloc_offset;
3192 uint32_t __iomem *reloc_entry;
673a394b 3193
673a394b 3194 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3195 reloc->target_handle);
673a394b
EA		 3196 if (target_obj == NULL) {
3197 i915_gem_object_unpin(obj);
3198 return -EBADF;
3199 }
3200 target_obj_priv = target_obj->driver_private;
3201
8542a0bb
CW		 3202#if WATCH_RELOC
3203 DRM_INFO("%s: obj %p offset %08x target %d "
3204 "read %08x write %08x gtt %08x "
3205 "presumed %08x delta %08x\n",
3206 __func__,
3207 obj,
3208 (int) reloc->offset,
3209 (int) reloc->target_handle,
3210 (int) reloc->read_domains,
3211 (int) reloc->write_domain,
3212 (int) target_obj_priv->gtt_offset,
3213 (int) reloc->presumed_offset,
3214 reloc->delta);
3215#endif
3216
673a394b
EA		 3217 /* The target buffer should have appeared before us in the
3218 * exec_object list, so it should have a GTT space bound by now.
3219 */
3220 if (target_obj_priv->gtt_space == NULL) {
3221 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3222 reloc->target_handle);
673a394b
EA		 3223 drm_gem_object_unreference(target_obj);
3224 i915_gem_object_unpin(obj);
3225 return -EINVAL;
3226 }
3227
8542a0bb 3228 /* Validate that the target is in a valid r/w GPU domain */
40a5f0de
EA		 3229 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3230 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3231 DRM_ERROR("reloc with read/write CPU domains: "
3232 "obj %p target %d offset %d "
3233 "read %08x write %08x",
40a5f0de
EA		 3234 obj, reloc->target_handle,
3235 (int) reloc->offset,
3236 reloc->read_domains,
3237 reloc->write_domain);
491152b8
CW		 3238 drm_gem_object_unreference(target_obj);
3239 i915_gem_object_unpin(obj);
e47c68e9
EA		 3240 return -EINVAL;
3241 }
40a5f0de
EA		 3242 if (reloc->write_domain && target_obj->pending_write_domain &&
3243 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3244 DRM_ERROR("Write domain conflict: "
3245 "obj %p target %d offset %d "
3246 "new %08x old %08x\n",
40a5f0de
EA		 3247 obj, reloc->target_handle,
3248 (int) reloc->offset,
3249 reloc->write_domain,
673a394b
EA		 3250 target_obj->pending_write_domain);
3251 drm_gem_object_unreference(target_obj);
3252 i915_gem_object_unpin(obj);
3253 return -EINVAL;
3254 }
3255
40a5f0de
EA		 3256 target_obj->pending_read_domains |= reloc->read_domains;
3257 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3258
3259 /* If the relocation already has the right value in it, no
3260 * more work needs to be done.
3261 */
40a5f0de 3262 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3263 drm_gem_object_unreference(target_obj);
3264 continue;
3265 }
3266
8542a0bb
CW		 3267 /* Check that the relocation address is valid... */
3268 if (reloc->offset > obj->size - 4) {
3269 DRM_ERROR("Relocation beyond object bounds: "
3270 "obj %p target %d offset %d size %d.\n",
3271 obj, reloc->target_handle,
3272 (int) reloc->offset, (int) obj->size);
3273 drm_gem_object_unreference(target_obj);
3274 i915_gem_object_unpin(obj);
3275 return -EINVAL;
3276 }
3277 if (reloc->offset & 3) {
3278 DRM_ERROR("Relocation not 4-byte aligned: "
3279 "obj %p target %d offset %d.\n",
3280 obj, reloc->target_handle,
3281 (int) reloc->offset);
3282 drm_gem_object_unreference(target_obj);
3283 i915_gem_object_unpin(obj);
3284 return -EINVAL;
3285 }
3286
3287 /* and points to somewhere within the target object. */
3288 if (reloc->delta >= target_obj->size) {
3289 DRM_ERROR("Relocation beyond target object bounds: "
3290 "obj %p target %d delta %d size %d.\n",
3291 obj, reloc->target_handle,
3292 (int) reloc->delta, (int) target_obj->size);
3293 drm_gem_object_unreference(target_obj);
3294 i915_gem_object_unpin(obj);
3295 return -EINVAL;
3296 }
3297
2ef7eeaa
EA		 3298 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3299 if (ret != 0) {
3300 drm_gem_object_unreference(target_obj);
3301 i915_gem_object_unpin(obj);
3302 return -EINVAL;
673a394b
EA		 3303 }
3304
3305 /* Map the page containing the relocation we're going to
3306 * perform.
3307 */
40a5f0de 3308 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3309 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3310 (reloc_offset &
3311 ~(PAGE_SIZE - 1)));
3043c60c 3312 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3313 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3314 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3315
3316#if WATCH_BUF
3317 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3318 obj, (unsigned int) reloc->offset,
673a394b
EA		 3319 readl(reloc_entry), reloc_val);
3320#endif
3321 writel(reloc_val, reloc_entry);
0839ccb8 3322 io_mapping_unmap_atomic(reloc_page);
673a394b 3323
40a5f0de
EA		 3324 /* The updated presumed offset for this entry will be
3325 * copied back out to the user.
673a394b 3326 */
40a5f0de 3327 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3328
3329 drm_gem_object_unreference(target_obj);
3330 }
3331
673a394b
EA		 3332#if WATCH_BUF
3333 if (0)
3334 i915_gem_dump_object(obj, 128, __func__, ~0);
3335#endif
3336 return 0;
3337}
3338
3339/** Dispatch a batchbuffer to the ring
3340 */
3341static int
3342i915_dispatch_gem_execbuffer(struct drm_device *dev,
3343 struct drm_i915_gem_execbuffer *exec,
201361a5 3344 struct drm_clip_rect *cliprects,
673a394b
EA		 3345 uint64_t exec_offset)
3346{
3347 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3348 int nbox = exec->num_cliprects;
3349 int i = 0, count;
83d60795 3350 uint32_t exec_start, exec_len;
673a394b
EA		 3351 RING_LOCALS;
3352
3353 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3354 exec_len = (uint32_t) exec->batch_len;
3355
1c5d22f7
CW		 3356 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno);
3357
673a394b
EA		 3358 count = nbox ? nbox : 1;
3359
3360 for (i = 0; i < count; i++) {
3361 if (i < nbox) {
201361a5 3362 int ret = i915_emit_box(dev, cliprects, i,
673a394b
EA		 3363 exec->DR1, exec->DR4);
3364 if (ret)
3365 return ret;
3366 }
3367
3368 if (IS_I830(dev) || IS_845G(dev)) {
3369 BEGIN_LP_RING(4);
3370 OUT_RING(MI_BATCH_BUFFER);
3371 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3372 OUT_RING(exec_start + exec_len - 4);
3373 OUT_RING(0);
3374 ADVANCE_LP_RING();
3375 } else {
3376 BEGIN_LP_RING(2);
3377 if (IS_I965G(dev)) {
3378 OUT_RING(MI_BATCH_BUFFER_START |
3379 (2 << 6) |
3380 MI_BATCH_NON_SECURE_I965);
3381 OUT_RING(exec_start);
3382 } else {
3383 OUT_RING(MI_BATCH_BUFFER_START |
3384 (2 << 6));
3385 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3386 }
3387 ADVANCE_LP_RING();
3388 }
3389 }
3390
3391 /* XXX breadcrumb */
3392 return 0;
3393}
3394
3395/* Throttle our rendering by waiting until the ring has completed our requests
3396 * emitted over 20 msec ago.
3397 *
b962442e
EA		 3398 * Note that if we were to use the current jiffies each time around the loop,
3399 * we wouldn't escape the function with any frames outstanding if the time to
3400 * render a frame was over 20ms.
3401 *
673a394b
EA		 3402 * This should get us reasonable parallelism between CPU and GPU but also
3403 * relatively low latency when blocking on a particular request to finish.
3404 */
3405static int
3406i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3407{
3408 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3409 int ret = 0;
b962442e 3410 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3411
3412 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3413 while (!list_empty(&i915_file_priv->mm.request_list)) {
3414 struct drm_i915_gem_request *request;
3415
3416 request = list_first_entry(&i915_file_priv->mm.request_list,
3417 struct drm_i915_gem_request,
3418 client_list);
3419
3420 if (time_after_eq(request->emitted_jiffies, recent_enough))
3421 break;
3422
3423 ret = i915_wait_request(dev, request->seqno);
3424 if (ret != 0)
3425 break;
3426 }
673a394b 3427 mutex_unlock(&dev->struct_mutex);
b962442e 3428
673a394b
EA		 3429 return ret;
3430}
3431
40a5f0de
EA		 3432static int
3433i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3434 uint32_t buffer_count,
3435 struct drm_i915_gem_relocation_entry **relocs)
3436{
3437 uint32_t reloc_count = 0, reloc_index = 0, i;
3438 int ret;
3439
3440 *relocs = NULL;
3441 for (i = 0; i < buffer_count; i++) {
3442 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3443 return -EINVAL;
3444 reloc_count += exec_list[i].relocation_count;
3445 }
3446
8e7d2b2c 3447 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
40a5f0de
EA		 3448 if (*relocs == NULL)
3449 return -ENOMEM;
3450
3451 for (i = 0; i < buffer_count; i++) {
3452 struct drm_i915_gem_relocation_entry __user *user_relocs;
3453
3454 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3455
3456 ret = copy_from_user(&(*relocs)[reloc_index],
3457 user_relocs,
3458 exec_list[i].relocation_count *
3459 sizeof(**relocs));
3460 if (ret != 0) {
8e7d2b2c 3461 drm_free_large(*relocs);
40a5f0de 3462 *relocs = NULL;
2bc43b5c 3463 return -EFAULT;
40a5f0de
EA		 3464 }
3465
3466 reloc_index += exec_list[i].relocation_count;
3467 }
3468
2bc43b5c 3469 return 0;
40a5f0de
EA		 3470}
3471
3472static int
3473i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3474 uint32_t buffer_count,
3475 struct drm_i915_gem_relocation_entry *relocs)
3476{
3477 uint32_t reloc_count = 0, i;
2bc43b5c 3478 int ret = 0;
40a5f0de
EA		 3479
3480 for (i = 0; i < buffer_count; i++) {
3481 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3482 int unwritten;
40a5f0de
EA		 3483
3484 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3485
2bc43b5c
FM		 3486 unwritten = copy_to_user(user_relocs,
3487 &relocs[reloc_count],
3488 exec_list[i].relocation_count *
3489 sizeof(*relocs));
3490
3491 if (unwritten) {
3492 ret = -EFAULT;
3493 goto err;
40a5f0de
EA		 3494 }
3495
3496 reloc_count += exec_list[i].relocation_count;
3497 }
3498
2bc43b5c 3499err:
8e7d2b2c 3500 drm_free_large(relocs);
40a5f0de
EA		 3501
3502 return ret;
3503}
3504
83d60795
CW		 3505static int
3506i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3507 uint64_t exec_offset)
3508{
3509 uint32_t exec_start, exec_len;
3510
3511 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3512 exec_len = (uint32_t) exec->batch_len;
3513
3514 if ((exec_start | exec_len) & 0x7)
3515 return -EINVAL;
3516
3517 if (!exec_start)
3518 return -EINVAL;
3519
3520 return 0;
3521}
3522
673a394b
EA		 3523int
3524i915_gem_execbuffer(struct drm_device *dev, void *data,
3525 struct drm_file *file_priv)
3526{
3527 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3528 struct drm_i915_gem_execbuffer *args = data;
3529 struct drm_i915_gem_exec_object *exec_list = NULL;
3530 struct drm_gem_object **object_list = NULL;
3531 struct drm_gem_object *batch_obj;
b70d11da 3532 struct drm_i915_gem_object *obj_priv;
201361a5 3533 struct drm_clip_rect *cliprects = NULL;
40a5f0de
EA		 3534 struct drm_i915_gem_relocation_entry *relocs;
3535 int ret, ret2, i, pinned = 0;
673a394b 3536 uint64_t exec_offset;
40a5f0de 3537 uint32_t seqno, flush_domains, reloc_index;
ac94a962 3538 int pin_tries;
673a394b
EA		 3539
3540#if WATCH_EXEC
3541 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3542 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3543#endif
3544
4f481ed2
EA		 3545 if (args->buffer_count < 1) {
3546 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3547 return -EINVAL;
3548 }
673a394b 3549 /* Copy in the exec list from userland */
8e7d2b2c
JB		 3550 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3551 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
673a394b
EA		 3552 if (exec_list == NULL || object_list == NULL) {
3553 DRM_ERROR("Failed to allocate exec or object list "
3554 "for %d buffers\n",
3555 args->buffer_count);
3556 ret = -ENOMEM;
3557 goto pre_mutex_err;
3558 }
3559 ret = copy_from_user(exec_list,
3560 (struct drm_i915_relocation_entry __user *)
3561 (uintptr_t) args->buffers_ptr,
3562 sizeof(*exec_list) * args->buffer_count);
3563 if (ret != 0) {
3564 DRM_ERROR("copy %d exec entries failed %d\n",
3565 args->buffer_count, ret);
3566 goto pre_mutex_err;
3567 }
3568
201361a5 3569 if (args->num_cliprects != 0) {
9a298b2a
EA		 3570 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3571 GFP_KERNEL);
201361a5
EA		 3572 if (cliprects == NULL)
3573 goto pre_mutex_err;
3574
3575 ret = copy_from_user(cliprects,
3576 (struct drm_clip_rect __user *)
3577 (uintptr_t) args->cliprects_ptr,
3578 sizeof(*cliprects) * args->num_cliprects);
3579 if (ret != 0) {
3580 DRM_ERROR("copy %d cliprects failed: %d\n",
3581 args->num_cliprects, ret);
3582 goto pre_mutex_err;
3583 }
3584 }
3585
40a5f0de
EA		 3586 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3587 &relocs);
3588 if (ret != 0)
3589 goto pre_mutex_err;
3590
673a394b
EA		 3591 mutex_lock(&dev->struct_mutex);
3592
3593 i915_verify_inactive(dev, __FILE__, __LINE__);
3594
ba1234d1 3595 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 3596 DRM_ERROR("Execbuf while wedged\n");
3597 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3598 ret = -EIO;
3599 goto pre_mutex_err;
673a394b
EA		 3600 }
3601
3602 if (dev_priv->mm.suspended) {
3603 DRM_ERROR("Execbuf while VT-switched.\n");
3604 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3605 ret = -EBUSY;
3606 goto pre_mutex_err;
673a394b
EA		 3607 }
3608
ac94a962 3609 /* Look up object handles */
673a394b
EA		 3610 for (i = 0; i < args->buffer_count; i++) {
3611 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3612 exec_list[i].handle);
3613 if (object_list[i] == NULL) {
3614 DRM_ERROR("Invalid object handle %d at index %d\n",
3615 exec_list[i].handle, i);
3616 ret = -EBADF;
3617 goto err;
3618 }
b70d11da
KH		 3619
3620 obj_priv = object_list[i]->driver_private;
3621 if (obj_priv->in_execbuffer) {
3622 DRM_ERROR("Object %p appears more than once in object list\n",
3623 object_list[i]);
3624 ret = -EBADF;
3625 goto err;
3626 }
3627 obj_priv->in_execbuffer = true;
ac94a962 3628 }
673a394b 3629
ac94a962
KP		 3630 /* Pin and relocate */
3631 for (pin_tries = 0; ; pin_tries++) {
3632 ret = 0;
40a5f0de
EA		 3633 reloc_index = 0;
3634
ac94a962
KP		 3635 for (i = 0; i < args->buffer_count; i++) {
3636 object_list[i]->pending_read_domains = 0;
3637 object_list[i]->pending_write_domain = 0;
3638 ret = i915_gem_object_pin_and_relocate(object_list[i],
3639 file_priv,
40a5f0de
EA		 3640 &exec_list[i],
3641 &relocs[reloc_index]);
ac94a962
KP		 3642 if (ret)
3643 break;
3644 pinned = i + 1;
40a5f0de 3645 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3646 }
3647 /* success */
3648 if (ret == 0)
3649 break;
3650
3651 /* error other than GTT full, or we've already tried again */
2939e1f5 3652 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3653 if (ret != -ERESTARTSYS) {
3654 unsigned long long total_size = 0;
3655 for (i = 0; i < args->buffer_count; i++)
3656 total_size += object_list[i]->size;
3657 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3658 pinned+1, args->buffer_count,
3659 total_size, ret);
3660 DRM_ERROR("%d objects [%d pinned], "
3661 "%d object bytes [%d pinned], "
3662 "%d/%d gtt bytes\n",
3663 atomic_read(&dev->object_count),
3664 atomic_read(&dev->pin_count),
3665 atomic_read(&dev->object_memory),
3666 atomic_read(&dev->pin_memory),
3667 atomic_read(&dev->gtt_memory),
3668 dev->gtt_total);
3669 }
673a394b
EA		 3670 goto err;
3671 }
ac94a962
KP		 3672
3673 /* unpin all of our buffers */
3674 for (i = 0; i < pinned; i++)
3675 i915_gem_object_unpin(object_list[i]);
b1177636 3676 pinned = 0;
ac94a962
KP		 3677
3678 /* evict everyone we can from the aperture */
3679 ret = i915_gem_evict_everything(dev);
07f73f69 3680 if (ret && ret != -ENOSPC)
ac94a962 3681 goto err;
673a394b
EA		 3682 }
3683
3684 /* Set the pending read domains for the batch buffer to COMMAND */
3685 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3686 if (batch_obj->pending_write_domain) {
3687 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3688 ret = -EINVAL;
3689 goto err;
3690 }
3691 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3692
83d60795
CW		 3693 /* Sanity check the batch buffer, prior to moving objects */
3694 exec_offset = exec_list[args->buffer_count - 1].offset;
3695 ret = i915_gem_check_execbuffer (args, exec_offset);
3696 if (ret != 0) {
3697 DRM_ERROR("execbuf with invalid offset/length\n");
3698 goto err;
3699 }
3700
673a394b
EA		 3701 i915_verify_inactive(dev, __FILE__, __LINE__);
3702
646f0f6e
KP		 3703 /* Zero the global flush/invalidate flags. These
3704 * will be modified as new domains are computed
3705 * for each object
3706 */
3707 dev->invalidate_domains = 0;
3708 dev->flush_domains = 0;
3709
673a394b
EA		 3710 for (i = 0; i < args->buffer_count; i++) {
3711 struct drm_gem_object *obj = object_list[i];
673a394b 3712
646f0f6e 3713 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3714 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3715 }
3716
3717 i915_verify_inactive(dev, __FILE__, __LINE__);
3718
646f0f6e
KP		 3719 if (dev->invalidate_domains | dev->flush_domains) {
3720#if WATCH_EXEC
3721 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3722 __func__,
3723 dev->invalidate_domains,
3724 dev->flush_domains);
3725#endif
3726 i915_gem_flush(dev,
3727 dev->invalidate_domains,
3728 dev->flush_domains);
3729 if (dev->flush_domains)
b962442e
EA		 3730 (void)i915_add_request(dev, file_priv,
3731 dev->flush_domains);
646f0f6e 3732 }
673a394b 3733
efbeed96
EA		 3734 for (i = 0; i < args->buffer_count; i++) {
3735 struct drm_gem_object *obj = object_list[i];
1c5d22f7 3736 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3737
3738 obj->write_domain = obj->pending_write_domain;
1c5d22f7
CW		 3739 trace_i915_gem_object_change_domain(obj,
3740 obj->read_domains,
3741 old_write_domain);
efbeed96
EA		 3742 }
3743
673a394b
EA		 3744 i915_verify_inactive(dev, __FILE__, __LINE__);
3745
3746#if WATCH_COHERENCY
3747 for (i = 0; i < args->buffer_count; i++) {
3748 i915_gem_object_check_coherency(object_list[i],
3749 exec_list[i].handle);
3750 }
3751#endif
3752
673a394b 3753#if WATCH_EXEC
6911a9b8 3754 i915_gem_dump_object(batch_obj,
673a394b
EA		 3755 args->batch_len,
3756 __func__,
3757 ~0);
3758#endif
3759
673a394b 3760 /* Exec the batchbuffer */
201361a5 3761 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
673a394b
EA		 3762 if (ret) {
3763 DRM_ERROR("dispatch failed %d\n", ret);
3764 goto err;
3765 }
3766
3767 /*
3768 * Ensure that the commands in the batch buffer are
3769 * finished before the interrupt fires
3770 */
3771 flush_domains = i915_retire_commands(dev);
3772
3773 i915_verify_inactive(dev, __FILE__, __LINE__);
3774
3775 /*
3776 * Get a seqno representing the execution of the current buffer,
3777 * which we can wait on. We would like to mitigate these interrupts,
3778 * likely by only creating seqnos occasionally (so that we have
3779 * *some* interrupts representing completion of buffers that we can
3780 * wait on when trying to clear up gtt space).
3781 */
b962442e 3782 seqno = i915_add_request(dev, file_priv, flush_domains);
673a394b 3783 BUG_ON(seqno == 0);
673a394b
EA		 3784 for (i = 0; i < args->buffer_count; i++) {
3785 struct drm_gem_object *obj = object_list[i];
673a394b 3786
ce44b0ea 3787 i915_gem_object_move_to_active(obj, seqno);
673a394b
EA		 3788#if WATCH_LRU
3789 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3790#endif
3791 }
3792#if WATCH_LRU
3793 i915_dump_lru(dev, __func__);
3794#endif
3795
3796 i915_verify_inactive(dev, __FILE__, __LINE__);
3797
673a394b 3798err:
aad87dff
JL		 3799 for (i = 0; i < pinned; i++)
3800 i915_gem_object_unpin(object_list[i]);
3801
b70d11da
KH		 3802 for (i = 0; i < args->buffer_count; i++) {
3803 if (object_list[i]) {
3804 obj_priv = object_list[i]->driver_private;
3805 obj_priv->in_execbuffer = false;
3806 }
aad87dff 3807 drm_gem_object_unreference(object_list[i]);
b70d11da 3808 }
673a394b 3809
673a394b
EA		 3810 mutex_unlock(&dev->struct_mutex);
3811
a35f2e2b
RD		 3812 if (!ret) {
3813 /* Copy the new buffer offsets back to the user's exec list. */
3814 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3815 (uintptr_t) args->buffers_ptr,
3816 exec_list,
3817 sizeof(*exec_list) * args->buffer_count);
2bc43b5c
FM		 3818 if (ret) {
3819 ret = -EFAULT;
a35f2e2b
RD		 3820 DRM_ERROR("failed to copy %d exec entries "
3821 "back to user (%d)\n",
3822 args->buffer_count, ret);
2bc43b5c 3823 }
a35f2e2b
RD		 3824 }
3825
40a5f0de
EA		 3826 /* Copy the updated relocations out regardless of current error
3827 * state. Failure to update the relocs would mean that the next
3828 * time userland calls execbuf, it would do so with presumed offset
3829 * state that didn't match the actual object state.
3830 */
3831 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3832 relocs);
3833 if (ret2 != 0) {
3834 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3835
3836 if (ret == 0)
3837 ret = ret2;
3838 }
3839
673a394b 3840pre_mutex_err:
8e7d2b2c
JB		 3841 drm_free_large(object_list);
3842 drm_free_large(exec_list);
9a298b2a 3843 kfree(cliprects);
673a394b
EA		 3844
3845 return ret;
3846}
3847
3848int
3849i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3850{
3851 struct drm_device *dev = obj->dev;
3852 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3853 int ret;
3854
3855 i915_verify_inactive(dev, __FILE__, __LINE__);
3856 if (obj_priv->gtt_space == NULL) {
3857 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3858 if (ret != 0) {
9bb2d6f9 3859 if (ret != -EBUSY && ret != -ERESTARTSYS)
0fce81e3 3860 DRM_ERROR("Failure to bind: %d\n", ret);
673a394b
EA		 3861 return ret;
3862 }
22c344e9
CW		 3863 }
3864 /*
3865 * Pre-965 chips need a fence register set up in order to
3866 * properly handle tiled surfaces.
3867 */
a09ba7fa 3868 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 3869 ret = i915_gem_object_get_fence_reg(obj);
22c344e9
CW		 3870 if (ret != 0) {
3871 if (ret != -EBUSY && ret != -ERESTARTSYS)
3872 DRM_ERROR("Failure to install fence: %d\n",
3873 ret);
3874 return ret;
3875 }
673a394b
EA		 3876 }
3877 obj_priv->pin_count++;
3878
3879 /* If the object is not active and not pending a flush,
3880 * remove it from the inactive list
3881 */
3882 if (obj_priv->pin_count == 1) {
3883 atomic_inc(&dev->pin_count);
3884 atomic_add(obj->size, &dev->pin_memory);
3885 if (!obj_priv->active &&
21d509e3 3886 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 3887 !list_empty(&obj_priv->list))
3888 list_del_init(&obj_priv->list);
3889 }
3890 i915_verify_inactive(dev, __FILE__, __LINE__);
3891
3892 return 0;
3893}
3894
3895void
3896i915_gem_object_unpin(struct drm_gem_object *obj)
3897{
3898 struct drm_device *dev = obj->dev;
3899 drm_i915_private_t *dev_priv = dev->dev_private;
3900 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3901
3902 i915_verify_inactive(dev, __FILE__, __LINE__);
3903 obj_priv->pin_count--;
3904 BUG_ON(obj_priv->pin_count < 0);
3905 BUG_ON(obj_priv->gtt_space == NULL);
3906
3907 /* If the object is no longer pinned, and is
3908 * neither active nor being flushed, then stick it on
3909 * the inactive list
3910 */
3911 if (obj_priv->pin_count == 0) {
3912 if (!obj_priv->active &&
21d509e3 3913 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 3914 list_move_tail(&obj_priv->list,
3915 &dev_priv->mm.inactive_list);
3916 atomic_dec(&dev->pin_count);
3917 atomic_sub(obj->size, &dev->pin_memory);
3918 }
3919 i915_verify_inactive(dev, __FILE__, __LINE__);
3920}
3921
3922int
3923i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3924 struct drm_file *file_priv)
3925{
3926 struct drm_i915_gem_pin *args = data;
3927 struct drm_gem_object *obj;
3928 struct drm_i915_gem_object *obj_priv;
3929 int ret;
3930
3931 mutex_lock(&dev->struct_mutex);
3932
3933 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3934 if (obj == NULL) {
3935 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3936 args->handle);
3937 mutex_unlock(&dev->struct_mutex);
3938 return -EBADF;
3939 }
3940 obj_priv = obj->driver_private;
3941
3ef94daa
CW		 3942 if (obj_priv->madv == I915_MADV_DONTNEED) {
3943 DRM_ERROR("Attempting to pin a I915_MADV_DONTNEED buffer\n");
3944 drm_gem_object_unreference(obj);
3945 mutex_unlock(&dev->struct_mutex);
3946 return -EINVAL;
3947 }
3948
79e53945
JB		 3949 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3950 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3951 args->handle);
96dec61d 3952 drm_gem_object_unreference(obj);
673a394b 3953 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 3954 return -EINVAL;
3955 }
3956
3957 obj_priv->user_pin_count++;
3958 obj_priv->pin_filp = file_priv;
3959 if (obj_priv->user_pin_count == 1) {
3960 ret = i915_gem_object_pin(obj, args->alignment);
3961 if (ret != 0) {
3962 drm_gem_object_unreference(obj);
3963 mutex_unlock(&dev->struct_mutex);
3964 return ret;
3965 }
673a394b
EA		 3966 }
3967
3968 /* XXX - flush the CPU caches for pinned objects
3969 * as the X server doesn't manage domains yet
3970 */
e47c68e9 3971 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 3972 args->offset = obj_priv->gtt_offset;
3973 drm_gem_object_unreference(obj);
3974 mutex_unlock(&dev->struct_mutex);
3975
3976 return 0;
3977}
3978
3979int
3980i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3981 struct drm_file *file_priv)
3982{
3983 struct drm_i915_gem_pin *args = data;
3984 struct drm_gem_object *obj;
79e53945 3985 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 3986
3987 mutex_lock(&dev->struct_mutex);
3988
3989 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3990 if (obj == NULL) {
3991 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3992 args->handle);
3993 mutex_unlock(&dev->struct_mutex);
3994 return -EBADF;
3995 }
3996
79e53945
JB		 3997 obj_priv = obj->driver_private;
3998 if (obj_priv->pin_filp != file_priv) {
3999 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4000 args->handle);
4001 drm_gem_object_unreference(obj);
4002 mutex_unlock(&dev->struct_mutex);
4003 return -EINVAL;
4004 }
4005 obj_priv->user_pin_count--;
4006 if (obj_priv->user_pin_count == 0) {
4007 obj_priv->pin_filp = NULL;
4008 i915_gem_object_unpin(obj);
4009 }
673a394b
EA		 4010
4011 drm_gem_object_unreference(obj);
4012 mutex_unlock(&dev->struct_mutex);
4013 return 0;
4014}
4015
4016int
4017i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4018 struct drm_file *file_priv)
4019{
4020 struct drm_i915_gem_busy *args = data;
4021 struct drm_gem_object *obj;
4022 struct drm_i915_gem_object *obj_priv;
4023
673a394b
EA		 4024 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4025 if (obj == NULL) {
4026 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4027 args->handle);
673a394b
EA		 4028 return -EBADF;
4029 }
4030
b1ce786c 4031 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4032 /* Update the active list for the hardware's current position.
4033 * Otherwise this only updates on a delayed timer or when irqs are
4034 * actually unmasked, and our working set ends up being larger than
4035 * required.
4036 */
4037 i915_gem_retire_requests(dev);
4038
673a394b 4039 obj_priv = obj->driver_private;
c4de0a5d
EA		 4040 /* Don't count being on the flushing list against the object being
4041 * done. Otherwise, a buffer left on the flushing list but not getting
4042 * flushed (because nobody's flushing that domain) won't ever return
4043 * unbusy and get reused by libdrm's bo cache. The other expected
4044 * consumer of this interface, OpenGL's occlusion queries, also specs
4045 * that the objects get unbusy "eventually" without any interference.
4046 */
4047 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4048
4049 drm_gem_object_unreference(obj);
4050 mutex_unlock(&dev->struct_mutex);
4051 return 0;
4052}
4053
4054int
4055i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4056 struct drm_file *file_priv)
4057{
4058 return i915_gem_ring_throttle(dev, file_priv);
4059}
4060
3ef94daa
CW		 4061int
4062i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4063 struct drm_file *file_priv)
4064{
4065 struct drm_i915_gem_madvise *args = data;
4066 struct drm_gem_object *obj;
4067 struct drm_i915_gem_object *obj_priv;
4068
4069 switch (args->madv) {
4070 case I915_MADV_DONTNEED:
4071 case I915_MADV_WILLNEED:
4072 break;
4073 default:
4074 return -EINVAL;
4075 }
4076
4077 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4078 if (obj == NULL) {
4079 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4080 args->handle);
4081 return -EBADF;
4082 }
4083
4084 mutex_lock(&dev->struct_mutex);
4085 obj_priv = obj->driver_private;
4086
4087 if (obj_priv->pin_count) {
4088 drm_gem_object_unreference(obj);
4089 mutex_unlock(&dev->struct_mutex);
4090
4091 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4092 return -EINVAL;
4093 }
4094
4095 obj_priv->madv = args->madv;
4096 args->retained = obj_priv->gtt_space != NULL;
4097
4098 drm_gem_object_unreference(obj);
4099 mutex_unlock(&dev->struct_mutex);
4100
4101 return 0;
4102}
4103
673a394b
EA		 4104int i915_gem_init_object(struct drm_gem_object *obj)
4105{
4106 struct drm_i915_gem_object *obj_priv;
4107
9a298b2a 4108 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
673a394b
EA		 4109 if (obj_priv == NULL)
4110 return -ENOMEM;
4111
4112 /*
4113 * We've just allocated pages from the kernel,
4114 * so they've just been written by the CPU with
4115 * zeros. They'll need to be clflushed before we
4116 * use them with the GPU.
4117 */
4118 obj->write_domain = I915_GEM_DOMAIN_CPU;
4119 obj->read_domains = I915_GEM_DOMAIN_CPU;
4120
ba1eb1d8
KP		 4121 obj_priv->agp_type = AGP_USER_MEMORY;
4122
673a394b
EA		 4123 obj->driver_private = obj_priv;
4124 obj_priv->obj = obj;
de151cf6 4125 obj_priv->fence_reg = I915_FENCE_REG_NONE;
673a394b 4126 INIT_LIST_HEAD(&obj_priv->list);
a09ba7fa 4127 INIT_LIST_HEAD(&obj_priv->fence_list);
3ef94daa 4128 obj_priv->madv = I915_MADV_WILLNEED;
de151cf6 4129
1c5d22f7
CW		 4130 trace_i915_gem_object_create(obj);
4131
673a394b
EA		 4132 return 0;
4133}
4134
4135void i915_gem_free_object(struct drm_gem_object *obj)
4136{
de151cf6 4137 struct drm_device *dev = obj->dev;
673a394b
EA		 4138 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4139
1c5d22f7
CW		 4140 trace_i915_gem_object_destroy(obj);
4141
673a394b
EA		 4142 while (obj_priv->pin_count > 0)
4143 i915_gem_object_unpin(obj);
4144
71acb5eb
DA		 4145 if (obj_priv->phys_obj)
4146 i915_gem_detach_phys_object(dev, obj);
4147
673a394b
EA		 4148 i915_gem_object_unbind(obj);
4149
7e616158
CW		 4150 if (obj_priv->mmap_offset)
4151 i915_gem_free_mmap_offset(obj);
de151cf6 4152
9a298b2a 4153 kfree(obj_priv->page_cpu_valid);
280b713b 4154 kfree(obj_priv->bit_17);
9a298b2a 4155 kfree(obj->driver_private);
673a394b
EA		 4156}
4157
ab5ee576 4158/** Unbinds all inactive objects. */
673a394b 4159static int
ab5ee576 4160i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4161{
ab5ee576 4162 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4163
ab5ee576
CW		 4164 while (!list_empty(&dev_priv->mm.inactive_list)) {
4165 struct drm_gem_object *obj;
4166 int ret;
673a394b 4167
ab5ee576
CW		 4168 obj = list_first_entry(&dev_priv->mm.inactive_list,
4169 struct drm_i915_gem_object,
4170 list)->obj;
673a394b
EA		 4171
4172 ret = i915_gem_object_unbind(obj);
4173 if (ret != 0) {
ab5ee576 4174 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4175 return ret;
4176 }
4177 }
4178
673a394b
EA		 4179 return 0;
4180}
4181
5669fcac 4182int
673a394b
EA		 4183i915_gem_idle(struct drm_device *dev)
4184{
4185 drm_i915_private_t *dev_priv = dev->dev_private;
4186 uint32_t seqno, cur_seqno, last_seqno;
4187 int stuck, ret;
4188
6dbe2772
KP		 4189 mutex_lock(&dev->struct_mutex);
4190
4191 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4192 mutex_unlock(&dev->struct_mutex);
673a394b 4193 return 0;
6dbe2772 4194 }
673a394b
EA		 4195
4196 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4197 * We need to replace this with a semaphore, or something.
4198 */
4199 dev_priv->mm.suspended = 1;
f65d9421 4200 del_timer(&dev_priv->hangcheck_timer);
673a394b 4201
6dbe2772
KP		 4202 /* Cancel the retire work handler, wait for it to finish if running
4203 */
4204 mutex_unlock(&dev->struct_mutex);
4205 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4206 mutex_lock(&dev->struct_mutex);
4207
673a394b
EA		 4208 i915_kernel_lost_context(dev);
4209
4210 /* Flush the GPU along with all non-CPU write domains
4211 */
21d509e3
CW		 4212 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4213 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
673a394b
EA		 4214
4215 if (seqno == 0) {
4216 mutex_unlock(&dev->struct_mutex);
4217 return -ENOMEM;
4218 }
4219
4220 dev_priv->mm.waiting_gem_seqno = seqno;
4221 last_seqno = 0;
4222 stuck = 0;
4223 for (;;) {
4224 cur_seqno = i915_get_gem_seqno(dev);
4225 if (i915_seqno_passed(cur_seqno, seqno))
4226 break;
4227 if (last_seqno == cur_seqno) {
4228 if (stuck++ > 100) {
4229 DRM_ERROR("hardware wedged\n");
ba1234d1 4230 atomic_set(&dev_priv->mm.wedged, 1);
673a394b
EA		 4231 DRM_WAKEUP(&dev_priv->irq_queue);
4232 break;
4233 }
4234 }
4235 msleep(10);
4236 last_seqno = cur_seqno;
4237 }
4238 dev_priv->mm.waiting_gem_seqno = 0;
4239
4240 i915_gem_retire_requests(dev);
4241
5e118f41 4242 spin_lock(&dev_priv->mm.active_list_lock);
ba1234d1 4243 if (!atomic_read(&dev_priv->mm.wedged)) {
28dfe52a
EA		 4244 /* Active and flushing should now be empty as we've
4245 * waited for a sequence higher than any pending execbuffer
4246 */
4247 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4248 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4249 /* Request should now be empty as we've also waited
4250 * for the last request in the list
4251 */
4252 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4253 }
673a394b 4254
28dfe52a
EA		 4255 /* Empty the active and flushing lists to inactive. If there's
4256 * anything left at this point, it means that we're wedged and
4257 * nothing good's going to happen by leaving them there. So strip
4258 * the GPU domains and just stuff them onto inactive.
673a394b 4259 */
28dfe52a 4260 while (!list_empty(&dev_priv->mm.active_list)) {
1c5d22f7
CW		 4261 struct drm_gem_object *obj;
4262 uint32_t old_write_domain;
4263
4264 obj = list_first_entry(&dev_priv->mm.active_list,
4265 struct drm_i915_gem_object,
4266 list)->obj;
4267 old_write_domain = obj->write_domain;
4268 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4269 i915_gem_object_move_to_inactive(obj);
4270
4271 trace_i915_gem_object_change_domain(obj,
4272 obj->read_domains,
4273 old_write_domain);
28dfe52a 4274 }
5e118f41 4275 spin_unlock(&dev_priv->mm.active_list_lock);
28dfe52a
EA		 4276
4277 while (!list_empty(&dev_priv->mm.flushing_list)) {
1c5d22f7
CW		 4278 struct drm_gem_object *obj;
4279 uint32_t old_write_domain;
4280
4281 obj = list_first_entry(&dev_priv->mm.flushing_list,
4282 struct drm_i915_gem_object,
4283 list)->obj;
4284 old_write_domain = obj->write_domain;
4285 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4286 i915_gem_object_move_to_inactive(obj);
4287
4288 trace_i915_gem_object_change_domain(obj,
4289 obj->read_domains,
4290 old_write_domain);
28dfe52a
EA		 4291 }
4292
4293
4294 /* Move all inactive buffers out of the GTT. */
ab5ee576 4295 ret = i915_gem_evict_from_inactive_list(dev);
28dfe52a 4296 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
6dbe2772
KP		 4297 if (ret) {
4298 mutex_unlock(&dev->struct_mutex);
673a394b 4299 return ret;
6dbe2772 4300 }
673a394b 4301
6dbe2772
KP		 4302 i915_gem_cleanup_ringbuffer(dev);
4303 mutex_unlock(&dev->struct_mutex);
4304
673a394b
EA		 4305 return 0;
4306}
4307
4308static int
4309i915_gem_init_hws(struct drm_device *dev)
4310{
4311 drm_i915_private_t *dev_priv = dev->dev_private;
4312 struct drm_gem_object *obj;
4313 struct drm_i915_gem_object *obj_priv;
4314 int ret;
4315
4316 /* If we need a physical address for the status page, it's already
4317 * initialized at driver load time.
4318 */
4319 if (!I915_NEED_GFX_HWS(dev))
4320 return 0;
4321
4322 obj = drm_gem_object_alloc(dev, 4096);
4323 if (obj == NULL) {
4324 DRM_ERROR("Failed to allocate status page\n");
4325 return -ENOMEM;
4326 }
4327 obj_priv = obj->driver_private;
ba1eb1d8 4328 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
673a394b
EA		 4329
4330 ret = i915_gem_object_pin(obj, 4096);
4331 if (ret != 0) {
4332 drm_gem_object_unreference(obj);
4333 return ret;
4334 }
4335
4336 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
673a394b 4337
856fa198 4338 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
ba1eb1d8 4339 if (dev_priv->hw_status_page == NULL) {
673a394b
EA		 4340 DRM_ERROR("Failed to map status page.\n");
4341 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3eb2ee77 4342 i915_gem_object_unpin(obj);
673a394b
EA		 4343 drm_gem_object_unreference(obj);
4344 return -EINVAL;
4345 }
4346 dev_priv->hws_obj = obj;
673a394b
EA		 4347 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4348 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
ba1eb1d8 4349 I915_READ(HWS_PGA); /* posting read */
673a394b
EA		 4350 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4351
4352 return 0;
4353}
4354
85a7bb98
CW		 4355static void
4356i915_gem_cleanup_hws(struct drm_device *dev)
4357{
4358 drm_i915_private_t *dev_priv = dev->dev_private;
bab2d1f6
CW		 4359 struct drm_gem_object *obj;
4360 struct drm_i915_gem_object *obj_priv;
85a7bb98
CW		 4361
4362 if (dev_priv->hws_obj == NULL)
4363 return;
4364
bab2d1f6
CW		 4365 obj = dev_priv->hws_obj;
4366 obj_priv = obj->driver_private;
4367
856fa198 4368 kunmap(obj_priv->pages[0]);
85a7bb98
CW		 4369 i915_gem_object_unpin(obj);
4370 drm_gem_object_unreference(obj);
4371 dev_priv->hws_obj = NULL;
bab2d1f6 4372
85a7bb98
CW		 4373 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4374 dev_priv->hw_status_page = NULL;
4375
4376 /* Write high address into HWS_PGA when disabling. */
4377 I915_WRITE(HWS_PGA, 0x1ffff000);
4378}
4379
79e53945 4380int
673a394b
EA		 4381i915_gem_init_ringbuffer(struct drm_device *dev)
4382{
4383 drm_i915_private_t *dev_priv = dev->dev_private;
4384 struct drm_gem_object *obj;
4385 struct drm_i915_gem_object *obj_priv;
79e53945 4386 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
673a394b 4387 int ret;
50aa253d 4388 u32 head;
673a394b
EA		 4389
4390 ret = i915_gem_init_hws(dev);
4391 if (ret != 0)
4392 return ret;
4393
4394 obj = drm_gem_object_alloc(dev, 128 * 1024);
4395 if (obj == NULL) {
4396 DRM_ERROR("Failed to allocate ringbuffer\n");
85a7bb98 4397 i915_gem_cleanup_hws(dev);
673a394b
EA		 4398 return -ENOMEM;
4399 }
4400 obj_priv = obj->driver_private;
4401
4402 ret = i915_gem_object_pin(obj, 4096);
4403 if (ret != 0) {
4404 drm_gem_object_unreference(obj);
85a7bb98 4405 i915_gem_cleanup_hws(dev);
673a394b
EA		 4406 return ret;
4407 }
4408
4409 /* Set up the kernel mapping for the ring. */
79e53945 4410 ring->Size = obj->size;
673a394b 4411
79e53945
JB		 4412 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4413 ring->map.size = obj->size;
4414 ring->map.type = 0;
4415 ring->map.flags = 0;
4416 ring->map.mtrr = 0;
673a394b 4417
79e53945
JB		 4418 drm_core_ioremap_wc(&ring->map, dev);
4419 if (ring->map.handle == NULL) {
673a394b
EA		 4420 DRM_ERROR("Failed to map ringbuffer.\n");
4421 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
47ed185a 4422 i915_gem_object_unpin(obj);
673a394b 4423 drm_gem_object_unreference(obj);
85a7bb98 4424 i915_gem_cleanup_hws(dev);
673a394b
EA		 4425 return -EINVAL;
4426 }
79e53945
JB		 4427 ring->ring_obj = obj;
4428 ring->virtual_start = ring->map.handle;
673a394b
EA		 4429
4430 /* Stop the ring if it's running. */
4431 I915_WRITE(PRB0_CTL, 0);
673a394b 4432 I915_WRITE(PRB0_TAIL, 0);
50aa253d 4433 I915_WRITE(PRB0_HEAD, 0);
673a394b
EA		 4434
4435 /* Initialize the ring. */
4436 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
50aa253d
KP		 4437 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4438
4439 /* G45 ring initialization fails to reset head to zero */
4440 if (head != 0) {
4441 DRM_ERROR("Ring head not reset to zero "
4442 "ctl %08x head %08x tail %08x start %08x\n",
4443 I915_READ(PRB0_CTL),
4444 I915_READ(PRB0_HEAD),
4445 I915_READ(PRB0_TAIL),
4446 I915_READ(PRB0_START));
4447 I915_WRITE(PRB0_HEAD, 0);
4448
4449 DRM_ERROR("Ring head forced to zero "
4450 "ctl %08x head %08x tail %08x start %08x\n",
4451 I915_READ(PRB0_CTL),
4452 I915_READ(PRB0_HEAD),
4453 I915_READ(PRB0_TAIL),
4454 I915_READ(PRB0_START));
4455 }
4456
673a394b
EA		 4457 I915_WRITE(PRB0_CTL,
4458 ((obj->size - 4096) & RING_NR_PAGES) |
4459 RING_NO_REPORT |
4460 RING_VALID);
4461
50aa253d
KP		 4462 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4463
4464 /* If the head is still not zero, the ring is dead */
4465 if (head != 0) {
4466 DRM_ERROR("Ring initialization failed "
4467 "ctl %08x head %08x tail %08x start %08x\n",
4468 I915_READ(PRB0_CTL),
4469 I915_READ(PRB0_HEAD),
4470 I915_READ(PRB0_TAIL),
4471 I915_READ(PRB0_START));
4472 return -EIO;
4473 }
4474
673a394b 4475 /* Update our cache of the ring state */
79e53945
JB		 4476 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4477 i915_kernel_lost_context(dev);
4478 else {
4479 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4480 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4481 ring->space = ring->head - (ring->tail + 8);
4482 if (ring->space < 0)
4483 ring->space += ring->Size;
4484 }
673a394b
EA		 4485
4486 return 0;
4487}
4488
79e53945 4489void
673a394b
EA		 4490i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4491{
4492 drm_i915_private_t *dev_priv = dev->dev_private;
4493
4494 if (dev_priv->ring.ring_obj == NULL)
4495 return;
4496
4497 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4498
4499 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4500 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4501 dev_priv->ring.ring_obj = NULL;
4502 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4503
85a7bb98 4504 i915_gem_cleanup_hws(dev);
673a394b
EA		 4505}
4506
4507int
4508i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4509 struct drm_file *file_priv)
4510{
4511 drm_i915_private_t *dev_priv = dev->dev_private;
4512 int ret;
4513
79e53945
JB		 4514 if (drm_core_check_feature(dev, DRIVER_MODESET))
4515 return 0;
4516
ba1234d1 4517 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4518 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4519 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4520 }
4521
673a394b 4522 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4523 dev_priv->mm.suspended = 0;
4524
4525 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4526 if (ret != 0) {
4527 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4528 return ret;
d816f6ac 4529 }
9bb2d6f9 4530
5e118f41 4531 spin_lock(&dev_priv->mm.active_list_lock);
673a394b 4532 BUG_ON(!list_empty(&dev_priv->mm.active_list));
5e118f41
CW		 4533 spin_unlock(&dev_priv->mm.active_list_lock);
4534
673a394b
EA		 4535 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4536 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4537 BUG_ON(!list_empty(&dev_priv->mm.request_list));
673a394b 4538 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4539
4540 drm_irq_install(dev);
4541
673a394b
EA		 4542 return 0;
4543}
4544
4545int
4546i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4547 struct drm_file *file_priv)
4548{
4549 int ret;
4550
79e53945
JB		 4551 if (drm_core_check_feature(dev, DRIVER_MODESET))
4552 return 0;
4553
673a394b 4554 ret = i915_gem_idle(dev);
dbb19d30
KH		 4555 drm_irq_uninstall(dev);
4556
6dbe2772 4557 return ret;
673a394b
EA		 4558}
4559
4560void
4561i915_gem_lastclose(struct drm_device *dev)
4562{
4563 int ret;
673a394b 4564
e806b495
EA		 4565 if (drm_core_check_feature(dev, DRIVER_MODESET))
4566 return;
4567
6dbe2772
KP		 4568 ret = i915_gem_idle(dev);
4569 if (ret)
4570 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4571}
4572
4573void
4574i915_gem_load(struct drm_device *dev)
4575{
b5aa8a0f 4576 int i;
673a394b
EA		 4577 drm_i915_private_t *dev_priv = dev->dev_private;
4578
5e118f41 4579 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b
EA		 4580 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4581 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4582 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4583 INIT_LIST_HEAD(&dev_priv->mm.request_list);
a09ba7fa 4584 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
673a394b
EA		 4585 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4586 i915_gem_retire_work_handler);
4587 dev_priv->mm.next_gem_seqno = 1;
4588
31169714
CW		 4589 spin_lock(&shrink_list_lock);
4590 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4591 spin_unlock(&shrink_list_lock);
4592
de151cf6
JB		 4593 /* Old X drivers will take 0-2 for front, back, depth buffers */
4594 dev_priv->fence_reg_start = 3;
4595
0f973f27 4596 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4597 dev_priv->num_fence_regs = 16;
4598 else
4599 dev_priv->num_fence_regs = 8;
4600
b5aa8a0f
GH		 4601 /* Initialize fence registers to zero */
4602 if (IS_I965G(dev)) {
4603 for (i = 0; i < 16; i++)
4604 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4605 } else {
4606 for (i = 0; i < 8; i++)
4607 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4608 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4609 for (i = 0; i < 8; i++)
4610 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4611 }
4612
673a394b
EA		 4613 i915_gem_detect_bit_6_swizzle(dev);
4614}
71acb5eb
DA		 4615
4616/*
4617 * Create a physically contiguous memory object for this object
4618 * e.g. for cursor + overlay regs
4619 */
4620int i915_gem_init_phys_object(struct drm_device *dev,
4621 int id, int size)
4622{
4623 drm_i915_private_t *dev_priv = dev->dev_private;
4624 struct drm_i915_gem_phys_object *phys_obj;
4625 int ret;
4626
4627 if (dev_priv->mm.phys_objs[id - 1] || !size)
4628 return 0;
4629
9a298b2a 4630 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4631 if (!phys_obj)
4632 return -ENOMEM;
4633
4634 phys_obj->id = id;
4635
4636 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4637 if (!phys_obj->handle) {
4638 ret = -ENOMEM;
4639 goto kfree_obj;
4640 }
4641#ifdef CONFIG_X86
4642 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4643#endif
4644
4645 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4646
4647 return 0;
4648kfree_obj:
9a298b2a 4649 kfree(phys_obj);
71acb5eb
DA		 4650 return ret;
4651}
4652
4653void i915_gem_free_phys_object(struct drm_device *dev, int id)
4654{
4655 drm_i915_private_t *dev_priv = dev->dev_private;
4656 struct drm_i915_gem_phys_object *phys_obj;
4657
4658 if (!dev_priv->mm.phys_objs[id - 1])
4659 return;
4660
4661 phys_obj = dev_priv->mm.phys_objs[id - 1];
4662 if (phys_obj->cur_obj) {
4663 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4664 }
4665
4666#ifdef CONFIG_X86
4667 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4668#endif
4669 drm_pci_free(dev, phys_obj->handle);
4670 kfree(phys_obj);
4671 dev_priv->mm.phys_objs[id - 1] = NULL;
4672}
4673
4674void i915_gem_free_all_phys_object(struct drm_device *dev)
4675{
4676 int i;
4677
260883c8 4678 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4679 i915_gem_free_phys_object(dev, i);
4680}
4681
4682void i915_gem_detach_phys_object(struct drm_device *dev,
4683 struct drm_gem_object *obj)
4684{
4685 struct drm_i915_gem_object *obj_priv;
4686 int i;
4687 int ret;
4688 int page_count;
4689
4690 obj_priv = obj->driver_private;
4691 if (!obj_priv->phys_obj)
4692 return;
4693
856fa198 4694 ret = i915_gem_object_get_pages(obj);
71acb5eb
DA		 4695 if (ret)
4696 goto out;
4697
4698 page_count = obj->size / PAGE_SIZE;
4699
4700 for (i = 0; i < page_count; i++) {
856fa198 4701 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4702 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4703
4704 memcpy(dst, src, PAGE_SIZE);
4705 kunmap_atomic(dst, KM_USER0);
4706 }
856fa198 4707 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4708 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4709
4710 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4711out:
4712 obj_priv->phys_obj->cur_obj = NULL;
4713 obj_priv->phys_obj = NULL;
4714}
4715
4716int
4717i915_gem_attach_phys_object(struct drm_device *dev,
4718 struct drm_gem_object *obj, int id)
4719{
4720 drm_i915_private_t *dev_priv = dev->dev_private;
4721 struct drm_i915_gem_object *obj_priv;
4722 int ret = 0;
4723 int page_count;
4724 int i;
4725
4726 if (id > I915_MAX_PHYS_OBJECT)
4727 return -EINVAL;
4728
4729 obj_priv = obj->driver_private;
4730
4731 if (obj_priv->phys_obj) {
4732 if (obj_priv->phys_obj->id == id)
4733 return 0;
4734 i915_gem_detach_phys_object(dev, obj);
4735 }
4736
4737
4738 /* create a new object */
4739 if (!dev_priv->mm.phys_objs[id - 1]) {
4740 ret = i915_gem_init_phys_object(dev, id,
4741 obj->size);
4742 if (ret) {
aeb565df 4743 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4744 goto out;
4745 }
4746 }
4747
4748 /* bind to the object */
4749 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4750 obj_priv->phys_obj->cur_obj = obj;
4751
856fa198 4752 ret = i915_gem_object_get_pages(obj);
71acb5eb
DA		 4753 if (ret) {
4754 DRM_ERROR("failed to get page list\n");
4755 goto out;
4756 }
4757
4758 page_count = obj->size / PAGE_SIZE;
4759
4760 for (i = 0; i < page_count; i++) {
856fa198 4761 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4762 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4763
4764 memcpy(dst, src, PAGE_SIZE);
4765 kunmap_atomic(src, KM_USER0);
4766 }
4767
d78b47b9
CW		 4768 i915_gem_object_put_pages(obj);
4769
71acb5eb
DA		 4770 return 0;
4771out:
4772 return ret;
4773}
4774
4775static int
4776i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4777 struct drm_i915_gem_pwrite *args,
4778 struct drm_file *file_priv)
4779{
4780 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4781 void *obj_addr;
4782 int ret;
4783 char __user *user_data;
4784
4785 user_data = (char __user *) (uintptr_t) args->data_ptr;
4786 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4787
e08fb4f6 4788 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4789 ret = copy_from_user(obj_addr, user_data, args->size);
4790 if (ret)
4791 return -EFAULT;
4792
4793 drm_agp_chipset_flush(dev);
4794 return 0;
4795}
b962442e
EA		 4796
4797void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4798{
4799 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4800
4801 /* Clean up our request list when the client is going away, so that
4802 * later retire_requests won't dereference our soon-to-be-gone
4803 * file_priv.
4804 */
4805 mutex_lock(&dev->struct_mutex);
4806 while (!list_empty(&i915_file_priv->mm.request_list))
4807 list_del_init(i915_file_priv->mm.request_list.next);
4808 mutex_unlock(&dev->struct_mutex);
4809}
31169714
CW		 4810
4811/* Immediately discard the backing storage */
4812static void
4813i915_gem_object_truncate(struct drm_gem_object *obj)
4814{
4815 struct inode *inode;
4816
4817 inode = obj->filp->f_path.dentry->d_inode;
4818
4819 mutex_lock(&inode->i_mutex);
4820 truncate_inode_pages(inode->i_mapping, 0);
4821 mutex_unlock(&inode->i_mutex);
4822}
4823
31169714
CW		 4824static int
4825i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4826{
4827 drm_i915_private_t *dev_priv, *next_dev;
4828 struct drm_i915_gem_object *obj_priv, *next_obj;
4829 int cnt = 0;
4830 int would_deadlock = 1;
4831
4832 /* "fast-path" to count number of available objects */
4833 if (nr_to_scan == 0) {
4834 spin_lock(&shrink_list_lock);
4835 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4836 struct drm_device *dev = dev_priv->dev;
4837
4838 if (mutex_trylock(&dev->struct_mutex)) {
4839 list_for_each_entry(obj_priv,
4840 &dev_priv->mm.inactive_list,
4841 list)
4842 cnt++;
4843 mutex_unlock(&dev->struct_mutex);
4844 }
4845 }
4846 spin_unlock(&shrink_list_lock);
4847
4848 return (cnt / 100) * sysctl_vfs_cache_pressure;
4849 }
4850
4851 spin_lock(&shrink_list_lock);
4852
4853 /* first scan for clean buffers */
4854 list_for_each_entry_safe(dev_priv, next_dev,
4855 &shrink_list, mm.shrink_list) {
4856 struct drm_device *dev = dev_priv->dev;
4857
4858 if (! mutex_trylock(&dev->struct_mutex))
4859 continue;
4860
4861 spin_unlock(&shrink_list_lock);
4862
4863 i915_gem_retire_requests(dev);
4864
4865 list_for_each_entry_safe(obj_priv, next_obj,
4866 &dev_priv->mm.inactive_list,
4867 list) {
4868 if (i915_gem_object_is_purgeable(obj_priv)) {
4869 struct drm_gem_object *obj = obj_priv->obj;
4870 i915_gem_object_unbind(obj);
4871 i915_gem_object_truncate(obj);
4872
4873 if (--nr_to_scan <= 0)
4874 break;
4875 }
4876 }
4877
4878 spin_lock(&shrink_list_lock);
4879 mutex_unlock(&dev->struct_mutex);
4880
4881 if (nr_to_scan <= 0)
4882 break;
4883 }
4884
4885 /* second pass, evict/count anything still on the inactive list */
4886 list_for_each_entry_safe(dev_priv, next_dev,
4887 &shrink_list, mm.shrink_list) {
4888 struct drm_device *dev = dev_priv->dev;
4889
4890 if (! mutex_trylock(&dev->struct_mutex))
4891 continue;
4892
4893 spin_unlock(&shrink_list_lock);
4894
4895 list_for_each_entry_safe(obj_priv, next_obj,
4896 &dev_priv->mm.inactive_list,
4897 list) {
4898 if (nr_to_scan > 0) {
4899 struct drm_gem_object *obj = obj_priv->obj;
4900 i915_gem_object_unbind(obj);
4901 if (i915_gem_object_is_purgeable(obj_priv))
4902 i915_gem_object_truncate(obj);
4903
4904 nr_to_scan--;
4905 } else
4906 cnt++;
4907 }
4908
4909 spin_lock(&shrink_list_lock);
4910 mutex_unlock(&dev->struct_mutex);
4911
4912 would_deadlock = 0;
4913 }
4914
4915 spin_unlock(&shrink_list_lock);
4916
4917 if (would_deadlock)
4918 return -1;
4919 else if (cnt > 0)
4920 return (cnt / 100) * sysctl_vfs_cache_pressure;
4921 else
4922 return 0;
4923}
4924
4925static struct shrinker shrinker = {
4926 .shrink = i915_gem_shrink,
4927 .seeks = DEFAULT_SEEKS,
4928};
4929
4930__init void
4931i915_gem_shrinker_init(void)
4932{
4933 register_shrinker(&shrinker);
4934}
4935
4936__exit void
4937i915_gem_shrinker_exit(void)
4938{
4939 unregister_shrinker(&shrinker);
4940}
Linux kernel - Deliverables
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