Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 JB |
53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
54 | unsigned alignment); | |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
5cdf5881 CW |
61 | static int |
62 | i915_gem_object_get_pages(struct drm_gem_object *obj, | |
63 | gfp_t gfpmask); | |
64 | ||
65 | static void | |
66 | i915_gem_object_put_pages(struct drm_gem_object *obj); | |
67 | ||
31169714 CW |
68 | static LIST_HEAD(shrink_list); |
69 | static DEFINE_SPINLOCK(shrink_list_lock); | |
70 | ||
73aa808f CW |
71 | /* some bookkeeping */ |
72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
73 | size_t size) | |
74 | { | |
75 | dev_priv->mm.object_count++; | |
76 | dev_priv->mm.object_memory += size; | |
77 | } | |
78 | ||
79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
80 | size_t size) | |
81 | { | |
82 | dev_priv->mm.object_count--; | |
83 | dev_priv->mm.object_memory -= size; | |
84 | } | |
85 | ||
86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
87 | size_t size) | |
88 | { | |
89 | dev_priv->mm.gtt_count++; | |
90 | dev_priv->mm.gtt_memory += size; | |
91 | } | |
92 | ||
93 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
96 | dev_priv->mm.gtt_count--; | |
97 | dev_priv->mm.gtt_memory -= size; | |
98 | } | |
99 | ||
100 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
101 | size_t size) | |
102 | { | |
103 | dev_priv->mm.pin_count++; | |
104 | dev_priv->mm.pin_memory += size; | |
105 | } | |
106 | ||
107 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
108 | size_t size) | |
109 | { | |
110 | dev_priv->mm.pin_count--; | |
111 | dev_priv->mm.pin_memory -= size; | |
112 | } | |
113 | ||
30dbf0c0 CW |
114 | int |
115 | i915_gem_check_is_wedged(struct drm_device *dev) | |
116 | { | |
117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
118 | struct completion *x = &dev_priv->error_completion; | |
119 | unsigned long flags; | |
120 | int ret; | |
121 | ||
122 | if (!atomic_read(&dev_priv->mm.wedged)) | |
123 | return 0; | |
124 | ||
125 | ret = wait_for_completion_interruptible(x); | |
126 | if (ret) | |
127 | return ret; | |
128 | ||
129 | /* Success, we reset the GPU! */ | |
130 | if (!atomic_read(&dev_priv->mm.wedged)) | |
131 | return 0; | |
132 | ||
133 | /* GPU is hung, bump the completion count to account for | |
134 | * the token we just consumed so that we never hit zero and | |
135 | * end up waiting upon a subsequent completion event that | |
136 | * will never happen. | |
137 | */ | |
138 | spin_lock_irqsave(&x->wait.lock, flags); | |
139 | x->done++; | |
140 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
141 | return -EIO; | |
142 | } | |
143 | ||
76c1dec1 CW |
144 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
145 | { | |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | int ret; | |
148 | ||
149 | ret = i915_gem_check_is_wedged(dev); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
153 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
154 | if (ret) | |
155 | return ret; | |
156 | ||
157 | if (atomic_read(&dev_priv->mm.wedged)) { | |
158 | mutex_unlock(&dev->struct_mutex); | |
159 | return -EAGAIN; | |
160 | } | |
161 | ||
23bc5982 | 162 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
163 | return 0; |
164 | } | |
30dbf0c0 | 165 | |
7d1c4804 CW |
166 | static inline bool |
167 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
168 | { | |
169 | return obj_priv->gtt_space && | |
170 | !obj_priv->active && | |
171 | obj_priv->pin_count == 0; | |
172 | } | |
173 | ||
73aa808f CW |
174 | int i915_gem_do_init(struct drm_device *dev, |
175 | unsigned long start, | |
79e53945 | 176 | unsigned long end) |
673a394b EA |
177 | { |
178 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 179 | |
79e53945 JB |
180 | if (start >= end || |
181 | (start & (PAGE_SIZE - 1)) != 0 || | |
182 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
183 | return -EINVAL; |
184 | } | |
185 | ||
79e53945 JB |
186 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
187 | end - start); | |
673a394b | 188 | |
73aa808f | 189 | dev_priv->mm.gtt_total = end - start; |
79e53945 JB |
190 | |
191 | return 0; | |
192 | } | |
673a394b | 193 | |
79e53945 JB |
194 | int |
195 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
196 | struct drm_file *file_priv) | |
197 | { | |
198 | struct drm_i915_gem_init *args = data; | |
199 | int ret; | |
200 | ||
201 | mutex_lock(&dev->struct_mutex); | |
202 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
203 | mutex_unlock(&dev->struct_mutex); |
204 | ||
79e53945 | 205 | return ret; |
673a394b EA |
206 | } |
207 | ||
5a125c3c EA |
208 | int |
209 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
210 | struct drm_file *file_priv) | |
211 | { | |
73aa808f | 212 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 213 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
214 | |
215 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
216 | return -ENODEV; | |
217 | ||
73aa808f CW |
218 | mutex_lock(&dev->struct_mutex); |
219 | args->aper_size = dev_priv->mm.gtt_total; | |
220 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
221 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
222 | |
223 | return 0; | |
224 | } | |
225 | ||
673a394b EA |
226 | |
227 | /** | |
228 | * Creates a new mm object and returns a handle to it. | |
229 | */ | |
230 | int | |
231 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
232 | struct drm_file *file_priv) | |
233 | { | |
234 | struct drm_i915_gem_create *args = data; | |
235 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
236 | int ret; |
237 | u32 handle; | |
673a394b EA |
238 | |
239 | args->size = roundup(args->size, PAGE_SIZE); | |
240 | ||
241 | /* Allocate the new object */ | |
ac52bc56 | 242 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
243 | if (obj == NULL) |
244 | return -ENOMEM; | |
245 | ||
246 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 247 | if (ret) { |
202f2fef CW |
248 | drm_gem_object_release(obj); |
249 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
250 | kfree(obj); | |
673a394b | 251 | return ret; |
1dfd9754 | 252 | } |
673a394b | 253 | |
202f2fef CW |
254 | /* drop reference from allocate - handle holds it now */ |
255 | drm_gem_object_unreference(obj); | |
256 | trace_i915_gem_object_create(obj); | |
257 | ||
1dfd9754 | 258 | args->handle = handle; |
673a394b EA |
259 | return 0; |
260 | } | |
261 | ||
eb01459f EA |
262 | static inline int |
263 | fast_shmem_read(struct page **pages, | |
264 | loff_t page_base, int page_offset, | |
265 | char __user *data, | |
266 | int length) | |
267 | { | |
b5e4feb6 | 268 | char *vaddr; |
4f27b75d | 269 | int ret; |
eb01459f | 270 | |
3e4d3af5 | 271 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
4f27b75d | 272 | ret = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
3e4d3af5 | 273 | kunmap_atomic(vaddr); |
eb01459f | 274 | |
4f27b75d | 275 | return ret; |
eb01459f EA |
276 | } |
277 | ||
280b713b EA |
278 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
279 | { | |
280 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 281 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
282 | |
283 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
284 | obj_priv->tiling_mode != I915_TILING_NONE; | |
285 | } | |
286 | ||
99a03df5 | 287 | static inline void |
40123c1f EA |
288 | slow_shmem_copy(struct page *dst_page, |
289 | int dst_offset, | |
290 | struct page *src_page, | |
291 | int src_offset, | |
292 | int length) | |
293 | { | |
294 | char *dst_vaddr, *src_vaddr; | |
295 | ||
99a03df5 CW |
296 | dst_vaddr = kmap(dst_page); |
297 | src_vaddr = kmap(src_page); | |
40123c1f EA |
298 | |
299 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
300 | ||
99a03df5 CW |
301 | kunmap(src_page); |
302 | kunmap(dst_page); | |
40123c1f EA |
303 | } |
304 | ||
99a03df5 | 305 | static inline void |
280b713b EA |
306 | slow_shmem_bit17_copy(struct page *gpu_page, |
307 | int gpu_offset, | |
308 | struct page *cpu_page, | |
309 | int cpu_offset, | |
310 | int length, | |
311 | int is_read) | |
312 | { | |
313 | char *gpu_vaddr, *cpu_vaddr; | |
314 | ||
315 | /* Use the unswizzled path if this page isn't affected. */ | |
316 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
317 | if (is_read) | |
318 | return slow_shmem_copy(cpu_page, cpu_offset, | |
319 | gpu_page, gpu_offset, length); | |
320 | else | |
321 | return slow_shmem_copy(gpu_page, gpu_offset, | |
322 | cpu_page, cpu_offset, length); | |
323 | } | |
324 | ||
99a03df5 CW |
325 | gpu_vaddr = kmap(gpu_page); |
326 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
327 | |
328 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
329 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
330 | */ | |
331 | while (length > 0) { | |
332 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
333 | int this_length = min(cacheline_end - gpu_offset, length); | |
334 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
335 | ||
336 | if (is_read) { | |
337 | memcpy(cpu_vaddr + cpu_offset, | |
338 | gpu_vaddr + swizzled_gpu_offset, | |
339 | this_length); | |
340 | } else { | |
341 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
342 | cpu_vaddr + cpu_offset, | |
343 | this_length); | |
344 | } | |
345 | cpu_offset += this_length; | |
346 | gpu_offset += this_length; | |
347 | length -= this_length; | |
348 | } | |
349 | ||
99a03df5 CW |
350 | kunmap(cpu_page); |
351 | kunmap(gpu_page); | |
280b713b EA |
352 | } |
353 | ||
eb01459f EA |
354 | /** |
355 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
356 | * from the backing pages of the object to the user's address space. On a | |
357 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
358 | */ | |
359 | static int | |
360 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
361 | struct drm_i915_gem_pread *args, | |
362 | struct drm_file *file_priv) | |
363 | { | |
23010e43 | 364 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
365 | ssize_t remain; |
366 | loff_t offset, page_base; | |
367 | char __user *user_data; | |
368 | int page_offset, page_length; | |
eb01459f EA |
369 | |
370 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
371 | remain = args->size; | |
372 | ||
23010e43 | 373 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
374 | offset = args->offset; |
375 | ||
376 | while (remain > 0) { | |
377 | /* Operation in this page | |
378 | * | |
379 | * page_base = page offset within aperture | |
380 | * page_offset = offset within page | |
381 | * page_length = bytes to copy for this page | |
382 | */ | |
383 | page_base = (offset & ~(PAGE_SIZE-1)); | |
384 | page_offset = offset & (PAGE_SIZE-1); | |
385 | page_length = remain; | |
386 | if ((page_offset + remain) > PAGE_SIZE) | |
387 | page_length = PAGE_SIZE - page_offset; | |
388 | ||
4f27b75d CW |
389 | if (fast_shmem_read(obj_priv->pages, |
390 | page_base, page_offset, | |
391 | user_data, page_length)) | |
392 | return -EFAULT; | |
eb01459f EA |
393 | |
394 | remain -= page_length; | |
395 | user_data += page_length; | |
396 | offset += page_length; | |
397 | } | |
398 | ||
4f27b75d | 399 | return 0; |
eb01459f EA |
400 | } |
401 | ||
07f73f69 CW |
402 | static int |
403 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
404 | { | |
405 | int ret; | |
406 | ||
4bdadb97 | 407 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
408 | |
409 | /* If we've insufficient memory to map in the pages, attempt | |
410 | * to make some space by throwing out some old buffers. | |
411 | */ | |
412 | if (ret == -ENOMEM) { | |
413 | struct drm_device *dev = obj->dev; | |
07f73f69 | 414 | |
0108a3ed DV |
415 | ret = i915_gem_evict_something(dev, obj->size, |
416 | i915_gem_get_gtt_alignment(obj)); | |
07f73f69 CW |
417 | if (ret) |
418 | return ret; | |
419 | ||
4bdadb97 | 420 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
421 | } |
422 | ||
423 | return ret; | |
424 | } | |
425 | ||
eb01459f EA |
426 | /** |
427 | * This is the fallback shmem pread path, which allocates temporary storage | |
428 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
429 | * can copy out of the object's backing pages while holding the struct mutex | |
430 | * and not take page faults. | |
431 | */ | |
432 | static int | |
433 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
434 | struct drm_i915_gem_pread *args, | |
435 | struct drm_file *file_priv) | |
436 | { | |
23010e43 | 437 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
438 | struct mm_struct *mm = current->mm; |
439 | struct page **user_pages; | |
440 | ssize_t remain; | |
441 | loff_t offset, pinned_pages, i; | |
442 | loff_t first_data_page, last_data_page, num_pages; | |
443 | int shmem_page_index, shmem_page_offset; | |
444 | int data_page_index, data_page_offset; | |
445 | int page_length; | |
446 | int ret; | |
447 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 448 | int do_bit17_swizzling; |
eb01459f EA |
449 | |
450 | remain = args->size; | |
451 | ||
452 | /* Pin the user pages containing the data. We can't fault while | |
453 | * holding the struct mutex, yet we want to hold it while | |
454 | * dereferencing the user data. | |
455 | */ | |
456 | first_data_page = data_ptr / PAGE_SIZE; | |
457 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
458 | num_pages = last_data_page - first_data_page + 1; | |
459 | ||
4f27b75d | 460 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
461 | if (user_pages == NULL) |
462 | return -ENOMEM; | |
463 | ||
4f27b75d | 464 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
465 | down_read(&mm->mmap_sem); |
466 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 467 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 468 | up_read(&mm->mmap_sem); |
4f27b75d | 469 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
470 | if (pinned_pages < num_pages) { |
471 | ret = -EFAULT; | |
4f27b75d | 472 | goto out; |
eb01459f EA |
473 | } |
474 | ||
4f27b75d CW |
475 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
476 | args->offset, | |
477 | args->size); | |
07f73f69 | 478 | if (ret) |
4f27b75d | 479 | goto out; |
eb01459f | 480 | |
4f27b75d | 481 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 482 | |
23010e43 | 483 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
484 | offset = args->offset; |
485 | ||
486 | while (remain > 0) { | |
487 | /* Operation in this page | |
488 | * | |
489 | * shmem_page_index = page number within shmem file | |
490 | * shmem_page_offset = offset within page in shmem file | |
491 | * data_page_index = page number in get_user_pages return | |
492 | * data_page_offset = offset with data_page_index page. | |
493 | * page_length = bytes to copy for this page | |
494 | */ | |
495 | shmem_page_index = offset / PAGE_SIZE; | |
496 | shmem_page_offset = offset & ~PAGE_MASK; | |
497 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
498 | data_page_offset = data_ptr & ~PAGE_MASK; | |
499 | ||
500 | page_length = remain; | |
501 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
502 | page_length = PAGE_SIZE - shmem_page_offset; | |
503 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
504 | page_length = PAGE_SIZE - data_page_offset; | |
505 | ||
280b713b | 506 | if (do_bit17_swizzling) { |
99a03df5 | 507 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 508 | shmem_page_offset, |
99a03df5 CW |
509 | user_pages[data_page_index], |
510 | data_page_offset, | |
511 | page_length, | |
512 | 1); | |
513 | } else { | |
514 | slow_shmem_copy(user_pages[data_page_index], | |
515 | data_page_offset, | |
516 | obj_priv->pages[shmem_page_index], | |
517 | shmem_page_offset, | |
518 | page_length); | |
280b713b | 519 | } |
eb01459f EA |
520 | |
521 | remain -= page_length; | |
522 | data_ptr += page_length; | |
523 | offset += page_length; | |
524 | } | |
525 | ||
4f27b75d | 526 | out: |
eb01459f EA |
527 | for (i = 0; i < pinned_pages; i++) { |
528 | SetPageDirty(user_pages[i]); | |
529 | page_cache_release(user_pages[i]); | |
530 | } | |
8e7d2b2c | 531 | drm_free_large(user_pages); |
eb01459f EA |
532 | |
533 | return ret; | |
534 | } | |
535 | ||
673a394b EA |
536 | /** |
537 | * Reads data from the object referenced by handle. | |
538 | * | |
539 | * On error, the contents of *data are undefined. | |
540 | */ | |
541 | int | |
542 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
543 | struct drm_file *file_priv) | |
544 | { | |
545 | struct drm_i915_gem_pread *args = data; | |
546 | struct drm_gem_object *obj; | |
547 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 548 | int ret = 0; |
673a394b | 549 | |
4f27b75d | 550 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 551 | if (ret) |
4f27b75d | 552 | return ret; |
673a394b EA |
553 | |
554 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1d7cfea1 CW |
555 | if (obj == NULL) { |
556 | ret = -ENOENT; | |
557 | goto unlock; | |
4f27b75d | 558 | } |
23010e43 | 559 | obj_priv = to_intel_bo(obj); |
673a394b | 560 | |
7dcd2499 CW |
561 | /* Bounds check source. */ |
562 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 563 | ret = -EINVAL; |
35b62a89 | 564 | goto out; |
ce9d419d CW |
565 | } |
566 | ||
35b62a89 CW |
567 | if (args->size == 0) |
568 | goto out; | |
569 | ||
ce9d419d CW |
570 | if (!access_ok(VERIFY_WRITE, |
571 | (char __user *)(uintptr_t)args->data_ptr, | |
572 | args->size)) { | |
573 | ret = -EFAULT; | |
35b62a89 | 574 | goto out; |
673a394b EA |
575 | } |
576 | ||
b5e4feb6 CW |
577 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
578 | args->size); | |
579 | if (ret) { | |
580 | ret = -EFAULT; | |
581 | goto out; | |
280b713b | 582 | } |
673a394b | 583 | |
4f27b75d CW |
584 | ret = i915_gem_object_get_pages_or_evict(obj); |
585 | if (ret) | |
586 | goto out; | |
587 | ||
588 | ret = i915_gem_object_set_cpu_read_domain_range(obj, | |
589 | args->offset, | |
590 | args->size); | |
591 | if (ret) | |
592 | goto out_put; | |
593 | ||
594 | ret = -EFAULT; | |
595 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
280b713b | 596 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
4f27b75d CW |
597 | if (ret == -EFAULT) |
598 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); | |
673a394b | 599 | |
4f27b75d CW |
600 | out_put: |
601 | i915_gem_object_put_pages(obj); | |
35b62a89 | 602 | out: |
4f27b75d | 603 | drm_gem_object_unreference(obj); |
1d7cfea1 | 604 | unlock: |
4f27b75d | 605 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 606 | return ret; |
673a394b EA |
607 | } |
608 | ||
0839ccb8 KP |
609 | /* This is the fast write path which cannot handle |
610 | * page faults in the source data | |
9b7530cc | 611 | */ |
0839ccb8 KP |
612 | |
613 | static inline int | |
614 | fast_user_write(struct io_mapping *mapping, | |
615 | loff_t page_base, int page_offset, | |
616 | char __user *user_data, | |
617 | int length) | |
9b7530cc | 618 | { |
9b7530cc | 619 | char *vaddr_atomic; |
0839ccb8 | 620 | unsigned long unwritten; |
9b7530cc | 621 | |
3e4d3af5 | 622 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
623 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
624 | user_data, length); | |
3e4d3af5 | 625 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 626 | return unwritten; |
0839ccb8 KP |
627 | } |
628 | ||
629 | /* Here's the write path which can sleep for | |
630 | * page faults | |
631 | */ | |
632 | ||
ab34c226 | 633 | static inline void |
3de09aa3 EA |
634 | slow_kernel_write(struct io_mapping *mapping, |
635 | loff_t gtt_base, int gtt_offset, | |
636 | struct page *user_page, int user_offset, | |
637 | int length) | |
0839ccb8 | 638 | { |
ab34c226 CW |
639 | char __iomem *dst_vaddr; |
640 | char *src_vaddr; | |
0839ccb8 | 641 | |
ab34c226 CW |
642 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
643 | src_vaddr = kmap(user_page); | |
644 | ||
645 | memcpy_toio(dst_vaddr + gtt_offset, | |
646 | src_vaddr + user_offset, | |
647 | length); | |
648 | ||
649 | kunmap(user_page); | |
650 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
651 | } |
652 | ||
40123c1f EA |
653 | static inline int |
654 | fast_shmem_write(struct page **pages, | |
655 | loff_t page_base, int page_offset, | |
656 | char __user *data, | |
657 | int length) | |
658 | { | |
b5e4feb6 | 659 | char *vaddr; |
fbd5a26d | 660 | int ret; |
40123c1f | 661 | |
3e4d3af5 | 662 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
fbd5a26d | 663 | ret = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
3e4d3af5 | 664 | kunmap_atomic(vaddr); |
40123c1f | 665 | |
fbd5a26d | 666 | return ret; |
40123c1f EA |
667 | } |
668 | ||
3de09aa3 EA |
669 | /** |
670 | * This is the fast pwrite path, where we copy the data directly from the | |
671 | * user into the GTT, uncached. | |
672 | */ | |
673a394b | 673 | static int |
3de09aa3 EA |
674 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
675 | struct drm_i915_gem_pwrite *args, | |
676 | struct drm_file *file_priv) | |
673a394b | 677 | { |
23010e43 | 678 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 679 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 680 | ssize_t remain; |
0839ccb8 | 681 | loff_t offset, page_base; |
673a394b | 682 | char __user *user_data; |
0839ccb8 | 683 | int page_offset, page_length; |
673a394b EA |
684 | |
685 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
686 | remain = args->size; | |
673a394b | 687 | |
23010e43 | 688 | obj_priv = to_intel_bo(obj); |
673a394b | 689 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
690 | |
691 | while (remain > 0) { | |
692 | /* Operation in this page | |
693 | * | |
0839ccb8 KP |
694 | * page_base = page offset within aperture |
695 | * page_offset = offset within page | |
696 | * page_length = bytes to copy for this page | |
673a394b | 697 | */ |
0839ccb8 KP |
698 | page_base = (offset & ~(PAGE_SIZE-1)); |
699 | page_offset = offset & (PAGE_SIZE-1); | |
700 | page_length = remain; | |
701 | if ((page_offset + remain) > PAGE_SIZE) | |
702 | page_length = PAGE_SIZE - page_offset; | |
703 | ||
0839ccb8 | 704 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
705 | * source page isn't available. Return the error and we'll |
706 | * retry in the slow path. | |
0839ccb8 | 707 | */ |
fbd5a26d CW |
708 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
709 | page_offset, user_data, page_length)) | |
710 | ||
711 | return -EFAULT; | |
673a394b | 712 | |
0839ccb8 KP |
713 | remain -= page_length; |
714 | user_data += page_length; | |
715 | offset += page_length; | |
673a394b | 716 | } |
673a394b | 717 | |
fbd5a26d | 718 | return 0; |
673a394b EA |
719 | } |
720 | ||
3de09aa3 EA |
721 | /** |
722 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
723 | * the memory and maps it using kmap_atomic for copying. | |
724 | * | |
725 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
726 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
727 | */ | |
3043c60c | 728 | static int |
3de09aa3 EA |
729 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
730 | struct drm_i915_gem_pwrite *args, | |
731 | struct drm_file *file_priv) | |
673a394b | 732 | { |
23010e43 | 733 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
734 | drm_i915_private_t *dev_priv = dev->dev_private; |
735 | ssize_t remain; | |
736 | loff_t gtt_page_base, offset; | |
737 | loff_t first_data_page, last_data_page, num_pages; | |
738 | loff_t pinned_pages, i; | |
739 | struct page **user_pages; | |
740 | struct mm_struct *mm = current->mm; | |
741 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 742 | int ret; |
3de09aa3 EA |
743 | uint64_t data_ptr = args->data_ptr; |
744 | ||
745 | remain = args->size; | |
746 | ||
747 | /* Pin the user pages containing the data. We can't fault while | |
748 | * holding the struct mutex, and all of the pwrite implementations | |
749 | * want to hold it while dereferencing the user data. | |
750 | */ | |
751 | first_data_page = data_ptr / PAGE_SIZE; | |
752 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
753 | num_pages = last_data_page - first_data_page + 1; | |
754 | ||
fbd5a26d | 755 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
756 | if (user_pages == NULL) |
757 | return -ENOMEM; | |
758 | ||
fbd5a26d | 759 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
760 | down_read(&mm->mmap_sem); |
761 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
762 | num_pages, 0, 0, user_pages, NULL); | |
763 | up_read(&mm->mmap_sem); | |
fbd5a26d | 764 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
765 | if (pinned_pages < num_pages) { |
766 | ret = -EFAULT; | |
767 | goto out_unpin_pages; | |
768 | } | |
673a394b | 769 | |
3de09aa3 EA |
770 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
771 | if (ret) | |
fbd5a26d | 772 | goto out_unpin_pages; |
3de09aa3 | 773 | |
23010e43 | 774 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
775 | offset = obj_priv->gtt_offset + args->offset; |
776 | ||
777 | while (remain > 0) { | |
778 | /* Operation in this page | |
779 | * | |
780 | * gtt_page_base = page offset within aperture | |
781 | * gtt_page_offset = offset within page in aperture | |
782 | * data_page_index = page number in get_user_pages return | |
783 | * data_page_offset = offset with data_page_index page. | |
784 | * page_length = bytes to copy for this page | |
785 | */ | |
786 | gtt_page_base = offset & PAGE_MASK; | |
787 | gtt_page_offset = offset & ~PAGE_MASK; | |
788 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
789 | data_page_offset = data_ptr & ~PAGE_MASK; | |
790 | ||
791 | page_length = remain; | |
792 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
793 | page_length = PAGE_SIZE - gtt_page_offset; | |
794 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
795 | page_length = PAGE_SIZE - data_page_offset; | |
796 | ||
ab34c226 CW |
797 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
798 | gtt_page_base, gtt_page_offset, | |
799 | user_pages[data_page_index], | |
800 | data_page_offset, | |
801 | page_length); | |
3de09aa3 EA |
802 | |
803 | remain -= page_length; | |
804 | offset += page_length; | |
805 | data_ptr += page_length; | |
806 | } | |
807 | ||
3de09aa3 EA |
808 | out_unpin_pages: |
809 | for (i = 0; i < pinned_pages; i++) | |
810 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 811 | drm_free_large(user_pages); |
3de09aa3 EA |
812 | |
813 | return ret; | |
814 | } | |
815 | ||
40123c1f EA |
816 | /** |
817 | * This is the fast shmem pwrite path, which attempts to directly | |
818 | * copy_from_user into the kmapped pages backing the object. | |
819 | */ | |
3043c60c | 820 | static int |
40123c1f EA |
821 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
822 | struct drm_i915_gem_pwrite *args, | |
823 | struct drm_file *file_priv) | |
673a394b | 824 | { |
23010e43 | 825 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
826 | ssize_t remain; |
827 | loff_t offset, page_base; | |
828 | char __user *user_data; | |
829 | int page_offset, page_length; | |
40123c1f EA |
830 | |
831 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
832 | remain = args->size; | |
673a394b | 833 | |
23010e43 | 834 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
835 | offset = args->offset; |
836 | obj_priv->dirty = 1; | |
837 | ||
838 | while (remain > 0) { | |
839 | /* Operation in this page | |
840 | * | |
841 | * page_base = page offset within aperture | |
842 | * page_offset = offset within page | |
843 | * page_length = bytes to copy for this page | |
844 | */ | |
845 | page_base = (offset & ~(PAGE_SIZE-1)); | |
846 | page_offset = offset & (PAGE_SIZE-1); | |
847 | page_length = remain; | |
848 | if ((page_offset + remain) > PAGE_SIZE) | |
849 | page_length = PAGE_SIZE - page_offset; | |
850 | ||
fbd5a26d | 851 | if (fast_shmem_write(obj_priv->pages, |
40123c1f | 852 | page_base, page_offset, |
fbd5a26d CW |
853 | user_data, page_length)) |
854 | return -EFAULT; | |
40123c1f EA |
855 | |
856 | remain -= page_length; | |
857 | user_data += page_length; | |
858 | offset += page_length; | |
859 | } | |
860 | ||
fbd5a26d | 861 | return 0; |
40123c1f EA |
862 | } |
863 | ||
864 | /** | |
865 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
866 | * the memory and maps it using kmap_atomic for copying. | |
867 | * | |
868 | * This avoids taking mmap_sem for faulting on the user's address while the | |
869 | * struct_mutex is held. | |
870 | */ | |
871 | static int | |
872 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
873 | struct drm_i915_gem_pwrite *args, | |
874 | struct drm_file *file_priv) | |
875 | { | |
23010e43 | 876 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
877 | struct mm_struct *mm = current->mm; |
878 | struct page **user_pages; | |
879 | ssize_t remain; | |
880 | loff_t offset, pinned_pages, i; | |
881 | loff_t first_data_page, last_data_page, num_pages; | |
882 | int shmem_page_index, shmem_page_offset; | |
883 | int data_page_index, data_page_offset; | |
884 | int page_length; | |
885 | int ret; | |
886 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 887 | int do_bit17_swizzling; |
40123c1f EA |
888 | |
889 | remain = args->size; | |
890 | ||
891 | /* Pin the user pages containing the data. We can't fault while | |
892 | * holding the struct mutex, and all of the pwrite implementations | |
893 | * want to hold it while dereferencing the user data. | |
894 | */ | |
895 | first_data_page = data_ptr / PAGE_SIZE; | |
896 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
897 | num_pages = last_data_page - first_data_page + 1; | |
898 | ||
4f27b75d | 899 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
900 | if (user_pages == NULL) |
901 | return -ENOMEM; | |
902 | ||
fbd5a26d | 903 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
904 | down_read(&mm->mmap_sem); |
905 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
906 | num_pages, 0, 0, user_pages, NULL); | |
907 | up_read(&mm->mmap_sem); | |
fbd5a26d | 908 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
909 | if (pinned_pages < num_pages) { |
910 | ret = -EFAULT; | |
fbd5a26d | 911 | goto out; |
673a394b EA |
912 | } |
913 | ||
fbd5a26d | 914 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 915 | if (ret) |
fbd5a26d | 916 | goto out; |
40123c1f | 917 | |
fbd5a26d | 918 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 919 | |
23010e43 | 920 | obj_priv = to_intel_bo(obj); |
673a394b | 921 | offset = args->offset; |
40123c1f | 922 | obj_priv->dirty = 1; |
673a394b | 923 | |
40123c1f EA |
924 | while (remain > 0) { |
925 | /* Operation in this page | |
926 | * | |
927 | * shmem_page_index = page number within shmem file | |
928 | * shmem_page_offset = offset within page in shmem file | |
929 | * data_page_index = page number in get_user_pages return | |
930 | * data_page_offset = offset with data_page_index page. | |
931 | * page_length = bytes to copy for this page | |
932 | */ | |
933 | shmem_page_index = offset / PAGE_SIZE; | |
934 | shmem_page_offset = offset & ~PAGE_MASK; | |
935 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
936 | data_page_offset = data_ptr & ~PAGE_MASK; | |
937 | ||
938 | page_length = remain; | |
939 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
940 | page_length = PAGE_SIZE - shmem_page_offset; | |
941 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
942 | page_length = PAGE_SIZE - data_page_offset; | |
943 | ||
280b713b | 944 | if (do_bit17_swizzling) { |
99a03df5 | 945 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
946 | shmem_page_offset, |
947 | user_pages[data_page_index], | |
948 | data_page_offset, | |
99a03df5 CW |
949 | page_length, |
950 | 0); | |
951 | } else { | |
952 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
953 | shmem_page_offset, | |
954 | user_pages[data_page_index], | |
955 | data_page_offset, | |
956 | page_length); | |
280b713b | 957 | } |
40123c1f EA |
958 | |
959 | remain -= page_length; | |
960 | data_ptr += page_length; | |
961 | offset += page_length; | |
673a394b EA |
962 | } |
963 | ||
fbd5a26d | 964 | out: |
40123c1f EA |
965 | for (i = 0; i < pinned_pages; i++) |
966 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 967 | drm_free_large(user_pages); |
673a394b | 968 | |
40123c1f | 969 | return ret; |
673a394b EA |
970 | } |
971 | ||
972 | /** | |
973 | * Writes data to the object referenced by handle. | |
974 | * | |
975 | * On error, the contents of the buffer that were to be modified are undefined. | |
976 | */ | |
977 | int | |
978 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 979 | struct drm_file *file) |
673a394b EA |
980 | { |
981 | struct drm_i915_gem_pwrite *args = data; | |
982 | struct drm_gem_object *obj; | |
983 | struct drm_i915_gem_object *obj_priv; | |
984 | int ret = 0; | |
985 | ||
fbd5a26d | 986 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 987 | if (ret) |
fbd5a26d | 988 | return ret; |
1d7cfea1 CW |
989 | |
990 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
991 | if (obj == NULL) { | |
992 | ret = -ENOENT; | |
993 | goto unlock; | |
fbd5a26d | 994 | } |
23010e43 | 995 | obj_priv = to_intel_bo(obj); |
673a394b | 996 | |
fbd5a26d | 997 | |
7dcd2499 CW |
998 | /* Bounds check destination. */ |
999 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1000 | ret = -EINVAL; |
35b62a89 | 1001 | goto out; |
ce9d419d CW |
1002 | } |
1003 | ||
35b62a89 CW |
1004 | if (args->size == 0) |
1005 | goto out; | |
1006 | ||
ce9d419d CW |
1007 | if (!access_ok(VERIFY_READ, |
1008 | (char __user *)(uintptr_t)args->data_ptr, | |
1009 | args->size)) { | |
1010 | ret = -EFAULT; | |
35b62a89 | 1011 | goto out; |
673a394b EA |
1012 | } |
1013 | ||
b5e4feb6 CW |
1014 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
1015 | args->size); | |
1016 | if (ret) { | |
1017 | ret = -EFAULT; | |
1018 | goto out; | |
673a394b EA |
1019 | } |
1020 | ||
1021 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1022 | * it would end up going through the fenced access, and we'll get | |
1023 | * different detiling behavior between reading and writing. | |
1024 | * pread/pwrite currently are reading and writing from the CPU | |
1025 | * perspective, requiring manual detiling by the client. | |
1026 | */ | |
71acb5eb | 1027 | if (obj_priv->phys_obj) |
fbd5a26d | 1028 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1029 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1030 | obj_priv->gtt_space && |
9b8c4a0b | 1031 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d CW |
1032 | ret = i915_gem_object_pin(obj, 0); |
1033 | if (ret) | |
1034 | goto out; | |
1035 | ||
1036 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1037 | if (ret) | |
1038 | goto out_unpin; | |
1039 | ||
1040 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1041 | if (ret == -EFAULT) | |
1042 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1043 | ||
1044 | out_unpin: | |
1045 | i915_gem_object_unpin(obj); | |
40123c1f | 1046 | } else { |
fbd5a26d CW |
1047 | ret = i915_gem_object_get_pages_or_evict(obj); |
1048 | if (ret) | |
1049 | goto out; | |
673a394b | 1050 | |
fbd5a26d CW |
1051 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1052 | if (ret) | |
1053 | goto out_put; | |
673a394b | 1054 | |
fbd5a26d CW |
1055 | ret = -EFAULT; |
1056 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1057 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1058 | if (ret == -EFAULT) | |
1059 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
1060 | ||
1061 | out_put: | |
1062 | i915_gem_object_put_pages(obj); | |
1063 | } | |
673a394b | 1064 | |
35b62a89 | 1065 | out: |
fbd5a26d | 1066 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1067 | unlock: |
fbd5a26d | 1068 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1069 | return ret; |
1070 | } | |
1071 | ||
1072 | /** | |
2ef7eeaa EA |
1073 | * Called when user space prepares to use an object with the CPU, either |
1074 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1075 | */ |
1076 | int | |
1077 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1078 | struct drm_file *file_priv) | |
1079 | { | |
a09ba7fa | 1080 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1081 | struct drm_i915_gem_set_domain *args = data; |
1082 | struct drm_gem_object *obj; | |
652c393a | 1083 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1084 | uint32_t read_domains = args->read_domains; |
1085 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1086 | int ret; |
1087 | ||
1088 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1089 | return -ENODEV; | |
1090 | ||
2ef7eeaa | 1091 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1092 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1093 | return -EINVAL; |
1094 | ||
21d509e3 | 1095 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1096 | return -EINVAL; |
1097 | ||
1098 | /* Having something in the write domain implies it's in the read | |
1099 | * domain, and only that read domain. Enforce that in the request. | |
1100 | */ | |
1101 | if (write_domain != 0 && read_domains != write_domain) | |
1102 | return -EINVAL; | |
1103 | ||
76c1dec1 | 1104 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1105 | if (ret) |
76c1dec1 | 1106 | return ret; |
1d7cfea1 | 1107 | |
673a394b | 1108 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1d7cfea1 CW |
1109 | if (obj == NULL) { |
1110 | ret = -ENOENT; | |
1111 | goto unlock; | |
76c1dec1 | 1112 | } |
23010e43 | 1113 | obj_priv = to_intel_bo(obj); |
673a394b | 1114 | |
652c393a JB |
1115 | intel_mark_busy(dev, obj); |
1116 | ||
2ef7eeaa EA |
1117 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1118 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1119 | |
a09ba7fa EA |
1120 | /* Update the LRU on the fence for the CPU access that's |
1121 | * about to occur. | |
1122 | */ | |
1123 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1124 | struct drm_i915_fence_reg *reg = |
1125 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1126 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1127 | &dev_priv->mm.fence_list); |
1128 | } | |
1129 | ||
02354392 EA |
1130 | /* Silently promote "you're not bound, there was nothing to do" |
1131 | * to success, since the client was just asking us to | |
1132 | * make sure everything was done. | |
1133 | */ | |
1134 | if (ret == -EINVAL) | |
1135 | ret = 0; | |
2ef7eeaa | 1136 | } else { |
e47c68e9 | 1137 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1138 | } |
1139 | ||
7d1c4804 CW |
1140 | /* Maintain LRU order of "inactive" objects */ |
1141 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
69dc4987 | 1142 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1143 | |
673a394b | 1144 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1145 | unlock: |
673a394b EA |
1146 | mutex_unlock(&dev->struct_mutex); |
1147 | return ret; | |
1148 | } | |
1149 | ||
1150 | /** | |
1151 | * Called when user space has done writes to this buffer | |
1152 | */ | |
1153 | int | |
1154 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1155 | struct drm_file *file_priv) | |
1156 | { | |
1157 | struct drm_i915_gem_sw_finish *args = data; | |
1158 | struct drm_gem_object *obj; | |
673a394b EA |
1159 | int ret = 0; |
1160 | ||
1161 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1162 | return -ENODEV; | |
1163 | ||
76c1dec1 | 1164 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1165 | if (ret) |
76c1dec1 | 1166 | return ret; |
1d7cfea1 | 1167 | |
673a394b EA |
1168 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1169 | if (obj == NULL) { | |
1d7cfea1 CW |
1170 | ret = -ENOENT; |
1171 | goto unlock; | |
673a394b EA |
1172 | } |
1173 | ||
673a394b | 1174 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1175 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1176 | i915_gem_object_flush_cpu_write_domain(obj); |
1177 | ||
673a394b | 1178 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1179 | unlock: |
673a394b EA |
1180 | mutex_unlock(&dev->struct_mutex); |
1181 | return ret; | |
1182 | } | |
1183 | ||
1184 | /** | |
1185 | * Maps the contents of an object, returning the address it is mapped | |
1186 | * into. | |
1187 | * | |
1188 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1189 | * imply a ref on the object itself. | |
1190 | */ | |
1191 | int | |
1192 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1193 | struct drm_file *file_priv) | |
1194 | { | |
1195 | struct drm_i915_gem_mmap *args = data; | |
1196 | struct drm_gem_object *obj; | |
1197 | loff_t offset; | |
1198 | unsigned long addr; | |
1199 | ||
1200 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1201 | return -ENODEV; | |
1202 | ||
1203 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1204 | if (obj == NULL) | |
bf79cb91 | 1205 | return -ENOENT; |
673a394b EA |
1206 | |
1207 | offset = args->offset; | |
1208 | ||
1209 | down_write(¤t->mm->mmap_sem); | |
1210 | addr = do_mmap(obj->filp, 0, args->size, | |
1211 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1212 | args->offset); | |
1213 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1214 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1215 | if (IS_ERR((void *)addr)) |
1216 | return addr; | |
1217 | ||
1218 | args->addr_ptr = (uint64_t) addr; | |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
de151cf6 JB |
1223 | /** |
1224 | * i915_gem_fault - fault a page into the GTT | |
1225 | * vma: VMA in question | |
1226 | * vmf: fault info | |
1227 | * | |
1228 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1229 | * from userspace. The fault handler takes care of binding the object to | |
1230 | * the GTT (if needed), allocating and programming a fence register (again, | |
1231 | * only if needed based on whether the old reg is still valid or the object | |
1232 | * is tiled) and inserting a new PTE into the faulting process. | |
1233 | * | |
1234 | * Note that the faulting process may involve evicting existing objects | |
1235 | * from the GTT and/or fence registers to make room. So performance may | |
1236 | * suffer if the GTT working set is large or there are few fence registers | |
1237 | * left. | |
1238 | */ | |
1239 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1240 | { | |
1241 | struct drm_gem_object *obj = vma->vm_private_data; | |
1242 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1243 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1244 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1245 | pgoff_t page_offset; |
1246 | unsigned long pfn; | |
1247 | int ret = 0; | |
0f973f27 | 1248 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1249 | |
1250 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1251 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1252 | PAGE_SHIFT; | |
1253 | ||
1254 | /* Now bind it into the GTT if needed */ | |
1255 | mutex_lock(&dev->struct_mutex); | |
1256 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1257 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1258 | if (ret) |
1259 | goto unlock; | |
07f4f3e8 | 1260 | |
07f4f3e8 | 1261 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1262 | if (ret) |
1263 | goto unlock; | |
de151cf6 JB |
1264 | } |
1265 | ||
1266 | /* Need a new fence register? */ | |
a09ba7fa | 1267 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1268 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1269 | if (ret) |
1270 | goto unlock; | |
d9ddcb96 | 1271 | } |
de151cf6 | 1272 | |
7d1c4804 | 1273 | if (i915_gem_object_is_inactive(obj_priv)) |
69dc4987 | 1274 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1275 | |
de151cf6 JB |
1276 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1277 | page_offset; | |
1278 | ||
1279 | /* Finally, remap it using the new GTT offset */ | |
1280 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1281 | unlock: |
de151cf6 JB |
1282 | mutex_unlock(&dev->struct_mutex); |
1283 | ||
1284 | switch (ret) { | |
c715089f CW |
1285 | case 0: |
1286 | case -ERESTARTSYS: | |
1287 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1288 | case -ENOMEM: |
1289 | case -EAGAIN: | |
1290 | return VM_FAULT_OOM; | |
de151cf6 | 1291 | default: |
c715089f | 1292 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1293 | } |
1294 | } | |
1295 | ||
1296 | /** | |
1297 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1298 | * @obj: obj in question | |
1299 | * | |
1300 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1301 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1302 | * up the object based on the offset and sets up the various memory mapping | |
1303 | * structures. | |
1304 | * | |
1305 | * This routine allocates and attaches a fake offset for @obj. | |
1306 | */ | |
1307 | static int | |
1308 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1309 | { | |
1310 | struct drm_device *dev = obj->dev; | |
1311 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1312 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1313 | struct drm_map_list *list; |
f77d390c | 1314 | struct drm_local_map *map; |
de151cf6 JB |
1315 | int ret = 0; |
1316 | ||
1317 | /* Set the object up for mmap'ing */ | |
1318 | list = &obj->map_list; | |
9a298b2a | 1319 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1320 | if (!list->map) |
1321 | return -ENOMEM; | |
1322 | ||
1323 | map = list->map; | |
1324 | map->type = _DRM_GEM; | |
1325 | map->size = obj->size; | |
1326 | map->handle = obj; | |
1327 | ||
1328 | /* Get a DRM GEM mmap offset allocated... */ | |
1329 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1330 | obj->size / PAGE_SIZE, 0, 0); | |
1331 | if (!list->file_offset_node) { | |
1332 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1333 | ret = -ENOSPC; |
de151cf6 JB |
1334 | goto out_free_list; |
1335 | } | |
1336 | ||
1337 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1338 | obj->size / PAGE_SIZE, 0); | |
1339 | if (!list->file_offset_node) { | |
1340 | ret = -ENOMEM; | |
1341 | goto out_free_list; | |
1342 | } | |
1343 | ||
1344 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1345 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1346 | if (ret) { | |
de151cf6 JB |
1347 | DRM_ERROR("failed to add to map hash\n"); |
1348 | goto out_free_mm; | |
1349 | } | |
1350 | ||
1351 | /* By now we should be all set, any drm_mmap request on the offset | |
1352 | * below will get to our mmap & fault handler */ | |
1353 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1354 | ||
1355 | return 0; | |
1356 | ||
1357 | out_free_mm: | |
1358 | drm_mm_put_block(list->file_offset_node); | |
1359 | out_free_list: | |
9a298b2a | 1360 | kfree(list->map); |
de151cf6 JB |
1361 | |
1362 | return ret; | |
1363 | } | |
1364 | ||
901782b2 CW |
1365 | /** |
1366 | * i915_gem_release_mmap - remove physical page mappings | |
1367 | * @obj: obj in question | |
1368 | * | |
af901ca1 | 1369 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1370 | * relinquish ownership of the pages back to the system. |
1371 | * | |
1372 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1373 | * object through the GTT and then lose the fence register due to | |
1374 | * resource pressure. Similarly if the object has been moved out of the | |
1375 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1376 | * mapping will then trigger a page fault on the next user access, allowing | |
1377 | * fixup by i915_gem_fault(). | |
1378 | */ | |
d05ca301 | 1379 | void |
901782b2 CW |
1380 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1381 | { | |
1382 | struct drm_device *dev = obj->dev; | |
23010e43 | 1383 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1384 | |
1385 | if (dev->dev_mapping) | |
1386 | unmap_mapping_range(dev->dev_mapping, | |
1387 | obj_priv->mmap_offset, obj->size, 1); | |
1388 | } | |
1389 | ||
ab00b3e5 JB |
1390 | static void |
1391 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1392 | { | |
1393 | struct drm_device *dev = obj->dev; | |
23010e43 | 1394 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1395 | struct drm_gem_mm *mm = dev->mm_private; |
1396 | struct drm_map_list *list; | |
1397 | ||
1398 | list = &obj->map_list; | |
1399 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1400 | ||
1401 | if (list->file_offset_node) { | |
1402 | drm_mm_put_block(list->file_offset_node); | |
1403 | list->file_offset_node = NULL; | |
1404 | } | |
1405 | ||
1406 | if (list->map) { | |
9a298b2a | 1407 | kfree(list->map); |
ab00b3e5 JB |
1408 | list->map = NULL; |
1409 | } | |
1410 | ||
1411 | obj_priv->mmap_offset = 0; | |
1412 | } | |
1413 | ||
de151cf6 JB |
1414 | /** |
1415 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1416 | * @obj: object to check | |
1417 | * | |
1418 | * Return the required GTT alignment for an object, taking into account | |
1419 | * potential fence register mapping if needed. | |
1420 | */ | |
1421 | static uint32_t | |
1422 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1423 | { | |
1424 | struct drm_device *dev = obj->dev; | |
23010e43 | 1425 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1426 | int start, i; |
1427 | ||
1428 | /* | |
1429 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1430 | * if a fence register is needed for the object. | |
1431 | */ | |
a6c45cf0 | 1432 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1433 | return 4096; |
1434 | ||
1435 | /* | |
1436 | * Previous chips need to be aligned to the size of the smallest | |
1437 | * fence register that can contain the object. | |
1438 | */ | |
a6c45cf0 | 1439 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1440 | start = 1024*1024; |
1441 | else | |
1442 | start = 512*1024; | |
1443 | ||
1444 | for (i = start; i < obj->size; i <<= 1) | |
1445 | ; | |
1446 | ||
1447 | return i; | |
1448 | } | |
1449 | ||
1450 | /** | |
1451 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1452 | * @dev: DRM device | |
1453 | * @data: GTT mapping ioctl data | |
1454 | * @file_priv: GEM object info | |
1455 | * | |
1456 | * Simply returns the fake offset to userspace so it can mmap it. | |
1457 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1458 | * up so we can get faults in the handler above. | |
1459 | * | |
1460 | * The fault handler will take care of binding the object into the GTT | |
1461 | * (since it may have been evicted to make room for something), allocating | |
1462 | * a fence register, and mapping the appropriate aperture address into | |
1463 | * userspace. | |
1464 | */ | |
1465 | int | |
1466 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1467 | struct drm_file *file_priv) | |
1468 | { | |
1469 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1470 | struct drm_gem_object *obj; |
1471 | struct drm_i915_gem_object *obj_priv; | |
1472 | int ret; | |
1473 | ||
1474 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1475 | return -ENODEV; | |
1476 | ||
76c1dec1 | 1477 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1478 | if (ret) |
76c1dec1 | 1479 | return ret; |
de151cf6 | 1480 | |
1d7cfea1 CW |
1481 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1482 | if (obj == NULL) { | |
1483 | ret = -ENOENT; | |
1484 | goto unlock; | |
1485 | } | |
23010e43 | 1486 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1487 | |
ab18282d CW |
1488 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1489 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1d7cfea1 CW |
1490 | ret = -EINVAL; |
1491 | goto out; | |
ab18282d CW |
1492 | } |
1493 | ||
de151cf6 JB |
1494 | if (!obj_priv->mmap_offset) { |
1495 | ret = i915_gem_create_mmap_offset(obj); | |
1d7cfea1 CW |
1496 | if (ret) |
1497 | goto out; | |
de151cf6 JB |
1498 | } |
1499 | ||
1500 | args->offset = obj_priv->mmap_offset; | |
1501 | ||
de151cf6 JB |
1502 | /* |
1503 | * Pull it into the GTT so that we have a page list (makes the | |
1504 | * initial fault faster and any subsequent flushing possible). | |
1505 | */ | |
1506 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1507 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
1d7cfea1 CW |
1508 | if (ret) |
1509 | goto out; | |
de151cf6 JB |
1510 | } |
1511 | ||
1d7cfea1 | 1512 | out: |
de151cf6 | 1513 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1514 | unlock: |
de151cf6 | 1515 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1516 | return ret; |
de151cf6 JB |
1517 | } |
1518 | ||
5cdf5881 | 1519 | static void |
856fa198 | 1520 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1521 | { |
23010e43 | 1522 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1523 | int page_count = obj->size / PAGE_SIZE; |
1524 | int i; | |
1525 | ||
856fa198 | 1526 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1527 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1528 | |
856fa198 EA |
1529 | if (--obj_priv->pages_refcount != 0) |
1530 | return; | |
673a394b | 1531 | |
280b713b EA |
1532 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1533 | i915_gem_object_save_bit_17_swizzle(obj); | |
1534 | ||
3ef94daa | 1535 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1536 | obj_priv->dirty = 0; |
3ef94daa CW |
1537 | |
1538 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1539 | if (obj_priv->dirty) |
1540 | set_page_dirty(obj_priv->pages[i]); | |
1541 | ||
1542 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1543 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1544 | |
1545 | page_cache_release(obj_priv->pages[i]); | |
1546 | } | |
673a394b EA |
1547 | obj_priv->dirty = 0; |
1548 | ||
8e7d2b2c | 1549 | drm_free_large(obj_priv->pages); |
856fa198 | 1550 | obj_priv->pages = NULL; |
673a394b EA |
1551 | } |
1552 | ||
a56ba56c CW |
1553 | static uint32_t |
1554 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1555 | struct intel_ring_buffer *ring) | |
1556 | { | |
1557 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1558 | ||
1559 | ring->outstanding_lazy_request = true; | |
1560 | return dev_priv->next_seqno; | |
1561 | } | |
1562 | ||
673a394b | 1563 | static void |
617dbe27 | 1564 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1565 | struct intel_ring_buffer *ring) |
673a394b EA |
1566 | { |
1567 | struct drm_device *dev = obj->dev; | |
69dc4987 | 1568 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1569 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1570 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1571 | |
852835f3 ZN |
1572 | BUG_ON(ring == NULL); |
1573 | obj_priv->ring = ring; | |
673a394b EA |
1574 | |
1575 | /* Add a reference if we're newly entering the active list. */ | |
1576 | if (!obj_priv->active) { | |
1577 | drm_gem_object_reference(obj); | |
1578 | obj_priv->active = 1; | |
1579 | } | |
e35a41de | 1580 | |
673a394b | 1581 | /* Move from whatever list we were on to the tail of execution. */ |
69dc4987 CW |
1582 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
1583 | list_move_tail(&obj_priv->ring_list, &ring->active_list); | |
ce44b0ea | 1584 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1585 | } |
1586 | ||
ce44b0ea EA |
1587 | static void |
1588 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1589 | { | |
1590 | struct drm_device *dev = obj->dev; | |
1591 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1592 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1593 | |
1594 | BUG_ON(!obj_priv->active); | |
69dc4987 CW |
1595 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
1596 | list_del_init(&obj_priv->ring_list); | |
ce44b0ea EA |
1597 | obj_priv->last_rendering_seqno = 0; |
1598 | } | |
673a394b | 1599 | |
963b4836 CW |
1600 | /* Immediately discard the backing storage */ |
1601 | static void | |
1602 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1603 | { | |
23010e43 | 1604 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1605 | struct inode *inode; |
963b4836 | 1606 | |
ae9fed6b CW |
1607 | /* Our goal here is to return as much of the memory as |
1608 | * is possible back to the system as we are called from OOM. | |
1609 | * To do this we must instruct the shmfs to drop all of its | |
1610 | * backing pages, *now*. Here we mirror the actions taken | |
1611 | * when by shmem_delete_inode() to release the backing store. | |
1612 | */ | |
bb6baf76 | 1613 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1614 | truncate_inode_pages(inode->i_mapping, 0); |
1615 | if (inode->i_op->truncate_range) | |
1616 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1617 | |
1618 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1619 | } |
1620 | ||
1621 | static inline int | |
1622 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1623 | { | |
1624 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1625 | } | |
1626 | ||
673a394b EA |
1627 | static void |
1628 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1629 | { | |
1630 | struct drm_device *dev = obj->dev; | |
1631 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1632 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1633 | |
673a394b | 1634 | if (obj_priv->pin_count != 0) |
69dc4987 | 1635 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
673a394b | 1636 | else |
69dc4987 CW |
1637 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
1638 | list_del_init(&obj_priv->ring_list); | |
673a394b | 1639 | |
99fcb766 DV |
1640 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1641 | ||
ce44b0ea | 1642 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1643 | obj_priv->ring = NULL; |
673a394b EA |
1644 | if (obj_priv->active) { |
1645 | obj_priv->active = 0; | |
1646 | drm_gem_object_unreference(obj); | |
1647 | } | |
23bc5982 | 1648 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1649 | } |
1650 | ||
63560396 DV |
1651 | static void |
1652 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1653 | uint32_t flush_domains, |
852835f3 | 1654 | struct intel_ring_buffer *ring) |
63560396 DV |
1655 | { |
1656 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1657 | struct drm_i915_gem_object *obj_priv, *next; | |
1658 | ||
1659 | list_for_each_entry_safe(obj_priv, next, | |
64193406 | 1660 | &ring->gpu_write_list, |
63560396 | 1661 | gpu_write_list) { |
a8089e84 | 1662 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1663 | |
64193406 | 1664 | if (obj->write_domain & flush_domains) { |
63560396 DV |
1665 | uint32_t old_write_domain = obj->write_domain; |
1666 | ||
1667 | obj->write_domain = 0; | |
1668 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1669 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1670 | |
1671 | /* update the fence lru list */ | |
007cc8ac DV |
1672 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1673 | struct drm_i915_fence_reg *reg = | |
1674 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1675 | list_move_tail(®->lru_list, | |
63560396 | 1676 | &dev_priv->mm.fence_list); |
007cc8ac | 1677 | } |
63560396 DV |
1678 | |
1679 | trace_i915_gem_object_change_domain(obj, | |
1680 | obj->read_domains, | |
1681 | old_write_domain); | |
1682 | } | |
1683 | } | |
1684 | } | |
8187a2b7 | 1685 | |
5a5a0c64 | 1686 | uint32_t |
8a1a49f9 | 1687 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1688 | struct drm_file *file, |
8dc5d147 | 1689 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1690 | struct intel_ring_buffer *ring) |
673a394b EA |
1691 | { |
1692 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1693 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1694 | uint32_t seqno; |
1695 | int was_empty; | |
673a394b | 1696 | |
f787a5f5 CW |
1697 | if (file != NULL) |
1698 | file_priv = file->driver_priv; | |
b962442e | 1699 | |
8dc5d147 CW |
1700 | if (request == NULL) { |
1701 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1702 | if (request == NULL) | |
1703 | return 0; | |
1704 | } | |
673a394b | 1705 | |
f787a5f5 | 1706 | seqno = ring->add_request(dev, ring, 0); |
a56ba56c | 1707 | ring->outstanding_lazy_request = false; |
673a394b EA |
1708 | |
1709 | request->seqno = seqno; | |
852835f3 | 1710 | request->ring = ring; |
673a394b | 1711 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1712 | was_empty = list_empty(&ring->request_list); |
1713 | list_add_tail(&request->list, &ring->request_list); | |
1714 | ||
f787a5f5 | 1715 | if (file_priv) { |
1c25595f | 1716 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1717 | request->file_priv = file_priv; |
b962442e | 1718 | list_add_tail(&request->client_list, |
f787a5f5 | 1719 | &file_priv->mm.request_list); |
1c25595f | 1720 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1721 | } |
673a394b | 1722 | |
f65d9421 | 1723 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1724 | mod_timer(&dev_priv->hangcheck_timer, |
1725 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1726 | if (was_empty) |
b3b079db CW |
1727 | queue_delayed_work(dev_priv->wq, |
1728 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1729 | } |
673a394b EA |
1730 | return seqno; |
1731 | } | |
1732 | ||
1733 | /** | |
1734 | * Command execution barrier | |
1735 | * | |
1736 | * Ensures that all commands in the ring are finished | |
1737 | * before signalling the CPU | |
1738 | */ | |
8a1a49f9 | 1739 | static void |
852835f3 | 1740 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1741 | { |
673a394b | 1742 | uint32_t flush_domains = 0; |
673a394b EA |
1743 | |
1744 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1745 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1746 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 ZN |
1747 | |
1748 | ring->flush(dev, ring, | |
1749 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1750 | } |
1751 | ||
f787a5f5 CW |
1752 | static inline void |
1753 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1754 | { |
1c25595f | 1755 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1756 | |
1c25595f CW |
1757 | if (!file_priv) |
1758 | return; | |
1c5d22f7 | 1759 | |
1c25595f CW |
1760 | spin_lock(&file_priv->mm.lock); |
1761 | list_del(&request->client_list); | |
1762 | request->file_priv = NULL; | |
1763 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1764 | } |
673a394b | 1765 | |
dfaae392 CW |
1766 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1767 | struct intel_ring_buffer *ring) | |
9375e446 | 1768 | { |
dfaae392 CW |
1769 | while (!list_empty(&ring->request_list)) { |
1770 | struct drm_i915_gem_request *request; | |
673a394b | 1771 | |
dfaae392 CW |
1772 | request = list_first_entry(&ring->request_list, |
1773 | struct drm_i915_gem_request, | |
1774 | list); | |
de151cf6 | 1775 | |
dfaae392 | 1776 | list_del(&request->list); |
f787a5f5 | 1777 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1778 | kfree(request); |
1779 | } | |
673a394b | 1780 | |
dfaae392 | 1781 | while (!list_empty(&ring->active_list)) { |
9375e446 CW |
1782 | struct drm_i915_gem_object *obj_priv; |
1783 | ||
dfaae392 | 1784 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 | 1785 | struct drm_i915_gem_object, |
69dc4987 | 1786 | ring_list); |
9375e446 CW |
1787 | |
1788 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1789 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 | 1790 | i915_gem_object_move_to_inactive(&obj_priv->base); |
673a394b EA |
1791 | } |
1792 | } | |
1793 | ||
069efc1d | 1794 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1795 | { |
77f01230 CW |
1796 | struct drm_i915_private *dev_priv = dev->dev_private; |
1797 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1798 | int i; |
673a394b | 1799 | |
dfaae392 | 1800 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1801 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1802 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1803 | |
1804 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1805 | * to be lost on reset along with the data, so simply move the | |
1806 | * lost bo to the inactive list. | |
1807 | */ | |
1808 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1809 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1810 | struct drm_i915_gem_object, | |
69dc4987 | 1811 | mm_list); |
dfaae392 CW |
1812 | |
1813 | obj_priv->base.write_domain = 0; | |
1814 | list_del_init(&obj_priv->gpu_write_list); | |
1815 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1816 | } | |
1817 | ||
1818 | /* Move everything out of the GPU domains to ensure we do any | |
1819 | * necessary invalidation upon reuse. | |
1820 | */ | |
77f01230 CW |
1821 | list_for_each_entry(obj_priv, |
1822 | &dev_priv->mm.inactive_list, | |
69dc4987 | 1823 | mm_list) |
77f01230 CW |
1824 | { |
1825 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1826 | } | |
069efc1d CW |
1827 | |
1828 | /* The fence registers are invalidated so clear them out */ | |
1829 | for (i = 0; i < 16; i++) { | |
1830 | struct drm_i915_fence_reg *reg; | |
1831 | ||
1832 | reg = &dev_priv->fence_regs[i]; | |
1833 | if (!reg->obj) | |
1834 | continue; | |
1835 | ||
1836 | i915_gem_clear_fence_reg(reg->obj); | |
1837 | } | |
673a394b EA |
1838 | } |
1839 | ||
1840 | /** | |
1841 | * This function clears the request list as sequence numbers are passed. | |
1842 | */ | |
b09a1fec CW |
1843 | static void |
1844 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1845 | struct intel_ring_buffer *ring) | |
673a394b EA |
1846 | { |
1847 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1848 | uint32_t seqno; | |
1849 | ||
b84d5f0c CW |
1850 | if (!ring->status_page.page_addr || |
1851 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1852 | return; |
1853 | ||
23bc5982 | 1854 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1855 | |
f787a5f5 | 1856 | seqno = ring->get_seqno(dev, ring); |
852835f3 | 1857 | while (!list_empty(&ring->request_list)) { |
673a394b | 1858 | struct drm_i915_gem_request *request; |
673a394b | 1859 | |
852835f3 | 1860 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1861 | struct drm_i915_gem_request, |
1862 | list); | |
673a394b | 1863 | |
dfaae392 | 1864 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1865 | break; |
1866 | ||
1867 | trace_i915_gem_request_retire(dev, request->seqno); | |
1868 | ||
1869 | list_del(&request->list); | |
f787a5f5 | 1870 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1871 | kfree(request); |
1872 | } | |
673a394b | 1873 | |
b84d5f0c CW |
1874 | /* Move any buffers on the active list that are no longer referenced |
1875 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1876 | */ | |
1877 | while (!list_empty(&ring->active_list)) { | |
1878 | struct drm_gem_object *obj; | |
1879 | struct drm_i915_gem_object *obj_priv; | |
1880 | ||
1881 | obj_priv = list_first_entry(&ring->active_list, | |
1882 | struct drm_i915_gem_object, | |
69dc4987 | 1883 | ring_list); |
673a394b | 1884 | |
dfaae392 | 1885 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1886 | break; |
b84d5f0c CW |
1887 | |
1888 | obj = &obj_priv->base; | |
b84d5f0c CW |
1889 | if (obj->write_domain != 0) |
1890 | i915_gem_object_move_to_flushing(obj); | |
1891 | else | |
1892 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1893 | } |
9d34e5db CW |
1894 | |
1895 | if (unlikely (dev_priv->trace_irq_seqno && | |
1896 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 | 1897 | ring->user_irq_put(dev, ring); |
9d34e5db CW |
1898 | dev_priv->trace_irq_seqno = 0; |
1899 | } | |
23bc5982 CW |
1900 | |
1901 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1902 | } |
1903 | ||
b09a1fec CW |
1904 | void |
1905 | i915_gem_retire_requests(struct drm_device *dev) | |
1906 | { | |
1907 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1908 | ||
be72615b CW |
1909 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1910 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1911 | ||
1912 | /* We must be careful that during unbind() we do not | |
1913 | * accidentally infinitely recurse into retire requests. | |
1914 | * Currently: | |
1915 | * retire -> free -> unbind -> wait -> retire_ring | |
1916 | */ | |
1917 | list_for_each_entry_safe(obj_priv, tmp, | |
1918 | &dev_priv->mm.deferred_free_list, | |
69dc4987 | 1919 | mm_list) |
be72615b CW |
1920 | i915_gem_free_object_tail(&obj_priv->base); |
1921 | } | |
1922 | ||
b09a1fec | 1923 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 1924 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 1925 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
1926 | } |
1927 | ||
75ef9da2 | 1928 | static void |
673a394b EA |
1929 | i915_gem_retire_work_handler(struct work_struct *work) |
1930 | { | |
1931 | drm_i915_private_t *dev_priv; | |
1932 | struct drm_device *dev; | |
1933 | ||
1934 | dev_priv = container_of(work, drm_i915_private_t, | |
1935 | mm.retire_work.work); | |
1936 | dev = dev_priv->dev; | |
1937 | ||
891b48cf CW |
1938 | /* Come back later if the device is busy... */ |
1939 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1940 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1941 | return; | |
1942 | } | |
1943 | ||
b09a1fec | 1944 | i915_gem_retire_requests(dev); |
d1b851fc | 1945 | |
6dbe2772 | 1946 | if (!dev_priv->mm.suspended && |
d1b851fc | 1947 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
1948 | !list_empty(&dev_priv->bsd_ring.request_list) || |
1949 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 1950 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1951 | mutex_unlock(&dev->struct_mutex); |
1952 | } | |
1953 | ||
5a5a0c64 | 1954 | int |
852835f3 | 1955 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1956 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1957 | { |
1958 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1959 | u32 ier; |
673a394b EA |
1960 | int ret = 0; |
1961 | ||
1962 | BUG_ON(seqno == 0); | |
1963 | ||
ba1234d1 | 1964 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
1965 | return -EAGAIN; |
1966 | ||
a56ba56c | 1967 | if (ring->outstanding_lazy_request) { |
8dc5d147 | 1968 | seqno = i915_add_request(dev, NULL, NULL, ring); |
e35a41de DV |
1969 | if (seqno == 0) |
1970 | return -ENOMEM; | |
1971 | } | |
a56ba56c | 1972 | BUG_ON(seqno == dev_priv->next_seqno); |
ffed1d09 | 1973 | |
f787a5f5 | 1974 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { |
bad720ff | 1975 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1976 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1977 | else | |
1978 | ier = I915_READ(IER); | |
802c7eb6 JB |
1979 | if (!ier) { |
1980 | DRM_ERROR("something (likely vbetool) disabled " | |
1981 | "interrupts, re-enabling\n"); | |
1982 | i915_driver_irq_preinstall(dev); | |
1983 | i915_driver_irq_postinstall(dev); | |
1984 | } | |
1985 | ||
1c5d22f7 CW |
1986 | trace_i915_gem_request_wait_begin(dev, seqno); |
1987 | ||
852835f3 | 1988 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 1989 | ring->user_irq_get(dev, ring); |
48764bf4 | 1990 | if (interruptible) |
852835f3 ZN |
1991 | ret = wait_event_interruptible(ring->irq_queue, |
1992 | i915_seqno_passed( | |
f787a5f5 | 1993 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 1994 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 1995 | else |
852835f3 ZN |
1996 | wait_event(ring->irq_queue, |
1997 | i915_seqno_passed( | |
f787a5f5 | 1998 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 1999 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2000 | |
8187a2b7 | 2001 | ring->user_irq_put(dev, ring); |
852835f3 | 2002 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
2003 | |
2004 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2005 | } |
ba1234d1 | 2006 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2007 | ret = -EAGAIN; |
673a394b EA |
2008 | |
2009 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2010 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
f787a5f5 | 2011 | __func__, ret, seqno, ring->get_seqno(dev, ring), |
8bff917c | 2012 | dev_priv->next_seqno); |
673a394b EA |
2013 | |
2014 | /* Directly dispatch request retiring. While we have the work queue | |
2015 | * to handle this, the waiter on a request often wants an associated | |
2016 | * buffer to have made it to the inactive list, and we would need | |
2017 | * a separate wait queue to handle that. | |
2018 | */ | |
2019 | if (ret == 0) | |
b09a1fec | 2020 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2021 | |
2022 | return ret; | |
2023 | } | |
2024 | ||
48764bf4 DV |
2025 | /** |
2026 | * Waits for a sequence number to be signaled, and cleans up the | |
2027 | * request and object lists appropriately for that event. | |
2028 | */ | |
2029 | static int | |
852835f3 | 2030 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2031 | struct intel_ring_buffer *ring) |
48764bf4 | 2032 | { |
852835f3 | 2033 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2034 | } |
2035 | ||
20f0cd55 | 2036 | static void |
9220434a | 2037 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2038 | struct drm_file *file_priv, |
9220434a CW |
2039 | struct intel_ring_buffer *ring, |
2040 | uint32_t invalidate_domains, | |
2041 | uint32_t flush_domains) | |
2042 | { | |
2043 | ring->flush(dev, ring, invalidate_domains, flush_domains); | |
2044 | i915_gem_process_flushing_list(dev, flush_domains, ring); | |
2045 | } | |
2046 | ||
8187a2b7 ZN |
2047 | static void |
2048 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2049 | struct drm_file *file_priv, |
8187a2b7 | 2050 | uint32_t invalidate_domains, |
9220434a CW |
2051 | uint32_t flush_domains, |
2052 | uint32_t flush_rings) | |
8187a2b7 ZN |
2053 | { |
2054 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2055 | |
8187a2b7 ZN |
2056 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2057 | drm_agp_chipset_flush(dev); | |
8bff917c | 2058 | |
9220434a CW |
2059 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2060 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2061 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2062 | &dev_priv->render_ring, |
2063 | invalidate_domains, flush_domains); | |
2064 | if (flush_rings & RING_BSD) | |
c78ec30b | 2065 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2066 | &dev_priv->bsd_ring, |
2067 | invalidate_domains, flush_domains); | |
549f7365 CW |
2068 | if (flush_rings & RING_BLT) |
2069 | i915_gem_flush_ring(dev, file_priv, | |
2070 | &dev_priv->blt_ring, | |
2071 | invalidate_domains, flush_domains); | |
9220434a | 2072 | } |
8187a2b7 ZN |
2073 | } |
2074 | ||
673a394b EA |
2075 | /** |
2076 | * Ensures that all rendering to the object has completed and the object is | |
2077 | * safe to unbind from the GTT or access from the CPU. | |
2078 | */ | |
2079 | static int | |
2cf34d7b CW |
2080 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2081 | bool interruptible) | |
673a394b EA |
2082 | { |
2083 | struct drm_device *dev = obj->dev; | |
23010e43 | 2084 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2085 | int ret; |
2086 | ||
e47c68e9 EA |
2087 | /* This function only exists to support waiting for existing rendering, |
2088 | * not for emitting required flushes. | |
673a394b | 2089 | */ |
e47c68e9 | 2090 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2091 | |
2092 | /* If there is rendering queued on the buffer being evicted, wait for | |
2093 | * it. | |
2094 | */ | |
2095 | if (obj_priv->active) { | |
2cf34d7b CW |
2096 | ret = i915_do_wait_request(dev, |
2097 | obj_priv->last_rendering_seqno, | |
2098 | interruptible, | |
2099 | obj_priv->ring); | |
2100 | if (ret) | |
673a394b EA |
2101 | return ret; |
2102 | } | |
2103 | ||
2104 | return 0; | |
2105 | } | |
2106 | ||
2107 | /** | |
2108 | * Unbinds an object from the GTT aperture. | |
2109 | */ | |
0f973f27 | 2110 | int |
673a394b EA |
2111 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2112 | { | |
2113 | struct drm_device *dev = obj->dev; | |
73aa808f | 2114 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2115 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2116 | int ret = 0; |
2117 | ||
673a394b EA |
2118 | if (obj_priv->gtt_space == NULL) |
2119 | return 0; | |
2120 | ||
2121 | if (obj_priv->pin_count != 0) { | |
2122 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2123 | return -EINVAL; | |
2124 | } | |
2125 | ||
5323fd04 EA |
2126 | /* blow away mappings if mapped through GTT */ |
2127 | i915_gem_release_mmap(obj); | |
2128 | ||
673a394b EA |
2129 | /* Move the object to the CPU domain to ensure that |
2130 | * any possible CPU writes while it's not in the GTT | |
2131 | * are flushed when we go to remap it. This will | |
2132 | * also ensure that all pending GPU writes are finished | |
2133 | * before we unbind. | |
2134 | */ | |
e47c68e9 | 2135 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2136 | if (ret == -ERESTARTSYS) |
673a394b | 2137 | return ret; |
8dc1775d CW |
2138 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2139 | * should be safe and we need to cleanup or else we might | |
2140 | * cause memory corruption through use-after-free. | |
2141 | */ | |
812ed492 CW |
2142 | if (ret) { |
2143 | i915_gem_clflush_object(obj); | |
2144 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2145 | } | |
673a394b | 2146 | |
96b47b65 DV |
2147 | /* release the fence reg _after_ flushing */ |
2148 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2149 | i915_gem_clear_fence_reg(obj); | |
2150 | ||
73aa808f CW |
2151 | drm_unbind_agp(obj_priv->agp_mem); |
2152 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2153 | |
856fa198 | 2154 | i915_gem_object_put_pages(obj); |
a32808c0 | 2155 | BUG_ON(obj_priv->pages_refcount); |
673a394b | 2156 | |
73aa808f | 2157 | i915_gem_info_remove_gtt(dev_priv, obj->size); |
69dc4987 | 2158 | list_del_init(&obj_priv->mm_list); |
673a394b | 2159 | |
73aa808f CW |
2160 | drm_mm_put_block(obj_priv->gtt_space); |
2161 | obj_priv->gtt_space = NULL; | |
9af90d19 | 2162 | obj_priv->gtt_offset = 0; |
673a394b | 2163 | |
963b4836 CW |
2164 | if (i915_gem_object_is_purgeable(obj_priv)) |
2165 | i915_gem_object_truncate(obj); | |
2166 | ||
1c5d22f7 CW |
2167 | trace_i915_gem_object_unbind(obj); |
2168 | ||
8dc1775d | 2169 | return ret; |
673a394b EA |
2170 | } |
2171 | ||
a56ba56c CW |
2172 | static int i915_ring_idle(struct drm_device *dev, |
2173 | struct intel_ring_buffer *ring) | |
2174 | { | |
395b70be | 2175 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2176 | return 0; |
2177 | ||
a56ba56c CW |
2178 | i915_gem_flush_ring(dev, NULL, ring, |
2179 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2180 | return i915_wait_request(dev, | |
2181 | i915_gem_next_request_seqno(dev, ring), | |
2182 | ring); | |
2183 | } | |
2184 | ||
b47eb4a2 | 2185 | int |
4df2faf4 DV |
2186 | i915_gpu_idle(struct drm_device *dev) |
2187 | { | |
2188 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2189 | bool lists_empty; | |
852835f3 | 2190 | int ret; |
4df2faf4 | 2191 | |
d1b851fc | 2192 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2193 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2194 | if (lists_empty) |
2195 | return 0; | |
2196 | ||
2197 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2198 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2199 | if (ret) |
2200 | return ret; | |
d1b851fc | 2201 | |
87acb0a5 CW |
2202 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2203 | if (ret) | |
2204 | return ret; | |
d1b851fc | 2205 | |
549f7365 CW |
2206 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2207 | if (ret) | |
2208 | return ret; | |
4df2faf4 | 2209 | |
8a1a49f9 | 2210 | return 0; |
4df2faf4 DV |
2211 | } |
2212 | ||
5cdf5881 | 2213 | static int |
4bdadb97 CW |
2214 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2215 | gfp_t gfpmask) | |
673a394b | 2216 | { |
23010e43 | 2217 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2218 | int page_count, i; |
2219 | struct address_space *mapping; | |
2220 | struct inode *inode; | |
2221 | struct page *page; | |
673a394b | 2222 | |
778c3544 DV |
2223 | BUG_ON(obj_priv->pages_refcount |
2224 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2225 | ||
856fa198 | 2226 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2227 | return 0; |
2228 | ||
2229 | /* Get the list of pages out of our struct file. They'll be pinned | |
2230 | * at this point until we release them. | |
2231 | */ | |
2232 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2233 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2234 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2235 | if (obj_priv->pages == NULL) { |
856fa198 | 2236 | obj_priv->pages_refcount--; |
673a394b EA |
2237 | return -ENOMEM; |
2238 | } | |
2239 | ||
2240 | inode = obj->filp->f_path.dentry->d_inode; | |
2241 | mapping = inode->i_mapping; | |
2242 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2243 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2244 | GFP_HIGHUSER | |
4bdadb97 | 2245 | __GFP_COLD | |
cd9f040d | 2246 | __GFP_RECLAIMABLE | |
4bdadb97 | 2247 | gfpmask); |
1f2b1013 CW |
2248 | if (IS_ERR(page)) |
2249 | goto err_pages; | |
2250 | ||
856fa198 | 2251 | obj_priv->pages[i] = page; |
673a394b | 2252 | } |
280b713b EA |
2253 | |
2254 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2255 | i915_gem_object_do_bit_17_swizzle(obj); | |
2256 | ||
673a394b | 2257 | return 0; |
1f2b1013 CW |
2258 | |
2259 | err_pages: | |
2260 | while (i--) | |
2261 | page_cache_release(obj_priv->pages[i]); | |
2262 | ||
2263 | drm_free_large(obj_priv->pages); | |
2264 | obj_priv->pages = NULL; | |
2265 | obj_priv->pages_refcount--; | |
2266 | return PTR_ERR(page); | |
673a394b EA |
2267 | } |
2268 | ||
4e901fdc EA |
2269 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2270 | { | |
2271 | struct drm_gem_object *obj = reg->obj; | |
2272 | struct drm_device *dev = obj->dev; | |
2273 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2274 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2275 | int regnum = obj_priv->fence_reg; |
2276 | uint64_t val; | |
2277 | ||
2278 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2279 | 0xfffff000) << 32; | |
2280 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2281 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2282 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2283 | ||
2284 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2285 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2286 | val |= I965_FENCE_REG_VALID; | |
2287 | ||
2288 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2289 | } | |
2290 | ||
de151cf6 JB |
2291 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2292 | { | |
2293 | struct drm_gem_object *obj = reg->obj; | |
2294 | struct drm_device *dev = obj->dev; | |
2295 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2296 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2297 | int regnum = obj_priv->fence_reg; |
2298 | uint64_t val; | |
2299 | ||
2300 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2301 | 0xfffff000) << 32; | |
2302 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2303 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2304 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2305 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2306 | val |= I965_FENCE_REG_VALID; | |
2307 | ||
2308 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2309 | } | |
2310 | ||
2311 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2312 | { | |
2313 | struct drm_gem_object *obj = reg->obj; | |
2314 | struct drm_device *dev = obj->dev; | |
2315 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2316 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2317 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2318 | int tile_width; |
dc529a4f | 2319 | uint32_t fence_reg, val; |
de151cf6 JB |
2320 | uint32_t pitch_val; |
2321 | ||
2322 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2323 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2324 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2325 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2326 | return; |
2327 | } | |
2328 | ||
0f973f27 JB |
2329 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2330 | HAS_128_BYTE_Y_TILING(dev)) | |
2331 | tile_width = 128; | |
de151cf6 | 2332 | else |
0f973f27 JB |
2333 | tile_width = 512; |
2334 | ||
2335 | /* Note: pitch better be a power of two tile widths */ | |
2336 | pitch_val = obj_priv->stride / tile_width; | |
2337 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2338 | |
c36a2a6d DV |
2339 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2340 | HAS_128_BYTE_Y_TILING(dev)) | |
2341 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2342 | else | |
2343 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2344 | ||
de151cf6 JB |
2345 | val = obj_priv->gtt_offset; |
2346 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2347 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2348 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2349 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2350 | val |= I830_FENCE_REG_VALID; | |
2351 | ||
dc529a4f EA |
2352 | if (regnum < 8) |
2353 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2354 | else | |
2355 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2356 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2357 | } |
2358 | ||
2359 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2360 | { | |
2361 | struct drm_gem_object *obj = reg->obj; | |
2362 | struct drm_device *dev = obj->dev; | |
2363 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2364 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2365 | int regnum = obj_priv->fence_reg; |
2366 | uint32_t val; | |
2367 | uint32_t pitch_val; | |
8d7773a3 | 2368 | uint32_t fence_size_bits; |
de151cf6 | 2369 | |
8d7773a3 | 2370 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2371 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2372 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2373 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2374 | return; |
2375 | } | |
2376 | ||
e76a16de EA |
2377 | pitch_val = obj_priv->stride / 128; |
2378 | pitch_val = ffs(pitch_val) - 1; | |
2379 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2380 | ||
de151cf6 JB |
2381 | val = obj_priv->gtt_offset; |
2382 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2383 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2384 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2385 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2386 | val |= fence_size_bits; | |
de151cf6 JB |
2387 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2388 | val |= I830_FENCE_REG_VALID; | |
2389 | ||
2390 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2391 | } |
2392 | ||
2cf34d7b CW |
2393 | static int i915_find_fence_reg(struct drm_device *dev, |
2394 | bool interruptible) | |
ae3db24a DV |
2395 | { |
2396 | struct drm_i915_fence_reg *reg = NULL; | |
2397 | struct drm_i915_gem_object *obj_priv = NULL; | |
2398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2399 | struct drm_gem_object *obj = NULL; | |
2400 | int i, avail, ret; | |
2401 | ||
2402 | /* First try to find a free reg */ | |
2403 | avail = 0; | |
2404 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2405 | reg = &dev_priv->fence_regs[i]; | |
2406 | if (!reg->obj) | |
2407 | return i; | |
2408 | ||
23010e43 | 2409 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2410 | if (!obj_priv->pin_count) |
2411 | avail++; | |
2412 | } | |
2413 | ||
2414 | if (avail == 0) | |
2415 | return -ENOSPC; | |
2416 | ||
2417 | /* None available, try to steal one or wait for a user to finish */ | |
2418 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2419 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2420 | lru_list) { | |
2421 | obj = reg->obj; | |
2422 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2423 | |
2424 | if (obj_priv->pin_count) | |
2425 | continue; | |
2426 | ||
2427 | /* found one! */ | |
2428 | i = obj_priv->fence_reg; | |
2429 | break; | |
2430 | } | |
2431 | ||
2432 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2433 | ||
2434 | /* We only have a reference on obj from the active list. put_fence_reg | |
2435 | * might drop that one, causing a use-after-free in it. So hold a | |
2436 | * private reference to obj like the other callers of put_fence_reg | |
2437 | * (set_tiling ioctl) do. */ | |
2438 | drm_gem_object_reference(obj); | |
2cf34d7b | 2439 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2440 | drm_gem_object_unreference(obj); |
2441 | if (ret != 0) | |
2442 | return ret; | |
2443 | ||
2444 | return i; | |
2445 | } | |
2446 | ||
de151cf6 JB |
2447 | /** |
2448 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2449 | * @obj: object to map through a fence reg | |
2450 | * | |
2451 | * When mapping objects through the GTT, userspace wants to be able to write | |
2452 | * to them without having to worry about swizzling if the object is tiled. | |
2453 | * | |
2454 | * This function walks the fence regs looking for a free one for @obj, | |
2455 | * stealing one if it can't find any. | |
2456 | * | |
2457 | * It then sets up the reg based on the object's properties: address, pitch | |
2458 | * and tiling format. | |
2459 | */ | |
8c4b8c3f | 2460 | int |
2cf34d7b CW |
2461 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2462 | bool interruptible) | |
de151cf6 JB |
2463 | { |
2464 | struct drm_device *dev = obj->dev; | |
79e53945 | 2465 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2466 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2467 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2468 | int ret; |
de151cf6 | 2469 | |
a09ba7fa EA |
2470 | /* Just update our place in the LRU if our fence is getting used. */ |
2471 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2472 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2473 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2474 | return 0; |
2475 | } | |
2476 | ||
de151cf6 JB |
2477 | switch (obj_priv->tiling_mode) { |
2478 | case I915_TILING_NONE: | |
2479 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2480 | break; | |
2481 | case I915_TILING_X: | |
0f973f27 JB |
2482 | if (!obj_priv->stride) |
2483 | return -EINVAL; | |
2484 | WARN((obj_priv->stride & (512 - 1)), | |
2485 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2486 | obj_priv->gtt_offset); | |
de151cf6 JB |
2487 | break; |
2488 | case I915_TILING_Y: | |
0f973f27 JB |
2489 | if (!obj_priv->stride) |
2490 | return -EINVAL; | |
2491 | WARN((obj_priv->stride & (128 - 1)), | |
2492 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2493 | obj_priv->gtt_offset); | |
de151cf6 JB |
2494 | break; |
2495 | } | |
2496 | ||
2cf34d7b | 2497 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2498 | if (ret < 0) |
2499 | return ret; | |
de151cf6 | 2500 | |
ae3db24a DV |
2501 | obj_priv->fence_reg = ret; |
2502 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2503 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2504 | |
de151cf6 JB |
2505 | reg->obj = obj; |
2506 | ||
e259befd CW |
2507 | switch (INTEL_INFO(dev)->gen) { |
2508 | case 6: | |
4e901fdc | 2509 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2510 | break; |
2511 | case 5: | |
2512 | case 4: | |
de151cf6 | 2513 | i965_write_fence_reg(reg); |
e259befd CW |
2514 | break; |
2515 | case 3: | |
de151cf6 | 2516 | i915_write_fence_reg(reg); |
e259befd CW |
2517 | break; |
2518 | case 2: | |
de151cf6 | 2519 | i830_write_fence_reg(reg); |
e259befd CW |
2520 | break; |
2521 | } | |
d9ddcb96 | 2522 | |
ae3db24a DV |
2523 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2524 | obj_priv->tiling_mode); | |
1c5d22f7 | 2525 | |
d9ddcb96 | 2526 | return 0; |
de151cf6 JB |
2527 | } |
2528 | ||
2529 | /** | |
2530 | * i915_gem_clear_fence_reg - clear out fence register info | |
2531 | * @obj: object to clear | |
2532 | * | |
2533 | * Zeroes out the fence register itself and clears out the associated | |
2534 | * data structures in dev_priv and obj_priv. | |
2535 | */ | |
2536 | static void | |
2537 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2538 | { | |
2539 | struct drm_device *dev = obj->dev; | |
79e53945 | 2540 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2541 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2542 | struct drm_i915_fence_reg *reg = |
2543 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2544 | uint32_t fence_reg; |
de151cf6 | 2545 | |
e259befd CW |
2546 | switch (INTEL_INFO(dev)->gen) { |
2547 | case 6: | |
4e901fdc EA |
2548 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2549 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2550 | break; |
2551 | case 5: | |
2552 | case 4: | |
de151cf6 | 2553 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2554 | break; |
2555 | case 3: | |
9b74f734 | 2556 | if (obj_priv->fence_reg >= 8) |
e259befd | 2557 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2558 | else |
e259befd CW |
2559 | case 2: |
2560 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2561 | |
2562 | I915_WRITE(fence_reg, 0); | |
e259befd | 2563 | break; |
dc529a4f | 2564 | } |
de151cf6 | 2565 | |
007cc8ac | 2566 | reg->obj = NULL; |
de151cf6 | 2567 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2568 | list_del_init(®->lru_list); |
de151cf6 JB |
2569 | } |
2570 | ||
52dc7d32 CW |
2571 | /** |
2572 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2573 | * to the buffer to finish, and then resets the fence register. | |
2574 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2575 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2576 | * |
2577 | * Zeroes out the fence register itself and clears out the associated | |
2578 | * data structures in dev_priv and obj_priv. | |
2579 | */ | |
2580 | int | |
2cf34d7b CW |
2581 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2582 | bool interruptible) | |
52dc7d32 CW |
2583 | { |
2584 | struct drm_device *dev = obj->dev; | |
53640e1d | 2585 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2586 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2587 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2588 | |
2589 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2590 | return 0; | |
2591 | ||
10ae9bd2 DV |
2592 | /* If we've changed tiling, GTT-mappings of the object |
2593 | * need to re-fault to ensure that the correct fence register | |
2594 | * setup is in place. | |
2595 | */ | |
2596 | i915_gem_release_mmap(obj); | |
2597 | ||
52dc7d32 CW |
2598 | /* On the i915, GPU access to tiled buffers is via a fence, |
2599 | * therefore we must wait for any outstanding access to complete | |
2600 | * before clearing the fence. | |
2601 | */ | |
53640e1d CW |
2602 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2603 | if (reg->gpu) { | |
52dc7d32 CW |
2604 | int ret; |
2605 | ||
2cf34d7b | 2606 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad | 2607 | if (ret) |
2dafb1e0 CW |
2608 | return ret; |
2609 | ||
2cf34d7b | 2610 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2611 | if (ret) |
52dc7d32 | 2612 | return ret; |
53640e1d CW |
2613 | |
2614 | reg->gpu = false; | |
52dc7d32 CW |
2615 | } |
2616 | ||
4a726612 | 2617 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2618 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2619 | |
2620 | return 0; | |
2621 | } | |
2622 | ||
673a394b EA |
2623 | /** |
2624 | * Finds free space in the GTT aperture and binds the object there. | |
2625 | */ | |
2626 | static int | |
2627 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2628 | { | |
2629 | struct drm_device *dev = obj->dev; | |
2630 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2631 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2632 | struct drm_mm_node *free_space; |
4bdadb97 | 2633 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2634 | int ret; |
673a394b | 2635 | |
bb6baf76 | 2636 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2637 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2638 | return -EINVAL; | |
2639 | } | |
2640 | ||
673a394b | 2641 | if (alignment == 0) |
0f973f27 | 2642 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2643 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2644 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2645 | return -EINVAL; | |
2646 | } | |
2647 | ||
654fc607 CW |
2648 | /* If the object is bigger than the entire aperture, reject it early |
2649 | * before evicting everything in a vain attempt to find space. | |
2650 | */ | |
73aa808f | 2651 | if (obj->size > dev_priv->mm.gtt_total) { |
654fc607 CW |
2652 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2653 | return -E2BIG; | |
2654 | } | |
2655 | ||
673a394b EA |
2656 | search_free: |
2657 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2658 | obj->size, alignment, 0); | |
9af90d19 | 2659 | if (free_space != NULL) |
673a394b EA |
2660 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
2661 | alignment); | |
673a394b EA |
2662 | if (obj_priv->gtt_space == NULL) { |
2663 | /* If the gtt is empty and we're still having trouble | |
2664 | * fitting our object in, we're out of memory. | |
2665 | */ | |
0108a3ed | 2666 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2667 | if (ret) |
673a394b | 2668 | return ret; |
9731129c | 2669 | |
673a394b EA |
2670 | goto search_free; |
2671 | } | |
2672 | ||
4bdadb97 | 2673 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2674 | if (ret) { |
2675 | drm_mm_put_block(obj_priv->gtt_space); | |
2676 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2677 | |
2678 | if (ret == -ENOMEM) { | |
2679 | /* first try to clear up some space from the GTT */ | |
0108a3ed DV |
2680 | ret = i915_gem_evict_something(dev, obj->size, |
2681 | alignment); | |
07f73f69 | 2682 | if (ret) { |
07f73f69 | 2683 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2684 | if (gfpmask) { |
2685 | gfpmask = 0; | |
2686 | goto search_free; | |
07f73f69 CW |
2687 | } |
2688 | ||
2689 | return ret; | |
2690 | } | |
2691 | ||
2692 | goto search_free; | |
2693 | } | |
2694 | ||
673a394b EA |
2695 | return ret; |
2696 | } | |
2697 | ||
673a394b EA |
2698 | /* Create an AGP memory structure pointing at our pages, and bind it |
2699 | * into the GTT. | |
2700 | */ | |
2701 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2702 | obj_priv->pages, |
07f73f69 | 2703 | obj->size >> PAGE_SHIFT, |
9af90d19 | 2704 | obj_priv->gtt_space->start, |
ba1eb1d8 | 2705 | obj_priv->agp_type); |
673a394b | 2706 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2707 | i915_gem_object_put_pages(obj); |
673a394b EA |
2708 | drm_mm_put_block(obj_priv->gtt_space); |
2709 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2710 | |
0108a3ed | 2711 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2712 | if (ret) |
07f73f69 | 2713 | return ret; |
07f73f69 CW |
2714 | |
2715 | goto search_free; | |
673a394b | 2716 | } |
673a394b | 2717 | |
bf1a1092 | 2718 | /* keep track of bounds object by adding it to the inactive list */ |
69dc4987 | 2719 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
73aa808f | 2720 | i915_gem_info_add_gtt(dev_priv, obj->size); |
bf1a1092 | 2721 | |
673a394b EA |
2722 | /* Assert that the object is not currently in any GPU domain. As it |
2723 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2724 | * a GPU cache | |
2725 | */ | |
21d509e3 CW |
2726 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2727 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2728 | |
9af90d19 | 2729 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
1c5d22f7 CW |
2730 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2731 | ||
673a394b EA |
2732 | return 0; |
2733 | } | |
2734 | ||
2735 | void | |
2736 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2737 | { | |
23010e43 | 2738 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2739 | |
2740 | /* If we don't have a page list set up, then we're not pinned | |
2741 | * to GPU, and we can ignore the cache flush because it'll happen | |
2742 | * again at bind time. | |
2743 | */ | |
856fa198 | 2744 | if (obj_priv->pages == NULL) |
673a394b EA |
2745 | return; |
2746 | ||
1c5d22f7 | 2747 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2748 | |
856fa198 | 2749 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2750 | } |
2751 | ||
e47c68e9 | 2752 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2753 | static int |
ba3d8d74 DV |
2754 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2755 | bool pipelined) | |
e47c68e9 EA |
2756 | { |
2757 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2758 | uint32_t old_write_domain; |
e47c68e9 EA |
2759 | |
2760 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2761 | return 0; |
e47c68e9 EA |
2762 | |
2763 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2764 | old_write_domain = obj->write_domain; |
c78ec30b | 2765 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2766 | to_intel_bo(obj)->ring, |
2767 | 0, obj->write_domain); | |
48b956c5 | 2768 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2769 | |
2770 | trace_i915_gem_object_change_domain(obj, | |
2771 | obj->read_domains, | |
2772 | old_write_domain); | |
ba3d8d74 DV |
2773 | |
2774 | if (pipelined) | |
2775 | return 0; | |
2776 | ||
2cf34d7b | 2777 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2778 | } |
2779 | ||
2780 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2781 | static void | |
2782 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2783 | { | |
1c5d22f7 CW |
2784 | uint32_t old_write_domain; |
2785 | ||
e47c68e9 EA |
2786 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2787 | return; | |
2788 | ||
2789 | /* No actual flushing is required for the GTT write domain. Writes | |
2790 | * to it immediately go to main memory as far as we know, so there's | |
2791 | * no chipset flush. It also doesn't land in render cache. | |
2792 | */ | |
1c5d22f7 | 2793 | old_write_domain = obj->write_domain; |
e47c68e9 | 2794 | obj->write_domain = 0; |
1c5d22f7 CW |
2795 | |
2796 | trace_i915_gem_object_change_domain(obj, | |
2797 | obj->read_domains, | |
2798 | old_write_domain); | |
e47c68e9 EA |
2799 | } |
2800 | ||
2801 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2802 | static void | |
2803 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2804 | { | |
2805 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2806 | uint32_t old_write_domain; |
e47c68e9 EA |
2807 | |
2808 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2809 | return; | |
2810 | ||
2811 | i915_gem_clflush_object(obj); | |
2812 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2813 | old_write_domain = obj->write_domain; |
e47c68e9 | 2814 | obj->write_domain = 0; |
1c5d22f7 CW |
2815 | |
2816 | trace_i915_gem_object_change_domain(obj, | |
2817 | obj->read_domains, | |
2818 | old_write_domain); | |
e47c68e9 EA |
2819 | } |
2820 | ||
2ef7eeaa EA |
2821 | /** |
2822 | * Moves a single object to the GTT read, and possibly write domain. | |
2823 | * | |
2824 | * This function returns when the move is complete, including waiting on | |
2825 | * flushes to occur. | |
2826 | */ | |
79e53945 | 2827 | int |
2ef7eeaa EA |
2828 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2829 | { | |
23010e43 | 2830 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2831 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2832 | int ret; |
2ef7eeaa | 2833 | |
02354392 EA |
2834 | /* Not valid to be called on unbound objects. */ |
2835 | if (obj_priv->gtt_space == NULL) | |
2836 | return -EINVAL; | |
2837 | ||
ba3d8d74 | 2838 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
2dafb1e0 CW |
2839 | if (ret != 0) |
2840 | return ret; | |
2841 | ||
7213342d | 2842 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2843 | |
ba3d8d74 | 2844 | if (write) { |
2cf34d7b | 2845 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2846 | if (ret) |
2847 | return ret; | |
ba3d8d74 | 2848 | } |
e47c68e9 | 2849 | |
1c5d22f7 CW |
2850 | old_write_domain = obj->write_domain; |
2851 | old_read_domains = obj->read_domains; | |
2852 | ||
e47c68e9 EA |
2853 | /* It should now be out of any other write domains, and we can update |
2854 | * the domain values for our changes. | |
2855 | */ | |
2856 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2857 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2858 | if (write) { | |
7213342d | 2859 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2860 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2861 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2862 | } |
2863 | ||
1c5d22f7 CW |
2864 | trace_i915_gem_object_change_domain(obj, |
2865 | old_read_domains, | |
2866 | old_write_domain); | |
2867 | ||
e47c68e9 EA |
2868 | return 0; |
2869 | } | |
2870 | ||
b9241ea3 ZW |
2871 | /* |
2872 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2873 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2874 | */ | |
2875 | int | |
48b956c5 CW |
2876 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2877 | bool pipelined) | |
b9241ea3 | 2878 | { |
23010e43 | 2879 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2880 | uint32_t old_read_domains; |
b9241ea3 ZW |
2881 | int ret; |
2882 | ||
2883 | /* Not valid to be called on unbound objects. */ | |
2884 | if (obj_priv->gtt_space == NULL) | |
2885 | return -EINVAL; | |
2886 | ||
ced270fa | 2887 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
2dafb1e0 CW |
2888 | if (ret) |
2889 | return ret; | |
b9241ea3 | 2890 | |
ced270fa CW |
2891 | /* Currently, we are always called from an non-interruptible context. */ |
2892 | if (!pipelined) { | |
2893 | ret = i915_gem_object_wait_rendering(obj, false); | |
2894 | if (ret) | |
b9241ea3 ZW |
2895 | return ret; |
2896 | } | |
2897 | ||
b118c1e3 CW |
2898 | i915_gem_object_flush_cpu_write_domain(obj); |
2899 | ||
b9241ea3 | 2900 | old_read_domains = obj->read_domains; |
c78ec30b | 2901 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2902 | |
2903 | trace_i915_gem_object_change_domain(obj, | |
2904 | old_read_domains, | |
ba3d8d74 | 2905 | obj->write_domain); |
b9241ea3 ZW |
2906 | |
2907 | return 0; | |
2908 | } | |
2909 | ||
e47c68e9 EA |
2910 | /** |
2911 | * Moves a single object to the CPU read, and possibly write domain. | |
2912 | * | |
2913 | * This function returns when the move is complete, including waiting on | |
2914 | * flushes to occur. | |
2915 | */ | |
2916 | static int | |
2917 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2918 | { | |
1c5d22f7 | 2919 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2920 | int ret; |
2921 | ||
ba3d8d74 | 2922 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2923 | if (ret != 0) |
2924 | return ret; | |
2ef7eeaa | 2925 | |
e47c68e9 | 2926 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2927 | |
e47c68e9 EA |
2928 | /* If we have a partially-valid cache of the object in the CPU, |
2929 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2930 | */ |
e47c68e9 | 2931 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2932 | |
7213342d | 2933 | if (write) { |
2cf34d7b | 2934 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
2935 | if (ret) |
2936 | return ret; | |
2937 | } | |
2938 | ||
1c5d22f7 CW |
2939 | old_write_domain = obj->write_domain; |
2940 | old_read_domains = obj->read_domains; | |
2941 | ||
e47c68e9 EA |
2942 | /* Flush the CPU cache if it's still invalid. */ |
2943 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2944 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2945 | |
e47c68e9 | 2946 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2947 | } |
2948 | ||
2949 | /* It should now be out of any other write domains, and we can update | |
2950 | * the domain values for our changes. | |
2951 | */ | |
e47c68e9 EA |
2952 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2953 | ||
2954 | /* If we're writing through the CPU, then the GPU read domains will | |
2955 | * need to be invalidated at next use. | |
2956 | */ | |
2957 | if (write) { | |
c78ec30b | 2958 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
2959 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
2960 | } | |
2ef7eeaa | 2961 | |
1c5d22f7 CW |
2962 | trace_i915_gem_object_change_domain(obj, |
2963 | old_read_domains, | |
2964 | old_write_domain); | |
2965 | ||
2ef7eeaa EA |
2966 | return 0; |
2967 | } | |
2968 | ||
673a394b EA |
2969 | /* |
2970 | * Set the next domain for the specified object. This | |
2971 | * may not actually perform the necessary flushing/invaliding though, | |
2972 | * as that may want to be batched with other set_domain operations | |
2973 | * | |
2974 | * This is (we hope) the only really tricky part of gem. The goal | |
2975 | * is fairly simple -- track which caches hold bits of the object | |
2976 | * and make sure they remain coherent. A few concrete examples may | |
2977 | * help to explain how it works. For shorthand, we use the notation | |
2978 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2979 | * a pair of read and write domain masks. | |
2980 | * | |
2981 | * Case 1: the batch buffer | |
2982 | * | |
2983 | * 1. Allocated | |
2984 | * 2. Written by CPU | |
2985 | * 3. Mapped to GTT | |
2986 | * 4. Read by GPU | |
2987 | * 5. Unmapped from GTT | |
2988 | * 6. Freed | |
2989 | * | |
2990 | * Let's take these a step at a time | |
2991 | * | |
2992 | * 1. Allocated | |
2993 | * Pages allocated from the kernel may still have | |
2994 | * cache contents, so we set them to (CPU, CPU) always. | |
2995 | * 2. Written by CPU (using pwrite) | |
2996 | * The pwrite function calls set_domain (CPU, CPU) and | |
2997 | * this function does nothing (as nothing changes) | |
2998 | * 3. Mapped by GTT | |
2999 | * This function asserts that the object is not | |
3000 | * currently in any GPU-based read or write domains | |
3001 | * 4. Read by GPU | |
3002 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3003 | * As write_domain is zero, this function adds in the | |
3004 | * current read domains (CPU+COMMAND, 0). | |
3005 | * flush_domains is set to CPU. | |
3006 | * invalidate_domains is set to COMMAND | |
3007 | * clflush is run to get data out of the CPU caches | |
3008 | * then i915_dev_set_domain calls i915_gem_flush to | |
3009 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3010 | * 5. Unmapped from GTT | |
3011 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3012 | * flush_domains and invalidate_domains end up both zero | |
3013 | * so no flushing/invalidating happens | |
3014 | * 6. Freed | |
3015 | * yay, done | |
3016 | * | |
3017 | * Case 2: The shared render buffer | |
3018 | * | |
3019 | * 1. Allocated | |
3020 | * 2. Mapped to GTT | |
3021 | * 3. Read/written by GPU | |
3022 | * 4. set_domain to (CPU,CPU) | |
3023 | * 5. Read/written by CPU | |
3024 | * 6. Read/written by GPU | |
3025 | * | |
3026 | * 1. Allocated | |
3027 | * Same as last example, (CPU, CPU) | |
3028 | * 2. Mapped to GTT | |
3029 | * Nothing changes (assertions find that it is not in the GPU) | |
3030 | * 3. Read/written by GPU | |
3031 | * execbuffer calls set_domain (RENDER, RENDER) | |
3032 | * flush_domains gets CPU | |
3033 | * invalidate_domains gets GPU | |
3034 | * clflush (obj) | |
3035 | * MI_FLUSH and drm_agp_chipset_flush | |
3036 | * 4. set_domain (CPU, CPU) | |
3037 | * flush_domains gets GPU | |
3038 | * invalidate_domains gets CPU | |
3039 | * wait_rendering (obj) to make sure all drawing is complete. | |
3040 | * This will include an MI_FLUSH to get the data from GPU | |
3041 | * to memory | |
3042 | * clflush (obj) to invalidate the CPU cache | |
3043 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3044 | * 5. Read/written by CPU | |
3045 | * cache lines are loaded and dirtied | |
3046 | * 6. Read written by GPU | |
3047 | * Same as last GPU access | |
3048 | * | |
3049 | * Case 3: The constant buffer | |
3050 | * | |
3051 | * 1. Allocated | |
3052 | * 2. Written by CPU | |
3053 | * 3. Read by GPU | |
3054 | * 4. Updated (written) by CPU again | |
3055 | * 5. Read by GPU | |
3056 | * | |
3057 | * 1. Allocated | |
3058 | * (CPU, CPU) | |
3059 | * 2. Written by CPU | |
3060 | * (CPU, CPU) | |
3061 | * 3. Read by GPU | |
3062 | * (CPU+RENDER, 0) | |
3063 | * flush_domains = CPU | |
3064 | * invalidate_domains = RENDER | |
3065 | * clflush (obj) | |
3066 | * MI_FLUSH | |
3067 | * drm_agp_chipset_flush | |
3068 | * 4. Updated (written) by CPU again | |
3069 | * (CPU, CPU) | |
3070 | * flush_domains = 0 (no previous write domain) | |
3071 | * invalidate_domains = 0 (no new read domains) | |
3072 | * 5. Read by GPU | |
3073 | * (CPU+RENDER, 0) | |
3074 | * flush_domains = CPU | |
3075 | * invalidate_domains = RENDER | |
3076 | * clflush (obj) | |
3077 | * MI_FLUSH | |
3078 | * drm_agp_chipset_flush | |
3079 | */ | |
c0d90829 | 3080 | static void |
b6651458 CW |
3081 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
3082 | struct intel_ring_buffer *ring) | |
673a394b EA |
3083 | { |
3084 | struct drm_device *dev = obj->dev; | |
9220434a | 3085 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 3086 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3087 | uint32_t invalidate_domains = 0; |
3088 | uint32_t flush_domains = 0; | |
1c5d22f7 | 3089 | uint32_t old_read_domains; |
e47c68e9 | 3090 | |
652c393a JB |
3091 | intel_mark_busy(dev, obj); |
3092 | ||
673a394b EA |
3093 | /* |
3094 | * If the object isn't moving to a new write domain, | |
3095 | * let the object stay in multiple read domains | |
3096 | */ | |
8b0e378a EA |
3097 | if (obj->pending_write_domain == 0) |
3098 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3099 | else |
3100 | obj_priv->dirty = 1; | |
3101 | ||
3102 | /* | |
3103 | * Flush the current write domain if | |
3104 | * the new read domains don't match. Invalidate | |
3105 | * any read domains which differ from the old | |
3106 | * write domain | |
3107 | */ | |
8b0e378a | 3108 | if (obj->write_domain && |
c6afd658 CW |
3109 | (obj->write_domain != obj->pending_read_domains || |
3110 | obj_priv->ring != ring)) { | |
673a394b | 3111 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3112 | invalidate_domains |= |
3113 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3114 | } |
3115 | /* | |
3116 | * Invalidate any read caches which may have | |
3117 | * stale data. That is, any new read domains. | |
3118 | */ | |
8b0e378a | 3119 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3120 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3121 | i915_gem_clflush_object(obj); |
673a394b | 3122 | |
1c5d22f7 CW |
3123 | old_read_domains = obj->read_domains; |
3124 | ||
efbeed96 EA |
3125 | /* The actual obj->write_domain will be updated with |
3126 | * pending_write_domain after we emit the accumulated flush for all | |
3127 | * of our domain changes in execbuffers (which clears objects' | |
3128 | * write_domains). So if we have a current write domain that we | |
3129 | * aren't changing, set pending_write_domain to that. | |
3130 | */ | |
3131 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3132 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3133 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
3134 | |
3135 | dev->invalidate_domains |= invalidate_domains; | |
3136 | dev->flush_domains |= flush_domains; | |
b6651458 | 3137 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
9220434a | 3138 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
b6651458 CW |
3139 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
3140 | dev_priv->mm.flush_rings |= ring->id; | |
1c5d22f7 CW |
3141 | |
3142 | trace_i915_gem_object_change_domain(obj, | |
3143 | old_read_domains, | |
3144 | obj->write_domain); | |
673a394b EA |
3145 | } |
3146 | ||
3147 | /** | |
e47c68e9 | 3148 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3149 | * |
e47c68e9 EA |
3150 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3151 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3152 | */ |
e47c68e9 EA |
3153 | static void |
3154 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3155 | { |
23010e43 | 3156 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3157 | |
e47c68e9 EA |
3158 | if (!obj_priv->page_cpu_valid) |
3159 | return; | |
3160 | ||
3161 | /* If we're partially in the CPU read domain, finish moving it in. | |
3162 | */ | |
3163 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3164 | int i; | |
3165 | ||
3166 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3167 | if (obj_priv->page_cpu_valid[i]) | |
3168 | continue; | |
856fa198 | 3169 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3170 | } |
e47c68e9 EA |
3171 | } |
3172 | ||
3173 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3174 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3175 | */ | |
9a298b2a | 3176 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3177 | obj_priv->page_cpu_valid = NULL; |
3178 | } | |
3179 | ||
3180 | /** | |
3181 | * Set the CPU read domain on a range of the object. | |
3182 | * | |
3183 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3184 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3185 | * pages have been flushed, and will be respected by | |
3186 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3187 | * of the whole object. | |
3188 | * | |
3189 | * This function returns when the move is complete, including waiting on | |
3190 | * flushes to occur. | |
3191 | */ | |
3192 | static int | |
3193 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3194 | uint64_t offset, uint64_t size) | |
3195 | { | |
23010e43 | 3196 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3197 | uint32_t old_read_domains; |
e47c68e9 | 3198 | int i, ret; |
673a394b | 3199 | |
e47c68e9 EA |
3200 | if (offset == 0 && size == obj->size) |
3201 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3202 | |
ba3d8d74 | 3203 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3204 | if (ret != 0) |
6a47baa6 | 3205 | return ret; |
e47c68e9 EA |
3206 | i915_gem_object_flush_gtt_write_domain(obj); |
3207 | ||
3208 | /* If we're already fully in the CPU read domain, we're done. */ | |
3209 | if (obj_priv->page_cpu_valid == NULL && | |
3210 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3211 | return 0; | |
673a394b | 3212 | |
e47c68e9 EA |
3213 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3214 | * newly adding I915_GEM_DOMAIN_CPU | |
3215 | */ | |
673a394b | 3216 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3217 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3218 | GFP_KERNEL); | |
e47c68e9 EA |
3219 | if (obj_priv->page_cpu_valid == NULL) |
3220 | return -ENOMEM; | |
3221 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3222 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3223 | |
3224 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3225 | * perspective. | |
3226 | */ | |
e47c68e9 EA |
3227 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3228 | i++) { | |
673a394b EA |
3229 | if (obj_priv->page_cpu_valid[i]) |
3230 | continue; | |
3231 | ||
856fa198 | 3232 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3233 | |
3234 | obj_priv->page_cpu_valid[i] = 1; | |
3235 | } | |
3236 | ||
e47c68e9 EA |
3237 | /* It should now be out of any other write domains, and we can update |
3238 | * the domain values for our changes. | |
3239 | */ | |
3240 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3241 | ||
1c5d22f7 | 3242 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3243 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3244 | ||
1c5d22f7 CW |
3245 | trace_i915_gem_object_change_domain(obj, |
3246 | old_read_domains, | |
3247 | obj->write_domain); | |
3248 | ||
673a394b EA |
3249 | return 0; |
3250 | } | |
3251 | ||
673a394b EA |
3252 | /** |
3253 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3254 | */ | |
3255 | static int | |
9af90d19 CW |
3256 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
3257 | struct drm_file *file_priv, | |
3258 | struct drm_i915_gem_exec_object2 *entry) | |
673a394b | 3259 | { |
9af90d19 | 3260 | struct drm_device *dev = obj->base.dev; |
0839ccb8 | 3261 | drm_i915_private_t *dev_priv = dev->dev_private; |
2549d6c2 | 3262 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
9af90d19 CW |
3263 | struct drm_gem_object *target_obj = NULL; |
3264 | uint32_t target_handle = 0; | |
3265 | int i, ret = 0; | |
673a394b | 3266 | |
2549d6c2 | 3267 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
673a394b | 3268 | for (i = 0; i < entry->relocation_count; i++) { |
2549d6c2 | 3269 | struct drm_i915_gem_relocation_entry reloc; |
9af90d19 | 3270 | uint32_t target_offset; |
673a394b | 3271 | |
9af90d19 CW |
3272 | if (__copy_from_user_inatomic(&reloc, |
3273 | user_relocs+i, | |
3274 | sizeof(reloc))) { | |
3275 | ret = -EFAULT; | |
3276 | break; | |
76446cac | 3277 | } |
76446cac | 3278 | |
9af90d19 CW |
3279 | if (reloc.target_handle != target_handle) { |
3280 | drm_gem_object_unreference(target_obj); | |
673a394b | 3281 | |
9af90d19 CW |
3282 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3283 | reloc.target_handle); | |
3284 | if (target_obj == NULL) { | |
3285 | ret = -ENOENT; | |
3286 | break; | |
3287 | } | |
3288 | ||
3289 | target_handle = reloc.target_handle; | |
673a394b | 3290 | } |
9af90d19 | 3291 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
673a394b | 3292 | |
8542a0bb CW |
3293 | #if WATCH_RELOC |
3294 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3295 | "read %08x write %08x gtt %08x " | |
3296 | "presumed %08x delta %08x\n", | |
3297 | __func__, | |
3298 | obj, | |
2549d6c2 CW |
3299 | (int) reloc.offset, |
3300 | (int) reloc.target_handle, | |
3301 | (int) reloc.read_domains, | |
3302 | (int) reloc.write_domain, | |
9af90d19 | 3303 | (int) target_offset, |
2549d6c2 CW |
3304 | (int) reloc.presumed_offset, |
3305 | reloc.delta); | |
8542a0bb CW |
3306 | #endif |
3307 | ||
673a394b EA |
3308 | /* The target buffer should have appeared before us in the |
3309 | * exec_object list, so it should have a GTT space bound by now. | |
3310 | */ | |
9af90d19 | 3311 | if (target_offset == 0) { |
673a394b | 3312 | DRM_ERROR("No GTT space found for object %d\n", |
2549d6c2 | 3313 | reloc.target_handle); |
9af90d19 CW |
3314 | ret = -EINVAL; |
3315 | break; | |
673a394b EA |
3316 | } |
3317 | ||
8542a0bb | 3318 | /* Validate that the target is in a valid r/w GPU domain */ |
2549d6c2 | 3319 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
16edd550 DV |
3320 | DRM_ERROR("reloc with multiple write domains: " |
3321 | "obj %p target %d offset %d " | |
3322 | "read %08x write %08x", | |
2549d6c2 CW |
3323 | obj, reloc.target_handle, |
3324 | (int) reloc.offset, | |
3325 | reloc.read_domains, | |
3326 | reloc.write_domain); | |
9af90d19 CW |
3327 | ret = -EINVAL; |
3328 | break; | |
16edd550 | 3329 | } |
2549d6c2 CW |
3330 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
3331 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3332 | DRM_ERROR("reloc with read/write CPU domains: " |
3333 | "obj %p target %d offset %d " | |
3334 | "read %08x write %08x", | |
2549d6c2 CW |
3335 | obj, reloc.target_handle, |
3336 | (int) reloc.offset, | |
3337 | reloc.read_domains, | |
3338 | reloc.write_domain); | |
9af90d19 CW |
3339 | ret = -EINVAL; |
3340 | break; | |
e47c68e9 | 3341 | } |
2549d6c2 CW |
3342 | if (reloc.write_domain && target_obj->pending_write_domain && |
3343 | reloc.write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3344 | DRM_ERROR("Write domain conflict: " |
3345 | "obj %p target %d offset %d " | |
3346 | "new %08x old %08x\n", | |
2549d6c2 CW |
3347 | obj, reloc.target_handle, |
3348 | (int) reloc.offset, | |
3349 | reloc.write_domain, | |
673a394b | 3350 | target_obj->pending_write_domain); |
9af90d19 CW |
3351 | ret = -EINVAL; |
3352 | break; | |
673a394b EA |
3353 | } |
3354 | ||
2549d6c2 | 3355 | target_obj->pending_read_domains |= reloc.read_domains; |
878a3c37 | 3356 | target_obj->pending_write_domain |= reloc.write_domain; |
673a394b EA |
3357 | |
3358 | /* If the relocation already has the right value in it, no | |
3359 | * more work needs to be done. | |
3360 | */ | |
9af90d19 | 3361 | if (target_offset == reloc.presumed_offset) |
673a394b | 3362 | continue; |
673a394b | 3363 | |
8542a0bb | 3364 | /* Check that the relocation address is valid... */ |
9af90d19 | 3365 | if (reloc.offset > obj->base.size - 4) { |
8542a0bb CW |
3366 | DRM_ERROR("Relocation beyond object bounds: " |
3367 | "obj %p target %d offset %d size %d.\n", | |
2549d6c2 | 3368 | obj, reloc.target_handle, |
9af90d19 CW |
3369 | (int) reloc.offset, (int) obj->base.size); |
3370 | ret = -EINVAL; | |
3371 | break; | |
8542a0bb | 3372 | } |
2549d6c2 | 3373 | if (reloc.offset & 3) { |
8542a0bb CW |
3374 | DRM_ERROR("Relocation not 4-byte aligned: " |
3375 | "obj %p target %d offset %d.\n", | |
2549d6c2 CW |
3376 | obj, reloc.target_handle, |
3377 | (int) reloc.offset); | |
9af90d19 CW |
3378 | ret = -EINVAL; |
3379 | break; | |
8542a0bb CW |
3380 | } |
3381 | ||
3382 | /* and points to somewhere within the target object. */ | |
2549d6c2 | 3383 | if (reloc.delta >= target_obj->size) { |
8542a0bb CW |
3384 | DRM_ERROR("Relocation beyond target object bounds: " |
3385 | "obj %p target %d delta %d size %d.\n", | |
2549d6c2 CW |
3386 | obj, reloc.target_handle, |
3387 | (int) reloc.delta, (int) target_obj->size); | |
9af90d19 CW |
3388 | ret = -EINVAL; |
3389 | break; | |
673a394b EA |
3390 | } |
3391 | ||
9af90d19 CW |
3392 | reloc.delta += target_offset; |
3393 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
f0c43d9b CW |
3394 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
3395 | char *vaddr; | |
673a394b | 3396 | |
c48c43e4 | 3397 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
f0c43d9b | 3398 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
c48c43e4 | 3399 | kunmap_atomic(vaddr); |
f0c43d9b CW |
3400 | } else { |
3401 | uint32_t __iomem *reloc_entry; | |
3402 | void __iomem *reloc_page; | |
b962442e | 3403 | |
9af90d19 CW |
3404 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
3405 | if (ret) | |
3406 | break; | |
b962442e | 3407 | |
f0c43d9b | 3408 | /* Map the page containing the relocation we're going to perform. */ |
9af90d19 | 3409 | reloc.offset += obj->gtt_offset; |
f0c43d9b | 3410 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
c48c43e4 | 3411 | reloc.offset & PAGE_MASK); |
f0c43d9b CW |
3412 | reloc_entry = (uint32_t __iomem *) |
3413 | (reloc_page + (reloc.offset & ~PAGE_MASK)); | |
3414 | iowrite32(reloc.delta, reloc_entry); | |
c48c43e4 | 3415 | io_mapping_unmap_atomic(reloc_page); |
f0c43d9b | 3416 | } |
b962442e | 3417 | |
b5dc608c CW |
3418 | /* and update the user's relocation entry */ |
3419 | reloc.presumed_offset = target_offset; | |
3420 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
3421 | &reloc.presumed_offset, | |
3422 | sizeof(reloc.presumed_offset))) { | |
3423 | ret = -EFAULT; | |
3424 | break; | |
3425 | } | |
b962442e | 3426 | } |
b962442e | 3427 | |
9af90d19 | 3428 | drm_gem_object_unreference(target_obj); |
673a394b EA |
3429 | return ret; |
3430 | } | |
3431 | ||
40a5f0de | 3432 | static int |
9af90d19 CW |
3433 | i915_gem_execbuffer_pin(struct drm_device *dev, |
3434 | struct drm_file *file, | |
3435 | struct drm_gem_object **object_list, | |
3436 | struct drm_i915_gem_exec_object2 *exec_list, | |
3437 | int count) | |
40a5f0de | 3438 | { |
9af90d19 CW |
3439 | struct drm_i915_private *dev_priv = dev->dev_private; |
3440 | int ret, i, retry; | |
40a5f0de | 3441 | |
9af90d19 CW |
3442 | /* attempt to pin all of the buffers into the GTT */ |
3443 | for (retry = 0; retry < 2; retry++) { | |
3444 | ret = 0; | |
3445 | for (i = 0; i < count; i++) { | |
3446 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
3447 | struct drm_i915_gem_object *obj= to_intel_bo(object_list[i]); | |
3448 | bool need_fence = | |
3449 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3450 | obj->tiling_mode != I915_TILING_NONE; | |
3451 | ||
3452 | /* Check fence reg constraints and rebind if necessary */ | |
3453 | if (need_fence && | |
3454 | !i915_gem_object_fence_offset_ok(&obj->base, | |
3455 | obj->tiling_mode)) { | |
3456 | ret = i915_gem_object_unbind(&obj->base); | |
3457 | if (ret) | |
3458 | break; | |
3459 | } | |
40a5f0de | 3460 | |
9af90d19 CW |
3461 | ret = i915_gem_object_pin(&obj->base, entry->alignment); |
3462 | if (ret) | |
3463 | break; | |
40a5f0de | 3464 | |
9af90d19 CW |
3465 | /* |
3466 | * Pre-965 chips need a fence register set up in order | |
3467 | * to properly handle blits to/from tiled surfaces. | |
3468 | */ | |
3469 | if (need_fence) { | |
3470 | ret = i915_gem_object_get_fence_reg(&obj->base, true); | |
3471 | if (ret) { | |
3472 | i915_gem_object_unpin(&obj->base); | |
3473 | break; | |
3474 | } | |
40a5f0de | 3475 | |
9af90d19 CW |
3476 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
3477 | } | |
40a5f0de | 3478 | |
9af90d19 | 3479 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3480 | } |
3481 | ||
9af90d19 CW |
3482 | while (i--) |
3483 | i915_gem_object_unpin(object_list[i]); | |
3484 | ||
3485 | if (ret == 0) | |
3486 | break; | |
673a394b | 3487 | |
9af90d19 CW |
3488 | if (ret != -ENOSPC || retry) |
3489 | return ret; | |
3490 | ||
3491 | ret = i915_gem_evict_everything(dev); | |
3492 | if (ret) | |
3493 | return ret; | |
40a5f0de EA |
3494 | } |
3495 | ||
2bc43b5c | 3496 | return 0; |
40a5f0de EA |
3497 | } |
3498 | ||
c6afd658 CW |
3499 | static int |
3500 | i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, | |
3501 | struct drm_file *file, | |
3502 | struct intel_ring_buffer *ring, | |
3503 | struct drm_gem_object **objects, | |
3504 | int count) | |
3505 | { | |
3506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3507 | int ret, i; | |
3508 | ||
3509 | /* Zero the global flush/invalidate flags. These | |
3510 | * will be modified as new domains are computed | |
3511 | * for each object | |
3512 | */ | |
3513 | dev->invalidate_domains = 0; | |
3514 | dev->flush_domains = 0; | |
3515 | dev_priv->mm.flush_rings = 0; | |
3516 | for (i = 0; i < count; i++) | |
3517 | i915_gem_object_set_to_gpu_domain(objects[i], ring); | |
3518 | ||
3519 | if (dev->invalidate_domains | dev->flush_domains) { | |
3520 | #if WATCH_EXEC | |
3521 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3522 | __func__, | |
3523 | dev->invalidate_domains, | |
3524 | dev->flush_domains); | |
3525 | #endif | |
3526 | i915_gem_flush(dev, file, | |
3527 | dev->invalidate_domains, | |
3528 | dev->flush_domains, | |
3529 | dev_priv->mm.flush_rings); | |
3530 | } | |
3531 | ||
3532 | for (i = 0; i < count; i++) { | |
3533 | struct drm_i915_gem_object *obj = to_intel_bo(objects[i]); | |
3534 | /* XXX replace with semaphores */ | |
3535 | if (obj->ring && ring != obj->ring) { | |
3536 | ret = i915_gem_object_wait_rendering(&obj->base, true); | |
3537 | if (ret) | |
3538 | return ret; | |
3539 | } | |
3540 | } | |
3541 | ||
3542 | return 0; | |
3543 | } | |
3544 | ||
673a394b EA |
3545 | /* Throttle our rendering by waiting until the ring has completed our requests |
3546 | * emitted over 20 msec ago. | |
3547 | * | |
b962442e EA |
3548 | * Note that if we were to use the current jiffies each time around the loop, |
3549 | * we wouldn't escape the function with any frames outstanding if the time to | |
3550 | * render a frame was over 20ms. | |
3551 | * | |
673a394b EA |
3552 | * This should get us reasonable parallelism between CPU and GPU but also |
3553 | * relatively low latency when blocking on a particular request to finish. | |
3554 | */ | |
40a5f0de | 3555 | static int |
f787a5f5 | 3556 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3557 | { |
f787a5f5 CW |
3558 | struct drm_i915_private *dev_priv = dev->dev_private; |
3559 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3560 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3561 | struct drm_i915_gem_request *request; |
3562 | struct intel_ring_buffer *ring = NULL; | |
3563 | u32 seqno = 0; | |
3564 | int ret; | |
93533c29 | 3565 | |
1c25595f | 3566 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3567 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3568 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3569 | break; | |
40a5f0de | 3570 | |
f787a5f5 CW |
3571 | ring = request->ring; |
3572 | seqno = request->seqno; | |
b962442e | 3573 | } |
1c25595f | 3574 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3575 | |
f787a5f5 CW |
3576 | if (seqno == 0) |
3577 | return 0; | |
2bc43b5c | 3578 | |
f787a5f5 CW |
3579 | ret = 0; |
3580 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { | |
3581 | /* And wait for the seqno passing without holding any locks and | |
3582 | * causing extra latency for others. This is safe as the irq | |
3583 | * generation is designed to be run atomically and so is | |
3584 | * lockless. | |
3585 | */ | |
3586 | ring->user_irq_get(dev, ring); | |
3587 | ret = wait_event_interruptible(ring->irq_queue, | |
3588 | i915_seqno_passed(ring->get_seqno(dev, ring), seqno) | |
3589 | || atomic_read(&dev_priv->mm.wedged)); | |
3590 | ring->user_irq_put(dev, ring); | |
40a5f0de | 3591 | |
f787a5f5 CW |
3592 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3593 | ret = -EIO; | |
40a5f0de EA |
3594 | } |
3595 | ||
f787a5f5 CW |
3596 | if (ret == 0) |
3597 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3598 | |
3599 | return ret; | |
3600 | } | |
3601 | ||
83d60795 | 3602 | static int |
2549d6c2 CW |
3603 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3604 | uint64_t exec_offset) | |
83d60795 CW |
3605 | { |
3606 | uint32_t exec_start, exec_len; | |
3607 | ||
3608 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3609 | exec_len = (uint32_t) exec->batch_len; | |
3610 | ||
3611 | if ((exec_start | exec_len) & 0x7) | |
3612 | return -EINVAL; | |
3613 | ||
3614 | if (!exec_start) | |
3615 | return -EINVAL; | |
3616 | ||
3617 | return 0; | |
3618 | } | |
3619 | ||
6b95a207 | 3620 | static int |
2549d6c2 CW |
3621 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3622 | int count) | |
6b95a207 | 3623 | { |
2549d6c2 | 3624 | int i; |
6b95a207 | 3625 | |
2549d6c2 CW |
3626 | for (i = 0; i < count; i++) { |
3627 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
3628 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); | |
6b95a207 | 3629 | |
2549d6c2 CW |
3630 | if (!access_ok(VERIFY_READ, ptr, length)) |
3631 | return -EFAULT; | |
40a5f0de | 3632 | |
b5dc608c CW |
3633 | /* we may also need to update the presumed offsets */ |
3634 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3635 | return -EFAULT; | |
3636 | ||
2549d6c2 CW |
3637 | if (fault_in_pages_readable(ptr, length)) |
3638 | return -EFAULT; | |
6b95a207 | 3639 | } |
6b95a207 | 3640 | |
83d60795 | 3641 | return 0; |
6b95a207 KH |
3642 | } |
3643 | ||
8dc5d147 | 3644 | static int |
76446cac | 3645 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3646 | struct drm_file *file, |
76446cac JB |
3647 | struct drm_i915_gem_execbuffer2 *args, |
3648 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3649 | { |
3650 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3651 | struct drm_gem_object **object_list = NULL; |
3652 | struct drm_gem_object *batch_obj; | |
b70d11da | 3653 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3654 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3655 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3656 | int ret, i, flips; |
673a394b | 3657 | uint64_t exec_offset; |
673a394b | 3658 | |
852835f3 ZN |
3659 | struct intel_ring_buffer *ring = NULL; |
3660 | ||
30dbf0c0 CW |
3661 | ret = i915_gem_check_is_wedged(dev); |
3662 | if (ret) | |
3663 | return ret; | |
3664 | ||
2549d6c2 CW |
3665 | ret = validate_exec_list(exec_list, args->buffer_count); |
3666 | if (ret) | |
3667 | return ret; | |
3668 | ||
673a394b EA |
3669 | #if WATCH_EXEC |
3670 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3671 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3672 | #endif | |
549f7365 CW |
3673 | switch (args->flags & I915_EXEC_RING_MASK) { |
3674 | case I915_EXEC_DEFAULT: | |
3675 | case I915_EXEC_RENDER: | |
3676 | ring = &dev_priv->render_ring; | |
3677 | break; | |
3678 | case I915_EXEC_BSD: | |
d1b851fc | 3679 | if (!HAS_BSD(dev)) { |
549f7365 | 3680 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3681 | return -EINVAL; |
3682 | } | |
3683 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3684 | break; |
3685 | case I915_EXEC_BLT: | |
3686 | if (!HAS_BLT(dev)) { | |
3687 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3688 | return -EINVAL; | |
3689 | } | |
3690 | ring = &dev_priv->blt_ring; | |
3691 | break; | |
3692 | default: | |
3693 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3694 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3695 | return -EINVAL; | |
d1b851fc ZN |
3696 | } |
3697 | ||
4f481ed2 EA |
3698 | if (args->buffer_count < 1) { |
3699 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3700 | return -EINVAL; | |
3701 | } | |
c8e0f93a | 3702 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3703 | if (object_list == NULL) { |
3704 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3705 | args->buffer_count); |
3706 | ret = -ENOMEM; | |
3707 | goto pre_mutex_err; | |
3708 | } | |
673a394b | 3709 | |
201361a5 | 3710 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3711 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3712 | GFP_KERNEL); | |
a40e8d31 OA |
3713 | if (cliprects == NULL) { |
3714 | ret = -ENOMEM; | |
201361a5 | 3715 | goto pre_mutex_err; |
a40e8d31 | 3716 | } |
201361a5 EA |
3717 | |
3718 | ret = copy_from_user(cliprects, | |
3719 | (struct drm_clip_rect __user *) | |
3720 | (uintptr_t) args->cliprects_ptr, | |
3721 | sizeof(*cliprects) * args->num_cliprects); | |
3722 | if (ret != 0) { | |
3723 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3724 | args->num_cliprects, ret); | |
c877cdce | 3725 | ret = -EFAULT; |
201361a5 EA |
3726 | goto pre_mutex_err; |
3727 | } | |
3728 | } | |
3729 | ||
8dc5d147 CW |
3730 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3731 | if (request == NULL) { | |
3732 | ret = -ENOMEM; | |
40a5f0de | 3733 | goto pre_mutex_err; |
8dc5d147 | 3734 | } |
40a5f0de | 3735 | |
76c1dec1 CW |
3736 | ret = i915_mutex_lock_interruptible(dev); |
3737 | if (ret) | |
a198bc80 | 3738 | goto pre_mutex_err; |
673a394b EA |
3739 | |
3740 | if (dev_priv->mm.suspended) { | |
673a394b | 3741 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3742 | ret = -EBUSY; |
3743 | goto pre_mutex_err; | |
673a394b EA |
3744 | } |
3745 | ||
ac94a962 | 3746 | /* Look up object handles */ |
673a394b | 3747 | for (i = 0; i < args->buffer_count; i++) { |
9af90d19 | 3748 | object_list[i] = drm_gem_object_lookup(dev, file, |
673a394b EA |
3749 | exec_list[i].handle); |
3750 | if (object_list[i] == NULL) { | |
3751 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3752 | exec_list[i].handle, i); | |
0ce907f8 CW |
3753 | /* prevent error path from reading uninitialized data */ |
3754 | args->buffer_count = i + 1; | |
bf79cb91 | 3755 | ret = -ENOENT; |
673a394b EA |
3756 | goto err; |
3757 | } | |
b70d11da | 3758 | |
23010e43 | 3759 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3760 | if (obj_priv->in_execbuffer) { |
3761 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3762 | object_list[i]); | |
0ce907f8 CW |
3763 | /* prevent error path from reading uninitialized data */ |
3764 | args->buffer_count = i + 1; | |
bf79cb91 | 3765 | ret = -EINVAL; |
b70d11da KH |
3766 | goto err; |
3767 | } | |
3768 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3769 | } |
673a394b | 3770 | |
9af90d19 CW |
3771 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
3772 | ret = i915_gem_execbuffer_pin(dev, file, | |
3773 | object_list, exec_list, | |
3774 | args->buffer_count); | |
3775 | if (ret) | |
3776 | goto err; | |
ac94a962 | 3777 | |
9af90d19 CW |
3778 | /* The objects are in their final locations, apply the relocations. */ |
3779 | for (i = 0; i < args->buffer_count; i++) { | |
3780 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3781 | obj->base.pending_read_domains = 0; | |
3782 | obj->base.pending_write_domain = 0; | |
3783 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); | |
3784 | if (ret) | |
ac94a962 | 3785 | goto err; |
673a394b EA |
3786 | } |
3787 | ||
3788 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3789 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3790 | if (batch_obj->pending_write_domain) { |
3791 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3792 | ret = -EINVAL; | |
3793 | goto err; | |
3794 | } | |
3795 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3796 | |
9af90d19 CW |
3797 | /* Sanity check the batch buffer */ |
3798 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; | |
3799 | ret = i915_gem_check_execbuffer(args, exec_offset); | |
83d60795 CW |
3800 | if (ret != 0) { |
3801 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3802 | goto err; | |
3803 | } | |
3804 | ||
c6afd658 CW |
3805 | ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring, |
3806 | object_list, args->buffer_count); | |
3807 | if (ret) | |
3808 | goto err; | |
673a394b | 3809 | |
efbeed96 EA |
3810 | for (i = 0; i < args->buffer_count; i++) { |
3811 | struct drm_gem_object *obj = object_list[i]; | |
1c5d22f7 | 3812 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 | 3813 | obj->write_domain = obj->pending_write_domain; |
1c5d22f7 CW |
3814 | trace_i915_gem_object_change_domain(obj, |
3815 | obj->read_domains, | |
3816 | old_write_domain); | |
efbeed96 EA |
3817 | } |
3818 | ||
673a394b EA |
3819 | #if WATCH_COHERENCY |
3820 | for (i = 0; i < args->buffer_count; i++) { | |
3821 | i915_gem_object_check_coherency(object_list[i], | |
3822 | exec_list[i].handle); | |
3823 | } | |
3824 | #endif | |
3825 | ||
673a394b | 3826 | #if WATCH_EXEC |
6911a9b8 | 3827 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3828 | args->batch_len, |
3829 | __func__, | |
3830 | ~0); | |
3831 | #endif | |
3832 | ||
e59f2bac CW |
3833 | /* Check for any pending flips. As we only maintain a flip queue depth |
3834 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3835 | * to executing the batch and avoid stalling the CPU. | |
3836 | */ | |
3837 | flips = 0; | |
3838 | for (i = 0; i < args->buffer_count; i++) { | |
3839 | if (object_list[i]->write_domain) | |
3840 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3841 | } | |
3842 | if (flips) { | |
3843 | int plane, flip_mask; | |
3844 | ||
3845 | for (plane = 0; flips >> plane; plane++) { | |
3846 | if (((flips >> plane) & 1) == 0) | |
3847 | continue; | |
3848 | ||
3849 | if (plane) | |
3850 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3851 | else | |
3852 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3853 | ||
3854 | intel_ring_begin(dev, ring, 2); | |
3855 | intel_ring_emit(dev, ring, | |
3856 | MI_WAIT_FOR_EVENT | flip_mask); | |
3857 | intel_ring_emit(dev, ring, MI_NOOP); | |
3858 | intel_ring_advance(dev, ring); | |
3859 | } | |
3860 | } | |
3861 | ||
673a394b | 3862 | /* Exec the batchbuffer */ |
852835f3 | 3863 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
e59f2bac | 3864 | cliprects, exec_offset); |
673a394b EA |
3865 | if (ret) { |
3866 | DRM_ERROR("dispatch failed %d\n", ret); | |
3867 | goto err; | |
3868 | } | |
3869 | ||
3870 | /* | |
3871 | * Ensure that the commands in the batch buffer are | |
3872 | * finished before the interrupt fires | |
3873 | */ | |
8a1a49f9 | 3874 | i915_retire_commands(dev, ring); |
673a394b | 3875 | |
673a394b EA |
3876 | for (i = 0; i < args->buffer_count; i++) { |
3877 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3878 | |
617dbe27 | 3879 | i915_gem_object_move_to_active(obj, ring); |
64193406 CW |
3880 | if (obj->write_domain) |
3881 | list_move_tail(&to_intel_bo(obj)->gpu_write_list, | |
3882 | &ring->gpu_write_list); | |
673a394b | 3883 | } |
673a394b | 3884 | |
9af90d19 | 3885 | i915_add_request(dev, file, request, ring); |
8dc5d147 | 3886 | request = NULL; |
673a394b | 3887 | |
673a394b | 3888 | err: |
b70d11da KH |
3889 | for (i = 0; i < args->buffer_count; i++) { |
3890 | if (object_list[i]) { | |
23010e43 | 3891 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3892 | obj_priv->in_execbuffer = false; |
3893 | } | |
aad87dff | 3894 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3895 | } |
673a394b | 3896 | |
673a394b EA |
3897 | mutex_unlock(&dev->struct_mutex); |
3898 | ||
93533c29 | 3899 | pre_mutex_err: |
8e7d2b2c | 3900 | drm_free_large(object_list); |
9a298b2a | 3901 | kfree(cliprects); |
8dc5d147 | 3902 | kfree(request); |
673a394b EA |
3903 | |
3904 | return ret; | |
3905 | } | |
3906 | ||
76446cac JB |
3907 | /* |
3908 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3909 | * list array and passes it to the real function. | |
3910 | */ | |
3911 | int | |
3912 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3913 | struct drm_file *file_priv) | |
3914 | { | |
3915 | struct drm_i915_gem_execbuffer *args = data; | |
3916 | struct drm_i915_gem_execbuffer2 exec2; | |
3917 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3918 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3919 | int ret, i; | |
3920 | ||
3921 | #if WATCH_EXEC | |
3922 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3923 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3924 | #endif | |
3925 | ||
3926 | if (args->buffer_count < 1) { | |
3927 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3928 | return -EINVAL; | |
3929 | } | |
3930 | ||
3931 | /* Copy in the exec list from userland */ | |
3932 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3933 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3934 | if (exec_list == NULL || exec2_list == NULL) { | |
3935 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3936 | args->buffer_count); | |
3937 | drm_free_large(exec_list); | |
3938 | drm_free_large(exec2_list); | |
3939 | return -ENOMEM; | |
3940 | } | |
3941 | ret = copy_from_user(exec_list, | |
3942 | (struct drm_i915_relocation_entry __user *) | |
3943 | (uintptr_t) args->buffers_ptr, | |
3944 | sizeof(*exec_list) * args->buffer_count); | |
3945 | if (ret != 0) { | |
3946 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3947 | args->buffer_count, ret); | |
3948 | drm_free_large(exec_list); | |
3949 | drm_free_large(exec2_list); | |
3950 | return -EFAULT; | |
3951 | } | |
3952 | ||
3953 | for (i = 0; i < args->buffer_count; i++) { | |
3954 | exec2_list[i].handle = exec_list[i].handle; | |
3955 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3956 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3957 | exec2_list[i].alignment = exec_list[i].alignment; | |
3958 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 3959 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
3960 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
3961 | else | |
3962 | exec2_list[i].flags = 0; | |
3963 | } | |
3964 | ||
3965 | exec2.buffers_ptr = args->buffers_ptr; | |
3966 | exec2.buffer_count = args->buffer_count; | |
3967 | exec2.batch_start_offset = args->batch_start_offset; | |
3968 | exec2.batch_len = args->batch_len; | |
3969 | exec2.DR1 = args->DR1; | |
3970 | exec2.DR4 = args->DR4; | |
3971 | exec2.num_cliprects = args->num_cliprects; | |
3972 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 3973 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
3974 | |
3975 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
3976 | if (!ret) { | |
3977 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3978 | for (i = 0; i < args->buffer_count; i++) | |
3979 | exec_list[i].offset = exec2_list[i].offset; | |
3980 | /* ... and back out to userspace */ | |
3981 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3982 | (uintptr_t) args->buffers_ptr, | |
3983 | exec_list, | |
3984 | sizeof(*exec_list) * args->buffer_count); | |
3985 | if (ret) { | |
3986 | ret = -EFAULT; | |
3987 | DRM_ERROR("failed to copy %d exec entries " | |
3988 | "back to user (%d)\n", | |
3989 | args->buffer_count, ret); | |
3990 | } | |
76446cac JB |
3991 | } |
3992 | ||
3993 | drm_free_large(exec_list); | |
3994 | drm_free_large(exec2_list); | |
3995 | return ret; | |
3996 | } | |
3997 | ||
3998 | int | |
3999 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4000 | struct drm_file *file_priv) | |
4001 | { | |
4002 | struct drm_i915_gem_execbuffer2 *args = data; | |
4003 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4004 | int ret; | |
4005 | ||
4006 | #if WATCH_EXEC | |
4007 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4008 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4009 | #endif | |
4010 | ||
4011 | if (args->buffer_count < 1) { | |
4012 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4013 | return -EINVAL; | |
4014 | } | |
4015 | ||
4016 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4017 | if (exec2_list == NULL) { | |
4018 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4019 | args->buffer_count); | |
4020 | return -ENOMEM; | |
4021 | } | |
4022 | ret = copy_from_user(exec2_list, | |
4023 | (struct drm_i915_relocation_entry __user *) | |
4024 | (uintptr_t) args->buffers_ptr, | |
4025 | sizeof(*exec2_list) * args->buffer_count); | |
4026 | if (ret != 0) { | |
4027 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4028 | args->buffer_count, ret); | |
4029 | drm_free_large(exec2_list); | |
4030 | return -EFAULT; | |
4031 | } | |
4032 | ||
4033 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4034 | if (!ret) { | |
4035 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4036 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4037 | (uintptr_t) args->buffers_ptr, | |
4038 | exec2_list, | |
4039 | sizeof(*exec2_list) * args->buffer_count); | |
4040 | if (ret) { | |
4041 | ret = -EFAULT; | |
4042 | DRM_ERROR("failed to copy %d exec entries " | |
4043 | "back to user (%d)\n", | |
4044 | args->buffer_count, ret); | |
4045 | } | |
4046 | } | |
4047 | ||
4048 | drm_free_large(exec2_list); | |
4049 | return ret; | |
4050 | } | |
4051 | ||
673a394b EA |
4052 | int |
4053 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
4054 | { | |
4055 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4056 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4057 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4058 | int ret; |
4059 | ||
778c3544 | 4060 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4061 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4062 | |
4063 | if (obj_priv->gtt_space != NULL) { | |
4064 | if (alignment == 0) | |
4065 | alignment = i915_gem_get_gtt_alignment(obj); | |
4066 | if (obj_priv->gtt_offset & (alignment - 1)) { | |
ae7d49d8 CW |
4067 | WARN(obj_priv->pin_count, |
4068 | "bo is already pinned with incorrect alignment:" | |
4069 | " offset=%x, req.alignment=%x\n", | |
4070 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4071 | ret = i915_gem_object_unbind(obj); |
4072 | if (ret) | |
4073 | return ret; | |
4074 | } | |
4075 | } | |
4076 | ||
673a394b EA |
4077 | if (obj_priv->gtt_space == NULL) { |
4078 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 4079 | if (ret) |
673a394b | 4080 | return ret; |
22c344e9 | 4081 | } |
76446cac | 4082 | |
673a394b EA |
4083 | obj_priv->pin_count++; |
4084 | ||
4085 | /* If the object is not active and not pending a flush, | |
4086 | * remove it from the inactive list | |
4087 | */ | |
4088 | if (obj_priv->pin_count == 1) { | |
73aa808f | 4089 | i915_gem_info_add_pin(dev_priv, obj->size); |
f13d3f73 | 4090 | if (!obj_priv->active) |
69dc4987 | 4091 | list_move_tail(&obj_priv->mm_list, |
f13d3f73 | 4092 | &dev_priv->mm.pinned_list); |
673a394b | 4093 | } |
673a394b | 4094 | |
23bc5982 | 4095 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4096 | return 0; |
4097 | } | |
4098 | ||
4099 | void | |
4100 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4101 | { | |
4102 | struct drm_device *dev = obj->dev; | |
4103 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4104 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4105 | |
23bc5982 | 4106 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4107 | obj_priv->pin_count--; |
4108 | BUG_ON(obj_priv->pin_count < 0); | |
4109 | BUG_ON(obj_priv->gtt_space == NULL); | |
4110 | ||
4111 | /* If the object is no longer pinned, and is | |
4112 | * neither active nor being flushed, then stick it on | |
4113 | * the inactive list | |
4114 | */ | |
4115 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4116 | if (!obj_priv->active) |
69dc4987 | 4117 | list_move_tail(&obj_priv->mm_list, |
673a394b | 4118 | &dev_priv->mm.inactive_list); |
73aa808f | 4119 | i915_gem_info_remove_pin(dev_priv, obj->size); |
673a394b | 4120 | } |
23bc5982 | 4121 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4122 | } |
4123 | ||
4124 | int | |
4125 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4126 | struct drm_file *file_priv) | |
4127 | { | |
4128 | struct drm_i915_gem_pin *args = data; | |
4129 | struct drm_gem_object *obj; | |
4130 | struct drm_i915_gem_object *obj_priv; | |
4131 | int ret; | |
4132 | ||
1d7cfea1 CW |
4133 | ret = i915_mutex_lock_interruptible(dev); |
4134 | if (ret) | |
4135 | return ret; | |
673a394b EA |
4136 | |
4137 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4138 | if (obj == NULL) { | |
1d7cfea1 CW |
4139 | ret = -ENOENT; |
4140 | goto unlock; | |
673a394b | 4141 | } |
23010e43 | 4142 | obj_priv = to_intel_bo(obj); |
673a394b | 4143 | |
bb6baf76 CW |
4144 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4145 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
1d7cfea1 CW |
4146 | ret = -EINVAL; |
4147 | goto out; | |
3ef94daa CW |
4148 | } |
4149 | ||
79e53945 JB |
4150 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4151 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4152 | args->handle); | |
1d7cfea1 CW |
4153 | ret = -EINVAL; |
4154 | goto out; | |
79e53945 JB |
4155 | } |
4156 | ||
4157 | obj_priv->user_pin_count++; | |
4158 | obj_priv->pin_filp = file_priv; | |
4159 | if (obj_priv->user_pin_count == 1) { | |
4160 | ret = i915_gem_object_pin(obj, args->alignment); | |
1d7cfea1 CW |
4161 | if (ret) |
4162 | goto out; | |
673a394b EA |
4163 | } |
4164 | ||
4165 | /* XXX - flush the CPU caches for pinned objects | |
4166 | * as the X server doesn't manage domains yet | |
4167 | */ | |
e47c68e9 | 4168 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b | 4169 | args->offset = obj_priv->gtt_offset; |
1d7cfea1 | 4170 | out: |
673a394b | 4171 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4172 | unlock: |
673a394b | 4173 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4174 | return ret; |
673a394b EA |
4175 | } |
4176 | ||
4177 | int | |
4178 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4179 | struct drm_file *file_priv) | |
4180 | { | |
4181 | struct drm_i915_gem_pin *args = data; | |
4182 | struct drm_gem_object *obj; | |
79e53945 | 4183 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4184 | int ret; |
673a394b | 4185 | |
1d7cfea1 CW |
4186 | ret = i915_mutex_lock_interruptible(dev); |
4187 | if (ret) | |
4188 | return ret; | |
673a394b EA |
4189 | |
4190 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4191 | if (obj == NULL) { | |
1d7cfea1 CW |
4192 | ret = -ENOENT; |
4193 | goto unlock; | |
673a394b | 4194 | } |
23010e43 | 4195 | obj_priv = to_intel_bo(obj); |
76c1dec1 | 4196 | |
79e53945 JB |
4197 | if (obj_priv->pin_filp != file_priv) { |
4198 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4199 | args->handle); | |
1d7cfea1 CW |
4200 | ret = -EINVAL; |
4201 | goto out; | |
79e53945 JB |
4202 | } |
4203 | obj_priv->user_pin_count--; | |
4204 | if (obj_priv->user_pin_count == 0) { | |
4205 | obj_priv->pin_filp = NULL; | |
4206 | i915_gem_object_unpin(obj); | |
4207 | } | |
673a394b | 4208 | |
1d7cfea1 | 4209 | out: |
673a394b | 4210 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4211 | unlock: |
673a394b | 4212 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4213 | return ret; |
673a394b EA |
4214 | } |
4215 | ||
4216 | int | |
4217 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4218 | struct drm_file *file_priv) | |
4219 | { | |
4220 | struct drm_i915_gem_busy *args = data; | |
4221 | struct drm_gem_object *obj; | |
4222 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4223 | int ret; |
4224 | ||
76c1dec1 | 4225 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4226 | if (ret) |
76c1dec1 | 4227 | return ret; |
673a394b | 4228 | |
673a394b EA |
4229 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4230 | if (obj == NULL) { | |
1d7cfea1 CW |
4231 | ret = -ENOENT; |
4232 | goto unlock; | |
673a394b | 4233 | } |
1d7cfea1 | 4234 | obj_priv = to_intel_bo(obj); |
d1b851fc | 4235 | |
0be555b6 CW |
4236 | /* Count all active objects as busy, even if they are currently not used |
4237 | * by the gpu. Users of this interface expect objects to eventually | |
4238 | * become non-busy without any further actions, therefore emit any | |
4239 | * necessary flushes here. | |
c4de0a5d | 4240 | */ |
0be555b6 CW |
4241 | args->busy = obj_priv->active; |
4242 | if (args->busy) { | |
4243 | /* Unconditionally flush objects, even when the gpu still uses this | |
4244 | * object. Userspace calling this function indicates that it wants to | |
4245 | * use this buffer rather sooner than later, so issuing the required | |
4246 | * flush earlier is beneficial. | |
4247 | */ | |
c78ec30b CW |
4248 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4249 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4250 | obj_priv->ring, |
4251 | 0, obj->write_domain); | |
0be555b6 CW |
4252 | |
4253 | /* Update the active list for the hardware's current position. | |
4254 | * Otherwise this only updates on a delayed timer or when irqs | |
4255 | * are actually unmasked, and our working set ends up being | |
4256 | * larger than required. | |
4257 | */ | |
4258 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4259 | ||
4260 | args->busy = obj_priv->active; | |
4261 | } | |
673a394b EA |
4262 | |
4263 | drm_gem_object_unreference(obj); | |
1d7cfea1 | 4264 | unlock: |
673a394b | 4265 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4266 | return ret; |
673a394b EA |
4267 | } |
4268 | ||
4269 | int | |
4270 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4271 | struct drm_file *file_priv) | |
4272 | { | |
4273 | return i915_gem_ring_throttle(dev, file_priv); | |
4274 | } | |
4275 | ||
3ef94daa CW |
4276 | int |
4277 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4278 | struct drm_file *file_priv) | |
4279 | { | |
4280 | struct drm_i915_gem_madvise *args = data; | |
4281 | struct drm_gem_object *obj; | |
4282 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4283 | int ret; |
3ef94daa CW |
4284 | |
4285 | switch (args->madv) { | |
4286 | case I915_MADV_DONTNEED: | |
4287 | case I915_MADV_WILLNEED: | |
4288 | break; | |
4289 | default: | |
4290 | return -EINVAL; | |
4291 | } | |
4292 | ||
1d7cfea1 CW |
4293 | ret = i915_mutex_lock_interruptible(dev); |
4294 | if (ret) | |
4295 | return ret; | |
4296 | ||
3ef94daa CW |
4297 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4298 | if (obj == NULL) { | |
1d7cfea1 CW |
4299 | ret = -ENOENT; |
4300 | goto unlock; | |
3ef94daa | 4301 | } |
23010e43 | 4302 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4303 | |
4304 | if (obj_priv->pin_count) { | |
1d7cfea1 CW |
4305 | ret = -EINVAL; |
4306 | goto out; | |
3ef94daa CW |
4307 | } |
4308 | ||
bb6baf76 CW |
4309 | if (obj_priv->madv != __I915_MADV_PURGED) |
4310 | obj_priv->madv = args->madv; | |
3ef94daa | 4311 | |
2d7ef395 CW |
4312 | /* if the object is no longer bound, discard its backing storage */ |
4313 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4314 | obj_priv->gtt_space == NULL) | |
4315 | i915_gem_object_truncate(obj); | |
4316 | ||
bb6baf76 CW |
4317 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4318 | ||
1d7cfea1 | 4319 | out: |
3ef94daa | 4320 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4321 | unlock: |
3ef94daa | 4322 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4323 | return ret; |
3ef94daa CW |
4324 | } |
4325 | ||
ac52bc56 DV |
4326 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4327 | size_t size) | |
4328 | { | |
73aa808f | 4329 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4330 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4331 | |
c397b908 DV |
4332 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4333 | if (obj == NULL) | |
4334 | return NULL; | |
673a394b | 4335 | |
c397b908 DV |
4336 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4337 | kfree(obj); | |
4338 | return NULL; | |
4339 | } | |
673a394b | 4340 | |
73aa808f CW |
4341 | i915_gem_info_add_obj(dev_priv, size); |
4342 | ||
c397b908 DV |
4343 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4344 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4345 | |
c397b908 | 4346 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4347 | obj->base.driver_private = NULL; |
c397b908 | 4348 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 CW |
4349 | INIT_LIST_HEAD(&obj->mm_list); |
4350 | INIT_LIST_HEAD(&obj->ring_list); | |
c397b908 | 4351 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4352 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4353 | |
c397b908 DV |
4354 | return &obj->base; |
4355 | } | |
4356 | ||
4357 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4358 | { | |
4359 | BUG(); | |
de151cf6 | 4360 | |
673a394b EA |
4361 | return 0; |
4362 | } | |
4363 | ||
be72615b | 4364 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4365 | { |
de151cf6 | 4366 | struct drm_device *dev = obj->dev; |
be72615b | 4367 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4368 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4369 | int ret; |
673a394b | 4370 | |
be72615b CW |
4371 | ret = i915_gem_object_unbind(obj); |
4372 | if (ret == -ERESTARTSYS) { | |
69dc4987 | 4373 | list_move(&obj_priv->mm_list, |
be72615b CW |
4374 | &dev_priv->mm.deferred_free_list); |
4375 | return; | |
4376 | } | |
673a394b | 4377 | |
7e616158 CW |
4378 | if (obj_priv->mmap_offset) |
4379 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4380 | |
c397b908 | 4381 | drm_gem_object_release(obj); |
73aa808f | 4382 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4383 | |
9a298b2a | 4384 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4385 | kfree(obj_priv->bit_17); |
c397b908 | 4386 | kfree(obj_priv); |
673a394b EA |
4387 | } |
4388 | ||
be72615b CW |
4389 | void i915_gem_free_object(struct drm_gem_object *obj) |
4390 | { | |
4391 | struct drm_device *dev = obj->dev; | |
4392 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4393 | ||
4394 | trace_i915_gem_object_destroy(obj); | |
4395 | ||
4396 | while (obj_priv->pin_count > 0) | |
4397 | i915_gem_object_unpin(obj); | |
4398 | ||
4399 | if (obj_priv->phys_obj) | |
4400 | i915_gem_detach_phys_object(dev, obj); | |
4401 | ||
4402 | i915_gem_free_object_tail(obj); | |
4403 | } | |
4404 | ||
29105ccc CW |
4405 | int |
4406 | i915_gem_idle(struct drm_device *dev) | |
4407 | { | |
4408 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4409 | int ret; | |
28dfe52a | 4410 | |
29105ccc | 4411 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4412 | |
87acb0a5 | 4413 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4414 | mutex_unlock(&dev->struct_mutex); |
4415 | return 0; | |
28dfe52a EA |
4416 | } |
4417 | ||
29105ccc | 4418 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4419 | if (ret) { |
4420 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4421 | return ret; |
6dbe2772 | 4422 | } |
673a394b | 4423 | |
29105ccc CW |
4424 | /* Under UMS, be paranoid and evict. */ |
4425 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4426 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4427 | if (ret) { |
4428 | mutex_unlock(&dev->struct_mutex); | |
4429 | return ret; | |
4430 | } | |
4431 | } | |
4432 | ||
4433 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4434 | * We need to replace this with a semaphore, or something. | |
4435 | * And not confound mm.suspended! | |
4436 | */ | |
4437 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4438 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4439 | |
4440 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4441 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4442 | |
6dbe2772 KP |
4443 | mutex_unlock(&dev->struct_mutex); |
4444 | ||
29105ccc CW |
4445 | /* Cancel the retire work handler, which should be idle now. */ |
4446 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4447 | ||
673a394b EA |
4448 | return 0; |
4449 | } | |
4450 | ||
e552eb70 JB |
4451 | /* |
4452 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4453 | * over cache flushing. | |
4454 | */ | |
8187a2b7 | 4455 | static int |
e552eb70 JB |
4456 | i915_gem_init_pipe_control(struct drm_device *dev) |
4457 | { | |
4458 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4459 | struct drm_gem_object *obj; | |
4460 | struct drm_i915_gem_object *obj_priv; | |
4461 | int ret; | |
4462 | ||
34dc4d44 | 4463 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4464 | if (obj == NULL) { |
4465 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4466 | ret = -ENOMEM; | |
4467 | goto err; | |
4468 | } | |
4469 | obj_priv = to_intel_bo(obj); | |
4470 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4471 | ||
4472 | ret = i915_gem_object_pin(obj, 4096); | |
4473 | if (ret) | |
4474 | goto err_unref; | |
4475 | ||
4476 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4477 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4478 | if (dev_priv->seqno_page == NULL) | |
4479 | goto err_unpin; | |
4480 | ||
4481 | dev_priv->seqno_obj = obj; | |
4482 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4483 | ||
4484 | return 0; | |
4485 | ||
4486 | err_unpin: | |
4487 | i915_gem_object_unpin(obj); | |
4488 | err_unref: | |
4489 | drm_gem_object_unreference(obj); | |
4490 | err: | |
4491 | return ret; | |
4492 | } | |
4493 | ||
8187a2b7 ZN |
4494 | |
4495 | static void | |
e552eb70 JB |
4496 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4497 | { | |
4498 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4499 | struct drm_gem_object *obj; | |
4500 | struct drm_i915_gem_object *obj_priv; | |
4501 | ||
4502 | obj = dev_priv->seqno_obj; | |
4503 | obj_priv = to_intel_bo(obj); | |
4504 | kunmap(obj_priv->pages[0]); | |
4505 | i915_gem_object_unpin(obj); | |
4506 | drm_gem_object_unreference(obj); | |
4507 | dev_priv->seqno_obj = NULL; | |
4508 | ||
4509 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4510 | } |
4511 | ||
8187a2b7 ZN |
4512 | int |
4513 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4514 | { | |
4515 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4516 | int ret; | |
68f95ba9 | 4517 | |
8187a2b7 ZN |
4518 | if (HAS_PIPE_CONTROL(dev)) { |
4519 | ret = i915_gem_init_pipe_control(dev); | |
4520 | if (ret) | |
4521 | return ret; | |
4522 | } | |
68f95ba9 | 4523 | |
5c1143bb | 4524 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4525 | if (ret) |
4526 | goto cleanup_pipe_control; | |
4527 | ||
4528 | if (HAS_BSD(dev)) { | |
5c1143bb | 4529 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4530 | if (ret) |
4531 | goto cleanup_render_ring; | |
d1b851fc | 4532 | } |
68f95ba9 | 4533 | |
549f7365 CW |
4534 | if (HAS_BLT(dev)) { |
4535 | ret = intel_init_blt_ring_buffer(dev); | |
4536 | if (ret) | |
4537 | goto cleanup_bsd_ring; | |
4538 | } | |
4539 | ||
6f392d54 CW |
4540 | dev_priv->next_seqno = 1; |
4541 | ||
68f95ba9 CW |
4542 | return 0; |
4543 | ||
549f7365 CW |
4544 | cleanup_bsd_ring: |
4545 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
68f95ba9 CW |
4546 | cleanup_render_ring: |
4547 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
4548 | cleanup_pipe_control: | |
4549 | if (HAS_PIPE_CONTROL(dev)) | |
4550 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4551 | return ret; |
4552 | } | |
4553 | ||
4554 | void | |
4555 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4556 | { | |
4557 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4558 | ||
4559 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
87acb0a5 | 4560 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); |
549f7365 | 4561 | intel_cleanup_ring_buffer(dev, &dev_priv->blt_ring); |
8187a2b7 ZN |
4562 | if (HAS_PIPE_CONTROL(dev)) |
4563 | i915_gem_cleanup_pipe_control(dev); | |
4564 | } | |
4565 | ||
673a394b EA |
4566 | int |
4567 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4568 | struct drm_file *file_priv) | |
4569 | { | |
4570 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4571 | int ret; | |
4572 | ||
79e53945 JB |
4573 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4574 | return 0; | |
4575 | ||
ba1234d1 | 4576 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4577 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4578 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4579 | } |
4580 | ||
673a394b | 4581 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4582 | dev_priv->mm.suspended = 0; |
4583 | ||
4584 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4585 | if (ret != 0) { |
4586 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4587 | return ret; |
d816f6ac | 4588 | } |
9bb2d6f9 | 4589 | |
69dc4987 | 4590 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4591 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4592 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4593 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4594 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4595 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4596 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4597 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4598 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4599 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4600 | |
5f35308b CW |
4601 | ret = drm_irq_install(dev); |
4602 | if (ret) | |
4603 | goto cleanup_ringbuffer; | |
dbb19d30 | 4604 | |
673a394b | 4605 | return 0; |
5f35308b CW |
4606 | |
4607 | cleanup_ringbuffer: | |
4608 | mutex_lock(&dev->struct_mutex); | |
4609 | i915_gem_cleanup_ringbuffer(dev); | |
4610 | dev_priv->mm.suspended = 1; | |
4611 | mutex_unlock(&dev->struct_mutex); | |
4612 | ||
4613 | return ret; | |
673a394b EA |
4614 | } |
4615 | ||
4616 | int | |
4617 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4618 | struct drm_file *file_priv) | |
4619 | { | |
79e53945 JB |
4620 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4621 | return 0; | |
4622 | ||
dbb19d30 | 4623 | drm_irq_uninstall(dev); |
e6890f6f | 4624 | return i915_gem_idle(dev); |
673a394b EA |
4625 | } |
4626 | ||
4627 | void | |
4628 | i915_gem_lastclose(struct drm_device *dev) | |
4629 | { | |
4630 | int ret; | |
673a394b | 4631 | |
e806b495 EA |
4632 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4633 | return; | |
4634 | ||
6dbe2772 KP |
4635 | ret = i915_gem_idle(dev); |
4636 | if (ret) | |
4637 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4638 | } |
4639 | ||
64193406 CW |
4640 | static void |
4641 | init_ring_lists(struct intel_ring_buffer *ring) | |
4642 | { | |
4643 | INIT_LIST_HEAD(&ring->active_list); | |
4644 | INIT_LIST_HEAD(&ring->request_list); | |
4645 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4646 | } | |
4647 | ||
673a394b EA |
4648 | void |
4649 | i915_gem_load(struct drm_device *dev) | |
4650 | { | |
b5aa8a0f | 4651 | int i; |
673a394b EA |
4652 | drm_i915_private_t *dev_priv = dev->dev_private; |
4653 | ||
69dc4987 | 4654 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4655 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4656 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4657 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4658 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4659 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
64193406 CW |
4660 | init_ring_lists(&dev_priv->render_ring); |
4661 | init_ring_lists(&dev_priv->bsd_ring); | |
4662 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4663 | for (i = 0; i < 16; i++) |
4664 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4665 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4666 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4667 | init_completion(&dev_priv->error_completion); |
31169714 CW |
4668 | spin_lock(&shrink_list_lock); |
4669 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4670 | spin_unlock(&shrink_list_lock); | |
4671 | ||
94400120 DA |
4672 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4673 | if (IS_GEN3(dev)) { | |
4674 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4675 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4676 | /* arb state is a masked write, so set bit + bit in mask */ | |
4677 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4678 | I915_WRITE(MI_ARB_STATE, tmp); | |
4679 | } | |
4680 | } | |
4681 | ||
de151cf6 | 4682 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4683 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4684 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4685 | |
a6c45cf0 | 4686 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4687 | dev_priv->num_fence_regs = 16; |
4688 | else | |
4689 | dev_priv->num_fence_regs = 8; | |
4690 | ||
b5aa8a0f | 4691 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4692 | switch (INTEL_INFO(dev)->gen) { |
4693 | case 6: | |
4694 | for (i = 0; i < 16; i++) | |
4695 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4696 | break; | |
4697 | case 5: | |
4698 | case 4: | |
b5aa8a0f GH |
4699 | for (i = 0; i < 16; i++) |
4700 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4701 | break; |
4702 | case 3: | |
b5aa8a0f GH |
4703 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4704 | for (i = 0; i < 8; i++) | |
4705 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4706 | case 2: |
4707 | for (i = 0; i < 8; i++) | |
4708 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4709 | break; | |
b5aa8a0f | 4710 | } |
673a394b | 4711 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4712 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4713 | } |
71acb5eb DA |
4714 | |
4715 | /* | |
4716 | * Create a physically contiguous memory object for this object | |
4717 | * e.g. for cursor + overlay regs | |
4718 | */ | |
995b6762 CW |
4719 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4720 | int id, int size, int align) | |
71acb5eb DA |
4721 | { |
4722 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4723 | struct drm_i915_gem_phys_object *phys_obj; | |
4724 | int ret; | |
4725 | ||
4726 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4727 | return 0; | |
4728 | ||
9a298b2a | 4729 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4730 | if (!phys_obj) |
4731 | return -ENOMEM; | |
4732 | ||
4733 | phys_obj->id = id; | |
4734 | ||
6eeefaf3 | 4735 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4736 | if (!phys_obj->handle) { |
4737 | ret = -ENOMEM; | |
4738 | goto kfree_obj; | |
4739 | } | |
4740 | #ifdef CONFIG_X86 | |
4741 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4742 | #endif | |
4743 | ||
4744 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4745 | ||
4746 | return 0; | |
4747 | kfree_obj: | |
9a298b2a | 4748 | kfree(phys_obj); |
71acb5eb DA |
4749 | return ret; |
4750 | } | |
4751 | ||
995b6762 | 4752 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4753 | { |
4754 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4755 | struct drm_i915_gem_phys_object *phys_obj; | |
4756 | ||
4757 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4758 | return; | |
4759 | ||
4760 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4761 | if (phys_obj->cur_obj) { | |
4762 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4763 | } | |
4764 | ||
4765 | #ifdef CONFIG_X86 | |
4766 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4767 | #endif | |
4768 | drm_pci_free(dev, phys_obj->handle); | |
4769 | kfree(phys_obj); | |
4770 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4771 | } | |
4772 | ||
4773 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4774 | { | |
4775 | int i; | |
4776 | ||
260883c8 | 4777 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4778 | i915_gem_free_phys_object(dev, i); |
4779 | } | |
4780 | ||
4781 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4782 | struct drm_gem_object *obj) | |
4783 | { | |
4784 | struct drm_i915_gem_object *obj_priv; | |
4785 | int i; | |
4786 | int ret; | |
4787 | int page_count; | |
4788 | ||
23010e43 | 4789 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4790 | if (!obj_priv->phys_obj) |
4791 | return; | |
4792 | ||
4bdadb97 | 4793 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4794 | if (ret) |
4795 | goto out; | |
4796 | ||
4797 | page_count = obj->size / PAGE_SIZE; | |
4798 | ||
4799 | for (i = 0; i < page_count; i++) { | |
3e4d3af5 | 4800 | char *dst = kmap_atomic(obj_priv->pages[i]); |
71acb5eb DA |
4801 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4802 | ||
4803 | memcpy(dst, src, PAGE_SIZE); | |
3e4d3af5 | 4804 | kunmap_atomic(dst); |
71acb5eb | 4805 | } |
856fa198 | 4806 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4807 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4808 | |
4809 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4810 | out: |
4811 | obj_priv->phys_obj->cur_obj = NULL; | |
4812 | obj_priv->phys_obj = NULL; | |
4813 | } | |
4814 | ||
4815 | int | |
4816 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4817 | struct drm_gem_object *obj, |
4818 | int id, | |
4819 | int align) | |
71acb5eb DA |
4820 | { |
4821 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4822 | struct drm_i915_gem_object *obj_priv; | |
4823 | int ret = 0; | |
4824 | int page_count; | |
4825 | int i; | |
4826 | ||
4827 | if (id > I915_MAX_PHYS_OBJECT) | |
4828 | return -EINVAL; | |
4829 | ||
23010e43 | 4830 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4831 | |
4832 | if (obj_priv->phys_obj) { | |
4833 | if (obj_priv->phys_obj->id == id) | |
4834 | return 0; | |
4835 | i915_gem_detach_phys_object(dev, obj); | |
4836 | } | |
4837 | ||
71acb5eb DA |
4838 | /* create a new object */ |
4839 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4840 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4841 | obj->size, align); |
71acb5eb | 4842 | if (ret) { |
aeb565df | 4843 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4844 | goto out; |
4845 | } | |
4846 | } | |
4847 | ||
4848 | /* bind to the object */ | |
4849 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4850 | obj_priv->phys_obj->cur_obj = obj; | |
4851 | ||
4bdadb97 | 4852 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4853 | if (ret) { |
4854 | DRM_ERROR("failed to get page list\n"); | |
4855 | goto out; | |
4856 | } | |
4857 | ||
4858 | page_count = obj->size / PAGE_SIZE; | |
4859 | ||
4860 | for (i = 0; i < page_count; i++) { | |
3e4d3af5 | 4861 | char *src = kmap_atomic(obj_priv->pages[i]); |
71acb5eb DA |
4862 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4863 | ||
4864 | memcpy(dst, src, PAGE_SIZE); | |
3e4d3af5 | 4865 | kunmap_atomic(src); |
71acb5eb DA |
4866 | } |
4867 | ||
d78b47b9 CW |
4868 | i915_gem_object_put_pages(obj); |
4869 | ||
71acb5eb DA |
4870 | return 0; |
4871 | out: | |
4872 | return ret; | |
4873 | } | |
4874 | ||
4875 | static int | |
4876 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4877 | struct drm_i915_gem_pwrite *args, | |
4878 | struct drm_file *file_priv) | |
4879 | { | |
23010e43 | 4880 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4881 | void *obj_addr; |
4882 | int ret; | |
4883 | char __user *user_data; | |
4884 | ||
4885 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4886 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4887 | ||
44d98a61 | 4888 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4889 | ret = copy_from_user(obj_addr, user_data, args->size); |
4890 | if (ret) | |
4891 | return -EFAULT; | |
4892 | ||
4893 | drm_agp_chipset_flush(dev); | |
4894 | return 0; | |
4895 | } | |
b962442e | 4896 | |
f787a5f5 | 4897 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4898 | { |
f787a5f5 | 4899 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4900 | |
4901 | /* Clean up our request list when the client is going away, so that | |
4902 | * later retire_requests won't dereference our soon-to-be-gone | |
4903 | * file_priv. | |
4904 | */ | |
1c25595f | 4905 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4906 | while (!list_empty(&file_priv->mm.request_list)) { |
4907 | struct drm_i915_gem_request *request; | |
4908 | ||
4909 | request = list_first_entry(&file_priv->mm.request_list, | |
4910 | struct drm_i915_gem_request, | |
4911 | client_list); | |
4912 | list_del(&request->client_list); | |
4913 | request->file_priv = NULL; | |
4914 | } | |
1c25595f | 4915 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4916 | } |
31169714 | 4917 | |
1637ef41 CW |
4918 | static int |
4919 | i915_gpu_is_active(struct drm_device *dev) | |
4920 | { | |
4921 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4922 | int lists_empty; | |
4923 | ||
1637ef41 | 4924 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 4925 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4926 | |
4927 | return !lists_empty; | |
4928 | } | |
4929 | ||
31169714 | 4930 | static int |
7f8275d0 | 4931 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
4932 | { |
4933 | drm_i915_private_t *dev_priv, *next_dev; | |
4934 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4935 | int cnt = 0; | |
4936 | int would_deadlock = 1; | |
4937 | ||
4938 | /* "fast-path" to count number of available objects */ | |
4939 | if (nr_to_scan == 0) { | |
4940 | spin_lock(&shrink_list_lock); | |
4941 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4942 | struct drm_device *dev = dev_priv->dev; | |
4943 | ||
4944 | if (mutex_trylock(&dev->struct_mutex)) { | |
4945 | list_for_each_entry(obj_priv, | |
4946 | &dev_priv->mm.inactive_list, | |
69dc4987 | 4947 | mm_list) |
31169714 CW |
4948 | cnt++; |
4949 | mutex_unlock(&dev->struct_mutex); | |
4950 | } | |
4951 | } | |
4952 | spin_unlock(&shrink_list_lock); | |
4953 | ||
4954 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4955 | } | |
4956 | ||
4957 | spin_lock(&shrink_list_lock); | |
4958 | ||
1637ef41 | 4959 | rescan: |
31169714 CW |
4960 | /* first scan for clean buffers */ |
4961 | list_for_each_entry_safe(dev_priv, next_dev, | |
4962 | &shrink_list, mm.shrink_list) { | |
4963 | struct drm_device *dev = dev_priv->dev; | |
4964 | ||
4965 | if (! mutex_trylock(&dev->struct_mutex)) | |
4966 | continue; | |
4967 | ||
4968 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 4969 | i915_gem_retire_requests(dev); |
31169714 CW |
4970 | |
4971 | list_for_each_entry_safe(obj_priv, next_obj, | |
4972 | &dev_priv->mm.inactive_list, | |
69dc4987 | 4973 | mm_list) { |
31169714 | 4974 | if (i915_gem_object_is_purgeable(obj_priv)) { |
a8089e84 | 4975 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4976 | if (--nr_to_scan <= 0) |
4977 | break; | |
4978 | } | |
4979 | } | |
4980 | ||
4981 | spin_lock(&shrink_list_lock); | |
4982 | mutex_unlock(&dev->struct_mutex); | |
4983 | ||
963b4836 CW |
4984 | would_deadlock = 0; |
4985 | ||
31169714 CW |
4986 | if (nr_to_scan <= 0) |
4987 | break; | |
4988 | } | |
4989 | ||
4990 | /* second pass, evict/count anything still on the inactive list */ | |
4991 | list_for_each_entry_safe(dev_priv, next_dev, | |
4992 | &shrink_list, mm.shrink_list) { | |
4993 | struct drm_device *dev = dev_priv->dev; | |
4994 | ||
4995 | if (! mutex_trylock(&dev->struct_mutex)) | |
4996 | continue; | |
4997 | ||
4998 | spin_unlock(&shrink_list_lock); | |
4999 | ||
5000 | list_for_each_entry_safe(obj_priv, next_obj, | |
5001 | &dev_priv->mm.inactive_list, | |
69dc4987 | 5002 | mm_list) { |
31169714 | 5003 | if (nr_to_scan > 0) { |
a8089e84 | 5004 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5005 | nr_to_scan--; |
5006 | } else | |
5007 | cnt++; | |
5008 | } | |
5009 | ||
5010 | spin_lock(&shrink_list_lock); | |
5011 | mutex_unlock(&dev->struct_mutex); | |
5012 | ||
5013 | would_deadlock = 0; | |
5014 | } | |
5015 | ||
1637ef41 CW |
5016 | if (nr_to_scan) { |
5017 | int active = 0; | |
5018 | ||
5019 | /* | |
5020 | * We are desperate for pages, so as a last resort, wait | |
5021 | * for the GPU to finish and discard whatever we can. | |
5022 | * This has a dramatic impact to reduce the number of | |
5023 | * OOM-killer events whilst running the GPU aggressively. | |
5024 | */ | |
5025 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5026 | struct drm_device *dev = dev_priv->dev; | |
5027 | ||
5028 | if (!mutex_trylock(&dev->struct_mutex)) | |
5029 | continue; | |
5030 | ||
5031 | spin_unlock(&shrink_list_lock); | |
5032 | ||
5033 | if (i915_gpu_is_active(dev)) { | |
5034 | i915_gpu_idle(dev); | |
5035 | active++; | |
5036 | } | |
5037 | ||
5038 | spin_lock(&shrink_list_lock); | |
5039 | mutex_unlock(&dev->struct_mutex); | |
5040 | } | |
5041 | ||
5042 | if (active) | |
5043 | goto rescan; | |
5044 | } | |
5045 | ||
31169714 CW |
5046 | spin_unlock(&shrink_list_lock); |
5047 | ||
5048 | if (would_deadlock) | |
5049 | return -1; | |
5050 | else if (cnt > 0) | |
5051 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5052 | else | |
5053 | return 0; | |
5054 | } | |
5055 | ||
5056 | static struct shrinker shrinker = { | |
5057 | .shrink = i915_gem_shrink, | |
5058 | .seeks = DEFAULT_SEEKS, | |
5059 | }; | |
5060 | ||
5061 | __init void | |
5062 | i915_gem_shrinker_init(void) | |
5063 | { | |
5064 | register_shrinker(&shrinker); | |
5065 | } | |
5066 | ||
5067 | __exit void | |
5068 | i915_gem_shrinker_exit(void) | |
5069 | { | |
5070 | unregister_shrinker(&shrinker); | |
5071 | } |