Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
86a1ee26 CW |
44 | bool map_and_fenceable, |
45 | bool nonblocking); | |
05394f39 CW |
46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
47 | struct drm_i915_gem_object *obj, | |
71acb5eb | 48 | struct drm_i915_gem_pwrite *args, |
05394f39 | 49 | struct drm_file *file); |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
6c085a72 CW |
59 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
60 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 61 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 62 | |
61050808 CW |
63 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
64 | { | |
65 | if (obj->tiling_mode) | |
66 | i915_gem_release_mmap(obj); | |
67 | ||
68 | /* As we do not have an associated fence register, we will force | |
69 | * a tiling change if we ever need to acquire one. | |
70 | */ | |
5d82e3e6 | 71 | obj->fence_dirty = false; |
61050808 CW |
72 | obj->fence_reg = I915_FENCE_REG_NONE; |
73 | } | |
74 | ||
73aa808f CW |
75 | /* some bookkeeping */ |
76 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
77 | size_t size) | |
78 | { | |
79 | dev_priv->mm.object_count++; | |
80 | dev_priv->mm.object_memory += size; | |
81 | } | |
82 | ||
83 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
84 | size_t size) | |
85 | { | |
86 | dev_priv->mm.object_count--; | |
87 | dev_priv->mm.object_memory -= size; | |
88 | } | |
89 | ||
21dd3734 CW |
90 | static int |
91 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
92 | { |
93 | struct drm_i915_private *dev_priv = dev->dev_private; | |
94 | struct completion *x = &dev_priv->error_completion; | |
95 | unsigned long flags; | |
96 | int ret; | |
97 | ||
98 | if (!atomic_read(&dev_priv->mm.wedged)) | |
99 | return 0; | |
100 | ||
0a6759c6 DV |
101 | /* |
102 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
103 | * userspace. If it takes that long something really bad is going on and | |
104 | * we should simply try to bail out and fail as gracefully as possible. | |
105 | */ | |
106 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
107 | if (ret == 0) { | |
108 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
109 | return -EIO; | |
110 | } else if (ret < 0) { | |
30dbf0c0 | 111 | return ret; |
0a6759c6 | 112 | } |
30dbf0c0 | 113 | |
21dd3734 CW |
114 | if (atomic_read(&dev_priv->mm.wedged)) { |
115 | /* GPU is hung, bump the completion count to account for | |
116 | * the token we just consumed so that we never hit zero and | |
117 | * end up waiting upon a subsequent completion event that | |
118 | * will never happen. | |
119 | */ | |
120 | spin_lock_irqsave(&x->wait.lock, flags); | |
121 | x->done++; | |
122 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
123 | } | |
124 | return 0; | |
30dbf0c0 CW |
125 | } |
126 | ||
54cf91dc | 127 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 128 | { |
76c1dec1 CW |
129 | int ret; |
130 | ||
21dd3734 | 131 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
132 | if (ret) |
133 | return ret; | |
134 | ||
135 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
136 | if (ret) | |
137 | return ret; | |
138 | ||
23bc5982 | 139 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
140 | return 0; |
141 | } | |
30dbf0c0 | 142 | |
7d1c4804 | 143 | static inline bool |
05394f39 | 144 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 145 | { |
6c085a72 | 146 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
147 | } |
148 | ||
79e53945 JB |
149 | int |
150 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 151 | struct drm_file *file) |
79e53945 JB |
152 | { |
153 | struct drm_i915_gem_init *args = data; | |
2021746e | 154 | |
7bb6fb8d DV |
155 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
156 | return -ENODEV; | |
157 | ||
2021746e CW |
158 | if (args->gtt_start >= args->gtt_end || |
159 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
160 | return -EINVAL; | |
79e53945 | 161 | |
f534bc0b DV |
162 | /* GEM with user mode setting was never supported on ilk and later. */ |
163 | if (INTEL_INFO(dev)->gen >= 5) | |
164 | return -ENODEV; | |
165 | ||
79e53945 | 166 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
167 | i915_gem_init_global_gtt(dev, args->gtt_start, |
168 | args->gtt_end, args->gtt_end); | |
673a394b EA |
169 | mutex_unlock(&dev->struct_mutex); |
170 | ||
2021746e | 171 | return 0; |
673a394b EA |
172 | } |
173 | ||
5a125c3c EA |
174 | int |
175 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 176 | struct drm_file *file) |
5a125c3c | 177 | { |
73aa808f | 178 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 179 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
180 | struct drm_i915_gem_object *obj; |
181 | size_t pinned; | |
5a125c3c | 182 | |
6299f992 | 183 | pinned = 0; |
73aa808f | 184 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 185 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
186 | if (obj->pin_count) |
187 | pinned += obj->gtt_space->size; | |
73aa808f | 188 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 189 | |
6299f992 | 190 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 191 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 192 | |
5a125c3c EA |
193 | return 0; |
194 | } | |
195 | ||
ff72145b DA |
196 | static int |
197 | i915_gem_create(struct drm_file *file, | |
198 | struct drm_device *dev, | |
199 | uint64_t size, | |
200 | uint32_t *handle_p) | |
673a394b | 201 | { |
05394f39 | 202 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
203 | int ret; |
204 | u32 handle; | |
673a394b | 205 | |
ff72145b | 206 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
207 | if (size == 0) |
208 | return -EINVAL; | |
673a394b EA |
209 | |
210 | /* Allocate the new object */ | |
ff72145b | 211 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
212 | if (obj == NULL) |
213 | return -ENOMEM; | |
214 | ||
05394f39 | 215 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 216 | if (ret) { |
05394f39 CW |
217 | drm_gem_object_release(&obj->base); |
218 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 219 | kfree(obj); |
673a394b | 220 | return ret; |
1dfd9754 | 221 | } |
673a394b | 222 | |
202f2fef | 223 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 224 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
225 | trace_i915_gem_object_create(obj); |
226 | ||
ff72145b | 227 | *handle_p = handle; |
673a394b EA |
228 | return 0; |
229 | } | |
230 | ||
ff72145b DA |
231 | int |
232 | i915_gem_dumb_create(struct drm_file *file, | |
233 | struct drm_device *dev, | |
234 | struct drm_mode_create_dumb *args) | |
235 | { | |
236 | /* have to work out size/pitch and return them */ | |
ed0291fd | 237 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
238 | args->size = args->pitch * args->height; |
239 | return i915_gem_create(file, dev, | |
240 | args->size, &args->handle); | |
241 | } | |
242 | ||
243 | int i915_gem_dumb_destroy(struct drm_file *file, | |
244 | struct drm_device *dev, | |
245 | uint32_t handle) | |
246 | { | |
247 | return drm_gem_handle_delete(file, handle); | |
248 | } | |
249 | ||
250 | /** | |
251 | * Creates a new mm object and returns a handle to it. | |
252 | */ | |
253 | int | |
254 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
255 | struct drm_file *file) | |
256 | { | |
257 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 258 | |
ff72145b DA |
259 | return i915_gem_create(file, dev, |
260 | args->size, &args->handle); | |
261 | } | |
262 | ||
05394f39 | 263 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 264 | { |
05394f39 | 265 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
266 | |
267 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 268 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
269 | } |
270 | ||
8461d226 DV |
271 | static inline int |
272 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
273 | const char *gpu_vaddr, int gpu_offset, | |
274 | int length) | |
275 | { | |
276 | int ret, cpu_offset = 0; | |
277 | ||
278 | while (length > 0) { | |
279 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
280 | int this_length = min(cacheline_end - gpu_offset, length); | |
281 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
282 | ||
283 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
284 | gpu_vaddr + swizzled_gpu_offset, | |
285 | this_length); | |
286 | if (ret) | |
287 | return ret + length; | |
288 | ||
289 | cpu_offset += this_length; | |
290 | gpu_offset += this_length; | |
291 | length -= this_length; | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
8c59967c | 297 | static inline int |
4f0c7cfb BW |
298 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
299 | const char __user *cpu_vaddr, | |
8c59967c DV |
300 | int length) |
301 | { | |
302 | int ret, cpu_offset = 0; | |
303 | ||
304 | while (length > 0) { | |
305 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
306 | int this_length = min(cacheline_end - gpu_offset, length); | |
307 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
308 | ||
309 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
310 | cpu_vaddr + cpu_offset, | |
311 | this_length); | |
312 | if (ret) | |
313 | return ret + length; | |
314 | ||
315 | cpu_offset += this_length; | |
316 | gpu_offset += this_length; | |
317 | length -= this_length; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
d174bd64 DV |
323 | /* Per-page copy function for the shmem pread fastpath. |
324 | * Flushes invalid cachelines before reading the target if | |
325 | * needs_clflush is set. */ | |
eb01459f | 326 | static int |
d174bd64 DV |
327 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
328 | char __user *user_data, | |
329 | bool page_do_bit17_swizzling, bool needs_clflush) | |
330 | { | |
331 | char *vaddr; | |
332 | int ret; | |
333 | ||
e7e58eb5 | 334 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
335 | return -EINVAL; |
336 | ||
337 | vaddr = kmap_atomic(page); | |
338 | if (needs_clflush) | |
339 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
340 | page_length); | |
341 | ret = __copy_to_user_inatomic(user_data, | |
342 | vaddr + shmem_page_offset, | |
343 | page_length); | |
344 | kunmap_atomic(vaddr); | |
345 | ||
f60d7f0c | 346 | return ret ? -EFAULT : 0; |
d174bd64 DV |
347 | } |
348 | ||
23c18c71 DV |
349 | static void |
350 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
351 | bool swizzled) | |
352 | { | |
e7e58eb5 | 353 | if (unlikely(swizzled)) { |
23c18c71 DV |
354 | unsigned long start = (unsigned long) addr; |
355 | unsigned long end = (unsigned long) addr + length; | |
356 | ||
357 | /* For swizzling simply ensure that we always flush both | |
358 | * channels. Lame, but simple and it works. Swizzled | |
359 | * pwrite/pread is far from a hotpath - current userspace | |
360 | * doesn't use it at all. */ | |
361 | start = round_down(start, 128); | |
362 | end = round_up(end, 128); | |
363 | ||
364 | drm_clflush_virt_range((void *)start, end - start); | |
365 | } else { | |
366 | drm_clflush_virt_range(addr, length); | |
367 | } | |
368 | ||
369 | } | |
370 | ||
d174bd64 DV |
371 | /* Only difference to the fast-path function is that this can handle bit17 |
372 | * and uses non-atomic copy and kmap functions. */ | |
373 | static int | |
374 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
375 | char __user *user_data, | |
376 | bool page_do_bit17_swizzling, bool needs_clflush) | |
377 | { | |
378 | char *vaddr; | |
379 | int ret; | |
380 | ||
381 | vaddr = kmap(page); | |
382 | if (needs_clflush) | |
23c18c71 DV |
383 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
384 | page_length, | |
385 | page_do_bit17_swizzling); | |
d174bd64 DV |
386 | |
387 | if (page_do_bit17_swizzling) | |
388 | ret = __copy_to_user_swizzled(user_data, | |
389 | vaddr, shmem_page_offset, | |
390 | page_length); | |
391 | else | |
392 | ret = __copy_to_user(user_data, | |
393 | vaddr + shmem_page_offset, | |
394 | page_length); | |
395 | kunmap(page); | |
396 | ||
f60d7f0c | 397 | return ret ? - EFAULT : 0; |
d174bd64 DV |
398 | } |
399 | ||
eb01459f | 400 | static int |
dbf7bff0 DV |
401 | i915_gem_shmem_pread(struct drm_device *dev, |
402 | struct drm_i915_gem_object *obj, | |
403 | struct drm_i915_gem_pread *args, | |
404 | struct drm_file *file) | |
eb01459f | 405 | { |
8461d226 | 406 | char __user *user_data; |
eb01459f | 407 | ssize_t remain; |
8461d226 | 408 | loff_t offset; |
eb2c0c81 | 409 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 410 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 411 | int hit_slowpath = 0; |
96d79b52 | 412 | int prefaulted = 0; |
8489731c | 413 | int needs_clflush = 0; |
9da3da66 CW |
414 | struct scatterlist *sg; |
415 | int i; | |
eb01459f | 416 | |
8461d226 | 417 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
418 | remain = args->size; |
419 | ||
8461d226 | 420 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 421 | |
8489731c DV |
422 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
423 | /* If we're not in the cpu read domain, set ourself into the gtt | |
424 | * read domain and manually flush cachelines (if required). This | |
425 | * optimizes for the case when the gpu will dirty the data | |
426 | * anyway again before the next pread happens. */ | |
427 | if (obj->cache_level == I915_CACHE_NONE) | |
428 | needs_clflush = 1; | |
6c085a72 CW |
429 | if (obj->gtt_space) { |
430 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
431 | if (ret) | |
432 | return ret; | |
433 | } | |
8489731c | 434 | } |
eb01459f | 435 | |
f60d7f0c CW |
436 | ret = i915_gem_object_get_pages(obj); |
437 | if (ret) | |
438 | return ret; | |
439 | ||
440 | i915_gem_object_pin_pages(obj); | |
441 | ||
8461d226 | 442 | offset = args->offset; |
eb01459f | 443 | |
9da3da66 | 444 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd CW |
445 | struct page *page; |
446 | ||
9da3da66 CW |
447 | if (i < offset >> PAGE_SHIFT) |
448 | continue; | |
449 | ||
450 | if (remain <= 0) | |
451 | break; | |
452 | ||
eb01459f EA |
453 | /* Operation in this page |
454 | * | |
eb01459f | 455 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
456 | * page_length = bytes to copy for this page |
457 | */ | |
c8cbbb8b | 458 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
459 | page_length = remain; |
460 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
461 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 462 | |
9da3da66 | 463 | page = sg_page(sg); |
8461d226 DV |
464 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
465 | (page_to_phys(page) & (1 << 17)) != 0; | |
466 | ||
d174bd64 DV |
467 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
468 | user_data, page_do_bit17_swizzling, | |
469 | needs_clflush); | |
470 | if (ret == 0) | |
471 | goto next_page; | |
dbf7bff0 DV |
472 | |
473 | hit_slowpath = 1; | |
dbf7bff0 DV |
474 | mutex_unlock(&dev->struct_mutex); |
475 | ||
96d79b52 | 476 | if (!prefaulted) { |
f56f821f | 477 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
478 | /* Userspace is tricking us, but we've already clobbered |
479 | * its pages with the prefault and promised to write the | |
480 | * data up to the first fault. Hence ignore any errors | |
481 | * and just continue. */ | |
482 | (void)ret; | |
483 | prefaulted = 1; | |
484 | } | |
eb01459f | 485 | |
d174bd64 DV |
486 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
487 | user_data, page_do_bit17_swizzling, | |
488 | needs_clflush); | |
eb01459f | 489 | |
dbf7bff0 | 490 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 491 | |
dbf7bff0 | 492 | next_page: |
e5281ccd | 493 | mark_page_accessed(page); |
e5281ccd | 494 | |
f60d7f0c | 495 | if (ret) |
8461d226 | 496 | goto out; |
8461d226 | 497 | |
eb01459f | 498 | remain -= page_length; |
8461d226 | 499 | user_data += page_length; |
eb01459f EA |
500 | offset += page_length; |
501 | } | |
502 | ||
4f27b75d | 503 | out: |
f60d7f0c CW |
504 | i915_gem_object_unpin_pages(obj); |
505 | ||
dbf7bff0 DV |
506 | if (hit_slowpath) { |
507 | /* Fixup: Kill any reinstated backing storage pages */ | |
508 | if (obj->madv == __I915_MADV_PURGED) | |
509 | i915_gem_object_truncate(obj); | |
510 | } | |
eb01459f EA |
511 | |
512 | return ret; | |
513 | } | |
514 | ||
673a394b EA |
515 | /** |
516 | * Reads data from the object referenced by handle. | |
517 | * | |
518 | * On error, the contents of *data are undefined. | |
519 | */ | |
520 | int | |
521 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 522 | struct drm_file *file) |
673a394b EA |
523 | { |
524 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 525 | struct drm_i915_gem_object *obj; |
35b62a89 | 526 | int ret = 0; |
673a394b | 527 | |
51311d0a CW |
528 | if (args->size == 0) |
529 | return 0; | |
530 | ||
531 | if (!access_ok(VERIFY_WRITE, | |
532 | (char __user *)(uintptr_t)args->data_ptr, | |
533 | args->size)) | |
534 | return -EFAULT; | |
535 | ||
4f27b75d | 536 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 537 | if (ret) |
4f27b75d | 538 | return ret; |
673a394b | 539 | |
05394f39 | 540 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 541 | if (&obj->base == NULL) { |
1d7cfea1 CW |
542 | ret = -ENOENT; |
543 | goto unlock; | |
4f27b75d | 544 | } |
673a394b | 545 | |
7dcd2499 | 546 | /* Bounds check source. */ |
05394f39 CW |
547 | if (args->offset > obj->base.size || |
548 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 549 | ret = -EINVAL; |
35b62a89 | 550 | goto out; |
ce9d419d CW |
551 | } |
552 | ||
1286ff73 DV |
553 | /* prime objects have no backing filp to GEM pread/pwrite |
554 | * pages from. | |
555 | */ | |
556 | if (!obj->base.filp) { | |
557 | ret = -EINVAL; | |
558 | goto out; | |
559 | } | |
560 | ||
db53a302 CW |
561 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
562 | ||
dbf7bff0 | 563 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 564 | |
35b62a89 | 565 | out: |
05394f39 | 566 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 567 | unlock: |
4f27b75d | 568 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 569 | return ret; |
673a394b EA |
570 | } |
571 | ||
0839ccb8 KP |
572 | /* This is the fast write path which cannot handle |
573 | * page faults in the source data | |
9b7530cc | 574 | */ |
0839ccb8 KP |
575 | |
576 | static inline int | |
577 | fast_user_write(struct io_mapping *mapping, | |
578 | loff_t page_base, int page_offset, | |
579 | char __user *user_data, | |
580 | int length) | |
9b7530cc | 581 | { |
4f0c7cfb BW |
582 | void __iomem *vaddr_atomic; |
583 | void *vaddr; | |
0839ccb8 | 584 | unsigned long unwritten; |
9b7530cc | 585 | |
3e4d3af5 | 586 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
587 | /* We can use the cpu mem copy function because this is X86. */ |
588 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
589 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 590 | user_data, length); |
3e4d3af5 | 591 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 592 | return unwritten; |
0839ccb8 KP |
593 | } |
594 | ||
3de09aa3 EA |
595 | /** |
596 | * This is the fast pwrite path, where we copy the data directly from the | |
597 | * user into the GTT, uncached. | |
598 | */ | |
673a394b | 599 | static int |
05394f39 CW |
600 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
601 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 602 | struct drm_i915_gem_pwrite *args, |
05394f39 | 603 | struct drm_file *file) |
673a394b | 604 | { |
0839ccb8 | 605 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 606 | ssize_t remain; |
0839ccb8 | 607 | loff_t offset, page_base; |
673a394b | 608 | char __user *user_data; |
935aaa69 DV |
609 | int page_offset, page_length, ret; |
610 | ||
86a1ee26 | 611 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
612 | if (ret) |
613 | goto out; | |
614 | ||
615 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
616 | if (ret) | |
617 | goto out_unpin; | |
618 | ||
619 | ret = i915_gem_object_put_fence(obj); | |
620 | if (ret) | |
621 | goto out_unpin; | |
673a394b EA |
622 | |
623 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
624 | remain = args->size; | |
673a394b | 625 | |
05394f39 | 626 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
627 | |
628 | while (remain > 0) { | |
629 | /* Operation in this page | |
630 | * | |
0839ccb8 KP |
631 | * page_base = page offset within aperture |
632 | * page_offset = offset within page | |
633 | * page_length = bytes to copy for this page | |
673a394b | 634 | */ |
c8cbbb8b CW |
635 | page_base = offset & PAGE_MASK; |
636 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
637 | page_length = remain; |
638 | if ((page_offset + remain) > PAGE_SIZE) | |
639 | page_length = PAGE_SIZE - page_offset; | |
640 | ||
0839ccb8 | 641 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
642 | * source page isn't available. Return the error and we'll |
643 | * retry in the slow path. | |
0839ccb8 | 644 | */ |
fbd5a26d | 645 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
646 | page_offset, user_data, page_length)) { |
647 | ret = -EFAULT; | |
648 | goto out_unpin; | |
649 | } | |
673a394b | 650 | |
0839ccb8 KP |
651 | remain -= page_length; |
652 | user_data += page_length; | |
653 | offset += page_length; | |
673a394b | 654 | } |
673a394b | 655 | |
935aaa69 DV |
656 | out_unpin: |
657 | i915_gem_object_unpin(obj); | |
658 | out: | |
3de09aa3 | 659 | return ret; |
673a394b EA |
660 | } |
661 | ||
d174bd64 DV |
662 | /* Per-page copy function for the shmem pwrite fastpath. |
663 | * Flushes invalid cachelines before writing to the target if | |
664 | * needs_clflush_before is set and flushes out any written cachelines after | |
665 | * writing if needs_clflush is set. */ | |
3043c60c | 666 | static int |
d174bd64 DV |
667 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
668 | char __user *user_data, | |
669 | bool page_do_bit17_swizzling, | |
670 | bool needs_clflush_before, | |
671 | bool needs_clflush_after) | |
673a394b | 672 | { |
d174bd64 | 673 | char *vaddr; |
673a394b | 674 | int ret; |
3de09aa3 | 675 | |
e7e58eb5 | 676 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 677 | return -EINVAL; |
3de09aa3 | 678 | |
d174bd64 DV |
679 | vaddr = kmap_atomic(page); |
680 | if (needs_clflush_before) | |
681 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
682 | page_length); | |
683 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
684 | user_data, | |
685 | page_length); | |
686 | if (needs_clflush_after) | |
687 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
688 | page_length); | |
689 | kunmap_atomic(vaddr); | |
3de09aa3 | 690 | |
755d2218 | 691 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
692 | } |
693 | ||
d174bd64 DV |
694 | /* Only difference to the fast-path function is that this can handle bit17 |
695 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 696 | static int |
d174bd64 DV |
697 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
698 | char __user *user_data, | |
699 | bool page_do_bit17_swizzling, | |
700 | bool needs_clflush_before, | |
701 | bool needs_clflush_after) | |
673a394b | 702 | { |
d174bd64 DV |
703 | char *vaddr; |
704 | int ret; | |
e5281ccd | 705 | |
d174bd64 | 706 | vaddr = kmap(page); |
e7e58eb5 | 707 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
708 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
709 | page_length, | |
710 | page_do_bit17_swizzling); | |
d174bd64 DV |
711 | if (page_do_bit17_swizzling) |
712 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
713 | user_data, |
714 | page_length); | |
d174bd64 DV |
715 | else |
716 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
717 | user_data, | |
718 | page_length); | |
719 | if (needs_clflush_after) | |
23c18c71 DV |
720 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
721 | page_length, | |
722 | page_do_bit17_swizzling); | |
d174bd64 | 723 | kunmap(page); |
40123c1f | 724 | |
755d2218 | 725 | return ret ? -EFAULT : 0; |
40123c1f EA |
726 | } |
727 | ||
40123c1f | 728 | static int |
e244a443 DV |
729 | i915_gem_shmem_pwrite(struct drm_device *dev, |
730 | struct drm_i915_gem_object *obj, | |
731 | struct drm_i915_gem_pwrite *args, | |
732 | struct drm_file *file) | |
40123c1f | 733 | { |
40123c1f | 734 | ssize_t remain; |
8c59967c DV |
735 | loff_t offset; |
736 | char __user *user_data; | |
eb2c0c81 | 737 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 738 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 739 | int hit_slowpath = 0; |
58642885 DV |
740 | int needs_clflush_after = 0; |
741 | int needs_clflush_before = 0; | |
9da3da66 CW |
742 | int i; |
743 | struct scatterlist *sg; | |
40123c1f | 744 | |
8c59967c | 745 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
746 | remain = args->size; |
747 | ||
8c59967c | 748 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 749 | |
58642885 DV |
750 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
751 | /* If we're not in the cpu write domain, set ourself into the gtt | |
752 | * write domain and manually flush cachelines (if required). This | |
753 | * optimizes for the case when the gpu will use the data | |
754 | * right away and we therefore have to clflush anyway. */ | |
755 | if (obj->cache_level == I915_CACHE_NONE) | |
756 | needs_clflush_after = 1; | |
6c085a72 CW |
757 | if (obj->gtt_space) { |
758 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
759 | if (ret) | |
760 | return ret; | |
761 | } | |
58642885 DV |
762 | } |
763 | /* Same trick applies for invalidate partially written cachelines before | |
764 | * writing. */ | |
765 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
766 | && obj->cache_level == I915_CACHE_NONE) | |
767 | needs_clflush_before = 1; | |
768 | ||
755d2218 CW |
769 | ret = i915_gem_object_get_pages(obj); |
770 | if (ret) | |
771 | return ret; | |
772 | ||
773 | i915_gem_object_pin_pages(obj); | |
774 | ||
673a394b | 775 | offset = args->offset; |
05394f39 | 776 | obj->dirty = 1; |
673a394b | 777 | |
9da3da66 | 778 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd | 779 | struct page *page; |
58642885 | 780 | int partial_cacheline_write; |
e5281ccd | 781 | |
9da3da66 CW |
782 | if (i < offset >> PAGE_SHIFT) |
783 | continue; | |
784 | ||
785 | if (remain <= 0) | |
786 | break; | |
787 | ||
40123c1f EA |
788 | /* Operation in this page |
789 | * | |
40123c1f | 790 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
791 | * page_length = bytes to copy for this page |
792 | */ | |
c8cbbb8b | 793 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
794 | |
795 | page_length = remain; | |
796 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
797 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 798 | |
58642885 DV |
799 | /* If we don't overwrite a cacheline completely we need to be |
800 | * careful to have up-to-date data by first clflushing. Don't | |
801 | * overcomplicate things and flush the entire patch. */ | |
802 | partial_cacheline_write = needs_clflush_before && | |
803 | ((shmem_page_offset | page_length) | |
804 | & (boot_cpu_data.x86_clflush_size - 1)); | |
805 | ||
9da3da66 | 806 | page = sg_page(sg); |
8c59967c DV |
807 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
808 | (page_to_phys(page) & (1 << 17)) != 0; | |
809 | ||
d174bd64 DV |
810 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
811 | user_data, page_do_bit17_swizzling, | |
812 | partial_cacheline_write, | |
813 | needs_clflush_after); | |
814 | if (ret == 0) | |
815 | goto next_page; | |
e244a443 DV |
816 | |
817 | hit_slowpath = 1; | |
e244a443 | 818 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
819 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
820 | user_data, page_do_bit17_swizzling, | |
821 | partial_cacheline_write, | |
822 | needs_clflush_after); | |
40123c1f | 823 | |
e244a443 | 824 | mutex_lock(&dev->struct_mutex); |
755d2218 | 825 | |
e244a443 | 826 | next_page: |
e5281ccd CW |
827 | set_page_dirty(page); |
828 | mark_page_accessed(page); | |
e5281ccd | 829 | |
755d2218 | 830 | if (ret) |
8c59967c | 831 | goto out; |
8c59967c | 832 | |
40123c1f | 833 | remain -= page_length; |
8c59967c | 834 | user_data += page_length; |
40123c1f | 835 | offset += page_length; |
673a394b EA |
836 | } |
837 | ||
fbd5a26d | 838 | out: |
755d2218 CW |
839 | i915_gem_object_unpin_pages(obj); |
840 | ||
e244a443 DV |
841 | if (hit_slowpath) { |
842 | /* Fixup: Kill any reinstated backing storage pages */ | |
843 | if (obj->madv == __I915_MADV_PURGED) | |
844 | i915_gem_object_truncate(obj); | |
845 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
846 | * domain anymore. */ | |
847 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
848 | i915_gem_clflush_object(obj); | |
849 | intel_gtt_chipset_flush(); | |
850 | } | |
8c59967c | 851 | } |
673a394b | 852 | |
58642885 DV |
853 | if (needs_clflush_after) |
854 | intel_gtt_chipset_flush(); | |
855 | ||
40123c1f | 856 | return ret; |
673a394b EA |
857 | } |
858 | ||
859 | /** | |
860 | * Writes data to the object referenced by handle. | |
861 | * | |
862 | * On error, the contents of the buffer that were to be modified are undefined. | |
863 | */ | |
864 | int | |
865 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 866 | struct drm_file *file) |
673a394b EA |
867 | { |
868 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 869 | struct drm_i915_gem_object *obj; |
51311d0a CW |
870 | int ret; |
871 | ||
872 | if (args->size == 0) | |
873 | return 0; | |
874 | ||
875 | if (!access_ok(VERIFY_READ, | |
876 | (char __user *)(uintptr_t)args->data_ptr, | |
877 | args->size)) | |
878 | return -EFAULT; | |
879 | ||
f56f821f DV |
880 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
881 | args->size); | |
51311d0a CW |
882 | if (ret) |
883 | return -EFAULT; | |
673a394b | 884 | |
fbd5a26d | 885 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 886 | if (ret) |
fbd5a26d | 887 | return ret; |
1d7cfea1 | 888 | |
05394f39 | 889 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 890 | if (&obj->base == NULL) { |
1d7cfea1 CW |
891 | ret = -ENOENT; |
892 | goto unlock; | |
fbd5a26d | 893 | } |
673a394b | 894 | |
7dcd2499 | 895 | /* Bounds check destination. */ |
05394f39 CW |
896 | if (args->offset > obj->base.size || |
897 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 898 | ret = -EINVAL; |
35b62a89 | 899 | goto out; |
ce9d419d CW |
900 | } |
901 | ||
1286ff73 DV |
902 | /* prime objects have no backing filp to GEM pread/pwrite |
903 | * pages from. | |
904 | */ | |
905 | if (!obj->base.filp) { | |
906 | ret = -EINVAL; | |
907 | goto out; | |
908 | } | |
909 | ||
db53a302 CW |
910 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
911 | ||
935aaa69 | 912 | ret = -EFAULT; |
673a394b EA |
913 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
914 | * it would end up going through the fenced access, and we'll get | |
915 | * different detiling behavior between reading and writing. | |
916 | * pread/pwrite currently are reading and writing from the CPU | |
917 | * perspective, requiring manual detiling by the client. | |
918 | */ | |
5c0480f2 | 919 | if (obj->phys_obj) { |
fbd5a26d | 920 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
921 | goto out; |
922 | } | |
923 | ||
86a1ee26 | 924 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 925 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 926 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 927 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
928 | /* Note that the gtt paths might fail with non-page-backed user |
929 | * pointers (e.g. gtt mappings when moving data between | |
930 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 931 | } |
673a394b | 932 | |
86a1ee26 | 933 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 934 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 935 | |
35b62a89 | 936 | out: |
05394f39 | 937 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 938 | unlock: |
fbd5a26d | 939 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
940 | return ret; |
941 | } | |
942 | ||
b361237b CW |
943 | int |
944 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
945 | bool interruptible) | |
946 | { | |
947 | if (atomic_read(&dev_priv->mm.wedged)) { | |
948 | struct completion *x = &dev_priv->error_completion; | |
949 | bool recovery_complete; | |
950 | unsigned long flags; | |
951 | ||
952 | /* Give the error handler a chance to run. */ | |
953 | spin_lock_irqsave(&x->wait.lock, flags); | |
954 | recovery_complete = x->done > 0; | |
955 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
956 | ||
957 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
958 | * -EIO unconditionally for these. */ | |
959 | if (!interruptible) | |
960 | return -EIO; | |
961 | ||
962 | /* Recovery complete, but still wedged means reset failure. */ | |
963 | if (recovery_complete) | |
964 | return -EIO; | |
965 | ||
966 | return -EAGAIN; | |
967 | } | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | /* | |
973 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
974 | * equal. | |
975 | */ | |
976 | static int | |
977 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
978 | { | |
979 | int ret; | |
980 | ||
981 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
982 | ||
983 | ret = 0; | |
984 | if (seqno == ring->outstanding_lazy_request) | |
985 | ret = i915_add_request(ring, NULL, NULL); | |
986 | ||
987 | return ret; | |
988 | } | |
989 | ||
990 | /** | |
991 | * __wait_seqno - wait until execution of seqno has finished | |
992 | * @ring: the ring expected to report seqno | |
993 | * @seqno: duh! | |
994 | * @interruptible: do an interruptible wait (normally yes) | |
995 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
996 | * | |
997 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
998 | * errno with remaining time filled in timeout argument. | |
999 | */ | |
1000 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
1001 | bool interruptible, struct timespec *timeout) | |
1002 | { | |
1003 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1004 | struct timespec before, now, wait_time={1,0}; | |
1005 | unsigned long timeout_jiffies; | |
1006 | long end; | |
1007 | bool wait_forever = true; | |
1008 | int ret; | |
1009 | ||
1010 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
1011 | return 0; | |
1012 | ||
1013 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1014 | ||
1015 | if (timeout != NULL) { | |
1016 | wait_time = *timeout; | |
1017 | wait_forever = false; | |
1018 | } | |
1019 | ||
1020 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1021 | ||
1022 | if (WARN_ON(!ring->irq_get(ring))) | |
1023 | return -ENODEV; | |
1024 | ||
1025 | /* Record current time in case interrupted by signal, or wedged * */ | |
1026 | getrawmonotonic(&before); | |
1027 | ||
1028 | #define EXIT_COND \ | |
1029 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
1030 | atomic_read(&dev_priv->mm.wedged)) | |
1031 | do { | |
1032 | if (interruptible) | |
1033 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1034 | EXIT_COND, | |
1035 | timeout_jiffies); | |
1036 | else | |
1037 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1038 | timeout_jiffies); | |
1039 | ||
1040 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1041 | if (ret) | |
1042 | end = ret; | |
1043 | } while (end == 0 && wait_forever); | |
1044 | ||
1045 | getrawmonotonic(&now); | |
1046 | ||
1047 | ring->irq_put(ring); | |
1048 | trace_i915_gem_request_wait_end(ring, seqno); | |
1049 | #undef EXIT_COND | |
1050 | ||
1051 | if (timeout) { | |
1052 | struct timespec sleep_time = timespec_sub(now, before); | |
1053 | *timeout = timespec_sub(*timeout, sleep_time); | |
1054 | } | |
1055 | ||
1056 | switch (end) { | |
1057 | case -EIO: | |
1058 | case -EAGAIN: /* Wedged */ | |
1059 | case -ERESTARTSYS: /* Signal */ | |
1060 | return (int)end; | |
1061 | case 0: /* Timeout */ | |
1062 | if (timeout) | |
1063 | set_normalized_timespec(timeout, 0, 0); | |
1064 | return -ETIME; | |
1065 | default: /* Completed */ | |
1066 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1067 | return 0; | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | /** | |
1072 | * Waits for a sequence number to be signaled, and cleans up the | |
1073 | * request and object lists appropriately for that event. | |
1074 | */ | |
1075 | int | |
1076 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1077 | { | |
1078 | struct drm_device *dev = ring->dev; | |
1079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1080 | bool interruptible = dev_priv->mm.interruptible; | |
1081 | int ret; | |
1082 | ||
1083 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1084 | BUG_ON(seqno == 0); | |
1085 | ||
1086 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1087 | if (ret) | |
1088 | return ret; | |
1089 | ||
1090 | ret = i915_gem_check_olr(ring, seqno); | |
1091 | if (ret) | |
1092 | return ret; | |
1093 | ||
1094 | return __wait_seqno(ring, seqno, interruptible, NULL); | |
1095 | } | |
1096 | ||
1097 | /** | |
1098 | * Ensures that all rendering to the object has completed and the object is | |
1099 | * safe to unbind from the GTT or access from the CPU. | |
1100 | */ | |
1101 | static __must_check int | |
1102 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1103 | bool readonly) | |
1104 | { | |
1105 | struct intel_ring_buffer *ring = obj->ring; | |
1106 | u32 seqno; | |
1107 | int ret; | |
1108 | ||
1109 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1110 | if (seqno == 0) | |
1111 | return 0; | |
1112 | ||
1113 | ret = i915_wait_seqno(ring, seqno); | |
1114 | if (ret) | |
1115 | return ret; | |
1116 | ||
1117 | i915_gem_retire_requests_ring(ring); | |
1118 | ||
1119 | /* Manually manage the write flush as we may have not yet | |
1120 | * retired the buffer. | |
1121 | */ | |
1122 | if (obj->last_write_seqno && | |
1123 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1124 | obj->last_write_seqno = 0; | |
1125 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1126 | } | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
3236f57a CW |
1131 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1132 | * as the object state may change during this call. | |
1133 | */ | |
1134 | static __must_check int | |
1135 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1136 | bool readonly) | |
1137 | { | |
1138 | struct drm_device *dev = obj->base.dev; | |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1140 | struct intel_ring_buffer *ring = obj->ring; | |
1141 | u32 seqno; | |
1142 | int ret; | |
1143 | ||
1144 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1145 | BUG_ON(!dev_priv->mm.interruptible); | |
1146 | ||
1147 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1148 | if (seqno == 0) | |
1149 | return 0; | |
1150 | ||
1151 | ret = i915_gem_check_wedge(dev_priv, true); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | ||
1155 | ret = i915_gem_check_olr(ring, seqno); | |
1156 | if (ret) | |
1157 | return ret; | |
1158 | ||
1159 | mutex_unlock(&dev->struct_mutex); | |
1160 | ret = __wait_seqno(ring, seqno, true, NULL); | |
1161 | mutex_lock(&dev->struct_mutex); | |
1162 | ||
1163 | i915_gem_retire_requests_ring(ring); | |
1164 | ||
1165 | /* Manually manage the write flush as we may have not yet | |
1166 | * retired the buffer. | |
1167 | */ | |
1168 | if (obj->last_write_seqno && | |
1169 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1170 | obj->last_write_seqno = 0; | |
1171 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1172 | } | |
1173 | ||
1174 | return ret; | |
1175 | } | |
1176 | ||
673a394b | 1177 | /** |
2ef7eeaa EA |
1178 | * Called when user space prepares to use an object with the CPU, either |
1179 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1180 | */ |
1181 | int | |
1182 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1183 | struct drm_file *file) |
673a394b EA |
1184 | { |
1185 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1186 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1187 | uint32_t read_domains = args->read_domains; |
1188 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1189 | int ret; |
1190 | ||
2ef7eeaa | 1191 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1192 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1193 | return -EINVAL; |
1194 | ||
21d509e3 | 1195 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1196 | return -EINVAL; |
1197 | ||
1198 | /* Having something in the write domain implies it's in the read | |
1199 | * domain, and only that read domain. Enforce that in the request. | |
1200 | */ | |
1201 | if (write_domain != 0 && read_domains != write_domain) | |
1202 | return -EINVAL; | |
1203 | ||
76c1dec1 | 1204 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1205 | if (ret) |
76c1dec1 | 1206 | return ret; |
1d7cfea1 | 1207 | |
05394f39 | 1208 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1209 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1210 | ret = -ENOENT; |
1211 | goto unlock; | |
76c1dec1 | 1212 | } |
673a394b | 1213 | |
3236f57a CW |
1214 | /* Try to flush the object off the GPU without holding the lock. |
1215 | * We will repeat the flush holding the lock in the normal manner | |
1216 | * to catch cases where we are gazumped. | |
1217 | */ | |
1218 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1219 | if (ret) | |
1220 | goto unref; | |
1221 | ||
2ef7eeaa EA |
1222 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1223 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1224 | |
1225 | /* Silently promote "you're not bound, there was nothing to do" | |
1226 | * to success, since the client was just asking us to | |
1227 | * make sure everything was done. | |
1228 | */ | |
1229 | if (ret == -EINVAL) | |
1230 | ret = 0; | |
2ef7eeaa | 1231 | } else { |
e47c68e9 | 1232 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1233 | } |
1234 | ||
3236f57a | 1235 | unref: |
05394f39 | 1236 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1237 | unlock: |
673a394b EA |
1238 | mutex_unlock(&dev->struct_mutex); |
1239 | return ret; | |
1240 | } | |
1241 | ||
1242 | /** | |
1243 | * Called when user space has done writes to this buffer | |
1244 | */ | |
1245 | int | |
1246 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1247 | struct drm_file *file) |
673a394b EA |
1248 | { |
1249 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1250 | struct drm_i915_gem_object *obj; |
673a394b EA |
1251 | int ret = 0; |
1252 | ||
76c1dec1 | 1253 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1254 | if (ret) |
76c1dec1 | 1255 | return ret; |
1d7cfea1 | 1256 | |
05394f39 | 1257 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1258 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1259 | ret = -ENOENT; |
1260 | goto unlock; | |
673a394b EA |
1261 | } |
1262 | ||
673a394b | 1263 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1264 | if (obj->pin_count) |
e47c68e9 EA |
1265 | i915_gem_object_flush_cpu_write_domain(obj); |
1266 | ||
05394f39 | 1267 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1268 | unlock: |
673a394b EA |
1269 | mutex_unlock(&dev->struct_mutex); |
1270 | return ret; | |
1271 | } | |
1272 | ||
1273 | /** | |
1274 | * Maps the contents of an object, returning the address it is mapped | |
1275 | * into. | |
1276 | * | |
1277 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1278 | * imply a ref on the object itself. | |
1279 | */ | |
1280 | int | |
1281 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1282 | struct drm_file *file) |
673a394b EA |
1283 | { |
1284 | struct drm_i915_gem_mmap *args = data; | |
1285 | struct drm_gem_object *obj; | |
673a394b EA |
1286 | unsigned long addr; |
1287 | ||
05394f39 | 1288 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1289 | if (obj == NULL) |
bf79cb91 | 1290 | return -ENOENT; |
673a394b | 1291 | |
1286ff73 DV |
1292 | /* prime objects have no backing filp to GEM mmap |
1293 | * pages from. | |
1294 | */ | |
1295 | if (!obj->filp) { | |
1296 | drm_gem_object_unreference_unlocked(obj); | |
1297 | return -EINVAL; | |
1298 | } | |
1299 | ||
6be5ceb0 | 1300 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1301 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1302 | args->offset); | |
bc9025bd | 1303 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1304 | if (IS_ERR((void *)addr)) |
1305 | return addr; | |
1306 | ||
1307 | args->addr_ptr = (uint64_t) addr; | |
1308 | ||
1309 | return 0; | |
1310 | } | |
1311 | ||
de151cf6 JB |
1312 | /** |
1313 | * i915_gem_fault - fault a page into the GTT | |
1314 | * vma: VMA in question | |
1315 | * vmf: fault info | |
1316 | * | |
1317 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1318 | * from userspace. The fault handler takes care of binding the object to | |
1319 | * the GTT (if needed), allocating and programming a fence register (again, | |
1320 | * only if needed based on whether the old reg is still valid or the object | |
1321 | * is tiled) and inserting a new PTE into the faulting process. | |
1322 | * | |
1323 | * Note that the faulting process may involve evicting existing objects | |
1324 | * from the GTT and/or fence registers to make room. So performance may | |
1325 | * suffer if the GTT working set is large or there are few fence registers | |
1326 | * left. | |
1327 | */ | |
1328 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1329 | { | |
05394f39 CW |
1330 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1331 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1332 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1333 | pgoff_t page_offset; |
1334 | unsigned long pfn; | |
1335 | int ret = 0; | |
0f973f27 | 1336 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1337 | |
1338 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1339 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1340 | PAGE_SHIFT; | |
1341 | ||
d9bc7e9f CW |
1342 | ret = i915_mutex_lock_interruptible(dev); |
1343 | if (ret) | |
1344 | goto out; | |
a00b10c3 | 1345 | |
db53a302 CW |
1346 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1347 | ||
d9bc7e9f | 1348 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1349 | if (!obj->map_and_fenceable) { |
1350 | ret = i915_gem_object_unbind(obj); | |
1351 | if (ret) | |
1352 | goto unlock; | |
a00b10c3 | 1353 | } |
05394f39 | 1354 | if (!obj->gtt_space) { |
86a1ee26 | 1355 | ret = i915_gem_object_bind_to_gtt(obj, 0, true, false); |
c715089f CW |
1356 | if (ret) |
1357 | goto unlock; | |
de151cf6 | 1358 | |
e92d03bf EA |
1359 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1360 | if (ret) | |
1361 | goto unlock; | |
1362 | } | |
4a684a41 | 1363 | |
74898d7e DV |
1364 | if (!obj->has_global_gtt_mapping) |
1365 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1366 | ||
06d98131 | 1367 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1368 | if (ret) |
1369 | goto unlock; | |
de151cf6 | 1370 | |
05394f39 CW |
1371 | if (i915_gem_object_is_inactive(obj)) |
1372 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1373 | |
6299f992 CW |
1374 | obj->fault_mappable = true; |
1375 | ||
dd2757f8 | 1376 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1377 | page_offset; |
1378 | ||
1379 | /* Finally, remap it using the new GTT offset */ | |
1380 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1381 | unlock: |
de151cf6 | 1382 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1383 | out: |
de151cf6 | 1384 | switch (ret) { |
d9bc7e9f | 1385 | case -EIO: |
a9340cca DV |
1386 | /* If this -EIO is due to a gpu hang, give the reset code a |
1387 | * chance to clean up the mess. Otherwise return the proper | |
1388 | * SIGBUS. */ | |
1389 | if (!atomic_read(&dev_priv->mm.wedged)) | |
1390 | return VM_FAULT_SIGBUS; | |
045e769a | 1391 | case -EAGAIN: |
d9bc7e9f CW |
1392 | /* Give the error handler a chance to run and move the |
1393 | * objects off the GPU active list. Next time we service the | |
1394 | * fault, we should be able to transition the page into the | |
1395 | * GTT without touching the GPU (and so avoid further | |
1396 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1397 | * with coherency, just lost writes. | |
1398 | */ | |
045e769a | 1399 | set_need_resched(); |
c715089f CW |
1400 | case 0: |
1401 | case -ERESTARTSYS: | |
bed636ab | 1402 | case -EINTR: |
c715089f | 1403 | return VM_FAULT_NOPAGE; |
de151cf6 | 1404 | case -ENOMEM: |
de151cf6 | 1405 | return VM_FAULT_OOM; |
de151cf6 | 1406 | default: |
c715089f | 1407 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1408 | } |
1409 | } | |
1410 | ||
901782b2 CW |
1411 | /** |
1412 | * i915_gem_release_mmap - remove physical page mappings | |
1413 | * @obj: obj in question | |
1414 | * | |
af901ca1 | 1415 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1416 | * relinquish ownership of the pages back to the system. |
1417 | * | |
1418 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1419 | * object through the GTT and then lose the fence register due to | |
1420 | * resource pressure. Similarly if the object has been moved out of the | |
1421 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1422 | * mapping will then trigger a page fault on the next user access, allowing | |
1423 | * fixup by i915_gem_fault(). | |
1424 | */ | |
d05ca301 | 1425 | void |
05394f39 | 1426 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1427 | { |
6299f992 CW |
1428 | if (!obj->fault_mappable) |
1429 | return; | |
901782b2 | 1430 | |
f6e47884 CW |
1431 | if (obj->base.dev->dev_mapping) |
1432 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1433 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1434 | obj->base.size, 1); | |
fb7d516a | 1435 | |
6299f992 | 1436 | obj->fault_mappable = false; |
901782b2 CW |
1437 | } |
1438 | ||
92b88aeb | 1439 | static uint32_t |
e28f8711 | 1440 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1441 | { |
e28f8711 | 1442 | uint32_t gtt_size; |
92b88aeb CW |
1443 | |
1444 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1445 | tiling_mode == I915_TILING_NONE) |
1446 | return size; | |
92b88aeb CW |
1447 | |
1448 | /* Previous chips need a power-of-two fence region when tiling */ | |
1449 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1450 | gtt_size = 1024*1024; |
92b88aeb | 1451 | else |
e28f8711 | 1452 | gtt_size = 512*1024; |
92b88aeb | 1453 | |
e28f8711 CW |
1454 | while (gtt_size < size) |
1455 | gtt_size <<= 1; | |
92b88aeb | 1456 | |
e28f8711 | 1457 | return gtt_size; |
92b88aeb CW |
1458 | } |
1459 | ||
de151cf6 JB |
1460 | /** |
1461 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1462 | * @obj: object to check | |
1463 | * | |
1464 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1465 | * potential fence register mapping. |
de151cf6 JB |
1466 | */ |
1467 | static uint32_t | |
e28f8711 CW |
1468 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1469 | uint32_t size, | |
1470 | int tiling_mode) | |
de151cf6 | 1471 | { |
de151cf6 JB |
1472 | /* |
1473 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1474 | * if a fence register is needed for the object. | |
1475 | */ | |
a00b10c3 | 1476 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1477 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1478 | return 4096; |
1479 | ||
a00b10c3 CW |
1480 | /* |
1481 | * Previous chips need to be aligned to the size of the smallest | |
1482 | * fence register that can contain the object. | |
1483 | */ | |
e28f8711 | 1484 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1485 | } |
1486 | ||
5e783301 DV |
1487 | /** |
1488 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1489 | * unfenced object | |
e28f8711 CW |
1490 | * @dev: the device |
1491 | * @size: size of the object | |
1492 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1493 | * |
1494 | * Return the required GTT alignment for an object, only taking into account | |
1495 | * unfenced tiled surface requirements. | |
1496 | */ | |
467cffba | 1497 | uint32_t |
e28f8711 CW |
1498 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1499 | uint32_t size, | |
1500 | int tiling_mode) | |
5e783301 | 1501 | { |
5e783301 DV |
1502 | /* |
1503 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1504 | */ | |
1505 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1506 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1507 | return 4096; |
1508 | ||
e28f8711 CW |
1509 | /* Previous hardware however needs to be aligned to a power-of-two |
1510 | * tile height. The simplest method for determining this is to reuse | |
1511 | * the power-of-tile object size. | |
5e783301 | 1512 | */ |
e28f8711 | 1513 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1514 | } |
1515 | ||
d8cb5086 CW |
1516 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1517 | { | |
1518 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1519 | int ret; | |
1520 | ||
1521 | if (obj->base.map_list.map) | |
1522 | return 0; | |
1523 | ||
1524 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1525 | if (ret != -ENOSPC) | |
1526 | return ret; | |
1527 | ||
1528 | /* Badly fragmented mmap space? The only way we can recover | |
1529 | * space is by destroying unwanted objects. We can't randomly release | |
1530 | * mmap_offsets as userspace expects them to be persistent for the | |
1531 | * lifetime of the objects. The closest we can is to release the | |
1532 | * offsets on purgeable objects by truncating it and marking it purged, | |
1533 | * which prevents userspace from ever using that object again. | |
1534 | */ | |
1535 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1536 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1537 | if (ret != -ENOSPC) | |
1538 | return ret; | |
1539 | ||
1540 | i915_gem_shrink_all(dev_priv); | |
1541 | return drm_gem_create_mmap_offset(&obj->base); | |
1542 | } | |
1543 | ||
1544 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1545 | { | |
1546 | if (!obj->base.map_list.map) | |
1547 | return; | |
1548 | ||
1549 | drm_gem_free_mmap_offset(&obj->base); | |
1550 | } | |
1551 | ||
de151cf6 | 1552 | int |
ff72145b DA |
1553 | i915_gem_mmap_gtt(struct drm_file *file, |
1554 | struct drm_device *dev, | |
1555 | uint32_t handle, | |
1556 | uint64_t *offset) | |
de151cf6 | 1557 | { |
da761a6e | 1558 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1559 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1560 | int ret; |
1561 | ||
76c1dec1 | 1562 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1563 | if (ret) |
76c1dec1 | 1564 | return ret; |
de151cf6 | 1565 | |
ff72145b | 1566 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1567 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1568 | ret = -ENOENT; |
1569 | goto unlock; | |
1570 | } | |
de151cf6 | 1571 | |
05394f39 | 1572 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1573 | ret = -E2BIG; |
ff56b0bc | 1574 | goto out; |
da761a6e CW |
1575 | } |
1576 | ||
05394f39 | 1577 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1578 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1579 | ret = -EINVAL; |
1580 | goto out; | |
ab18282d CW |
1581 | } |
1582 | ||
d8cb5086 CW |
1583 | ret = i915_gem_object_create_mmap_offset(obj); |
1584 | if (ret) | |
1585 | goto out; | |
de151cf6 | 1586 | |
ff72145b | 1587 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1588 | |
1d7cfea1 | 1589 | out: |
05394f39 | 1590 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1591 | unlock: |
de151cf6 | 1592 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1593 | return ret; |
de151cf6 JB |
1594 | } |
1595 | ||
ff72145b DA |
1596 | /** |
1597 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1598 | * @dev: DRM device | |
1599 | * @data: GTT mapping ioctl data | |
1600 | * @file: GEM object info | |
1601 | * | |
1602 | * Simply returns the fake offset to userspace so it can mmap it. | |
1603 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1604 | * up so we can get faults in the handler above. | |
1605 | * | |
1606 | * The fault handler will take care of binding the object into the GTT | |
1607 | * (since it may have been evicted to make room for something), allocating | |
1608 | * a fence register, and mapping the appropriate aperture address into | |
1609 | * userspace. | |
1610 | */ | |
1611 | int | |
1612 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1613 | struct drm_file *file) | |
1614 | { | |
1615 | struct drm_i915_gem_mmap_gtt *args = data; | |
1616 | ||
ff72145b DA |
1617 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1618 | } | |
1619 | ||
225067ee DV |
1620 | /* Immediately discard the backing storage */ |
1621 | static void | |
1622 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1623 | { |
e5281ccd | 1624 | struct inode *inode; |
e5281ccd | 1625 | |
4d6294bf | 1626 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1627 | |
4d6294bf CW |
1628 | if (obj->base.filp == NULL) |
1629 | return; | |
e5281ccd | 1630 | |
225067ee DV |
1631 | /* Our goal here is to return as much of the memory as |
1632 | * is possible back to the system as we are called from OOM. | |
1633 | * To do this we must instruct the shmfs to drop all of its | |
1634 | * backing pages, *now*. | |
1635 | */ | |
05394f39 | 1636 | inode = obj->base.filp->f_path.dentry->d_inode; |
225067ee | 1637 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1638 | |
225067ee DV |
1639 | obj->madv = __I915_MADV_PURGED; |
1640 | } | |
e5281ccd | 1641 | |
225067ee DV |
1642 | static inline int |
1643 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1644 | { | |
1645 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1646 | } |
1647 | ||
37e680a1 | 1648 | static void |
05394f39 | 1649 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1650 | { |
05394f39 | 1651 | int page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1652 | struct scatterlist *sg; |
6c085a72 | 1653 | int ret, i; |
673a394b | 1654 | |
05394f39 | 1655 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1656 | |
6c085a72 CW |
1657 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1658 | if (ret) { | |
1659 | /* In the event of a disaster, abandon all caches and | |
1660 | * hope for the best. | |
1661 | */ | |
1662 | WARN_ON(ret != -EIO); | |
1663 | i915_gem_clflush_object(obj); | |
1664 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1665 | } | |
1666 | ||
6dacfd2f | 1667 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1668 | i915_gem_object_save_bit_17_swizzle(obj); |
1669 | ||
05394f39 CW |
1670 | if (obj->madv == I915_MADV_DONTNEED) |
1671 | obj->dirty = 0; | |
3ef94daa | 1672 | |
9da3da66 CW |
1673 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
1674 | struct page *page = sg_page(sg); | |
1675 | ||
05394f39 | 1676 | if (obj->dirty) |
9da3da66 | 1677 | set_page_dirty(page); |
3ef94daa | 1678 | |
05394f39 | 1679 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1680 | mark_page_accessed(page); |
3ef94daa | 1681 | |
9da3da66 | 1682 | page_cache_release(page); |
3ef94daa | 1683 | } |
05394f39 | 1684 | obj->dirty = 0; |
673a394b | 1685 | |
9da3da66 CW |
1686 | sg_free_table(obj->pages); |
1687 | kfree(obj->pages); | |
37e680a1 | 1688 | } |
6c085a72 | 1689 | |
37e680a1 CW |
1690 | static int |
1691 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) | |
1692 | { | |
1693 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1694 | ||
2f745ad3 | 1695 | if (obj->pages == NULL) |
37e680a1 CW |
1696 | return 0; |
1697 | ||
1698 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1699 | |
a5570178 CW |
1700 | if (obj->pages_pin_count) |
1701 | return -EBUSY; | |
1702 | ||
37e680a1 | 1703 | ops->put_pages(obj); |
9da3da66 | 1704 | obj->pages = NULL; |
37e680a1 CW |
1705 | |
1706 | list_del(&obj->gtt_list); | |
6c085a72 CW |
1707 | if (i915_gem_object_is_purgeable(obj)) |
1708 | i915_gem_object_truncate(obj); | |
1709 | ||
1710 | return 0; | |
1711 | } | |
1712 | ||
1713 | static long | |
1714 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1715 | { | |
1716 | struct drm_i915_gem_object *obj, *next; | |
1717 | long count = 0; | |
1718 | ||
1719 | list_for_each_entry_safe(obj, next, | |
1720 | &dev_priv->mm.unbound_list, | |
1721 | gtt_list) { | |
1722 | if (i915_gem_object_is_purgeable(obj) && | |
37e680a1 | 1723 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1724 | count += obj->base.size >> PAGE_SHIFT; |
1725 | if (count >= target) | |
1726 | return count; | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | list_for_each_entry_safe(obj, next, | |
1731 | &dev_priv->mm.inactive_list, | |
1732 | mm_list) { | |
1733 | if (i915_gem_object_is_purgeable(obj) && | |
1734 | i915_gem_object_unbind(obj) == 0 && | |
37e680a1 | 1735 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1736 | count += obj->base.size >> PAGE_SHIFT; |
1737 | if (count >= target) | |
1738 | return count; | |
1739 | } | |
1740 | } | |
1741 | ||
1742 | return count; | |
1743 | } | |
1744 | ||
1745 | static void | |
1746 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1747 | { | |
1748 | struct drm_i915_gem_object *obj, *next; | |
1749 | ||
1750 | i915_gem_evict_everything(dev_priv->dev); | |
1751 | ||
1752 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1753 | i915_gem_object_put_pages(obj); |
225067ee DV |
1754 | } |
1755 | ||
37e680a1 | 1756 | static int |
6c085a72 | 1757 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1758 | { |
6c085a72 | 1759 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1760 | int page_count, i; |
1761 | struct address_space *mapping; | |
9da3da66 CW |
1762 | struct sg_table *st; |
1763 | struct scatterlist *sg; | |
e5281ccd | 1764 | struct page *page; |
6c085a72 | 1765 | gfp_t gfp; |
e5281ccd | 1766 | |
6c085a72 CW |
1767 | /* Assert that the object is not currently in any GPU domain. As it |
1768 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1769 | * a GPU cache | |
1770 | */ | |
1771 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1772 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1773 | ||
9da3da66 CW |
1774 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1775 | if (st == NULL) | |
1776 | return -ENOMEM; | |
1777 | ||
05394f39 | 1778 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1779 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1780 | sg_free_table(st); | |
1781 | kfree(st); | |
e5281ccd | 1782 | return -ENOMEM; |
9da3da66 | 1783 | } |
e5281ccd | 1784 | |
9da3da66 CW |
1785 | /* Get the list of pages out of our struct file. They'll be pinned |
1786 | * at this point until we release them. | |
1787 | * | |
1788 | * Fail silently without starting the shrinker | |
1789 | */ | |
6c085a72 CW |
1790 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
1791 | gfp = mapping_gfp_mask(mapping); | |
d7c3b937 | 1792 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 | 1793 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
9da3da66 | 1794 | for_each_sg(st->sgl, sg, page_count, i) { |
6c085a72 CW |
1795 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1796 | if (IS_ERR(page)) { | |
1797 | i915_gem_purge(dev_priv, page_count); | |
1798 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1799 | } | |
1800 | if (IS_ERR(page)) { | |
1801 | /* We've tried hard to allocate the memory by reaping | |
1802 | * our own buffer, now let the real VM do its job and | |
1803 | * go down in flames if truly OOM. | |
1804 | */ | |
d7c3b937 | 1805 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN); |
6c085a72 CW |
1806 | gfp |= __GFP_IO | __GFP_WAIT; |
1807 | ||
1808 | i915_gem_shrink_all(dev_priv); | |
1809 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1810 | if (IS_ERR(page)) | |
1811 | goto err_pages; | |
1812 | ||
d7c3b937 | 1813 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 CW |
1814 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1815 | } | |
e5281ccd | 1816 | |
9da3da66 | 1817 | sg_set_page(sg, page, PAGE_SIZE, 0); |
e5281ccd CW |
1818 | } |
1819 | ||
6dacfd2f | 1820 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1821 | i915_gem_object_do_bit_17_swizzle(obj); |
1822 | ||
9da3da66 | 1823 | obj->pages = st; |
e5281ccd CW |
1824 | return 0; |
1825 | ||
1826 | err_pages: | |
9da3da66 CW |
1827 | for_each_sg(st->sgl, sg, i, page_count) |
1828 | page_cache_release(sg_page(sg)); | |
1829 | sg_free_table(st); | |
1830 | kfree(st); | |
e5281ccd | 1831 | return PTR_ERR(page); |
673a394b EA |
1832 | } |
1833 | ||
37e680a1 CW |
1834 | /* Ensure that the associated pages are gathered from the backing storage |
1835 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1836 | * multiple times before they are released by a single call to | |
1837 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1838 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1839 | * or as the object is itself released. | |
1840 | */ | |
1841 | int | |
1842 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1843 | { | |
1844 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1845 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1846 | int ret; | |
1847 | ||
2f745ad3 | 1848 | if (obj->pages) |
37e680a1 CW |
1849 | return 0; |
1850 | ||
a5570178 CW |
1851 | BUG_ON(obj->pages_pin_count); |
1852 | ||
37e680a1 CW |
1853 | ret = ops->get_pages(obj); |
1854 | if (ret) | |
1855 | return ret; | |
1856 | ||
1857 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1858 | return 0; | |
1859 | } | |
1860 | ||
54cf91dc | 1861 | void |
05394f39 | 1862 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1863 | struct intel_ring_buffer *ring, |
1864 | u32 seqno) | |
673a394b | 1865 | { |
05394f39 | 1866 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1868 | |
852835f3 | 1869 | BUG_ON(ring == NULL); |
05394f39 | 1870 | obj->ring = ring; |
673a394b EA |
1871 | |
1872 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1873 | if (!obj->active) { |
1874 | drm_gem_object_reference(&obj->base); | |
1875 | obj->active = 1; | |
673a394b | 1876 | } |
e35a41de | 1877 | |
673a394b | 1878 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1879 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1880 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1881 | |
0201f1ec | 1882 | obj->last_read_seqno = seqno; |
caea7476 | 1883 | |
7dd49065 | 1884 | if (obj->fenced_gpu_access) { |
caea7476 | 1885 | obj->last_fenced_seqno = seqno; |
caea7476 | 1886 | |
7dd49065 CW |
1887 | /* Bump MRU to take account of the delayed flush */ |
1888 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1889 | struct drm_i915_fence_reg *reg; | |
1890 | ||
1891 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1892 | list_move_tail(®->lru_list, | |
1893 | &dev_priv->mm.fence_list); | |
1894 | } | |
caea7476 CW |
1895 | } |
1896 | } | |
1897 | ||
caea7476 CW |
1898 | static void |
1899 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1900 | { | |
1901 | struct drm_device *dev = obj->base.dev; | |
1902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1903 | ||
65ce3027 | 1904 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
caea7476 | 1905 | BUG_ON(!obj->active); |
65ce3027 | 1906 | |
f047e395 CW |
1907 | if (obj->pin_count) /* are we a framebuffer? */ |
1908 | intel_mark_fb_idle(obj); | |
1909 | ||
1910 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1911 | ||
65ce3027 | 1912 | list_del_init(&obj->ring_list); |
caea7476 CW |
1913 | obj->ring = NULL; |
1914 | ||
65ce3027 CW |
1915 | obj->last_read_seqno = 0; |
1916 | obj->last_write_seqno = 0; | |
1917 | obj->base.write_domain = 0; | |
1918 | ||
1919 | obj->last_fenced_seqno = 0; | |
caea7476 | 1920 | obj->fenced_gpu_access = false; |
caea7476 CW |
1921 | |
1922 | obj->active = 0; | |
1923 | drm_gem_object_unreference(&obj->base); | |
1924 | ||
1925 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1926 | } |
673a394b | 1927 | |
53d227f2 DV |
1928 | static u32 |
1929 | i915_gem_get_seqno(struct drm_device *dev) | |
1930 | { | |
1931 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1932 | u32 seqno = dev_priv->next_seqno; | |
1933 | ||
1934 | /* reserve 0 for non-seqno */ | |
1935 | if (++dev_priv->next_seqno == 0) | |
1936 | dev_priv->next_seqno = 1; | |
1937 | ||
1938 | return seqno; | |
1939 | } | |
1940 | ||
1941 | u32 | |
1942 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1943 | { | |
1944 | if (ring->outstanding_lazy_request == 0) | |
1945 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1946 | ||
1947 | return ring->outstanding_lazy_request; | |
1948 | } | |
1949 | ||
3cce469c | 1950 | int |
db53a302 | 1951 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1952 | struct drm_file *file, |
db53a302 | 1953 | struct drm_i915_gem_request *request) |
673a394b | 1954 | { |
db53a302 | 1955 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1956 | uint32_t seqno; |
a71d8d94 | 1957 | u32 request_ring_position; |
673a394b | 1958 | int was_empty; |
3cce469c CW |
1959 | int ret; |
1960 | ||
cc889e0f DV |
1961 | /* |
1962 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1963 | * after having emitted the batchbuffer command. Hence we need to fix | |
1964 | * things up similar to emitting the lazy request. The difference here | |
1965 | * is that the flush _must_ happen before the next request, no matter | |
1966 | * what. | |
1967 | */ | |
a7b9761d CW |
1968 | ret = intel_ring_flush_all_caches(ring); |
1969 | if (ret) | |
1970 | return ret; | |
cc889e0f | 1971 | |
3bb73aba CW |
1972 | if (request == NULL) { |
1973 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1974 | if (request == NULL) | |
1975 | return -ENOMEM; | |
1976 | } | |
1977 | ||
53d227f2 | 1978 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1979 | |
a71d8d94 CW |
1980 | /* Record the position of the start of the request so that |
1981 | * should we detect the updated seqno part-way through the | |
1982 | * GPU processing the request, we never over-estimate the | |
1983 | * position of the head. | |
1984 | */ | |
1985 | request_ring_position = intel_ring_get_tail(ring); | |
1986 | ||
3cce469c | 1987 | ret = ring->add_request(ring, &seqno); |
3bb73aba CW |
1988 | if (ret) { |
1989 | kfree(request); | |
1990 | return ret; | |
1991 | } | |
673a394b | 1992 | |
db53a302 | 1993 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1994 | |
1995 | request->seqno = seqno; | |
852835f3 | 1996 | request->ring = ring; |
a71d8d94 | 1997 | request->tail = request_ring_position; |
673a394b | 1998 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1999 | was_empty = list_empty(&ring->request_list); |
2000 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2001 | request->file_priv = NULL; |
852835f3 | 2002 | |
db53a302 CW |
2003 | if (file) { |
2004 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2005 | ||
1c25595f | 2006 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2007 | request->file_priv = file_priv; |
b962442e | 2008 | list_add_tail(&request->client_list, |
f787a5f5 | 2009 | &file_priv->mm.request_list); |
1c25595f | 2010 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2011 | } |
673a394b | 2012 | |
5391d0cf | 2013 | ring->outstanding_lazy_request = 0; |
db53a302 | 2014 | |
f65d9421 | 2015 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
2016 | if (i915_enable_hangcheck) { |
2017 | mod_timer(&dev_priv->hangcheck_timer, | |
2018 | jiffies + | |
2019 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
2020 | } | |
f047e395 | 2021 | if (was_empty) { |
b3b079db CW |
2022 | queue_delayed_work(dev_priv->wq, |
2023 | &dev_priv->mm.retire_work, HZ); | |
f047e395 CW |
2024 | intel_mark_busy(dev_priv->dev); |
2025 | } | |
f65d9421 | 2026 | } |
cc889e0f | 2027 | |
3cce469c | 2028 | return 0; |
673a394b EA |
2029 | } |
2030 | ||
f787a5f5 CW |
2031 | static inline void |
2032 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2033 | { |
1c25595f | 2034 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2035 | |
1c25595f CW |
2036 | if (!file_priv) |
2037 | return; | |
1c5d22f7 | 2038 | |
1c25595f | 2039 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2040 | if (request->file_priv) { |
2041 | list_del(&request->client_list); | |
2042 | request->file_priv = NULL; | |
2043 | } | |
1c25595f | 2044 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2045 | } |
673a394b | 2046 | |
dfaae392 CW |
2047 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2048 | struct intel_ring_buffer *ring) | |
9375e446 | 2049 | { |
dfaae392 CW |
2050 | while (!list_empty(&ring->request_list)) { |
2051 | struct drm_i915_gem_request *request; | |
673a394b | 2052 | |
dfaae392 CW |
2053 | request = list_first_entry(&ring->request_list, |
2054 | struct drm_i915_gem_request, | |
2055 | list); | |
de151cf6 | 2056 | |
dfaae392 | 2057 | list_del(&request->list); |
f787a5f5 | 2058 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2059 | kfree(request); |
2060 | } | |
673a394b | 2061 | |
dfaae392 | 2062 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2063 | struct drm_i915_gem_object *obj; |
9375e446 | 2064 | |
05394f39 CW |
2065 | obj = list_first_entry(&ring->active_list, |
2066 | struct drm_i915_gem_object, | |
2067 | ring_list); | |
9375e446 | 2068 | |
05394f39 | 2069 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2070 | } |
2071 | } | |
2072 | ||
312817a3 CW |
2073 | static void i915_gem_reset_fences(struct drm_device *dev) |
2074 | { | |
2075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2076 | int i; | |
2077 | ||
4b9de737 | 2078 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2079 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2080 | |
ada726c7 | 2081 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 2082 | |
ada726c7 CW |
2083 | if (reg->obj) |
2084 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2085 | |
ada726c7 CW |
2086 | reg->pin_count = 0; |
2087 | reg->obj = NULL; | |
2088 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2089 | } |
ada726c7 CW |
2090 | |
2091 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2092 | } |
2093 | ||
069efc1d | 2094 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2095 | { |
77f01230 | 2096 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2097 | struct drm_i915_gem_object *obj; |
b4519513 | 2098 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2099 | int i; |
673a394b | 2100 | |
b4519513 CW |
2101 | for_each_ring(ring, dev_priv, i) |
2102 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2103 | |
dfaae392 CW |
2104 | /* Move everything out of the GPU domains to ensure we do any |
2105 | * necessary invalidation upon reuse. | |
2106 | */ | |
05394f39 | 2107 | list_for_each_entry(obj, |
77f01230 | 2108 | &dev_priv->mm.inactive_list, |
69dc4987 | 2109 | mm_list) |
77f01230 | 2110 | { |
05394f39 | 2111 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2112 | } |
069efc1d CW |
2113 | |
2114 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 2115 | i915_gem_reset_fences(dev); |
673a394b EA |
2116 | } |
2117 | ||
2118 | /** | |
2119 | * This function clears the request list as sequence numbers are passed. | |
2120 | */ | |
a71d8d94 | 2121 | void |
db53a302 | 2122 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2123 | { |
673a394b | 2124 | uint32_t seqno; |
1ec14ad3 | 2125 | int i; |
673a394b | 2126 | |
db53a302 | 2127 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2128 | return; |
2129 | ||
db53a302 | 2130 | WARN_ON(i915_verify_lists(ring->dev)); |
5c81fe85 | 2131 | |
b2eadbc8 | 2132 | seqno = ring->get_seqno(ring, true); |
604dd3ec | 2133 | |
076e2c0e | 2134 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
2135 | if (seqno >= ring->sync_seqno[i]) |
2136 | ring->sync_seqno[i] = 0; | |
5c81fe85 | 2137 | |
852835f3 | 2138 | while (!list_empty(&ring->request_list)) { |
673a394b | 2139 | struct drm_i915_gem_request *request; |
604dd3ec | 2140 | |
852835f3 | 2141 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2142 | struct drm_i915_gem_request, |
2143 | list); | |
5c81fe85 | 2144 | |
dfaae392 | 2145 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c | 2146 | break; |
604dd3ec | 2147 | |
db53a302 | 2148 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2149 | /* We know the GPU must have read the request to have |
2150 | * sent us the seqno + interrupt, so use the position | |
2151 | * of tail of the request to update the last known position | |
2152 | * of the GPU head. | |
2153 | */ | |
2154 | ring->last_retired_head = request->tail; | |
604dd3ec | 2155 | |
b84d5f0c | 2156 | list_del(&request->list); |
f787a5f5 | 2157 | i915_gem_request_remove_from_client(request); |
b84d5f0c | 2158 | kfree(request); |
5c81fe85 BW |
2159 | } |
2160 | ||
b84d5f0c CW |
2161 | /* Move any buffers on the active list that are no longer referenced |
2162 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2163 | */ | |
2164 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2165 | struct drm_i915_gem_object *obj; |
604dd3ec | 2166 | |
0206e353 | 2167 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2168 | struct drm_i915_gem_object, |
2169 | ring_list); | |
673a394b | 2170 | |
0201f1ec | 2171 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2172 | break; |
673a394b | 2173 | |
65ce3027 | 2174 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2175 | } |
3cce469c | 2176 | |
db53a302 CW |
2177 | if (unlikely(ring->trace_irq_seqno && |
2178 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2179 | ring->irq_put(ring); |
db53a302 | 2180 | ring->trace_irq_seqno = 0; |
9d34e5db | 2181 | } |
23bc5982 | 2182 | |
db53a302 | 2183 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2184 | } |
ffed1d09 | 2185 | |
b09a1fec CW |
2186 | void |
2187 | i915_gem_retire_requests(struct drm_device *dev) | |
2188 | { | |
2189 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2190 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2191 | int i; |
673a394b | 2192 | |
b4519513 CW |
2193 | for_each_ring(ring, dev_priv, i) |
2194 | i915_gem_retire_requests_ring(ring); | |
673a394b EA |
2195 | } |
2196 | ||
75ef9da2 | 2197 | static void |
673a394b | 2198 | i915_gem_retire_work_handler(struct work_struct *work) |
673a394b | 2199 | { |
673a394b EA |
2200 | drm_i915_private_t *dev_priv; |
2201 | struct drm_device *dev; | |
b4519513 | 2202 | struct intel_ring_buffer *ring; |
0a58705b CW |
2203 | bool idle; |
2204 | int i; | |
673a394b | 2205 | |
673a394b EA |
2206 | dev_priv = container_of(work, drm_i915_private_t, |
2207 | mm.retire_work.work); | |
2208 | dev = dev_priv->dev; | |
0201f1ec | 2209 | |
891b48cf CW |
2210 | /* Come back later if the device is busy... */ |
2211 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2212 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2213 | return; | |
2214 | } | |
2215 | ||
b09a1fec | 2216 | i915_gem_retire_requests(dev); |
0201f1ec | 2217 | |
0a58705b CW |
2218 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2219 | * objects indefinitely. | |
0201f1ec | 2220 | */ |
0a58705b | 2221 | idle = true; |
b4519513 | 2222 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2223 | if (ring->gpu_caches_dirty) |
2224 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2225 | |
2226 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2227 | } |
2228 | ||
0a58705b | 2229 | if (!dev_priv->mm.suspended && !idle) |
9c9fe1f8 | 2230 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
f047e395 CW |
2231 | if (idle) |
2232 | intel_mark_idle(dev); | |
0a58705b | 2233 | |
673a394b | 2234 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2235 | } |
2236 | ||
30dfebf3 DV |
2237 | /** |
2238 | * Ensures that an object will eventually get non-busy by flushing any required | |
2239 | * write domains, emitting any outstanding lazy request and retiring and | |
2240 | * completed requests. | |
2241 | */ | |
2242 | static int | |
2243 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2244 | { | |
2245 | int ret; | |
2246 | ||
2247 | if (obj->active) { | |
0201f1ec | 2248 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2249 | if (ret) |
2250 | return ret; | |
0201f1ec | 2251 | |
30dfebf3 DV |
2252 | i915_gem_retire_requests_ring(obj->ring); |
2253 | } | |
2254 | ||
2255 | return 0; | |
2256 | } | |
2257 | ||
23ba4fd0 BW |
2258 | /** |
2259 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2260 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2261 | * | |
2262 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2263 | * the timeout parameter. | |
2264 | * -ETIME: object is still busy after timeout | |
2265 | * -ERESTARTSYS: signal interrupted the wait | |
2266 | * -ENONENT: object doesn't exist | |
2267 | * Also possible, but rare: | |
2268 | * -EAGAIN: GPU wedged | |
2269 | * -ENOMEM: damn | |
2270 | * -ENODEV: Internal IRQ fail | |
2271 | * -E?: The add request failed | |
2272 | * | |
2273 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2274 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2275 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2276 | * without holding struct_mutex the object may become re-busied before this | |
2277 | * function completes. A similar but shorter * race condition exists in the busy | |
2278 | * ioctl | |
2279 | */ | |
2280 | int | |
2281 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2282 | { | |
2283 | struct drm_i915_gem_wait *args = data; | |
2284 | struct drm_i915_gem_object *obj; | |
2285 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2286 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2287 | u32 seqno = 0; |
2288 | int ret = 0; | |
2289 | ||
eac1f14f BW |
2290 | if (args->timeout_ns >= 0) { |
2291 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2292 | timeout = &timeout_stack; | |
2293 | } | |
23ba4fd0 BW |
2294 | |
2295 | ret = i915_mutex_lock_interruptible(dev); | |
2296 | if (ret) | |
2297 | return ret; | |
2298 | ||
2299 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2300 | if (&obj->base == NULL) { | |
2301 | mutex_unlock(&dev->struct_mutex); | |
2302 | return -ENOENT; | |
2303 | } | |
2304 | ||
30dfebf3 DV |
2305 | /* Need to make sure the object gets inactive eventually. */ |
2306 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2307 | if (ret) |
2308 | goto out; | |
2309 | ||
2310 | if (obj->active) { | |
0201f1ec | 2311 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2312 | ring = obj->ring; |
2313 | } | |
2314 | ||
2315 | if (seqno == 0) | |
2316 | goto out; | |
2317 | ||
23ba4fd0 BW |
2318 | /* Do this after OLR check to make sure we make forward progress polling |
2319 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2320 | */ | |
2321 | if (!args->timeout_ns) { | |
2322 | ret = -ETIME; | |
2323 | goto out; | |
2324 | } | |
2325 | ||
2326 | drm_gem_object_unreference(&obj->base); | |
2327 | mutex_unlock(&dev->struct_mutex); | |
2328 | ||
eac1f14f BW |
2329 | ret = __wait_seqno(ring, seqno, true, timeout); |
2330 | if (timeout) { | |
2331 | WARN_ON(!timespec_valid(timeout)); | |
2332 | args->timeout_ns = timespec_to_ns(timeout); | |
2333 | } | |
23ba4fd0 BW |
2334 | return ret; |
2335 | ||
2336 | out: | |
2337 | drm_gem_object_unreference(&obj->base); | |
2338 | mutex_unlock(&dev->struct_mutex); | |
2339 | return ret; | |
2340 | } | |
2341 | ||
5816d648 BW |
2342 | /** |
2343 | * i915_gem_object_sync - sync an object to a ring. | |
2344 | * | |
2345 | * @obj: object which may be in use on another ring. | |
2346 | * @to: ring we wish to use the object on. May be NULL. | |
2347 | * | |
2348 | * This code is meant to abstract object synchronization with the GPU. | |
2349 | * Calling with NULL implies synchronizing the object with the CPU | |
2350 | * rather than a particular GPU ring. | |
2351 | * | |
2352 | * Returns 0 if successful, else propagates up the lower layer error. | |
2353 | */ | |
2911a35b BW |
2354 | int |
2355 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2356 | struct intel_ring_buffer *to) | |
2357 | { | |
2358 | struct intel_ring_buffer *from = obj->ring; | |
2359 | u32 seqno; | |
2360 | int ret, idx; | |
2361 | ||
2362 | if (from == NULL || to == from) | |
2363 | return 0; | |
2364 | ||
5816d648 | 2365 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2366 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2367 | |
2368 | idx = intel_ring_sync_index(from, to); | |
2369 | ||
0201f1ec | 2370 | seqno = obj->last_read_seqno; |
2911a35b BW |
2371 | if (seqno <= from->sync_seqno[idx]) |
2372 | return 0; | |
2373 | ||
b4aca010 BW |
2374 | ret = i915_gem_check_olr(obj->ring, seqno); |
2375 | if (ret) | |
2376 | return ret; | |
2911a35b | 2377 | |
1500f7ea | 2378 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
2379 | if (!ret) |
2380 | from->sync_seqno[idx] = seqno; | |
2911a35b | 2381 | |
e3a5a225 | 2382 | return ret; |
2911a35b BW |
2383 | } |
2384 | ||
b5ffc9bc CW |
2385 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2386 | { | |
2387 | u32 old_write_domain, old_read_domains; | |
2388 | ||
b5ffc9bc CW |
2389 | /* Act a barrier for all accesses through the GTT */ |
2390 | mb(); | |
2391 | ||
2392 | /* Force a pagefault for domain tracking on next user access */ | |
2393 | i915_gem_release_mmap(obj); | |
2394 | ||
b97c3d9c KP |
2395 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2396 | return; | |
2397 | ||
b5ffc9bc CW |
2398 | old_read_domains = obj->base.read_domains; |
2399 | old_write_domain = obj->base.write_domain; | |
2400 | ||
2401 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2402 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2403 | ||
2404 | trace_i915_gem_object_change_domain(obj, | |
2405 | old_read_domains, | |
2406 | old_write_domain); | |
2407 | } | |
2408 | ||
673a394b EA |
2409 | /** |
2410 | * Unbinds an object from the GTT aperture. | |
2411 | */ | |
0f973f27 | 2412 | int |
05394f39 | 2413 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2414 | { |
7bddb01f | 2415 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2416 | int ret = 0; |
2417 | ||
05394f39 | 2418 | if (obj->gtt_space == NULL) |
673a394b EA |
2419 | return 0; |
2420 | ||
31d8d651 CW |
2421 | if (obj->pin_count) |
2422 | return -EBUSY; | |
673a394b | 2423 | |
c4670ad0 CW |
2424 | BUG_ON(obj->pages == NULL); |
2425 | ||
a8198eea | 2426 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2427 | if (ret) |
a8198eea CW |
2428 | return ret; |
2429 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2430 | * should be safe and we need to cleanup or else we might | |
2431 | * cause memory corruption through use-after-free. | |
2432 | */ | |
2433 | ||
b5ffc9bc | 2434 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2435 | |
96b47b65 | 2436 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2437 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2438 | if (ret) |
d9e86c0e | 2439 | return ret; |
96b47b65 | 2440 | |
db53a302 CW |
2441 | trace_i915_gem_object_unbind(obj); |
2442 | ||
74898d7e DV |
2443 | if (obj->has_global_gtt_mapping) |
2444 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2445 | if (obj->has_aliasing_ppgtt_mapping) { |
2446 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2447 | obj->has_aliasing_ppgtt_mapping = 0; | |
2448 | } | |
74163907 | 2449 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2450 | |
6c085a72 CW |
2451 | list_del(&obj->mm_list); |
2452 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2453 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2454 | obj->map_and_fenceable = true; |
673a394b | 2455 | |
05394f39 CW |
2456 | drm_mm_put_block(obj->gtt_space); |
2457 | obj->gtt_space = NULL; | |
2458 | obj->gtt_offset = 0; | |
673a394b | 2459 | |
6c085a72 | 2460 | return 0; |
673a394b EA |
2461 | } |
2462 | ||
b2da9fe5 | 2463 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2464 | { |
69c2fc89 | 2465 | if (list_empty(&ring->active_list)) |
64193406 CW |
2466 | return 0; |
2467 | ||
199b2bc2 | 2468 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2469 | } |
2470 | ||
b2da9fe5 | 2471 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2472 | { |
2473 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2474 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2475 | int ret, i; |
4df2faf4 | 2476 | |
4df2faf4 | 2477 | /* Flush everything onto the inactive list. */ |
b4519513 | 2478 | for_each_ring(ring, dev_priv, i) { |
b6c7488d | 2479 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
1ec14ad3 CW |
2480 | if (ret) |
2481 | return ret; | |
b4519513 | 2482 | |
b4519513 | 2483 | ret = i915_ring_idle(ring); |
f2ef6eb1 BW |
2484 | if (ret) |
2485 | return ret; | |
1ec14ad3 | 2486 | } |
4df2faf4 | 2487 | |
8a1a49f9 | 2488 | return 0; |
4df2faf4 DV |
2489 | } |
2490 | ||
9ce079e4 CW |
2491 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2492 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2493 | { |
4e901fdc | 2494 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2495 | uint64_t val; |
2496 | ||
9ce079e4 CW |
2497 | if (obj) { |
2498 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2499 | |
9ce079e4 CW |
2500 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2501 | 0xfffff000) << 32; | |
2502 | val |= obj->gtt_offset & 0xfffff000; | |
2503 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2504 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2505 | |
9ce079e4 CW |
2506 | if (obj->tiling_mode == I915_TILING_Y) |
2507 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2508 | val |= I965_FENCE_REG_VALID; | |
2509 | } else | |
2510 | val = 0; | |
c6642782 | 2511 | |
9ce079e4 CW |
2512 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2513 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2514 | } |
2515 | ||
9ce079e4 CW |
2516 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2517 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2518 | { |
de151cf6 | 2519 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2520 | uint64_t val; |
2521 | ||
9ce079e4 CW |
2522 | if (obj) { |
2523 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2524 | |
9ce079e4 CW |
2525 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2526 | 0xfffff000) << 32; | |
2527 | val |= obj->gtt_offset & 0xfffff000; | |
2528 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2529 | if (obj->tiling_mode == I915_TILING_Y) | |
2530 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2531 | val |= I965_FENCE_REG_VALID; | |
2532 | } else | |
2533 | val = 0; | |
c6642782 | 2534 | |
9ce079e4 CW |
2535 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2536 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2537 | } |
2538 | ||
9ce079e4 CW |
2539 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2540 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2541 | { |
de151cf6 | 2542 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2543 | u32 val; |
de151cf6 | 2544 | |
9ce079e4 CW |
2545 | if (obj) { |
2546 | u32 size = obj->gtt_space->size; | |
2547 | int pitch_val; | |
2548 | int tile_width; | |
c6642782 | 2549 | |
9ce079e4 CW |
2550 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2551 | (size & -size) != size || | |
2552 | (obj->gtt_offset & (size - 1)), | |
2553 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2554 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2555 | |
9ce079e4 CW |
2556 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2557 | tile_width = 128; | |
2558 | else | |
2559 | tile_width = 512; | |
2560 | ||
2561 | /* Note: pitch better be a power of two tile widths */ | |
2562 | pitch_val = obj->stride / tile_width; | |
2563 | pitch_val = ffs(pitch_val) - 1; | |
2564 | ||
2565 | val = obj->gtt_offset; | |
2566 | if (obj->tiling_mode == I915_TILING_Y) | |
2567 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2568 | val |= I915_FENCE_SIZE_BITS(size); | |
2569 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2570 | val |= I830_FENCE_REG_VALID; | |
2571 | } else | |
2572 | val = 0; | |
2573 | ||
2574 | if (reg < 8) | |
2575 | reg = FENCE_REG_830_0 + reg * 4; | |
2576 | else | |
2577 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2578 | ||
2579 | I915_WRITE(reg, val); | |
2580 | POSTING_READ(reg); | |
de151cf6 JB |
2581 | } |
2582 | ||
9ce079e4 CW |
2583 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2584 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2585 | { |
de151cf6 | 2586 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2587 | uint32_t val; |
de151cf6 | 2588 | |
9ce079e4 CW |
2589 | if (obj) { |
2590 | u32 size = obj->gtt_space->size; | |
2591 | uint32_t pitch_val; | |
de151cf6 | 2592 | |
9ce079e4 CW |
2593 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2594 | (size & -size) != size || | |
2595 | (obj->gtt_offset & (size - 1)), | |
2596 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2597 | obj->gtt_offset, size); | |
e76a16de | 2598 | |
9ce079e4 CW |
2599 | pitch_val = obj->stride / 128; |
2600 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2601 | |
9ce079e4 CW |
2602 | val = obj->gtt_offset; |
2603 | if (obj->tiling_mode == I915_TILING_Y) | |
2604 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2605 | val |= I830_FENCE_SIZE_BITS(size); | |
2606 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2607 | val |= I830_FENCE_REG_VALID; | |
2608 | } else | |
2609 | val = 0; | |
c6642782 | 2610 | |
9ce079e4 CW |
2611 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2612 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2613 | } | |
2614 | ||
2615 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2616 | struct drm_i915_gem_object *obj) | |
2617 | { | |
2618 | switch (INTEL_INFO(dev)->gen) { | |
2619 | case 7: | |
2620 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2621 | case 5: | |
2622 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2623 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2624 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2625 | default: break; | |
2626 | } | |
de151cf6 JB |
2627 | } |
2628 | ||
61050808 CW |
2629 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2630 | struct drm_i915_fence_reg *fence) | |
2631 | { | |
2632 | return fence - dev_priv->fence_regs; | |
2633 | } | |
2634 | ||
2635 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2636 | struct drm_i915_fence_reg *fence, | |
2637 | bool enable) | |
2638 | { | |
2639 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2640 | int reg = fence_number(dev_priv, fence); | |
2641 | ||
2642 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2643 | ||
2644 | if (enable) { | |
2645 | obj->fence_reg = reg; | |
2646 | fence->obj = obj; | |
2647 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2648 | } else { | |
2649 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2650 | fence->obj = NULL; | |
2651 | list_del_init(&fence->lru_list); | |
2652 | } | |
2653 | } | |
2654 | ||
d9e86c0e | 2655 | static int |
a360bb1a | 2656 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2657 | { |
1c293ea3 | 2658 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2659 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2660 | if (ret) |
2661 | return ret; | |
d9e86c0e CW |
2662 | |
2663 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2664 | } |
2665 | ||
63256ec5 CW |
2666 | /* Ensure that all CPU reads are completed before installing a fence |
2667 | * and all writes before removing the fence. | |
2668 | */ | |
2669 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2670 | mb(); | |
2671 | ||
86d5bc37 | 2672 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2673 | return 0; |
2674 | } | |
2675 | ||
2676 | int | |
2677 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2678 | { | |
61050808 | 2679 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2680 | int ret; |
2681 | ||
a360bb1a | 2682 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2683 | if (ret) |
2684 | return ret; | |
2685 | ||
61050808 CW |
2686 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2687 | return 0; | |
d9e86c0e | 2688 | |
61050808 CW |
2689 | i915_gem_object_update_fence(obj, |
2690 | &dev_priv->fence_regs[obj->fence_reg], | |
2691 | false); | |
2692 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2693 | |
2694 | return 0; | |
2695 | } | |
2696 | ||
2697 | static struct drm_i915_fence_reg * | |
a360bb1a | 2698 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2699 | { |
ae3db24a | 2700 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2701 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2702 | int i; |
ae3db24a DV |
2703 | |
2704 | /* First try to find a free reg */ | |
d9e86c0e | 2705 | avail = NULL; |
ae3db24a DV |
2706 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2707 | reg = &dev_priv->fence_regs[i]; | |
2708 | if (!reg->obj) | |
d9e86c0e | 2709 | return reg; |
ae3db24a | 2710 | |
1690e1eb | 2711 | if (!reg->pin_count) |
d9e86c0e | 2712 | avail = reg; |
ae3db24a DV |
2713 | } |
2714 | ||
d9e86c0e CW |
2715 | if (avail == NULL) |
2716 | return NULL; | |
ae3db24a DV |
2717 | |
2718 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2719 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2720 | if (reg->pin_count) |
ae3db24a DV |
2721 | continue; |
2722 | ||
8fe301ad | 2723 | return reg; |
ae3db24a DV |
2724 | } |
2725 | ||
8fe301ad | 2726 | return NULL; |
ae3db24a DV |
2727 | } |
2728 | ||
de151cf6 | 2729 | /** |
9a5a53b3 | 2730 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2731 | * @obj: object to map through a fence reg |
2732 | * | |
2733 | * When mapping objects through the GTT, userspace wants to be able to write | |
2734 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2735 | * This function walks the fence regs looking for a free one for @obj, |
2736 | * stealing one if it can't find any. | |
2737 | * | |
2738 | * It then sets up the reg based on the object's properties: address, pitch | |
2739 | * and tiling format. | |
9a5a53b3 CW |
2740 | * |
2741 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2742 | */ |
8c4b8c3f | 2743 | int |
06d98131 | 2744 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2745 | { |
05394f39 | 2746 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2747 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2748 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2749 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2750 | int ret; |
de151cf6 | 2751 | |
14415745 CW |
2752 | /* Have we updated the tiling parameters upon the object and so |
2753 | * will need to serialise the write to the associated fence register? | |
2754 | */ | |
5d82e3e6 | 2755 | if (obj->fence_dirty) { |
14415745 CW |
2756 | ret = i915_gem_object_flush_fence(obj); |
2757 | if (ret) | |
2758 | return ret; | |
2759 | } | |
9a5a53b3 | 2760 | |
d9e86c0e | 2761 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2762 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2763 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2764 | if (!obj->fence_dirty) { |
14415745 CW |
2765 | list_move_tail(®->lru_list, |
2766 | &dev_priv->mm.fence_list); | |
2767 | return 0; | |
2768 | } | |
2769 | } else if (enable) { | |
2770 | reg = i915_find_fence_reg(dev); | |
2771 | if (reg == NULL) | |
2772 | return -EDEADLK; | |
d9e86c0e | 2773 | |
14415745 CW |
2774 | if (reg->obj) { |
2775 | struct drm_i915_gem_object *old = reg->obj; | |
2776 | ||
2777 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2778 | if (ret) |
2779 | return ret; | |
2780 | ||
14415745 | 2781 | i915_gem_object_fence_lost(old); |
29c5a587 | 2782 | } |
14415745 | 2783 | } else |
a09ba7fa | 2784 | return 0; |
a09ba7fa | 2785 | |
14415745 | 2786 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2787 | obj->fence_dirty = false; |
14415745 | 2788 | |
9ce079e4 | 2789 | return 0; |
de151cf6 JB |
2790 | } |
2791 | ||
42d6ab48 CW |
2792 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2793 | struct drm_mm_node *gtt_space, | |
2794 | unsigned long cache_level) | |
2795 | { | |
2796 | struct drm_mm_node *other; | |
2797 | ||
2798 | /* On non-LLC machines we have to be careful when putting differing | |
2799 | * types of snoopable memory together to avoid the prefetcher | |
2800 | * crossing memory domains and dieing. | |
2801 | */ | |
2802 | if (HAS_LLC(dev)) | |
2803 | return true; | |
2804 | ||
2805 | if (gtt_space == NULL) | |
2806 | return true; | |
2807 | ||
2808 | if (list_empty(>t_space->node_list)) | |
2809 | return true; | |
2810 | ||
2811 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2812 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2813 | return false; | |
2814 | ||
2815 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2816 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2817 | return false; | |
2818 | ||
2819 | return true; | |
2820 | } | |
2821 | ||
2822 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2823 | { | |
2824 | #if WATCH_GTT | |
2825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2826 | struct drm_i915_gem_object *obj; | |
2827 | int err = 0; | |
2828 | ||
2829 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2830 | if (obj->gtt_space == NULL) { | |
2831 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2832 | err++; | |
2833 | continue; | |
2834 | } | |
2835 | ||
2836 | if (obj->cache_level != obj->gtt_space->color) { | |
2837 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2838 | obj->gtt_space->start, | |
2839 | obj->gtt_space->start + obj->gtt_space->size, | |
2840 | obj->cache_level, | |
2841 | obj->gtt_space->color); | |
2842 | err++; | |
2843 | continue; | |
2844 | } | |
2845 | ||
2846 | if (!i915_gem_valid_gtt_space(dev, | |
2847 | obj->gtt_space, | |
2848 | obj->cache_level)) { | |
2849 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2850 | obj->gtt_space->start, | |
2851 | obj->gtt_space->start + obj->gtt_space->size, | |
2852 | obj->cache_level); | |
2853 | err++; | |
2854 | continue; | |
2855 | } | |
2856 | } | |
2857 | ||
2858 | WARN_ON(err); | |
2859 | #endif | |
2860 | } | |
2861 | ||
673a394b EA |
2862 | /** |
2863 | * Finds free space in the GTT aperture and binds the object there. | |
2864 | */ | |
2865 | static int | |
05394f39 | 2866 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2867 | unsigned alignment, |
86a1ee26 CW |
2868 | bool map_and_fenceable, |
2869 | bool nonblocking) | |
673a394b | 2870 | { |
05394f39 | 2871 | struct drm_device *dev = obj->base.dev; |
673a394b | 2872 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2873 | struct drm_mm_node *free_space; |
5e783301 | 2874 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2875 | bool mappable, fenceable; |
07f73f69 | 2876 | int ret; |
673a394b | 2877 | |
05394f39 | 2878 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2879 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2880 | return -EINVAL; | |
2881 | } | |
2882 | ||
e28f8711 CW |
2883 | fence_size = i915_gem_get_gtt_size(dev, |
2884 | obj->base.size, | |
2885 | obj->tiling_mode); | |
2886 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2887 | obj->base.size, | |
2888 | obj->tiling_mode); | |
2889 | unfenced_alignment = | |
2890 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2891 | obj->base.size, | |
2892 | obj->tiling_mode); | |
a00b10c3 | 2893 | |
673a394b | 2894 | if (alignment == 0) |
5e783301 DV |
2895 | alignment = map_and_fenceable ? fence_alignment : |
2896 | unfenced_alignment; | |
75e9e915 | 2897 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2898 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2899 | return -EINVAL; | |
2900 | } | |
2901 | ||
05394f39 | 2902 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2903 | |
654fc607 CW |
2904 | /* If the object is bigger than the entire aperture, reject it early |
2905 | * before evicting everything in a vain attempt to find space. | |
2906 | */ | |
05394f39 | 2907 | if (obj->base.size > |
75e9e915 | 2908 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2909 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2910 | return -E2BIG; | |
2911 | } | |
2912 | ||
37e680a1 | 2913 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2914 | if (ret) |
2915 | return ret; | |
2916 | ||
673a394b | 2917 | search_free: |
75e9e915 | 2918 | if (map_and_fenceable) |
920afa77 | 2919 | free_space = |
42d6ab48 CW |
2920 | drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space, |
2921 | size, alignment, obj->cache_level, | |
2922 | 0, dev_priv->mm.gtt_mappable_end, | |
2923 | false); | |
920afa77 | 2924 | else |
42d6ab48 CW |
2925 | free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space, |
2926 | size, alignment, obj->cache_level, | |
2927 | false); | |
920afa77 DV |
2928 | |
2929 | if (free_space != NULL) { | |
75e9e915 | 2930 | if (map_and_fenceable) |
05394f39 | 2931 | obj->gtt_space = |
920afa77 | 2932 | drm_mm_get_block_range_generic(free_space, |
42d6ab48 | 2933 | size, alignment, obj->cache_level, |
6b9d89b4 | 2934 | 0, dev_priv->mm.gtt_mappable_end, |
42d6ab48 | 2935 | false); |
920afa77 | 2936 | else |
05394f39 | 2937 | obj->gtt_space = |
42d6ab48 CW |
2938 | drm_mm_get_block_generic(free_space, |
2939 | size, alignment, obj->cache_level, | |
2940 | false); | |
920afa77 | 2941 | } |
05394f39 | 2942 | if (obj->gtt_space == NULL) { |
75e9e915 | 2943 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2944 | obj->cache_level, |
86a1ee26 CW |
2945 | map_and_fenceable, |
2946 | nonblocking); | |
9731129c | 2947 | if (ret) |
673a394b | 2948 | return ret; |
9731129c | 2949 | |
673a394b EA |
2950 | goto search_free; |
2951 | } | |
42d6ab48 CW |
2952 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, |
2953 | obj->gtt_space, | |
2954 | obj->cache_level))) { | |
2955 | drm_mm_put_block(obj->gtt_space); | |
2956 | obj->gtt_space = NULL; | |
2957 | return -EINVAL; | |
2958 | } | |
673a394b | 2959 | |
673a394b | 2960 | |
74163907 | 2961 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2962 | if (ret) { |
05394f39 CW |
2963 | drm_mm_put_block(obj->gtt_space); |
2964 | obj->gtt_space = NULL; | |
6c085a72 | 2965 | return ret; |
673a394b | 2966 | } |
673a394b | 2967 | |
0ebb9829 DV |
2968 | if (!dev_priv->mm.aliasing_ppgtt) |
2969 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2970 | |
6c085a72 | 2971 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2972 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2973 | |
6299f992 | 2974 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2975 | |
75e9e915 | 2976 | fenceable = |
05394f39 | 2977 | obj->gtt_space->size == fence_size && |
0206e353 | 2978 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2979 | |
75e9e915 | 2980 | mappable = |
05394f39 | 2981 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2982 | |
05394f39 | 2983 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2984 | |
db53a302 | 2985 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 2986 | i915_gem_verify_gtt(dev); |
673a394b EA |
2987 | return 0; |
2988 | } | |
2989 | ||
2990 | void | |
05394f39 | 2991 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2992 | { |
673a394b EA |
2993 | /* If we don't have a page list set up, then we're not pinned |
2994 | * to GPU, and we can ignore the cache flush because it'll happen | |
2995 | * again at bind time. | |
2996 | */ | |
05394f39 | 2997 | if (obj->pages == NULL) |
673a394b EA |
2998 | return; |
2999 | ||
9c23f7fc CW |
3000 | /* If the GPU is snooping the contents of the CPU cache, |
3001 | * we do not need to manually clear the CPU cache lines. However, | |
3002 | * the caches are only snooped when the render cache is | |
3003 | * flushed/invalidated. As we always have to emit invalidations | |
3004 | * and flushes when moving into and out of the RENDER domain, correct | |
3005 | * snooping behaviour occurs naturally as the result of our domain | |
3006 | * tracking. | |
3007 | */ | |
3008 | if (obj->cache_level != I915_CACHE_NONE) | |
3009 | return; | |
3010 | ||
1c5d22f7 | 3011 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3012 | |
9da3da66 | 3013 | drm_clflush_sg(obj->pages); |
673a394b EA |
3014 | } |
3015 | ||
e47c68e9 EA |
3016 | /** Flushes the GTT write domain for the object if it's dirty. */ |
3017 | static void | |
05394f39 | 3018 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3019 | { |
1c5d22f7 CW |
3020 | uint32_t old_write_domain; |
3021 | ||
05394f39 | 3022 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3023 | return; |
3024 | ||
63256ec5 | 3025 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3026 | * to it immediately go to main memory as far as we know, so there's |
3027 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3028 | * |
3029 | * However, we do have to enforce the order so that all writes through | |
3030 | * the GTT land before any writes to the device, such as updates to | |
3031 | * the GATT itself. | |
e47c68e9 | 3032 | */ |
63256ec5 CW |
3033 | wmb(); |
3034 | ||
05394f39 CW |
3035 | old_write_domain = obj->base.write_domain; |
3036 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3037 | |
3038 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3039 | obj->base.read_domains, |
1c5d22f7 | 3040 | old_write_domain); |
e47c68e9 EA |
3041 | } |
3042 | ||
3043 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3044 | static void | |
05394f39 | 3045 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3046 | { |
1c5d22f7 | 3047 | uint32_t old_write_domain; |
e47c68e9 | 3048 | |
05394f39 | 3049 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3050 | return; |
3051 | ||
3052 | i915_gem_clflush_object(obj); | |
40ce6575 | 3053 | intel_gtt_chipset_flush(); |
05394f39 CW |
3054 | old_write_domain = obj->base.write_domain; |
3055 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3056 | |
3057 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3058 | obj->base.read_domains, |
1c5d22f7 | 3059 | old_write_domain); |
e47c68e9 EA |
3060 | } |
3061 | ||
2ef7eeaa EA |
3062 | /** |
3063 | * Moves a single object to the GTT read, and possibly write domain. | |
3064 | * | |
3065 | * This function returns when the move is complete, including waiting on | |
3066 | * flushes to occur. | |
3067 | */ | |
79e53945 | 3068 | int |
2021746e | 3069 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3070 | { |
8325a09d | 3071 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3072 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3073 | int ret; |
2ef7eeaa | 3074 | |
02354392 | 3075 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3076 | if (obj->gtt_space == NULL) |
02354392 EA |
3077 | return -EINVAL; |
3078 | ||
8d7e3de1 CW |
3079 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3080 | return 0; | |
3081 | ||
0201f1ec CW |
3082 | ret = i915_gem_object_wait_rendering(obj, !write); |
3083 | if (ret) | |
3084 | return ret; | |
2dafb1e0 | 3085 | |
7213342d | 3086 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3087 | |
05394f39 CW |
3088 | old_write_domain = obj->base.write_domain; |
3089 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3090 | |
e47c68e9 EA |
3091 | /* It should now be out of any other write domains, and we can update |
3092 | * the domain values for our changes. | |
3093 | */ | |
05394f39 CW |
3094 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3095 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3096 | if (write) { |
05394f39 CW |
3097 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3098 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3099 | obj->dirty = 1; | |
2ef7eeaa EA |
3100 | } |
3101 | ||
1c5d22f7 CW |
3102 | trace_i915_gem_object_change_domain(obj, |
3103 | old_read_domains, | |
3104 | old_write_domain); | |
3105 | ||
8325a09d CW |
3106 | /* And bump the LRU for this access */ |
3107 | if (i915_gem_object_is_inactive(obj)) | |
3108 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3109 | ||
e47c68e9 EA |
3110 | return 0; |
3111 | } | |
3112 | ||
e4ffd173 CW |
3113 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3114 | enum i915_cache_level cache_level) | |
3115 | { | |
7bddb01f DV |
3116 | struct drm_device *dev = obj->base.dev; |
3117 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3118 | int ret; |
3119 | ||
3120 | if (obj->cache_level == cache_level) | |
3121 | return 0; | |
3122 | ||
3123 | if (obj->pin_count) { | |
3124 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3125 | return -EBUSY; | |
3126 | } | |
3127 | ||
42d6ab48 CW |
3128 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3129 | ret = i915_gem_object_unbind(obj); | |
3130 | if (ret) | |
3131 | return ret; | |
3132 | } | |
3133 | ||
e4ffd173 CW |
3134 | if (obj->gtt_space) { |
3135 | ret = i915_gem_object_finish_gpu(obj); | |
3136 | if (ret) | |
3137 | return ret; | |
3138 | ||
3139 | i915_gem_object_finish_gtt(obj); | |
3140 | ||
3141 | /* Before SandyBridge, you could not use tiling or fence | |
3142 | * registers with snooped memory, so relinquish any fences | |
3143 | * currently pointing to our region in the aperture. | |
3144 | */ | |
42d6ab48 | 3145 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3146 | ret = i915_gem_object_put_fence(obj); |
3147 | if (ret) | |
3148 | return ret; | |
3149 | } | |
3150 | ||
74898d7e DV |
3151 | if (obj->has_global_gtt_mapping) |
3152 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3153 | if (obj->has_aliasing_ppgtt_mapping) |
3154 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3155 | obj, cache_level); | |
42d6ab48 CW |
3156 | |
3157 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3158 | } |
3159 | ||
3160 | if (cache_level == I915_CACHE_NONE) { | |
3161 | u32 old_read_domains, old_write_domain; | |
3162 | ||
3163 | /* If we're coming from LLC cached, then we haven't | |
3164 | * actually been tracking whether the data is in the | |
3165 | * CPU cache or not, since we only allow one bit set | |
3166 | * in obj->write_domain and have been skipping the clflushes. | |
3167 | * Just set it to the CPU cache for now. | |
3168 | */ | |
3169 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3170 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3171 | ||
3172 | old_read_domains = obj->base.read_domains; | |
3173 | old_write_domain = obj->base.write_domain; | |
3174 | ||
3175 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3176 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3177 | ||
3178 | trace_i915_gem_object_change_domain(obj, | |
3179 | old_read_domains, | |
3180 | old_write_domain); | |
3181 | } | |
3182 | ||
3183 | obj->cache_level = cache_level; | |
42d6ab48 | 3184 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3185 | return 0; |
3186 | } | |
3187 | ||
199adf40 BW |
3188 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3189 | struct drm_file *file) | |
e6994aee | 3190 | { |
199adf40 | 3191 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3192 | struct drm_i915_gem_object *obj; |
3193 | int ret; | |
3194 | ||
3195 | ret = i915_mutex_lock_interruptible(dev); | |
3196 | if (ret) | |
3197 | return ret; | |
3198 | ||
3199 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3200 | if (&obj->base == NULL) { | |
3201 | ret = -ENOENT; | |
3202 | goto unlock; | |
3203 | } | |
3204 | ||
199adf40 | 3205 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3206 | |
3207 | drm_gem_object_unreference(&obj->base); | |
3208 | unlock: | |
3209 | mutex_unlock(&dev->struct_mutex); | |
3210 | return ret; | |
3211 | } | |
3212 | ||
199adf40 BW |
3213 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3214 | struct drm_file *file) | |
e6994aee | 3215 | { |
199adf40 | 3216 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3217 | struct drm_i915_gem_object *obj; |
3218 | enum i915_cache_level level; | |
3219 | int ret; | |
3220 | ||
3221 | ret = i915_mutex_lock_interruptible(dev); | |
3222 | if (ret) | |
3223 | return ret; | |
3224 | ||
199adf40 BW |
3225 | switch (args->caching) { |
3226 | case I915_CACHING_NONE: | |
e6994aee CW |
3227 | level = I915_CACHE_NONE; |
3228 | break; | |
199adf40 | 3229 | case I915_CACHING_CACHED: |
e6994aee CW |
3230 | level = I915_CACHE_LLC; |
3231 | break; | |
3232 | default: | |
3233 | return -EINVAL; | |
3234 | } | |
3235 | ||
3236 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3237 | if (&obj->base == NULL) { | |
3238 | ret = -ENOENT; | |
3239 | goto unlock; | |
3240 | } | |
3241 | ||
3242 | ret = i915_gem_object_set_cache_level(obj, level); | |
3243 | ||
3244 | drm_gem_object_unreference(&obj->base); | |
3245 | unlock: | |
3246 | mutex_unlock(&dev->struct_mutex); | |
3247 | return ret; | |
3248 | } | |
3249 | ||
b9241ea3 | 3250 | /* |
2da3b9b9 CW |
3251 | * Prepare buffer for display plane (scanout, cursors, etc). |
3252 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3253 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3254 | */ |
3255 | int | |
2da3b9b9 CW |
3256 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3257 | u32 alignment, | |
919926ae | 3258 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3259 | { |
2da3b9b9 | 3260 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3261 | int ret; |
3262 | ||
0be73284 | 3263 | if (pipelined != obj->ring) { |
2911a35b BW |
3264 | ret = i915_gem_object_sync(obj, pipelined); |
3265 | if (ret) | |
b9241ea3 ZW |
3266 | return ret; |
3267 | } | |
3268 | ||
a7ef0640 EA |
3269 | /* The display engine is not coherent with the LLC cache on gen6. As |
3270 | * a result, we make sure that the pinning that is about to occur is | |
3271 | * done with uncached PTEs. This is lowest common denominator for all | |
3272 | * chipsets. | |
3273 | * | |
3274 | * However for gen6+, we could do better by using the GFDT bit instead | |
3275 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3276 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3277 | */ | |
3278 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3279 | if (ret) | |
3280 | return ret; | |
3281 | ||
2da3b9b9 CW |
3282 | /* As the user may map the buffer once pinned in the display plane |
3283 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3284 | * always use map_and_fenceable for all scanout buffers. | |
3285 | */ | |
86a1ee26 | 3286 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3287 | if (ret) |
3288 | return ret; | |
3289 | ||
b118c1e3 CW |
3290 | i915_gem_object_flush_cpu_write_domain(obj); |
3291 | ||
2da3b9b9 | 3292 | old_write_domain = obj->base.write_domain; |
05394f39 | 3293 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3294 | |
3295 | /* It should now be out of any other write domains, and we can update | |
3296 | * the domain values for our changes. | |
3297 | */ | |
e5f1d962 | 3298 | obj->base.write_domain = 0; |
05394f39 | 3299 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3300 | |
3301 | trace_i915_gem_object_change_domain(obj, | |
3302 | old_read_domains, | |
2da3b9b9 | 3303 | old_write_domain); |
b9241ea3 ZW |
3304 | |
3305 | return 0; | |
3306 | } | |
3307 | ||
85345517 | 3308 | int |
a8198eea | 3309 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3310 | { |
88241785 CW |
3311 | int ret; |
3312 | ||
a8198eea | 3313 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3314 | return 0; |
3315 | ||
0201f1ec | 3316 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3317 | if (ret) |
3318 | return ret; | |
3319 | ||
a8198eea CW |
3320 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3321 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3322 | return 0; |
85345517 CW |
3323 | } |
3324 | ||
e47c68e9 EA |
3325 | /** |
3326 | * Moves a single object to the CPU read, and possibly write domain. | |
3327 | * | |
3328 | * This function returns when the move is complete, including waiting on | |
3329 | * flushes to occur. | |
3330 | */ | |
dabdfe02 | 3331 | int |
919926ae | 3332 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3333 | { |
1c5d22f7 | 3334 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3335 | int ret; |
3336 | ||
8d7e3de1 CW |
3337 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3338 | return 0; | |
3339 | ||
0201f1ec CW |
3340 | ret = i915_gem_object_wait_rendering(obj, !write); |
3341 | if (ret) | |
3342 | return ret; | |
2ef7eeaa | 3343 | |
e47c68e9 | 3344 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3345 | |
05394f39 CW |
3346 | old_write_domain = obj->base.write_domain; |
3347 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3348 | |
e47c68e9 | 3349 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3350 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3351 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3352 | |
05394f39 | 3353 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3354 | } |
3355 | ||
3356 | /* It should now be out of any other write domains, and we can update | |
3357 | * the domain values for our changes. | |
3358 | */ | |
05394f39 | 3359 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3360 | |
3361 | /* If we're writing through the CPU, then the GPU read domains will | |
3362 | * need to be invalidated at next use. | |
3363 | */ | |
3364 | if (write) { | |
05394f39 CW |
3365 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3366 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3367 | } |
2ef7eeaa | 3368 | |
1c5d22f7 CW |
3369 | trace_i915_gem_object_change_domain(obj, |
3370 | old_read_domains, | |
3371 | old_write_domain); | |
3372 | ||
2ef7eeaa EA |
3373 | return 0; |
3374 | } | |
3375 | ||
673a394b EA |
3376 | /* Throttle our rendering by waiting until the ring has completed our requests |
3377 | * emitted over 20 msec ago. | |
3378 | * | |
b962442e EA |
3379 | * Note that if we were to use the current jiffies each time around the loop, |
3380 | * we wouldn't escape the function with any frames outstanding if the time to | |
3381 | * render a frame was over 20ms. | |
3382 | * | |
673a394b EA |
3383 | * This should get us reasonable parallelism between CPU and GPU but also |
3384 | * relatively low latency when blocking on a particular request to finish. | |
3385 | */ | |
40a5f0de | 3386 | static int |
f787a5f5 | 3387 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3388 | { |
f787a5f5 CW |
3389 | struct drm_i915_private *dev_priv = dev->dev_private; |
3390 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3391 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3392 | struct drm_i915_gem_request *request; |
3393 | struct intel_ring_buffer *ring = NULL; | |
3394 | u32 seqno = 0; | |
3395 | int ret; | |
93533c29 | 3396 | |
e110e8d6 CW |
3397 | if (atomic_read(&dev_priv->mm.wedged)) |
3398 | return -EIO; | |
3399 | ||
1c25595f | 3400 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3401 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3402 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3403 | break; | |
40a5f0de | 3404 | |
f787a5f5 CW |
3405 | ring = request->ring; |
3406 | seqno = request->seqno; | |
b962442e | 3407 | } |
1c25595f | 3408 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3409 | |
f787a5f5 CW |
3410 | if (seqno == 0) |
3411 | return 0; | |
2bc43b5c | 3412 | |
5c81fe85 | 3413 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3414 | if (ret == 0) |
3415 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3416 | |
3417 | return ret; | |
3418 | } | |
3419 | ||
673a394b | 3420 | int |
05394f39 CW |
3421 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3422 | uint32_t alignment, | |
86a1ee26 CW |
3423 | bool map_and_fenceable, |
3424 | bool nonblocking) | |
673a394b | 3425 | { |
673a394b EA |
3426 | int ret; |
3427 | ||
7e81a42e CW |
3428 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3429 | return -EBUSY; | |
ac0c6b5a | 3430 | |
05394f39 CW |
3431 | if (obj->gtt_space != NULL) { |
3432 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3433 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3434 | WARN(obj->pin_count, | |
ae7d49d8 | 3435 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3436 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3437 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3438 | obj->gtt_offset, alignment, |
75e9e915 | 3439 | map_and_fenceable, |
05394f39 | 3440 | obj->map_and_fenceable); |
ac0c6b5a CW |
3441 | ret = i915_gem_object_unbind(obj); |
3442 | if (ret) | |
3443 | return ret; | |
3444 | } | |
3445 | } | |
3446 | ||
05394f39 | 3447 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3448 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3449 | map_and_fenceable, |
3450 | nonblocking); | |
9731129c | 3451 | if (ret) |
673a394b | 3452 | return ret; |
22c344e9 | 3453 | } |
76446cac | 3454 | |
74898d7e DV |
3455 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3456 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3457 | ||
1b50247a | 3458 | obj->pin_count++; |
6299f992 | 3459 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3460 | |
3461 | return 0; | |
3462 | } | |
3463 | ||
3464 | void | |
05394f39 | 3465 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3466 | { |
05394f39 CW |
3467 | BUG_ON(obj->pin_count == 0); |
3468 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3469 | |
1b50247a | 3470 | if (--obj->pin_count == 0) |
6299f992 | 3471 | obj->pin_mappable = false; |
673a394b EA |
3472 | } |
3473 | ||
3474 | int | |
3475 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3476 | struct drm_file *file) |
673a394b EA |
3477 | { |
3478 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3479 | struct drm_i915_gem_object *obj; |
673a394b EA |
3480 | int ret; |
3481 | ||
1d7cfea1 CW |
3482 | ret = i915_mutex_lock_interruptible(dev); |
3483 | if (ret) | |
3484 | return ret; | |
673a394b | 3485 | |
05394f39 | 3486 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3487 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3488 | ret = -ENOENT; |
3489 | goto unlock; | |
673a394b | 3490 | } |
673a394b | 3491 | |
05394f39 | 3492 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3493 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3494 | ret = -EINVAL; |
3495 | goto out; | |
3ef94daa CW |
3496 | } |
3497 | ||
05394f39 | 3498 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3499 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3500 | args->handle); | |
1d7cfea1 CW |
3501 | ret = -EINVAL; |
3502 | goto out; | |
79e53945 JB |
3503 | } |
3504 | ||
05394f39 CW |
3505 | obj->user_pin_count++; |
3506 | obj->pin_filp = file; | |
3507 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3508 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3509 | if (ret) |
3510 | goto out; | |
673a394b EA |
3511 | } |
3512 | ||
3513 | /* XXX - flush the CPU caches for pinned objects | |
3514 | * as the X server doesn't manage domains yet | |
3515 | */ | |
e47c68e9 | 3516 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3517 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3518 | out: |
05394f39 | 3519 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3520 | unlock: |
673a394b | 3521 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3522 | return ret; |
673a394b EA |
3523 | } |
3524 | ||
3525 | int | |
3526 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3527 | struct drm_file *file) |
673a394b EA |
3528 | { |
3529 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3530 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3531 | int ret; |
673a394b | 3532 | |
1d7cfea1 CW |
3533 | ret = i915_mutex_lock_interruptible(dev); |
3534 | if (ret) | |
3535 | return ret; | |
673a394b | 3536 | |
05394f39 | 3537 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3538 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3539 | ret = -ENOENT; |
3540 | goto unlock; | |
673a394b | 3541 | } |
76c1dec1 | 3542 | |
05394f39 | 3543 | if (obj->pin_filp != file) { |
79e53945 JB |
3544 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3545 | args->handle); | |
1d7cfea1 CW |
3546 | ret = -EINVAL; |
3547 | goto out; | |
79e53945 | 3548 | } |
05394f39 CW |
3549 | obj->user_pin_count--; |
3550 | if (obj->user_pin_count == 0) { | |
3551 | obj->pin_filp = NULL; | |
79e53945 JB |
3552 | i915_gem_object_unpin(obj); |
3553 | } | |
673a394b | 3554 | |
1d7cfea1 | 3555 | out: |
05394f39 | 3556 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3557 | unlock: |
673a394b | 3558 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3559 | return ret; |
673a394b EA |
3560 | } |
3561 | ||
3562 | int | |
3563 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3564 | struct drm_file *file) |
673a394b EA |
3565 | { |
3566 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3567 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3568 | int ret; |
3569 | ||
76c1dec1 | 3570 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3571 | if (ret) |
76c1dec1 | 3572 | return ret; |
673a394b | 3573 | |
05394f39 | 3574 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3575 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3576 | ret = -ENOENT; |
3577 | goto unlock; | |
673a394b | 3578 | } |
d1b851fc | 3579 | |
0be555b6 CW |
3580 | /* Count all active objects as busy, even if they are currently not used |
3581 | * by the gpu. Users of this interface expect objects to eventually | |
3582 | * become non-busy without any further actions, therefore emit any | |
3583 | * necessary flushes here. | |
c4de0a5d | 3584 | */ |
30dfebf3 | 3585 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3586 | |
30dfebf3 | 3587 | args->busy = obj->active; |
e9808edd CW |
3588 | if (obj->ring) { |
3589 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3590 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3591 | } | |
673a394b | 3592 | |
05394f39 | 3593 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3594 | unlock: |
673a394b | 3595 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3596 | return ret; |
673a394b EA |
3597 | } |
3598 | ||
3599 | int | |
3600 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3601 | struct drm_file *file_priv) | |
3602 | { | |
0206e353 | 3603 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3604 | } |
3605 | ||
3ef94daa CW |
3606 | int |
3607 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3608 | struct drm_file *file_priv) | |
3609 | { | |
3610 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3611 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3612 | int ret; |
3ef94daa CW |
3613 | |
3614 | switch (args->madv) { | |
3615 | case I915_MADV_DONTNEED: | |
3616 | case I915_MADV_WILLNEED: | |
3617 | break; | |
3618 | default: | |
3619 | return -EINVAL; | |
3620 | } | |
3621 | ||
1d7cfea1 CW |
3622 | ret = i915_mutex_lock_interruptible(dev); |
3623 | if (ret) | |
3624 | return ret; | |
3625 | ||
05394f39 | 3626 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3627 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3628 | ret = -ENOENT; |
3629 | goto unlock; | |
3ef94daa | 3630 | } |
3ef94daa | 3631 | |
05394f39 | 3632 | if (obj->pin_count) { |
1d7cfea1 CW |
3633 | ret = -EINVAL; |
3634 | goto out; | |
3ef94daa CW |
3635 | } |
3636 | ||
05394f39 CW |
3637 | if (obj->madv != __I915_MADV_PURGED) |
3638 | obj->madv = args->madv; | |
3ef94daa | 3639 | |
6c085a72 CW |
3640 | /* if the object is no longer attached, discard its backing storage */ |
3641 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3642 | i915_gem_object_truncate(obj); |
3643 | ||
05394f39 | 3644 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3645 | |
1d7cfea1 | 3646 | out: |
05394f39 | 3647 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3648 | unlock: |
3ef94daa | 3649 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3650 | return ret; |
3ef94daa CW |
3651 | } |
3652 | ||
37e680a1 CW |
3653 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3654 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3655 | { |
0327d6ba CW |
3656 | INIT_LIST_HEAD(&obj->mm_list); |
3657 | INIT_LIST_HEAD(&obj->gtt_list); | |
3658 | INIT_LIST_HEAD(&obj->ring_list); | |
3659 | INIT_LIST_HEAD(&obj->exec_list); | |
3660 | ||
37e680a1 CW |
3661 | obj->ops = ops; |
3662 | ||
0327d6ba CW |
3663 | obj->fence_reg = I915_FENCE_REG_NONE; |
3664 | obj->madv = I915_MADV_WILLNEED; | |
3665 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3666 | obj->map_and_fenceable = true; | |
3667 | ||
3668 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3669 | } | |
3670 | ||
37e680a1 CW |
3671 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3672 | .get_pages = i915_gem_object_get_pages_gtt, | |
3673 | .put_pages = i915_gem_object_put_pages_gtt, | |
3674 | }; | |
3675 | ||
05394f39 CW |
3676 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3677 | size_t size) | |
ac52bc56 | 3678 | { |
c397b908 | 3679 | struct drm_i915_gem_object *obj; |
5949eac4 | 3680 | struct address_space *mapping; |
bed1ea95 | 3681 | u32 mask; |
ac52bc56 | 3682 | |
c397b908 DV |
3683 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3684 | if (obj == NULL) | |
3685 | return NULL; | |
673a394b | 3686 | |
c397b908 DV |
3687 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3688 | kfree(obj); | |
3689 | return NULL; | |
3690 | } | |
673a394b | 3691 | |
bed1ea95 CW |
3692 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3693 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3694 | /* 965gm cannot relocate objects above 4GiB. */ | |
3695 | mask &= ~__GFP_HIGHMEM; | |
3696 | mask |= __GFP_DMA32; | |
3697 | } | |
3698 | ||
5949eac4 | 3699 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3700 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3701 | |
37e680a1 | 3702 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3703 | |
c397b908 DV |
3704 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3705 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3706 | |
3d29b842 ED |
3707 | if (HAS_LLC(dev)) { |
3708 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3709 | * cache) for about a 10% performance improvement |
3710 | * compared to uncached. Graphics requests other than | |
3711 | * display scanout are coherent with the CPU in | |
3712 | * accessing this cache. This means in this mode we | |
3713 | * don't need to clflush on the CPU side, and on the | |
3714 | * GPU side we only need to flush internal caches to | |
3715 | * get data visible to the CPU. | |
3716 | * | |
3717 | * However, we maintain the display planes as UC, and so | |
3718 | * need to rebind when first used as such. | |
3719 | */ | |
3720 | obj->cache_level = I915_CACHE_LLC; | |
3721 | } else | |
3722 | obj->cache_level = I915_CACHE_NONE; | |
3723 | ||
05394f39 | 3724 | return obj; |
c397b908 DV |
3725 | } |
3726 | ||
3727 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3728 | { | |
3729 | BUG(); | |
de151cf6 | 3730 | |
673a394b EA |
3731 | return 0; |
3732 | } | |
3733 | ||
1488fc08 | 3734 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3735 | { |
1488fc08 | 3736 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3737 | struct drm_device *dev = obj->base.dev; |
be72615b | 3738 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3739 | |
26e12f89 CW |
3740 | trace_i915_gem_object_destroy(obj); |
3741 | ||
1488fc08 CW |
3742 | if (obj->phys_obj) |
3743 | i915_gem_detach_phys_object(dev, obj); | |
3744 | ||
3745 | obj->pin_count = 0; | |
3746 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3747 | bool was_interruptible; | |
3748 | ||
3749 | was_interruptible = dev_priv->mm.interruptible; | |
3750 | dev_priv->mm.interruptible = false; | |
3751 | ||
3752 | WARN_ON(i915_gem_object_unbind(obj)); | |
3753 | ||
3754 | dev_priv->mm.interruptible = was_interruptible; | |
3755 | } | |
3756 | ||
a5570178 | 3757 | obj->pages_pin_count = 0; |
37e680a1 | 3758 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3759 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 3760 | |
9da3da66 CW |
3761 | BUG_ON(obj->pages); |
3762 | ||
2f745ad3 CW |
3763 | if (obj->base.import_attach) |
3764 | drm_prime_gem_destroy(&obj->base, NULL); | |
3765 | ||
05394f39 CW |
3766 | drm_gem_object_release(&obj->base); |
3767 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3768 | |
05394f39 CW |
3769 | kfree(obj->bit_17); |
3770 | kfree(obj); | |
673a394b EA |
3771 | } |
3772 | ||
29105ccc CW |
3773 | int |
3774 | i915_gem_idle(struct drm_device *dev) | |
3775 | { | |
3776 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3777 | int ret; | |
28dfe52a | 3778 | |
29105ccc | 3779 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3780 | |
87acb0a5 | 3781 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3782 | mutex_unlock(&dev->struct_mutex); |
3783 | return 0; | |
28dfe52a EA |
3784 | } |
3785 | ||
b2da9fe5 | 3786 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3787 | if (ret) { |
3788 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3789 | return ret; |
6dbe2772 | 3790 | } |
b2da9fe5 | 3791 | i915_gem_retire_requests(dev); |
673a394b | 3792 | |
29105ccc | 3793 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3794 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3795 | i915_gem_evict_everything(dev); |
29105ccc | 3796 | |
312817a3 CW |
3797 | i915_gem_reset_fences(dev); |
3798 | ||
29105ccc CW |
3799 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3800 | * We need to replace this with a semaphore, or something. | |
3801 | * And not confound mm.suspended! | |
3802 | */ | |
3803 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3804 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3805 | |
3806 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3807 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3808 | |
6dbe2772 KP |
3809 | mutex_unlock(&dev->struct_mutex); |
3810 | ||
29105ccc CW |
3811 | /* Cancel the retire work handler, which should be idle now. */ |
3812 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3813 | ||
673a394b EA |
3814 | return 0; |
3815 | } | |
3816 | ||
b9524a1e BW |
3817 | void i915_gem_l3_remap(struct drm_device *dev) |
3818 | { | |
3819 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3820 | u32 misccpctl; | |
3821 | int i; | |
3822 | ||
3823 | if (!IS_IVYBRIDGE(dev)) | |
3824 | return; | |
3825 | ||
3826 | if (!dev_priv->mm.l3_remap_info) | |
3827 | return; | |
3828 | ||
3829 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3830 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3831 | POSTING_READ(GEN7_MISCCPCTL); | |
3832 | ||
3833 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3834 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
3835 | if (remap && remap != dev_priv->mm.l3_remap_info[i/4]) | |
3836 | DRM_DEBUG("0x%x was already programmed to %x\n", | |
3837 | GEN7_L3LOG_BASE + i, remap); | |
3838 | if (remap && !dev_priv->mm.l3_remap_info[i/4]) | |
3839 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); | |
3840 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]); | |
3841 | } | |
3842 | ||
3843 | /* Make sure all the writes land before disabling dop clock gating */ | |
3844 | POSTING_READ(GEN7_L3LOG_BASE); | |
3845 | ||
3846 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3847 | } | |
3848 | ||
f691e2f4 DV |
3849 | void i915_gem_init_swizzling(struct drm_device *dev) |
3850 | { | |
3851 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3852 | ||
11782b02 | 3853 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3854 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3855 | return; | |
3856 | ||
3857 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3858 | DISP_TILE_SURFACE_SWIZZLING); | |
3859 | ||
11782b02 DV |
3860 | if (IS_GEN5(dev)) |
3861 | return; | |
3862 | ||
f691e2f4 DV |
3863 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3864 | if (IS_GEN6(dev)) | |
6b26c86d | 3865 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3866 | else |
6b26c86d | 3867 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3868 | } |
e21af88d DV |
3869 | |
3870 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3871 | { | |
3872 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3873 | uint32_t pd_offset; | |
3874 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3875 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3876 | uint32_t __iomem *pd_addr; | |
3877 | uint32_t pd_entry; | |
e21af88d DV |
3878 | int i; |
3879 | ||
3880 | if (!dev_priv->mm.aliasing_ppgtt) | |
3881 | return; | |
3882 | ||
55a254ac DV |
3883 | |
3884 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3885 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3886 | dma_addr_t pt_addr; | |
3887 | ||
3888 | if (dev_priv->mm.gtt->needs_dmar) | |
3889 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3890 | else | |
3891 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3892 | ||
3893 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3894 | pd_entry |= GEN6_PDE_VALID; | |
3895 | ||
3896 | writel(pd_entry, pd_addr + i); | |
3897 | } | |
3898 | readl(pd_addr); | |
3899 | ||
3900 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3901 | pd_offset /= 64; /* in cachelines, */ |
3902 | pd_offset <<= 16; | |
3903 | ||
3904 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3905 | uint32_t ecochk, gab_ctl, ecobits; |
3906 | ||
3907 | ecobits = I915_READ(GAC_ECO_BITS); | |
3908 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3909 | |
3910 | gab_ctl = I915_READ(GAB_CTL); | |
3911 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3912 | ||
3913 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3914 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3915 | ECOCHK_PPGTT_CACHE64B); | |
6b26c86d | 3916 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3917 | } else if (INTEL_INFO(dev)->gen >= 7) { |
3918 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3919 | /* GFX_MODE is per-ring on gen7+ */ | |
3920 | } | |
3921 | ||
b4519513 | 3922 | for_each_ring(ring, dev_priv, i) { |
e21af88d DV |
3923 | if (INTEL_INFO(dev)->gen >= 7) |
3924 | I915_WRITE(RING_MODE_GEN7(ring), | |
6b26c86d | 3925 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3926 | |
3927 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3928 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3929 | } | |
3930 | } | |
3931 | ||
67b1b571 CW |
3932 | static bool |
3933 | intel_enable_blt(struct drm_device *dev) | |
3934 | { | |
3935 | if (!HAS_BLT(dev)) | |
3936 | return false; | |
3937 | ||
3938 | /* The blitter was dysfunctional on early prototypes */ | |
3939 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3940 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3941 | " graphics performance will be degraded.\n"); | |
3942 | return false; | |
3943 | } | |
3944 | ||
3945 | return true; | |
3946 | } | |
3947 | ||
8187a2b7 | 3948 | int |
f691e2f4 | 3949 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3950 | { |
3951 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3952 | int ret; | |
68f95ba9 | 3953 | |
8ecd1a66 DV |
3954 | if (!intel_enable_gtt()) |
3955 | return -EIO; | |
3956 | ||
b9524a1e BW |
3957 | i915_gem_l3_remap(dev); |
3958 | ||
f691e2f4 DV |
3959 | i915_gem_init_swizzling(dev); |
3960 | ||
5c1143bb | 3961 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3962 | if (ret) |
b6913e4b | 3963 | return ret; |
68f95ba9 CW |
3964 | |
3965 | if (HAS_BSD(dev)) { | |
5c1143bb | 3966 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3967 | if (ret) |
3968 | goto cleanup_render_ring; | |
d1b851fc | 3969 | } |
68f95ba9 | 3970 | |
67b1b571 | 3971 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3972 | ret = intel_init_blt_ring_buffer(dev); |
3973 | if (ret) | |
3974 | goto cleanup_bsd_ring; | |
3975 | } | |
3976 | ||
6f392d54 CW |
3977 | dev_priv->next_seqno = 1; |
3978 | ||
254f965c BW |
3979 | /* |
3980 | * XXX: There was some w/a described somewhere suggesting loading | |
3981 | * contexts before PPGTT. | |
3982 | */ | |
3983 | i915_gem_context_init(dev); | |
e21af88d DV |
3984 | i915_gem_init_ppgtt(dev); |
3985 | ||
68f95ba9 CW |
3986 | return 0; |
3987 | ||
549f7365 | 3988 | cleanup_bsd_ring: |
1ec14ad3 | 3989 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3990 | cleanup_render_ring: |
1ec14ad3 | 3991 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3992 | return ret; |
3993 | } | |
3994 | ||
1070a42b CW |
3995 | static bool |
3996 | intel_enable_ppgtt(struct drm_device *dev) | |
3997 | { | |
3998 | if (i915_enable_ppgtt >= 0) | |
3999 | return i915_enable_ppgtt; | |
4000 | ||
4001 | #ifdef CONFIG_INTEL_IOMMU | |
4002 | /* Disable ppgtt on SNB if VT-d is on. */ | |
4003 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
4004 | return false; | |
4005 | #endif | |
4006 | ||
4007 | return true; | |
4008 | } | |
4009 | ||
4010 | int i915_gem_init(struct drm_device *dev) | |
4011 | { | |
4012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4013 | unsigned long gtt_size, mappable_size; | |
4014 | int ret; | |
4015 | ||
4016 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
4017 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
4018 | ||
4019 | mutex_lock(&dev->struct_mutex); | |
4020 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
4021 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
4022 | * aperture accordingly when using aliasing ppgtt. */ | |
4023 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
4024 | ||
4025 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
4026 | ||
4027 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
4028 | if (ret) { | |
4029 | mutex_unlock(&dev->struct_mutex); | |
4030 | return ret; | |
4031 | } | |
4032 | } else { | |
4033 | /* Let GEM Manage all of the aperture. | |
4034 | * | |
4035 | * However, leave one page at the end still bound to the scratch | |
4036 | * page. There are a number of places where the hardware | |
4037 | * apparently prefetches past the end of the object, and we've | |
4038 | * seen multiple hangs with the GPU head pointer stuck in a | |
4039 | * batchbuffer bound at the last page of the aperture. One page | |
4040 | * should be enough to keep any prefetching inside of the | |
4041 | * aperture. | |
4042 | */ | |
4043 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
4044 | gtt_size); | |
4045 | } | |
4046 | ||
4047 | ret = i915_gem_init_hw(dev); | |
4048 | mutex_unlock(&dev->struct_mutex); | |
4049 | if (ret) { | |
4050 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4051 | return ret; | |
4052 | } | |
4053 | ||
53ca26ca DV |
4054 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4055 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4056 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4057 | return 0; |
4058 | } | |
4059 | ||
8187a2b7 ZN |
4060 | void |
4061 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4062 | { | |
4063 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4064 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4065 | int i; |
8187a2b7 | 4066 | |
b4519513 CW |
4067 | for_each_ring(ring, dev_priv, i) |
4068 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4069 | } |
4070 | ||
673a394b EA |
4071 | int |
4072 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4073 | struct drm_file *file_priv) | |
4074 | { | |
4075 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4076 | int ret; |
673a394b | 4077 | |
79e53945 JB |
4078 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4079 | return 0; | |
4080 | ||
ba1234d1 | 4081 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4082 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4083 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4084 | } |
4085 | ||
673a394b | 4086 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4087 | dev_priv->mm.suspended = 0; |
4088 | ||
f691e2f4 | 4089 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4090 | if (ret != 0) { |
4091 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4092 | return ret; |
d816f6ac | 4093 | } |
9bb2d6f9 | 4094 | |
69dc4987 | 4095 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4096 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
673a394b | 4097 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4098 | |
5f35308b CW |
4099 | ret = drm_irq_install(dev); |
4100 | if (ret) | |
4101 | goto cleanup_ringbuffer; | |
dbb19d30 | 4102 | |
673a394b | 4103 | return 0; |
5f35308b CW |
4104 | |
4105 | cleanup_ringbuffer: | |
4106 | mutex_lock(&dev->struct_mutex); | |
4107 | i915_gem_cleanup_ringbuffer(dev); | |
4108 | dev_priv->mm.suspended = 1; | |
4109 | mutex_unlock(&dev->struct_mutex); | |
4110 | ||
4111 | return ret; | |
673a394b EA |
4112 | } |
4113 | ||
4114 | int | |
4115 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4116 | struct drm_file *file_priv) | |
4117 | { | |
79e53945 JB |
4118 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4119 | return 0; | |
4120 | ||
dbb19d30 | 4121 | drm_irq_uninstall(dev); |
e6890f6f | 4122 | return i915_gem_idle(dev); |
673a394b EA |
4123 | } |
4124 | ||
4125 | void | |
4126 | i915_gem_lastclose(struct drm_device *dev) | |
4127 | { | |
4128 | int ret; | |
673a394b | 4129 | |
e806b495 EA |
4130 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4131 | return; | |
4132 | ||
6dbe2772 KP |
4133 | ret = i915_gem_idle(dev); |
4134 | if (ret) | |
4135 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4136 | } |
4137 | ||
64193406 CW |
4138 | static void |
4139 | init_ring_lists(struct intel_ring_buffer *ring) | |
4140 | { | |
4141 | INIT_LIST_HEAD(&ring->active_list); | |
4142 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4143 | } |
4144 | ||
673a394b EA |
4145 | void |
4146 | i915_gem_load(struct drm_device *dev) | |
4147 | { | |
b5aa8a0f | 4148 | int i; |
673a394b EA |
4149 | drm_i915_private_t *dev_priv = dev->dev_private; |
4150 | ||
69dc4987 | 4151 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4152 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4153 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4154 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4155 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4156 | for (i = 0; i < I915_NUM_RINGS; i++) |
4157 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4158 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4159 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4160 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4161 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4162 | init_completion(&dev_priv->error_completion); |
31169714 | 4163 | |
94400120 DA |
4164 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4165 | if (IS_GEN3(dev)) { | |
50743298 DV |
4166 | I915_WRITE(MI_ARB_STATE, |
4167 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4168 | } |
4169 | ||
72bfa19c CW |
4170 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4171 | ||
de151cf6 | 4172 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4173 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4174 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4175 | |
a6c45cf0 | 4176 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4177 | dev_priv->num_fence_regs = 16; |
4178 | else | |
4179 | dev_priv->num_fence_regs = 8; | |
4180 | ||
b5aa8a0f | 4181 | /* Initialize fence registers to zero */ |
ada726c7 | 4182 | i915_gem_reset_fences(dev); |
10ed13e4 | 4183 | |
673a394b | 4184 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4185 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4186 | |
ce453d81 CW |
4187 | dev_priv->mm.interruptible = true; |
4188 | ||
17250b71 CW |
4189 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4190 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4191 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4192 | } |
71acb5eb DA |
4193 | |
4194 | /* | |
4195 | * Create a physically contiguous memory object for this object | |
4196 | * e.g. for cursor + overlay regs | |
4197 | */ | |
995b6762 CW |
4198 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4199 | int id, int size, int align) | |
71acb5eb DA |
4200 | { |
4201 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4202 | struct drm_i915_gem_phys_object *phys_obj; | |
4203 | int ret; | |
4204 | ||
4205 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4206 | return 0; | |
4207 | ||
9a298b2a | 4208 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4209 | if (!phys_obj) |
4210 | return -ENOMEM; | |
4211 | ||
4212 | phys_obj->id = id; | |
4213 | ||
6eeefaf3 | 4214 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4215 | if (!phys_obj->handle) { |
4216 | ret = -ENOMEM; | |
4217 | goto kfree_obj; | |
4218 | } | |
4219 | #ifdef CONFIG_X86 | |
4220 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4221 | #endif | |
4222 | ||
4223 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4224 | ||
4225 | return 0; | |
4226 | kfree_obj: | |
9a298b2a | 4227 | kfree(phys_obj); |
71acb5eb DA |
4228 | return ret; |
4229 | } | |
4230 | ||
995b6762 | 4231 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4232 | { |
4233 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4234 | struct drm_i915_gem_phys_object *phys_obj; | |
4235 | ||
4236 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4237 | return; | |
4238 | ||
4239 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4240 | if (phys_obj->cur_obj) { | |
4241 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4242 | } | |
4243 | ||
4244 | #ifdef CONFIG_X86 | |
4245 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4246 | #endif | |
4247 | drm_pci_free(dev, phys_obj->handle); | |
4248 | kfree(phys_obj); | |
4249 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4250 | } | |
4251 | ||
4252 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4253 | { | |
4254 | int i; | |
4255 | ||
260883c8 | 4256 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4257 | i915_gem_free_phys_object(dev, i); |
4258 | } | |
4259 | ||
4260 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4261 | struct drm_i915_gem_object *obj) |
71acb5eb | 4262 | { |
05394f39 | 4263 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4264 | char *vaddr; |
71acb5eb | 4265 | int i; |
71acb5eb DA |
4266 | int page_count; |
4267 | ||
05394f39 | 4268 | if (!obj->phys_obj) |
71acb5eb | 4269 | return; |
05394f39 | 4270 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4271 | |
05394f39 | 4272 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4273 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4274 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4275 | if (!IS_ERR(page)) { |
4276 | char *dst = kmap_atomic(page); | |
4277 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4278 | kunmap_atomic(dst); | |
4279 | ||
4280 | drm_clflush_pages(&page, 1); | |
4281 | ||
4282 | set_page_dirty(page); | |
4283 | mark_page_accessed(page); | |
4284 | page_cache_release(page); | |
4285 | } | |
71acb5eb | 4286 | } |
40ce6575 | 4287 | intel_gtt_chipset_flush(); |
d78b47b9 | 4288 | |
05394f39 CW |
4289 | obj->phys_obj->cur_obj = NULL; |
4290 | obj->phys_obj = NULL; | |
71acb5eb DA |
4291 | } |
4292 | ||
4293 | int | |
4294 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4295 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4296 | int id, |
4297 | int align) | |
71acb5eb | 4298 | { |
05394f39 | 4299 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4300 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4301 | int ret = 0; |
4302 | int page_count; | |
4303 | int i; | |
4304 | ||
4305 | if (id > I915_MAX_PHYS_OBJECT) | |
4306 | return -EINVAL; | |
4307 | ||
05394f39 CW |
4308 | if (obj->phys_obj) { |
4309 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4310 | return 0; |
4311 | i915_gem_detach_phys_object(dev, obj); | |
4312 | } | |
4313 | ||
71acb5eb DA |
4314 | /* create a new object */ |
4315 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4316 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4317 | obj->base.size, align); |
71acb5eb | 4318 | if (ret) { |
05394f39 CW |
4319 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4320 | id, obj->base.size); | |
e5281ccd | 4321 | return ret; |
71acb5eb DA |
4322 | } |
4323 | } | |
4324 | ||
4325 | /* bind to the object */ | |
05394f39 CW |
4326 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4327 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4328 | |
05394f39 | 4329 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4330 | |
4331 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4332 | struct page *page; |
4333 | char *dst, *src; | |
4334 | ||
5949eac4 | 4335 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4336 | if (IS_ERR(page)) |
4337 | return PTR_ERR(page); | |
71acb5eb | 4338 | |
ff75b9bc | 4339 | src = kmap_atomic(page); |
05394f39 | 4340 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4341 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4342 | kunmap_atomic(src); |
71acb5eb | 4343 | |
e5281ccd CW |
4344 | mark_page_accessed(page); |
4345 | page_cache_release(page); | |
4346 | } | |
d78b47b9 | 4347 | |
71acb5eb | 4348 | return 0; |
71acb5eb DA |
4349 | } |
4350 | ||
4351 | static int | |
05394f39 CW |
4352 | i915_gem_phys_pwrite(struct drm_device *dev, |
4353 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4354 | struct drm_i915_gem_pwrite *args, |
4355 | struct drm_file *file_priv) | |
4356 | { | |
05394f39 | 4357 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4358 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4359 | |
b47b30cc CW |
4360 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4361 | unsigned long unwritten; | |
4362 | ||
4363 | /* The physical object once assigned is fixed for the lifetime | |
4364 | * of the obj, so we can safely drop the lock and continue | |
4365 | * to access vaddr. | |
4366 | */ | |
4367 | mutex_unlock(&dev->struct_mutex); | |
4368 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4369 | mutex_lock(&dev->struct_mutex); | |
4370 | if (unwritten) | |
4371 | return -EFAULT; | |
4372 | } | |
71acb5eb | 4373 | |
40ce6575 | 4374 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4375 | return 0; |
4376 | } | |
b962442e | 4377 | |
f787a5f5 | 4378 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4379 | { |
f787a5f5 | 4380 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4381 | |
4382 | /* Clean up our request list when the client is going away, so that | |
4383 | * later retire_requests won't dereference our soon-to-be-gone | |
4384 | * file_priv. | |
4385 | */ | |
1c25595f | 4386 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4387 | while (!list_empty(&file_priv->mm.request_list)) { |
4388 | struct drm_i915_gem_request *request; | |
4389 | ||
4390 | request = list_first_entry(&file_priv->mm.request_list, | |
4391 | struct drm_i915_gem_request, | |
4392 | client_list); | |
4393 | list_del(&request->client_list); | |
4394 | request->file_priv = NULL; | |
4395 | } | |
1c25595f | 4396 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4397 | } |
31169714 | 4398 | |
31169714 | 4399 | static int |
1495f230 | 4400 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4401 | { |
17250b71 CW |
4402 | struct drm_i915_private *dev_priv = |
4403 | container_of(shrinker, | |
4404 | struct drm_i915_private, | |
4405 | mm.inactive_shrinker); | |
4406 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4407 | struct drm_i915_gem_object *obj; |
1495f230 | 4408 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4409 | int cnt; |
4410 | ||
4411 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4412 | return 0; |
31169714 | 4413 | |
6c085a72 CW |
4414 | if (nr_to_scan) { |
4415 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4416 | if (nr_to_scan > 0) | |
4417 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4418 | } |
4419 | ||
17250b71 | 4420 | cnt = 0; |
6c085a72 | 4421 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4422 | if (obj->pages_pin_count == 0) |
4423 | cnt += obj->base.size >> PAGE_SHIFT; | |
6c085a72 | 4424 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
a5570178 | 4425 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4426 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4427 | |
17250b71 | 4428 | mutex_unlock(&dev->struct_mutex); |
6c085a72 | 4429 | return cnt; |
31169714 | 4430 | } |