Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 JB |
53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
54 | unsigned alignment); | |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
31169714 CW |
61 | static LIST_HEAD(shrink_list); |
62 | static DEFINE_SPINLOCK(shrink_list_lock); | |
63 | ||
30dbf0c0 CW |
64 | int |
65 | i915_gem_check_is_wedged(struct drm_device *dev) | |
66 | { | |
67 | struct drm_i915_private *dev_priv = dev->dev_private; | |
68 | struct completion *x = &dev_priv->error_completion; | |
69 | unsigned long flags; | |
70 | int ret; | |
71 | ||
72 | if (!atomic_read(&dev_priv->mm.wedged)) | |
73 | return 0; | |
74 | ||
75 | ret = wait_for_completion_interruptible(x); | |
76 | if (ret) | |
77 | return ret; | |
78 | ||
79 | /* Success, we reset the GPU! */ | |
80 | if (!atomic_read(&dev_priv->mm.wedged)) | |
81 | return 0; | |
82 | ||
83 | /* GPU is hung, bump the completion count to account for | |
84 | * the token we just consumed so that we never hit zero and | |
85 | * end up waiting upon a subsequent completion event that | |
86 | * will never happen. | |
87 | */ | |
88 | spin_lock_irqsave(&x->wait.lock, flags); | |
89 | x->done++; | |
90 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
91 | return -EIO; | |
92 | } | |
93 | ||
76c1dec1 CW |
94 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
95 | { | |
96 | struct drm_i915_private *dev_priv = dev->dev_private; | |
97 | int ret; | |
98 | ||
99 | ret = i915_gem_check_is_wedged(dev); | |
100 | if (ret) | |
101 | return ret; | |
102 | ||
103 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
104 | if (ret) | |
105 | return ret; | |
106 | ||
107 | if (atomic_read(&dev_priv->mm.wedged)) { | |
108 | mutex_unlock(&dev->struct_mutex); | |
109 | return -EAGAIN; | |
110 | } | |
111 | ||
23bc5982 | 112 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
113 | return 0; |
114 | } | |
30dbf0c0 | 115 | |
7d1c4804 CW |
116 | static inline bool |
117 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
118 | { | |
119 | return obj_priv->gtt_space && | |
120 | !obj_priv->active && | |
121 | obj_priv->pin_count == 0; | |
122 | } | |
123 | ||
79e53945 JB |
124 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
125 | unsigned long end) | |
673a394b EA |
126 | { |
127 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 128 | |
79e53945 JB |
129 | if (start >= end || |
130 | (start & (PAGE_SIZE - 1)) != 0 || | |
131 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
132 | return -EINVAL; |
133 | } | |
134 | ||
79e53945 JB |
135 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
136 | end - start); | |
673a394b | 137 | |
79e53945 JB |
138 | dev->gtt_total = (uint32_t) (end - start); |
139 | ||
140 | return 0; | |
141 | } | |
673a394b | 142 | |
79e53945 JB |
143 | int |
144 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
145 | struct drm_file *file_priv) | |
146 | { | |
147 | struct drm_i915_gem_init *args = data; | |
148 | int ret; | |
149 | ||
150 | mutex_lock(&dev->struct_mutex); | |
151 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
152 | mutex_unlock(&dev->struct_mutex); |
153 | ||
79e53945 | 154 | return ret; |
673a394b EA |
155 | } |
156 | ||
5a125c3c EA |
157 | int |
158 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
159 | struct drm_file *file_priv) | |
160 | { | |
5a125c3c | 161 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
162 | |
163 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
164 | return -ENODEV; | |
165 | ||
166 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
167 | args->aper_available_size = (args->aper_size - |
168 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
169 | |
170 | return 0; | |
171 | } | |
172 | ||
673a394b EA |
173 | |
174 | /** | |
175 | * Creates a new mm object and returns a handle to it. | |
176 | */ | |
177 | int | |
178 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
179 | struct drm_file *file_priv) | |
180 | { | |
181 | struct drm_i915_gem_create *args = data; | |
182 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
183 | int ret; |
184 | u32 handle; | |
673a394b EA |
185 | |
186 | args->size = roundup(args->size, PAGE_SIZE); | |
187 | ||
188 | /* Allocate the new object */ | |
ac52bc56 | 189 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
190 | if (obj == NULL) |
191 | return -ENOMEM; | |
192 | ||
193 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 CW |
194 | if (ret) { |
195 | drm_gem_object_unreference_unlocked(obj); | |
673a394b | 196 | return ret; |
1dfd9754 | 197 | } |
673a394b | 198 | |
1dfd9754 CW |
199 | /* Sink the floating reference from kref_init(handlecount) */ |
200 | drm_gem_object_handle_unreference_unlocked(obj); | |
673a394b | 201 | |
1dfd9754 | 202 | args->handle = handle; |
673a394b EA |
203 | return 0; |
204 | } | |
205 | ||
eb01459f EA |
206 | static inline int |
207 | fast_shmem_read(struct page **pages, | |
208 | loff_t page_base, int page_offset, | |
209 | char __user *data, | |
210 | int length) | |
211 | { | |
212 | char __iomem *vaddr; | |
2bc43b5c | 213 | int unwritten; |
eb01459f EA |
214 | |
215 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
216 | if (vaddr == NULL) | |
217 | return -ENOMEM; | |
2bc43b5c | 218 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
219 | kunmap_atomic(vaddr, KM_USER0); |
220 | ||
2bc43b5c FM |
221 | if (unwritten) |
222 | return -EFAULT; | |
223 | ||
224 | return 0; | |
eb01459f EA |
225 | } |
226 | ||
280b713b EA |
227 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
228 | { | |
229 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 230 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
231 | |
232 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
233 | obj_priv->tiling_mode != I915_TILING_NONE; | |
234 | } | |
235 | ||
99a03df5 | 236 | static inline void |
40123c1f EA |
237 | slow_shmem_copy(struct page *dst_page, |
238 | int dst_offset, | |
239 | struct page *src_page, | |
240 | int src_offset, | |
241 | int length) | |
242 | { | |
243 | char *dst_vaddr, *src_vaddr; | |
244 | ||
99a03df5 CW |
245 | dst_vaddr = kmap(dst_page); |
246 | src_vaddr = kmap(src_page); | |
40123c1f EA |
247 | |
248 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
249 | ||
99a03df5 CW |
250 | kunmap(src_page); |
251 | kunmap(dst_page); | |
40123c1f EA |
252 | } |
253 | ||
99a03df5 | 254 | static inline void |
280b713b EA |
255 | slow_shmem_bit17_copy(struct page *gpu_page, |
256 | int gpu_offset, | |
257 | struct page *cpu_page, | |
258 | int cpu_offset, | |
259 | int length, | |
260 | int is_read) | |
261 | { | |
262 | char *gpu_vaddr, *cpu_vaddr; | |
263 | ||
264 | /* Use the unswizzled path if this page isn't affected. */ | |
265 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
266 | if (is_read) | |
267 | return slow_shmem_copy(cpu_page, cpu_offset, | |
268 | gpu_page, gpu_offset, length); | |
269 | else | |
270 | return slow_shmem_copy(gpu_page, gpu_offset, | |
271 | cpu_page, cpu_offset, length); | |
272 | } | |
273 | ||
99a03df5 CW |
274 | gpu_vaddr = kmap(gpu_page); |
275 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
276 | |
277 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
278 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
279 | */ | |
280 | while (length > 0) { | |
281 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
282 | int this_length = min(cacheline_end - gpu_offset, length); | |
283 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
284 | ||
285 | if (is_read) { | |
286 | memcpy(cpu_vaddr + cpu_offset, | |
287 | gpu_vaddr + swizzled_gpu_offset, | |
288 | this_length); | |
289 | } else { | |
290 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
291 | cpu_vaddr + cpu_offset, | |
292 | this_length); | |
293 | } | |
294 | cpu_offset += this_length; | |
295 | gpu_offset += this_length; | |
296 | length -= this_length; | |
297 | } | |
298 | ||
99a03df5 CW |
299 | kunmap(cpu_page); |
300 | kunmap(gpu_page); | |
280b713b EA |
301 | } |
302 | ||
eb01459f EA |
303 | /** |
304 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
305 | * from the backing pages of the object to the user's address space. On a | |
306 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
307 | */ | |
308 | static int | |
309 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
310 | struct drm_i915_gem_pread *args, | |
311 | struct drm_file *file_priv) | |
312 | { | |
23010e43 | 313 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
314 | ssize_t remain; |
315 | loff_t offset, page_base; | |
316 | char __user *user_data; | |
317 | int page_offset, page_length; | |
318 | int ret; | |
319 | ||
320 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
321 | remain = args->size; | |
322 | ||
76c1dec1 CW |
323 | ret = i915_mutex_lock_interruptible(dev); |
324 | if (ret) | |
325 | return ret; | |
eb01459f | 326 | |
4bdadb97 | 327 | ret = i915_gem_object_get_pages(obj, 0); |
eb01459f EA |
328 | if (ret != 0) |
329 | goto fail_unlock; | |
330 | ||
331 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
332 | args->size); | |
333 | if (ret != 0) | |
334 | goto fail_put_pages; | |
335 | ||
23010e43 | 336 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
337 | offset = args->offset; |
338 | ||
339 | while (remain > 0) { | |
340 | /* Operation in this page | |
341 | * | |
342 | * page_base = page offset within aperture | |
343 | * page_offset = offset within page | |
344 | * page_length = bytes to copy for this page | |
345 | */ | |
346 | page_base = (offset & ~(PAGE_SIZE-1)); | |
347 | page_offset = offset & (PAGE_SIZE-1); | |
348 | page_length = remain; | |
349 | if ((page_offset + remain) > PAGE_SIZE) | |
350 | page_length = PAGE_SIZE - page_offset; | |
351 | ||
352 | ret = fast_shmem_read(obj_priv->pages, | |
353 | page_base, page_offset, | |
354 | user_data, page_length); | |
355 | if (ret) | |
356 | goto fail_put_pages; | |
357 | ||
358 | remain -= page_length; | |
359 | user_data += page_length; | |
360 | offset += page_length; | |
361 | } | |
362 | ||
363 | fail_put_pages: | |
364 | i915_gem_object_put_pages(obj); | |
365 | fail_unlock: | |
366 | mutex_unlock(&dev->struct_mutex); | |
367 | ||
368 | return ret; | |
369 | } | |
370 | ||
07f73f69 CW |
371 | static int |
372 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
373 | { | |
374 | int ret; | |
375 | ||
4bdadb97 | 376 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
377 | |
378 | /* If we've insufficient memory to map in the pages, attempt | |
379 | * to make some space by throwing out some old buffers. | |
380 | */ | |
381 | if (ret == -ENOMEM) { | |
382 | struct drm_device *dev = obj->dev; | |
07f73f69 | 383 | |
0108a3ed DV |
384 | ret = i915_gem_evict_something(dev, obj->size, |
385 | i915_gem_get_gtt_alignment(obj)); | |
07f73f69 CW |
386 | if (ret) |
387 | return ret; | |
388 | ||
4bdadb97 | 389 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
390 | } |
391 | ||
392 | return ret; | |
393 | } | |
394 | ||
eb01459f EA |
395 | /** |
396 | * This is the fallback shmem pread path, which allocates temporary storage | |
397 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
398 | * can copy out of the object's backing pages while holding the struct mutex | |
399 | * and not take page faults. | |
400 | */ | |
401 | static int | |
402 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
403 | struct drm_i915_gem_pread *args, | |
404 | struct drm_file *file_priv) | |
405 | { | |
23010e43 | 406 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
407 | struct mm_struct *mm = current->mm; |
408 | struct page **user_pages; | |
409 | ssize_t remain; | |
410 | loff_t offset, pinned_pages, i; | |
411 | loff_t first_data_page, last_data_page, num_pages; | |
412 | int shmem_page_index, shmem_page_offset; | |
413 | int data_page_index, data_page_offset; | |
414 | int page_length; | |
415 | int ret; | |
416 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 417 | int do_bit17_swizzling; |
eb01459f EA |
418 | |
419 | remain = args->size; | |
420 | ||
421 | /* Pin the user pages containing the data. We can't fault while | |
422 | * holding the struct mutex, yet we want to hold it while | |
423 | * dereferencing the user data. | |
424 | */ | |
425 | first_data_page = data_ptr / PAGE_SIZE; | |
426 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
427 | num_pages = last_data_page - first_data_page + 1; | |
428 | ||
8e7d2b2c | 429 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
430 | if (user_pages == NULL) |
431 | return -ENOMEM; | |
432 | ||
433 | down_read(&mm->mmap_sem); | |
434 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 435 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
436 | up_read(&mm->mmap_sem); |
437 | if (pinned_pages < num_pages) { | |
438 | ret = -EFAULT; | |
439 | goto fail_put_user_pages; | |
440 | } | |
441 | ||
280b713b EA |
442 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
443 | ||
76c1dec1 CW |
444 | ret = i915_mutex_lock_interruptible(dev); |
445 | if (ret) | |
446 | goto fail_put_user_pages; | |
eb01459f | 447 | |
07f73f69 CW |
448 | ret = i915_gem_object_get_pages_or_evict(obj); |
449 | if (ret) | |
eb01459f EA |
450 | goto fail_unlock; |
451 | ||
452 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
453 | args->size); | |
454 | if (ret != 0) | |
455 | goto fail_put_pages; | |
456 | ||
23010e43 | 457 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
458 | offset = args->offset; |
459 | ||
460 | while (remain > 0) { | |
461 | /* Operation in this page | |
462 | * | |
463 | * shmem_page_index = page number within shmem file | |
464 | * shmem_page_offset = offset within page in shmem file | |
465 | * data_page_index = page number in get_user_pages return | |
466 | * data_page_offset = offset with data_page_index page. | |
467 | * page_length = bytes to copy for this page | |
468 | */ | |
469 | shmem_page_index = offset / PAGE_SIZE; | |
470 | shmem_page_offset = offset & ~PAGE_MASK; | |
471 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
472 | data_page_offset = data_ptr & ~PAGE_MASK; | |
473 | ||
474 | page_length = remain; | |
475 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
476 | page_length = PAGE_SIZE - shmem_page_offset; | |
477 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
478 | page_length = PAGE_SIZE - data_page_offset; | |
479 | ||
280b713b | 480 | if (do_bit17_swizzling) { |
99a03df5 | 481 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 482 | shmem_page_offset, |
99a03df5 CW |
483 | user_pages[data_page_index], |
484 | data_page_offset, | |
485 | page_length, | |
486 | 1); | |
487 | } else { | |
488 | slow_shmem_copy(user_pages[data_page_index], | |
489 | data_page_offset, | |
490 | obj_priv->pages[shmem_page_index], | |
491 | shmem_page_offset, | |
492 | page_length); | |
280b713b | 493 | } |
eb01459f EA |
494 | |
495 | remain -= page_length; | |
496 | data_ptr += page_length; | |
497 | offset += page_length; | |
498 | } | |
499 | ||
500 | fail_put_pages: | |
501 | i915_gem_object_put_pages(obj); | |
502 | fail_unlock: | |
503 | mutex_unlock(&dev->struct_mutex); | |
504 | fail_put_user_pages: | |
505 | for (i = 0; i < pinned_pages; i++) { | |
506 | SetPageDirty(user_pages[i]); | |
507 | page_cache_release(user_pages[i]); | |
508 | } | |
8e7d2b2c | 509 | drm_free_large(user_pages); |
eb01459f EA |
510 | |
511 | return ret; | |
512 | } | |
513 | ||
673a394b EA |
514 | /** |
515 | * Reads data from the object referenced by handle. | |
516 | * | |
517 | * On error, the contents of *data are undefined. | |
518 | */ | |
519 | int | |
520 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
521 | struct drm_file *file_priv) | |
522 | { | |
523 | struct drm_i915_gem_pread *args = data; | |
524 | struct drm_gem_object *obj; | |
525 | struct drm_i915_gem_object *obj_priv; | |
673a394b EA |
526 | int ret; |
527 | ||
528 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
529 | if (obj == NULL) | |
bf79cb91 | 530 | return -ENOENT; |
23010e43 | 531 | obj_priv = to_intel_bo(obj); |
673a394b EA |
532 | |
533 | /* Bounds check source. | |
534 | * | |
535 | * XXX: This could use review for overflow issues... | |
536 | */ | |
537 | if (args->offset > obj->size || args->size > obj->size || | |
538 | args->offset + args->size > obj->size) { | |
bc9025bd | 539 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
540 | return -EINVAL; |
541 | } | |
542 | ||
280b713b | 543 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 544 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
545 | } else { |
546 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
547 | if (ret != 0) | |
548 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
549 | file_priv); | |
550 | } | |
673a394b | 551 | |
bc9025bd | 552 | drm_gem_object_unreference_unlocked(obj); |
673a394b | 553 | |
eb01459f | 554 | return ret; |
673a394b EA |
555 | } |
556 | ||
0839ccb8 KP |
557 | /* This is the fast write path which cannot handle |
558 | * page faults in the source data | |
9b7530cc | 559 | */ |
0839ccb8 KP |
560 | |
561 | static inline int | |
562 | fast_user_write(struct io_mapping *mapping, | |
563 | loff_t page_base, int page_offset, | |
564 | char __user *user_data, | |
565 | int length) | |
9b7530cc | 566 | { |
9b7530cc | 567 | char *vaddr_atomic; |
0839ccb8 | 568 | unsigned long unwritten; |
9b7530cc | 569 | |
fca3ec01 | 570 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
0839ccb8 KP |
571 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
572 | user_data, length); | |
fca3ec01 | 573 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
0839ccb8 KP |
574 | if (unwritten) |
575 | return -EFAULT; | |
576 | return 0; | |
577 | } | |
578 | ||
579 | /* Here's the write path which can sleep for | |
580 | * page faults | |
581 | */ | |
582 | ||
ab34c226 | 583 | static inline void |
3de09aa3 EA |
584 | slow_kernel_write(struct io_mapping *mapping, |
585 | loff_t gtt_base, int gtt_offset, | |
586 | struct page *user_page, int user_offset, | |
587 | int length) | |
0839ccb8 | 588 | { |
ab34c226 CW |
589 | char __iomem *dst_vaddr; |
590 | char *src_vaddr; | |
0839ccb8 | 591 | |
ab34c226 CW |
592 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
593 | src_vaddr = kmap(user_page); | |
594 | ||
595 | memcpy_toio(dst_vaddr + gtt_offset, | |
596 | src_vaddr + user_offset, | |
597 | length); | |
598 | ||
599 | kunmap(user_page); | |
600 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
601 | } |
602 | ||
40123c1f EA |
603 | static inline int |
604 | fast_shmem_write(struct page **pages, | |
605 | loff_t page_base, int page_offset, | |
606 | char __user *data, | |
607 | int length) | |
608 | { | |
609 | char __iomem *vaddr; | |
d0088775 | 610 | unsigned long unwritten; |
40123c1f EA |
611 | |
612 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
613 | if (vaddr == NULL) | |
614 | return -ENOMEM; | |
d0088775 | 615 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
616 | kunmap_atomic(vaddr, KM_USER0); |
617 | ||
d0088775 DA |
618 | if (unwritten) |
619 | return -EFAULT; | |
40123c1f EA |
620 | return 0; |
621 | } | |
622 | ||
3de09aa3 EA |
623 | /** |
624 | * This is the fast pwrite path, where we copy the data directly from the | |
625 | * user into the GTT, uncached. | |
626 | */ | |
673a394b | 627 | static int |
3de09aa3 EA |
628 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
629 | struct drm_i915_gem_pwrite *args, | |
630 | struct drm_file *file_priv) | |
673a394b | 631 | { |
23010e43 | 632 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 633 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 634 | ssize_t remain; |
0839ccb8 | 635 | loff_t offset, page_base; |
673a394b | 636 | char __user *user_data; |
0839ccb8 KP |
637 | int page_offset, page_length; |
638 | int ret; | |
673a394b EA |
639 | |
640 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
641 | remain = args->size; | |
642 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
643 | return -EFAULT; | |
644 | ||
76c1dec1 CW |
645 | ret = i915_mutex_lock_interruptible(dev); |
646 | if (ret) | |
647 | return ret; | |
673a394b | 648 | |
673a394b EA |
649 | ret = i915_gem_object_pin(obj, 0); |
650 | if (ret) { | |
651 | mutex_unlock(&dev->struct_mutex); | |
652 | return ret; | |
653 | } | |
2ef7eeaa | 654 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
655 | if (ret) |
656 | goto fail; | |
657 | ||
23010e43 | 658 | obj_priv = to_intel_bo(obj); |
673a394b | 659 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
660 | |
661 | while (remain > 0) { | |
662 | /* Operation in this page | |
663 | * | |
0839ccb8 KP |
664 | * page_base = page offset within aperture |
665 | * page_offset = offset within page | |
666 | * page_length = bytes to copy for this page | |
673a394b | 667 | */ |
0839ccb8 KP |
668 | page_base = (offset & ~(PAGE_SIZE-1)); |
669 | page_offset = offset & (PAGE_SIZE-1); | |
670 | page_length = remain; | |
671 | if ((page_offset + remain) > PAGE_SIZE) | |
672 | page_length = PAGE_SIZE - page_offset; | |
673 | ||
674 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
675 | page_offset, user_data, page_length); | |
676 | ||
677 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
678 | * source page isn't available. Return the error and we'll |
679 | * retry in the slow path. | |
0839ccb8 | 680 | */ |
3de09aa3 EA |
681 | if (ret) |
682 | goto fail; | |
673a394b | 683 | |
0839ccb8 KP |
684 | remain -= page_length; |
685 | user_data += page_length; | |
686 | offset += page_length; | |
673a394b | 687 | } |
673a394b EA |
688 | |
689 | fail: | |
690 | i915_gem_object_unpin(obj); | |
691 | mutex_unlock(&dev->struct_mutex); | |
692 | ||
693 | return ret; | |
694 | } | |
695 | ||
3de09aa3 EA |
696 | /** |
697 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
698 | * the memory and maps it using kmap_atomic for copying. | |
699 | * | |
700 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
701 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
702 | */ | |
3043c60c | 703 | static int |
3de09aa3 EA |
704 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
705 | struct drm_i915_gem_pwrite *args, | |
706 | struct drm_file *file_priv) | |
673a394b | 707 | { |
23010e43 | 708 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
709 | drm_i915_private_t *dev_priv = dev->dev_private; |
710 | ssize_t remain; | |
711 | loff_t gtt_page_base, offset; | |
712 | loff_t first_data_page, last_data_page, num_pages; | |
713 | loff_t pinned_pages, i; | |
714 | struct page **user_pages; | |
715 | struct mm_struct *mm = current->mm; | |
716 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 717 | int ret; |
3de09aa3 EA |
718 | uint64_t data_ptr = args->data_ptr; |
719 | ||
720 | remain = args->size; | |
721 | ||
722 | /* Pin the user pages containing the data. We can't fault while | |
723 | * holding the struct mutex, and all of the pwrite implementations | |
724 | * want to hold it while dereferencing the user data. | |
725 | */ | |
726 | first_data_page = data_ptr / PAGE_SIZE; | |
727 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
728 | num_pages = last_data_page - first_data_page + 1; | |
729 | ||
8e7d2b2c | 730 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
731 | if (user_pages == NULL) |
732 | return -ENOMEM; | |
733 | ||
734 | down_read(&mm->mmap_sem); | |
735 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
736 | num_pages, 0, 0, user_pages, NULL); | |
737 | up_read(&mm->mmap_sem); | |
738 | if (pinned_pages < num_pages) { | |
739 | ret = -EFAULT; | |
740 | goto out_unpin_pages; | |
741 | } | |
673a394b | 742 | |
76c1dec1 CW |
743 | ret = i915_mutex_lock_interruptible(dev); |
744 | if (ret) | |
745 | goto out_unpin_pages; | |
746 | ||
3de09aa3 EA |
747 | ret = i915_gem_object_pin(obj, 0); |
748 | if (ret) | |
749 | goto out_unlock; | |
750 | ||
751 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
752 | if (ret) | |
753 | goto out_unpin_object; | |
754 | ||
23010e43 | 755 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
756 | offset = obj_priv->gtt_offset + args->offset; |
757 | ||
758 | while (remain > 0) { | |
759 | /* Operation in this page | |
760 | * | |
761 | * gtt_page_base = page offset within aperture | |
762 | * gtt_page_offset = offset within page in aperture | |
763 | * data_page_index = page number in get_user_pages return | |
764 | * data_page_offset = offset with data_page_index page. | |
765 | * page_length = bytes to copy for this page | |
766 | */ | |
767 | gtt_page_base = offset & PAGE_MASK; | |
768 | gtt_page_offset = offset & ~PAGE_MASK; | |
769 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
770 | data_page_offset = data_ptr & ~PAGE_MASK; | |
771 | ||
772 | page_length = remain; | |
773 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
774 | page_length = PAGE_SIZE - gtt_page_offset; | |
775 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
776 | page_length = PAGE_SIZE - data_page_offset; | |
777 | ||
ab34c226 CW |
778 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
779 | gtt_page_base, gtt_page_offset, | |
780 | user_pages[data_page_index], | |
781 | data_page_offset, | |
782 | page_length); | |
3de09aa3 EA |
783 | |
784 | remain -= page_length; | |
785 | offset += page_length; | |
786 | data_ptr += page_length; | |
787 | } | |
788 | ||
789 | out_unpin_object: | |
790 | i915_gem_object_unpin(obj); | |
791 | out_unlock: | |
792 | mutex_unlock(&dev->struct_mutex); | |
793 | out_unpin_pages: | |
794 | for (i = 0; i < pinned_pages; i++) | |
795 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 796 | drm_free_large(user_pages); |
3de09aa3 EA |
797 | |
798 | return ret; | |
799 | } | |
800 | ||
40123c1f EA |
801 | /** |
802 | * This is the fast shmem pwrite path, which attempts to directly | |
803 | * copy_from_user into the kmapped pages backing the object. | |
804 | */ | |
3043c60c | 805 | static int |
40123c1f EA |
806 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
807 | struct drm_i915_gem_pwrite *args, | |
808 | struct drm_file *file_priv) | |
673a394b | 809 | { |
23010e43 | 810 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
811 | ssize_t remain; |
812 | loff_t offset, page_base; | |
813 | char __user *user_data; | |
814 | int page_offset, page_length; | |
673a394b | 815 | int ret; |
40123c1f EA |
816 | |
817 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
818 | remain = args->size; | |
673a394b | 819 | |
76c1dec1 CW |
820 | ret = i915_mutex_lock_interruptible(dev); |
821 | if (ret) | |
822 | return ret; | |
673a394b | 823 | |
4bdadb97 | 824 | ret = i915_gem_object_get_pages(obj, 0); |
40123c1f EA |
825 | if (ret != 0) |
826 | goto fail_unlock; | |
673a394b | 827 | |
e47c68e9 | 828 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
829 | if (ret != 0) |
830 | goto fail_put_pages; | |
831 | ||
23010e43 | 832 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
833 | offset = args->offset; |
834 | obj_priv->dirty = 1; | |
835 | ||
836 | while (remain > 0) { | |
837 | /* Operation in this page | |
838 | * | |
839 | * page_base = page offset within aperture | |
840 | * page_offset = offset within page | |
841 | * page_length = bytes to copy for this page | |
842 | */ | |
843 | page_base = (offset & ~(PAGE_SIZE-1)); | |
844 | page_offset = offset & (PAGE_SIZE-1); | |
845 | page_length = remain; | |
846 | if ((page_offset + remain) > PAGE_SIZE) | |
847 | page_length = PAGE_SIZE - page_offset; | |
848 | ||
849 | ret = fast_shmem_write(obj_priv->pages, | |
850 | page_base, page_offset, | |
851 | user_data, page_length); | |
852 | if (ret) | |
853 | goto fail_put_pages; | |
854 | ||
855 | remain -= page_length; | |
856 | user_data += page_length; | |
857 | offset += page_length; | |
858 | } | |
859 | ||
860 | fail_put_pages: | |
861 | i915_gem_object_put_pages(obj); | |
862 | fail_unlock: | |
863 | mutex_unlock(&dev->struct_mutex); | |
864 | ||
865 | return ret; | |
866 | } | |
867 | ||
868 | /** | |
869 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
870 | * the memory and maps it using kmap_atomic for copying. | |
871 | * | |
872 | * This avoids taking mmap_sem for faulting on the user's address while the | |
873 | * struct_mutex is held. | |
874 | */ | |
875 | static int | |
876 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
877 | struct drm_i915_gem_pwrite *args, | |
878 | struct drm_file *file_priv) | |
879 | { | |
23010e43 | 880 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
881 | struct mm_struct *mm = current->mm; |
882 | struct page **user_pages; | |
883 | ssize_t remain; | |
884 | loff_t offset, pinned_pages, i; | |
885 | loff_t first_data_page, last_data_page, num_pages; | |
886 | int shmem_page_index, shmem_page_offset; | |
887 | int data_page_index, data_page_offset; | |
888 | int page_length; | |
889 | int ret; | |
890 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 891 | int do_bit17_swizzling; |
40123c1f EA |
892 | |
893 | remain = args->size; | |
894 | ||
895 | /* Pin the user pages containing the data. We can't fault while | |
896 | * holding the struct mutex, and all of the pwrite implementations | |
897 | * want to hold it while dereferencing the user data. | |
898 | */ | |
899 | first_data_page = data_ptr / PAGE_SIZE; | |
900 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
901 | num_pages = last_data_page - first_data_page + 1; | |
902 | ||
8e7d2b2c | 903 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
904 | if (user_pages == NULL) |
905 | return -ENOMEM; | |
906 | ||
907 | down_read(&mm->mmap_sem); | |
908 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
909 | num_pages, 0, 0, user_pages, NULL); | |
910 | up_read(&mm->mmap_sem); | |
911 | if (pinned_pages < num_pages) { | |
912 | ret = -EFAULT; | |
913 | goto fail_put_user_pages; | |
673a394b EA |
914 | } |
915 | ||
280b713b EA |
916 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
917 | ||
76c1dec1 CW |
918 | ret = i915_mutex_lock_interruptible(dev); |
919 | if (ret) | |
920 | goto fail_put_user_pages; | |
40123c1f | 921 | |
07f73f69 CW |
922 | ret = i915_gem_object_get_pages_or_evict(obj); |
923 | if (ret) | |
40123c1f EA |
924 | goto fail_unlock; |
925 | ||
926 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
927 | if (ret != 0) | |
928 | goto fail_put_pages; | |
929 | ||
23010e43 | 930 | obj_priv = to_intel_bo(obj); |
673a394b | 931 | offset = args->offset; |
40123c1f | 932 | obj_priv->dirty = 1; |
673a394b | 933 | |
40123c1f EA |
934 | while (remain > 0) { |
935 | /* Operation in this page | |
936 | * | |
937 | * shmem_page_index = page number within shmem file | |
938 | * shmem_page_offset = offset within page in shmem file | |
939 | * data_page_index = page number in get_user_pages return | |
940 | * data_page_offset = offset with data_page_index page. | |
941 | * page_length = bytes to copy for this page | |
942 | */ | |
943 | shmem_page_index = offset / PAGE_SIZE; | |
944 | shmem_page_offset = offset & ~PAGE_MASK; | |
945 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
946 | data_page_offset = data_ptr & ~PAGE_MASK; | |
947 | ||
948 | page_length = remain; | |
949 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
950 | page_length = PAGE_SIZE - shmem_page_offset; | |
951 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
952 | page_length = PAGE_SIZE - data_page_offset; | |
953 | ||
280b713b | 954 | if (do_bit17_swizzling) { |
99a03df5 | 955 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
956 | shmem_page_offset, |
957 | user_pages[data_page_index], | |
958 | data_page_offset, | |
99a03df5 CW |
959 | page_length, |
960 | 0); | |
961 | } else { | |
962 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
963 | shmem_page_offset, | |
964 | user_pages[data_page_index], | |
965 | data_page_offset, | |
966 | page_length); | |
280b713b | 967 | } |
40123c1f EA |
968 | |
969 | remain -= page_length; | |
970 | data_ptr += page_length; | |
971 | offset += page_length; | |
673a394b EA |
972 | } |
973 | ||
40123c1f EA |
974 | fail_put_pages: |
975 | i915_gem_object_put_pages(obj); | |
976 | fail_unlock: | |
673a394b | 977 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
978 | fail_put_user_pages: |
979 | for (i = 0; i < pinned_pages; i++) | |
980 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 981 | drm_free_large(user_pages); |
673a394b | 982 | |
40123c1f | 983 | return ret; |
673a394b EA |
984 | } |
985 | ||
986 | /** | |
987 | * Writes data to the object referenced by handle. | |
988 | * | |
989 | * On error, the contents of the buffer that were to be modified are undefined. | |
990 | */ | |
991 | int | |
992 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
993 | struct drm_file *file_priv) | |
994 | { | |
995 | struct drm_i915_gem_pwrite *args = data; | |
996 | struct drm_gem_object *obj; | |
997 | struct drm_i915_gem_object *obj_priv; | |
998 | int ret = 0; | |
999 | ||
1000 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1001 | if (obj == NULL) | |
bf79cb91 | 1002 | return -ENOENT; |
23010e43 | 1003 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1004 | |
1005 | /* Bounds check destination. | |
1006 | * | |
1007 | * XXX: This could use review for overflow issues... | |
1008 | */ | |
1009 | if (args->offset > obj->size || args->size > obj->size || | |
1010 | args->offset + args->size > obj->size) { | |
bc9025bd | 1011 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1012 | return -EINVAL; |
1013 | } | |
1014 | ||
1015 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1016 | * it would end up going through the fenced access, and we'll get | |
1017 | * different detiling behavior between reading and writing. | |
1018 | * pread/pwrite currently are reading and writing from the CPU | |
1019 | * perspective, requiring manual detiling by the client. | |
1020 | */ | |
71acb5eb DA |
1021 | if (obj_priv->phys_obj) |
1022 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
1023 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
9b8c4a0b CW |
1024 | dev->gtt_total != 0 && |
1025 | obj->write_domain != I915_GEM_DOMAIN_CPU) { | |
3de09aa3 EA |
1026 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
1027 | if (ret == -EFAULT) { | |
1028 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
1029 | file_priv); | |
1030 | } | |
280b713b EA |
1031 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
1032 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
1033 | } else { |
1034 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
1035 | if (ret == -EFAULT) { | |
1036 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
1037 | file_priv); | |
1038 | } | |
1039 | } | |
673a394b EA |
1040 | |
1041 | #if WATCH_PWRITE | |
1042 | if (ret) | |
1043 | DRM_INFO("pwrite failed %d\n", ret); | |
1044 | #endif | |
1045 | ||
bc9025bd | 1046 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1047 | |
1048 | return ret; | |
1049 | } | |
1050 | ||
1051 | /** | |
2ef7eeaa EA |
1052 | * Called when user space prepares to use an object with the CPU, either |
1053 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1054 | */ |
1055 | int | |
1056 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1057 | struct drm_file *file_priv) | |
1058 | { | |
a09ba7fa | 1059 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1060 | struct drm_i915_gem_set_domain *args = data; |
1061 | struct drm_gem_object *obj; | |
652c393a | 1062 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1063 | uint32_t read_domains = args->read_domains; |
1064 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1065 | int ret; |
1066 | ||
1067 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1068 | return -ENODEV; | |
1069 | ||
2ef7eeaa | 1070 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1071 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1072 | return -EINVAL; |
1073 | ||
21d509e3 | 1074 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1075 | return -EINVAL; |
1076 | ||
1077 | /* Having something in the write domain implies it's in the read | |
1078 | * domain, and only that read domain. Enforce that in the request. | |
1079 | */ | |
1080 | if (write_domain != 0 && read_domains != write_domain) | |
1081 | return -EINVAL; | |
1082 | ||
673a394b EA |
1083 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1084 | if (obj == NULL) | |
bf79cb91 | 1085 | return -ENOENT; |
23010e43 | 1086 | obj_priv = to_intel_bo(obj); |
673a394b | 1087 | |
76c1dec1 CW |
1088 | ret = i915_mutex_lock_interruptible(dev); |
1089 | if (ret) { | |
1090 | drm_gem_object_unreference_unlocked(obj); | |
1091 | return ret; | |
1092 | } | |
652c393a JB |
1093 | |
1094 | intel_mark_busy(dev, obj); | |
1095 | ||
2ef7eeaa EA |
1096 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1097 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1098 | |
a09ba7fa EA |
1099 | /* Update the LRU on the fence for the CPU access that's |
1100 | * about to occur. | |
1101 | */ | |
1102 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1103 | struct drm_i915_fence_reg *reg = |
1104 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1105 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1106 | &dev_priv->mm.fence_list); |
1107 | } | |
1108 | ||
02354392 EA |
1109 | /* Silently promote "you're not bound, there was nothing to do" |
1110 | * to success, since the client was just asking us to | |
1111 | * make sure everything was done. | |
1112 | */ | |
1113 | if (ret == -EINVAL) | |
1114 | ret = 0; | |
2ef7eeaa | 1115 | } else { |
e47c68e9 | 1116 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1117 | } |
1118 | ||
7d1c4804 CW |
1119 | /* Maintain LRU order of "inactive" objects */ |
1120 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
1121 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1122 | ||
673a394b EA |
1123 | drm_gem_object_unreference(obj); |
1124 | mutex_unlock(&dev->struct_mutex); | |
1125 | return ret; | |
1126 | } | |
1127 | ||
1128 | /** | |
1129 | * Called when user space has done writes to this buffer | |
1130 | */ | |
1131 | int | |
1132 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1133 | struct drm_file *file_priv) | |
1134 | { | |
1135 | struct drm_i915_gem_sw_finish *args = data; | |
1136 | struct drm_gem_object *obj; | |
673a394b EA |
1137 | int ret = 0; |
1138 | ||
1139 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1140 | return -ENODEV; | |
1141 | ||
673a394b | 1142 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
76c1dec1 | 1143 | if (obj == NULL) |
bf79cb91 | 1144 | return -ENOENT; |
76c1dec1 CW |
1145 | |
1146 | ret = i915_mutex_lock_interruptible(dev); | |
1147 | if (ret) { | |
1148 | drm_gem_object_unreference_unlocked(obj); | |
1149 | return ret; | |
673a394b EA |
1150 | } |
1151 | ||
673a394b | 1152 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1153 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1154 | i915_gem_object_flush_cpu_write_domain(obj); |
1155 | ||
673a394b EA |
1156 | drm_gem_object_unreference(obj); |
1157 | mutex_unlock(&dev->struct_mutex); | |
1158 | return ret; | |
1159 | } | |
1160 | ||
1161 | /** | |
1162 | * Maps the contents of an object, returning the address it is mapped | |
1163 | * into. | |
1164 | * | |
1165 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1166 | * imply a ref on the object itself. | |
1167 | */ | |
1168 | int | |
1169 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1170 | struct drm_file *file_priv) | |
1171 | { | |
1172 | struct drm_i915_gem_mmap *args = data; | |
1173 | struct drm_gem_object *obj; | |
1174 | loff_t offset; | |
1175 | unsigned long addr; | |
1176 | ||
1177 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1178 | return -ENODEV; | |
1179 | ||
1180 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1181 | if (obj == NULL) | |
bf79cb91 | 1182 | return -ENOENT; |
673a394b EA |
1183 | |
1184 | offset = args->offset; | |
1185 | ||
1186 | down_write(¤t->mm->mmap_sem); | |
1187 | addr = do_mmap(obj->filp, 0, args->size, | |
1188 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1189 | args->offset); | |
1190 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1191 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1192 | if (IS_ERR((void *)addr)) |
1193 | return addr; | |
1194 | ||
1195 | args->addr_ptr = (uint64_t) addr; | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
de151cf6 JB |
1200 | /** |
1201 | * i915_gem_fault - fault a page into the GTT | |
1202 | * vma: VMA in question | |
1203 | * vmf: fault info | |
1204 | * | |
1205 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1206 | * from userspace. The fault handler takes care of binding the object to | |
1207 | * the GTT (if needed), allocating and programming a fence register (again, | |
1208 | * only if needed based on whether the old reg is still valid or the object | |
1209 | * is tiled) and inserting a new PTE into the faulting process. | |
1210 | * | |
1211 | * Note that the faulting process may involve evicting existing objects | |
1212 | * from the GTT and/or fence registers to make room. So performance may | |
1213 | * suffer if the GTT working set is large or there are few fence registers | |
1214 | * left. | |
1215 | */ | |
1216 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1217 | { | |
1218 | struct drm_gem_object *obj = vma->vm_private_data; | |
1219 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1220 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1221 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1222 | pgoff_t page_offset; |
1223 | unsigned long pfn; | |
1224 | int ret = 0; | |
0f973f27 | 1225 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1226 | |
1227 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1228 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1229 | PAGE_SHIFT; | |
1230 | ||
1231 | /* Now bind it into the GTT if needed */ | |
1232 | mutex_lock(&dev->struct_mutex); | |
1233 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1234 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1235 | if (ret) |
1236 | goto unlock; | |
07f4f3e8 | 1237 | |
07f4f3e8 | 1238 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1239 | if (ret) |
1240 | goto unlock; | |
de151cf6 JB |
1241 | } |
1242 | ||
1243 | /* Need a new fence register? */ | |
a09ba7fa | 1244 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1245 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1246 | if (ret) |
1247 | goto unlock; | |
d9ddcb96 | 1248 | } |
de151cf6 | 1249 | |
7d1c4804 CW |
1250 | if (i915_gem_object_is_inactive(obj_priv)) |
1251 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1252 | ||
de151cf6 JB |
1253 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1254 | page_offset; | |
1255 | ||
1256 | /* Finally, remap it using the new GTT offset */ | |
1257 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1258 | unlock: |
de151cf6 JB |
1259 | mutex_unlock(&dev->struct_mutex); |
1260 | ||
1261 | switch (ret) { | |
c715089f CW |
1262 | case 0: |
1263 | case -ERESTARTSYS: | |
1264 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1265 | case -ENOMEM: |
1266 | case -EAGAIN: | |
1267 | return VM_FAULT_OOM; | |
de151cf6 | 1268 | default: |
c715089f | 1269 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1270 | } |
1271 | } | |
1272 | ||
1273 | /** | |
1274 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1275 | * @obj: obj in question | |
1276 | * | |
1277 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1278 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1279 | * up the object based on the offset and sets up the various memory mapping | |
1280 | * structures. | |
1281 | * | |
1282 | * This routine allocates and attaches a fake offset for @obj. | |
1283 | */ | |
1284 | static int | |
1285 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1286 | { | |
1287 | struct drm_device *dev = obj->dev; | |
1288 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1289 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1290 | struct drm_map_list *list; |
f77d390c | 1291 | struct drm_local_map *map; |
de151cf6 JB |
1292 | int ret = 0; |
1293 | ||
1294 | /* Set the object up for mmap'ing */ | |
1295 | list = &obj->map_list; | |
9a298b2a | 1296 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1297 | if (!list->map) |
1298 | return -ENOMEM; | |
1299 | ||
1300 | map = list->map; | |
1301 | map->type = _DRM_GEM; | |
1302 | map->size = obj->size; | |
1303 | map->handle = obj; | |
1304 | ||
1305 | /* Get a DRM GEM mmap offset allocated... */ | |
1306 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1307 | obj->size / PAGE_SIZE, 0, 0); | |
1308 | if (!list->file_offset_node) { | |
1309 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1310 | ret = -ENOSPC; |
de151cf6 JB |
1311 | goto out_free_list; |
1312 | } | |
1313 | ||
1314 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1315 | obj->size / PAGE_SIZE, 0); | |
1316 | if (!list->file_offset_node) { | |
1317 | ret = -ENOMEM; | |
1318 | goto out_free_list; | |
1319 | } | |
1320 | ||
1321 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1322 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1323 | if (ret) { | |
de151cf6 JB |
1324 | DRM_ERROR("failed to add to map hash\n"); |
1325 | goto out_free_mm; | |
1326 | } | |
1327 | ||
1328 | /* By now we should be all set, any drm_mmap request on the offset | |
1329 | * below will get to our mmap & fault handler */ | |
1330 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1331 | ||
1332 | return 0; | |
1333 | ||
1334 | out_free_mm: | |
1335 | drm_mm_put_block(list->file_offset_node); | |
1336 | out_free_list: | |
9a298b2a | 1337 | kfree(list->map); |
de151cf6 JB |
1338 | |
1339 | return ret; | |
1340 | } | |
1341 | ||
901782b2 CW |
1342 | /** |
1343 | * i915_gem_release_mmap - remove physical page mappings | |
1344 | * @obj: obj in question | |
1345 | * | |
af901ca1 | 1346 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1347 | * relinquish ownership of the pages back to the system. |
1348 | * | |
1349 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1350 | * object through the GTT and then lose the fence register due to | |
1351 | * resource pressure. Similarly if the object has been moved out of the | |
1352 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1353 | * mapping will then trigger a page fault on the next user access, allowing | |
1354 | * fixup by i915_gem_fault(). | |
1355 | */ | |
d05ca301 | 1356 | void |
901782b2 CW |
1357 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1358 | { | |
1359 | struct drm_device *dev = obj->dev; | |
23010e43 | 1360 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1361 | |
1362 | if (dev->dev_mapping) | |
1363 | unmap_mapping_range(dev->dev_mapping, | |
1364 | obj_priv->mmap_offset, obj->size, 1); | |
1365 | } | |
1366 | ||
ab00b3e5 JB |
1367 | static void |
1368 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1369 | { | |
1370 | struct drm_device *dev = obj->dev; | |
23010e43 | 1371 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1372 | struct drm_gem_mm *mm = dev->mm_private; |
1373 | struct drm_map_list *list; | |
1374 | ||
1375 | list = &obj->map_list; | |
1376 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1377 | ||
1378 | if (list->file_offset_node) { | |
1379 | drm_mm_put_block(list->file_offset_node); | |
1380 | list->file_offset_node = NULL; | |
1381 | } | |
1382 | ||
1383 | if (list->map) { | |
9a298b2a | 1384 | kfree(list->map); |
ab00b3e5 JB |
1385 | list->map = NULL; |
1386 | } | |
1387 | ||
1388 | obj_priv->mmap_offset = 0; | |
1389 | } | |
1390 | ||
de151cf6 JB |
1391 | /** |
1392 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1393 | * @obj: object to check | |
1394 | * | |
1395 | * Return the required GTT alignment for an object, taking into account | |
1396 | * potential fence register mapping if needed. | |
1397 | */ | |
1398 | static uint32_t | |
1399 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1400 | { | |
1401 | struct drm_device *dev = obj->dev; | |
23010e43 | 1402 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1403 | int start, i; |
1404 | ||
1405 | /* | |
1406 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1407 | * if a fence register is needed for the object. | |
1408 | */ | |
a6c45cf0 | 1409 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1410 | return 4096; |
1411 | ||
1412 | /* | |
1413 | * Previous chips need to be aligned to the size of the smallest | |
1414 | * fence register that can contain the object. | |
1415 | */ | |
a6c45cf0 | 1416 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1417 | start = 1024*1024; |
1418 | else | |
1419 | start = 512*1024; | |
1420 | ||
1421 | for (i = start; i < obj->size; i <<= 1) | |
1422 | ; | |
1423 | ||
1424 | return i; | |
1425 | } | |
1426 | ||
1427 | /** | |
1428 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1429 | * @dev: DRM device | |
1430 | * @data: GTT mapping ioctl data | |
1431 | * @file_priv: GEM object info | |
1432 | * | |
1433 | * Simply returns the fake offset to userspace so it can mmap it. | |
1434 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1435 | * up so we can get faults in the handler above. | |
1436 | * | |
1437 | * The fault handler will take care of binding the object into the GTT | |
1438 | * (since it may have been evicted to make room for something), allocating | |
1439 | * a fence register, and mapping the appropriate aperture address into | |
1440 | * userspace. | |
1441 | */ | |
1442 | int | |
1443 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1444 | struct drm_file *file_priv) | |
1445 | { | |
1446 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1447 | struct drm_gem_object *obj; |
1448 | struct drm_i915_gem_object *obj_priv; | |
1449 | int ret; | |
1450 | ||
1451 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1452 | return -ENODEV; | |
1453 | ||
1454 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1455 | if (obj == NULL) | |
bf79cb91 | 1456 | return -ENOENT; |
de151cf6 | 1457 | |
76c1dec1 CW |
1458 | ret = i915_mutex_lock_interruptible(dev); |
1459 | if (ret) { | |
1460 | drm_gem_object_unreference_unlocked(obj); | |
1461 | return ret; | |
1462 | } | |
de151cf6 | 1463 | |
23010e43 | 1464 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1465 | |
ab18282d CW |
1466 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1467 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1468 | drm_gem_object_unreference(obj); | |
1469 | mutex_unlock(&dev->struct_mutex); | |
1470 | return -EINVAL; | |
1471 | } | |
1472 | ||
1473 | ||
de151cf6 JB |
1474 | if (!obj_priv->mmap_offset) { |
1475 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1476 | if (ret) { |
1477 | drm_gem_object_unreference(obj); | |
1478 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1479 | return ret; |
13af1062 | 1480 | } |
de151cf6 JB |
1481 | } |
1482 | ||
1483 | args->offset = obj_priv->mmap_offset; | |
1484 | ||
de151cf6 JB |
1485 | /* |
1486 | * Pull it into the GTT so that we have a page list (makes the | |
1487 | * initial fault faster and any subsequent flushing possible). | |
1488 | */ | |
1489 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1490 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1491 | if (ret) { |
1492 | drm_gem_object_unreference(obj); | |
1493 | mutex_unlock(&dev->struct_mutex); | |
1494 | return ret; | |
1495 | } | |
de151cf6 JB |
1496 | } |
1497 | ||
1498 | drm_gem_object_unreference(obj); | |
1499 | mutex_unlock(&dev->struct_mutex); | |
1500 | ||
1501 | return 0; | |
1502 | } | |
1503 | ||
6911a9b8 | 1504 | void |
856fa198 | 1505 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1506 | { |
23010e43 | 1507 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1508 | int page_count = obj->size / PAGE_SIZE; |
1509 | int i; | |
1510 | ||
856fa198 | 1511 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1512 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1513 | |
856fa198 EA |
1514 | if (--obj_priv->pages_refcount != 0) |
1515 | return; | |
673a394b | 1516 | |
280b713b EA |
1517 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1518 | i915_gem_object_save_bit_17_swizzle(obj); | |
1519 | ||
3ef94daa | 1520 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1521 | obj_priv->dirty = 0; |
3ef94daa CW |
1522 | |
1523 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1524 | if (obj_priv->dirty) |
1525 | set_page_dirty(obj_priv->pages[i]); | |
1526 | ||
1527 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1528 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1529 | |
1530 | page_cache_release(obj_priv->pages[i]); | |
1531 | } | |
673a394b EA |
1532 | obj_priv->dirty = 0; |
1533 | ||
8e7d2b2c | 1534 | drm_free_large(obj_priv->pages); |
856fa198 | 1535 | obj_priv->pages = NULL; |
673a394b EA |
1536 | } |
1537 | ||
a56ba56c CW |
1538 | static uint32_t |
1539 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1540 | struct intel_ring_buffer *ring) | |
1541 | { | |
1542 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1543 | ||
1544 | ring->outstanding_lazy_request = true; | |
1545 | return dev_priv->next_seqno; | |
1546 | } | |
1547 | ||
673a394b | 1548 | static void |
617dbe27 | 1549 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1550 | struct intel_ring_buffer *ring) |
673a394b | 1551 | { |
a56ba56c | 1552 | struct drm_device *dev = obj->dev; |
23010e43 | 1553 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1554 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1555 | |
852835f3 ZN |
1556 | BUG_ON(ring == NULL); |
1557 | obj_priv->ring = ring; | |
673a394b EA |
1558 | |
1559 | /* Add a reference if we're newly entering the active list. */ | |
1560 | if (!obj_priv->active) { | |
1561 | drm_gem_object_reference(obj); | |
1562 | obj_priv->active = 1; | |
1563 | } | |
e35a41de | 1564 | |
673a394b | 1565 | /* Move from whatever list we were on to the tail of execution. */ |
852835f3 | 1566 | list_move_tail(&obj_priv->list, &ring->active_list); |
a56ba56c | 1567 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1568 | } |
1569 | ||
ce44b0ea EA |
1570 | static void |
1571 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1572 | { | |
1573 | struct drm_device *dev = obj->dev; | |
1574 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1575 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1576 | |
1577 | BUG_ON(!obj_priv->active); | |
1578 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1579 | obj_priv->last_rendering_seqno = 0; | |
1580 | } | |
673a394b | 1581 | |
963b4836 CW |
1582 | /* Immediately discard the backing storage */ |
1583 | static void | |
1584 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1585 | { | |
23010e43 | 1586 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1587 | struct inode *inode; |
963b4836 | 1588 | |
ae9fed6b CW |
1589 | /* Our goal here is to return as much of the memory as |
1590 | * is possible back to the system as we are called from OOM. | |
1591 | * To do this we must instruct the shmfs to drop all of its | |
1592 | * backing pages, *now*. Here we mirror the actions taken | |
1593 | * when by shmem_delete_inode() to release the backing store. | |
1594 | */ | |
bb6baf76 | 1595 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1596 | truncate_inode_pages(inode->i_mapping, 0); |
1597 | if (inode->i_op->truncate_range) | |
1598 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1599 | |
1600 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1601 | } |
1602 | ||
1603 | static inline int | |
1604 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1605 | { | |
1606 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1607 | } | |
1608 | ||
673a394b EA |
1609 | static void |
1610 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1611 | { | |
1612 | struct drm_device *dev = obj->dev; | |
1613 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1614 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1615 | |
673a394b | 1616 | if (obj_priv->pin_count != 0) |
f13d3f73 | 1617 | list_move_tail(&obj_priv->list, &dev_priv->mm.pinned_list); |
673a394b EA |
1618 | else |
1619 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1620 | ||
99fcb766 DV |
1621 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1622 | ||
ce44b0ea | 1623 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1624 | obj_priv->ring = NULL; |
673a394b EA |
1625 | if (obj_priv->active) { |
1626 | obj_priv->active = 0; | |
1627 | drm_gem_object_unreference(obj); | |
1628 | } | |
23bc5982 | 1629 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1630 | } |
1631 | ||
9220434a | 1632 | static void |
63560396 | 1633 | i915_gem_process_flushing_list(struct drm_device *dev, |
8a1a49f9 | 1634 | uint32_t flush_domains, |
852835f3 | 1635 | struct intel_ring_buffer *ring) |
63560396 DV |
1636 | { |
1637 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1638 | struct drm_i915_gem_object *obj_priv, *next; | |
1639 | ||
1640 | list_for_each_entry_safe(obj_priv, next, | |
1641 | &dev_priv->mm.gpu_write_list, | |
1642 | gpu_write_list) { | |
a8089e84 | 1643 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1644 | |
2b6efaa4 CW |
1645 | if (obj->write_domain & flush_domains && |
1646 | obj_priv->ring == ring) { | |
63560396 DV |
1647 | uint32_t old_write_domain = obj->write_domain; |
1648 | ||
1649 | obj->write_domain = 0; | |
1650 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1651 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1652 | |
1653 | /* update the fence lru list */ | |
007cc8ac DV |
1654 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1655 | struct drm_i915_fence_reg *reg = | |
1656 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1657 | list_move_tail(®->lru_list, | |
63560396 | 1658 | &dev_priv->mm.fence_list); |
007cc8ac | 1659 | } |
63560396 DV |
1660 | |
1661 | trace_i915_gem_object_change_domain(obj, | |
1662 | obj->read_domains, | |
1663 | old_write_domain); | |
1664 | } | |
1665 | } | |
1666 | } | |
8187a2b7 | 1667 | |
5a5a0c64 | 1668 | uint32_t |
8a1a49f9 | 1669 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1670 | struct drm_file *file, |
8dc5d147 | 1671 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1672 | struct intel_ring_buffer *ring) |
673a394b EA |
1673 | { |
1674 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1675 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1676 | uint32_t seqno; |
1677 | int was_empty; | |
673a394b | 1678 | |
f787a5f5 CW |
1679 | if (file != NULL) |
1680 | file_priv = file->driver_priv; | |
b962442e | 1681 | |
8dc5d147 CW |
1682 | if (request == NULL) { |
1683 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1684 | if (request == NULL) | |
1685 | return 0; | |
1686 | } | |
673a394b | 1687 | |
f787a5f5 | 1688 | seqno = ring->add_request(dev, ring, 0); |
a56ba56c | 1689 | ring->outstanding_lazy_request = false; |
673a394b EA |
1690 | |
1691 | request->seqno = seqno; | |
852835f3 | 1692 | request->ring = ring; |
673a394b | 1693 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1694 | was_empty = list_empty(&ring->request_list); |
1695 | list_add_tail(&request->list, &ring->request_list); | |
1696 | ||
f787a5f5 | 1697 | if (file_priv) { |
1c25595f | 1698 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1699 | request->file_priv = file_priv; |
b962442e | 1700 | list_add_tail(&request->client_list, |
f787a5f5 | 1701 | &file_priv->mm.request_list); |
1c25595f | 1702 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1703 | } |
673a394b | 1704 | |
f65d9421 | 1705 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1706 | mod_timer(&dev_priv->hangcheck_timer, |
1707 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1708 | if (was_empty) |
b3b079db CW |
1709 | queue_delayed_work(dev_priv->wq, |
1710 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1711 | } |
673a394b EA |
1712 | return seqno; |
1713 | } | |
1714 | ||
1715 | /** | |
1716 | * Command execution barrier | |
1717 | * | |
1718 | * Ensures that all commands in the ring are finished | |
1719 | * before signalling the CPU | |
1720 | */ | |
8a1a49f9 | 1721 | static void |
852835f3 | 1722 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1723 | { |
673a394b | 1724 | uint32_t flush_domains = 0; |
673a394b EA |
1725 | |
1726 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1727 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1728 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 ZN |
1729 | |
1730 | ring->flush(dev, ring, | |
1731 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1732 | } |
1733 | ||
f787a5f5 CW |
1734 | static inline void |
1735 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1736 | { |
1c25595f CW |
1737 | struct drm_i915_file_private *file_priv = request->file_priv; |
1738 | ||
1739 | if (!file_priv) | |
1740 | return; | |
1741 | ||
1742 | spin_lock(&file_priv->mm.lock); | |
1743 | list_del(&request->client_list); | |
1744 | request->file_priv = NULL; | |
1745 | spin_unlock(&file_priv->mm.lock); | |
673a394b EA |
1746 | } |
1747 | ||
dfaae392 CW |
1748 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1749 | struct intel_ring_buffer *ring) | |
9375e446 | 1750 | { |
dfaae392 CW |
1751 | while (!list_empty(&ring->request_list)) { |
1752 | struct drm_i915_gem_request *request; | |
9375e446 | 1753 | |
dfaae392 CW |
1754 | request = list_first_entry(&ring->request_list, |
1755 | struct drm_i915_gem_request, | |
1756 | list); | |
1757 | ||
1758 | list_del(&request->list); | |
f787a5f5 | 1759 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1760 | kfree(request); |
1761 | } | |
1762 | ||
1763 | while (!list_empty(&ring->active_list)) { | |
9375e446 CW |
1764 | struct drm_i915_gem_object *obj_priv; |
1765 | ||
dfaae392 | 1766 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 CW |
1767 | struct drm_i915_gem_object, |
1768 | list); | |
1769 | ||
1770 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1771 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 CW |
1772 | i915_gem_object_move_to_inactive(&obj_priv->base); |
1773 | } | |
1774 | } | |
1775 | ||
dfaae392 | 1776 | void i915_gem_reset_lists(struct drm_device *dev) |
77f01230 CW |
1777 | { |
1778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1779 | struct drm_i915_gem_object *obj_priv; | |
1780 | ||
dfaae392 CW |
1781 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
1782 | if (HAS_BSD(dev)) | |
1783 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); | |
1784 | ||
1785 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1786 | * to be lost on reset along with the data, so simply move the | |
1787 | * lost bo to the inactive list. | |
1788 | */ | |
1789 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1790 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1791 | struct drm_i915_gem_object, | |
1792 | list); | |
1793 | ||
1794 | obj_priv->base.write_domain = 0; | |
1795 | list_del_init(&obj_priv->gpu_write_list); | |
1796 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1797 | } | |
1798 | ||
1799 | /* Move everything out of the GPU domains to ensure we do any | |
1800 | * necessary invalidation upon reuse. | |
1801 | */ | |
77f01230 CW |
1802 | list_for_each_entry(obj_priv, |
1803 | &dev_priv->mm.inactive_list, | |
1804 | list) | |
1805 | { | |
1806 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1807 | } | |
1808 | } | |
1809 | ||
673a394b EA |
1810 | /** |
1811 | * This function clears the request list as sequence numbers are passed. | |
1812 | */ | |
b09a1fec CW |
1813 | static void |
1814 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1815 | struct intel_ring_buffer *ring) | |
673a394b EA |
1816 | { |
1817 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1818 | uint32_t seqno; | |
1819 | ||
b84d5f0c CW |
1820 | if (!ring->status_page.page_addr || |
1821 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1822 | return; |
1823 | ||
23bc5982 CW |
1824 | WARN_ON(i915_verify_lists(dev)); |
1825 | ||
f787a5f5 | 1826 | seqno = ring->get_seqno(dev, ring); |
852835f3 | 1827 | while (!list_empty(&ring->request_list)) { |
673a394b | 1828 | struct drm_i915_gem_request *request; |
673a394b | 1829 | |
852835f3 | 1830 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1831 | struct drm_i915_gem_request, |
1832 | list); | |
673a394b | 1833 | |
dfaae392 | 1834 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1835 | break; |
1836 | ||
1837 | trace_i915_gem_request_retire(dev, request->seqno); | |
1838 | ||
1839 | list_del(&request->list); | |
f787a5f5 | 1840 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1841 | kfree(request); |
1842 | } | |
1843 | ||
1844 | /* Move any buffers on the active list that are no longer referenced | |
1845 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1846 | */ | |
1847 | while (!list_empty(&ring->active_list)) { | |
1848 | struct drm_gem_object *obj; | |
1849 | struct drm_i915_gem_object *obj_priv; | |
1850 | ||
1851 | obj_priv = list_first_entry(&ring->active_list, | |
1852 | struct drm_i915_gem_object, | |
1853 | list); | |
673a394b | 1854 | |
dfaae392 | 1855 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1856 | break; |
b84d5f0c CW |
1857 | |
1858 | obj = &obj_priv->base; | |
b84d5f0c CW |
1859 | if (obj->write_domain != 0) |
1860 | i915_gem_object_move_to_flushing(obj); | |
1861 | else | |
1862 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1863 | } |
9d34e5db CW |
1864 | |
1865 | if (unlikely (dev_priv->trace_irq_seqno && | |
1866 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 | 1867 | ring->user_irq_put(dev, ring); |
9d34e5db CW |
1868 | dev_priv->trace_irq_seqno = 0; |
1869 | } | |
23bc5982 CW |
1870 | |
1871 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1872 | } |
1873 | ||
b09a1fec CW |
1874 | void |
1875 | i915_gem_retire_requests(struct drm_device *dev) | |
1876 | { | |
1877 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1878 | ||
be72615b CW |
1879 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1880 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1881 | ||
1882 | /* We must be careful that during unbind() we do not | |
1883 | * accidentally infinitely recurse into retire requests. | |
1884 | * Currently: | |
1885 | * retire -> free -> unbind -> wait -> retire_ring | |
1886 | */ | |
1887 | list_for_each_entry_safe(obj_priv, tmp, | |
1888 | &dev_priv->mm.deferred_free_list, | |
1889 | list) | |
1890 | i915_gem_free_object_tail(&obj_priv->base); | |
1891 | } | |
1892 | ||
b09a1fec CW |
1893 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
1894 | if (HAS_BSD(dev)) | |
1895 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); | |
1896 | } | |
1897 | ||
75ef9da2 | 1898 | static void |
673a394b EA |
1899 | i915_gem_retire_work_handler(struct work_struct *work) |
1900 | { | |
1901 | drm_i915_private_t *dev_priv; | |
1902 | struct drm_device *dev; | |
1903 | ||
1904 | dev_priv = container_of(work, drm_i915_private_t, | |
1905 | mm.retire_work.work); | |
1906 | dev = dev_priv->dev; | |
1907 | ||
891b48cf CW |
1908 | /* Come back later if the device is busy... */ |
1909 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1910 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1911 | return; | |
1912 | } | |
1913 | ||
b09a1fec | 1914 | i915_gem_retire_requests(dev); |
d1b851fc | 1915 | |
6dbe2772 | 1916 | if (!dev_priv->mm.suspended && |
d1b851fc ZN |
1917 | (!list_empty(&dev_priv->render_ring.request_list) || |
1918 | (HAS_BSD(dev) && | |
1919 | !list_empty(&dev_priv->bsd_ring.request_list)))) | |
9c9fe1f8 | 1920 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1921 | mutex_unlock(&dev->struct_mutex); |
1922 | } | |
1923 | ||
5a5a0c64 | 1924 | int |
852835f3 | 1925 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1926 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1927 | { |
1928 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1929 | u32 ier; |
673a394b EA |
1930 | int ret = 0; |
1931 | ||
1932 | BUG_ON(seqno == 0); | |
1933 | ||
30dbf0c0 CW |
1934 | if (atomic_read(&dev_priv->mm.wedged)) |
1935 | return -EAGAIN; | |
1936 | ||
a56ba56c | 1937 | if (ring->outstanding_lazy_request) { |
8dc5d147 | 1938 | seqno = i915_add_request(dev, NULL, NULL, ring); |
e35a41de DV |
1939 | if (seqno == 0) |
1940 | return -ENOMEM; | |
1941 | } | |
a56ba56c | 1942 | BUG_ON(seqno == dev_priv->next_seqno); |
e35a41de | 1943 | |
f787a5f5 | 1944 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { |
bad720ff | 1945 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1946 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1947 | else | |
1948 | ier = I915_READ(IER); | |
802c7eb6 JB |
1949 | if (!ier) { |
1950 | DRM_ERROR("something (likely vbetool) disabled " | |
1951 | "interrupts, re-enabling\n"); | |
1952 | i915_driver_irq_preinstall(dev); | |
1953 | i915_driver_irq_postinstall(dev); | |
1954 | } | |
1955 | ||
1c5d22f7 CW |
1956 | trace_i915_gem_request_wait_begin(dev, seqno); |
1957 | ||
852835f3 | 1958 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 1959 | ring->user_irq_get(dev, ring); |
48764bf4 | 1960 | if (interruptible) |
852835f3 ZN |
1961 | ret = wait_event_interruptible(ring->irq_queue, |
1962 | i915_seqno_passed( | |
f787a5f5 | 1963 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 1964 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 1965 | else |
852835f3 ZN |
1966 | wait_event(ring->irq_queue, |
1967 | i915_seqno_passed( | |
f787a5f5 | 1968 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 1969 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 1970 | |
8187a2b7 | 1971 | ring->user_irq_put(dev, ring); |
852835f3 | 1972 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
1973 | |
1974 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 1975 | } |
ba1234d1 | 1976 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1977 | ret = -EAGAIN; |
673a394b EA |
1978 | |
1979 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 1980 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
f787a5f5 | 1981 | __func__, ret, seqno, ring->get_seqno(dev, ring), |
8bff917c | 1982 | dev_priv->next_seqno); |
673a394b EA |
1983 | |
1984 | /* Directly dispatch request retiring. While we have the work queue | |
1985 | * to handle this, the waiter on a request often wants an associated | |
1986 | * buffer to have made it to the inactive list, and we would need | |
1987 | * a separate wait queue to handle that. | |
1988 | */ | |
1989 | if (ret == 0) | |
b09a1fec | 1990 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
1991 | |
1992 | return ret; | |
1993 | } | |
1994 | ||
48764bf4 DV |
1995 | /** |
1996 | * Waits for a sequence number to be signaled, and cleans up the | |
1997 | * request and object lists appropriately for that event. | |
1998 | */ | |
1999 | static int | |
852835f3 | 2000 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2001 | struct intel_ring_buffer *ring) |
48764bf4 | 2002 | { |
852835f3 | 2003 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2004 | } |
2005 | ||
20f0cd55 | 2006 | static void |
9220434a | 2007 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2008 | struct drm_file *file_priv, |
9220434a CW |
2009 | struct intel_ring_buffer *ring, |
2010 | uint32_t invalidate_domains, | |
2011 | uint32_t flush_domains) | |
2012 | { | |
2013 | ring->flush(dev, ring, invalidate_domains, flush_domains); | |
2014 | i915_gem_process_flushing_list(dev, flush_domains, ring); | |
2015 | } | |
2016 | ||
8187a2b7 ZN |
2017 | static void |
2018 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2019 | struct drm_file *file_priv, |
8187a2b7 | 2020 | uint32_t invalidate_domains, |
9220434a CW |
2021 | uint32_t flush_domains, |
2022 | uint32_t flush_rings) | |
8187a2b7 ZN |
2023 | { |
2024 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2025 | |
8187a2b7 ZN |
2026 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2027 | drm_agp_chipset_flush(dev); | |
8bff917c | 2028 | |
9220434a CW |
2029 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2030 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2031 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2032 | &dev_priv->render_ring, |
2033 | invalidate_domains, flush_domains); | |
2034 | if (flush_rings & RING_BSD) | |
c78ec30b | 2035 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2036 | &dev_priv->bsd_ring, |
2037 | invalidate_domains, flush_domains); | |
2038 | } | |
8187a2b7 ZN |
2039 | } |
2040 | ||
673a394b EA |
2041 | /** |
2042 | * Ensures that all rendering to the object has completed and the object is | |
2043 | * safe to unbind from the GTT or access from the CPU. | |
2044 | */ | |
2045 | static int | |
2cf34d7b CW |
2046 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2047 | bool interruptible) | |
673a394b EA |
2048 | { |
2049 | struct drm_device *dev = obj->dev; | |
23010e43 | 2050 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2051 | int ret; |
2052 | ||
e47c68e9 EA |
2053 | /* This function only exists to support waiting for existing rendering, |
2054 | * not for emitting required flushes. | |
673a394b | 2055 | */ |
e47c68e9 | 2056 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2057 | |
2058 | /* If there is rendering queued on the buffer being evicted, wait for | |
2059 | * it. | |
2060 | */ | |
2061 | if (obj_priv->active) { | |
2cf34d7b CW |
2062 | ret = i915_do_wait_request(dev, |
2063 | obj_priv->last_rendering_seqno, | |
2064 | interruptible, | |
2065 | obj_priv->ring); | |
2066 | if (ret) | |
673a394b EA |
2067 | return ret; |
2068 | } | |
2069 | ||
2070 | return 0; | |
2071 | } | |
2072 | ||
2073 | /** | |
2074 | * Unbinds an object from the GTT aperture. | |
2075 | */ | |
0f973f27 | 2076 | int |
673a394b EA |
2077 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2078 | { | |
2079 | struct drm_device *dev = obj->dev; | |
23010e43 | 2080 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2081 | int ret = 0; |
2082 | ||
673a394b EA |
2083 | if (obj_priv->gtt_space == NULL) |
2084 | return 0; | |
2085 | ||
2086 | if (obj_priv->pin_count != 0) { | |
2087 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2088 | return -EINVAL; | |
2089 | } | |
2090 | ||
5323fd04 EA |
2091 | /* blow away mappings if mapped through GTT */ |
2092 | i915_gem_release_mmap(obj); | |
2093 | ||
673a394b EA |
2094 | /* Move the object to the CPU domain to ensure that |
2095 | * any possible CPU writes while it's not in the GTT | |
2096 | * are flushed when we go to remap it. This will | |
2097 | * also ensure that all pending GPU writes are finished | |
2098 | * before we unbind. | |
2099 | */ | |
e47c68e9 | 2100 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2101 | if (ret == -ERESTARTSYS) |
673a394b | 2102 | return ret; |
8dc1775d CW |
2103 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2104 | * should be safe and we need to cleanup or else we might | |
2105 | * cause memory corruption through use-after-free. | |
2106 | */ | |
673a394b | 2107 | |
96b47b65 DV |
2108 | /* release the fence reg _after_ flushing */ |
2109 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2110 | i915_gem_clear_fence_reg(obj); | |
2111 | ||
673a394b EA |
2112 | if (obj_priv->agp_mem != NULL) { |
2113 | drm_unbind_agp(obj_priv->agp_mem); | |
2114 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
2115 | obj_priv->agp_mem = NULL; | |
2116 | } | |
2117 | ||
856fa198 | 2118 | i915_gem_object_put_pages(obj); |
a32808c0 | 2119 | BUG_ON(obj_priv->pages_refcount); |
673a394b EA |
2120 | |
2121 | if (obj_priv->gtt_space) { | |
2122 | atomic_dec(&dev->gtt_count); | |
2123 | atomic_sub(obj->size, &dev->gtt_memory); | |
2124 | ||
2125 | drm_mm_put_block(obj_priv->gtt_space); | |
2126 | obj_priv->gtt_space = NULL; | |
2127 | } | |
2128 | ||
f13d3f73 | 2129 | list_del_init(&obj_priv->list); |
673a394b | 2130 | |
963b4836 CW |
2131 | if (i915_gem_object_is_purgeable(obj_priv)) |
2132 | i915_gem_object_truncate(obj); | |
2133 | ||
1c5d22f7 CW |
2134 | trace_i915_gem_object_unbind(obj); |
2135 | ||
8dc1775d | 2136 | return ret; |
673a394b EA |
2137 | } |
2138 | ||
a56ba56c CW |
2139 | static int i915_ring_idle(struct drm_device *dev, |
2140 | struct intel_ring_buffer *ring) | |
2141 | { | |
2142 | i915_gem_flush_ring(dev, NULL, ring, | |
2143 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2144 | return i915_wait_request(dev, | |
2145 | i915_gem_next_request_seqno(dev, ring), | |
2146 | ring); | |
2147 | } | |
2148 | ||
b47eb4a2 | 2149 | int |
4df2faf4 DV |
2150 | i915_gpu_idle(struct drm_device *dev) |
2151 | { | |
2152 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2153 | bool lists_empty; | |
852835f3 | 2154 | int ret; |
4df2faf4 | 2155 | |
d1b851fc ZN |
2156 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2157 | list_empty(&dev_priv->render_ring.active_list) && | |
2158 | (!HAS_BSD(dev) || | |
2159 | list_empty(&dev_priv->bsd_ring.active_list))); | |
4df2faf4 DV |
2160 | if (lists_empty) |
2161 | return 0; | |
2162 | ||
2163 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2164 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2165 | if (ret) |
2166 | return ret; | |
d1b851fc ZN |
2167 | |
2168 | if (HAS_BSD(dev)) { | |
a56ba56c | 2169 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
d1b851fc ZN |
2170 | if (ret) |
2171 | return ret; | |
2172 | } | |
2173 | ||
8a1a49f9 | 2174 | return 0; |
4df2faf4 DV |
2175 | } |
2176 | ||
6911a9b8 | 2177 | int |
4bdadb97 CW |
2178 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2179 | gfp_t gfpmask) | |
673a394b | 2180 | { |
23010e43 | 2181 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2182 | int page_count, i; |
2183 | struct address_space *mapping; | |
2184 | struct inode *inode; | |
2185 | struct page *page; | |
673a394b | 2186 | |
778c3544 DV |
2187 | BUG_ON(obj_priv->pages_refcount |
2188 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2189 | ||
856fa198 | 2190 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2191 | return 0; |
2192 | ||
2193 | /* Get the list of pages out of our struct file. They'll be pinned | |
2194 | * at this point until we release them. | |
2195 | */ | |
2196 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2197 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2198 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2199 | if (obj_priv->pages == NULL) { |
856fa198 | 2200 | obj_priv->pages_refcount--; |
673a394b EA |
2201 | return -ENOMEM; |
2202 | } | |
2203 | ||
2204 | inode = obj->filp->f_path.dentry->d_inode; | |
2205 | mapping = inode->i_mapping; | |
2206 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2207 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2208 | GFP_HIGHUSER | |
4bdadb97 | 2209 | __GFP_COLD | |
cd9f040d | 2210 | __GFP_RECLAIMABLE | |
4bdadb97 | 2211 | gfpmask); |
1f2b1013 CW |
2212 | if (IS_ERR(page)) |
2213 | goto err_pages; | |
2214 | ||
856fa198 | 2215 | obj_priv->pages[i] = page; |
673a394b | 2216 | } |
280b713b EA |
2217 | |
2218 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2219 | i915_gem_object_do_bit_17_swizzle(obj); | |
2220 | ||
673a394b | 2221 | return 0; |
1f2b1013 CW |
2222 | |
2223 | err_pages: | |
2224 | while (i--) | |
2225 | page_cache_release(obj_priv->pages[i]); | |
2226 | ||
2227 | drm_free_large(obj_priv->pages); | |
2228 | obj_priv->pages = NULL; | |
2229 | obj_priv->pages_refcount--; | |
2230 | return PTR_ERR(page); | |
673a394b EA |
2231 | } |
2232 | ||
4e901fdc EA |
2233 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2234 | { | |
2235 | struct drm_gem_object *obj = reg->obj; | |
2236 | struct drm_device *dev = obj->dev; | |
2237 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2238 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2239 | int regnum = obj_priv->fence_reg; |
2240 | uint64_t val; | |
2241 | ||
2242 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2243 | 0xfffff000) << 32; | |
2244 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2245 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2246 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2247 | ||
2248 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2249 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2250 | val |= I965_FENCE_REG_VALID; | |
2251 | ||
2252 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2253 | } | |
2254 | ||
de151cf6 JB |
2255 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2256 | { | |
2257 | struct drm_gem_object *obj = reg->obj; | |
2258 | struct drm_device *dev = obj->dev; | |
2259 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2260 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2261 | int regnum = obj_priv->fence_reg; |
2262 | uint64_t val; | |
2263 | ||
2264 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2265 | 0xfffff000) << 32; | |
2266 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2267 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2268 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2269 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2270 | val |= I965_FENCE_REG_VALID; | |
2271 | ||
2272 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2273 | } | |
2274 | ||
2275 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2276 | { | |
2277 | struct drm_gem_object *obj = reg->obj; | |
2278 | struct drm_device *dev = obj->dev; | |
2279 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2280 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2281 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2282 | int tile_width; |
dc529a4f | 2283 | uint32_t fence_reg, val; |
de151cf6 JB |
2284 | uint32_t pitch_val; |
2285 | ||
2286 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2287 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2288 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2289 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2290 | return; |
2291 | } | |
2292 | ||
0f973f27 JB |
2293 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2294 | HAS_128_BYTE_Y_TILING(dev)) | |
2295 | tile_width = 128; | |
de151cf6 | 2296 | else |
0f973f27 JB |
2297 | tile_width = 512; |
2298 | ||
2299 | /* Note: pitch better be a power of two tile widths */ | |
2300 | pitch_val = obj_priv->stride / tile_width; | |
2301 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2302 | |
c36a2a6d DV |
2303 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2304 | HAS_128_BYTE_Y_TILING(dev)) | |
2305 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2306 | else | |
2307 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2308 | ||
de151cf6 JB |
2309 | val = obj_priv->gtt_offset; |
2310 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2311 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2312 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2313 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2314 | val |= I830_FENCE_REG_VALID; | |
2315 | ||
dc529a4f EA |
2316 | if (regnum < 8) |
2317 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2318 | else | |
2319 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2320 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2321 | } |
2322 | ||
2323 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2324 | { | |
2325 | struct drm_gem_object *obj = reg->obj; | |
2326 | struct drm_device *dev = obj->dev; | |
2327 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2328 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2329 | int regnum = obj_priv->fence_reg; |
2330 | uint32_t val; | |
2331 | uint32_t pitch_val; | |
8d7773a3 | 2332 | uint32_t fence_size_bits; |
de151cf6 | 2333 | |
8d7773a3 | 2334 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2335 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2336 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2337 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2338 | return; |
2339 | } | |
2340 | ||
e76a16de EA |
2341 | pitch_val = obj_priv->stride / 128; |
2342 | pitch_val = ffs(pitch_val) - 1; | |
2343 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2344 | ||
de151cf6 JB |
2345 | val = obj_priv->gtt_offset; |
2346 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2347 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2348 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2349 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2350 | val |= fence_size_bits; | |
de151cf6 JB |
2351 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2352 | val |= I830_FENCE_REG_VALID; | |
2353 | ||
2354 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2355 | } |
2356 | ||
2cf34d7b CW |
2357 | static int i915_find_fence_reg(struct drm_device *dev, |
2358 | bool interruptible) | |
ae3db24a DV |
2359 | { |
2360 | struct drm_i915_fence_reg *reg = NULL; | |
2361 | struct drm_i915_gem_object *obj_priv = NULL; | |
2362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2363 | struct drm_gem_object *obj = NULL; | |
2364 | int i, avail, ret; | |
2365 | ||
2366 | /* First try to find a free reg */ | |
2367 | avail = 0; | |
2368 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2369 | reg = &dev_priv->fence_regs[i]; | |
2370 | if (!reg->obj) | |
2371 | return i; | |
2372 | ||
23010e43 | 2373 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2374 | if (!obj_priv->pin_count) |
2375 | avail++; | |
2376 | } | |
2377 | ||
2378 | if (avail == 0) | |
2379 | return -ENOSPC; | |
2380 | ||
2381 | /* None available, try to steal one or wait for a user to finish */ | |
2382 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2383 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2384 | lru_list) { | |
2385 | obj = reg->obj; | |
2386 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2387 | |
2388 | if (obj_priv->pin_count) | |
2389 | continue; | |
2390 | ||
2391 | /* found one! */ | |
2392 | i = obj_priv->fence_reg; | |
2393 | break; | |
2394 | } | |
2395 | ||
2396 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2397 | ||
2398 | /* We only have a reference on obj from the active list. put_fence_reg | |
2399 | * might drop that one, causing a use-after-free in it. So hold a | |
2400 | * private reference to obj like the other callers of put_fence_reg | |
2401 | * (set_tiling ioctl) do. */ | |
2402 | drm_gem_object_reference(obj); | |
2cf34d7b | 2403 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2404 | drm_gem_object_unreference(obj); |
2405 | if (ret != 0) | |
2406 | return ret; | |
2407 | ||
2408 | return i; | |
2409 | } | |
2410 | ||
de151cf6 JB |
2411 | /** |
2412 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2413 | * @obj: object to map through a fence reg | |
2414 | * | |
2415 | * When mapping objects through the GTT, userspace wants to be able to write | |
2416 | * to them without having to worry about swizzling if the object is tiled. | |
2417 | * | |
2418 | * This function walks the fence regs looking for a free one for @obj, | |
2419 | * stealing one if it can't find any. | |
2420 | * | |
2421 | * It then sets up the reg based on the object's properties: address, pitch | |
2422 | * and tiling format. | |
2423 | */ | |
8c4b8c3f | 2424 | int |
2cf34d7b CW |
2425 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2426 | bool interruptible) | |
de151cf6 JB |
2427 | { |
2428 | struct drm_device *dev = obj->dev; | |
79e53945 | 2429 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2430 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2431 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2432 | int ret; |
de151cf6 | 2433 | |
a09ba7fa EA |
2434 | /* Just update our place in the LRU if our fence is getting used. */ |
2435 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2436 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2437 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2438 | return 0; |
2439 | } | |
2440 | ||
de151cf6 JB |
2441 | switch (obj_priv->tiling_mode) { |
2442 | case I915_TILING_NONE: | |
2443 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2444 | break; | |
2445 | case I915_TILING_X: | |
0f973f27 JB |
2446 | if (!obj_priv->stride) |
2447 | return -EINVAL; | |
2448 | WARN((obj_priv->stride & (512 - 1)), | |
2449 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2450 | obj_priv->gtt_offset); | |
de151cf6 JB |
2451 | break; |
2452 | case I915_TILING_Y: | |
0f973f27 JB |
2453 | if (!obj_priv->stride) |
2454 | return -EINVAL; | |
2455 | WARN((obj_priv->stride & (128 - 1)), | |
2456 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2457 | obj_priv->gtt_offset); | |
de151cf6 JB |
2458 | break; |
2459 | } | |
2460 | ||
2cf34d7b | 2461 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2462 | if (ret < 0) |
2463 | return ret; | |
de151cf6 | 2464 | |
ae3db24a DV |
2465 | obj_priv->fence_reg = ret; |
2466 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2467 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2468 | |
de151cf6 JB |
2469 | reg->obj = obj; |
2470 | ||
e259befd CW |
2471 | switch (INTEL_INFO(dev)->gen) { |
2472 | case 6: | |
4e901fdc | 2473 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2474 | break; |
2475 | case 5: | |
2476 | case 4: | |
de151cf6 | 2477 | i965_write_fence_reg(reg); |
e259befd CW |
2478 | break; |
2479 | case 3: | |
de151cf6 | 2480 | i915_write_fence_reg(reg); |
e259befd CW |
2481 | break; |
2482 | case 2: | |
de151cf6 | 2483 | i830_write_fence_reg(reg); |
e259befd CW |
2484 | break; |
2485 | } | |
d9ddcb96 | 2486 | |
ae3db24a DV |
2487 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2488 | obj_priv->tiling_mode); | |
1c5d22f7 | 2489 | |
d9ddcb96 | 2490 | return 0; |
de151cf6 JB |
2491 | } |
2492 | ||
2493 | /** | |
2494 | * i915_gem_clear_fence_reg - clear out fence register info | |
2495 | * @obj: object to clear | |
2496 | * | |
2497 | * Zeroes out the fence register itself and clears out the associated | |
2498 | * data structures in dev_priv and obj_priv. | |
2499 | */ | |
2500 | static void | |
2501 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2502 | { | |
2503 | struct drm_device *dev = obj->dev; | |
79e53945 | 2504 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2505 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2506 | struct drm_i915_fence_reg *reg = |
2507 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2508 | uint32_t fence_reg; |
de151cf6 | 2509 | |
e259befd CW |
2510 | switch (INTEL_INFO(dev)->gen) { |
2511 | case 6: | |
4e901fdc EA |
2512 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2513 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2514 | break; |
2515 | case 5: | |
2516 | case 4: | |
de151cf6 | 2517 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2518 | break; |
2519 | case 3: | |
9b74f734 | 2520 | if (obj_priv->fence_reg >= 8) |
e259befd | 2521 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2522 | else |
e259befd CW |
2523 | case 2: |
2524 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2525 | |
2526 | I915_WRITE(fence_reg, 0); | |
e259befd | 2527 | break; |
dc529a4f | 2528 | } |
de151cf6 | 2529 | |
007cc8ac | 2530 | reg->obj = NULL; |
de151cf6 | 2531 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2532 | list_del_init(®->lru_list); |
de151cf6 JB |
2533 | } |
2534 | ||
52dc7d32 CW |
2535 | /** |
2536 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2537 | * to the buffer to finish, and then resets the fence register. | |
2538 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2539 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2540 | * |
2541 | * Zeroes out the fence register itself and clears out the associated | |
2542 | * data structures in dev_priv and obj_priv. | |
2543 | */ | |
2544 | int | |
2cf34d7b CW |
2545 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2546 | bool interruptible) | |
52dc7d32 CW |
2547 | { |
2548 | struct drm_device *dev = obj->dev; | |
53640e1d | 2549 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2550 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2551 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2552 | |
2553 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2554 | return 0; | |
2555 | ||
10ae9bd2 DV |
2556 | /* If we've changed tiling, GTT-mappings of the object |
2557 | * need to re-fault to ensure that the correct fence register | |
2558 | * setup is in place. | |
2559 | */ | |
2560 | i915_gem_release_mmap(obj); | |
2561 | ||
52dc7d32 CW |
2562 | /* On the i915, GPU access to tiled buffers is via a fence, |
2563 | * therefore we must wait for any outstanding access to complete | |
2564 | * before clearing the fence. | |
2565 | */ | |
53640e1d CW |
2566 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2567 | if (reg->gpu) { | |
52dc7d32 CW |
2568 | int ret; |
2569 | ||
2cf34d7b | 2570 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad CW |
2571 | if (ret) |
2572 | return ret; | |
2573 | ||
2cf34d7b | 2574 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2575 | if (ret) |
52dc7d32 | 2576 | return ret; |
53640e1d CW |
2577 | |
2578 | reg->gpu = false; | |
52dc7d32 CW |
2579 | } |
2580 | ||
4a726612 | 2581 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2582 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2583 | |
2584 | return 0; | |
2585 | } | |
2586 | ||
673a394b EA |
2587 | /** |
2588 | * Finds free space in the GTT aperture and binds the object there. | |
2589 | */ | |
2590 | static int | |
2591 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2592 | { | |
2593 | struct drm_device *dev = obj->dev; | |
2594 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2595 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2596 | struct drm_mm_node *free_space; |
4bdadb97 | 2597 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2598 | int ret; |
673a394b | 2599 | |
bb6baf76 | 2600 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2601 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2602 | return -EINVAL; | |
2603 | } | |
2604 | ||
673a394b | 2605 | if (alignment == 0) |
0f973f27 | 2606 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2607 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2608 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2609 | return -EINVAL; | |
2610 | } | |
2611 | ||
654fc607 CW |
2612 | /* If the object is bigger than the entire aperture, reject it early |
2613 | * before evicting everything in a vain attempt to find space. | |
2614 | */ | |
2615 | if (obj->size > dev->gtt_total) { | |
2616 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); | |
2617 | return -E2BIG; | |
2618 | } | |
2619 | ||
673a394b EA |
2620 | search_free: |
2621 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2622 | obj->size, alignment, 0); | |
2623 | if (free_space != NULL) { | |
2624 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2625 | alignment); | |
db3307a9 | 2626 | if (obj_priv->gtt_space != NULL) |
673a394b | 2627 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
673a394b EA |
2628 | } |
2629 | if (obj_priv->gtt_space == NULL) { | |
2630 | /* If the gtt is empty and we're still having trouble | |
2631 | * fitting our object in, we're out of memory. | |
2632 | */ | |
0108a3ed | 2633 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2634 | if (ret) |
673a394b | 2635 | return ret; |
9731129c | 2636 | |
673a394b EA |
2637 | goto search_free; |
2638 | } | |
2639 | ||
4bdadb97 | 2640 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2641 | if (ret) { |
2642 | drm_mm_put_block(obj_priv->gtt_space); | |
2643 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2644 | |
2645 | if (ret == -ENOMEM) { | |
2646 | /* first try to clear up some space from the GTT */ | |
0108a3ed DV |
2647 | ret = i915_gem_evict_something(dev, obj->size, |
2648 | alignment); | |
07f73f69 | 2649 | if (ret) { |
07f73f69 | 2650 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2651 | if (gfpmask) { |
2652 | gfpmask = 0; | |
2653 | goto search_free; | |
07f73f69 CW |
2654 | } |
2655 | ||
2656 | return ret; | |
2657 | } | |
2658 | ||
2659 | goto search_free; | |
2660 | } | |
2661 | ||
673a394b EA |
2662 | return ret; |
2663 | } | |
2664 | ||
673a394b EA |
2665 | /* Create an AGP memory structure pointing at our pages, and bind it |
2666 | * into the GTT. | |
2667 | */ | |
2668 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2669 | obj_priv->pages, |
07f73f69 | 2670 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2671 | obj_priv->gtt_offset, |
2672 | obj_priv->agp_type); | |
673a394b | 2673 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2674 | i915_gem_object_put_pages(obj); |
673a394b EA |
2675 | drm_mm_put_block(obj_priv->gtt_space); |
2676 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2677 | |
0108a3ed | 2678 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2679 | if (ret) |
07f73f69 | 2680 | return ret; |
07f73f69 CW |
2681 | |
2682 | goto search_free; | |
673a394b EA |
2683 | } |
2684 | atomic_inc(&dev->gtt_count); | |
2685 | atomic_add(obj->size, &dev->gtt_memory); | |
2686 | ||
bf1a1092 CW |
2687 | /* keep track of bounds object by adding it to the inactive list */ |
2688 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
2689 | ||
673a394b EA |
2690 | /* Assert that the object is not currently in any GPU domain. As it |
2691 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2692 | * a GPU cache | |
2693 | */ | |
21d509e3 CW |
2694 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2695 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2696 | |
1c5d22f7 CW |
2697 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2698 | ||
673a394b EA |
2699 | return 0; |
2700 | } | |
2701 | ||
2702 | void | |
2703 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2704 | { | |
23010e43 | 2705 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2706 | |
2707 | /* If we don't have a page list set up, then we're not pinned | |
2708 | * to GPU, and we can ignore the cache flush because it'll happen | |
2709 | * again at bind time. | |
2710 | */ | |
856fa198 | 2711 | if (obj_priv->pages == NULL) |
673a394b EA |
2712 | return; |
2713 | ||
1c5d22f7 | 2714 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2715 | |
856fa198 | 2716 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2717 | } |
2718 | ||
e47c68e9 | 2719 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2720 | static int |
ba3d8d74 DV |
2721 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2722 | bool pipelined) | |
e47c68e9 EA |
2723 | { |
2724 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2725 | uint32_t old_write_domain; |
e47c68e9 EA |
2726 | |
2727 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2728 | return 0; |
e47c68e9 EA |
2729 | |
2730 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2731 | old_write_domain = obj->write_domain; |
c78ec30b | 2732 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2733 | to_intel_bo(obj)->ring, |
2734 | 0, obj->write_domain); | |
48b956c5 | 2735 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2736 | |
2737 | trace_i915_gem_object_change_domain(obj, | |
2738 | obj->read_domains, | |
2739 | old_write_domain); | |
ba3d8d74 DV |
2740 | |
2741 | if (pipelined) | |
2742 | return 0; | |
2743 | ||
2cf34d7b | 2744 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2745 | } |
2746 | ||
2747 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2748 | static void | |
2749 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2750 | { | |
1c5d22f7 CW |
2751 | uint32_t old_write_domain; |
2752 | ||
e47c68e9 EA |
2753 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2754 | return; | |
2755 | ||
2756 | /* No actual flushing is required for the GTT write domain. Writes | |
2757 | * to it immediately go to main memory as far as we know, so there's | |
2758 | * no chipset flush. It also doesn't land in render cache. | |
2759 | */ | |
1c5d22f7 | 2760 | old_write_domain = obj->write_domain; |
e47c68e9 | 2761 | obj->write_domain = 0; |
1c5d22f7 CW |
2762 | |
2763 | trace_i915_gem_object_change_domain(obj, | |
2764 | obj->read_domains, | |
2765 | old_write_domain); | |
e47c68e9 EA |
2766 | } |
2767 | ||
2768 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2769 | static void | |
2770 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2771 | { | |
2772 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2773 | uint32_t old_write_domain; |
e47c68e9 EA |
2774 | |
2775 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2776 | return; | |
2777 | ||
2778 | i915_gem_clflush_object(obj); | |
2779 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2780 | old_write_domain = obj->write_domain; |
e47c68e9 | 2781 | obj->write_domain = 0; |
1c5d22f7 CW |
2782 | |
2783 | trace_i915_gem_object_change_domain(obj, | |
2784 | obj->read_domains, | |
2785 | old_write_domain); | |
e47c68e9 EA |
2786 | } |
2787 | ||
2ef7eeaa EA |
2788 | /** |
2789 | * Moves a single object to the GTT read, and possibly write domain. | |
2790 | * | |
2791 | * This function returns when the move is complete, including waiting on | |
2792 | * flushes to occur. | |
2793 | */ | |
79e53945 | 2794 | int |
2ef7eeaa EA |
2795 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2796 | { | |
23010e43 | 2797 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2798 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2799 | int ret; |
2ef7eeaa | 2800 | |
02354392 EA |
2801 | /* Not valid to be called on unbound objects. */ |
2802 | if (obj_priv->gtt_space == NULL) | |
2803 | return -EINVAL; | |
2804 | ||
ba3d8d74 | 2805 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2806 | if (ret != 0) |
2807 | return ret; | |
2808 | ||
7213342d | 2809 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2810 | |
ba3d8d74 | 2811 | if (write) { |
2cf34d7b | 2812 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2813 | if (ret) |
2814 | return ret; | |
ba3d8d74 | 2815 | } |
2ef7eeaa | 2816 | |
7213342d CW |
2817 | old_write_domain = obj->write_domain; |
2818 | old_read_domains = obj->read_domains; | |
2ef7eeaa | 2819 | |
e47c68e9 EA |
2820 | /* It should now be out of any other write domains, and we can update |
2821 | * the domain values for our changes. | |
2822 | */ | |
2823 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2824 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2825 | if (write) { | |
7213342d | 2826 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2827 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2828 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2829 | } |
2830 | ||
1c5d22f7 CW |
2831 | trace_i915_gem_object_change_domain(obj, |
2832 | old_read_domains, | |
2833 | old_write_domain); | |
2834 | ||
e47c68e9 EA |
2835 | return 0; |
2836 | } | |
2837 | ||
b9241ea3 ZW |
2838 | /* |
2839 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2840 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2841 | */ | |
2842 | int | |
48b956c5 CW |
2843 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2844 | bool pipelined) | |
b9241ea3 | 2845 | { |
23010e43 | 2846 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2847 | uint32_t old_read_domains; |
b9241ea3 ZW |
2848 | int ret; |
2849 | ||
2850 | /* Not valid to be called on unbound objects. */ | |
2851 | if (obj_priv->gtt_space == NULL) | |
2852 | return -EINVAL; | |
2853 | ||
ced270fa | 2854 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
48b956c5 | 2855 | if (ret) |
e35a41de | 2856 | return ret; |
b9241ea3 | 2857 | |
ced270fa CW |
2858 | /* Currently, we are always called from an non-interruptible context. */ |
2859 | if (!pipelined) { | |
2860 | ret = i915_gem_object_wait_rendering(obj, false); | |
2861 | if (ret) | |
2862 | return ret; | |
2863 | } | |
2864 | ||
b118c1e3 CW |
2865 | i915_gem_object_flush_cpu_write_domain(obj); |
2866 | ||
b9241ea3 | 2867 | old_read_domains = obj->read_domains; |
c78ec30b | 2868 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2869 | |
2870 | trace_i915_gem_object_change_domain(obj, | |
2871 | old_read_domains, | |
ba3d8d74 | 2872 | obj->write_domain); |
b9241ea3 ZW |
2873 | |
2874 | return 0; | |
2875 | } | |
2876 | ||
e47c68e9 EA |
2877 | /** |
2878 | * Moves a single object to the CPU read, and possibly write domain. | |
2879 | * | |
2880 | * This function returns when the move is complete, including waiting on | |
2881 | * flushes to occur. | |
2882 | */ | |
2883 | static int | |
2884 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2885 | { | |
1c5d22f7 | 2886 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2887 | int ret; |
2888 | ||
ba3d8d74 | 2889 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2890 | if (ret != 0) |
2891 | return ret; | |
2ef7eeaa | 2892 | |
e47c68e9 | 2893 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2894 | |
e47c68e9 EA |
2895 | /* If we have a partially-valid cache of the object in the CPU, |
2896 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2897 | */ |
e47c68e9 | 2898 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2899 | |
7213342d | 2900 | if (write) { |
2cf34d7b | 2901 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
2902 | if (ret) |
2903 | return ret; | |
2904 | } | |
2905 | ||
1c5d22f7 CW |
2906 | old_write_domain = obj->write_domain; |
2907 | old_read_domains = obj->read_domains; | |
2908 | ||
e47c68e9 EA |
2909 | /* Flush the CPU cache if it's still invalid. */ |
2910 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2911 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2912 | |
e47c68e9 | 2913 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2914 | } |
2915 | ||
2916 | /* It should now be out of any other write domains, and we can update | |
2917 | * the domain values for our changes. | |
2918 | */ | |
e47c68e9 EA |
2919 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2920 | ||
2921 | /* If we're writing through the CPU, then the GPU read domains will | |
2922 | * need to be invalidated at next use. | |
2923 | */ | |
2924 | if (write) { | |
c78ec30b | 2925 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
2926 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
2927 | } | |
2ef7eeaa | 2928 | |
1c5d22f7 CW |
2929 | trace_i915_gem_object_change_domain(obj, |
2930 | old_read_domains, | |
2931 | old_write_domain); | |
2932 | ||
2ef7eeaa EA |
2933 | return 0; |
2934 | } | |
2935 | ||
673a394b EA |
2936 | /* |
2937 | * Set the next domain for the specified object. This | |
2938 | * may not actually perform the necessary flushing/invaliding though, | |
2939 | * as that may want to be batched with other set_domain operations | |
2940 | * | |
2941 | * This is (we hope) the only really tricky part of gem. The goal | |
2942 | * is fairly simple -- track which caches hold bits of the object | |
2943 | * and make sure they remain coherent. A few concrete examples may | |
2944 | * help to explain how it works. For shorthand, we use the notation | |
2945 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2946 | * a pair of read and write domain masks. | |
2947 | * | |
2948 | * Case 1: the batch buffer | |
2949 | * | |
2950 | * 1. Allocated | |
2951 | * 2. Written by CPU | |
2952 | * 3. Mapped to GTT | |
2953 | * 4. Read by GPU | |
2954 | * 5. Unmapped from GTT | |
2955 | * 6. Freed | |
2956 | * | |
2957 | * Let's take these a step at a time | |
2958 | * | |
2959 | * 1. Allocated | |
2960 | * Pages allocated from the kernel may still have | |
2961 | * cache contents, so we set them to (CPU, CPU) always. | |
2962 | * 2. Written by CPU (using pwrite) | |
2963 | * The pwrite function calls set_domain (CPU, CPU) and | |
2964 | * this function does nothing (as nothing changes) | |
2965 | * 3. Mapped by GTT | |
2966 | * This function asserts that the object is not | |
2967 | * currently in any GPU-based read or write domains | |
2968 | * 4. Read by GPU | |
2969 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
2970 | * As write_domain is zero, this function adds in the | |
2971 | * current read domains (CPU+COMMAND, 0). | |
2972 | * flush_domains is set to CPU. | |
2973 | * invalidate_domains is set to COMMAND | |
2974 | * clflush is run to get data out of the CPU caches | |
2975 | * then i915_dev_set_domain calls i915_gem_flush to | |
2976 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
2977 | * 5. Unmapped from GTT | |
2978 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
2979 | * flush_domains and invalidate_domains end up both zero | |
2980 | * so no flushing/invalidating happens | |
2981 | * 6. Freed | |
2982 | * yay, done | |
2983 | * | |
2984 | * Case 2: The shared render buffer | |
2985 | * | |
2986 | * 1. Allocated | |
2987 | * 2. Mapped to GTT | |
2988 | * 3. Read/written by GPU | |
2989 | * 4. set_domain to (CPU,CPU) | |
2990 | * 5. Read/written by CPU | |
2991 | * 6. Read/written by GPU | |
2992 | * | |
2993 | * 1. Allocated | |
2994 | * Same as last example, (CPU, CPU) | |
2995 | * 2. Mapped to GTT | |
2996 | * Nothing changes (assertions find that it is not in the GPU) | |
2997 | * 3. Read/written by GPU | |
2998 | * execbuffer calls set_domain (RENDER, RENDER) | |
2999 | * flush_domains gets CPU | |
3000 | * invalidate_domains gets GPU | |
3001 | * clflush (obj) | |
3002 | * MI_FLUSH and drm_agp_chipset_flush | |
3003 | * 4. set_domain (CPU, CPU) | |
3004 | * flush_domains gets GPU | |
3005 | * invalidate_domains gets CPU | |
3006 | * wait_rendering (obj) to make sure all drawing is complete. | |
3007 | * This will include an MI_FLUSH to get the data from GPU | |
3008 | * to memory | |
3009 | * clflush (obj) to invalidate the CPU cache | |
3010 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3011 | * 5. Read/written by CPU | |
3012 | * cache lines are loaded and dirtied | |
3013 | * 6. Read written by GPU | |
3014 | * Same as last GPU access | |
3015 | * | |
3016 | * Case 3: The constant buffer | |
3017 | * | |
3018 | * 1. Allocated | |
3019 | * 2. Written by CPU | |
3020 | * 3. Read by GPU | |
3021 | * 4. Updated (written) by CPU again | |
3022 | * 5. Read by GPU | |
3023 | * | |
3024 | * 1. Allocated | |
3025 | * (CPU, CPU) | |
3026 | * 2. Written by CPU | |
3027 | * (CPU, CPU) | |
3028 | * 3. Read by GPU | |
3029 | * (CPU+RENDER, 0) | |
3030 | * flush_domains = CPU | |
3031 | * invalidate_domains = RENDER | |
3032 | * clflush (obj) | |
3033 | * MI_FLUSH | |
3034 | * drm_agp_chipset_flush | |
3035 | * 4. Updated (written) by CPU again | |
3036 | * (CPU, CPU) | |
3037 | * flush_domains = 0 (no previous write domain) | |
3038 | * invalidate_domains = 0 (no new read domains) | |
3039 | * 5. Read by GPU | |
3040 | * (CPU+RENDER, 0) | |
3041 | * flush_domains = CPU | |
3042 | * invalidate_domains = RENDER | |
3043 | * clflush (obj) | |
3044 | * MI_FLUSH | |
3045 | * drm_agp_chipset_flush | |
3046 | */ | |
c0d90829 | 3047 | static void |
8b0e378a | 3048 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
3049 | { |
3050 | struct drm_device *dev = obj->dev; | |
9220434a | 3051 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 3052 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3053 | uint32_t invalidate_domains = 0; |
3054 | uint32_t flush_domains = 0; | |
1c5d22f7 | 3055 | uint32_t old_read_domains; |
e47c68e9 | 3056 | |
8b0e378a EA |
3057 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
3058 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 3059 | |
652c393a JB |
3060 | intel_mark_busy(dev, obj); |
3061 | ||
673a394b EA |
3062 | /* |
3063 | * If the object isn't moving to a new write domain, | |
3064 | * let the object stay in multiple read domains | |
3065 | */ | |
8b0e378a EA |
3066 | if (obj->pending_write_domain == 0) |
3067 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3068 | else |
3069 | obj_priv->dirty = 1; | |
3070 | ||
3071 | /* | |
3072 | * Flush the current write domain if | |
3073 | * the new read domains don't match. Invalidate | |
3074 | * any read domains which differ from the old | |
3075 | * write domain | |
3076 | */ | |
8b0e378a EA |
3077 | if (obj->write_domain && |
3078 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3079 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3080 | invalidate_domains |= |
3081 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3082 | } |
3083 | /* | |
3084 | * Invalidate any read caches which may have | |
3085 | * stale data. That is, any new read domains. | |
3086 | */ | |
8b0e378a | 3087 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3088 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3089 | i915_gem_clflush_object(obj); |
673a394b | 3090 | |
1c5d22f7 CW |
3091 | old_read_domains = obj->read_domains; |
3092 | ||
efbeed96 EA |
3093 | /* The actual obj->write_domain will be updated with |
3094 | * pending_write_domain after we emit the accumulated flush for all | |
3095 | * of our domain changes in execbuffers (which clears objects' | |
3096 | * write_domains). So if we have a current write domain that we | |
3097 | * aren't changing, set pending_write_domain to that. | |
3098 | */ | |
3099 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3100 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3101 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
3102 | |
3103 | dev->invalidate_domains |= invalidate_domains; | |
3104 | dev->flush_domains |= flush_domains; | |
9220434a CW |
3105 | if (obj_priv->ring) |
3106 | dev_priv->mm.flush_rings |= obj_priv->ring->id; | |
1c5d22f7 CW |
3107 | |
3108 | trace_i915_gem_object_change_domain(obj, | |
3109 | old_read_domains, | |
3110 | obj->write_domain); | |
673a394b EA |
3111 | } |
3112 | ||
3113 | /** | |
e47c68e9 | 3114 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3115 | * |
e47c68e9 EA |
3116 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3117 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3118 | */ |
e47c68e9 EA |
3119 | static void |
3120 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3121 | { |
23010e43 | 3122 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3123 | |
e47c68e9 EA |
3124 | if (!obj_priv->page_cpu_valid) |
3125 | return; | |
3126 | ||
3127 | /* If we're partially in the CPU read domain, finish moving it in. | |
3128 | */ | |
3129 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3130 | int i; | |
3131 | ||
3132 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3133 | if (obj_priv->page_cpu_valid[i]) | |
3134 | continue; | |
856fa198 | 3135 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3136 | } |
e47c68e9 EA |
3137 | } |
3138 | ||
3139 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3140 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3141 | */ | |
9a298b2a | 3142 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3143 | obj_priv->page_cpu_valid = NULL; |
3144 | } | |
3145 | ||
3146 | /** | |
3147 | * Set the CPU read domain on a range of the object. | |
3148 | * | |
3149 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3150 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3151 | * pages have been flushed, and will be respected by | |
3152 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3153 | * of the whole object. | |
3154 | * | |
3155 | * This function returns when the move is complete, including waiting on | |
3156 | * flushes to occur. | |
3157 | */ | |
3158 | static int | |
3159 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3160 | uint64_t offset, uint64_t size) | |
3161 | { | |
23010e43 | 3162 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3163 | uint32_t old_read_domains; |
e47c68e9 | 3164 | int i, ret; |
673a394b | 3165 | |
e47c68e9 EA |
3166 | if (offset == 0 && size == obj->size) |
3167 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3168 | |
ba3d8d74 | 3169 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3170 | if (ret != 0) |
6a47baa6 | 3171 | return ret; |
e47c68e9 EA |
3172 | i915_gem_object_flush_gtt_write_domain(obj); |
3173 | ||
3174 | /* If we're already fully in the CPU read domain, we're done. */ | |
3175 | if (obj_priv->page_cpu_valid == NULL && | |
3176 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3177 | return 0; | |
673a394b | 3178 | |
e47c68e9 EA |
3179 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3180 | * newly adding I915_GEM_DOMAIN_CPU | |
3181 | */ | |
673a394b | 3182 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3183 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3184 | GFP_KERNEL); | |
e47c68e9 EA |
3185 | if (obj_priv->page_cpu_valid == NULL) |
3186 | return -ENOMEM; | |
3187 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3188 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3189 | |
3190 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3191 | * perspective. | |
3192 | */ | |
e47c68e9 EA |
3193 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3194 | i++) { | |
673a394b EA |
3195 | if (obj_priv->page_cpu_valid[i]) |
3196 | continue; | |
3197 | ||
856fa198 | 3198 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3199 | |
3200 | obj_priv->page_cpu_valid[i] = 1; | |
3201 | } | |
3202 | ||
e47c68e9 EA |
3203 | /* It should now be out of any other write domains, and we can update |
3204 | * the domain values for our changes. | |
3205 | */ | |
3206 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3207 | ||
1c5d22f7 | 3208 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3209 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3210 | ||
1c5d22f7 CW |
3211 | trace_i915_gem_object_change_domain(obj, |
3212 | old_read_domains, | |
3213 | obj->write_domain); | |
3214 | ||
673a394b EA |
3215 | return 0; |
3216 | } | |
3217 | ||
673a394b EA |
3218 | /** |
3219 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3220 | */ | |
3221 | static int | |
3222 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3223 | struct drm_file *file_priv, | |
76446cac | 3224 | struct drm_i915_gem_exec_object2 *entry, |
40a5f0de | 3225 | struct drm_i915_gem_relocation_entry *relocs) |
673a394b EA |
3226 | { |
3227 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3228 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 3229 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3230 | int i, ret; |
0839ccb8 | 3231 | void __iomem *reloc_page; |
76446cac JB |
3232 | bool need_fence; |
3233 | ||
3234 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3235 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3236 | ||
3237 | /* Check fence reg constraints and rebind if necessary */ | |
808b24d6 CW |
3238 | if (need_fence && |
3239 | !i915_gem_object_fence_offset_ok(obj, | |
3240 | obj_priv->tiling_mode)) { | |
3241 | ret = i915_gem_object_unbind(obj); | |
3242 | if (ret) | |
3243 | return ret; | |
3244 | } | |
673a394b EA |
3245 | |
3246 | /* Choose the GTT offset for our buffer and put it there. */ | |
3247 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3248 | if (ret) | |
3249 | return ret; | |
3250 | ||
76446cac JB |
3251 | /* |
3252 | * Pre-965 chips need a fence register set up in order to | |
3253 | * properly handle blits to/from tiled surfaces. | |
3254 | */ | |
3255 | if (need_fence) { | |
53640e1d | 3256 | ret = i915_gem_object_get_fence_reg(obj, true); |
76446cac | 3257 | if (ret != 0) { |
76446cac JB |
3258 | i915_gem_object_unpin(obj); |
3259 | return ret; | |
3260 | } | |
53640e1d CW |
3261 | |
3262 | dev_priv->fence_regs[obj_priv->fence_reg].gpu = true; | |
76446cac JB |
3263 | } |
3264 | ||
673a394b EA |
3265 | entry->offset = obj_priv->gtt_offset; |
3266 | ||
673a394b EA |
3267 | /* Apply the relocations, using the GTT aperture to avoid cache |
3268 | * flushing requirements. | |
3269 | */ | |
3270 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 3271 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
3272 | struct drm_gem_object *target_obj; |
3273 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
3274 | uint32_t reloc_val, reloc_offset; |
3275 | uint32_t __iomem *reloc_entry; | |
673a394b | 3276 | |
673a394b | 3277 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 3278 | reloc->target_handle); |
673a394b EA |
3279 | if (target_obj == NULL) { |
3280 | i915_gem_object_unpin(obj); | |
bf79cb91 | 3281 | return -ENOENT; |
673a394b | 3282 | } |
23010e43 | 3283 | target_obj_priv = to_intel_bo(target_obj); |
673a394b | 3284 | |
8542a0bb CW |
3285 | #if WATCH_RELOC |
3286 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3287 | "read %08x write %08x gtt %08x " | |
3288 | "presumed %08x delta %08x\n", | |
3289 | __func__, | |
3290 | obj, | |
3291 | (int) reloc->offset, | |
3292 | (int) reloc->target_handle, | |
3293 | (int) reloc->read_domains, | |
3294 | (int) reloc->write_domain, | |
3295 | (int) target_obj_priv->gtt_offset, | |
3296 | (int) reloc->presumed_offset, | |
3297 | reloc->delta); | |
3298 | #endif | |
3299 | ||
673a394b EA |
3300 | /* The target buffer should have appeared before us in the |
3301 | * exec_object list, so it should have a GTT space bound by now. | |
3302 | */ | |
3303 | if (target_obj_priv->gtt_space == NULL) { | |
3304 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 3305 | reloc->target_handle); |
673a394b EA |
3306 | drm_gem_object_unreference(target_obj); |
3307 | i915_gem_object_unpin(obj); | |
3308 | return -EINVAL; | |
3309 | } | |
3310 | ||
8542a0bb | 3311 | /* Validate that the target is in a valid r/w GPU domain */ |
16edd550 DV |
3312 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
3313 | DRM_ERROR("reloc with multiple write domains: " | |
3314 | "obj %p target %d offset %d " | |
3315 | "read %08x write %08x", | |
3316 | obj, reloc->target_handle, | |
3317 | (int) reloc->offset, | |
3318 | reloc->read_domains, | |
3319 | reloc->write_domain); | |
3320 | return -EINVAL; | |
3321 | } | |
40a5f0de EA |
3322 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3323 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3324 | DRM_ERROR("reloc with read/write CPU domains: " |
3325 | "obj %p target %d offset %d " | |
3326 | "read %08x write %08x", | |
40a5f0de EA |
3327 | obj, reloc->target_handle, |
3328 | (int) reloc->offset, | |
3329 | reloc->read_domains, | |
3330 | reloc->write_domain); | |
491152b8 CW |
3331 | drm_gem_object_unreference(target_obj); |
3332 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3333 | return -EINVAL; |
3334 | } | |
40a5f0de EA |
3335 | if (reloc->write_domain && target_obj->pending_write_domain && |
3336 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3337 | DRM_ERROR("Write domain conflict: " |
3338 | "obj %p target %d offset %d " | |
3339 | "new %08x old %08x\n", | |
40a5f0de EA |
3340 | obj, reloc->target_handle, |
3341 | (int) reloc->offset, | |
3342 | reloc->write_domain, | |
673a394b EA |
3343 | target_obj->pending_write_domain); |
3344 | drm_gem_object_unreference(target_obj); | |
3345 | i915_gem_object_unpin(obj); | |
3346 | return -EINVAL; | |
3347 | } | |
3348 | ||
40a5f0de EA |
3349 | target_obj->pending_read_domains |= reloc->read_domains; |
3350 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3351 | |
3352 | /* If the relocation already has the right value in it, no | |
3353 | * more work needs to be done. | |
3354 | */ | |
40a5f0de | 3355 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3356 | drm_gem_object_unreference(target_obj); |
3357 | continue; | |
3358 | } | |
3359 | ||
8542a0bb CW |
3360 | /* Check that the relocation address is valid... */ |
3361 | if (reloc->offset > obj->size - 4) { | |
3362 | DRM_ERROR("Relocation beyond object bounds: " | |
3363 | "obj %p target %d offset %d size %d.\n", | |
3364 | obj, reloc->target_handle, | |
3365 | (int) reloc->offset, (int) obj->size); | |
3366 | drm_gem_object_unreference(target_obj); | |
3367 | i915_gem_object_unpin(obj); | |
3368 | return -EINVAL; | |
3369 | } | |
3370 | if (reloc->offset & 3) { | |
3371 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3372 | "obj %p target %d offset %d.\n", | |
3373 | obj, reloc->target_handle, | |
3374 | (int) reloc->offset); | |
3375 | drm_gem_object_unreference(target_obj); | |
3376 | i915_gem_object_unpin(obj); | |
3377 | return -EINVAL; | |
3378 | } | |
3379 | ||
3380 | /* and points to somewhere within the target object. */ | |
3381 | if (reloc->delta >= target_obj->size) { | |
3382 | DRM_ERROR("Relocation beyond target object bounds: " | |
3383 | "obj %p target %d delta %d size %d.\n", | |
3384 | obj, reloc->target_handle, | |
3385 | (int) reloc->delta, (int) target_obj->size); | |
3386 | drm_gem_object_unreference(target_obj); | |
3387 | i915_gem_object_unpin(obj); | |
3388 | return -EINVAL; | |
3389 | } | |
3390 | ||
2ef7eeaa EA |
3391 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3392 | if (ret != 0) { | |
3393 | drm_gem_object_unreference(target_obj); | |
3394 | i915_gem_object_unpin(obj); | |
3395 | return -EINVAL; | |
673a394b EA |
3396 | } |
3397 | ||
3398 | /* Map the page containing the relocation we're going to | |
3399 | * perform. | |
3400 | */ | |
40a5f0de | 3401 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3402 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3403 | (reloc_offset & | |
fca3ec01 CW |
3404 | ~(PAGE_SIZE - 1)), |
3405 | KM_USER0); | |
3043c60c | 3406 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3407 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3408 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b | 3409 | |
673a394b | 3410 | writel(reloc_val, reloc_entry); |
fca3ec01 | 3411 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
673a394b | 3412 | |
40a5f0de EA |
3413 | /* The updated presumed offset for this entry will be |
3414 | * copied back out to the user. | |
673a394b | 3415 | */ |
40a5f0de | 3416 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3417 | |
3418 | drm_gem_object_unreference(target_obj); | |
3419 | } | |
3420 | ||
673a394b EA |
3421 | return 0; |
3422 | } | |
3423 | ||
673a394b EA |
3424 | /* Throttle our rendering by waiting until the ring has completed our requests |
3425 | * emitted over 20 msec ago. | |
3426 | * | |
b962442e EA |
3427 | * Note that if we were to use the current jiffies each time around the loop, |
3428 | * we wouldn't escape the function with any frames outstanding if the time to | |
3429 | * render a frame was over 20ms. | |
3430 | * | |
673a394b EA |
3431 | * This should get us reasonable parallelism between CPU and GPU but also |
3432 | * relatively low latency when blocking on a particular request to finish. | |
3433 | */ | |
3434 | static int | |
f787a5f5 | 3435 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
673a394b | 3436 | { |
f787a5f5 CW |
3437 | struct drm_i915_private *dev_priv = dev->dev_private; |
3438 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3439 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3440 | struct drm_i915_gem_request *request; |
3441 | struct intel_ring_buffer *ring = NULL; | |
3442 | u32 seqno = 0; | |
3443 | int ret; | |
673a394b | 3444 | |
1c25595f | 3445 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3446 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3447 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3448 | break; | |
3449 | ||
f787a5f5 CW |
3450 | ring = request->ring; |
3451 | seqno = request->seqno; | |
b962442e | 3452 | } |
1c25595f | 3453 | spin_unlock(&file_priv->mm.lock); |
f787a5f5 CW |
3454 | |
3455 | if (seqno == 0) | |
3456 | return 0; | |
3457 | ||
3458 | ret = 0; | |
3459 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { | |
3460 | /* And wait for the seqno passing without holding any locks and | |
3461 | * causing extra latency for others. This is safe as the irq | |
3462 | * generation is designed to be run atomically and so is | |
3463 | * lockless. | |
3464 | */ | |
3465 | ring->user_irq_get(dev, ring); | |
3466 | ret = wait_event_interruptible(ring->irq_queue, | |
3467 | i915_seqno_passed(ring->get_seqno(dev, ring), seqno) | |
3468 | || atomic_read(&dev_priv->mm.wedged)); | |
3469 | ring->user_irq_put(dev, ring); | |
3470 | ||
3471 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) | |
3472 | ret = -EIO; | |
3473 | } | |
3474 | ||
3475 | if (ret == 0) | |
3476 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
b962442e | 3477 | |
673a394b EA |
3478 | return ret; |
3479 | } | |
3480 | ||
40a5f0de | 3481 | static int |
76446cac | 3482 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3483 | uint32_t buffer_count, |
3484 | struct drm_i915_gem_relocation_entry **relocs) | |
3485 | { | |
3486 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3487 | int ret; | |
3488 | ||
3489 | *relocs = NULL; | |
3490 | for (i = 0; i < buffer_count; i++) { | |
3491 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3492 | return -EINVAL; | |
3493 | reloc_count += exec_list[i].relocation_count; | |
3494 | } | |
3495 | ||
8e7d2b2c | 3496 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
76446cac JB |
3497 | if (*relocs == NULL) { |
3498 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); | |
40a5f0de | 3499 | return -ENOMEM; |
76446cac | 3500 | } |
40a5f0de EA |
3501 | |
3502 | for (i = 0; i < buffer_count; i++) { | |
3503 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3504 | ||
3505 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3506 | ||
3507 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3508 | user_relocs, | |
3509 | exec_list[i].relocation_count * | |
3510 | sizeof(**relocs)); | |
3511 | if (ret != 0) { | |
8e7d2b2c | 3512 | drm_free_large(*relocs); |
40a5f0de | 3513 | *relocs = NULL; |
2bc43b5c | 3514 | return -EFAULT; |
40a5f0de EA |
3515 | } |
3516 | ||
3517 | reloc_index += exec_list[i].relocation_count; | |
3518 | } | |
3519 | ||
2bc43b5c | 3520 | return 0; |
40a5f0de EA |
3521 | } |
3522 | ||
3523 | static int | |
76446cac | 3524 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3525 | uint32_t buffer_count, |
3526 | struct drm_i915_gem_relocation_entry *relocs) | |
3527 | { | |
3528 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3529 | int ret = 0; |
40a5f0de | 3530 | |
93533c29 CW |
3531 | if (relocs == NULL) |
3532 | return 0; | |
3533 | ||
40a5f0de EA |
3534 | for (i = 0; i < buffer_count; i++) { |
3535 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3536 | int unwritten; |
40a5f0de EA |
3537 | |
3538 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3539 | ||
2bc43b5c FM |
3540 | unwritten = copy_to_user(user_relocs, |
3541 | &relocs[reloc_count], | |
3542 | exec_list[i].relocation_count * | |
3543 | sizeof(*relocs)); | |
3544 | ||
3545 | if (unwritten) { | |
3546 | ret = -EFAULT; | |
3547 | goto err; | |
40a5f0de EA |
3548 | } |
3549 | ||
3550 | reloc_count += exec_list[i].relocation_count; | |
3551 | } | |
3552 | ||
2bc43b5c | 3553 | err: |
8e7d2b2c | 3554 | drm_free_large(relocs); |
40a5f0de EA |
3555 | |
3556 | return ret; | |
3557 | } | |
3558 | ||
83d60795 | 3559 | static int |
76446cac | 3560 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
83d60795 CW |
3561 | uint64_t exec_offset) |
3562 | { | |
3563 | uint32_t exec_start, exec_len; | |
3564 | ||
3565 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3566 | exec_len = (uint32_t) exec->batch_len; | |
3567 | ||
3568 | if ((exec_start | exec_len) & 0x7) | |
3569 | return -EINVAL; | |
3570 | ||
3571 | if (!exec_start) | |
3572 | return -EINVAL; | |
3573 | ||
3574 | return 0; | |
3575 | } | |
3576 | ||
e6c3a2a6 | 3577 | static int |
6b95a207 KH |
3578 | i915_gem_wait_for_pending_flip(struct drm_device *dev, |
3579 | struct drm_gem_object **object_list, | |
3580 | int count) | |
3581 | { | |
3582 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3583 | struct drm_i915_gem_object *obj_priv; | |
3584 | DEFINE_WAIT(wait); | |
3585 | int i, ret = 0; | |
3586 | ||
3587 | for (;;) { | |
3588 | prepare_to_wait(&dev_priv->pending_flip_queue, | |
3589 | &wait, TASK_INTERRUPTIBLE); | |
3590 | for (i = 0; i < count; i++) { | |
23010e43 | 3591 | obj_priv = to_intel_bo(object_list[i]); |
6b95a207 KH |
3592 | if (atomic_read(&obj_priv->pending_flip) > 0) |
3593 | break; | |
3594 | } | |
3595 | if (i == count) | |
3596 | break; | |
3597 | ||
3598 | if (!signal_pending(current)) { | |
3599 | mutex_unlock(&dev->struct_mutex); | |
3600 | schedule(); | |
3601 | mutex_lock(&dev->struct_mutex); | |
3602 | continue; | |
3603 | } | |
3604 | ret = -ERESTARTSYS; | |
3605 | break; | |
3606 | } | |
3607 | finish_wait(&dev_priv->pending_flip_queue, &wait); | |
3608 | ||
3609 | return ret; | |
3610 | } | |
3611 | ||
8dc5d147 | 3612 | static int |
76446cac JB |
3613 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
3614 | struct drm_file *file_priv, | |
3615 | struct drm_i915_gem_execbuffer2 *args, | |
3616 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3617 | { |
3618 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3619 | struct drm_gem_object **object_list = NULL; |
3620 | struct drm_gem_object *batch_obj; | |
b70d11da | 3621 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3622 | struct drm_clip_rect *cliprects = NULL; |
93533c29 | 3623 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
8dc5d147 | 3624 | struct drm_i915_gem_request *request = NULL; |
30dbf0c0 | 3625 | int ret, ret2, i, pinned = 0; |
673a394b | 3626 | uint64_t exec_offset; |
5c12a07e | 3627 | uint32_t reloc_index; |
6b95a207 | 3628 | int pin_tries, flips; |
673a394b | 3629 | |
852835f3 ZN |
3630 | struct intel_ring_buffer *ring = NULL; |
3631 | ||
30dbf0c0 CW |
3632 | ret = i915_gem_check_is_wedged(dev); |
3633 | if (ret) | |
3634 | return ret; | |
3635 | ||
673a394b EA |
3636 | #if WATCH_EXEC |
3637 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3638 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3639 | #endif | |
d1b851fc ZN |
3640 | if (args->flags & I915_EXEC_BSD) { |
3641 | if (!HAS_BSD(dev)) { | |
3642 | DRM_ERROR("execbuf with wrong flag\n"); | |
3643 | return -EINVAL; | |
3644 | } | |
3645 | ring = &dev_priv->bsd_ring; | |
3646 | } else { | |
3647 | ring = &dev_priv->render_ring; | |
3648 | } | |
3649 | ||
4f481ed2 EA |
3650 | if (args->buffer_count < 1) { |
3651 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3652 | return -EINVAL; | |
3653 | } | |
c8e0f93a | 3654 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3655 | if (object_list == NULL) { |
3656 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3657 | args->buffer_count); |
3658 | ret = -ENOMEM; | |
3659 | goto pre_mutex_err; | |
3660 | } | |
673a394b | 3661 | |
201361a5 | 3662 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3663 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3664 | GFP_KERNEL); | |
a40e8d31 OA |
3665 | if (cliprects == NULL) { |
3666 | ret = -ENOMEM; | |
201361a5 | 3667 | goto pre_mutex_err; |
a40e8d31 | 3668 | } |
201361a5 EA |
3669 | |
3670 | ret = copy_from_user(cliprects, | |
3671 | (struct drm_clip_rect __user *) | |
3672 | (uintptr_t) args->cliprects_ptr, | |
3673 | sizeof(*cliprects) * args->num_cliprects); | |
3674 | if (ret != 0) { | |
3675 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3676 | args->num_cliprects, ret); | |
c877cdce | 3677 | ret = -EFAULT; |
201361a5 EA |
3678 | goto pre_mutex_err; |
3679 | } | |
3680 | } | |
3681 | ||
8dc5d147 CW |
3682 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3683 | if (request == NULL) { | |
3684 | ret = -ENOMEM; | |
3685 | goto pre_mutex_err; | |
3686 | } | |
3687 | ||
40a5f0de EA |
3688 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3689 | &relocs); | |
3690 | if (ret != 0) | |
3691 | goto pre_mutex_err; | |
3692 | ||
76c1dec1 CW |
3693 | ret = i915_mutex_lock_interruptible(dev); |
3694 | if (ret) | |
3695 | goto pre_mutex_err; | |
673a394b | 3696 | |
673a394b | 3697 | if (dev_priv->mm.suspended) { |
673a394b | 3698 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3699 | ret = -EBUSY; |
3700 | goto pre_mutex_err; | |
673a394b EA |
3701 | } |
3702 | ||
ac94a962 | 3703 | /* Look up object handles */ |
6b95a207 | 3704 | flips = 0; |
673a394b EA |
3705 | for (i = 0; i < args->buffer_count; i++) { |
3706 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3707 | exec_list[i].handle); | |
3708 | if (object_list[i] == NULL) { | |
3709 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3710 | exec_list[i].handle, i); | |
0ce907f8 CW |
3711 | /* prevent error path from reading uninitialized data */ |
3712 | args->buffer_count = i + 1; | |
bf79cb91 | 3713 | ret = -ENOENT; |
673a394b EA |
3714 | goto err; |
3715 | } | |
b70d11da | 3716 | |
23010e43 | 3717 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3718 | if (obj_priv->in_execbuffer) { |
3719 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3720 | object_list[i]); | |
0ce907f8 CW |
3721 | /* prevent error path from reading uninitialized data */ |
3722 | args->buffer_count = i + 1; | |
bf79cb91 | 3723 | ret = -EINVAL; |
b70d11da KH |
3724 | goto err; |
3725 | } | |
3726 | obj_priv->in_execbuffer = true; | |
6b95a207 KH |
3727 | flips += atomic_read(&obj_priv->pending_flip); |
3728 | } | |
3729 | ||
3730 | if (flips > 0) { | |
3731 | ret = i915_gem_wait_for_pending_flip(dev, object_list, | |
3732 | args->buffer_count); | |
3733 | if (ret) | |
3734 | goto err; | |
ac94a962 | 3735 | } |
673a394b | 3736 | |
ac94a962 KP |
3737 | /* Pin and relocate */ |
3738 | for (pin_tries = 0; ; pin_tries++) { | |
3739 | ret = 0; | |
40a5f0de EA |
3740 | reloc_index = 0; |
3741 | ||
ac94a962 KP |
3742 | for (i = 0; i < args->buffer_count; i++) { |
3743 | object_list[i]->pending_read_domains = 0; | |
3744 | object_list[i]->pending_write_domain = 0; | |
3745 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3746 | file_priv, | |
40a5f0de EA |
3747 | &exec_list[i], |
3748 | &relocs[reloc_index]); | |
ac94a962 KP |
3749 | if (ret) |
3750 | break; | |
3751 | pinned = i + 1; | |
40a5f0de | 3752 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3753 | } |
3754 | /* success */ | |
3755 | if (ret == 0) | |
3756 | break; | |
3757 | ||
3758 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3759 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3760 | if (ret != -ERESTARTSYS) { |
3761 | unsigned long long total_size = 0; | |
3d1cc470 CW |
3762 | int num_fences = 0; |
3763 | for (i = 0; i < args->buffer_count; i++) { | |
43b27f40 | 3764 | obj_priv = to_intel_bo(object_list[i]); |
3d1cc470 | 3765 | |
07f73f69 | 3766 | total_size += object_list[i]->size; |
3d1cc470 CW |
3767 | num_fences += |
3768 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && | |
3769 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3770 | } | |
3771 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", | |
07f73f69 | 3772 | pinned+1, args->buffer_count, |
3d1cc470 CW |
3773 | total_size, num_fences, |
3774 | ret); | |
07f73f69 CW |
3775 | DRM_ERROR("%d objects [%d pinned], " |
3776 | "%d object bytes [%d pinned], " | |
3777 | "%d/%d gtt bytes\n", | |
3778 | atomic_read(&dev->object_count), | |
3779 | atomic_read(&dev->pin_count), | |
3780 | atomic_read(&dev->object_memory), | |
3781 | atomic_read(&dev->pin_memory), | |
3782 | atomic_read(&dev->gtt_memory), | |
3783 | dev->gtt_total); | |
3784 | } | |
673a394b EA |
3785 | goto err; |
3786 | } | |
ac94a962 KP |
3787 | |
3788 | /* unpin all of our buffers */ | |
3789 | for (i = 0; i < pinned; i++) | |
3790 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3791 | pinned = 0; |
ac94a962 KP |
3792 | |
3793 | /* evict everyone we can from the aperture */ | |
3794 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3795 | if (ret && ret != -ENOSPC) |
ac94a962 | 3796 | goto err; |
673a394b EA |
3797 | } |
3798 | ||
3799 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3800 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3801 | if (batch_obj->pending_write_domain) { |
3802 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3803 | ret = -EINVAL; | |
3804 | goto err; | |
3805 | } | |
3806 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3807 | |
83d60795 CW |
3808 | /* Sanity check the batch buffer, prior to moving objects */ |
3809 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3810 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3811 | if (ret != 0) { | |
3812 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3813 | goto err; | |
3814 | } | |
3815 | ||
646f0f6e KP |
3816 | /* Zero the global flush/invalidate flags. These |
3817 | * will be modified as new domains are computed | |
3818 | * for each object | |
3819 | */ | |
3820 | dev->invalidate_domains = 0; | |
3821 | dev->flush_domains = 0; | |
9220434a | 3822 | dev_priv->mm.flush_rings = 0; |
646f0f6e | 3823 | |
673a394b EA |
3824 | for (i = 0; i < args->buffer_count; i++) { |
3825 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3826 | |
646f0f6e | 3827 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3828 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3829 | } |
3830 | ||
646f0f6e KP |
3831 | if (dev->invalidate_domains | dev->flush_domains) { |
3832 | #if WATCH_EXEC | |
3833 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3834 | __func__, | |
3835 | dev->invalidate_domains, | |
3836 | dev->flush_domains); | |
3837 | #endif | |
c78ec30b | 3838 | i915_gem_flush(dev, file_priv, |
646f0f6e | 3839 | dev->invalidate_domains, |
9220434a CW |
3840 | dev->flush_domains, |
3841 | dev_priv->mm.flush_rings); | |
a6910434 DV |
3842 | } |
3843 | ||
efbeed96 EA |
3844 | for (i = 0; i < args->buffer_count; i++) { |
3845 | struct drm_gem_object *obj = object_list[i]; | |
23010e43 | 3846 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3847 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3848 | |
3849 | obj->write_domain = obj->pending_write_domain; | |
99fcb766 DV |
3850 | if (obj->write_domain) |
3851 | list_move_tail(&obj_priv->gpu_write_list, | |
3852 | &dev_priv->mm.gpu_write_list); | |
3853 | else | |
3854 | list_del_init(&obj_priv->gpu_write_list); | |
3855 | ||
1c5d22f7 CW |
3856 | trace_i915_gem_object_change_domain(obj, |
3857 | obj->read_domains, | |
3858 | old_write_domain); | |
efbeed96 EA |
3859 | } |
3860 | ||
673a394b EA |
3861 | #if WATCH_COHERENCY |
3862 | for (i = 0; i < args->buffer_count; i++) { | |
3863 | i915_gem_object_check_coherency(object_list[i], | |
3864 | exec_list[i].handle); | |
3865 | } | |
3866 | #endif | |
3867 | ||
673a394b | 3868 | #if WATCH_EXEC |
6911a9b8 | 3869 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3870 | args->batch_len, |
3871 | __func__, | |
3872 | ~0); | |
3873 | #endif | |
3874 | ||
673a394b | 3875 | /* Exec the batchbuffer */ |
852835f3 ZN |
3876 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
3877 | cliprects, exec_offset); | |
673a394b EA |
3878 | if (ret) { |
3879 | DRM_ERROR("dispatch failed %d\n", ret); | |
3880 | goto err; | |
3881 | } | |
3882 | ||
3883 | /* | |
3884 | * Ensure that the commands in the batch buffer are | |
3885 | * finished before the interrupt fires | |
3886 | */ | |
8a1a49f9 | 3887 | i915_retire_commands(dev, ring); |
673a394b | 3888 | |
617dbe27 DV |
3889 | for (i = 0; i < args->buffer_count; i++) { |
3890 | struct drm_gem_object *obj = object_list[i]; | |
3891 | obj_priv = to_intel_bo(obj); | |
3892 | ||
3893 | i915_gem_object_move_to_active(obj, ring); | |
617dbe27 | 3894 | } |
a56ba56c | 3895 | |
5c12a07e | 3896 | i915_add_request(dev, file_priv, request, ring); |
8dc5d147 | 3897 | request = NULL; |
673a394b | 3898 | |
673a394b | 3899 | err: |
aad87dff JL |
3900 | for (i = 0; i < pinned; i++) |
3901 | i915_gem_object_unpin(object_list[i]); | |
3902 | ||
b70d11da KH |
3903 | for (i = 0; i < args->buffer_count; i++) { |
3904 | if (object_list[i]) { | |
23010e43 | 3905 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3906 | obj_priv->in_execbuffer = false; |
3907 | } | |
aad87dff | 3908 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3909 | } |
673a394b | 3910 | |
673a394b EA |
3911 | mutex_unlock(&dev->struct_mutex); |
3912 | ||
93533c29 | 3913 | pre_mutex_err: |
40a5f0de EA |
3914 | /* Copy the updated relocations out regardless of current error |
3915 | * state. Failure to update the relocs would mean that the next | |
3916 | * time userland calls execbuf, it would do so with presumed offset | |
3917 | * state that didn't match the actual object state. | |
3918 | */ | |
3919 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3920 | relocs); | |
3921 | if (ret2 != 0) { | |
3922 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3923 | ||
3924 | if (ret == 0) | |
3925 | ret = ret2; | |
3926 | } | |
3927 | ||
8e7d2b2c | 3928 | drm_free_large(object_list); |
9a298b2a | 3929 | kfree(cliprects); |
8dc5d147 | 3930 | kfree(request); |
673a394b EA |
3931 | |
3932 | return ret; | |
3933 | } | |
3934 | ||
76446cac JB |
3935 | /* |
3936 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3937 | * list array and passes it to the real function. | |
3938 | */ | |
3939 | int | |
3940 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3941 | struct drm_file *file_priv) | |
3942 | { | |
3943 | struct drm_i915_gem_execbuffer *args = data; | |
3944 | struct drm_i915_gem_execbuffer2 exec2; | |
3945 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3946 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3947 | int ret, i; | |
3948 | ||
3949 | #if WATCH_EXEC | |
3950 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3951 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3952 | #endif | |
3953 | ||
3954 | if (args->buffer_count < 1) { | |
3955 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3956 | return -EINVAL; | |
3957 | } | |
3958 | ||
3959 | /* Copy in the exec list from userland */ | |
3960 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3961 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3962 | if (exec_list == NULL || exec2_list == NULL) { | |
3963 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3964 | args->buffer_count); | |
3965 | drm_free_large(exec_list); | |
3966 | drm_free_large(exec2_list); | |
3967 | return -ENOMEM; | |
3968 | } | |
3969 | ret = copy_from_user(exec_list, | |
3970 | (struct drm_i915_relocation_entry __user *) | |
3971 | (uintptr_t) args->buffers_ptr, | |
3972 | sizeof(*exec_list) * args->buffer_count); | |
3973 | if (ret != 0) { | |
3974 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3975 | args->buffer_count, ret); | |
3976 | drm_free_large(exec_list); | |
3977 | drm_free_large(exec2_list); | |
3978 | return -EFAULT; | |
3979 | } | |
3980 | ||
3981 | for (i = 0; i < args->buffer_count; i++) { | |
3982 | exec2_list[i].handle = exec_list[i].handle; | |
3983 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3984 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3985 | exec2_list[i].alignment = exec_list[i].alignment; | |
3986 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 3987 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
3988 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
3989 | else | |
3990 | exec2_list[i].flags = 0; | |
3991 | } | |
3992 | ||
3993 | exec2.buffers_ptr = args->buffers_ptr; | |
3994 | exec2.buffer_count = args->buffer_count; | |
3995 | exec2.batch_start_offset = args->batch_start_offset; | |
3996 | exec2.batch_len = args->batch_len; | |
3997 | exec2.DR1 = args->DR1; | |
3998 | exec2.DR4 = args->DR4; | |
3999 | exec2.num_cliprects = args->num_cliprects; | |
4000 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4001 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4002 | |
4003 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4004 | if (!ret) { | |
4005 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4006 | for (i = 0; i < args->buffer_count; i++) | |
4007 | exec_list[i].offset = exec2_list[i].offset; | |
4008 | /* ... and back out to userspace */ | |
4009 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4010 | (uintptr_t) args->buffers_ptr, | |
4011 | exec_list, | |
4012 | sizeof(*exec_list) * args->buffer_count); | |
4013 | if (ret) { | |
4014 | ret = -EFAULT; | |
4015 | DRM_ERROR("failed to copy %d exec entries " | |
4016 | "back to user (%d)\n", | |
4017 | args->buffer_count, ret); | |
4018 | } | |
76446cac JB |
4019 | } |
4020 | ||
4021 | drm_free_large(exec_list); | |
4022 | drm_free_large(exec2_list); | |
4023 | return ret; | |
4024 | } | |
4025 | ||
4026 | int | |
4027 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4028 | struct drm_file *file_priv) | |
4029 | { | |
4030 | struct drm_i915_gem_execbuffer2 *args = data; | |
4031 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4032 | int ret; | |
4033 | ||
4034 | #if WATCH_EXEC | |
4035 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4036 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4037 | #endif | |
4038 | ||
4039 | if (args->buffer_count < 1) { | |
4040 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4041 | return -EINVAL; | |
4042 | } | |
4043 | ||
4044 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4045 | if (exec2_list == NULL) { | |
4046 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4047 | args->buffer_count); | |
4048 | return -ENOMEM; | |
4049 | } | |
4050 | ret = copy_from_user(exec2_list, | |
4051 | (struct drm_i915_relocation_entry __user *) | |
4052 | (uintptr_t) args->buffers_ptr, | |
4053 | sizeof(*exec2_list) * args->buffer_count); | |
4054 | if (ret != 0) { | |
4055 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4056 | args->buffer_count, ret); | |
4057 | drm_free_large(exec2_list); | |
4058 | return -EFAULT; | |
4059 | } | |
4060 | ||
4061 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4062 | if (!ret) { | |
4063 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4064 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4065 | (uintptr_t) args->buffers_ptr, | |
4066 | exec2_list, | |
4067 | sizeof(*exec2_list) * args->buffer_count); | |
4068 | if (ret) { | |
4069 | ret = -EFAULT; | |
4070 | DRM_ERROR("failed to copy %d exec entries " | |
4071 | "back to user (%d)\n", | |
4072 | args->buffer_count, ret); | |
4073 | } | |
4074 | } | |
4075 | ||
4076 | drm_free_large(exec2_list); | |
4077 | return ret; | |
4078 | } | |
4079 | ||
673a394b EA |
4080 | int |
4081 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
4082 | { | |
4083 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4084 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4085 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4086 | int ret; |
4087 | ||
778c3544 | 4088 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4089 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4090 | |
4091 | if (obj_priv->gtt_space != NULL) { | |
4092 | if (alignment == 0) | |
4093 | alignment = i915_gem_get_gtt_alignment(obj); | |
4094 | if (obj_priv->gtt_offset & (alignment - 1)) { | |
ae7d49d8 CW |
4095 | WARN(obj_priv->pin_count, |
4096 | "bo is already pinned with incorrect alignment:" | |
4097 | " offset=%x, req.alignment=%x\n", | |
4098 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4099 | ret = i915_gem_object_unbind(obj); |
4100 | if (ret) | |
4101 | return ret; | |
4102 | } | |
4103 | } | |
4104 | ||
673a394b EA |
4105 | if (obj_priv->gtt_space == NULL) { |
4106 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 4107 | if (ret) |
673a394b | 4108 | return ret; |
22c344e9 | 4109 | } |
76446cac | 4110 | |
673a394b EA |
4111 | obj_priv->pin_count++; |
4112 | ||
4113 | /* If the object is not active and not pending a flush, | |
4114 | * remove it from the inactive list | |
4115 | */ | |
4116 | if (obj_priv->pin_count == 1) { | |
4117 | atomic_inc(&dev->pin_count); | |
4118 | atomic_add(obj->size, &dev->pin_memory); | |
f13d3f73 CW |
4119 | if (!obj_priv->active) |
4120 | list_move_tail(&obj_priv->list, | |
4121 | &dev_priv->mm.pinned_list); | |
673a394b | 4122 | } |
673a394b | 4123 | |
23bc5982 | 4124 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4125 | return 0; |
4126 | } | |
4127 | ||
4128 | void | |
4129 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4130 | { | |
4131 | struct drm_device *dev = obj->dev; | |
4132 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4133 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4134 | |
23bc5982 | 4135 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4136 | obj_priv->pin_count--; |
4137 | BUG_ON(obj_priv->pin_count < 0); | |
4138 | BUG_ON(obj_priv->gtt_space == NULL); | |
4139 | ||
4140 | /* If the object is no longer pinned, and is | |
4141 | * neither active nor being flushed, then stick it on | |
4142 | * the inactive list | |
4143 | */ | |
4144 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4145 | if (!obj_priv->active) |
673a394b EA |
4146 | list_move_tail(&obj_priv->list, |
4147 | &dev_priv->mm.inactive_list); | |
4148 | atomic_dec(&dev->pin_count); | |
4149 | atomic_sub(obj->size, &dev->pin_memory); | |
4150 | } | |
23bc5982 | 4151 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4152 | } |
4153 | ||
4154 | int | |
4155 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4156 | struct drm_file *file_priv) | |
4157 | { | |
4158 | struct drm_i915_gem_pin *args = data; | |
4159 | struct drm_gem_object *obj; | |
4160 | struct drm_i915_gem_object *obj_priv; | |
4161 | int ret; | |
4162 | ||
673a394b EA |
4163 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4164 | if (obj == NULL) { | |
4165 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
4166 | args->handle); | |
bf79cb91 | 4167 | return -ENOENT; |
673a394b | 4168 | } |
23010e43 | 4169 | obj_priv = to_intel_bo(obj); |
673a394b | 4170 | |
76c1dec1 CW |
4171 | ret = i915_mutex_lock_interruptible(dev); |
4172 | if (ret) { | |
4173 | drm_gem_object_unreference_unlocked(obj); | |
4174 | return ret; | |
4175 | } | |
4176 | ||
bb6baf76 CW |
4177 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4178 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
4179 | drm_gem_object_unreference(obj); |
4180 | mutex_unlock(&dev->struct_mutex); | |
4181 | return -EINVAL; | |
4182 | } | |
4183 | ||
79e53945 JB |
4184 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4185 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4186 | args->handle); | |
96dec61d | 4187 | drm_gem_object_unreference(obj); |
673a394b | 4188 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
4189 | return -EINVAL; |
4190 | } | |
4191 | ||
4192 | obj_priv->user_pin_count++; | |
4193 | obj_priv->pin_filp = file_priv; | |
4194 | if (obj_priv->user_pin_count == 1) { | |
4195 | ret = i915_gem_object_pin(obj, args->alignment); | |
4196 | if (ret != 0) { | |
4197 | drm_gem_object_unreference(obj); | |
4198 | mutex_unlock(&dev->struct_mutex); | |
4199 | return ret; | |
4200 | } | |
673a394b EA |
4201 | } |
4202 | ||
4203 | /* XXX - flush the CPU caches for pinned objects | |
4204 | * as the X server doesn't manage domains yet | |
4205 | */ | |
e47c68e9 | 4206 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
4207 | args->offset = obj_priv->gtt_offset; |
4208 | drm_gem_object_unreference(obj); | |
4209 | mutex_unlock(&dev->struct_mutex); | |
4210 | ||
4211 | return 0; | |
4212 | } | |
4213 | ||
4214 | int | |
4215 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4216 | struct drm_file *file_priv) | |
4217 | { | |
4218 | struct drm_i915_gem_pin *args = data; | |
4219 | struct drm_gem_object *obj; | |
79e53945 | 4220 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4221 | int ret; |
673a394b EA |
4222 | |
4223 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4224 | if (obj == NULL) { | |
4225 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
4226 | args->handle); | |
bf79cb91 | 4227 | return -ENOENT; |
673a394b EA |
4228 | } |
4229 | ||
23010e43 | 4230 | obj_priv = to_intel_bo(obj); |
76c1dec1 CW |
4231 | |
4232 | ret = i915_mutex_lock_interruptible(dev); | |
4233 | if (ret) { | |
4234 | drm_gem_object_unreference_unlocked(obj); | |
4235 | return ret; | |
4236 | } | |
4237 | ||
79e53945 JB |
4238 | if (obj_priv->pin_filp != file_priv) { |
4239 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4240 | args->handle); | |
4241 | drm_gem_object_unreference(obj); | |
4242 | mutex_unlock(&dev->struct_mutex); | |
4243 | return -EINVAL; | |
4244 | } | |
4245 | obj_priv->user_pin_count--; | |
4246 | if (obj_priv->user_pin_count == 0) { | |
4247 | obj_priv->pin_filp = NULL; | |
4248 | i915_gem_object_unpin(obj); | |
4249 | } | |
673a394b EA |
4250 | |
4251 | drm_gem_object_unreference(obj); | |
4252 | mutex_unlock(&dev->struct_mutex); | |
4253 | return 0; | |
4254 | } | |
4255 | ||
4256 | int | |
4257 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4258 | struct drm_file *file_priv) | |
4259 | { | |
4260 | struct drm_i915_gem_busy *args = data; | |
4261 | struct drm_gem_object *obj; | |
4262 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4263 | int ret; |
4264 | ||
673a394b EA |
4265 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4266 | if (obj == NULL) { | |
4267 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4268 | args->handle); | |
bf79cb91 | 4269 | return -ENOENT; |
673a394b EA |
4270 | } |
4271 | ||
76c1dec1 CW |
4272 | ret = i915_mutex_lock_interruptible(dev); |
4273 | if (ret) { | |
4274 | drm_gem_object_unreference_unlocked(obj); | |
4275 | return ret; | |
30dbf0c0 CW |
4276 | } |
4277 | ||
0be555b6 CW |
4278 | /* Count all active objects as busy, even if they are currently not used |
4279 | * by the gpu. Users of this interface expect objects to eventually | |
4280 | * become non-busy without any further actions, therefore emit any | |
4281 | * necessary flushes here. | |
c4de0a5d | 4282 | */ |
0be555b6 CW |
4283 | obj_priv = to_intel_bo(obj); |
4284 | args->busy = obj_priv->active; | |
4285 | if (args->busy) { | |
4286 | /* Unconditionally flush objects, even when the gpu still uses this | |
4287 | * object. Userspace calling this function indicates that it wants to | |
4288 | * use this buffer rather sooner than later, so issuing the required | |
4289 | * flush earlier is beneficial. | |
4290 | */ | |
c78ec30b CW |
4291 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4292 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4293 | obj_priv->ring, |
4294 | 0, obj->write_domain); | |
0be555b6 CW |
4295 | |
4296 | /* Update the active list for the hardware's current position. | |
4297 | * Otherwise this only updates on a delayed timer or when irqs | |
4298 | * are actually unmasked, and our working set ends up being | |
4299 | * larger than required. | |
4300 | */ | |
4301 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4302 | ||
4303 | args->busy = obj_priv->active; | |
4304 | } | |
673a394b EA |
4305 | |
4306 | drm_gem_object_unreference(obj); | |
4307 | mutex_unlock(&dev->struct_mutex); | |
76c1dec1 | 4308 | return 0; |
673a394b EA |
4309 | } |
4310 | ||
4311 | int | |
4312 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4313 | struct drm_file *file_priv) | |
4314 | { | |
4315 | return i915_gem_ring_throttle(dev, file_priv); | |
4316 | } | |
4317 | ||
3ef94daa CW |
4318 | int |
4319 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4320 | struct drm_file *file_priv) | |
4321 | { | |
4322 | struct drm_i915_gem_madvise *args = data; | |
4323 | struct drm_gem_object *obj; | |
4324 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4325 | int ret; |
3ef94daa CW |
4326 | |
4327 | switch (args->madv) { | |
4328 | case I915_MADV_DONTNEED: | |
4329 | case I915_MADV_WILLNEED: | |
4330 | break; | |
4331 | default: | |
4332 | return -EINVAL; | |
4333 | } | |
4334 | ||
4335 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4336 | if (obj == NULL) { | |
4337 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4338 | args->handle); | |
bf79cb91 | 4339 | return -ENOENT; |
3ef94daa | 4340 | } |
23010e43 | 4341 | obj_priv = to_intel_bo(obj); |
3ef94daa | 4342 | |
76c1dec1 CW |
4343 | ret = i915_mutex_lock_interruptible(dev); |
4344 | if (ret) { | |
4345 | drm_gem_object_unreference_unlocked(obj); | |
4346 | return ret; | |
4347 | } | |
4348 | ||
3ef94daa CW |
4349 | if (obj_priv->pin_count) { |
4350 | drm_gem_object_unreference(obj); | |
4351 | mutex_unlock(&dev->struct_mutex); | |
4352 | ||
4353 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4354 | return -EINVAL; | |
4355 | } | |
4356 | ||
bb6baf76 CW |
4357 | if (obj_priv->madv != __I915_MADV_PURGED) |
4358 | obj_priv->madv = args->madv; | |
3ef94daa | 4359 | |
2d7ef395 CW |
4360 | /* if the object is no longer bound, discard its backing storage */ |
4361 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4362 | obj_priv->gtt_space == NULL) | |
4363 | i915_gem_object_truncate(obj); | |
4364 | ||
bb6baf76 CW |
4365 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4366 | ||
3ef94daa CW |
4367 | drm_gem_object_unreference(obj); |
4368 | mutex_unlock(&dev->struct_mutex); | |
4369 | ||
4370 | return 0; | |
4371 | } | |
4372 | ||
ac52bc56 DV |
4373 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4374 | size_t size) | |
4375 | { | |
c397b908 | 4376 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4377 | |
c397b908 DV |
4378 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4379 | if (obj == NULL) | |
4380 | return NULL; | |
673a394b | 4381 | |
c397b908 DV |
4382 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4383 | kfree(obj); | |
4384 | return NULL; | |
4385 | } | |
673a394b | 4386 | |
c397b908 DV |
4387 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4388 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4389 | |
c397b908 | 4390 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4391 | obj->base.driver_private = NULL; |
c397b908 DV |
4392 | obj->fence_reg = I915_FENCE_REG_NONE; |
4393 | INIT_LIST_HEAD(&obj->list); | |
4394 | INIT_LIST_HEAD(&obj->gpu_write_list); | |
c397b908 | 4395 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4396 | |
c397b908 DV |
4397 | trace_i915_gem_object_create(&obj->base); |
4398 | ||
4399 | return &obj->base; | |
4400 | } | |
4401 | ||
4402 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4403 | { | |
4404 | BUG(); | |
de151cf6 | 4405 | |
673a394b EA |
4406 | return 0; |
4407 | } | |
4408 | ||
be72615b | 4409 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4410 | { |
de151cf6 | 4411 | struct drm_device *dev = obj->dev; |
be72615b | 4412 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4413 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4414 | int ret; |
673a394b | 4415 | |
be72615b CW |
4416 | ret = i915_gem_object_unbind(obj); |
4417 | if (ret == -ERESTARTSYS) { | |
4418 | list_move(&obj_priv->list, | |
4419 | &dev_priv->mm.deferred_free_list); | |
4420 | return; | |
4421 | } | |
673a394b | 4422 | |
7e616158 CW |
4423 | if (obj_priv->mmap_offset) |
4424 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4425 | |
c397b908 DV |
4426 | drm_gem_object_release(obj); |
4427 | ||
9a298b2a | 4428 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4429 | kfree(obj_priv->bit_17); |
c397b908 | 4430 | kfree(obj_priv); |
673a394b EA |
4431 | } |
4432 | ||
be72615b CW |
4433 | void i915_gem_free_object(struct drm_gem_object *obj) |
4434 | { | |
4435 | struct drm_device *dev = obj->dev; | |
4436 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4437 | ||
4438 | trace_i915_gem_object_destroy(obj); | |
4439 | ||
4440 | while (obj_priv->pin_count > 0) | |
4441 | i915_gem_object_unpin(obj); | |
4442 | ||
4443 | if (obj_priv->phys_obj) | |
4444 | i915_gem_detach_phys_object(dev, obj); | |
4445 | ||
4446 | i915_gem_free_object_tail(obj); | |
4447 | } | |
4448 | ||
29105ccc CW |
4449 | int |
4450 | i915_gem_idle(struct drm_device *dev) | |
4451 | { | |
4452 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4453 | int ret; | |
28dfe52a | 4454 | |
29105ccc | 4455 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4456 | |
8187a2b7 | 4457 | if (dev_priv->mm.suspended || |
d1b851fc ZN |
4458 | (dev_priv->render_ring.gem_object == NULL) || |
4459 | (HAS_BSD(dev) && | |
4460 | dev_priv->bsd_ring.gem_object == NULL)) { | |
29105ccc CW |
4461 | mutex_unlock(&dev->struct_mutex); |
4462 | return 0; | |
28dfe52a EA |
4463 | } |
4464 | ||
29105ccc | 4465 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4466 | if (ret) { |
4467 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4468 | return ret; |
6dbe2772 | 4469 | } |
673a394b | 4470 | |
29105ccc CW |
4471 | /* Under UMS, be paranoid and evict. */ |
4472 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4473 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4474 | if (ret) { |
4475 | mutex_unlock(&dev->struct_mutex); | |
4476 | return ret; | |
4477 | } | |
4478 | } | |
4479 | ||
4480 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4481 | * We need to replace this with a semaphore, or something. | |
4482 | * And not confound mm.suspended! | |
4483 | */ | |
4484 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4485 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4486 | |
4487 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4488 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4489 | |
6dbe2772 KP |
4490 | mutex_unlock(&dev->struct_mutex); |
4491 | ||
29105ccc CW |
4492 | /* Cancel the retire work handler, which should be idle now. */ |
4493 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4494 | ||
673a394b EA |
4495 | return 0; |
4496 | } | |
4497 | ||
e552eb70 JB |
4498 | /* |
4499 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4500 | * over cache flushing. | |
4501 | */ | |
8187a2b7 | 4502 | static int |
e552eb70 JB |
4503 | i915_gem_init_pipe_control(struct drm_device *dev) |
4504 | { | |
4505 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4506 | struct drm_gem_object *obj; | |
4507 | struct drm_i915_gem_object *obj_priv; | |
4508 | int ret; | |
4509 | ||
34dc4d44 | 4510 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4511 | if (obj == NULL) { |
4512 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4513 | ret = -ENOMEM; | |
4514 | goto err; | |
4515 | } | |
4516 | obj_priv = to_intel_bo(obj); | |
4517 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4518 | ||
4519 | ret = i915_gem_object_pin(obj, 4096); | |
4520 | if (ret) | |
4521 | goto err_unref; | |
4522 | ||
4523 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4524 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4525 | if (dev_priv->seqno_page == NULL) | |
4526 | goto err_unpin; | |
4527 | ||
4528 | dev_priv->seqno_obj = obj; | |
4529 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4530 | ||
4531 | return 0; | |
4532 | ||
4533 | err_unpin: | |
4534 | i915_gem_object_unpin(obj); | |
4535 | err_unref: | |
4536 | drm_gem_object_unreference(obj); | |
4537 | err: | |
4538 | return ret; | |
4539 | } | |
4540 | ||
8187a2b7 ZN |
4541 | |
4542 | static void | |
e552eb70 JB |
4543 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4544 | { | |
4545 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4546 | struct drm_gem_object *obj; | |
4547 | struct drm_i915_gem_object *obj_priv; | |
4548 | ||
4549 | obj = dev_priv->seqno_obj; | |
4550 | obj_priv = to_intel_bo(obj); | |
4551 | kunmap(obj_priv->pages[0]); | |
4552 | i915_gem_object_unpin(obj); | |
4553 | drm_gem_object_unreference(obj); | |
4554 | dev_priv->seqno_obj = NULL; | |
4555 | ||
4556 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4557 | } |
4558 | ||
8187a2b7 ZN |
4559 | int |
4560 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4561 | { | |
4562 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4563 | int ret; | |
68f95ba9 | 4564 | |
8187a2b7 ZN |
4565 | if (HAS_PIPE_CONTROL(dev)) { |
4566 | ret = i915_gem_init_pipe_control(dev); | |
4567 | if (ret) | |
4568 | return ret; | |
4569 | } | |
68f95ba9 | 4570 | |
5c1143bb | 4571 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4572 | if (ret) |
4573 | goto cleanup_pipe_control; | |
4574 | ||
4575 | if (HAS_BSD(dev)) { | |
5c1143bb | 4576 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4577 | if (ret) |
4578 | goto cleanup_render_ring; | |
d1b851fc | 4579 | } |
68f95ba9 | 4580 | |
6f392d54 CW |
4581 | dev_priv->next_seqno = 1; |
4582 | ||
68f95ba9 CW |
4583 | return 0; |
4584 | ||
4585 | cleanup_render_ring: | |
4586 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
4587 | cleanup_pipe_control: | |
4588 | if (HAS_PIPE_CONTROL(dev)) | |
4589 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4590 | return ret; |
4591 | } | |
4592 | ||
4593 | void | |
4594 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4595 | { | |
4596 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4597 | ||
4598 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4599 | if (HAS_BSD(dev)) |
4600 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
8187a2b7 ZN |
4601 | if (HAS_PIPE_CONTROL(dev)) |
4602 | i915_gem_cleanup_pipe_control(dev); | |
4603 | } | |
4604 | ||
673a394b EA |
4605 | int |
4606 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4607 | struct drm_file *file_priv) | |
4608 | { | |
4609 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4610 | int ret; | |
4611 | ||
79e53945 JB |
4612 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4613 | return 0; | |
4614 | ||
ba1234d1 | 4615 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4616 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4617 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4618 | } |
4619 | ||
673a394b | 4620 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4621 | dev_priv->mm.suspended = 0; |
4622 | ||
4623 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4624 | if (ret != 0) { |
4625 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4626 | return ret; |
d816f6ac | 4627 | } |
9bb2d6f9 | 4628 | |
852835f3 | 4629 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
d1b851fc | 4630 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
673a394b EA |
4631 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4632 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4633 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
d1b851fc | 4634 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
673a394b | 4635 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4636 | |
5f35308b CW |
4637 | ret = drm_irq_install(dev); |
4638 | if (ret) | |
4639 | goto cleanup_ringbuffer; | |
dbb19d30 | 4640 | |
673a394b | 4641 | return 0; |
5f35308b CW |
4642 | |
4643 | cleanup_ringbuffer: | |
4644 | mutex_lock(&dev->struct_mutex); | |
4645 | i915_gem_cleanup_ringbuffer(dev); | |
4646 | dev_priv->mm.suspended = 1; | |
4647 | mutex_unlock(&dev->struct_mutex); | |
4648 | ||
4649 | return ret; | |
673a394b EA |
4650 | } |
4651 | ||
4652 | int | |
4653 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4654 | struct drm_file *file_priv) | |
4655 | { | |
79e53945 JB |
4656 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4657 | return 0; | |
4658 | ||
dbb19d30 | 4659 | drm_irq_uninstall(dev); |
e6890f6f | 4660 | return i915_gem_idle(dev); |
673a394b EA |
4661 | } |
4662 | ||
4663 | void | |
4664 | i915_gem_lastclose(struct drm_device *dev) | |
4665 | { | |
4666 | int ret; | |
673a394b | 4667 | |
e806b495 EA |
4668 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4669 | return; | |
4670 | ||
6dbe2772 KP |
4671 | ret = i915_gem_idle(dev); |
4672 | if (ret) | |
4673 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4674 | } |
4675 | ||
4676 | void | |
4677 | i915_gem_load(struct drm_device *dev) | |
4678 | { | |
b5aa8a0f | 4679 | int i; |
673a394b EA |
4680 | drm_i915_private_t *dev_priv = dev->dev_private; |
4681 | ||
673a394b | 4682 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
99fcb766 | 4683 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
673a394b | 4684 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
f13d3f73 | 4685 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4686 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4687 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
852835f3 ZN |
4688 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
4689 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); | |
d1b851fc ZN |
4690 | if (HAS_BSD(dev)) { |
4691 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); | |
4692 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); | |
4693 | } | |
007cc8ac DV |
4694 | for (i = 0; i < 16; i++) |
4695 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4696 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4697 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4698 | init_completion(&dev_priv->error_completion); |
31169714 CW |
4699 | spin_lock(&shrink_list_lock); |
4700 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4701 | spin_unlock(&shrink_list_lock); | |
4702 | ||
94400120 DA |
4703 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4704 | if (IS_GEN3(dev)) { | |
4705 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4706 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4707 | /* arb state is a masked write, so set bit + bit in mask */ | |
4708 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4709 | I915_WRITE(MI_ARB_STATE, tmp); | |
4710 | } | |
4711 | } | |
4712 | ||
de151cf6 | 4713 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4714 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4715 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4716 | |
a6c45cf0 | 4717 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4718 | dev_priv->num_fence_regs = 16; |
4719 | else | |
4720 | dev_priv->num_fence_regs = 8; | |
4721 | ||
b5aa8a0f | 4722 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4723 | switch (INTEL_INFO(dev)->gen) { |
4724 | case 6: | |
4725 | for (i = 0; i < 16; i++) | |
4726 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4727 | break; | |
4728 | case 5: | |
4729 | case 4: | |
b5aa8a0f GH |
4730 | for (i = 0; i < 16; i++) |
4731 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4732 | break; |
4733 | case 3: | |
b5aa8a0f GH |
4734 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4735 | for (i = 0; i < 8; i++) | |
4736 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4737 | case 2: |
4738 | for (i = 0; i < 8; i++) | |
4739 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4740 | break; | |
b5aa8a0f | 4741 | } |
673a394b | 4742 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4743 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4744 | } |
71acb5eb DA |
4745 | |
4746 | /* | |
4747 | * Create a physically contiguous memory object for this object | |
4748 | * e.g. for cursor + overlay regs | |
4749 | */ | |
995b6762 CW |
4750 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4751 | int id, int size, int align) | |
71acb5eb DA |
4752 | { |
4753 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4754 | struct drm_i915_gem_phys_object *phys_obj; | |
4755 | int ret; | |
4756 | ||
4757 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4758 | return 0; | |
4759 | ||
9a298b2a | 4760 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4761 | if (!phys_obj) |
4762 | return -ENOMEM; | |
4763 | ||
4764 | phys_obj->id = id; | |
4765 | ||
6eeefaf3 | 4766 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4767 | if (!phys_obj->handle) { |
4768 | ret = -ENOMEM; | |
4769 | goto kfree_obj; | |
4770 | } | |
4771 | #ifdef CONFIG_X86 | |
4772 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4773 | #endif | |
4774 | ||
4775 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4776 | ||
4777 | return 0; | |
4778 | kfree_obj: | |
9a298b2a | 4779 | kfree(phys_obj); |
71acb5eb DA |
4780 | return ret; |
4781 | } | |
4782 | ||
995b6762 | 4783 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4784 | { |
4785 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4786 | struct drm_i915_gem_phys_object *phys_obj; | |
4787 | ||
4788 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4789 | return; | |
4790 | ||
4791 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4792 | if (phys_obj->cur_obj) { | |
4793 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4794 | } | |
4795 | ||
4796 | #ifdef CONFIG_X86 | |
4797 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4798 | #endif | |
4799 | drm_pci_free(dev, phys_obj->handle); | |
4800 | kfree(phys_obj); | |
4801 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4802 | } | |
4803 | ||
4804 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4805 | { | |
4806 | int i; | |
4807 | ||
260883c8 | 4808 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4809 | i915_gem_free_phys_object(dev, i); |
4810 | } | |
4811 | ||
4812 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4813 | struct drm_gem_object *obj) | |
4814 | { | |
4815 | struct drm_i915_gem_object *obj_priv; | |
4816 | int i; | |
4817 | int ret; | |
4818 | int page_count; | |
4819 | ||
23010e43 | 4820 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4821 | if (!obj_priv->phys_obj) |
4822 | return; | |
4823 | ||
4bdadb97 | 4824 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4825 | if (ret) |
4826 | goto out; | |
4827 | ||
4828 | page_count = obj->size / PAGE_SIZE; | |
4829 | ||
4830 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4831 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4832 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4833 | ||
4834 | memcpy(dst, src, PAGE_SIZE); | |
4835 | kunmap_atomic(dst, KM_USER0); | |
4836 | } | |
856fa198 | 4837 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4838 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4839 | |
4840 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4841 | out: |
4842 | obj_priv->phys_obj->cur_obj = NULL; | |
4843 | obj_priv->phys_obj = NULL; | |
4844 | } | |
4845 | ||
4846 | int | |
4847 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4848 | struct drm_gem_object *obj, |
4849 | int id, | |
4850 | int align) | |
71acb5eb DA |
4851 | { |
4852 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4853 | struct drm_i915_gem_object *obj_priv; | |
4854 | int ret = 0; | |
4855 | int page_count; | |
4856 | int i; | |
4857 | ||
4858 | if (id > I915_MAX_PHYS_OBJECT) | |
4859 | return -EINVAL; | |
4860 | ||
23010e43 | 4861 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4862 | |
4863 | if (obj_priv->phys_obj) { | |
4864 | if (obj_priv->phys_obj->id == id) | |
4865 | return 0; | |
4866 | i915_gem_detach_phys_object(dev, obj); | |
4867 | } | |
4868 | ||
71acb5eb DA |
4869 | /* create a new object */ |
4870 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4871 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4872 | obj->size, align); |
71acb5eb | 4873 | if (ret) { |
aeb565df | 4874 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4875 | goto out; |
4876 | } | |
4877 | } | |
4878 | ||
4879 | /* bind to the object */ | |
4880 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4881 | obj_priv->phys_obj->cur_obj = obj; | |
4882 | ||
4bdadb97 | 4883 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4884 | if (ret) { |
4885 | DRM_ERROR("failed to get page list\n"); | |
4886 | goto out; | |
4887 | } | |
4888 | ||
4889 | page_count = obj->size / PAGE_SIZE; | |
4890 | ||
4891 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4892 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4893 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4894 | ||
4895 | memcpy(dst, src, PAGE_SIZE); | |
4896 | kunmap_atomic(src, KM_USER0); | |
4897 | } | |
4898 | ||
d78b47b9 CW |
4899 | i915_gem_object_put_pages(obj); |
4900 | ||
71acb5eb DA |
4901 | return 0; |
4902 | out: | |
4903 | return ret; | |
4904 | } | |
4905 | ||
4906 | static int | |
4907 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4908 | struct drm_i915_gem_pwrite *args, | |
4909 | struct drm_file *file_priv) | |
4910 | { | |
23010e43 | 4911 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4912 | void *obj_addr; |
4913 | int ret; | |
4914 | char __user *user_data; | |
4915 | ||
4916 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4917 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4918 | ||
44d98a61 | 4919 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4920 | ret = copy_from_user(obj_addr, user_data, args->size); |
4921 | if (ret) | |
4922 | return -EFAULT; | |
4923 | ||
4924 | drm_agp_chipset_flush(dev); | |
4925 | return 0; | |
4926 | } | |
b962442e | 4927 | |
f787a5f5 | 4928 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4929 | { |
f787a5f5 | 4930 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4931 | |
4932 | /* Clean up our request list when the client is going away, so that | |
4933 | * later retire_requests won't dereference our soon-to-be-gone | |
4934 | * file_priv. | |
4935 | */ | |
1c25595f | 4936 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4937 | while (!list_empty(&file_priv->mm.request_list)) { |
4938 | struct drm_i915_gem_request *request; | |
4939 | ||
4940 | request = list_first_entry(&file_priv->mm.request_list, | |
4941 | struct drm_i915_gem_request, | |
4942 | client_list); | |
4943 | list_del(&request->client_list); | |
4944 | request->file_priv = NULL; | |
4945 | } | |
1c25595f | 4946 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4947 | } |
31169714 | 4948 | |
1637ef41 CW |
4949 | static int |
4950 | i915_gpu_is_active(struct drm_device *dev) | |
4951 | { | |
4952 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4953 | int lists_empty; | |
4954 | ||
1637ef41 | 4955 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
852835f3 | 4956 | list_empty(&dev_priv->render_ring.active_list); |
d1b851fc ZN |
4957 | if (HAS_BSD(dev)) |
4958 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); | |
1637ef41 CW |
4959 | |
4960 | return !lists_empty; | |
4961 | } | |
4962 | ||
31169714 | 4963 | static int |
7f8275d0 | 4964 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
4965 | { |
4966 | drm_i915_private_t *dev_priv, *next_dev; | |
4967 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4968 | int cnt = 0; | |
4969 | int would_deadlock = 1; | |
4970 | ||
4971 | /* "fast-path" to count number of available objects */ | |
4972 | if (nr_to_scan == 0) { | |
4973 | spin_lock(&shrink_list_lock); | |
4974 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4975 | struct drm_device *dev = dev_priv->dev; | |
4976 | ||
4977 | if (mutex_trylock(&dev->struct_mutex)) { | |
4978 | list_for_each_entry(obj_priv, | |
4979 | &dev_priv->mm.inactive_list, | |
4980 | list) | |
4981 | cnt++; | |
4982 | mutex_unlock(&dev->struct_mutex); | |
4983 | } | |
4984 | } | |
4985 | spin_unlock(&shrink_list_lock); | |
4986 | ||
4987 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4988 | } | |
4989 | ||
4990 | spin_lock(&shrink_list_lock); | |
4991 | ||
1637ef41 | 4992 | rescan: |
31169714 CW |
4993 | /* first scan for clean buffers */ |
4994 | list_for_each_entry_safe(dev_priv, next_dev, | |
4995 | &shrink_list, mm.shrink_list) { | |
4996 | struct drm_device *dev = dev_priv->dev; | |
4997 | ||
4998 | if (! mutex_trylock(&dev->struct_mutex)) | |
4999 | continue; | |
5000 | ||
5001 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 5002 | i915_gem_retire_requests(dev); |
31169714 CW |
5003 | |
5004 | list_for_each_entry_safe(obj_priv, next_obj, | |
5005 | &dev_priv->mm.inactive_list, | |
5006 | list) { | |
5007 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
a8089e84 | 5008 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5009 | if (--nr_to_scan <= 0) |
5010 | break; | |
5011 | } | |
5012 | } | |
5013 | ||
5014 | spin_lock(&shrink_list_lock); | |
5015 | mutex_unlock(&dev->struct_mutex); | |
5016 | ||
963b4836 CW |
5017 | would_deadlock = 0; |
5018 | ||
31169714 CW |
5019 | if (nr_to_scan <= 0) |
5020 | break; | |
5021 | } | |
5022 | ||
5023 | /* second pass, evict/count anything still on the inactive list */ | |
5024 | list_for_each_entry_safe(dev_priv, next_dev, | |
5025 | &shrink_list, mm.shrink_list) { | |
5026 | struct drm_device *dev = dev_priv->dev; | |
5027 | ||
5028 | if (! mutex_trylock(&dev->struct_mutex)) | |
5029 | continue; | |
5030 | ||
5031 | spin_unlock(&shrink_list_lock); | |
5032 | ||
5033 | list_for_each_entry_safe(obj_priv, next_obj, | |
5034 | &dev_priv->mm.inactive_list, | |
5035 | list) { | |
5036 | if (nr_to_scan > 0) { | |
a8089e84 | 5037 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5038 | nr_to_scan--; |
5039 | } else | |
5040 | cnt++; | |
5041 | } | |
5042 | ||
5043 | spin_lock(&shrink_list_lock); | |
5044 | mutex_unlock(&dev->struct_mutex); | |
5045 | ||
5046 | would_deadlock = 0; | |
5047 | } | |
5048 | ||
1637ef41 CW |
5049 | if (nr_to_scan) { |
5050 | int active = 0; | |
5051 | ||
5052 | /* | |
5053 | * We are desperate for pages, so as a last resort, wait | |
5054 | * for the GPU to finish and discard whatever we can. | |
5055 | * This has a dramatic impact to reduce the number of | |
5056 | * OOM-killer events whilst running the GPU aggressively. | |
5057 | */ | |
5058 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5059 | struct drm_device *dev = dev_priv->dev; | |
5060 | ||
5061 | if (!mutex_trylock(&dev->struct_mutex)) | |
5062 | continue; | |
5063 | ||
5064 | spin_unlock(&shrink_list_lock); | |
5065 | ||
5066 | if (i915_gpu_is_active(dev)) { | |
5067 | i915_gpu_idle(dev); | |
5068 | active++; | |
5069 | } | |
5070 | ||
5071 | spin_lock(&shrink_list_lock); | |
5072 | mutex_unlock(&dev->struct_mutex); | |
5073 | } | |
5074 | ||
5075 | if (active) | |
5076 | goto rescan; | |
5077 | } | |
5078 | ||
31169714 CW |
5079 | spin_unlock(&shrink_list_lock); |
5080 | ||
5081 | if (would_deadlock) | |
5082 | return -1; | |
5083 | else if (cnt > 0) | |
5084 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5085 | else | |
5086 | return 0; | |
5087 | } | |
5088 | ||
5089 | static struct shrinker shrinker = { | |
5090 | .shrink = i915_gem_shrink, | |
5091 | .seeks = DEFAULT_SEEKS, | |
5092 | }; | |
5093 | ||
5094 | __init void | |
5095 | i915_gem_shrinker_init(void) | |
5096 | { | |
5097 | register_shrinker(&shrinker); | |
5098 | } | |
5099 | ||
5100 | __exit void | |
5101 | i915_gem_shrinker_exit(void) | |
5102 | { | |
5103 | unregister_shrinker(&shrinker); | |
5104 | } |