Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
42 | bool force); | |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
46 | static __must_check int | |
07fe0b12 BW |
47 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
48 | struct i915_address_space *vm, | |
49 | unsigned alignment, | |
50 | bool map_and_fenceable, | |
51 | bool nonblocking); | |
05394f39 CW |
52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
53 | struct drm_i915_gem_object *obj, | |
71acb5eb | 54 | struct drm_i915_gem_pwrite *args, |
05394f39 | 55 | struct drm_file *file); |
673a394b | 56 | |
61050808 CW |
57 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
58 | struct drm_i915_gem_object *obj); | |
59 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
60 | struct drm_i915_fence_reg *fence, | |
61 | bool enable); | |
62 | ||
7dc19d5a DC |
63 | static unsigned long i915_gem_inactive_count(struct shrinker *shrinker, |
64 | struct shrink_control *sc); | |
65 | static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker, | |
66 | struct shrink_control *sc); | |
d9973b43 CW |
67 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
68 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 69 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 70 | |
c76ce038 CW |
71 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
72 | enum i915_cache_level level) | |
73 | { | |
74 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
75 | } | |
76 | ||
2c22569b CW |
77 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
78 | { | |
79 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
80 | return true; | |
81 | ||
82 | return obj->pin_display; | |
83 | } | |
84 | ||
61050808 CW |
85 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
86 | { | |
87 | if (obj->tiling_mode) | |
88 | i915_gem_release_mmap(obj); | |
89 | ||
90 | /* As we do not have an associated fence register, we will force | |
91 | * a tiling change if we ever need to acquire one. | |
92 | */ | |
5d82e3e6 | 93 | obj->fence_dirty = false; |
61050808 CW |
94 | obj->fence_reg = I915_FENCE_REG_NONE; |
95 | } | |
96 | ||
73aa808f CW |
97 | /* some bookkeeping */ |
98 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
99 | size_t size) | |
100 | { | |
c20e8355 | 101 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
102 | dev_priv->mm.object_count++; |
103 | dev_priv->mm.object_memory += size; | |
c20e8355 | 104 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | } |
106 | ||
107 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
108 | size_t size) | |
109 | { | |
c20e8355 | 110 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
111 | dev_priv->mm.object_count--; |
112 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 113 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
114 | } |
115 | ||
21dd3734 | 116 | static int |
33196ded | 117 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 118 | { |
30dbf0c0 CW |
119 | int ret; |
120 | ||
7abb690a DV |
121 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
122 | i915_terminally_wedged(error)) | |
1f83fee0 | 123 | if (EXIT_COND) |
30dbf0c0 CW |
124 | return 0; |
125 | ||
0a6759c6 DV |
126 | /* |
127 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
128 | * userspace. If it takes that long something really bad is going on and | |
129 | * we should simply try to bail out and fail as gracefully as possible. | |
130 | */ | |
1f83fee0 DV |
131 | ret = wait_event_interruptible_timeout(error->reset_queue, |
132 | EXIT_COND, | |
133 | 10*HZ); | |
0a6759c6 DV |
134 | if (ret == 0) { |
135 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
136 | return -EIO; | |
137 | } else if (ret < 0) { | |
30dbf0c0 | 138 | return ret; |
0a6759c6 | 139 | } |
1f83fee0 | 140 | #undef EXIT_COND |
30dbf0c0 | 141 | |
21dd3734 | 142 | return 0; |
30dbf0c0 CW |
143 | } |
144 | ||
54cf91dc | 145 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 146 | { |
33196ded | 147 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
148 | int ret; |
149 | ||
33196ded | 150 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
151 | if (ret) |
152 | return ret; | |
153 | ||
154 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
155 | if (ret) | |
156 | return ret; | |
157 | ||
23bc5982 | 158 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
159 | return 0; |
160 | } | |
30dbf0c0 | 161 | |
7d1c4804 | 162 | static inline bool |
05394f39 | 163 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 164 | { |
9843877d | 165 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
166 | } |
167 | ||
79e53945 JB |
168 | int |
169 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 170 | struct drm_file *file) |
79e53945 | 171 | { |
93d18799 | 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 173 | struct drm_i915_gem_init *args = data; |
2021746e | 174 | |
7bb6fb8d DV |
175 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
176 | return -ENODEV; | |
177 | ||
2021746e CW |
178 | if (args->gtt_start >= args->gtt_end || |
179 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
180 | return -EINVAL; | |
79e53945 | 181 | |
f534bc0b DV |
182 | /* GEM with user mode setting was never supported on ilk and later. */ |
183 | if (INTEL_INFO(dev)->gen >= 5) | |
184 | return -ENODEV; | |
185 | ||
79e53945 | 186 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
187 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
188 | args->gtt_end); | |
93d18799 | 189 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
190 | mutex_unlock(&dev->struct_mutex); |
191 | ||
2021746e | 192 | return 0; |
673a394b EA |
193 | } |
194 | ||
5a125c3c EA |
195 | int |
196 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 197 | struct drm_file *file) |
5a125c3c | 198 | { |
73aa808f | 199 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 200 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
201 | struct drm_i915_gem_object *obj; |
202 | size_t pinned; | |
5a125c3c | 203 | |
6299f992 | 204 | pinned = 0; |
73aa808f | 205 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 206 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
1b50247a | 207 | if (obj->pin_count) |
f343c5f6 | 208 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 209 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 210 | |
853ba5d2 | 211 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 212 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 213 | |
5a125c3c EA |
214 | return 0; |
215 | } | |
216 | ||
42dcedd4 CW |
217 | void *i915_gem_object_alloc(struct drm_device *dev) |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 220 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
221 | } |
222 | ||
223 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
224 | { | |
225 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
226 | kmem_cache_free(dev_priv->slab, obj); | |
227 | } | |
228 | ||
ff72145b DA |
229 | static int |
230 | i915_gem_create(struct drm_file *file, | |
231 | struct drm_device *dev, | |
232 | uint64_t size, | |
233 | uint32_t *handle_p) | |
673a394b | 234 | { |
05394f39 | 235 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
236 | int ret; |
237 | u32 handle; | |
673a394b | 238 | |
ff72145b | 239 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
240 | if (size == 0) |
241 | return -EINVAL; | |
673a394b EA |
242 | |
243 | /* Allocate the new object */ | |
ff72145b | 244 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
245 | if (obj == NULL) |
246 | return -ENOMEM; | |
247 | ||
05394f39 | 248 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 249 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
250 | drm_gem_object_unreference_unlocked(&obj->base); |
251 | if (ret) | |
252 | return ret; | |
202f2fef | 253 | |
ff72145b | 254 | *handle_p = handle; |
673a394b EA |
255 | return 0; |
256 | } | |
257 | ||
ff72145b DA |
258 | int |
259 | i915_gem_dumb_create(struct drm_file *file, | |
260 | struct drm_device *dev, | |
261 | struct drm_mode_create_dumb *args) | |
262 | { | |
263 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 264 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
265 | args->size = args->pitch * args->height; |
266 | return i915_gem_create(file, dev, | |
267 | args->size, &args->handle); | |
268 | } | |
269 | ||
ff72145b DA |
270 | /** |
271 | * Creates a new mm object and returns a handle to it. | |
272 | */ | |
273 | int | |
274 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
275 | struct drm_file *file) | |
276 | { | |
277 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 278 | |
ff72145b DA |
279 | return i915_gem_create(file, dev, |
280 | args->size, &args->handle); | |
281 | } | |
282 | ||
8461d226 DV |
283 | static inline int |
284 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
285 | const char *gpu_vaddr, int gpu_offset, | |
286 | int length) | |
287 | { | |
288 | int ret, cpu_offset = 0; | |
289 | ||
290 | while (length > 0) { | |
291 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
292 | int this_length = min(cacheline_end - gpu_offset, length); | |
293 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
294 | ||
295 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
296 | gpu_vaddr + swizzled_gpu_offset, | |
297 | this_length); | |
298 | if (ret) | |
299 | return ret + length; | |
300 | ||
301 | cpu_offset += this_length; | |
302 | gpu_offset += this_length; | |
303 | length -= this_length; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
8c59967c | 309 | static inline int |
4f0c7cfb BW |
310 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
311 | const char __user *cpu_vaddr, | |
8c59967c DV |
312 | int length) |
313 | { | |
314 | int ret, cpu_offset = 0; | |
315 | ||
316 | while (length > 0) { | |
317 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
318 | int this_length = min(cacheline_end - gpu_offset, length); | |
319 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
320 | ||
321 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
322 | cpu_vaddr + cpu_offset, | |
323 | this_length); | |
324 | if (ret) | |
325 | return ret + length; | |
326 | ||
327 | cpu_offset += this_length; | |
328 | gpu_offset += this_length; | |
329 | length -= this_length; | |
330 | } | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
d174bd64 DV |
335 | /* Per-page copy function for the shmem pread fastpath. |
336 | * Flushes invalid cachelines before reading the target if | |
337 | * needs_clflush is set. */ | |
eb01459f | 338 | static int |
d174bd64 DV |
339 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
340 | char __user *user_data, | |
341 | bool page_do_bit17_swizzling, bool needs_clflush) | |
342 | { | |
343 | char *vaddr; | |
344 | int ret; | |
345 | ||
e7e58eb5 | 346 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
347 | return -EINVAL; |
348 | ||
349 | vaddr = kmap_atomic(page); | |
350 | if (needs_clflush) | |
351 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
352 | page_length); | |
353 | ret = __copy_to_user_inatomic(user_data, | |
354 | vaddr + shmem_page_offset, | |
355 | page_length); | |
356 | kunmap_atomic(vaddr); | |
357 | ||
f60d7f0c | 358 | return ret ? -EFAULT : 0; |
d174bd64 DV |
359 | } |
360 | ||
23c18c71 DV |
361 | static void |
362 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
363 | bool swizzled) | |
364 | { | |
e7e58eb5 | 365 | if (unlikely(swizzled)) { |
23c18c71 DV |
366 | unsigned long start = (unsigned long) addr; |
367 | unsigned long end = (unsigned long) addr + length; | |
368 | ||
369 | /* For swizzling simply ensure that we always flush both | |
370 | * channels. Lame, but simple and it works. Swizzled | |
371 | * pwrite/pread is far from a hotpath - current userspace | |
372 | * doesn't use it at all. */ | |
373 | start = round_down(start, 128); | |
374 | end = round_up(end, 128); | |
375 | ||
376 | drm_clflush_virt_range((void *)start, end - start); | |
377 | } else { | |
378 | drm_clflush_virt_range(addr, length); | |
379 | } | |
380 | ||
381 | } | |
382 | ||
d174bd64 DV |
383 | /* Only difference to the fast-path function is that this can handle bit17 |
384 | * and uses non-atomic copy and kmap functions. */ | |
385 | static int | |
386 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
387 | char __user *user_data, | |
388 | bool page_do_bit17_swizzling, bool needs_clflush) | |
389 | { | |
390 | char *vaddr; | |
391 | int ret; | |
392 | ||
393 | vaddr = kmap(page); | |
394 | if (needs_clflush) | |
23c18c71 DV |
395 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
396 | page_length, | |
397 | page_do_bit17_swizzling); | |
d174bd64 DV |
398 | |
399 | if (page_do_bit17_swizzling) | |
400 | ret = __copy_to_user_swizzled(user_data, | |
401 | vaddr, shmem_page_offset, | |
402 | page_length); | |
403 | else | |
404 | ret = __copy_to_user(user_data, | |
405 | vaddr + shmem_page_offset, | |
406 | page_length); | |
407 | kunmap(page); | |
408 | ||
f60d7f0c | 409 | return ret ? - EFAULT : 0; |
d174bd64 DV |
410 | } |
411 | ||
eb01459f | 412 | static int |
dbf7bff0 DV |
413 | i915_gem_shmem_pread(struct drm_device *dev, |
414 | struct drm_i915_gem_object *obj, | |
415 | struct drm_i915_gem_pread *args, | |
416 | struct drm_file *file) | |
eb01459f | 417 | { |
8461d226 | 418 | char __user *user_data; |
eb01459f | 419 | ssize_t remain; |
8461d226 | 420 | loff_t offset; |
eb2c0c81 | 421 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 422 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 423 | int prefaulted = 0; |
8489731c | 424 | int needs_clflush = 0; |
67d5a50c | 425 | struct sg_page_iter sg_iter; |
eb01459f | 426 | |
2bb4629a | 427 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
428 | remain = args->size; |
429 | ||
8461d226 | 430 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 431 | |
8489731c DV |
432 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
433 | /* If we're not in the cpu read domain, set ourself into the gtt | |
434 | * read domain and manually flush cachelines (if required). This | |
435 | * optimizes for the case when the gpu will dirty the data | |
436 | * anyway again before the next pread happens. */ | |
c76ce038 | 437 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
23f54483 BW |
438 | ret = i915_gem_object_wait_rendering(obj, true); |
439 | if (ret) | |
440 | return ret; | |
8489731c | 441 | } |
eb01459f | 442 | |
f60d7f0c CW |
443 | ret = i915_gem_object_get_pages(obj); |
444 | if (ret) | |
445 | return ret; | |
446 | ||
447 | i915_gem_object_pin_pages(obj); | |
448 | ||
8461d226 | 449 | offset = args->offset; |
eb01459f | 450 | |
67d5a50c ID |
451 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
452 | offset >> PAGE_SHIFT) { | |
2db76d7c | 453 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
454 | |
455 | if (remain <= 0) | |
456 | break; | |
457 | ||
eb01459f EA |
458 | /* Operation in this page |
459 | * | |
eb01459f | 460 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
461 | * page_length = bytes to copy for this page |
462 | */ | |
c8cbbb8b | 463 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
464 | page_length = remain; |
465 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
466 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 467 | |
8461d226 DV |
468 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
469 | (page_to_phys(page) & (1 << 17)) != 0; | |
470 | ||
d174bd64 DV |
471 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
472 | user_data, page_do_bit17_swizzling, | |
473 | needs_clflush); | |
474 | if (ret == 0) | |
475 | goto next_page; | |
dbf7bff0 | 476 | |
dbf7bff0 DV |
477 | mutex_unlock(&dev->struct_mutex); |
478 | ||
0b74b508 | 479 | if (likely(!i915_prefault_disable) && !prefaulted) { |
f56f821f | 480 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
481 | /* Userspace is tricking us, but we've already clobbered |
482 | * its pages with the prefault and promised to write the | |
483 | * data up to the first fault. Hence ignore any errors | |
484 | * and just continue. */ | |
485 | (void)ret; | |
486 | prefaulted = 1; | |
487 | } | |
eb01459f | 488 | |
d174bd64 DV |
489 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
490 | user_data, page_do_bit17_swizzling, | |
491 | needs_clflush); | |
eb01459f | 492 | |
dbf7bff0 | 493 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 494 | |
dbf7bff0 | 495 | next_page: |
e5281ccd | 496 | mark_page_accessed(page); |
e5281ccd | 497 | |
f60d7f0c | 498 | if (ret) |
8461d226 | 499 | goto out; |
8461d226 | 500 | |
eb01459f | 501 | remain -= page_length; |
8461d226 | 502 | user_data += page_length; |
eb01459f EA |
503 | offset += page_length; |
504 | } | |
505 | ||
4f27b75d | 506 | out: |
f60d7f0c CW |
507 | i915_gem_object_unpin_pages(obj); |
508 | ||
eb01459f EA |
509 | return ret; |
510 | } | |
511 | ||
673a394b EA |
512 | /** |
513 | * Reads data from the object referenced by handle. | |
514 | * | |
515 | * On error, the contents of *data are undefined. | |
516 | */ | |
517 | int | |
518 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 519 | struct drm_file *file) |
673a394b EA |
520 | { |
521 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 522 | struct drm_i915_gem_object *obj; |
35b62a89 | 523 | int ret = 0; |
673a394b | 524 | |
51311d0a CW |
525 | if (args->size == 0) |
526 | return 0; | |
527 | ||
528 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 529 | to_user_ptr(args->data_ptr), |
51311d0a CW |
530 | args->size)) |
531 | return -EFAULT; | |
532 | ||
4f27b75d | 533 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 534 | if (ret) |
4f27b75d | 535 | return ret; |
673a394b | 536 | |
05394f39 | 537 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 538 | if (&obj->base == NULL) { |
1d7cfea1 CW |
539 | ret = -ENOENT; |
540 | goto unlock; | |
4f27b75d | 541 | } |
673a394b | 542 | |
7dcd2499 | 543 | /* Bounds check source. */ |
05394f39 CW |
544 | if (args->offset > obj->base.size || |
545 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 546 | ret = -EINVAL; |
35b62a89 | 547 | goto out; |
ce9d419d CW |
548 | } |
549 | ||
1286ff73 DV |
550 | /* prime objects have no backing filp to GEM pread/pwrite |
551 | * pages from. | |
552 | */ | |
553 | if (!obj->base.filp) { | |
554 | ret = -EINVAL; | |
555 | goto out; | |
556 | } | |
557 | ||
db53a302 CW |
558 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
559 | ||
dbf7bff0 | 560 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 561 | |
35b62a89 | 562 | out: |
05394f39 | 563 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 564 | unlock: |
4f27b75d | 565 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 566 | return ret; |
673a394b EA |
567 | } |
568 | ||
0839ccb8 KP |
569 | /* This is the fast write path which cannot handle |
570 | * page faults in the source data | |
9b7530cc | 571 | */ |
0839ccb8 KP |
572 | |
573 | static inline int | |
574 | fast_user_write(struct io_mapping *mapping, | |
575 | loff_t page_base, int page_offset, | |
576 | char __user *user_data, | |
577 | int length) | |
9b7530cc | 578 | { |
4f0c7cfb BW |
579 | void __iomem *vaddr_atomic; |
580 | void *vaddr; | |
0839ccb8 | 581 | unsigned long unwritten; |
9b7530cc | 582 | |
3e4d3af5 | 583 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
584 | /* We can use the cpu mem copy function because this is X86. */ |
585 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
586 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 587 | user_data, length); |
3e4d3af5 | 588 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 589 | return unwritten; |
0839ccb8 KP |
590 | } |
591 | ||
3de09aa3 EA |
592 | /** |
593 | * This is the fast pwrite path, where we copy the data directly from the | |
594 | * user into the GTT, uncached. | |
595 | */ | |
673a394b | 596 | static int |
05394f39 CW |
597 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
598 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 599 | struct drm_i915_gem_pwrite *args, |
05394f39 | 600 | struct drm_file *file) |
673a394b | 601 | { |
0839ccb8 | 602 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 603 | ssize_t remain; |
0839ccb8 | 604 | loff_t offset, page_base; |
673a394b | 605 | char __user *user_data; |
935aaa69 DV |
606 | int page_offset, page_length, ret; |
607 | ||
c37e2204 | 608 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
935aaa69 DV |
609 | if (ret) |
610 | goto out; | |
611 | ||
612 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
613 | if (ret) | |
614 | goto out_unpin; | |
615 | ||
616 | ret = i915_gem_object_put_fence(obj); | |
617 | if (ret) | |
618 | goto out_unpin; | |
673a394b | 619 | |
2bb4629a | 620 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 621 | remain = args->size; |
673a394b | 622 | |
f343c5f6 | 623 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
624 | |
625 | while (remain > 0) { | |
626 | /* Operation in this page | |
627 | * | |
0839ccb8 KP |
628 | * page_base = page offset within aperture |
629 | * page_offset = offset within page | |
630 | * page_length = bytes to copy for this page | |
673a394b | 631 | */ |
c8cbbb8b CW |
632 | page_base = offset & PAGE_MASK; |
633 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
634 | page_length = remain; |
635 | if ((page_offset + remain) > PAGE_SIZE) | |
636 | page_length = PAGE_SIZE - page_offset; | |
637 | ||
0839ccb8 | 638 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
639 | * source page isn't available. Return the error and we'll |
640 | * retry in the slow path. | |
0839ccb8 | 641 | */ |
5d4545ae | 642 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
643 | page_offset, user_data, page_length)) { |
644 | ret = -EFAULT; | |
645 | goto out_unpin; | |
646 | } | |
673a394b | 647 | |
0839ccb8 KP |
648 | remain -= page_length; |
649 | user_data += page_length; | |
650 | offset += page_length; | |
673a394b | 651 | } |
673a394b | 652 | |
935aaa69 DV |
653 | out_unpin: |
654 | i915_gem_object_unpin(obj); | |
655 | out: | |
3de09aa3 | 656 | return ret; |
673a394b EA |
657 | } |
658 | ||
d174bd64 DV |
659 | /* Per-page copy function for the shmem pwrite fastpath. |
660 | * Flushes invalid cachelines before writing to the target if | |
661 | * needs_clflush_before is set and flushes out any written cachelines after | |
662 | * writing if needs_clflush is set. */ | |
3043c60c | 663 | static int |
d174bd64 DV |
664 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
665 | char __user *user_data, | |
666 | bool page_do_bit17_swizzling, | |
667 | bool needs_clflush_before, | |
668 | bool needs_clflush_after) | |
673a394b | 669 | { |
d174bd64 | 670 | char *vaddr; |
673a394b | 671 | int ret; |
3de09aa3 | 672 | |
e7e58eb5 | 673 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 674 | return -EINVAL; |
3de09aa3 | 675 | |
d174bd64 DV |
676 | vaddr = kmap_atomic(page); |
677 | if (needs_clflush_before) | |
678 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
679 | page_length); | |
680 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
681 | user_data, | |
682 | page_length); | |
683 | if (needs_clflush_after) | |
684 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
685 | page_length); | |
686 | kunmap_atomic(vaddr); | |
3de09aa3 | 687 | |
755d2218 | 688 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
689 | } |
690 | ||
d174bd64 DV |
691 | /* Only difference to the fast-path function is that this can handle bit17 |
692 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 693 | static int |
d174bd64 DV |
694 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
695 | char __user *user_data, | |
696 | bool page_do_bit17_swizzling, | |
697 | bool needs_clflush_before, | |
698 | bool needs_clflush_after) | |
673a394b | 699 | { |
d174bd64 DV |
700 | char *vaddr; |
701 | int ret; | |
e5281ccd | 702 | |
d174bd64 | 703 | vaddr = kmap(page); |
e7e58eb5 | 704 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
705 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
706 | page_length, | |
707 | page_do_bit17_swizzling); | |
d174bd64 DV |
708 | if (page_do_bit17_swizzling) |
709 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
710 | user_data, |
711 | page_length); | |
d174bd64 DV |
712 | else |
713 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
714 | user_data, | |
715 | page_length); | |
716 | if (needs_clflush_after) | |
23c18c71 DV |
717 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
718 | page_length, | |
719 | page_do_bit17_swizzling); | |
d174bd64 | 720 | kunmap(page); |
40123c1f | 721 | |
755d2218 | 722 | return ret ? -EFAULT : 0; |
40123c1f EA |
723 | } |
724 | ||
40123c1f | 725 | static int |
e244a443 DV |
726 | i915_gem_shmem_pwrite(struct drm_device *dev, |
727 | struct drm_i915_gem_object *obj, | |
728 | struct drm_i915_gem_pwrite *args, | |
729 | struct drm_file *file) | |
40123c1f | 730 | { |
40123c1f | 731 | ssize_t remain; |
8c59967c DV |
732 | loff_t offset; |
733 | char __user *user_data; | |
eb2c0c81 | 734 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 735 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 736 | int hit_slowpath = 0; |
58642885 DV |
737 | int needs_clflush_after = 0; |
738 | int needs_clflush_before = 0; | |
67d5a50c | 739 | struct sg_page_iter sg_iter; |
40123c1f | 740 | |
2bb4629a | 741 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
742 | remain = args->size; |
743 | ||
8c59967c | 744 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 745 | |
58642885 DV |
746 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
747 | /* If we're not in the cpu write domain, set ourself into the gtt | |
748 | * write domain and manually flush cachelines (if required). This | |
749 | * optimizes for the case when the gpu will use the data | |
750 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 751 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
752 | ret = i915_gem_object_wait_rendering(obj, false); |
753 | if (ret) | |
754 | return ret; | |
58642885 | 755 | } |
c76ce038 CW |
756 | /* Same trick applies to invalidate partially written cachelines read |
757 | * before writing. */ | |
758 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
759 | needs_clflush_before = | |
760 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 761 | |
755d2218 CW |
762 | ret = i915_gem_object_get_pages(obj); |
763 | if (ret) | |
764 | return ret; | |
765 | ||
766 | i915_gem_object_pin_pages(obj); | |
767 | ||
673a394b | 768 | offset = args->offset; |
05394f39 | 769 | obj->dirty = 1; |
673a394b | 770 | |
67d5a50c ID |
771 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
772 | offset >> PAGE_SHIFT) { | |
2db76d7c | 773 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 774 | int partial_cacheline_write; |
e5281ccd | 775 | |
9da3da66 CW |
776 | if (remain <= 0) |
777 | break; | |
778 | ||
40123c1f EA |
779 | /* Operation in this page |
780 | * | |
40123c1f | 781 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
782 | * page_length = bytes to copy for this page |
783 | */ | |
c8cbbb8b | 784 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
785 | |
786 | page_length = remain; | |
787 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
788 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 789 | |
58642885 DV |
790 | /* If we don't overwrite a cacheline completely we need to be |
791 | * careful to have up-to-date data by first clflushing. Don't | |
792 | * overcomplicate things and flush the entire patch. */ | |
793 | partial_cacheline_write = needs_clflush_before && | |
794 | ((shmem_page_offset | page_length) | |
795 | & (boot_cpu_data.x86_clflush_size - 1)); | |
796 | ||
8c59967c DV |
797 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
798 | (page_to_phys(page) & (1 << 17)) != 0; | |
799 | ||
d174bd64 DV |
800 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
801 | user_data, page_do_bit17_swizzling, | |
802 | partial_cacheline_write, | |
803 | needs_clflush_after); | |
804 | if (ret == 0) | |
805 | goto next_page; | |
e244a443 DV |
806 | |
807 | hit_slowpath = 1; | |
e244a443 | 808 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
809 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
810 | user_data, page_do_bit17_swizzling, | |
811 | partial_cacheline_write, | |
812 | needs_clflush_after); | |
40123c1f | 813 | |
e244a443 | 814 | mutex_lock(&dev->struct_mutex); |
755d2218 | 815 | |
e244a443 | 816 | next_page: |
e5281ccd CW |
817 | set_page_dirty(page); |
818 | mark_page_accessed(page); | |
e5281ccd | 819 | |
755d2218 | 820 | if (ret) |
8c59967c | 821 | goto out; |
8c59967c | 822 | |
40123c1f | 823 | remain -= page_length; |
8c59967c | 824 | user_data += page_length; |
40123c1f | 825 | offset += page_length; |
673a394b EA |
826 | } |
827 | ||
fbd5a26d | 828 | out: |
755d2218 CW |
829 | i915_gem_object_unpin_pages(obj); |
830 | ||
e244a443 | 831 | if (hit_slowpath) { |
8dcf015e DV |
832 | /* |
833 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
834 | * cachelines in-line while writing and the object moved | |
835 | * out of the cpu write domain while we've dropped the lock. | |
836 | */ | |
837 | if (!needs_clflush_after && | |
838 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
839 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
840 | i915_gem_chipset_flush(dev); | |
e244a443 | 841 | } |
8c59967c | 842 | } |
673a394b | 843 | |
58642885 | 844 | if (needs_clflush_after) |
e76e9aeb | 845 | i915_gem_chipset_flush(dev); |
58642885 | 846 | |
40123c1f | 847 | return ret; |
673a394b EA |
848 | } |
849 | ||
850 | /** | |
851 | * Writes data to the object referenced by handle. | |
852 | * | |
853 | * On error, the contents of the buffer that were to be modified are undefined. | |
854 | */ | |
855 | int | |
856 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 857 | struct drm_file *file) |
673a394b EA |
858 | { |
859 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 860 | struct drm_i915_gem_object *obj; |
51311d0a CW |
861 | int ret; |
862 | ||
863 | if (args->size == 0) | |
864 | return 0; | |
865 | ||
866 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 867 | to_user_ptr(args->data_ptr), |
51311d0a CW |
868 | args->size)) |
869 | return -EFAULT; | |
870 | ||
0b74b508 XZ |
871 | if (likely(!i915_prefault_disable)) { |
872 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), | |
873 | args->size); | |
874 | if (ret) | |
875 | return -EFAULT; | |
876 | } | |
673a394b | 877 | |
fbd5a26d | 878 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 879 | if (ret) |
fbd5a26d | 880 | return ret; |
1d7cfea1 | 881 | |
05394f39 | 882 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 883 | if (&obj->base == NULL) { |
1d7cfea1 CW |
884 | ret = -ENOENT; |
885 | goto unlock; | |
fbd5a26d | 886 | } |
673a394b | 887 | |
7dcd2499 | 888 | /* Bounds check destination. */ |
05394f39 CW |
889 | if (args->offset > obj->base.size || |
890 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 891 | ret = -EINVAL; |
35b62a89 | 892 | goto out; |
ce9d419d CW |
893 | } |
894 | ||
1286ff73 DV |
895 | /* prime objects have no backing filp to GEM pread/pwrite |
896 | * pages from. | |
897 | */ | |
898 | if (!obj->base.filp) { | |
899 | ret = -EINVAL; | |
900 | goto out; | |
901 | } | |
902 | ||
db53a302 CW |
903 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
904 | ||
935aaa69 | 905 | ret = -EFAULT; |
673a394b EA |
906 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
907 | * it would end up going through the fenced access, and we'll get | |
908 | * different detiling behavior between reading and writing. | |
909 | * pread/pwrite currently are reading and writing from the CPU | |
910 | * perspective, requiring manual detiling by the client. | |
911 | */ | |
5c0480f2 | 912 | if (obj->phys_obj) { |
fbd5a26d | 913 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
914 | goto out; |
915 | } | |
916 | ||
2c22569b CW |
917 | if (obj->tiling_mode == I915_TILING_NONE && |
918 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
919 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 920 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
921 | /* Note that the gtt paths might fail with non-page-backed user |
922 | * pointers (e.g. gtt mappings when moving data between | |
923 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 924 | } |
673a394b | 925 | |
86a1ee26 | 926 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 927 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 928 | |
35b62a89 | 929 | out: |
05394f39 | 930 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 931 | unlock: |
fbd5a26d | 932 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
933 | return ret; |
934 | } | |
935 | ||
b361237b | 936 | int |
33196ded | 937 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
938 | bool interruptible) |
939 | { | |
1f83fee0 | 940 | if (i915_reset_in_progress(error)) { |
b361237b CW |
941 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
942 | * -EIO unconditionally for these. */ | |
943 | if (!interruptible) | |
944 | return -EIO; | |
945 | ||
1f83fee0 DV |
946 | /* Recovery complete, but the reset failed ... */ |
947 | if (i915_terminally_wedged(error)) | |
b361237b CW |
948 | return -EIO; |
949 | ||
950 | return -EAGAIN; | |
951 | } | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
956 | /* | |
957 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
958 | * equal. | |
959 | */ | |
960 | static int | |
961 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
962 | { | |
963 | int ret; | |
964 | ||
965 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
966 | ||
967 | ret = 0; | |
1823521d | 968 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 969 | ret = i915_add_request(ring, NULL); |
b361237b CW |
970 | |
971 | return ret; | |
972 | } | |
973 | ||
094f9a54 CW |
974 | static void fake_irq(unsigned long data) |
975 | { | |
976 | wake_up_process((struct task_struct *)data); | |
977 | } | |
978 | ||
979 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
980 | struct intel_ring_buffer *ring) | |
981 | { | |
982 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
983 | } | |
984 | ||
b29c19b6 CW |
985 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
986 | { | |
987 | if (file_priv == NULL) | |
988 | return true; | |
989 | ||
990 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
991 | } | |
992 | ||
b361237b CW |
993 | /** |
994 | * __wait_seqno - wait until execution of seqno has finished | |
995 | * @ring: the ring expected to report seqno | |
996 | * @seqno: duh! | |
f69061be | 997 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
998 | * @interruptible: do an interruptible wait (normally yes) |
999 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1000 | * | |
f69061be DV |
1001 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1002 | * values have been read by the caller in an smp safe manner. Where read-side | |
1003 | * locks are involved, it is sufficient to read the reset_counter before | |
1004 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1005 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1006 | * inserted. | |
1007 | * | |
b361237b CW |
1008 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1009 | * errno with remaining time filled in timeout argument. | |
1010 | */ | |
1011 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 1012 | unsigned reset_counter, |
b29c19b6 CW |
1013 | bool interruptible, |
1014 | struct timespec *timeout, | |
1015 | struct drm_i915_file_private *file_priv) | |
b361237b CW |
1016 | { |
1017 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
168c3f21 MK |
1018 | const bool irq_test_in_progress = |
1019 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 CW |
1020 | struct timespec before, now; |
1021 | DEFINE_WAIT(wait); | |
47e9766d | 1022 | unsigned long timeout_expire; |
b361237b CW |
1023 | int ret; |
1024 | ||
c67a470b PZ |
1025 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
1026 | ||
b361237b CW |
1027 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1028 | return 0; | |
1029 | ||
47e9766d | 1030 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
b361237b | 1031 | |
b29c19b6 CW |
1032 | if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) { |
1033 | gen6_rps_boost(dev_priv); | |
1034 | if (file_priv) | |
1035 | mod_delayed_work(dev_priv->wq, | |
1036 | &file_priv->mm.idle_work, | |
1037 | msecs_to_jiffies(100)); | |
1038 | } | |
1039 | ||
168c3f21 | 1040 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1041 | return -ENODEV; |
1042 | ||
094f9a54 CW |
1043 | /* Record current time in case interrupted by signal, or wedged */ |
1044 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1045 | getrawmonotonic(&before); |
094f9a54 CW |
1046 | for (;;) { |
1047 | struct timer_list timer; | |
b361237b | 1048 | |
094f9a54 CW |
1049 | prepare_to_wait(&ring->irq_queue, &wait, |
1050 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1051 | |
f69061be DV |
1052 | /* We need to check whether any gpu reset happened in between |
1053 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1054 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1055 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1056 | * is truely gone. */ | |
1057 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1058 | if (ret == 0) | |
1059 | ret = -EAGAIN; | |
1060 | break; | |
1061 | } | |
f69061be | 1062 | |
094f9a54 CW |
1063 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1064 | ret = 0; | |
1065 | break; | |
1066 | } | |
b361237b | 1067 | |
094f9a54 CW |
1068 | if (interruptible && signal_pending(current)) { |
1069 | ret = -ERESTARTSYS; | |
1070 | break; | |
1071 | } | |
1072 | ||
47e9766d | 1073 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1074 | ret = -ETIME; |
1075 | break; | |
1076 | } | |
1077 | ||
1078 | timer.function = NULL; | |
1079 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1080 | unsigned long expire; |
1081 | ||
094f9a54 | 1082 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1083 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1084 | mod_timer(&timer, expire); |
1085 | } | |
1086 | ||
5035c275 | 1087 | io_schedule(); |
094f9a54 | 1088 | |
094f9a54 CW |
1089 | if (timer.function) { |
1090 | del_singleshot_timer_sync(&timer); | |
1091 | destroy_timer_on_stack(&timer); | |
1092 | } | |
1093 | } | |
b361237b | 1094 | getrawmonotonic(&now); |
094f9a54 | 1095 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1096 | |
168c3f21 MK |
1097 | if (!irq_test_in_progress) |
1098 | ring->irq_put(ring); | |
094f9a54 CW |
1099 | |
1100 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1101 | |
1102 | if (timeout) { | |
1103 | struct timespec sleep_time = timespec_sub(now, before); | |
1104 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1105 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1106 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1107 | } |
1108 | ||
094f9a54 | 1109 | return ret; |
b361237b CW |
1110 | } |
1111 | ||
1112 | /** | |
1113 | * Waits for a sequence number to be signaled, and cleans up the | |
1114 | * request and object lists appropriately for that event. | |
1115 | */ | |
1116 | int | |
1117 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1118 | { | |
1119 | struct drm_device *dev = ring->dev; | |
1120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1121 | bool interruptible = dev_priv->mm.interruptible; | |
1122 | int ret; | |
1123 | ||
1124 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1125 | BUG_ON(seqno == 0); | |
1126 | ||
33196ded | 1127 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1128 | if (ret) |
1129 | return ret; | |
1130 | ||
1131 | ret = i915_gem_check_olr(ring, seqno); | |
1132 | if (ret) | |
1133 | return ret; | |
1134 | ||
f69061be DV |
1135 | return __wait_seqno(ring, seqno, |
1136 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1137 | interruptible, NULL, NULL); |
b361237b CW |
1138 | } |
1139 | ||
d26e3af8 CW |
1140 | static int |
1141 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1142 | struct intel_ring_buffer *ring) | |
1143 | { | |
1144 | i915_gem_retire_requests_ring(ring); | |
1145 | ||
1146 | /* Manually manage the write flush as we may have not yet | |
1147 | * retired the buffer. | |
1148 | * | |
1149 | * Note that the last_write_seqno is always the earlier of | |
1150 | * the two (read/write) seqno, so if we haved successfully waited, | |
1151 | * we know we have passed the last write. | |
1152 | */ | |
1153 | obj->last_write_seqno = 0; | |
1154 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
b361237b CW |
1159 | /** |
1160 | * Ensures that all rendering to the object has completed and the object is | |
1161 | * safe to unbind from the GTT or access from the CPU. | |
1162 | */ | |
1163 | static __must_check int | |
1164 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1165 | bool readonly) | |
1166 | { | |
1167 | struct intel_ring_buffer *ring = obj->ring; | |
1168 | u32 seqno; | |
1169 | int ret; | |
1170 | ||
1171 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1172 | if (seqno == 0) | |
1173 | return 0; | |
1174 | ||
1175 | ret = i915_wait_seqno(ring, seqno); | |
1176 | if (ret) | |
1177 | return ret; | |
1178 | ||
d26e3af8 | 1179 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1180 | } |
1181 | ||
3236f57a CW |
1182 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1183 | * as the object state may change during this call. | |
1184 | */ | |
1185 | static __must_check int | |
1186 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
b29c19b6 | 1187 | struct drm_file *file, |
3236f57a CW |
1188 | bool readonly) |
1189 | { | |
1190 | struct drm_device *dev = obj->base.dev; | |
1191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1192 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1193 | unsigned reset_counter; |
3236f57a CW |
1194 | u32 seqno; |
1195 | int ret; | |
1196 | ||
1197 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1198 | BUG_ON(!dev_priv->mm.interruptible); | |
1199 | ||
1200 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1201 | if (seqno == 0) | |
1202 | return 0; | |
1203 | ||
33196ded | 1204 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1205 | if (ret) |
1206 | return ret; | |
1207 | ||
1208 | ret = i915_gem_check_olr(ring, seqno); | |
1209 | if (ret) | |
1210 | return ret; | |
1211 | ||
f69061be | 1212 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1213 | mutex_unlock(&dev->struct_mutex); |
b29c19b6 | 1214 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file->driver_priv); |
3236f57a | 1215 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1216 | if (ret) |
1217 | return ret; | |
3236f57a | 1218 | |
d26e3af8 | 1219 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1220 | } |
1221 | ||
673a394b | 1222 | /** |
2ef7eeaa EA |
1223 | * Called when user space prepares to use an object with the CPU, either |
1224 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1225 | */ |
1226 | int | |
1227 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1228 | struct drm_file *file) |
673a394b EA |
1229 | { |
1230 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1231 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1232 | uint32_t read_domains = args->read_domains; |
1233 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1234 | int ret; |
1235 | ||
2ef7eeaa | 1236 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1237 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1238 | return -EINVAL; |
1239 | ||
21d509e3 | 1240 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1241 | return -EINVAL; |
1242 | ||
1243 | /* Having something in the write domain implies it's in the read | |
1244 | * domain, and only that read domain. Enforce that in the request. | |
1245 | */ | |
1246 | if (write_domain != 0 && read_domains != write_domain) | |
1247 | return -EINVAL; | |
1248 | ||
76c1dec1 | 1249 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1250 | if (ret) |
76c1dec1 | 1251 | return ret; |
1d7cfea1 | 1252 | |
05394f39 | 1253 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1254 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1255 | ret = -ENOENT; |
1256 | goto unlock; | |
76c1dec1 | 1257 | } |
673a394b | 1258 | |
3236f57a CW |
1259 | /* Try to flush the object off the GPU without holding the lock. |
1260 | * We will repeat the flush holding the lock in the normal manner | |
1261 | * to catch cases where we are gazumped. | |
1262 | */ | |
b29c19b6 | 1263 | ret = i915_gem_object_wait_rendering__nonblocking(obj, file, !write_domain); |
3236f57a CW |
1264 | if (ret) |
1265 | goto unref; | |
1266 | ||
2ef7eeaa EA |
1267 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1268 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1269 | |
1270 | /* Silently promote "you're not bound, there was nothing to do" | |
1271 | * to success, since the client was just asking us to | |
1272 | * make sure everything was done. | |
1273 | */ | |
1274 | if (ret == -EINVAL) | |
1275 | ret = 0; | |
2ef7eeaa | 1276 | } else { |
e47c68e9 | 1277 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1278 | } |
1279 | ||
3236f57a | 1280 | unref: |
05394f39 | 1281 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1282 | unlock: |
673a394b EA |
1283 | mutex_unlock(&dev->struct_mutex); |
1284 | return ret; | |
1285 | } | |
1286 | ||
1287 | /** | |
1288 | * Called when user space has done writes to this buffer | |
1289 | */ | |
1290 | int | |
1291 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1292 | struct drm_file *file) |
673a394b EA |
1293 | { |
1294 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1295 | struct drm_i915_gem_object *obj; |
673a394b EA |
1296 | int ret = 0; |
1297 | ||
76c1dec1 | 1298 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1299 | if (ret) |
76c1dec1 | 1300 | return ret; |
1d7cfea1 | 1301 | |
05394f39 | 1302 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1303 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1304 | ret = -ENOENT; |
1305 | goto unlock; | |
673a394b EA |
1306 | } |
1307 | ||
673a394b | 1308 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1309 | if (obj->pin_display) |
1310 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1311 | |
05394f39 | 1312 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1313 | unlock: |
673a394b EA |
1314 | mutex_unlock(&dev->struct_mutex); |
1315 | return ret; | |
1316 | } | |
1317 | ||
1318 | /** | |
1319 | * Maps the contents of an object, returning the address it is mapped | |
1320 | * into. | |
1321 | * | |
1322 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1323 | * imply a ref on the object itself. | |
1324 | */ | |
1325 | int | |
1326 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1327 | struct drm_file *file) |
673a394b EA |
1328 | { |
1329 | struct drm_i915_gem_mmap *args = data; | |
1330 | struct drm_gem_object *obj; | |
673a394b EA |
1331 | unsigned long addr; |
1332 | ||
05394f39 | 1333 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1334 | if (obj == NULL) |
bf79cb91 | 1335 | return -ENOENT; |
673a394b | 1336 | |
1286ff73 DV |
1337 | /* prime objects have no backing filp to GEM mmap |
1338 | * pages from. | |
1339 | */ | |
1340 | if (!obj->filp) { | |
1341 | drm_gem_object_unreference_unlocked(obj); | |
1342 | return -EINVAL; | |
1343 | } | |
1344 | ||
6be5ceb0 | 1345 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1346 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1347 | args->offset); | |
bc9025bd | 1348 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1349 | if (IS_ERR((void *)addr)) |
1350 | return addr; | |
1351 | ||
1352 | args->addr_ptr = (uint64_t) addr; | |
1353 | ||
1354 | return 0; | |
1355 | } | |
1356 | ||
de151cf6 JB |
1357 | /** |
1358 | * i915_gem_fault - fault a page into the GTT | |
1359 | * vma: VMA in question | |
1360 | * vmf: fault info | |
1361 | * | |
1362 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1363 | * from userspace. The fault handler takes care of binding the object to | |
1364 | * the GTT (if needed), allocating and programming a fence register (again, | |
1365 | * only if needed based on whether the old reg is still valid or the object | |
1366 | * is tiled) and inserting a new PTE into the faulting process. | |
1367 | * | |
1368 | * Note that the faulting process may involve evicting existing objects | |
1369 | * from the GTT and/or fence registers to make room. So performance may | |
1370 | * suffer if the GTT working set is large or there are few fence registers | |
1371 | * left. | |
1372 | */ | |
1373 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1374 | { | |
05394f39 CW |
1375 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1376 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1377 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1378 | pgoff_t page_offset; |
1379 | unsigned long pfn; | |
1380 | int ret = 0; | |
0f973f27 | 1381 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1382 | |
f65c9168 PZ |
1383 | intel_runtime_pm_get(dev_priv); |
1384 | ||
de151cf6 JB |
1385 | /* We don't use vmf->pgoff since that has the fake offset */ |
1386 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1387 | PAGE_SHIFT; | |
1388 | ||
d9bc7e9f CW |
1389 | ret = i915_mutex_lock_interruptible(dev); |
1390 | if (ret) | |
1391 | goto out; | |
a00b10c3 | 1392 | |
db53a302 CW |
1393 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1394 | ||
eb119bd6 CW |
1395 | /* Access to snoopable pages through the GTT is incoherent. */ |
1396 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1397 | ret = -EINVAL; | |
1398 | goto unlock; | |
1399 | } | |
1400 | ||
d9bc7e9f | 1401 | /* Now bind it into the GTT if needed */ |
c37e2204 | 1402 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
c9839303 CW |
1403 | if (ret) |
1404 | goto unlock; | |
4a684a41 | 1405 | |
c9839303 CW |
1406 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1407 | if (ret) | |
1408 | goto unpin; | |
74898d7e | 1409 | |
06d98131 | 1410 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1411 | if (ret) |
c9839303 | 1412 | goto unpin; |
7d1c4804 | 1413 | |
6299f992 CW |
1414 | obj->fault_mappable = true; |
1415 | ||
f343c5f6 BW |
1416 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1417 | pfn >>= PAGE_SHIFT; | |
1418 | pfn += page_offset; | |
de151cf6 JB |
1419 | |
1420 | /* Finally, remap it using the new GTT offset */ | |
1421 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1422 | unpin: |
1423 | i915_gem_object_unpin(obj); | |
c715089f | 1424 | unlock: |
de151cf6 | 1425 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1426 | out: |
de151cf6 | 1427 | switch (ret) { |
d9bc7e9f | 1428 | case -EIO: |
a9340cca DV |
1429 | /* If this -EIO is due to a gpu hang, give the reset code a |
1430 | * chance to clean up the mess. Otherwise return the proper | |
1431 | * SIGBUS. */ | |
f65c9168 PZ |
1432 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
1433 | ret = VM_FAULT_SIGBUS; | |
1434 | break; | |
1435 | } | |
045e769a | 1436 | case -EAGAIN: |
571c608d DV |
1437 | /* |
1438 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1439 | * handler to reset everything when re-faulting in | |
1440 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1441 | */ |
c715089f CW |
1442 | case 0: |
1443 | case -ERESTARTSYS: | |
bed636ab | 1444 | case -EINTR: |
e79e0fe3 DR |
1445 | case -EBUSY: |
1446 | /* | |
1447 | * EBUSY is ok: this just means that another thread | |
1448 | * already did the job. | |
1449 | */ | |
f65c9168 PZ |
1450 | ret = VM_FAULT_NOPAGE; |
1451 | break; | |
de151cf6 | 1452 | case -ENOMEM: |
f65c9168 PZ |
1453 | ret = VM_FAULT_OOM; |
1454 | break; | |
a7c2e1aa | 1455 | case -ENOSPC: |
f65c9168 PZ |
1456 | ret = VM_FAULT_SIGBUS; |
1457 | break; | |
de151cf6 | 1458 | default: |
a7c2e1aa | 1459 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1460 | ret = VM_FAULT_SIGBUS; |
1461 | break; | |
de151cf6 | 1462 | } |
f65c9168 PZ |
1463 | |
1464 | intel_runtime_pm_put(dev_priv); | |
1465 | return ret; | |
de151cf6 JB |
1466 | } |
1467 | ||
48018a57 PZ |
1468 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
1469 | { | |
1470 | struct i915_vma *vma; | |
1471 | ||
1472 | /* | |
1473 | * Only the global gtt is relevant for gtt memory mappings, so restrict | |
1474 | * list traversal to objects bound into the global address space. Note | |
1475 | * that the active list should be empty, but better safe than sorry. | |
1476 | */ | |
1477 | WARN_ON(!list_empty(&dev_priv->gtt.base.active_list)); | |
1478 | list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list) | |
1479 | i915_gem_release_mmap(vma->obj); | |
1480 | list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list) | |
1481 | i915_gem_release_mmap(vma->obj); | |
1482 | } | |
1483 | ||
901782b2 CW |
1484 | /** |
1485 | * i915_gem_release_mmap - remove physical page mappings | |
1486 | * @obj: obj in question | |
1487 | * | |
af901ca1 | 1488 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1489 | * relinquish ownership of the pages back to the system. |
1490 | * | |
1491 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1492 | * object through the GTT and then lose the fence register due to | |
1493 | * resource pressure. Similarly if the object has been moved out of the | |
1494 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1495 | * mapping will then trigger a page fault on the next user access, allowing | |
1496 | * fixup by i915_gem_fault(). | |
1497 | */ | |
d05ca301 | 1498 | void |
05394f39 | 1499 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1500 | { |
6299f992 CW |
1501 | if (!obj->fault_mappable) |
1502 | return; | |
901782b2 | 1503 | |
51335df9 | 1504 | drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
6299f992 | 1505 | obj->fault_mappable = false; |
901782b2 CW |
1506 | } |
1507 | ||
0fa87796 | 1508 | uint32_t |
e28f8711 | 1509 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1510 | { |
e28f8711 | 1511 | uint32_t gtt_size; |
92b88aeb CW |
1512 | |
1513 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1514 | tiling_mode == I915_TILING_NONE) |
1515 | return size; | |
92b88aeb CW |
1516 | |
1517 | /* Previous chips need a power-of-two fence region when tiling */ | |
1518 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1519 | gtt_size = 1024*1024; |
92b88aeb | 1520 | else |
e28f8711 | 1521 | gtt_size = 512*1024; |
92b88aeb | 1522 | |
e28f8711 CW |
1523 | while (gtt_size < size) |
1524 | gtt_size <<= 1; | |
92b88aeb | 1525 | |
e28f8711 | 1526 | return gtt_size; |
92b88aeb CW |
1527 | } |
1528 | ||
de151cf6 JB |
1529 | /** |
1530 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1531 | * @obj: object to check | |
1532 | * | |
1533 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1534 | * potential fence register mapping. |
de151cf6 | 1535 | */ |
d865110c ID |
1536 | uint32_t |
1537 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1538 | int tiling_mode, bool fenced) | |
de151cf6 | 1539 | { |
de151cf6 JB |
1540 | /* |
1541 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1542 | * if a fence register is needed for the object. | |
1543 | */ | |
d865110c | 1544 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1545 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1546 | return 4096; |
1547 | ||
a00b10c3 CW |
1548 | /* |
1549 | * Previous chips need to be aligned to the size of the smallest | |
1550 | * fence register that can contain the object. | |
1551 | */ | |
e28f8711 | 1552 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1553 | } |
1554 | ||
d8cb5086 CW |
1555 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1556 | { | |
1557 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1558 | int ret; | |
1559 | ||
0de23977 | 1560 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1561 | return 0; |
1562 | ||
da494d7c DV |
1563 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1564 | ||
d8cb5086 CW |
1565 | ret = drm_gem_create_mmap_offset(&obj->base); |
1566 | if (ret != -ENOSPC) | |
da494d7c | 1567 | goto out; |
d8cb5086 CW |
1568 | |
1569 | /* Badly fragmented mmap space? The only way we can recover | |
1570 | * space is by destroying unwanted objects. We can't randomly release | |
1571 | * mmap_offsets as userspace expects them to be persistent for the | |
1572 | * lifetime of the objects. The closest we can is to release the | |
1573 | * offsets on purgeable objects by truncating it and marking it purged, | |
1574 | * which prevents userspace from ever using that object again. | |
1575 | */ | |
1576 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1577 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1578 | if (ret != -ENOSPC) | |
da494d7c | 1579 | goto out; |
d8cb5086 CW |
1580 | |
1581 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1582 | ret = drm_gem_create_mmap_offset(&obj->base); |
1583 | out: | |
1584 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1585 | ||
1586 | return ret; | |
d8cb5086 CW |
1587 | } |
1588 | ||
1589 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1590 | { | |
d8cb5086 CW |
1591 | drm_gem_free_mmap_offset(&obj->base); |
1592 | } | |
1593 | ||
de151cf6 | 1594 | int |
ff72145b DA |
1595 | i915_gem_mmap_gtt(struct drm_file *file, |
1596 | struct drm_device *dev, | |
1597 | uint32_t handle, | |
1598 | uint64_t *offset) | |
de151cf6 | 1599 | { |
da761a6e | 1600 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1601 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1602 | int ret; |
1603 | ||
76c1dec1 | 1604 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1605 | if (ret) |
76c1dec1 | 1606 | return ret; |
de151cf6 | 1607 | |
ff72145b | 1608 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1609 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1610 | ret = -ENOENT; |
1611 | goto unlock; | |
1612 | } | |
de151cf6 | 1613 | |
5d4545ae | 1614 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1615 | ret = -E2BIG; |
ff56b0bc | 1616 | goto out; |
da761a6e CW |
1617 | } |
1618 | ||
05394f39 | 1619 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1620 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1621 | ret = -EINVAL; |
1622 | goto out; | |
ab18282d CW |
1623 | } |
1624 | ||
d8cb5086 CW |
1625 | ret = i915_gem_object_create_mmap_offset(obj); |
1626 | if (ret) | |
1627 | goto out; | |
de151cf6 | 1628 | |
0de23977 | 1629 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1630 | |
1d7cfea1 | 1631 | out: |
05394f39 | 1632 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1633 | unlock: |
de151cf6 | 1634 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1635 | return ret; |
de151cf6 JB |
1636 | } |
1637 | ||
ff72145b DA |
1638 | /** |
1639 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1640 | * @dev: DRM device | |
1641 | * @data: GTT mapping ioctl data | |
1642 | * @file: GEM object info | |
1643 | * | |
1644 | * Simply returns the fake offset to userspace so it can mmap it. | |
1645 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1646 | * up so we can get faults in the handler above. | |
1647 | * | |
1648 | * The fault handler will take care of binding the object into the GTT | |
1649 | * (since it may have been evicted to make room for something), allocating | |
1650 | * a fence register, and mapping the appropriate aperture address into | |
1651 | * userspace. | |
1652 | */ | |
1653 | int | |
1654 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1655 | struct drm_file *file) | |
1656 | { | |
1657 | struct drm_i915_gem_mmap_gtt *args = data; | |
1658 | ||
ff72145b DA |
1659 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1660 | } | |
1661 | ||
225067ee DV |
1662 | /* Immediately discard the backing storage */ |
1663 | static void | |
1664 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1665 | { |
e5281ccd | 1666 | struct inode *inode; |
e5281ccd | 1667 | |
4d6294bf | 1668 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1669 | |
4d6294bf CW |
1670 | if (obj->base.filp == NULL) |
1671 | return; | |
e5281ccd | 1672 | |
225067ee DV |
1673 | /* Our goal here is to return as much of the memory as |
1674 | * is possible back to the system as we are called from OOM. | |
1675 | * To do this we must instruct the shmfs to drop all of its | |
1676 | * backing pages, *now*. | |
1677 | */ | |
496ad9aa | 1678 | inode = file_inode(obj->base.filp); |
225067ee | 1679 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1680 | |
225067ee DV |
1681 | obj->madv = __I915_MADV_PURGED; |
1682 | } | |
e5281ccd | 1683 | |
225067ee DV |
1684 | static inline int |
1685 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1686 | { | |
1687 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1688 | } |
1689 | ||
5cdf5881 | 1690 | static void |
05394f39 | 1691 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1692 | { |
90797e6d ID |
1693 | struct sg_page_iter sg_iter; |
1694 | int ret; | |
1286ff73 | 1695 | |
05394f39 | 1696 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1697 | |
6c085a72 CW |
1698 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1699 | if (ret) { | |
1700 | /* In the event of a disaster, abandon all caches and | |
1701 | * hope for the best. | |
1702 | */ | |
1703 | WARN_ON(ret != -EIO); | |
2c22569b | 1704 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1705 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1706 | } | |
1707 | ||
6dacfd2f | 1708 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1709 | i915_gem_object_save_bit_17_swizzle(obj); |
1710 | ||
05394f39 CW |
1711 | if (obj->madv == I915_MADV_DONTNEED) |
1712 | obj->dirty = 0; | |
3ef94daa | 1713 | |
90797e6d | 1714 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1715 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1716 | |
05394f39 | 1717 | if (obj->dirty) |
9da3da66 | 1718 | set_page_dirty(page); |
3ef94daa | 1719 | |
05394f39 | 1720 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1721 | mark_page_accessed(page); |
3ef94daa | 1722 | |
9da3da66 | 1723 | page_cache_release(page); |
3ef94daa | 1724 | } |
05394f39 | 1725 | obj->dirty = 0; |
673a394b | 1726 | |
9da3da66 CW |
1727 | sg_free_table(obj->pages); |
1728 | kfree(obj->pages); | |
37e680a1 | 1729 | } |
6c085a72 | 1730 | |
dd624afd | 1731 | int |
37e680a1 CW |
1732 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1733 | { | |
1734 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1735 | ||
2f745ad3 | 1736 | if (obj->pages == NULL) |
37e680a1 CW |
1737 | return 0; |
1738 | ||
a5570178 CW |
1739 | if (obj->pages_pin_count) |
1740 | return -EBUSY; | |
1741 | ||
9843877d | 1742 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1743 | |
a2165e31 CW |
1744 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1745 | * array, hence protect them from being reaped by removing them from gtt | |
1746 | * lists early. */ | |
35c20a60 | 1747 | list_del(&obj->global_list); |
a2165e31 | 1748 | |
37e680a1 | 1749 | ops->put_pages(obj); |
05394f39 | 1750 | obj->pages = NULL; |
37e680a1 | 1751 | |
6c085a72 CW |
1752 | if (i915_gem_object_is_purgeable(obj)) |
1753 | i915_gem_object_truncate(obj); | |
1754 | ||
1755 | return 0; | |
1756 | } | |
1757 | ||
d9973b43 | 1758 | static unsigned long |
93927ca5 DV |
1759 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1760 | bool purgeable_only) | |
6c085a72 | 1761 | { |
57094f82 | 1762 | struct list_head still_bound_list; |
6c085a72 | 1763 | struct drm_i915_gem_object *obj, *next; |
d9973b43 | 1764 | unsigned long count = 0; |
6c085a72 CW |
1765 | |
1766 | list_for_each_entry_safe(obj, next, | |
1767 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1768 | global_list) { |
93927ca5 | 1769 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1770 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1771 | count += obj->base.size >> PAGE_SHIFT; |
1772 | if (count >= target) | |
1773 | return count; | |
1774 | } | |
1775 | } | |
1776 | ||
57094f82 CW |
1777 | /* |
1778 | * As we may completely rewrite the bound list whilst unbinding | |
1779 | * (due to retiring requests) we have to strictly process only | |
1780 | * one element of the list at the time, and recheck the list | |
1781 | * on every iteration. | |
1782 | */ | |
1783 | INIT_LIST_HEAD(&still_bound_list); | |
1784 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { | |
07fe0b12 | 1785 | struct i915_vma *vma, *v; |
80dcfdbd | 1786 | |
57094f82 CW |
1787 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1788 | typeof(*obj), global_list); | |
1789 | list_move_tail(&obj->global_list, &still_bound_list); | |
1790 | ||
80dcfdbd BW |
1791 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1792 | continue; | |
1793 | ||
57094f82 CW |
1794 | /* |
1795 | * Hold a reference whilst we unbind this object, as we may | |
1796 | * end up waiting for and retiring requests. This might | |
1797 | * release the final reference (held by the active list) | |
1798 | * and result in the object being freed from under us. | |
1799 | * in this object being freed. | |
1800 | * | |
1801 | * Note 1: Shrinking the bound list is special since only active | |
1802 | * (and hence bound objects) can contain such limbo objects, so | |
1803 | * we don't need special tricks for shrinking the unbound list. | |
1804 | * The only other place where we have to be careful with active | |
1805 | * objects suddenly disappearing due to retiring requests is the | |
1806 | * eviction code. | |
1807 | * | |
1808 | * Note 2: Even though the bound list doesn't hold a reference | |
1809 | * to the object we can safely grab one here: The final object | |
1810 | * unreferencing and the bound_list are both protected by the | |
1811 | * dev->struct_mutex and so we won't ever be able to observe an | |
1812 | * object on the bound_list with a reference count equals 0. | |
1813 | */ | |
1814 | drm_gem_object_reference(&obj->base); | |
1815 | ||
07fe0b12 BW |
1816 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1817 | if (i915_vma_unbind(vma)) | |
1818 | break; | |
80dcfdbd | 1819 | |
57094f82 | 1820 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1821 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1822 | |
1823 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1824 | } |
57094f82 | 1825 | list_splice(&still_bound_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1826 | |
1827 | return count; | |
1828 | } | |
1829 | ||
d9973b43 | 1830 | static unsigned long |
93927ca5 DV |
1831 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
1832 | { | |
1833 | return __i915_gem_shrink(dev_priv, target, true); | |
1834 | } | |
1835 | ||
d9973b43 | 1836 | static unsigned long |
6c085a72 CW |
1837 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
1838 | { | |
1839 | struct drm_i915_gem_object *obj, *next; | |
7dc19d5a | 1840 | long freed = 0; |
6c085a72 CW |
1841 | |
1842 | i915_gem_evict_everything(dev_priv->dev); | |
1843 | ||
35c20a60 | 1844 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
7dc19d5a | 1845 | global_list) { |
d9973b43 | 1846 | if (i915_gem_object_put_pages(obj) == 0) |
7dc19d5a | 1847 | freed += obj->base.size >> PAGE_SHIFT; |
7dc19d5a DC |
1848 | } |
1849 | return freed; | |
225067ee DV |
1850 | } |
1851 | ||
37e680a1 | 1852 | static int |
6c085a72 | 1853 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1854 | { |
6c085a72 | 1855 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1856 | int page_count, i; |
1857 | struct address_space *mapping; | |
9da3da66 CW |
1858 | struct sg_table *st; |
1859 | struct scatterlist *sg; | |
90797e6d | 1860 | struct sg_page_iter sg_iter; |
e5281ccd | 1861 | struct page *page; |
90797e6d | 1862 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1863 | gfp_t gfp; |
e5281ccd | 1864 | |
6c085a72 CW |
1865 | /* Assert that the object is not currently in any GPU domain. As it |
1866 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1867 | * a GPU cache | |
1868 | */ | |
1869 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1870 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1871 | ||
9da3da66 CW |
1872 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1873 | if (st == NULL) | |
1874 | return -ENOMEM; | |
1875 | ||
05394f39 | 1876 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1877 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 1878 | kfree(st); |
e5281ccd | 1879 | return -ENOMEM; |
9da3da66 | 1880 | } |
e5281ccd | 1881 | |
9da3da66 CW |
1882 | /* Get the list of pages out of our struct file. They'll be pinned |
1883 | * at this point until we release them. | |
1884 | * | |
1885 | * Fail silently without starting the shrinker | |
1886 | */ | |
496ad9aa | 1887 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1888 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1889 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1890 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1891 | sg = st->sgl; |
1892 | st->nents = 0; | |
1893 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1894 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1895 | if (IS_ERR(page)) { | |
1896 | i915_gem_purge(dev_priv, page_count); | |
1897 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1898 | } | |
1899 | if (IS_ERR(page)) { | |
1900 | /* We've tried hard to allocate the memory by reaping | |
1901 | * our own buffer, now let the real VM do its job and | |
1902 | * go down in flames if truly OOM. | |
1903 | */ | |
caf49191 | 1904 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1905 | gfp |= __GFP_IO | __GFP_WAIT; |
1906 | ||
1907 | i915_gem_shrink_all(dev_priv); | |
1908 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1909 | if (IS_ERR(page)) | |
1910 | goto err_pages; | |
1911 | ||
caf49191 | 1912 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1913 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1914 | } | |
426729dc KRW |
1915 | #ifdef CONFIG_SWIOTLB |
1916 | if (swiotlb_nr_tbl()) { | |
1917 | st->nents++; | |
1918 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1919 | sg = sg_next(sg); | |
1920 | continue; | |
1921 | } | |
1922 | #endif | |
90797e6d ID |
1923 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1924 | if (i) | |
1925 | sg = sg_next(sg); | |
1926 | st->nents++; | |
1927 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1928 | } else { | |
1929 | sg->length += PAGE_SIZE; | |
1930 | } | |
1931 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
1932 | |
1933 | /* Check that the i965g/gm workaround works. */ | |
1934 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 1935 | } |
426729dc KRW |
1936 | #ifdef CONFIG_SWIOTLB |
1937 | if (!swiotlb_nr_tbl()) | |
1938 | #endif | |
1939 | sg_mark_end(sg); | |
74ce6b6c CW |
1940 | obj->pages = st; |
1941 | ||
6dacfd2f | 1942 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1943 | i915_gem_object_do_bit_17_swizzle(obj); |
1944 | ||
1945 | return 0; | |
1946 | ||
1947 | err_pages: | |
90797e6d ID |
1948 | sg_mark_end(sg); |
1949 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1950 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1951 | sg_free_table(st); |
1952 | kfree(st); | |
e5281ccd | 1953 | return PTR_ERR(page); |
673a394b EA |
1954 | } |
1955 | ||
37e680a1 CW |
1956 | /* Ensure that the associated pages are gathered from the backing storage |
1957 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1958 | * multiple times before they are released by a single call to | |
1959 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1960 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1961 | * or as the object is itself released. | |
1962 | */ | |
1963 | int | |
1964 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1965 | { | |
1966 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1967 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1968 | int ret; | |
1969 | ||
2f745ad3 | 1970 | if (obj->pages) |
37e680a1 CW |
1971 | return 0; |
1972 | ||
43e28f09 CW |
1973 | if (obj->madv != I915_MADV_WILLNEED) { |
1974 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1975 | return -EINVAL; | |
1976 | } | |
1977 | ||
a5570178 CW |
1978 | BUG_ON(obj->pages_pin_count); |
1979 | ||
37e680a1 CW |
1980 | ret = ops->get_pages(obj); |
1981 | if (ret) | |
1982 | return ret; | |
1983 | ||
35c20a60 | 1984 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 1985 | return 0; |
673a394b EA |
1986 | } |
1987 | ||
e2d05a8b | 1988 | static void |
05394f39 | 1989 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1990 | struct intel_ring_buffer *ring) |
673a394b | 1991 | { |
05394f39 | 1992 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1993 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1994 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1995 | |
852835f3 | 1996 | BUG_ON(ring == NULL); |
02978ff5 CW |
1997 | if (obj->ring != ring && obj->last_write_seqno) { |
1998 | /* Keep the seqno relative to the current ring */ | |
1999 | obj->last_write_seqno = seqno; | |
2000 | } | |
05394f39 | 2001 | obj->ring = ring; |
673a394b EA |
2002 | |
2003 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2004 | if (!obj->active) { |
2005 | drm_gem_object_reference(&obj->base); | |
2006 | obj->active = 1; | |
673a394b | 2007 | } |
e35a41de | 2008 | |
05394f39 | 2009 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2010 | |
0201f1ec | 2011 | obj->last_read_seqno = seqno; |
caea7476 | 2012 | |
7dd49065 | 2013 | if (obj->fenced_gpu_access) { |
caea7476 | 2014 | obj->last_fenced_seqno = seqno; |
caea7476 | 2015 | |
7dd49065 CW |
2016 | /* Bump MRU to take account of the delayed flush */ |
2017 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2018 | struct drm_i915_fence_reg *reg; | |
2019 | ||
2020 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
2021 | list_move_tail(®->lru_list, | |
2022 | &dev_priv->mm.fence_list); | |
2023 | } | |
caea7476 CW |
2024 | } |
2025 | } | |
2026 | ||
e2d05a8b BW |
2027 | void i915_vma_move_to_active(struct i915_vma *vma, |
2028 | struct intel_ring_buffer *ring) | |
2029 | { | |
2030 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2031 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2032 | } | |
2033 | ||
caea7476 | 2034 | static void |
caea7476 | 2035 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2036 | { |
ca191b13 BW |
2037 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2038 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
2039 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); | |
ce44b0ea | 2040 | |
65ce3027 | 2041 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2042 | BUG_ON(!obj->active); |
caea7476 | 2043 | |
ca191b13 | 2044 | list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list); |
caea7476 | 2045 | |
65ce3027 | 2046 | list_del_init(&obj->ring_list); |
caea7476 CW |
2047 | obj->ring = NULL; |
2048 | ||
65ce3027 CW |
2049 | obj->last_read_seqno = 0; |
2050 | obj->last_write_seqno = 0; | |
2051 | obj->base.write_domain = 0; | |
2052 | ||
2053 | obj->last_fenced_seqno = 0; | |
caea7476 | 2054 | obj->fenced_gpu_access = false; |
caea7476 CW |
2055 | |
2056 | obj->active = 0; | |
2057 | drm_gem_object_unreference(&obj->base); | |
2058 | ||
2059 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2060 | } |
673a394b | 2061 | |
9d773091 | 2062 | static int |
fca26bb4 | 2063 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2064 | { |
9d773091 CW |
2065 | struct drm_i915_private *dev_priv = dev->dev_private; |
2066 | struct intel_ring_buffer *ring; | |
2067 | int ret, i, j; | |
53d227f2 | 2068 | |
107f27a5 | 2069 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2070 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2071 | ret = intel_ring_idle(ring); |
2072 | if (ret) | |
2073 | return ret; | |
9d773091 | 2074 | } |
9d773091 | 2075 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2076 | |
2077 | /* Finally reset hw state */ | |
9d773091 | 2078 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2079 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2080 | |
9d773091 CW |
2081 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
2082 | ring->sync_seqno[j] = 0; | |
2083 | } | |
53d227f2 | 2084 | |
9d773091 | 2085 | return 0; |
53d227f2 DV |
2086 | } |
2087 | ||
fca26bb4 MK |
2088 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2089 | { | |
2090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2091 | int ret; | |
2092 | ||
2093 | if (seqno == 0) | |
2094 | return -EINVAL; | |
2095 | ||
2096 | /* HWS page needs to be set less than what we | |
2097 | * will inject to ring | |
2098 | */ | |
2099 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2100 | if (ret) | |
2101 | return ret; | |
2102 | ||
2103 | /* Carefully set the last_seqno value so that wrap | |
2104 | * detection still works | |
2105 | */ | |
2106 | dev_priv->next_seqno = seqno; | |
2107 | dev_priv->last_seqno = seqno - 1; | |
2108 | if (dev_priv->last_seqno == 0) | |
2109 | dev_priv->last_seqno--; | |
2110 | ||
2111 | return 0; | |
2112 | } | |
2113 | ||
9d773091 CW |
2114 | int |
2115 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2116 | { |
9d773091 CW |
2117 | struct drm_i915_private *dev_priv = dev->dev_private; |
2118 | ||
2119 | /* reserve 0 for non-seqno */ | |
2120 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2121 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2122 | if (ret) |
2123 | return ret; | |
53d227f2 | 2124 | |
9d773091 CW |
2125 | dev_priv->next_seqno = 1; |
2126 | } | |
53d227f2 | 2127 | |
f72b3435 | 2128 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2129 | return 0; |
53d227f2 DV |
2130 | } |
2131 | ||
0025c077 MK |
2132 | int __i915_add_request(struct intel_ring_buffer *ring, |
2133 | struct drm_file *file, | |
7d736f4f | 2134 | struct drm_i915_gem_object *obj, |
0025c077 | 2135 | u32 *out_seqno) |
673a394b | 2136 | { |
db53a302 | 2137 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2138 | struct drm_i915_gem_request *request; |
7d736f4f | 2139 | u32 request_ring_position, request_start; |
673a394b | 2140 | int was_empty; |
3cce469c CW |
2141 | int ret; |
2142 | ||
7d736f4f | 2143 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2144 | /* |
2145 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2146 | * after having emitted the batchbuffer command. Hence we need to fix | |
2147 | * things up similar to emitting the lazy request. The difference here | |
2148 | * is that the flush _must_ happen before the next request, no matter | |
2149 | * what. | |
2150 | */ | |
a7b9761d CW |
2151 | ret = intel_ring_flush_all_caches(ring); |
2152 | if (ret) | |
2153 | return ret; | |
cc889e0f | 2154 | |
3c0e234c CW |
2155 | request = ring->preallocated_lazy_request; |
2156 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2157 | return -ENOMEM; |
cc889e0f | 2158 | |
a71d8d94 CW |
2159 | /* Record the position of the start of the request so that |
2160 | * should we detect the updated seqno part-way through the | |
2161 | * GPU processing the request, we never over-estimate the | |
2162 | * position of the head. | |
2163 | */ | |
2164 | request_ring_position = intel_ring_get_tail(ring); | |
2165 | ||
9d773091 | 2166 | ret = ring->add_request(ring); |
3c0e234c | 2167 | if (ret) |
3bb73aba | 2168 | return ret; |
673a394b | 2169 | |
9d773091 | 2170 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2171 | request->ring = ring; |
7d736f4f | 2172 | request->head = request_start; |
a71d8d94 | 2173 | request->tail = request_ring_position; |
7d736f4f MK |
2174 | |
2175 | /* Whilst this request exists, batch_obj will be on the | |
2176 | * active_list, and so will hold the active reference. Only when this | |
2177 | * request is retired will the the batch_obj be moved onto the | |
2178 | * inactive_list and lose its active reference. Hence we do not need | |
2179 | * to explicitly hold another reference here. | |
2180 | */ | |
9a7e0c2a | 2181 | request->batch_obj = obj; |
0e50e96b | 2182 | |
9a7e0c2a CW |
2183 | /* Hold a reference to the current context so that we can inspect |
2184 | * it later in case a hangcheck error event fires. | |
2185 | */ | |
2186 | request->ctx = ring->last_context; | |
0e50e96b MK |
2187 | if (request->ctx) |
2188 | i915_gem_context_reference(request->ctx); | |
2189 | ||
673a394b | 2190 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2191 | was_empty = list_empty(&ring->request_list); |
2192 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2193 | request->file_priv = NULL; |
852835f3 | 2194 | |
db53a302 CW |
2195 | if (file) { |
2196 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2197 | ||
1c25595f | 2198 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2199 | request->file_priv = file_priv; |
b962442e | 2200 | list_add_tail(&request->client_list, |
f787a5f5 | 2201 | &file_priv->mm.request_list); |
1c25595f | 2202 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2203 | } |
673a394b | 2204 | |
9d773091 | 2205 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2206 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2207 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2208 | |
db1b76ca | 2209 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2210 | i915_queue_hangcheck(ring->dev); |
2211 | ||
f047e395 | 2212 | if (was_empty) { |
b29c19b6 | 2213 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
b3b079db | 2214 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2215 | &dev_priv->mm.retire_work, |
2216 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2217 | intel_mark_busy(dev_priv->dev); |
2218 | } | |
f65d9421 | 2219 | } |
cc889e0f | 2220 | |
acb868d3 | 2221 | if (out_seqno) |
9d773091 | 2222 | *out_seqno = request->seqno; |
3cce469c | 2223 | return 0; |
673a394b EA |
2224 | } |
2225 | ||
f787a5f5 CW |
2226 | static inline void |
2227 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2228 | { |
1c25595f | 2229 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2230 | |
1c25595f CW |
2231 | if (!file_priv) |
2232 | return; | |
1c5d22f7 | 2233 | |
1c25595f | 2234 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2235 | list_del(&request->client_list); |
2236 | request->file_priv = NULL; | |
1c25595f | 2237 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2238 | } |
673a394b | 2239 | |
d1ccbb5d BW |
2240 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj, |
2241 | struct i915_address_space *vm) | |
aa60c664 | 2242 | { |
d1ccbb5d BW |
2243 | if (acthd >= i915_gem_obj_offset(obj, vm) && |
2244 | acthd < i915_gem_obj_offset(obj, vm) + obj->base.size) | |
aa60c664 MK |
2245 | return true; |
2246 | ||
2247 | return false; | |
2248 | } | |
2249 | ||
2250 | static bool i915_head_inside_request(const u32 acthd_unmasked, | |
2251 | const u32 request_start, | |
2252 | const u32 request_end) | |
2253 | { | |
2254 | const u32 acthd = acthd_unmasked & HEAD_ADDR; | |
2255 | ||
2256 | if (request_start < request_end) { | |
2257 | if (acthd >= request_start && acthd < request_end) | |
2258 | return true; | |
2259 | } else if (request_start > request_end) { | |
2260 | if (acthd >= request_start || acthd < request_end) | |
2261 | return true; | |
2262 | } | |
2263 | ||
2264 | return false; | |
2265 | } | |
2266 | ||
d1ccbb5d BW |
2267 | static struct i915_address_space * |
2268 | request_to_vm(struct drm_i915_gem_request *request) | |
2269 | { | |
2270 | struct drm_i915_private *dev_priv = request->ring->dev->dev_private; | |
2271 | struct i915_address_space *vm; | |
2272 | ||
2273 | vm = &dev_priv->gtt.base; | |
2274 | ||
2275 | return vm; | |
2276 | } | |
2277 | ||
aa60c664 MK |
2278 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
2279 | const u32 acthd, bool *inside) | |
2280 | { | |
2281 | /* There is a possibility that unmasked head address | |
2282 | * pointing inside the ring, matches the batch_obj address range. | |
2283 | * However this is extremely unlikely. | |
2284 | */ | |
aa60c664 | 2285 | if (request->batch_obj) { |
d1ccbb5d BW |
2286 | if (i915_head_inside_object(acthd, request->batch_obj, |
2287 | request_to_vm(request))) { | |
aa60c664 MK |
2288 | *inside = true; |
2289 | return true; | |
2290 | } | |
2291 | } | |
2292 | ||
2293 | if (i915_head_inside_request(acthd, request->head, request->tail)) { | |
2294 | *inside = false; | |
2295 | return true; | |
2296 | } | |
2297 | ||
2298 | return false; | |
2299 | } | |
2300 | ||
be62acb4 MK |
2301 | static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs) |
2302 | { | |
2303 | const unsigned long elapsed = get_seconds() - hs->guilty_ts; | |
2304 | ||
2305 | if (hs->banned) | |
2306 | return true; | |
2307 | ||
2308 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
2309 | DRM_ERROR("context hanging too fast, declaring banned!\n"); | |
2310 | return true; | |
2311 | } | |
2312 | ||
2313 | return false; | |
2314 | } | |
2315 | ||
aa60c664 MK |
2316 | static void i915_set_reset_status(struct intel_ring_buffer *ring, |
2317 | struct drm_i915_gem_request *request, | |
2318 | u32 acthd) | |
2319 | { | |
2320 | struct i915_ctx_hang_stats *hs = NULL; | |
2321 | bool inside, guilty; | |
d1ccbb5d | 2322 | unsigned long offset = 0; |
aa60c664 MK |
2323 | |
2324 | /* Innocent until proven guilty */ | |
2325 | guilty = false; | |
2326 | ||
d1ccbb5d BW |
2327 | if (request->batch_obj) |
2328 | offset = i915_gem_obj_offset(request->batch_obj, | |
2329 | request_to_vm(request)); | |
2330 | ||
f2f4d82f | 2331 | if (ring->hangcheck.action != HANGCHECK_WAIT && |
aa60c664 | 2332 | i915_request_guilty(request, acthd, &inside)) { |
86648500 | 2333 | DRM_DEBUG("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
aa60c664 MK |
2334 | ring->name, |
2335 | inside ? "inside" : "flushing", | |
d1ccbb5d | 2336 | offset, |
aa60c664 MK |
2337 | request->ctx ? request->ctx->id : 0, |
2338 | acthd); | |
2339 | ||
2340 | guilty = true; | |
2341 | } | |
2342 | ||
2343 | /* If contexts are disabled or this is the default context, use | |
2344 | * file_priv->reset_state | |
2345 | */ | |
2346 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) | |
2347 | hs = &request->ctx->hang_stats; | |
2348 | else if (request->file_priv) | |
2349 | hs = &request->file_priv->hang_stats; | |
2350 | ||
2351 | if (hs) { | |
be62acb4 MK |
2352 | if (guilty) { |
2353 | hs->banned = i915_context_is_banned(hs); | |
aa60c664 | 2354 | hs->batch_active++; |
be62acb4 MK |
2355 | hs->guilty_ts = get_seconds(); |
2356 | } else { | |
aa60c664 | 2357 | hs->batch_pending++; |
be62acb4 | 2358 | } |
aa60c664 MK |
2359 | } |
2360 | } | |
2361 | ||
0e50e96b MK |
2362 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2363 | { | |
2364 | list_del(&request->list); | |
2365 | i915_gem_request_remove_from_client(request); | |
2366 | ||
2367 | if (request->ctx) | |
2368 | i915_gem_context_unreference(request->ctx); | |
2369 | ||
2370 | kfree(request); | |
2371 | } | |
2372 | ||
4db080f9 CW |
2373 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, |
2374 | struct intel_ring_buffer *ring) | |
9375e446 | 2375 | { |
4db080f9 CW |
2376 | u32 completed_seqno = ring->get_seqno(ring, false); |
2377 | u32 acthd = intel_ring_get_active_head(ring); | |
2378 | struct drm_i915_gem_request *request; | |
2379 | ||
2380 | list_for_each_entry(request, &ring->request_list, list) { | |
2381 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2382 | continue; | |
aa60c664 | 2383 | |
4db080f9 CW |
2384 | i915_set_reset_status(ring, request, acthd); |
2385 | } | |
2386 | } | |
aa60c664 | 2387 | |
4db080f9 CW |
2388 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
2389 | struct intel_ring_buffer *ring) | |
2390 | { | |
dfaae392 | 2391 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2392 | struct drm_i915_gem_object *obj; |
9375e446 | 2393 | |
05394f39 CW |
2394 | obj = list_first_entry(&ring->active_list, |
2395 | struct drm_i915_gem_object, | |
2396 | ring_list); | |
9375e446 | 2397 | |
05394f39 | 2398 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2399 | } |
1d62beea BW |
2400 | |
2401 | /* | |
2402 | * We must free the requests after all the corresponding objects have | |
2403 | * been moved off active lists. Which is the same order as the normal | |
2404 | * retire_requests function does. This is important if object hold | |
2405 | * implicit references on things like e.g. ppgtt address spaces through | |
2406 | * the request. | |
2407 | */ | |
2408 | while (!list_empty(&ring->request_list)) { | |
2409 | struct drm_i915_gem_request *request; | |
2410 | ||
2411 | request = list_first_entry(&ring->request_list, | |
2412 | struct drm_i915_gem_request, | |
2413 | list); | |
2414 | ||
2415 | i915_gem_free_request(request); | |
2416 | } | |
673a394b EA |
2417 | } |
2418 | ||
19b2dbde | 2419 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2420 | { |
2421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2422 | int i; | |
2423 | ||
4b9de737 | 2424 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2425 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2426 | |
94a335db DV |
2427 | /* |
2428 | * Commit delayed tiling changes if we have an object still | |
2429 | * attached to the fence, otherwise just clear the fence. | |
2430 | */ | |
2431 | if (reg->obj) { | |
2432 | i915_gem_object_update_fence(reg->obj, reg, | |
2433 | reg->obj->tiling_mode); | |
2434 | } else { | |
2435 | i915_gem_write_fence(dev, i, NULL); | |
2436 | } | |
312817a3 CW |
2437 | } |
2438 | } | |
2439 | ||
069efc1d | 2440 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2441 | { |
77f01230 | 2442 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2443 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2444 | int i; |
673a394b | 2445 | |
4db080f9 CW |
2446 | /* |
2447 | * Before we free the objects from the requests, we need to inspect | |
2448 | * them for finding the guilty party. As the requests only borrow | |
2449 | * their reference to the objects, the inspection must be done first. | |
2450 | */ | |
2451 | for_each_ring(ring, dev_priv, i) | |
2452 | i915_gem_reset_ring_status(dev_priv, ring); | |
2453 | ||
b4519513 | 2454 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2455 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2456 | |
3d57e5bd BW |
2457 | i915_gem_cleanup_ringbuffer(dev); |
2458 | ||
19b2dbde | 2459 | i915_gem_restore_fences(dev); |
673a394b EA |
2460 | } |
2461 | ||
2462 | /** | |
2463 | * This function clears the request list as sequence numbers are passed. | |
2464 | */ | |
a71d8d94 | 2465 | void |
db53a302 | 2466 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2467 | { |
673a394b EA |
2468 | uint32_t seqno; |
2469 | ||
db53a302 | 2470 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2471 | return; |
2472 | ||
db53a302 | 2473 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2474 | |
b2eadbc8 | 2475 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2476 | |
852835f3 | 2477 | while (!list_empty(&ring->request_list)) { |
673a394b | 2478 | struct drm_i915_gem_request *request; |
673a394b | 2479 | |
852835f3 | 2480 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2481 | struct drm_i915_gem_request, |
2482 | list); | |
673a394b | 2483 | |
dfaae392 | 2484 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2485 | break; |
2486 | ||
db53a302 | 2487 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2488 | /* We know the GPU must have read the request to have |
2489 | * sent us the seqno + interrupt, so use the position | |
2490 | * of tail of the request to update the last known position | |
2491 | * of the GPU head. | |
2492 | */ | |
2493 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2494 | |
0e50e96b | 2495 | i915_gem_free_request(request); |
b84d5f0c | 2496 | } |
673a394b | 2497 | |
b84d5f0c CW |
2498 | /* Move any buffers on the active list that are no longer referenced |
2499 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2500 | */ | |
2501 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2502 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2503 | |
0206e353 | 2504 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2505 | struct drm_i915_gem_object, |
2506 | ring_list); | |
673a394b | 2507 | |
0201f1ec | 2508 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2509 | break; |
b84d5f0c | 2510 | |
65ce3027 | 2511 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2512 | } |
9d34e5db | 2513 | |
db53a302 CW |
2514 | if (unlikely(ring->trace_irq_seqno && |
2515 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2516 | ring->irq_put(ring); |
db53a302 | 2517 | ring->trace_irq_seqno = 0; |
9d34e5db | 2518 | } |
23bc5982 | 2519 | |
db53a302 | 2520 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2521 | } |
2522 | ||
b29c19b6 | 2523 | bool |
b09a1fec CW |
2524 | i915_gem_retire_requests(struct drm_device *dev) |
2525 | { | |
2526 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2527 | struct intel_ring_buffer *ring; |
b29c19b6 | 2528 | bool idle = true; |
1ec14ad3 | 2529 | int i; |
b09a1fec | 2530 | |
b29c19b6 | 2531 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2532 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2533 | idle &= list_empty(&ring->request_list); |
2534 | } | |
2535 | ||
2536 | if (idle) | |
2537 | mod_delayed_work(dev_priv->wq, | |
2538 | &dev_priv->mm.idle_work, | |
2539 | msecs_to_jiffies(100)); | |
2540 | ||
2541 | return idle; | |
b09a1fec CW |
2542 | } |
2543 | ||
75ef9da2 | 2544 | static void |
673a394b EA |
2545 | i915_gem_retire_work_handler(struct work_struct *work) |
2546 | { | |
b29c19b6 CW |
2547 | struct drm_i915_private *dev_priv = |
2548 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2549 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2550 | bool idle; |
673a394b | 2551 | |
891b48cf | 2552 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2553 | idle = false; |
2554 | if (mutex_trylock(&dev->struct_mutex)) { | |
2555 | idle = i915_gem_retire_requests(dev); | |
2556 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2557 | } |
b29c19b6 | 2558 | if (!idle) |
bcb45086 CW |
2559 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2560 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2561 | } |
0a58705b | 2562 | |
b29c19b6 CW |
2563 | static void |
2564 | i915_gem_idle_work_handler(struct work_struct *work) | |
2565 | { | |
2566 | struct drm_i915_private *dev_priv = | |
2567 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2568 | ||
2569 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2570 | } |
2571 | ||
30dfebf3 DV |
2572 | /** |
2573 | * Ensures that an object will eventually get non-busy by flushing any required | |
2574 | * write domains, emitting any outstanding lazy request and retiring and | |
2575 | * completed requests. | |
2576 | */ | |
2577 | static int | |
2578 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2579 | { | |
2580 | int ret; | |
2581 | ||
2582 | if (obj->active) { | |
0201f1ec | 2583 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2584 | if (ret) |
2585 | return ret; | |
2586 | ||
30dfebf3 DV |
2587 | i915_gem_retire_requests_ring(obj->ring); |
2588 | } | |
2589 | ||
2590 | return 0; | |
2591 | } | |
2592 | ||
23ba4fd0 BW |
2593 | /** |
2594 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2595 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2596 | * | |
2597 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2598 | * the timeout parameter. | |
2599 | * -ETIME: object is still busy after timeout | |
2600 | * -ERESTARTSYS: signal interrupted the wait | |
2601 | * -ENONENT: object doesn't exist | |
2602 | * Also possible, but rare: | |
2603 | * -EAGAIN: GPU wedged | |
2604 | * -ENOMEM: damn | |
2605 | * -ENODEV: Internal IRQ fail | |
2606 | * -E?: The add request failed | |
2607 | * | |
2608 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2609 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2610 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2611 | * without holding struct_mutex the object may become re-busied before this | |
2612 | * function completes. A similar but shorter * race condition exists in the busy | |
2613 | * ioctl | |
2614 | */ | |
2615 | int | |
2616 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2617 | { | |
f69061be | 2618 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2619 | struct drm_i915_gem_wait *args = data; |
2620 | struct drm_i915_gem_object *obj; | |
2621 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2622 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2623 | unsigned reset_counter; |
23ba4fd0 BW |
2624 | u32 seqno = 0; |
2625 | int ret = 0; | |
2626 | ||
eac1f14f BW |
2627 | if (args->timeout_ns >= 0) { |
2628 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2629 | timeout = &timeout_stack; | |
2630 | } | |
23ba4fd0 BW |
2631 | |
2632 | ret = i915_mutex_lock_interruptible(dev); | |
2633 | if (ret) | |
2634 | return ret; | |
2635 | ||
2636 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2637 | if (&obj->base == NULL) { | |
2638 | mutex_unlock(&dev->struct_mutex); | |
2639 | return -ENOENT; | |
2640 | } | |
2641 | ||
30dfebf3 DV |
2642 | /* Need to make sure the object gets inactive eventually. */ |
2643 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2644 | if (ret) |
2645 | goto out; | |
2646 | ||
2647 | if (obj->active) { | |
0201f1ec | 2648 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2649 | ring = obj->ring; |
2650 | } | |
2651 | ||
2652 | if (seqno == 0) | |
2653 | goto out; | |
2654 | ||
23ba4fd0 BW |
2655 | /* Do this after OLR check to make sure we make forward progress polling |
2656 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2657 | */ | |
2658 | if (!args->timeout_ns) { | |
2659 | ret = -ETIME; | |
2660 | goto out; | |
2661 | } | |
2662 | ||
2663 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2664 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2665 | mutex_unlock(&dev->struct_mutex); |
2666 | ||
b29c19b6 | 2667 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2668 | if (timeout) |
eac1f14f | 2669 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2670 | return ret; |
2671 | ||
2672 | out: | |
2673 | drm_gem_object_unreference(&obj->base); | |
2674 | mutex_unlock(&dev->struct_mutex); | |
2675 | return ret; | |
2676 | } | |
2677 | ||
5816d648 BW |
2678 | /** |
2679 | * i915_gem_object_sync - sync an object to a ring. | |
2680 | * | |
2681 | * @obj: object which may be in use on another ring. | |
2682 | * @to: ring we wish to use the object on. May be NULL. | |
2683 | * | |
2684 | * This code is meant to abstract object synchronization with the GPU. | |
2685 | * Calling with NULL implies synchronizing the object with the CPU | |
2686 | * rather than a particular GPU ring. | |
2687 | * | |
2688 | * Returns 0 if successful, else propagates up the lower layer error. | |
2689 | */ | |
2911a35b BW |
2690 | int |
2691 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2692 | struct intel_ring_buffer *to) | |
2693 | { | |
2694 | struct intel_ring_buffer *from = obj->ring; | |
2695 | u32 seqno; | |
2696 | int ret, idx; | |
2697 | ||
2698 | if (from == NULL || to == from) | |
2699 | return 0; | |
2700 | ||
5816d648 | 2701 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2702 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2703 | |
2704 | idx = intel_ring_sync_index(from, to); | |
2705 | ||
0201f1ec | 2706 | seqno = obj->last_read_seqno; |
2911a35b BW |
2707 | if (seqno <= from->sync_seqno[idx]) |
2708 | return 0; | |
2709 | ||
b4aca010 BW |
2710 | ret = i915_gem_check_olr(obj->ring, seqno); |
2711 | if (ret) | |
2712 | return ret; | |
2911a35b | 2713 | |
b52b89da | 2714 | trace_i915_gem_ring_sync_to(from, to, seqno); |
1500f7ea | 2715 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2716 | if (!ret) |
7b01e260 MK |
2717 | /* We use last_read_seqno because sync_to() |
2718 | * might have just caused seqno wrap under | |
2719 | * the radar. | |
2720 | */ | |
2721 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2722 | |
e3a5a225 | 2723 | return ret; |
2911a35b BW |
2724 | } |
2725 | ||
b5ffc9bc CW |
2726 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2727 | { | |
2728 | u32 old_write_domain, old_read_domains; | |
2729 | ||
b5ffc9bc CW |
2730 | /* Force a pagefault for domain tracking on next user access */ |
2731 | i915_gem_release_mmap(obj); | |
2732 | ||
b97c3d9c KP |
2733 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2734 | return; | |
2735 | ||
97c809fd CW |
2736 | /* Wait for any direct GTT access to complete */ |
2737 | mb(); | |
2738 | ||
b5ffc9bc CW |
2739 | old_read_domains = obj->base.read_domains; |
2740 | old_write_domain = obj->base.write_domain; | |
2741 | ||
2742 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2743 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2744 | ||
2745 | trace_i915_gem_object_change_domain(obj, | |
2746 | old_read_domains, | |
2747 | old_write_domain); | |
2748 | } | |
2749 | ||
07fe0b12 | 2750 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2751 | { |
07fe0b12 | 2752 | struct drm_i915_gem_object *obj = vma->obj; |
7bddb01f | 2753 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2754 | int ret; |
673a394b | 2755 | |
b93dab6e DV |
2756 | /* For now we only ever use 1 vma per object */ |
2757 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
2758 | ||
07fe0b12 | 2759 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2760 | return 0; |
2761 | ||
0ff501cb DV |
2762 | if (!drm_mm_node_allocated(&vma->node)) { |
2763 | i915_gem_vma_destroy(vma); | |
2764 | ||
2765 | return 0; | |
2766 | } | |
433544bd | 2767 | |
31d8d651 CW |
2768 | if (obj->pin_count) |
2769 | return -EBUSY; | |
673a394b | 2770 | |
c4670ad0 CW |
2771 | BUG_ON(obj->pages == NULL); |
2772 | ||
a8198eea | 2773 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2774 | if (ret) |
a8198eea CW |
2775 | return ret; |
2776 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2777 | * should be safe and we need to cleanup or else we might | |
2778 | * cause memory corruption through use-after-free. | |
2779 | */ | |
2780 | ||
b5ffc9bc | 2781 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2782 | |
96b47b65 | 2783 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2784 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2785 | if (ret) |
d9e86c0e | 2786 | return ret; |
96b47b65 | 2787 | |
07fe0b12 | 2788 | trace_i915_vma_unbind(vma); |
db53a302 | 2789 | |
74898d7e DV |
2790 | if (obj->has_global_gtt_mapping) |
2791 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2792 | if (obj->has_aliasing_ppgtt_mapping) { |
2793 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2794 | obj->has_aliasing_ppgtt_mapping = 0; | |
2795 | } | |
74163907 | 2796 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2797 | |
ca191b13 | 2798 | list_del(&vma->mm_list); |
75e9e915 | 2799 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2800 | if (i915_is_ggtt(vma->vm)) |
2801 | obj->map_and_fenceable = true; | |
673a394b | 2802 | |
2f633156 BW |
2803 | drm_mm_remove_node(&vma->node); |
2804 | i915_gem_vma_destroy(vma); | |
2805 | ||
2806 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2807 | * no more VMAs exist. */ |
2f633156 BW |
2808 | if (list_empty(&obj->vma_list)) |
2809 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2810 | |
70903c3b CW |
2811 | /* And finally now the object is completely decoupled from this vma, |
2812 | * we can drop its hold on the backing storage and allow it to be | |
2813 | * reaped by the shrinker. | |
2814 | */ | |
2815 | i915_gem_object_unpin_pages(obj); | |
2816 | ||
88241785 | 2817 | return 0; |
54cf91dc CW |
2818 | } |
2819 | ||
07fe0b12 BW |
2820 | /** |
2821 | * Unbinds an object from the global GTT aperture. | |
2822 | */ | |
2823 | int | |
2824 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2825 | { | |
2826 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2827 | struct i915_address_space *ggtt = &dev_priv->gtt.base; | |
2828 | ||
58e73e15 | 2829 | if (!i915_gem_obj_ggtt_bound(obj)) |
07fe0b12 BW |
2830 | return 0; |
2831 | ||
2832 | if (obj->pin_count) | |
2833 | return -EBUSY; | |
2834 | ||
2835 | BUG_ON(obj->pages == NULL); | |
2836 | ||
2837 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); | |
2838 | } | |
2839 | ||
b2da9fe5 | 2840 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2841 | { |
2842 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2843 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2844 | int ret, i; |
4df2faf4 | 2845 | |
4df2faf4 | 2846 | /* Flush everything onto the inactive list. */ |
b4519513 | 2847 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2848 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2849 | if (ret) | |
2850 | return ret; | |
2851 | ||
3e960501 | 2852 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2853 | if (ret) |
2854 | return ret; | |
2855 | } | |
4df2faf4 | 2856 | |
8a1a49f9 | 2857 | return 0; |
4df2faf4 DV |
2858 | } |
2859 | ||
9ce079e4 CW |
2860 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2861 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2862 | { |
de151cf6 | 2863 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2864 | int fence_reg; |
2865 | int fence_pitch_shift; | |
de151cf6 | 2866 | |
56c844e5 ID |
2867 | if (INTEL_INFO(dev)->gen >= 6) { |
2868 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2869 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2870 | } else { | |
2871 | fence_reg = FENCE_REG_965_0; | |
2872 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2873 | } | |
2874 | ||
d18b9619 CW |
2875 | fence_reg += reg * 8; |
2876 | ||
2877 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2878 | * we split the 64-bit update into two 32-bit writes. In order | |
2879 | * for a partial fence not to be evaluated between writes, we | |
2880 | * precede the update with write to turn off the fence register, | |
2881 | * and only enable the fence as the last step. | |
2882 | * | |
2883 | * For extra levels of paranoia, we make sure each step lands | |
2884 | * before applying the next step. | |
2885 | */ | |
2886 | I915_WRITE(fence_reg, 0); | |
2887 | POSTING_READ(fence_reg); | |
2888 | ||
9ce079e4 | 2889 | if (obj) { |
f343c5f6 | 2890 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2891 | uint64_t val; |
de151cf6 | 2892 | |
f343c5f6 | 2893 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2894 | 0xfffff000) << 32; |
f343c5f6 | 2895 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2896 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2897 | if (obj->tiling_mode == I915_TILING_Y) |
2898 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2899 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2900 | |
d18b9619 CW |
2901 | I915_WRITE(fence_reg + 4, val >> 32); |
2902 | POSTING_READ(fence_reg + 4); | |
2903 | ||
2904 | I915_WRITE(fence_reg + 0, val); | |
2905 | POSTING_READ(fence_reg); | |
2906 | } else { | |
2907 | I915_WRITE(fence_reg + 4, 0); | |
2908 | POSTING_READ(fence_reg + 4); | |
2909 | } | |
de151cf6 JB |
2910 | } |
2911 | ||
9ce079e4 CW |
2912 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2913 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2914 | { |
de151cf6 | 2915 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2916 | u32 val; |
de151cf6 | 2917 | |
9ce079e4 | 2918 | if (obj) { |
f343c5f6 | 2919 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2920 | int pitch_val; |
2921 | int tile_width; | |
c6642782 | 2922 | |
f343c5f6 | 2923 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2924 | (size & -size) != size || |
f343c5f6 BW |
2925 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2926 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2927 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2928 | |
9ce079e4 CW |
2929 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2930 | tile_width = 128; | |
2931 | else | |
2932 | tile_width = 512; | |
2933 | ||
2934 | /* Note: pitch better be a power of two tile widths */ | |
2935 | pitch_val = obj->stride / tile_width; | |
2936 | pitch_val = ffs(pitch_val) - 1; | |
2937 | ||
f343c5f6 | 2938 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2939 | if (obj->tiling_mode == I915_TILING_Y) |
2940 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2941 | val |= I915_FENCE_SIZE_BITS(size); | |
2942 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2943 | val |= I830_FENCE_REG_VALID; | |
2944 | } else | |
2945 | val = 0; | |
2946 | ||
2947 | if (reg < 8) | |
2948 | reg = FENCE_REG_830_0 + reg * 4; | |
2949 | else | |
2950 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2951 | ||
2952 | I915_WRITE(reg, val); | |
2953 | POSTING_READ(reg); | |
de151cf6 JB |
2954 | } |
2955 | ||
9ce079e4 CW |
2956 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2957 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2958 | { |
de151cf6 | 2959 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2960 | uint32_t val; |
de151cf6 | 2961 | |
9ce079e4 | 2962 | if (obj) { |
f343c5f6 | 2963 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2964 | uint32_t pitch_val; |
de151cf6 | 2965 | |
f343c5f6 | 2966 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2967 | (size & -size) != size || |
f343c5f6 BW |
2968 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2969 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2970 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2971 | |
9ce079e4 CW |
2972 | pitch_val = obj->stride / 128; |
2973 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2974 | |
f343c5f6 | 2975 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2976 | if (obj->tiling_mode == I915_TILING_Y) |
2977 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2978 | val |= I830_FENCE_SIZE_BITS(size); | |
2979 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2980 | val |= I830_FENCE_REG_VALID; | |
2981 | } else | |
2982 | val = 0; | |
c6642782 | 2983 | |
9ce079e4 CW |
2984 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2985 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2986 | } | |
2987 | ||
d0a57789 CW |
2988 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2989 | { | |
2990 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2991 | } | |
2992 | ||
9ce079e4 CW |
2993 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2994 | struct drm_i915_gem_object *obj) | |
2995 | { | |
d0a57789 CW |
2996 | struct drm_i915_private *dev_priv = dev->dev_private; |
2997 | ||
2998 | /* Ensure that all CPU reads are completed before installing a fence | |
2999 | * and all writes before removing the fence. | |
3000 | */ | |
3001 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3002 | mb(); | |
3003 | ||
94a335db DV |
3004 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3005 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3006 | obj->stride, obj->tiling_mode); | |
3007 | ||
9ce079e4 | 3008 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 3009 | case 8: |
9ce079e4 | 3010 | case 7: |
56c844e5 | 3011 | case 6: |
9ce079e4 CW |
3012 | case 5: |
3013 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
3014 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
3015 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 3016 | default: BUG(); |
9ce079e4 | 3017 | } |
d0a57789 CW |
3018 | |
3019 | /* And similarly be paranoid that no direct access to this region | |
3020 | * is reordered to before the fence is installed. | |
3021 | */ | |
3022 | if (i915_gem_object_needs_mb(obj)) | |
3023 | mb(); | |
de151cf6 JB |
3024 | } |
3025 | ||
61050808 CW |
3026 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3027 | struct drm_i915_fence_reg *fence) | |
3028 | { | |
3029 | return fence - dev_priv->fence_regs; | |
3030 | } | |
3031 | ||
3032 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3033 | struct drm_i915_fence_reg *fence, | |
3034 | bool enable) | |
3035 | { | |
2dc8aae0 | 3036 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3037 | int reg = fence_number(dev_priv, fence); |
3038 | ||
3039 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3040 | |
3041 | if (enable) { | |
46a0b638 | 3042 | obj->fence_reg = reg; |
61050808 CW |
3043 | fence->obj = obj; |
3044 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3045 | } else { | |
3046 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3047 | fence->obj = NULL; | |
3048 | list_del_init(&fence->lru_list); | |
3049 | } | |
94a335db | 3050 | obj->fence_dirty = false; |
61050808 CW |
3051 | } |
3052 | ||
d9e86c0e | 3053 | static int |
d0a57789 | 3054 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3055 | { |
1c293ea3 | 3056 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3057 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3058 | if (ret) |
3059 | return ret; | |
d9e86c0e CW |
3060 | |
3061 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3062 | } |
3063 | ||
86d5bc37 | 3064 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3065 | return 0; |
3066 | } | |
3067 | ||
3068 | int | |
3069 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3070 | { | |
61050808 | 3071 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3072 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3073 | int ret; |
3074 | ||
d0a57789 | 3075 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3076 | if (ret) |
3077 | return ret; | |
3078 | ||
61050808 CW |
3079 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3080 | return 0; | |
d9e86c0e | 3081 | |
f9c513e9 CW |
3082 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3083 | ||
61050808 | 3084 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3085 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3086 | |
3087 | return 0; | |
3088 | } | |
3089 | ||
3090 | static struct drm_i915_fence_reg * | |
a360bb1a | 3091 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3092 | { |
ae3db24a | 3093 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3094 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3095 | int i; |
ae3db24a DV |
3096 | |
3097 | /* First try to find a free reg */ | |
d9e86c0e | 3098 | avail = NULL; |
ae3db24a DV |
3099 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3100 | reg = &dev_priv->fence_regs[i]; | |
3101 | if (!reg->obj) | |
d9e86c0e | 3102 | return reg; |
ae3db24a | 3103 | |
1690e1eb | 3104 | if (!reg->pin_count) |
d9e86c0e | 3105 | avail = reg; |
ae3db24a DV |
3106 | } |
3107 | ||
d9e86c0e CW |
3108 | if (avail == NULL) |
3109 | return NULL; | |
ae3db24a DV |
3110 | |
3111 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3112 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3113 | if (reg->pin_count) |
ae3db24a DV |
3114 | continue; |
3115 | ||
8fe301ad | 3116 | return reg; |
ae3db24a DV |
3117 | } |
3118 | ||
8fe301ad | 3119 | return NULL; |
ae3db24a DV |
3120 | } |
3121 | ||
de151cf6 | 3122 | /** |
9a5a53b3 | 3123 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3124 | * @obj: object to map through a fence reg |
3125 | * | |
3126 | * When mapping objects through the GTT, userspace wants to be able to write | |
3127 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3128 | * This function walks the fence regs looking for a free one for @obj, |
3129 | * stealing one if it can't find any. | |
3130 | * | |
3131 | * It then sets up the reg based on the object's properties: address, pitch | |
3132 | * and tiling format. | |
9a5a53b3 CW |
3133 | * |
3134 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3135 | */ |
8c4b8c3f | 3136 | int |
06d98131 | 3137 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3138 | { |
05394f39 | 3139 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3140 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3141 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3142 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3143 | int ret; |
de151cf6 | 3144 | |
14415745 CW |
3145 | /* Have we updated the tiling parameters upon the object and so |
3146 | * will need to serialise the write to the associated fence register? | |
3147 | */ | |
5d82e3e6 | 3148 | if (obj->fence_dirty) { |
d0a57789 | 3149 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3150 | if (ret) |
3151 | return ret; | |
3152 | } | |
9a5a53b3 | 3153 | |
d9e86c0e | 3154 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3155 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3156 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3157 | if (!obj->fence_dirty) { |
14415745 CW |
3158 | list_move_tail(®->lru_list, |
3159 | &dev_priv->mm.fence_list); | |
3160 | return 0; | |
3161 | } | |
3162 | } else if (enable) { | |
3163 | reg = i915_find_fence_reg(dev); | |
3164 | if (reg == NULL) | |
3165 | return -EDEADLK; | |
d9e86c0e | 3166 | |
14415745 CW |
3167 | if (reg->obj) { |
3168 | struct drm_i915_gem_object *old = reg->obj; | |
3169 | ||
d0a57789 | 3170 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3171 | if (ret) |
3172 | return ret; | |
3173 | ||
14415745 | 3174 | i915_gem_object_fence_lost(old); |
29c5a587 | 3175 | } |
14415745 | 3176 | } else |
a09ba7fa | 3177 | return 0; |
a09ba7fa | 3178 | |
14415745 | 3179 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3180 | |
9ce079e4 | 3181 | return 0; |
de151cf6 JB |
3182 | } |
3183 | ||
42d6ab48 CW |
3184 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3185 | struct drm_mm_node *gtt_space, | |
3186 | unsigned long cache_level) | |
3187 | { | |
3188 | struct drm_mm_node *other; | |
3189 | ||
3190 | /* On non-LLC machines we have to be careful when putting differing | |
3191 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3192 | * crossing memory domains and dying. |
42d6ab48 CW |
3193 | */ |
3194 | if (HAS_LLC(dev)) | |
3195 | return true; | |
3196 | ||
c6cfb325 | 3197 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3198 | return true; |
3199 | ||
3200 | if (list_empty(>t_space->node_list)) | |
3201 | return true; | |
3202 | ||
3203 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3204 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3205 | return false; | |
3206 | ||
3207 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3208 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3209 | return false; | |
3210 | ||
3211 | return true; | |
3212 | } | |
3213 | ||
3214 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3215 | { | |
3216 | #if WATCH_GTT | |
3217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3218 | struct drm_i915_gem_object *obj; | |
3219 | int err = 0; | |
3220 | ||
35c20a60 | 3221 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3222 | if (obj->gtt_space == NULL) { |
3223 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3224 | err++; | |
3225 | continue; | |
3226 | } | |
3227 | ||
3228 | if (obj->cache_level != obj->gtt_space->color) { | |
3229 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3230 | i915_gem_obj_ggtt_offset(obj), |
3231 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3232 | obj->cache_level, |
3233 | obj->gtt_space->color); | |
3234 | err++; | |
3235 | continue; | |
3236 | } | |
3237 | ||
3238 | if (!i915_gem_valid_gtt_space(dev, | |
3239 | obj->gtt_space, | |
3240 | obj->cache_level)) { | |
3241 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3242 | i915_gem_obj_ggtt_offset(obj), |
3243 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3244 | obj->cache_level); |
3245 | err++; | |
3246 | continue; | |
3247 | } | |
3248 | } | |
3249 | ||
3250 | WARN_ON(err); | |
3251 | #endif | |
3252 | } | |
3253 | ||
673a394b EA |
3254 | /** |
3255 | * Finds free space in the GTT aperture and binds the object there. | |
3256 | */ | |
3257 | static int | |
07fe0b12 BW |
3258 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3259 | struct i915_address_space *vm, | |
3260 | unsigned alignment, | |
3261 | bool map_and_fenceable, | |
3262 | bool nonblocking) | |
673a394b | 3263 | { |
05394f39 | 3264 | struct drm_device *dev = obj->base.dev; |
673a394b | 3265 | drm_i915_private_t *dev_priv = dev->dev_private; |
5e783301 | 3266 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 BW |
3267 | size_t gtt_max = |
3268 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; | |
2f633156 | 3269 | struct i915_vma *vma; |
07f73f69 | 3270 | int ret; |
673a394b | 3271 | |
e28f8711 CW |
3272 | fence_size = i915_gem_get_gtt_size(dev, |
3273 | obj->base.size, | |
3274 | obj->tiling_mode); | |
3275 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3276 | obj->base.size, | |
d865110c | 3277 | obj->tiling_mode, true); |
e28f8711 | 3278 | unfenced_alignment = |
d865110c | 3279 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 3280 | obj->base.size, |
d865110c | 3281 | obj->tiling_mode, false); |
a00b10c3 | 3282 | |
673a394b | 3283 | if (alignment == 0) |
5e783301 DV |
3284 | alignment = map_and_fenceable ? fence_alignment : |
3285 | unfenced_alignment; | |
75e9e915 | 3286 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
3287 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3288 | return -EINVAL; | |
3289 | } | |
3290 | ||
05394f39 | 3291 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 3292 | |
654fc607 CW |
3293 | /* If the object is bigger than the entire aperture, reject it early |
3294 | * before evicting everything in a vain attempt to find space. | |
3295 | */ | |
0a9ae0d7 | 3296 | if (obj->base.size > gtt_max) { |
3765f304 | 3297 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb CW |
3298 | obj->base.size, |
3299 | map_and_fenceable ? "mappable" : "total", | |
0a9ae0d7 | 3300 | gtt_max); |
654fc607 CW |
3301 | return -E2BIG; |
3302 | } | |
3303 | ||
37e680a1 | 3304 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
3305 | if (ret) |
3306 | return ret; | |
3307 | ||
fbdda6fb CW |
3308 | i915_gem_object_pin_pages(obj); |
3309 | ||
07fe0b12 | 3310 | BUG_ON(!i915_is_ggtt(vm)); |
07fe0b12 | 3311 | |
accfef2e | 3312 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
db473b36 | 3313 | if (IS_ERR(vma)) { |
bc6bc15b DV |
3314 | ret = PTR_ERR(vma); |
3315 | goto err_unpin; | |
2f633156 BW |
3316 | } |
3317 | ||
accfef2e BW |
3318 | /* For now we only ever use 1 vma per object */ |
3319 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
3320 | ||
0a9ae0d7 | 3321 | search_free: |
07fe0b12 | 3322 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3323 | size, alignment, |
31e5d7c6 DH |
3324 | obj->cache_level, 0, gtt_max, |
3325 | DRM_MM_SEARCH_DEFAULT); | |
dc9dd7a2 | 3326 | if (ret) { |
f6cd1f15 | 3327 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
42d6ab48 | 3328 | obj->cache_level, |
86a1ee26 CW |
3329 | map_and_fenceable, |
3330 | nonblocking); | |
dc9dd7a2 CW |
3331 | if (ret == 0) |
3332 | goto search_free; | |
9731129c | 3333 | |
bc6bc15b | 3334 | goto err_free_vma; |
673a394b | 3335 | } |
2f633156 | 3336 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3337 | obj->cache_level))) { |
2f633156 | 3338 | ret = -EINVAL; |
bc6bc15b | 3339 | goto err_remove_node; |
673a394b EA |
3340 | } |
3341 | ||
74163907 | 3342 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3343 | if (ret) |
bc6bc15b | 3344 | goto err_remove_node; |
673a394b | 3345 | |
35c20a60 | 3346 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3347 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3348 | |
4bd561b3 BW |
3349 | if (i915_is_ggtt(vm)) { |
3350 | bool mappable, fenceable; | |
a00b10c3 | 3351 | |
49987099 DV |
3352 | fenceable = (vma->node.size == fence_size && |
3353 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3354 | |
49987099 DV |
3355 | mappable = (vma->node.start + obj->base.size <= |
3356 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3357 | |
5cacaac7 | 3358 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3359 | } |
75e9e915 | 3360 | |
7ace7ef2 | 3361 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
75e9e915 | 3362 | |
07fe0b12 | 3363 | trace_i915_vma_bind(vma, map_and_fenceable); |
42d6ab48 | 3364 | i915_gem_verify_gtt(dev); |
673a394b | 3365 | return 0; |
2f633156 | 3366 | |
bc6bc15b | 3367 | err_remove_node: |
6286ef9b | 3368 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3369 | err_free_vma: |
2f633156 | 3370 | i915_gem_vma_destroy(vma); |
bc6bc15b | 3371 | err_unpin: |
2f633156 | 3372 | i915_gem_object_unpin_pages(obj); |
2f633156 | 3373 | return ret; |
673a394b EA |
3374 | } |
3375 | ||
000433b6 | 3376 | bool |
2c22569b CW |
3377 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3378 | bool force) | |
673a394b | 3379 | { |
673a394b EA |
3380 | /* If we don't have a page list set up, then we're not pinned |
3381 | * to GPU, and we can ignore the cache flush because it'll happen | |
3382 | * again at bind time. | |
3383 | */ | |
05394f39 | 3384 | if (obj->pages == NULL) |
000433b6 | 3385 | return false; |
673a394b | 3386 | |
769ce464 ID |
3387 | /* |
3388 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3389 | * marked as wc by the system, or the system is cache-coherent. | |
3390 | */ | |
3391 | if (obj->stolen) | |
000433b6 | 3392 | return false; |
769ce464 | 3393 | |
9c23f7fc CW |
3394 | /* If the GPU is snooping the contents of the CPU cache, |
3395 | * we do not need to manually clear the CPU cache lines. However, | |
3396 | * the caches are only snooped when the render cache is | |
3397 | * flushed/invalidated. As we always have to emit invalidations | |
3398 | * and flushes when moving into and out of the RENDER domain, correct | |
3399 | * snooping behaviour occurs naturally as the result of our domain | |
3400 | * tracking. | |
3401 | */ | |
2c22569b | 3402 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3403 | return false; |
9c23f7fc | 3404 | |
1c5d22f7 | 3405 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3406 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3407 | |
3408 | return true; | |
e47c68e9 EA |
3409 | } |
3410 | ||
3411 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3412 | static void | |
05394f39 | 3413 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3414 | { |
1c5d22f7 CW |
3415 | uint32_t old_write_domain; |
3416 | ||
05394f39 | 3417 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3418 | return; |
3419 | ||
63256ec5 | 3420 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3421 | * to it immediately go to main memory as far as we know, so there's |
3422 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3423 | * |
3424 | * However, we do have to enforce the order so that all writes through | |
3425 | * the GTT land before any writes to the device, such as updates to | |
3426 | * the GATT itself. | |
e47c68e9 | 3427 | */ |
63256ec5 CW |
3428 | wmb(); |
3429 | ||
05394f39 CW |
3430 | old_write_domain = obj->base.write_domain; |
3431 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3432 | |
3433 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3434 | obj->base.read_domains, |
1c5d22f7 | 3435 | old_write_domain); |
e47c68e9 EA |
3436 | } |
3437 | ||
3438 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3439 | static void | |
2c22569b CW |
3440 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3441 | bool force) | |
e47c68e9 | 3442 | { |
1c5d22f7 | 3443 | uint32_t old_write_domain; |
e47c68e9 | 3444 | |
05394f39 | 3445 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3446 | return; |
3447 | ||
000433b6 CW |
3448 | if (i915_gem_clflush_object(obj, force)) |
3449 | i915_gem_chipset_flush(obj->base.dev); | |
3450 | ||
05394f39 CW |
3451 | old_write_domain = obj->base.write_domain; |
3452 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3453 | |
3454 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3455 | obj->base.read_domains, |
1c5d22f7 | 3456 | old_write_domain); |
e47c68e9 EA |
3457 | } |
3458 | ||
2ef7eeaa EA |
3459 | /** |
3460 | * Moves a single object to the GTT read, and possibly write domain. | |
3461 | * | |
3462 | * This function returns when the move is complete, including waiting on | |
3463 | * flushes to occur. | |
3464 | */ | |
79e53945 | 3465 | int |
2021746e | 3466 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3467 | { |
8325a09d | 3468 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3469 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3470 | int ret; |
2ef7eeaa | 3471 | |
02354392 | 3472 | /* Not valid to be called on unbound objects. */ |
9843877d | 3473 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3474 | return -EINVAL; |
3475 | ||
8d7e3de1 CW |
3476 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3477 | return 0; | |
3478 | ||
0201f1ec | 3479 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3480 | if (ret) |
3481 | return ret; | |
3482 | ||
2c22569b | 3483 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3484 | |
d0a57789 CW |
3485 | /* Serialise direct access to this object with the barriers for |
3486 | * coherent writes from the GPU, by effectively invalidating the | |
3487 | * GTT domain upon first access. | |
3488 | */ | |
3489 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3490 | mb(); | |
3491 | ||
05394f39 CW |
3492 | old_write_domain = obj->base.write_domain; |
3493 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3494 | |
e47c68e9 EA |
3495 | /* It should now be out of any other write domains, and we can update |
3496 | * the domain values for our changes. | |
3497 | */ | |
05394f39 CW |
3498 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3499 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3500 | if (write) { |
05394f39 CW |
3501 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3502 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3503 | obj->dirty = 1; | |
2ef7eeaa EA |
3504 | } |
3505 | ||
1c5d22f7 CW |
3506 | trace_i915_gem_object_change_domain(obj, |
3507 | old_read_domains, | |
3508 | old_write_domain); | |
3509 | ||
8325a09d | 3510 | /* And bump the LRU for this access */ |
ca191b13 | 3511 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3512 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3513 | if (vma) |
3514 | list_move_tail(&vma->mm_list, | |
3515 | &dev_priv->gtt.base.inactive_list); | |
3516 | ||
3517 | } | |
8325a09d | 3518 | |
e47c68e9 EA |
3519 | return 0; |
3520 | } | |
3521 | ||
e4ffd173 CW |
3522 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3523 | enum i915_cache_level cache_level) | |
3524 | { | |
7bddb01f DV |
3525 | struct drm_device *dev = obj->base.dev; |
3526 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3089c6f2 | 3527 | struct i915_vma *vma; |
e4ffd173 CW |
3528 | int ret; |
3529 | ||
3530 | if (obj->cache_level == cache_level) | |
3531 | return 0; | |
3532 | ||
3533 | if (obj->pin_count) { | |
3534 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3535 | return -EBUSY; | |
3536 | } | |
3537 | ||
3089c6f2 BW |
3538 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3539 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { | |
07fe0b12 | 3540 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3541 | if (ret) |
3542 | return ret; | |
3543 | ||
3544 | break; | |
3545 | } | |
42d6ab48 CW |
3546 | } |
3547 | ||
3089c6f2 | 3548 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3549 | ret = i915_gem_object_finish_gpu(obj); |
3550 | if (ret) | |
3551 | return ret; | |
3552 | ||
3553 | i915_gem_object_finish_gtt(obj); | |
3554 | ||
3555 | /* Before SandyBridge, you could not use tiling or fence | |
3556 | * registers with snooped memory, so relinquish any fences | |
3557 | * currently pointing to our region in the aperture. | |
3558 | */ | |
42d6ab48 | 3559 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3560 | ret = i915_gem_object_put_fence(obj); |
3561 | if (ret) | |
3562 | return ret; | |
3563 | } | |
3564 | ||
74898d7e DV |
3565 | if (obj->has_global_gtt_mapping) |
3566 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3567 | if (obj->has_aliasing_ppgtt_mapping) |
3568 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3569 | obj, cache_level); | |
e4ffd173 CW |
3570 | } |
3571 | ||
2c22569b CW |
3572 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3573 | vma->node.color = cache_level; | |
3574 | obj->cache_level = cache_level; | |
3575 | ||
3576 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3577 | u32 old_read_domains, old_write_domain; |
3578 | ||
3579 | /* If we're coming from LLC cached, then we haven't | |
3580 | * actually been tracking whether the data is in the | |
3581 | * CPU cache or not, since we only allow one bit set | |
3582 | * in obj->write_domain and have been skipping the clflushes. | |
3583 | * Just set it to the CPU cache for now. | |
3584 | */ | |
3585 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
e4ffd173 CW |
3586 | |
3587 | old_read_domains = obj->base.read_domains; | |
3588 | old_write_domain = obj->base.write_domain; | |
3589 | ||
3590 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3591 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3592 | ||
3593 | trace_i915_gem_object_change_domain(obj, | |
3594 | old_read_domains, | |
3595 | old_write_domain); | |
3596 | } | |
3597 | ||
42d6ab48 | 3598 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3599 | return 0; |
3600 | } | |
3601 | ||
199adf40 BW |
3602 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3603 | struct drm_file *file) | |
e6994aee | 3604 | { |
199adf40 | 3605 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3606 | struct drm_i915_gem_object *obj; |
3607 | int ret; | |
3608 | ||
3609 | ret = i915_mutex_lock_interruptible(dev); | |
3610 | if (ret) | |
3611 | return ret; | |
3612 | ||
3613 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3614 | if (&obj->base == NULL) { | |
3615 | ret = -ENOENT; | |
3616 | goto unlock; | |
3617 | } | |
3618 | ||
651d794f CW |
3619 | switch (obj->cache_level) { |
3620 | case I915_CACHE_LLC: | |
3621 | case I915_CACHE_L3_LLC: | |
3622 | args->caching = I915_CACHING_CACHED; | |
3623 | break; | |
3624 | ||
4257d3ba CW |
3625 | case I915_CACHE_WT: |
3626 | args->caching = I915_CACHING_DISPLAY; | |
3627 | break; | |
3628 | ||
651d794f CW |
3629 | default: |
3630 | args->caching = I915_CACHING_NONE; | |
3631 | break; | |
3632 | } | |
e6994aee CW |
3633 | |
3634 | drm_gem_object_unreference(&obj->base); | |
3635 | unlock: | |
3636 | mutex_unlock(&dev->struct_mutex); | |
3637 | return ret; | |
3638 | } | |
3639 | ||
199adf40 BW |
3640 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3641 | struct drm_file *file) | |
e6994aee | 3642 | { |
199adf40 | 3643 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3644 | struct drm_i915_gem_object *obj; |
3645 | enum i915_cache_level level; | |
3646 | int ret; | |
3647 | ||
199adf40 BW |
3648 | switch (args->caching) { |
3649 | case I915_CACHING_NONE: | |
e6994aee CW |
3650 | level = I915_CACHE_NONE; |
3651 | break; | |
199adf40 | 3652 | case I915_CACHING_CACHED: |
e6994aee CW |
3653 | level = I915_CACHE_LLC; |
3654 | break; | |
4257d3ba CW |
3655 | case I915_CACHING_DISPLAY: |
3656 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3657 | break; | |
e6994aee CW |
3658 | default: |
3659 | return -EINVAL; | |
3660 | } | |
3661 | ||
3bc2913e BW |
3662 | ret = i915_mutex_lock_interruptible(dev); |
3663 | if (ret) | |
3664 | return ret; | |
3665 | ||
e6994aee CW |
3666 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3667 | if (&obj->base == NULL) { | |
3668 | ret = -ENOENT; | |
3669 | goto unlock; | |
3670 | } | |
3671 | ||
3672 | ret = i915_gem_object_set_cache_level(obj, level); | |
3673 | ||
3674 | drm_gem_object_unreference(&obj->base); | |
3675 | unlock: | |
3676 | mutex_unlock(&dev->struct_mutex); | |
3677 | return ret; | |
3678 | } | |
3679 | ||
cc98b413 CW |
3680 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3681 | { | |
3682 | /* There are 3 sources that pin objects: | |
3683 | * 1. The display engine (scanouts, sprites, cursors); | |
3684 | * 2. Reservations for execbuffer; | |
3685 | * 3. The user. | |
3686 | * | |
3687 | * We can ignore reservations as we hold the struct_mutex and | |
3688 | * are only called outside of the reservation path. The user | |
3689 | * can only increment pin_count once, and so if after | |
3690 | * subtracting the potential reference by the user, any pin_count | |
3691 | * remains, it must be due to another use by the display engine. | |
3692 | */ | |
3693 | return obj->pin_count - !!obj->user_pin_count; | |
3694 | } | |
3695 | ||
b9241ea3 | 3696 | /* |
2da3b9b9 CW |
3697 | * Prepare buffer for display plane (scanout, cursors, etc). |
3698 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3699 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3700 | */ |
3701 | int | |
2da3b9b9 CW |
3702 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3703 | u32 alignment, | |
919926ae | 3704 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3705 | { |
2da3b9b9 | 3706 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3707 | int ret; |
3708 | ||
0be73284 | 3709 | if (pipelined != obj->ring) { |
2911a35b BW |
3710 | ret = i915_gem_object_sync(obj, pipelined); |
3711 | if (ret) | |
b9241ea3 ZW |
3712 | return ret; |
3713 | } | |
3714 | ||
cc98b413 CW |
3715 | /* Mark the pin_display early so that we account for the |
3716 | * display coherency whilst setting up the cache domains. | |
3717 | */ | |
3718 | obj->pin_display = true; | |
3719 | ||
a7ef0640 EA |
3720 | /* The display engine is not coherent with the LLC cache on gen6. As |
3721 | * a result, we make sure that the pinning that is about to occur is | |
3722 | * done with uncached PTEs. This is lowest common denominator for all | |
3723 | * chipsets. | |
3724 | * | |
3725 | * However for gen6+, we could do better by using the GFDT bit instead | |
3726 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3727 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3728 | */ | |
651d794f CW |
3729 | ret = i915_gem_object_set_cache_level(obj, |
3730 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3731 | if (ret) |
cc98b413 | 3732 | goto err_unpin_display; |
a7ef0640 | 3733 | |
2da3b9b9 CW |
3734 | /* As the user may map the buffer once pinned in the display plane |
3735 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3736 | * always use map_and_fenceable for all scanout buffers. | |
3737 | */ | |
c37e2204 | 3738 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
2da3b9b9 | 3739 | if (ret) |
cc98b413 | 3740 | goto err_unpin_display; |
2da3b9b9 | 3741 | |
2c22569b | 3742 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3743 | |
2da3b9b9 | 3744 | old_write_domain = obj->base.write_domain; |
05394f39 | 3745 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3746 | |
3747 | /* It should now be out of any other write domains, and we can update | |
3748 | * the domain values for our changes. | |
3749 | */ | |
e5f1d962 | 3750 | obj->base.write_domain = 0; |
05394f39 | 3751 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3752 | |
3753 | trace_i915_gem_object_change_domain(obj, | |
3754 | old_read_domains, | |
2da3b9b9 | 3755 | old_write_domain); |
b9241ea3 ZW |
3756 | |
3757 | return 0; | |
cc98b413 CW |
3758 | |
3759 | err_unpin_display: | |
3760 | obj->pin_display = is_pin_display(obj); | |
3761 | return ret; | |
3762 | } | |
3763 | ||
3764 | void | |
3765 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3766 | { | |
3767 | i915_gem_object_unpin(obj); | |
3768 | obj->pin_display = is_pin_display(obj); | |
b9241ea3 ZW |
3769 | } |
3770 | ||
85345517 | 3771 | int |
a8198eea | 3772 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3773 | { |
88241785 CW |
3774 | int ret; |
3775 | ||
a8198eea | 3776 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3777 | return 0; |
3778 | ||
0201f1ec | 3779 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3780 | if (ret) |
3781 | return ret; | |
3782 | ||
a8198eea CW |
3783 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3784 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3785 | return 0; |
85345517 CW |
3786 | } |
3787 | ||
e47c68e9 EA |
3788 | /** |
3789 | * Moves a single object to the CPU read, and possibly write domain. | |
3790 | * | |
3791 | * This function returns when the move is complete, including waiting on | |
3792 | * flushes to occur. | |
3793 | */ | |
dabdfe02 | 3794 | int |
919926ae | 3795 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3796 | { |
1c5d22f7 | 3797 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3798 | int ret; |
3799 | ||
8d7e3de1 CW |
3800 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3801 | return 0; | |
3802 | ||
0201f1ec | 3803 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3804 | if (ret) |
3805 | return ret; | |
3806 | ||
e47c68e9 | 3807 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3808 | |
05394f39 CW |
3809 | old_write_domain = obj->base.write_domain; |
3810 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3811 | |
e47c68e9 | 3812 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3813 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3814 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3815 | |
05394f39 | 3816 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3817 | } |
3818 | ||
3819 | /* It should now be out of any other write domains, and we can update | |
3820 | * the domain values for our changes. | |
3821 | */ | |
05394f39 | 3822 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3823 | |
3824 | /* If we're writing through the CPU, then the GPU read domains will | |
3825 | * need to be invalidated at next use. | |
3826 | */ | |
3827 | if (write) { | |
05394f39 CW |
3828 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3829 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3830 | } |
2ef7eeaa | 3831 | |
1c5d22f7 CW |
3832 | trace_i915_gem_object_change_domain(obj, |
3833 | old_read_domains, | |
3834 | old_write_domain); | |
3835 | ||
2ef7eeaa EA |
3836 | return 0; |
3837 | } | |
3838 | ||
673a394b EA |
3839 | /* Throttle our rendering by waiting until the ring has completed our requests |
3840 | * emitted over 20 msec ago. | |
3841 | * | |
b962442e EA |
3842 | * Note that if we were to use the current jiffies each time around the loop, |
3843 | * we wouldn't escape the function with any frames outstanding if the time to | |
3844 | * render a frame was over 20ms. | |
3845 | * | |
673a394b EA |
3846 | * This should get us reasonable parallelism between CPU and GPU but also |
3847 | * relatively low latency when blocking on a particular request to finish. | |
3848 | */ | |
40a5f0de | 3849 | static int |
f787a5f5 | 3850 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3851 | { |
f787a5f5 CW |
3852 | struct drm_i915_private *dev_priv = dev->dev_private; |
3853 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3854 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3855 | struct drm_i915_gem_request *request; |
3856 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3857 | unsigned reset_counter; |
f787a5f5 CW |
3858 | u32 seqno = 0; |
3859 | int ret; | |
93533c29 | 3860 | |
308887aa DV |
3861 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3862 | if (ret) | |
3863 | return ret; | |
3864 | ||
3865 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3866 | if (ret) | |
3867 | return ret; | |
e110e8d6 | 3868 | |
1c25595f | 3869 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3870 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3871 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3872 | break; | |
40a5f0de | 3873 | |
f787a5f5 CW |
3874 | ring = request->ring; |
3875 | seqno = request->seqno; | |
b962442e | 3876 | } |
f69061be | 3877 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3878 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3879 | |
f787a5f5 CW |
3880 | if (seqno == 0) |
3881 | return 0; | |
2bc43b5c | 3882 | |
b29c19b6 | 3883 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
3884 | if (ret == 0) |
3885 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3886 | |
3887 | return ret; | |
3888 | } | |
3889 | ||
673a394b | 3890 | int |
05394f39 | 3891 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3892 | struct i915_address_space *vm, |
05394f39 | 3893 | uint32_t alignment, |
86a1ee26 CW |
3894 | bool map_and_fenceable, |
3895 | bool nonblocking) | |
673a394b | 3896 | { |
07fe0b12 | 3897 | struct i915_vma *vma; |
673a394b EA |
3898 | int ret; |
3899 | ||
7e81a42e CW |
3900 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3901 | return -EBUSY; | |
ac0c6b5a | 3902 | |
07fe0b12 BW |
3903 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
3904 | ||
3905 | vma = i915_gem_obj_to_vma(obj, vm); | |
3906 | ||
3907 | if (vma) { | |
3908 | if ((alignment && | |
3909 | vma->node.start & (alignment - 1)) || | |
05394f39 CW |
3910 | (map_and_fenceable && !obj->map_and_fenceable)) { |
3911 | WARN(obj->pin_count, | |
ae7d49d8 | 3912 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3913 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3914 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3915 | i915_gem_obj_offset(obj, vm), alignment, |
75e9e915 | 3916 | map_and_fenceable, |
05394f39 | 3917 | obj->map_and_fenceable); |
07fe0b12 | 3918 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3919 | if (ret) |
3920 | return ret; | |
3921 | } | |
3922 | } | |
3923 | ||
07fe0b12 | 3924 | if (!i915_gem_obj_bound(obj, vm)) { |
8742267a CW |
3925 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3926 | ||
07fe0b12 BW |
3927 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
3928 | map_and_fenceable, | |
3929 | nonblocking); | |
9731129c | 3930 | if (ret) |
673a394b | 3931 | return ret; |
8742267a CW |
3932 | |
3933 | if (!dev_priv->mm.aliasing_ppgtt) | |
3934 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3935 | } |
76446cac | 3936 | |
74898d7e DV |
3937 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3938 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3939 | ||
1b50247a | 3940 | obj->pin_count++; |
6299f992 | 3941 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3942 | |
3943 | return 0; | |
3944 | } | |
3945 | ||
3946 | void | |
05394f39 | 3947 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3948 | { |
05394f39 | 3949 | BUG_ON(obj->pin_count == 0); |
9843877d | 3950 | BUG_ON(!i915_gem_obj_bound_any(obj)); |
673a394b | 3951 | |
1b50247a | 3952 | if (--obj->pin_count == 0) |
6299f992 | 3953 | obj->pin_mappable = false; |
673a394b EA |
3954 | } |
3955 | ||
3956 | int | |
3957 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3958 | struct drm_file *file) |
673a394b EA |
3959 | { |
3960 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3961 | struct drm_i915_gem_object *obj; |
673a394b EA |
3962 | int ret; |
3963 | ||
1d7cfea1 CW |
3964 | ret = i915_mutex_lock_interruptible(dev); |
3965 | if (ret) | |
3966 | return ret; | |
673a394b | 3967 | |
05394f39 | 3968 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3969 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3970 | ret = -ENOENT; |
3971 | goto unlock; | |
673a394b | 3972 | } |
673a394b | 3973 | |
05394f39 | 3974 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3975 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3976 | ret = -EINVAL; |
3977 | goto out; | |
3ef94daa CW |
3978 | } |
3979 | ||
05394f39 | 3980 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3981 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3982 | args->handle); | |
1d7cfea1 CW |
3983 | ret = -EINVAL; |
3984 | goto out; | |
79e53945 JB |
3985 | } |
3986 | ||
aa5f8021 DV |
3987 | if (obj->user_pin_count == ULONG_MAX) { |
3988 | ret = -EBUSY; | |
3989 | goto out; | |
3990 | } | |
3991 | ||
93be8788 | 3992 | if (obj->user_pin_count == 0) { |
c37e2204 | 3993 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3994 | if (ret) |
3995 | goto out; | |
673a394b EA |
3996 | } |
3997 | ||
93be8788 CW |
3998 | obj->user_pin_count++; |
3999 | obj->pin_filp = file; | |
4000 | ||
f343c5f6 | 4001 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 4002 | out: |
05394f39 | 4003 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4004 | unlock: |
673a394b | 4005 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4006 | return ret; |
673a394b EA |
4007 | } |
4008 | ||
4009 | int | |
4010 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4011 | struct drm_file *file) |
673a394b EA |
4012 | { |
4013 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4014 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4015 | int ret; |
673a394b | 4016 | |
1d7cfea1 CW |
4017 | ret = i915_mutex_lock_interruptible(dev); |
4018 | if (ret) | |
4019 | return ret; | |
673a394b | 4020 | |
05394f39 | 4021 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4022 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4023 | ret = -ENOENT; |
4024 | goto unlock; | |
673a394b | 4025 | } |
76c1dec1 | 4026 | |
05394f39 | 4027 | if (obj->pin_filp != file) { |
79e53945 JB |
4028 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
4029 | args->handle); | |
1d7cfea1 CW |
4030 | ret = -EINVAL; |
4031 | goto out; | |
79e53945 | 4032 | } |
05394f39 CW |
4033 | obj->user_pin_count--; |
4034 | if (obj->user_pin_count == 0) { | |
4035 | obj->pin_filp = NULL; | |
79e53945 JB |
4036 | i915_gem_object_unpin(obj); |
4037 | } | |
673a394b | 4038 | |
1d7cfea1 | 4039 | out: |
05394f39 | 4040 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4041 | unlock: |
673a394b | 4042 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4043 | return ret; |
673a394b EA |
4044 | } |
4045 | ||
4046 | int | |
4047 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4048 | struct drm_file *file) |
673a394b EA |
4049 | { |
4050 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4051 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4052 | int ret; |
4053 | ||
76c1dec1 | 4054 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4055 | if (ret) |
76c1dec1 | 4056 | return ret; |
673a394b | 4057 | |
05394f39 | 4058 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4059 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4060 | ret = -ENOENT; |
4061 | goto unlock; | |
673a394b | 4062 | } |
d1b851fc | 4063 | |
0be555b6 CW |
4064 | /* Count all active objects as busy, even if they are currently not used |
4065 | * by the gpu. Users of this interface expect objects to eventually | |
4066 | * become non-busy without any further actions, therefore emit any | |
4067 | * necessary flushes here. | |
c4de0a5d | 4068 | */ |
30dfebf3 | 4069 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4070 | |
30dfebf3 | 4071 | args->busy = obj->active; |
e9808edd CW |
4072 | if (obj->ring) { |
4073 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4074 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4075 | } | |
673a394b | 4076 | |
05394f39 | 4077 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4078 | unlock: |
673a394b | 4079 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4080 | return ret; |
673a394b EA |
4081 | } |
4082 | ||
4083 | int | |
4084 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4085 | struct drm_file *file_priv) | |
4086 | { | |
0206e353 | 4087 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4088 | } |
4089 | ||
3ef94daa CW |
4090 | int |
4091 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4092 | struct drm_file *file_priv) | |
4093 | { | |
4094 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4095 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4096 | int ret; |
3ef94daa CW |
4097 | |
4098 | switch (args->madv) { | |
4099 | case I915_MADV_DONTNEED: | |
4100 | case I915_MADV_WILLNEED: | |
4101 | break; | |
4102 | default: | |
4103 | return -EINVAL; | |
4104 | } | |
4105 | ||
1d7cfea1 CW |
4106 | ret = i915_mutex_lock_interruptible(dev); |
4107 | if (ret) | |
4108 | return ret; | |
4109 | ||
05394f39 | 4110 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4111 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4112 | ret = -ENOENT; |
4113 | goto unlock; | |
3ef94daa | 4114 | } |
3ef94daa | 4115 | |
05394f39 | 4116 | if (obj->pin_count) { |
1d7cfea1 CW |
4117 | ret = -EINVAL; |
4118 | goto out; | |
3ef94daa CW |
4119 | } |
4120 | ||
05394f39 CW |
4121 | if (obj->madv != __I915_MADV_PURGED) |
4122 | obj->madv = args->madv; | |
3ef94daa | 4123 | |
6c085a72 CW |
4124 | /* if the object is no longer attached, discard its backing storage */ |
4125 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4126 | i915_gem_object_truncate(obj); |
4127 | ||
05394f39 | 4128 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4129 | |
1d7cfea1 | 4130 | out: |
05394f39 | 4131 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4132 | unlock: |
3ef94daa | 4133 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4134 | return ret; |
3ef94daa CW |
4135 | } |
4136 | ||
37e680a1 CW |
4137 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4138 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4139 | { |
35c20a60 | 4140 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4141 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4142 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4143 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4144 | |
37e680a1 CW |
4145 | obj->ops = ops; |
4146 | ||
0327d6ba CW |
4147 | obj->fence_reg = I915_FENCE_REG_NONE; |
4148 | obj->madv = I915_MADV_WILLNEED; | |
4149 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4150 | obj->map_and_fenceable = true; | |
4151 | ||
4152 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4153 | } | |
4154 | ||
37e680a1 CW |
4155 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4156 | .get_pages = i915_gem_object_get_pages_gtt, | |
4157 | .put_pages = i915_gem_object_put_pages_gtt, | |
4158 | }; | |
4159 | ||
05394f39 CW |
4160 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4161 | size_t size) | |
ac52bc56 | 4162 | { |
c397b908 | 4163 | struct drm_i915_gem_object *obj; |
5949eac4 | 4164 | struct address_space *mapping; |
1a240d4d | 4165 | gfp_t mask; |
ac52bc56 | 4166 | |
42dcedd4 | 4167 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4168 | if (obj == NULL) |
4169 | return NULL; | |
673a394b | 4170 | |
c397b908 | 4171 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4172 | i915_gem_object_free(obj); |
c397b908 DV |
4173 | return NULL; |
4174 | } | |
673a394b | 4175 | |
bed1ea95 CW |
4176 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4177 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4178 | /* 965gm cannot relocate objects above 4GiB. */ | |
4179 | mask &= ~__GFP_HIGHMEM; | |
4180 | mask |= __GFP_DMA32; | |
4181 | } | |
4182 | ||
496ad9aa | 4183 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4184 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4185 | |
37e680a1 | 4186 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4187 | |
c397b908 DV |
4188 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4189 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4190 | |
3d29b842 ED |
4191 | if (HAS_LLC(dev)) { |
4192 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4193 | * cache) for about a 10% performance improvement |
4194 | * compared to uncached. Graphics requests other than | |
4195 | * display scanout are coherent with the CPU in | |
4196 | * accessing this cache. This means in this mode we | |
4197 | * don't need to clflush on the CPU side, and on the | |
4198 | * GPU side we only need to flush internal caches to | |
4199 | * get data visible to the CPU. | |
4200 | * | |
4201 | * However, we maintain the display planes as UC, and so | |
4202 | * need to rebind when first used as such. | |
4203 | */ | |
4204 | obj->cache_level = I915_CACHE_LLC; | |
4205 | } else | |
4206 | obj->cache_level = I915_CACHE_NONE; | |
4207 | ||
d861e338 DV |
4208 | trace_i915_gem_object_create(obj); |
4209 | ||
05394f39 | 4210 | return obj; |
c397b908 DV |
4211 | } |
4212 | ||
1488fc08 | 4213 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4214 | { |
1488fc08 | 4215 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4216 | struct drm_device *dev = obj->base.dev; |
be72615b | 4217 | drm_i915_private_t *dev_priv = dev->dev_private; |
07fe0b12 | 4218 | struct i915_vma *vma, *next; |
673a394b | 4219 | |
f65c9168 PZ |
4220 | intel_runtime_pm_get(dev_priv); |
4221 | ||
26e12f89 CW |
4222 | trace_i915_gem_object_destroy(obj); |
4223 | ||
1488fc08 CW |
4224 | if (obj->phys_obj) |
4225 | i915_gem_detach_phys_object(dev, obj); | |
4226 | ||
4227 | obj->pin_count = 0; | |
07fe0b12 BW |
4228 | /* NB: 0 or 1 elements */ |
4229 | WARN_ON(!list_empty(&obj->vma_list) && | |
4230 | !list_is_singular(&obj->vma_list)); | |
4231 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { | |
4232 | int ret = i915_vma_unbind(vma); | |
4233 | if (WARN_ON(ret == -ERESTARTSYS)) { | |
4234 | bool was_interruptible; | |
1488fc08 | 4235 | |
07fe0b12 BW |
4236 | was_interruptible = dev_priv->mm.interruptible; |
4237 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4238 | |
07fe0b12 | 4239 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4240 | |
07fe0b12 BW |
4241 | dev_priv->mm.interruptible = was_interruptible; |
4242 | } | |
1488fc08 CW |
4243 | } |
4244 | ||
1d64ae71 BW |
4245 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4246 | * before progressing. */ | |
4247 | if (obj->stolen) | |
4248 | i915_gem_object_unpin_pages(obj); | |
4249 | ||
401c29f6 BW |
4250 | if (WARN_ON(obj->pages_pin_count)) |
4251 | obj->pages_pin_count = 0; | |
37e680a1 | 4252 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4253 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4254 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4255 | |
9da3da66 CW |
4256 | BUG_ON(obj->pages); |
4257 | ||
2f745ad3 CW |
4258 | if (obj->base.import_attach) |
4259 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4260 | |
05394f39 CW |
4261 | drm_gem_object_release(&obj->base); |
4262 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4263 | |
05394f39 | 4264 | kfree(obj->bit_17); |
42dcedd4 | 4265 | i915_gem_object_free(obj); |
f65c9168 PZ |
4266 | |
4267 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4268 | } |
4269 | ||
e656a6cb | 4270 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4271 | struct i915_address_space *vm) |
e656a6cb DV |
4272 | { |
4273 | struct i915_vma *vma; | |
4274 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4275 | if (vma->vm == vm) | |
4276 | return vma; | |
4277 | ||
4278 | return NULL; | |
4279 | } | |
4280 | ||
4281 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
4282 | struct i915_address_space *vm) | |
2f633156 BW |
4283 | { |
4284 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
4285 | if (vma == NULL) | |
4286 | return ERR_PTR(-ENOMEM); | |
4287 | ||
4288 | INIT_LIST_HEAD(&vma->vma_link); | |
ca191b13 | 4289 | INIT_LIST_HEAD(&vma->mm_list); |
82a55ad1 | 4290 | INIT_LIST_HEAD(&vma->exec_list); |
2f633156 BW |
4291 | vma->vm = vm; |
4292 | vma->obj = obj; | |
4293 | ||
8b9c2b94 BW |
4294 | /* Keep GGTT vmas first to make debug easier */ |
4295 | if (i915_is_ggtt(vm)) | |
4296 | list_add(&vma->vma_link, &obj->vma_list); | |
4297 | else | |
4298 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
4299 | ||
2f633156 BW |
4300 | return vma; |
4301 | } | |
4302 | ||
e656a6cb DV |
4303 | struct i915_vma * |
4304 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
4305 | struct i915_address_space *vm) | |
4306 | { | |
4307 | struct i915_vma *vma; | |
4308 | ||
4309 | vma = i915_gem_obj_to_vma(obj, vm); | |
4310 | if (!vma) | |
4311 | vma = __i915_gem_vma_create(obj, vm); | |
4312 | ||
4313 | return vma; | |
4314 | } | |
4315 | ||
2f633156 BW |
4316 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4317 | { | |
4318 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4319 | |
4320 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4321 | if (!list_empty(&vma->exec_list)) | |
4322 | return; | |
4323 | ||
8b9c2b94 | 4324 | list_del(&vma->vma_link); |
b93dab6e | 4325 | |
2f633156 BW |
4326 | kfree(vma); |
4327 | } | |
4328 | ||
29105ccc | 4329 | int |
45c5f202 | 4330 | i915_gem_suspend(struct drm_device *dev) |
29105ccc CW |
4331 | { |
4332 | drm_i915_private_t *dev_priv = dev->dev_private; | |
45c5f202 | 4333 | int ret = 0; |
28dfe52a | 4334 | |
45c5f202 | 4335 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4336 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4337 | goto err; |
28dfe52a | 4338 | |
b2da9fe5 | 4339 | ret = i915_gpu_idle(dev); |
f7403347 | 4340 | if (ret) |
45c5f202 | 4341 | goto err; |
f7403347 | 4342 | |
b2da9fe5 | 4343 | i915_gem_retire_requests(dev); |
673a394b | 4344 | |
29105ccc | 4345 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4346 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4347 | i915_gem_evict_everything(dev); |
29105ccc | 4348 | |
29105ccc | 4349 | i915_kernel_lost_context(dev); |
6dbe2772 | 4350 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4351 | |
45c5f202 CW |
4352 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4353 | * We need to replace this with a semaphore, or something. | |
4354 | * And not confound ums.mm_suspended! | |
4355 | */ | |
4356 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4357 | DRIVER_MODESET); | |
4358 | mutex_unlock(&dev->struct_mutex); | |
4359 | ||
4360 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4361 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
b29c19b6 | 4362 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4363 | |
673a394b | 4364 | return 0; |
45c5f202 CW |
4365 | |
4366 | err: | |
4367 | mutex_unlock(&dev->struct_mutex); | |
4368 | return ret; | |
673a394b EA |
4369 | } |
4370 | ||
c3787e2e | 4371 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice) |
b9524a1e | 4372 | { |
c3787e2e | 4373 | struct drm_device *dev = ring->dev; |
b9524a1e | 4374 | drm_i915_private_t *dev_priv = dev->dev_private; |
35a85ac6 BW |
4375 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4376 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4377 | int i, ret; |
b9524a1e | 4378 | |
040d2baa | 4379 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4380 | return 0; |
b9524a1e | 4381 | |
c3787e2e BW |
4382 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4383 | if (ret) | |
4384 | return ret; | |
b9524a1e | 4385 | |
c3787e2e BW |
4386 | /* |
4387 | * Note: We do not worry about the concurrent register cacheline hang | |
4388 | * here because no other code should access these registers other than | |
4389 | * at initialization time. | |
4390 | */ | |
b9524a1e | 4391 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4392 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4393 | intel_ring_emit(ring, reg_base + i); | |
4394 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4395 | } |
4396 | ||
c3787e2e | 4397 | intel_ring_advance(ring); |
b9524a1e | 4398 | |
c3787e2e | 4399 | return ret; |
b9524a1e BW |
4400 | } |
4401 | ||
f691e2f4 DV |
4402 | void i915_gem_init_swizzling(struct drm_device *dev) |
4403 | { | |
4404 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4405 | ||
11782b02 | 4406 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4407 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4408 | return; | |
4409 | ||
4410 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4411 | DISP_TILE_SURFACE_SWIZZLING); | |
4412 | ||
11782b02 DV |
4413 | if (IS_GEN5(dev)) |
4414 | return; | |
4415 | ||
f691e2f4 DV |
4416 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4417 | if (IS_GEN6(dev)) | |
6b26c86d | 4418 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4419 | else if (IS_GEN7(dev)) |
6b26c86d | 4420 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4421 | else if (IS_GEN8(dev)) |
4422 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4423 | else |
4424 | BUG(); | |
f691e2f4 | 4425 | } |
e21af88d | 4426 | |
67b1b571 CW |
4427 | static bool |
4428 | intel_enable_blt(struct drm_device *dev) | |
4429 | { | |
4430 | if (!HAS_BLT(dev)) | |
4431 | return false; | |
4432 | ||
4433 | /* The blitter was dysfunctional on early prototypes */ | |
4434 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4435 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4436 | " graphics performance will be degraded.\n"); | |
4437 | return false; | |
4438 | } | |
4439 | ||
4440 | return true; | |
4441 | } | |
4442 | ||
4fc7c971 | 4443 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4444 | { |
4fc7c971 | 4445 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4446 | int ret; |
68f95ba9 | 4447 | |
5c1143bb | 4448 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4449 | if (ret) |
b6913e4b | 4450 | return ret; |
68f95ba9 CW |
4451 | |
4452 | if (HAS_BSD(dev)) { | |
5c1143bb | 4453 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4454 | if (ret) |
4455 | goto cleanup_render_ring; | |
d1b851fc | 4456 | } |
68f95ba9 | 4457 | |
67b1b571 | 4458 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4459 | ret = intel_init_blt_ring_buffer(dev); |
4460 | if (ret) | |
4461 | goto cleanup_bsd_ring; | |
4462 | } | |
4463 | ||
9a8a2213 BW |
4464 | if (HAS_VEBOX(dev)) { |
4465 | ret = intel_init_vebox_ring_buffer(dev); | |
4466 | if (ret) | |
4467 | goto cleanup_blt_ring; | |
4468 | } | |
4469 | ||
4470 | ||
99433931 | 4471 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4472 | if (ret) |
9a8a2213 | 4473 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4474 | |
4475 | return 0; | |
4476 | ||
9a8a2213 BW |
4477 | cleanup_vebox_ring: |
4478 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4479 | cleanup_blt_ring: |
4480 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4481 | cleanup_bsd_ring: | |
4482 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4483 | cleanup_render_ring: | |
4484 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4485 | ||
4486 | return ret; | |
4487 | } | |
4488 | ||
4489 | int | |
4490 | i915_gem_init_hw(struct drm_device *dev) | |
4491 | { | |
4492 | drm_i915_private_t *dev_priv = dev->dev_private; | |
35a85ac6 | 4493 | int ret, i; |
4fc7c971 BW |
4494 | |
4495 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4496 | return -EIO; | |
4497 | ||
59124506 | 4498 | if (dev_priv->ellc_size) |
05e21cc4 | 4499 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4500 | |
0bf21347 VS |
4501 | if (IS_HASWELL(dev)) |
4502 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4503 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4504 | |
88a2b2a3 BW |
4505 | if (HAS_PCH_NOP(dev)) { |
4506 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4507 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4508 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4509 | } | |
4510 | ||
4fc7c971 BW |
4511 | i915_gem_init_swizzling(dev); |
4512 | ||
4513 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4514 | if (ret) |
4515 | return ret; | |
4516 | ||
c3787e2e BW |
4517 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4518 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4519 | ||
254f965c BW |
4520 | /* |
4521 | * XXX: There was some w/a described somewhere suggesting loading | |
4522 | * contexts before PPGTT. | |
4523 | */ | |
8245be31 BW |
4524 | ret = i915_gem_context_init(dev); |
4525 | if (ret) { | |
4526 | i915_gem_cleanup_ringbuffer(dev); | |
4527 | DRM_ERROR("Context initialization failed %d\n", ret); | |
4528 | return ret; | |
4529 | } | |
4530 | ||
b7c36d25 BW |
4531 | if (dev_priv->mm.aliasing_ppgtt) { |
4532 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4533 | if (ret) { | |
4534 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4535 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4536 | } | |
4537 | } | |
e21af88d | 4538 | |
68f95ba9 | 4539 | return 0; |
8187a2b7 ZN |
4540 | } |
4541 | ||
1070a42b CW |
4542 | int i915_gem_init(struct drm_device *dev) |
4543 | { | |
4544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4545 | int ret; |
4546 | ||
1070a42b | 4547 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4548 | |
4549 | if (IS_VALLEYVIEW(dev)) { | |
4550 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4551 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4552 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4553 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4554 | } | |
4555 | ||
d7e5008f | 4556 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4557 | |
1070a42b CW |
4558 | ret = i915_gem_init_hw(dev); |
4559 | mutex_unlock(&dev->struct_mutex); | |
4560 | if (ret) { | |
4561 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4562 | return ret; | |
4563 | } | |
4564 | ||
53ca26ca DV |
4565 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4566 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4567 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4568 | return 0; |
4569 | } | |
4570 | ||
8187a2b7 ZN |
4571 | void |
4572 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4573 | { | |
4574 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4575 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4576 | int i; |
8187a2b7 | 4577 | |
b4519513 CW |
4578 | for_each_ring(ring, dev_priv, i) |
4579 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4580 | } |
4581 | ||
673a394b EA |
4582 | int |
4583 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4584 | struct drm_file *file_priv) | |
4585 | { | |
db1b76ca | 4586 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4587 | int ret; |
673a394b | 4588 | |
79e53945 JB |
4589 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4590 | return 0; | |
4591 | ||
1f83fee0 | 4592 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4593 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4594 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4595 | } |
4596 | ||
673a394b | 4597 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4598 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4599 | |
f691e2f4 | 4600 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4601 | if (ret != 0) { |
4602 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4603 | return ret; |
d816f6ac | 4604 | } |
9bb2d6f9 | 4605 | |
5cef07e1 | 4606 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4607 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4608 | |
5f35308b CW |
4609 | ret = drm_irq_install(dev); |
4610 | if (ret) | |
4611 | goto cleanup_ringbuffer; | |
dbb19d30 | 4612 | |
673a394b | 4613 | return 0; |
5f35308b CW |
4614 | |
4615 | cleanup_ringbuffer: | |
4616 | mutex_lock(&dev->struct_mutex); | |
4617 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4618 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4619 | mutex_unlock(&dev->struct_mutex); |
4620 | ||
4621 | return ret; | |
673a394b EA |
4622 | } |
4623 | ||
4624 | int | |
4625 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4626 | struct drm_file *file_priv) | |
4627 | { | |
79e53945 JB |
4628 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4629 | return 0; | |
4630 | ||
dbb19d30 | 4631 | drm_irq_uninstall(dev); |
db1b76ca | 4632 | |
45c5f202 | 4633 | return i915_gem_suspend(dev); |
673a394b EA |
4634 | } |
4635 | ||
4636 | void | |
4637 | i915_gem_lastclose(struct drm_device *dev) | |
4638 | { | |
4639 | int ret; | |
673a394b | 4640 | |
e806b495 EA |
4641 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4642 | return; | |
4643 | ||
45c5f202 | 4644 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4645 | if (ret) |
4646 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4647 | } |
4648 | ||
64193406 CW |
4649 | static void |
4650 | init_ring_lists(struct intel_ring_buffer *ring) | |
4651 | { | |
4652 | INIT_LIST_HEAD(&ring->active_list); | |
4653 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4654 | } |
4655 | ||
fc8c067e BW |
4656 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
4657 | struct i915_address_space *vm) | |
4658 | { | |
4659 | vm->dev = dev_priv->dev; | |
4660 | INIT_LIST_HEAD(&vm->active_list); | |
4661 | INIT_LIST_HEAD(&vm->inactive_list); | |
4662 | INIT_LIST_HEAD(&vm->global_link); | |
4663 | list_add(&vm->global_link, &dev_priv->vm_list); | |
4664 | } | |
4665 | ||
673a394b EA |
4666 | void |
4667 | i915_gem_load(struct drm_device *dev) | |
4668 | { | |
4669 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4670 | int i; |
4671 | ||
4672 | dev_priv->slab = | |
4673 | kmem_cache_create("i915_gem_object", | |
4674 | sizeof(struct drm_i915_gem_object), 0, | |
4675 | SLAB_HWCACHE_ALIGN, | |
4676 | NULL); | |
673a394b | 4677 | |
fc8c067e BW |
4678 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4679 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4680 | ||
a33afea5 | 4681 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4682 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4683 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4684 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4685 | for (i = 0; i < I915_NUM_RINGS; i++) |
4686 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4687 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4688 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4689 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4690 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4691 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4692 | i915_gem_idle_work_handler); | |
1f83fee0 | 4693 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4694 | |
94400120 DA |
4695 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4696 | if (IS_GEN3(dev)) { | |
50743298 DV |
4697 | I915_WRITE(MI_ARB_STATE, |
4698 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4699 | } |
4700 | ||
72bfa19c CW |
4701 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4702 | ||
de151cf6 | 4703 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4704 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4705 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4706 | |
42b5aeab VS |
4707 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4708 | dev_priv->num_fence_regs = 32; | |
4709 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4710 | dev_priv->num_fence_regs = 16; |
4711 | else | |
4712 | dev_priv->num_fence_regs = 8; | |
4713 | ||
b5aa8a0f | 4714 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4715 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4716 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4717 | |
673a394b | 4718 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4719 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4720 | |
ce453d81 CW |
4721 | dev_priv->mm.interruptible = true; |
4722 | ||
7dc19d5a DC |
4723 | dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan; |
4724 | dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count; | |
17250b71 CW |
4725 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
4726 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4727 | } |
71acb5eb DA |
4728 | |
4729 | /* | |
4730 | * Create a physically contiguous memory object for this object | |
4731 | * e.g. for cursor + overlay regs | |
4732 | */ | |
995b6762 CW |
4733 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4734 | int id, int size, int align) | |
71acb5eb DA |
4735 | { |
4736 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4737 | struct drm_i915_gem_phys_object *phys_obj; | |
4738 | int ret; | |
4739 | ||
4740 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4741 | return 0; | |
4742 | ||
b14c5679 | 4743 | phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL); |
71acb5eb DA |
4744 | if (!phys_obj) |
4745 | return -ENOMEM; | |
4746 | ||
4747 | phys_obj->id = id; | |
4748 | ||
6eeefaf3 | 4749 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4750 | if (!phys_obj->handle) { |
4751 | ret = -ENOMEM; | |
4752 | goto kfree_obj; | |
4753 | } | |
4754 | #ifdef CONFIG_X86 | |
4755 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4756 | #endif | |
4757 | ||
4758 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4759 | ||
4760 | return 0; | |
4761 | kfree_obj: | |
9a298b2a | 4762 | kfree(phys_obj); |
71acb5eb DA |
4763 | return ret; |
4764 | } | |
4765 | ||
995b6762 | 4766 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4767 | { |
4768 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4769 | struct drm_i915_gem_phys_object *phys_obj; | |
4770 | ||
4771 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4772 | return; | |
4773 | ||
4774 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4775 | if (phys_obj->cur_obj) { | |
4776 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4777 | } | |
4778 | ||
4779 | #ifdef CONFIG_X86 | |
4780 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4781 | #endif | |
4782 | drm_pci_free(dev, phys_obj->handle); | |
4783 | kfree(phys_obj); | |
4784 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4785 | } | |
4786 | ||
4787 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4788 | { | |
4789 | int i; | |
4790 | ||
260883c8 | 4791 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4792 | i915_gem_free_phys_object(dev, i); |
4793 | } | |
4794 | ||
4795 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4796 | struct drm_i915_gem_object *obj) |
71acb5eb | 4797 | { |
496ad9aa | 4798 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4799 | char *vaddr; |
71acb5eb | 4800 | int i; |
71acb5eb DA |
4801 | int page_count; |
4802 | ||
05394f39 | 4803 | if (!obj->phys_obj) |
71acb5eb | 4804 | return; |
05394f39 | 4805 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4806 | |
05394f39 | 4807 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4808 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4809 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4810 | if (!IS_ERR(page)) { |
4811 | char *dst = kmap_atomic(page); | |
4812 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4813 | kunmap_atomic(dst); | |
4814 | ||
4815 | drm_clflush_pages(&page, 1); | |
4816 | ||
4817 | set_page_dirty(page); | |
4818 | mark_page_accessed(page); | |
4819 | page_cache_release(page); | |
4820 | } | |
71acb5eb | 4821 | } |
e76e9aeb | 4822 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4823 | |
05394f39 CW |
4824 | obj->phys_obj->cur_obj = NULL; |
4825 | obj->phys_obj = NULL; | |
71acb5eb DA |
4826 | } |
4827 | ||
4828 | int | |
4829 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4830 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4831 | int id, |
4832 | int align) | |
71acb5eb | 4833 | { |
496ad9aa | 4834 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4835 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4836 | int ret = 0; |
4837 | int page_count; | |
4838 | int i; | |
4839 | ||
4840 | if (id > I915_MAX_PHYS_OBJECT) | |
4841 | return -EINVAL; | |
4842 | ||
05394f39 CW |
4843 | if (obj->phys_obj) { |
4844 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4845 | return 0; |
4846 | i915_gem_detach_phys_object(dev, obj); | |
4847 | } | |
4848 | ||
71acb5eb DA |
4849 | /* create a new object */ |
4850 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4851 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4852 | obj->base.size, align); |
71acb5eb | 4853 | if (ret) { |
05394f39 CW |
4854 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4855 | id, obj->base.size); | |
e5281ccd | 4856 | return ret; |
71acb5eb DA |
4857 | } |
4858 | } | |
4859 | ||
4860 | /* bind to the object */ | |
05394f39 CW |
4861 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4862 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4863 | |
05394f39 | 4864 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4865 | |
4866 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4867 | struct page *page; |
4868 | char *dst, *src; | |
4869 | ||
5949eac4 | 4870 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4871 | if (IS_ERR(page)) |
4872 | return PTR_ERR(page); | |
71acb5eb | 4873 | |
ff75b9bc | 4874 | src = kmap_atomic(page); |
05394f39 | 4875 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4876 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4877 | kunmap_atomic(src); |
71acb5eb | 4878 | |
e5281ccd CW |
4879 | mark_page_accessed(page); |
4880 | page_cache_release(page); | |
4881 | } | |
d78b47b9 | 4882 | |
71acb5eb | 4883 | return 0; |
71acb5eb DA |
4884 | } |
4885 | ||
4886 | static int | |
05394f39 CW |
4887 | i915_gem_phys_pwrite(struct drm_device *dev, |
4888 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4889 | struct drm_i915_gem_pwrite *args, |
4890 | struct drm_file *file_priv) | |
4891 | { | |
05394f39 | 4892 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4893 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4894 | |
b47b30cc CW |
4895 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4896 | unsigned long unwritten; | |
4897 | ||
4898 | /* The physical object once assigned is fixed for the lifetime | |
4899 | * of the obj, so we can safely drop the lock and continue | |
4900 | * to access vaddr. | |
4901 | */ | |
4902 | mutex_unlock(&dev->struct_mutex); | |
4903 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4904 | mutex_lock(&dev->struct_mutex); | |
4905 | if (unwritten) | |
4906 | return -EFAULT; | |
4907 | } | |
71acb5eb | 4908 | |
e76e9aeb | 4909 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4910 | return 0; |
4911 | } | |
b962442e | 4912 | |
f787a5f5 | 4913 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4914 | { |
f787a5f5 | 4915 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4916 | |
b29c19b6 CW |
4917 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4918 | ||
b962442e EA |
4919 | /* Clean up our request list when the client is going away, so that |
4920 | * later retire_requests won't dereference our soon-to-be-gone | |
4921 | * file_priv. | |
4922 | */ | |
1c25595f | 4923 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4924 | while (!list_empty(&file_priv->mm.request_list)) { |
4925 | struct drm_i915_gem_request *request; | |
4926 | ||
4927 | request = list_first_entry(&file_priv->mm.request_list, | |
4928 | struct drm_i915_gem_request, | |
4929 | client_list); | |
4930 | list_del(&request->client_list); | |
4931 | request->file_priv = NULL; | |
4932 | } | |
1c25595f | 4933 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4934 | } |
31169714 | 4935 | |
b29c19b6 CW |
4936 | static void |
4937 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
4938 | { | |
4939 | struct drm_i915_file_private *file_priv = | |
4940 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
4941 | ||
4942 | atomic_set(&file_priv->rps_wait_boost, false); | |
4943 | } | |
4944 | ||
4945 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4946 | { | |
4947 | struct drm_i915_file_private *file_priv; | |
4948 | ||
4949 | DRM_DEBUG_DRIVER("\n"); | |
4950 | ||
4951 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4952 | if (!file_priv) | |
4953 | return -ENOMEM; | |
4954 | ||
4955 | file->driver_priv = file_priv; | |
4956 | file_priv->dev_priv = dev->dev_private; | |
4957 | ||
4958 | spin_lock_init(&file_priv->mm.lock); | |
4959 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4960 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
4961 | i915_gem_file_idle_work_handler); | |
4962 | ||
4963 | idr_init(&file_priv->context_idr); | |
4964 | ||
4965 | return 0; | |
4966 | } | |
4967 | ||
5774506f CW |
4968 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4969 | { | |
4970 | if (!mutex_is_locked(mutex)) | |
4971 | return false; | |
4972 | ||
4973 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4974 | return mutex->owner == task; | |
4975 | #else | |
4976 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4977 | return false; | |
4978 | #endif | |
4979 | } | |
4980 | ||
7dc19d5a DC |
4981 | static unsigned long |
4982 | i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc) | |
31169714 | 4983 | { |
17250b71 CW |
4984 | struct drm_i915_private *dev_priv = |
4985 | container_of(shrinker, | |
4986 | struct drm_i915_private, | |
4987 | mm.inactive_shrinker); | |
4988 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4989 | struct drm_i915_gem_object *obj; |
5774506f | 4990 | bool unlock = true; |
7dc19d5a | 4991 | unsigned long count; |
17250b71 | 4992 | |
5774506f CW |
4993 | if (!mutex_trylock(&dev->struct_mutex)) { |
4994 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 4995 | return 0; |
5774506f | 4996 | |
677feac2 | 4997 | if (dev_priv->mm.shrinker_no_lock_stealing) |
d3227046 | 4998 | return 0; |
677feac2 | 4999 | |
5774506f CW |
5000 | unlock = false; |
5001 | } | |
31169714 | 5002 | |
7dc19d5a | 5003 | count = 0; |
35c20a60 | 5004 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5005 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5006 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5007 | |
5008 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5009 | if (obj->active) | |
5010 | continue; | |
5011 | ||
a5570178 | 5012 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
7dc19d5a | 5013 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5014 | } |
17250b71 | 5015 | |
5774506f CW |
5016 | if (unlock) |
5017 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5018 | |
7dc19d5a | 5019 | return count; |
31169714 | 5020 | } |
a70a3148 BW |
5021 | |
5022 | /* All the new VM stuff */ | |
5023 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5024 | struct i915_address_space *vm) | |
5025 | { | |
5026 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5027 | struct i915_vma *vma; | |
5028 | ||
5029 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
5030 | vm = &dev_priv->gtt.base; | |
5031 | ||
5032 | BUG_ON(list_empty(&o->vma_list)); | |
5033 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
5034 | if (vma->vm == vm) | |
5035 | return vma->node.start; | |
5036 | ||
5037 | } | |
5038 | return -1; | |
5039 | } | |
5040 | ||
5041 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5042 | struct i915_address_space *vm) | |
5043 | { | |
5044 | struct i915_vma *vma; | |
5045 | ||
5046 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5047 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5048 | return true; |
5049 | ||
5050 | return false; | |
5051 | } | |
5052 | ||
5053 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5054 | { | |
5a1d5eb0 | 5055 | struct i915_vma *vma; |
a70a3148 | 5056 | |
5a1d5eb0 CW |
5057 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5058 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5059 | return true; |
5060 | ||
5061 | return false; | |
5062 | } | |
5063 | ||
5064 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5065 | struct i915_address_space *vm) | |
5066 | { | |
5067 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5068 | struct i915_vma *vma; | |
5069 | ||
5070 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
5071 | vm = &dev_priv->gtt.base; | |
5072 | ||
5073 | BUG_ON(list_empty(&o->vma_list)); | |
5074 | ||
5075 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5076 | if (vma->vm == vm) | |
5077 | return vma->node.size; | |
5078 | ||
5079 | return 0; | |
5080 | } | |
5081 | ||
7dc19d5a DC |
5082 | static unsigned long |
5083 | i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc) | |
5084 | { | |
5085 | struct drm_i915_private *dev_priv = | |
5086 | container_of(shrinker, | |
5087 | struct drm_i915_private, | |
5088 | mm.inactive_shrinker); | |
5089 | struct drm_device *dev = dev_priv->dev; | |
7dc19d5a DC |
5090 | unsigned long freed; |
5091 | bool unlock = true; | |
5092 | ||
5093 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5094 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 5095 | return SHRINK_STOP; |
7dc19d5a DC |
5096 | |
5097 | if (dev_priv->mm.shrinker_no_lock_stealing) | |
d3227046 | 5098 | return SHRINK_STOP; |
7dc19d5a DC |
5099 | |
5100 | unlock = false; | |
5101 | } | |
5102 | ||
d9973b43 CW |
5103 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
5104 | if (freed < sc->nr_to_scan) | |
5105 | freed += __i915_gem_shrink(dev_priv, | |
5106 | sc->nr_to_scan - freed, | |
5107 | false); | |
5108 | if (freed < sc->nr_to_scan) | |
7dc19d5a DC |
5109 | freed += i915_gem_shrink_all(dev_priv); |
5110 | ||
5111 | if (unlock) | |
5112 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5113 | |
7dc19d5a DC |
5114 | return freed; |
5115 | } | |
5c2abbea BW |
5116 | |
5117 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
5118 | { | |
5119 | struct i915_vma *vma; | |
5120 | ||
5121 | if (WARN_ON(list_empty(&obj->vma_list))) | |
5122 | return NULL; | |
5123 | ||
5124 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
5125 | if (WARN_ON(vma->vm != obj_to_ggtt(obj))) | |
5126 | return NULL; | |
5127 | ||
5128 | return vma; | |
5129 | } |