Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
2cfcd32a | 34 | #include <linux/oom.h> |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
43 | bool force); | |
07fe0b12 | 44 | static __must_check int |
23f54483 BW |
45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
46 | bool readonly); | |
c8725f3d CW |
47 | static void |
48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
49 | ||
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
ceabbba5 | 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 57 | struct shrink_control *sc); |
ceabbba5 | 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 59 | struct shrink_control *sc); |
2cfcd32a CW |
60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
61 | unsigned long event, | |
62 | void *ptr); | |
d9973b43 CW |
63 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
64 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
31169714 | 65 | |
c76ce038 CW |
66 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
67 | enum i915_cache_level level) | |
68 | { | |
69 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
70 | } | |
71 | ||
2c22569b CW |
72 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
73 | { | |
74 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
75 | return true; | |
76 | ||
77 | return obj->pin_display; | |
78 | } | |
79 | ||
61050808 CW |
80 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
81 | { | |
82 | if (obj->tiling_mode) | |
83 | i915_gem_release_mmap(obj); | |
84 | ||
85 | /* As we do not have an associated fence register, we will force | |
86 | * a tiling change if we ever need to acquire one. | |
87 | */ | |
5d82e3e6 | 88 | obj->fence_dirty = false; |
61050808 CW |
89 | obj->fence_reg = I915_FENCE_REG_NONE; |
90 | } | |
91 | ||
73aa808f CW |
92 | /* some bookkeeping */ |
93 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count++; |
98 | dev_priv->mm.object_memory += size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
102 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
103 | size_t size) | |
104 | { | |
c20e8355 | 105 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
106 | dev_priv->mm.object_count--; |
107 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 108 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
109 | } |
110 | ||
21dd3734 | 111 | static int |
33196ded | 112 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 113 | { |
30dbf0c0 CW |
114 | int ret; |
115 | ||
7abb690a DV |
116 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
117 | i915_terminally_wedged(error)) | |
1f83fee0 | 118 | if (EXIT_COND) |
30dbf0c0 CW |
119 | return 0; |
120 | ||
0a6759c6 DV |
121 | /* |
122 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
123 | * userspace. If it takes that long something really bad is going on and | |
124 | * we should simply try to bail out and fail as gracefully as possible. | |
125 | */ | |
1f83fee0 DV |
126 | ret = wait_event_interruptible_timeout(error->reset_queue, |
127 | EXIT_COND, | |
128 | 10*HZ); | |
0a6759c6 DV |
129 | if (ret == 0) { |
130 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
131 | return -EIO; | |
132 | } else if (ret < 0) { | |
30dbf0c0 | 133 | return ret; |
0a6759c6 | 134 | } |
1f83fee0 | 135 | #undef EXIT_COND |
30dbf0c0 | 136 | |
21dd3734 | 137 | return 0; |
30dbf0c0 CW |
138 | } |
139 | ||
54cf91dc | 140 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 141 | { |
33196ded | 142 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
143 | int ret; |
144 | ||
33196ded | 145 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
146 | if (ret) |
147 | return ret; | |
148 | ||
149 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
23bc5982 | 153 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
154 | return 0; |
155 | } | |
30dbf0c0 | 156 | |
7d1c4804 | 157 | static inline bool |
05394f39 | 158 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 159 | { |
9843877d | 160 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
161 | } |
162 | ||
79e53945 JB |
163 | int |
164 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 165 | struct drm_file *file) |
79e53945 | 166 | { |
93d18799 | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 168 | struct drm_i915_gem_init *args = data; |
2021746e | 169 | |
7bb6fb8d DV |
170 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
171 | return -ENODEV; | |
172 | ||
2021746e CW |
173 | if (args->gtt_start >= args->gtt_end || |
174 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
175 | return -EINVAL; | |
79e53945 | 176 | |
f534bc0b DV |
177 | /* GEM with user mode setting was never supported on ilk and later. */ |
178 | if (INTEL_INFO(dev)->gen >= 5) | |
179 | return -ENODEV; | |
180 | ||
79e53945 | 181 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
182 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
183 | args->gtt_end); | |
93d18799 | 184 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
185 | mutex_unlock(&dev->struct_mutex); |
186 | ||
2021746e | 187 | return 0; |
673a394b EA |
188 | } |
189 | ||
5a125c3c EA |
190 | int |
191 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 192 | struct drm_file *file) |
5a125c3c | 193 | { |
73aa808f | 194 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 195 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
196 | struct drm_i915_gem_object *obj; |
197 | size_t pinned; | |
5a125c3c | 198 | |
6299f992 | 199 | pinned = 0; |
73aa808f | 200 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 201 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 202 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 203 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 204 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 205 | |
853ba5d2 | 206 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 207 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 208 | |
5a125c3c EA |
209 | return 0; |
210 | } | |
211 | ||
00731155 CW |
212 | static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj) |
213 | { | |
214 | drm_dma_handle_t *phys = obj->phys_handle; | |
215 | ||
216 | if (!phys) | |
217 | return; | |
218 | ||
219 | if (obj->madv == I915_MADV_WILLNEED) { | |
220 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; | |
221 | char *vaddr = phys->vaddr; | |
222 | int i; | |
223 | ||
224 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
225 | struct page *page = shmem_read_mapping_page(mapping, i); | |
226 | if (!IS_ERR(page)) { | |
227 | char *dst = kmap_atomic(page); | |
228 | memcpy(dst, vaddr, PAGE_SIZE); | |
229 | drm_clflush_virt_range(dst, PAGE_SIZE); | |
230 | kunmap_atomic(dst); | |
231 | ||
232 | set_page_dirty(page); | |
233 | mark_page_accessed(page); | |
234 | page_cache_release(page); | |
235 | } | |
236 | vaddr += PAGE_SIZE; | |
237 | } | |
238 | i915_gem_chipset_flush(obj->base.dev); | |
239 | } | |
240 | ||
241 | #ifdef CONFIG_X86 | |
242 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); | |
243 | #endif | |
244 | drm_pci_free(obj->base.dev, phys); | |
245 | obj->phys_handle = NULL; | |
246 | } | |
247 | ||
248 | int | |
249 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
250 | int align) | |
251 | { | |
252 | drm_dma_handle_t *phys; | |
253 | struct address_space *mapping; | |
254 | char *vaddr; | |
255 | int i; | |
256 | ||
257 | if (obj->phys_handle) { | |
258 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
259 | return -EBUSY; | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | if (obj->madv != I915_MADV_WILLNEED) | |
265 | return -EFAULT; | |
266 | ||
267 | if (obj->base.filp == NULL) | |
268 | return -EINVAL; | |
269 | ||
270 | /* create a new object */ | |
271 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
272 | if (!phys) | |
273 | return -ENOMEM; | |
274 | ||
275 | vaddr = phys->vaddr; | |
276 | #ifdef CONFIG_X86 | |
277 | set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE); | |
278 | #endif | |
279 | mapping = file_inode(obj->base.filp)->i_mapping; | |
280 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
281 | struct page *page; | |
282 | char *src; | |
283 | ||
284 | page = shmem_read_mapping_page(mapping, i); | |
285 | if (IS_ERR(page)) { | |
286 | #ifdef CONFIG_X86 | |
287 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); | |
288 | #endif | |
289 | drm_pci_free(obj->base.dev, phys); | |
290 | return PTR_ERR(page); | |
291 | } | |
292 | ||
293 | src = kmap_atomic(page); | |
294 | memcpy(vaddr, src, PAGE_SIZE); | |
295 | kunmap_atomic(src); | |
296 | ||
297 | mark_page_accessed(page); | |
298 | page_cache_release(page); | |
299 | ||
300 | vaddr += PAGE_SIZE; | |
301 | } | |
302 | ||
303 | obj->phys_handle = phys; | |
304 | return 0; | |
305 | } | |
306 | ||
307 | static int | |
308 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
309 | struct drm_i915_gem_pwrite *args, | |
310 | struct drm_file *file_priv) | |
311 | { | |
312 | struct drm_device *dev = obj->base.dev; | |
313 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
314 | char __user *user_data = to_user_ptr(args->data_ptr); | |
315 | ||
316 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
317 | unsigned long unwritten; | |
318 | ||
319 | /* The physical object once assigned is fixed for the lifetime | |
320 | * of the obj, so we can safely drop the lock and continue | |
321 | * to access vaddr. | |
322 | */ | |
323 | mutex_unlock(&dev->struct_mutex); | |
324 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
325 | mutex_lock(&dev->struct_mutex); | |
326 | if (unwritten) | |
327 | return -EFAULT; | |
328 | } | |
329 | ||
330 | i915_gem_chipset_flush(dev); | |
331 | return 0; | |
332 | } | |
333 | ||
42dcedd4 CW |
334 | void *i915_gem_object_alloc(struct drm_device *dev) |
335 | { | |
336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 337 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
338 | } |
339 | ||
340 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
341 | { | |
342 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
343 | kmem_cache_free(dev_priv->slab, obj); | |
344 | } | |
345 | ||
ff72145b DA |
346 | static int |
347 | i915_gem_create(struct drm_file *file, | |
348 | struct drm_device *dev, | |
349 | uint64_t size, | |
350 | uint32_t *handle_p) | |
673a394b | 351 | { |
05394f39 | 352 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
353 | int ret; |
354 | u32 handle; | |
673a394b | 355 | |
ff72145b | 356 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
357 | if (size == 0) |
358 | return -EINVAL; | |
673a394b EA |
359 | |
360 | /* Allocate the new object */ | |
ff72145b | 361 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
362 | if (obj == NULL) |
363 | return -ENOMEM; | |
364 | ||
05394f39 | 365 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 366 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
367 | drm_gem_object_unreference_unlocked(&obj->base); |
368 | if (ret) | |
369 | return ret; | |
202f2fef | 370 | |
ff72145b | 371 | *handle_p = handle; |
673a394b EA |
372 | return 0; |
373 | } | |
374 | ||
ff72145b DA |
375 | int |
376 | i915_gem_dumb_create(struct drm_file *file, | |
377 | struct drm_device *dev, | |
378 | struct drm_mode_create_dumb *args) | |
379 | { | |
380 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 381 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
382 | args->size = args->pitch * args->height; |
383 | return i915_gem_create(file, dev, | |
384 | args->size, &args->handle); | |
385 | } | |
386 | ||
ff72145b DA |
387 | /** |
388 | * Creates a new mm object and returns a handle to it. | |
389 | */ | |
390 | int | |
391 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
392 | struct drm_file *file) | |
393 | { | |
394 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 395 | |
ff72145b DA |
396 | return i915_gem_create(file, dev, |
397 | args->size, &args->handle); | |
398 | } | |
399 | ||
8461d226 DV |
400 | static inline int |
401 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
402 | const char *gpu_vaddr, int gpu_offset, | |
403 | int length) | |
404 | { | |
405 | int ret, cpu_offset = 0; | |
406 | ||
407 | while (length > 0) { | |
408 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
409 | int this_length = min(cacheline_end - gpu_offset, length); | |
410 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
411 | ||
412 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
413 | gpu_vaddr + swizzled_gpu_offset, | |
414 | this_length); | |
415 | if (ret) | |
416 | return ret + length; | |
417 | ||
418 | cpu_offset += this_length; | |
419 | gpu_offset += this_length; | |
420 | length -= this_length; | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
8c59967c | 426 | static inline int |
4f0c7cfb BW |
427 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
428 | const char __user *cpu_vaddr, | |
8c59967c DV |
429 | int length) |
430 | { | |
431 | int ret, cpu_offset = 0; | |
432 | ||
433 | while (length > 0) { | |
434 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
435 | int this_length = min(cacheline_end - gpu_offset, length); | |
436 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
437 | ||
438 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
439 | cpu_vaddr + cpu_offset, | |
440 | this_length); | |
441 | if (ret) | |
442 | return ret + length; | |
443 | ||
444 | cpu_offset += this_length; | |
445 | gpu_offset += this_length; | |
446 | length -= this_length; | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
4c914c0c BV |
452 | /* |
453 | * Pins the specified object's pages and synchronizes the object with | |
454 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
455 | * flush the object from the CPU cache. | |
456 | */ | |
457 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
458 | int *needs_clflush) | |
459 | { | |
460 | int ret; | |
461 | ||
462 | *needs_clflush = 0; | |
463 | ||
464 | if (!obj->base.filp) | |
465 | return -EINVAL; | |
466 | ||
467 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
468 | /* If we're not in the cpu read domain, set ourself into the gtt | |
469 | * read domain and manually flush cachelines (if required). This | |
470 | * optimizes for the case when the gpu will dirty the data | |
471 | * anyway again before the next pread happens. */ | |
472 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
473 | obj->cache_level); | |
474 | ret = i915_gem_object_wait_rendering(obj, true); | |
475 | if (ret) | |
476 | return ret; | |
c8725f3d CW |
477 | |
478 | i915_gem_object_retire(obj); | |
4c914c0c BV |
479 | } |
480 | ||
481 | ret = i915_gem_object_get_pages(obj); | |
482 | if (ret) | |
483 | return ret; | |
484 | ||
485 | i915_gem_object_pin_pages(obj); | |
486 | ||
487 | return ret; | |
488 | } | |
489 | ||
d174bd64 DV |
490 | /* Per-page copy function for the shmem pread fastpath. |
491 | * Flushes invalid cachelines before reading the target if | |
492 | * needs_clflush is set. */ | |
eb01459f | 493 | static int |
d174bd64 DV |
494 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
495 | char __user *user_data, | |
496 | bool page_do_bit17_swizzling, bool needs_clflush) | |
497 | { | |
498 | char *vaddr; | |
499 | int ret; | |
500 | ||
e7e58eb5 | 501 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
502 | return -EINVAL; |
503 | ||
504 | vaddr = kmap_atomic(page); | |
505 | if (needs_clflush) | |
506 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
507 | page_length); | |
508 | ret = __copy_to_user_inatomic(user_data, | |
509 | vaddr + shmem_page_offset, | |
510 | page_length); | |
511 | kunmap_atomic(vaddr); | |
512 | ||
f60d7f0c | 513 | return ret ? -EFAULT : 0; |
d174bd64 DV |
514 | } |
515 | ||
23c18c71 DV |
516 | static void |
517 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
518 | bool swizzled) | |
519 | { | |
e7e58eb5 | 520 | if (unlikely(swizzled)) { |
23c18c71 DV |
521 | unsigned long start = (unsigned long) addr; |
522 | unsigned long end = (unsigned long) addr + length; | |
523 | ||
524 | /* For swizzling simply ensure that we always flush both | |
525 | * channels. Lame, but simple and it works. Swizzled | |
526 | * pwrite/pread is far from a hotpath - current userspace | |
527 | * doesn't use it at all. */ | |
528 | start = round_down(start, 128); | |
529 | end = round_up(end, 128); | |
530 | ||
531 | drm_clflush_virt_range((void *)start, end - start); | |
532 | } else { | |
533 | drm_clflush_virt_range(addr, length); | |
534 | } | |
535 | ||
536 | } | |
537 | ||
d174bd64 DV |
538 | /* Only difference to the fast-path function is that this can handle bit17 |
539 | * and uses non-atomic copy and kmap functions. */ | |
540 | static int | |
541 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
542 | char __user *user_data, | |
543 | bool page_do_bit17_swizzling, bool needs_clflush) | |
544 | { | |
545 | char *vaddr; | |
546 | int ret; | |
547 | ||
548 | vaddr = kmap(page); | |
549 | if (needs_clflush) | |
23c18c71 DV |
550 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
551 | page_length, | |
552 | page_do_bit17_swizzling); | |
d174bd64 DV |
553 | |
554 | if (page_do_bit17_swizzling) | |
555 | ret = __copy_to_user_swizzled(user_data, | |
556 | vaddr, shmem_page_offset, | |
557 | page_length); | |
558 | else | |
559 | ret = __copy_to_user(user_data, | |
560 | vaddr + shmem_page_offset, | |
561 | page_length); | |
562 | kunmap(page); | |
563 | ||
f60d7f0c | 564 | return ret ? - EFAULT : 0; |
d174bd64 DV |
565 | } |
566 | ||
eb01459f | 567 | static int |
dbf7bff0 DV |
568 | i915_gem_shmem_pread(struct drm_device *dev, |
569 | struct drm_i915_gem_object *obj, | |
570 | struct drm_i915_gem_pread *args, | |
571 | struct drm_file *file) | |
eb01459f | 572 | { |
8461d226 | 573 | char __user *user_data; |
eb01459f | 574 | ssize_t remain; |
8461d226 | 575 | loff_t offset; |
eb2c0c81 | 576 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 577 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 578 | int prefaulted = 0; |
8489731c | 579 | int needs_clflush = 0; |
67d5a50c | 580 | struct sg_page_iter sg_iter; |
eb01459f | 581 | |
2bb4629a | 582 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
583 | remain = args->size; |
584 | ||
8461d226 | 585 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 586 | |
4c914c0c | 587 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
588 | if (ret) |
589 | return ret; | |
590 | ||
8461d226 | 591 | offset = args->offset; |
eb01459f | 592 | |
67d5a50c ID |
593 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
594 | offset >> PAGE_SHIFT) { | |
2db76d7c | 595 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
596 | |
597 | if (remain <= 0) | |
598 | break; | |
599 | ||
eb01459f EA |
600 | /* Operation in this page |
601 | * | |
eb01459f | 602 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
603 | * page_length = bytes to copy for this page |
604 | */ | |
c8cbbb8b | 605 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
606 | page_length = remain; |
607 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
608 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 609 | |
8461d226 DV |
610 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
611 | (page_to_phys(page) & (1 << 17)) != 0; | |
612 | ||
d174bd64 DV |
613 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
614 | user_data, page_do_bit17_swizzling, | |
615 | needs_clflush); | |
616 | if (ret == 0) | |
617 | goto next_page; | |
dbf7bff0 | 618 | |
dbf7bff0 DV |
619 | mutex_unlock(&dev->struct_mutex); |
620 | ||
d330a953 | 621 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 622 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
623 | /* Userspace is tricking us, but we've already clobbered |
624 | * its pages with the prefault and promised to write the | |
625 | * data up to the first fault. Hence ignore any errors | |
626 | * and just continue. */ | |
627 | (void)ret; | |
628 | prefaulted = 1; | |
629 | } | |
eb01459f | 630 | |
d174bd64 DV |
631 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
632 | user_data, page_do_bit17_swizzling, | |
633 | needs_clflush); | |
eb01459f | 634 | |
dbf7bff0 | 635 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 636 | |
f60d7f0c | 637 | if (ret) |
8461d226 | 638 | goto out; |
8461d226 | 639 | |
17793c9a | 640 | next_page: |
eb01459f | 641 | remain -= page_length; |
8461d226 | 642 | user_data += page_length; |
eb01459f EA |
643 | offset += page_length; |
644 | } | |
645 | ||
4f27b75d | 646 | out: |
f60d7f0c CW |
647 | i915_gem_object_unpin_pages(obj); |
648 | ||
eb01459f EA |
649 | return ret; |
650 | } | |
651 | ||
673a394b EA |
652 | /** |
653 | * Reads data from the object referenced by handle. | |
654 | * | |
655 | * On error, the contents of *data are undefined. | |
656 | */ | |
657 | int | |
658 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 659 | struct drm_file *file) |
673a394b EA |
660 | { |
661 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 662 | struct drm_i915_gem_object *obj; |
35b62a89 | 663 | int ret = 0; |
673a394b | 664 | |
51311d0a CW |
665 | if (args->size == 0) |
666 | return 0; | |
667 | ||
668 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 669 | to_user_ptr(args->data_ptr), |
51311d0a CW |
670 | args->size)) |
671 | return -EFAULT; | |
672 | ||
4f27b75d | 673 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 674 | if (ret) |
4f27b75d | 675 | return ret; |
673a394b | 676 | |
05394f39 | 677 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 678 | if (&obj->base == NULL) { |
1d7cfea1 CW |
679 | ret = -ENOENT; |
680 | goto unlock; | |
4f27b75d | 681 | } |
673a394b | 682 | |
7dcd2499 | 683 | /* Bounds check source. */ |
05394f39 CW |
684 | if (args->offset > obj->base.size || |
685 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 686 | ret = -EINVAL; |
35b62a89 | 687 | goto out; |
ce9d419d CW |
688 | } |
689 | ||
1286ff73 DV |
690 | /* prime objects have no backing filp to GEM pread/pwrite |
691 | * pages from. | |
692 | */ | |
693 | if (!obj->base.filp) { | |
694 | ret = -EINVAL; | |
695 | goto out; | |
696 | } | |
697 | ||
db53a302 CW |
698 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
699 | ||
dbf7bff0 | 700 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 701 | |
35b62a89 | 702 | out: |
05394f39 | 703 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 704 | unlock: |
4f27b75d | 705 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 706 | return ret; |
673a394b EA |
707 | } |
708 | ||
0839ccb8 KP |
709 | /* This is the fast write path which cannot handle |
710 | * page faults in the source data | |
9b7530cc | 711 | */ |
0839ccb8 KP |
712 | |
713 | static inline int | |
714 | fast_user_write(struct io_mapping *mapping, | |
715 | loff_t page_base, int page_offset, | |
716 | char __user *user_data, | |
717 | int length) | |
9b7530cc | 718 | { |
4f0c7cfb BW |
719 | void __iomem *vaddr_atomic; |
720 | void *vaddr; | |
0839ccb8 | 721 | unsigned long unwritten; |
9b7530cc | 722 | |
3e4d3af5 | 723 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
724 | /* We can use the cpu mem copy function because this is X86. */ |
725 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
726 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 727 | user_data, length); |
3e4d3af5 | 728 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 729 | return unwritten; |
0839ccb8 KP |
730 | } |
731 | ||
3de09aa3 EA |
732 | /** |
733 | * This is the fast pwrite path, where we copy the data directly from the | |
734 | * user into the GTT, uncached. | |
735 | */ | |
673a394b | 736 | static int |
05394f39 CW |
737 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
738 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 739 | struct drm_i915_gem_pwrite *args, |
05394f39 | 740 | struct drm_file *file) |
673a394b | 741 | { |
3e31c6c0 | 742 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 743 | ssize_t remain; |
0839ccb8 | 744 | loff_t offset, page_base; |
673a394b | 745 | char __user *user_data; |
935aaa69 DV |
746 | int page_offset, page_length, ret; |
747 | ||
1ec9e26d | 748 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
749 | if (ret) |
750 | goto out; | |
751 | ||
752 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
753 | if (ret) | |
754 | goto out_unpin; | |
755 | ||
756 | ret = i915_gem_object_put_fence(obj); | |
757 | if (ret) | |
758 | goto out_unpin; | |
673a394b | 759 | |
2bb4629a | 760 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 761 | remain = args->size; |
673a394b | 762 | |
f343c5f6 | 763 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
764 | |
765 | while (remain > 0) { | |
766 | /* Operation in this page | |
767 | * | |
0839ccb8 KP |
768 | * page_base = page offset within aperture |
769 | * page_offset = offset within page | |
770 | * page_length = bytes to copy for this page | |
673a394b | 771 | */ |
c8cbbb8b CW |
772 | page_base = offset & PAGE_MASK; |
773 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
774 | page_length = remain; |
775 | if ((page_offset + remain) > PAGE_SIZE) | |
776 | page_length = PAGE_SIZE - page_offset; | |
777 | ||
0839ccb8 | 778 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
779 | * source page isn't available. Return the error and we'll |
780 | * retry in the slow path. | |
0839ccb8 | 781 | */ |
5d4545ae | 782 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
783 | page_offset, user_data, page_length)) { |
784 | ret = -EFAULT; | |
785 | goto out_unpin; | |
786 | } | |
673a394b | 787 | |
0839ccb8 KP |
788 | remain -= page_length; |
789 | user_data += page_length; | |
790 | offset += page_length; | |
673a394b | 791 | } |
673a394b | 792 | |
935aaa69 | 793 | out_unpin: |
d7f46fc4 | 794 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 795 | out: |
3de09aa3 | 796 | return ret; |
673a394b EA |
797 | } |
798 | ||
d174bd64 DV |
799 | /* Per-page copy function for the shmem pwrite fastpath. |
800 | * Flushes invalid cachelines before writing to the target if | |
801 | * needs_clflush_before is set and flushes out any written cachelines after | |
802 | * writing if needs_clflush is set. */ | |
3043c60c | 803 | static int |
d174bd64 DV |
804 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
805 | char __user *user_data, | |
806 | bool page_do_bit17_swizzling, | |
807 | bool needs_clflush_before, | |
808 | bool needs_clflush_after) | |
673a394b | 809 | { |
d174bd64 | 810 | char *vaddr; |
673a394b | 811 | int ret; |
3de09aa3 | 812 | |
e7e58eb5 | 813 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 814 | return -EINVAL; |
3de09aa3 | 815 | |
d174bd64 DV |
816 | vaddr = kmap_atomic(page); |
817 | if (needs_clflush_before) | |
818 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
819 | page_length); | |
c2831a94 CW |
820 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
821 | user_data, page_length); | |
d174bd64 DV |
822 | if (needs_clflush_after) |
823 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
824 | page_length); | |
825 | kunmap_atomic(vaddr); | |
3de09aa3 | 826 | |
755d2218 | 827 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
828 | } |
829 | ||
d174bd64 DV |
830 | /* Only difference to the fast-path function is that this can handle bit17 |
831 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 832 | static int |
d174bd64 DV |
833 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
834 | char __user *user_data, | |
835 | bool page_do_bit17_swizzling, | |
836 | bool needs_clflush_before, | |
837 | bool needs_clflush_after) | |
673a394b | 838 | { |
d174bd64 DV |
839 | char *vaddr; |
840 | int ret; | |
e5281ccd | 841 | |
d174bd64 | 842 | vaddr = kmap(page); |
e7e58eb5 | 843 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
844 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
845 | page_length, | |
846 | page_do_bit17_swizzling); | |
d174bd64 DV |
847 | if (page_do_bit17_swizzling) |
848 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
849 | user_data, |
850 | page_length); | |
d174bd64 DV |
851 | else |
852 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
853 | user_data, | |
854 | page_length); | |
855 | if (needs_clflush_after) | |
23c18c71 DV |
856 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
857 | page_length, | |
858 | page_do_bit17_swizzling); | |
d174bd64 | 859 | kunmap(page); |
40123c1f | 860 | |
755d2218 | 861 | return ret ? -EFAULT : 0; |
40123c1f EA |
862 | } |
863 | ||
40123c1f | 864 | static int |
e244a443 DV |
865 | i915_gem_shmem_pwrite(struct drm_device *dev, |
866 | struct drm_i915_gem_object *obj, | |
867 | struct drm_i915_gem_pwrite *args, | |
868 | struct drm_file *file) | |
40123c1f | 869 | { |
40123c1f | 870 | ssize_t remain; |
8c59967c DV |
871 | loff_t offset; |
872 | char __user *user_data; | |
eb2c0c81 | 873 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 874 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 875 | int hit_slowpath = 0; |
58642885 DV |
876 | int needs_clflush_after = 0; |
877 | int needs_clflush_before = 0; | |
67d5a50c | 878 | struct sg_page_iter sg_iter; |
40123c1f | 879 | |
2bb4629a | 880 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
881 | remain = args->size; |
882 | ||
8c59967c | 883 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 884 | |
58642885 DV |
885 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
886 | /* If we're not in the cpu write domain, set ourself into the gtt | |
887 | * write domain and manually flush cachelines (if required). This | |
888 | * optimizes for the case when the gpu will use the data | |
889 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 890 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
891 | ret = i915_gem_object_wait_rendering(obj, false); |
892 | if (ret) | |
893 | return ret; | |
c8725f3d CW |
894 | |
895 | i915_gem_object_retire(obj); | |
58642885 | 896 | } |
c76ce038 CW |
897 | /* Same trick applies to invalidate partially written cachelines read |
898 | * before writing. */ | |
899 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
900 | needs_clflush_before = | |
901 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 902 | |
755d2218 CW |
903 | ret = i915_gem_object_get_pages(obj); |
904 | if (ret) | |
905 | return ret; | |
906 | ||
907 | i915_gem_object_pin_pages(obj); | |
908 | ||
673a394b | 909 | offset = args->offset; |
05394f39 | 910 | obj->dirty = 1; |
673a394b | 911 | |
67d5a50c ID |
912 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
913 | offset >> PAGE_SHIFT) { | |
2db76d7c | 914 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 915 | int partial_cacheline_write; |
e5281ccd | 916 | |
9da3da66 CW |
917 | if (remain <= 0) |
918 | break; | |
919 | ||
40123c1f EA |
920 | /* Operation in this page |
921 | * | |
40123c1f | 922 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
923 | * page_length = bytes to copy for this page |
924 | */ | |
c8cbbb8b | 925 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
926 | |
927 | page_length = remain; | |
928 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
929 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 930 | |
58642885 DV |
931 | /* If we don't overwrite a cacheline completely we need to be |
932 | * careful to have up-to-date data by first clflushing. Don't | |
933 | * overcomplicate things and flush the entire patch. */ | |
934 | partial_cacheline_write = needs_clflush_before && | |
935 | ((shmem_page_offset | page_length) | |
936 | & (boot_cpu_data.x86_clflush_size - 1)); | |
937 | ||
8c59967c DV |
938 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
939 | (page_to_phys(page) & (1 << 17)) != 0; | |
940 | ||
d174bd64 DV |
941 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
942 | user_data, page_do_bit17_swizzling, | |
943 | partial_cacheline_write, | |
944 | needs_clflush_after); | |
945 | if (ret == 0) | |
946 | goto next_page; | |
e244a443 DV |
947 | |
948 | hit_slowpath = 1; | |
e244a443 | 949 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
950 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
951 | user_data, page_do_bit17_swizzling, | |
952 | partial_cacheline_write, | |
953 | needs_clflush_after); | |
40123c1f | 954 | |
e244a443 | 955 | mutex_lock(&dev->struct_mutex); |
755d2218 | 956 | |
755d2218 | 957 | if (ret) |
8c59967c | 958 | goto out; |
8c59967c | 959 | |
17793c9a | 960 | next_page: |
40123c1f | 961 | remain -= page_length; |
8c59967c | 962 | user_data += page_length; |
40123c1f | 963 | offset += page_length; |
673a394b EA |
964 | } |
965 | ||
fbd5a26d | 966 | out: |
755d2218 CW |
967 | i915_gem_object_unpin_pages(obj); |
968 | ||
e244a443 | 969 | if (hit_slowpath) { |
8dcf015e DV |
970 | /* |
971 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
972 | * cachelines in-line while writing and the object moved | |
973 | * out of the cpu write domain while we've dropped the lock. | |
974 | */ | |
975 | if (!needs_clflush_after && | |
976 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
977 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
978 | i915_gem_chipset_flush(dev); | |
e244a443 | 979 | } |
8c59967c | 980 | } |
673a394b | 981 | |
58642885 | 982 | if (needs_clflush_after) |
e76e9aeb | 983 | i915_gem_chipset_flush(dev); |
58642885 | 984 | |
40123c1f | 985 | return ret; |
673a394b EA |
986 | } |
987 | ||
988 | /** | |
989 | * Writes data to the object referenced by handle. | |
990 | * | |
991 | * On error, the contents of the buffer that were to be modified are undefined. | |
992 | */ | |
993 | int | |
994 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 995 | struct drm_file *file) |
673a394b EA |
996 | { |
997 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 998 | struct drm_i915_gem_object *obj; |
51311d0a CW |
999 | int ret; |
1000 | ||
1001 | if (args->size == 0) | |
1002 | return 0; | |
1003 | ||
1004 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1005 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1006 | args->size)) |
1007 | return -EFAULT; | |
1008 | ||
d330a953 | 1009 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1010 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1011 | args->size); | |
1012 | if (ret) | |
1013 | return -EFAULT; | |
1014 | } | |
673a394b | 1015 | |
fbd5a26d | 1016 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1017 | if (ret) |
fbd5a26d | 1018 | return ret; |
1d7cfea1 | 1019 | |
05394f39 | 1020 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1021 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1022 | ret = -ENOENT; |
1023 | goto unlock; | |
fbd5a26d | 1024 | } |
673a394b | 1025 | |
7dcd2499 | 1026 | /* Bounds check destination. */ |
05394f39 CW |
1027 | if (args->offset > obj->base.size || |
1028 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1029 | ret = -EINVAL; |
35b62a89 | 1030 | goto out; |
ce9d419d CW |
1031 | } |
1032 | ||
1286ff73 DV |
1033 | /* prime objects have no backing filp to GEM pread/pwrite |
1034 | * pages from. | |
1035 | */ | |
1036 | if (!obj->base.filp) { | |
1037 | ret = -EINVAL; | |
1038 | goto out; | |
1039 | } | |
1040 | ||
db53a302 CW |
1041 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1042 | ||
935aaa69 | 1043 | ret = -EFAULT; |
673a394b EA |
1044 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1045 | * it would end up going through the fenced access, and we'll get | |
1046 | * different detiling behavior between reading and writing. | |
1047 | * pread/pwrite currently are reading and writing from the CPU | |
1048 | * perspective, requiring manual detiling by the client. | |
1049 | */ | |
00731155 CW |
1050 | if (obj->phys_handle) { |
1051 | ret = i915_gem_phys_pwrite(obj, args, file); | |
5c0480f2 DV |
1052 | goto out; |
1053 | } | |
1054 | ||
2c22569b CW |
1055 | if (obj->tiling_mode == I915_TILING_NONE && |
1056 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1057 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1058 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1059 | /* Note that the gtt paths might fail with non-page-backed user |
1060 | * pointers (e.g. gtt mappings when moving data between | |
1061 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1062 | } |
673a394b | 1063 | |
86a1ee26 | 1064 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 1065 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 1066 | |
35b62a89 | 1067 | out: |
05394f39 | 1068 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1069 | unlock: |
fbd5a26d | 1070 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1071 | return ret; |
1072 | } | |
1073 | ||
b361237b | 1074 | int |
33196ded | 1075 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1076 | bool interruptible) |
1077 | { | |
1f83fee0 | 1078 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1079 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1080 | * -EIO unconditionally for these. */ | |
1081 | if (!interruptible) | |
1082 | return -EIO; | |
1083 | ||
1f83fee0 DV |
1084 | /* Recovery complete, but the reset failed ... */ |
1085 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1086 | return -EIO; |
1087 | ||
1088 | return -EAGAIN; | |
1089 | } | |
1090 | ||
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
1096 | * equal. | |
1097 | */ | |
84c33a64 | 1098 | int |
a4872ba6 | 1099 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
b361237b CW |
1100 | { |
1101 | int ret; | |
1102 | ||
1103 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
1104 | ||
1105 | ret = 0; | |
1823521d | 1106 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 1107 | ret = i915_add_request(ring, NULL); |
b361237b CW |
1108 | |
1109 | return ret; | |
1110 | } | |
1111 | ||
094f9a54 CW |
1112 | static void fake_irq(unsigned long data) |
1113 | { | |
1114 | wake_up_process((struct task_struct *)data); | |
1115 | } | |
1116 | ||
1117 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1118 | struct intel_engine_cs *ring) |
094f9a54 CW |
1119 | { |
1120 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1121 | } | |
1122 | ||
b29c19b6 CW |
1123 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1124 | { | |
1125 | if (file_priv == NULL) | |
1126 | return true; | |
1127 | ||
1128 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1129 | } | |
1130 | ||
b361237b CW |
1131 | /** |
1132 | * __wait_seqno - wait until execution of seqno has finished | |
1133 | * @ring: the ring expected to report seqno | |
1134 | * @seqno: duh! | |
f69061be | 1135 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
1136 | * @interruptible: do an interruptible wait (normally yes) |
1137 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1138 | * | |
f69061be DV |
1139 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1140 | * values have been read by the caller in an smp safe manner. Where read-side | |
1141 | * locks are involved, it is sufficient to read the reset_counter before | |
1142 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1143 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1144 | * inserted. | |
1145 | * | |
b361237b CW |
1146 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1147 | * errno with remaining time filled in timeout argument. | |
1148 | */ | |
a4872ba6 | 1149 | static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
f69061be | 1150 | unsigned reset_counter, |
b29c19b6 CW |
1151 | bool interruptible, |
1152 | struct timespec *timeout, | |
1153 | struct drm_i915_file_private *file_priv) | |
b361237b | 1154 | { |
3d13ef2e | 1155 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1156 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1157 | const bool irq_test_in_progress = |
1158 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 CW |
1159 | struct timespec before, now; |
1160 | DEFINE_WAIT(wait); | |
47e9766d | 1161 | unsigned long timeout_expire; |
b361237b CW |
1162 | int ret; |
1163 | ||
5d584b2e | 1164 | WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n"); |
c67a470b | 1165 | |
b361237b CW |
1166 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1167 | return 0; | |
1168 | ||
47e9766d | 1169 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
b361237b | 1170 | |
3d13ef2e | 1171 | if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1172 | gen6_rps_boost(dev_priv); |
1173 | if (file_priv) | |
1174 | mod_delayed_work(dev_priv->wq, | |
1175 | &file_priv->mm.idle_work, | |
1176 | msecs_to_jiffies(100)); | |
1177 | } | |
1178 | ||
168c3f21 | 1179 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1180 | return -ENODEV; |
1181 | ||
094f9a54 CW |
1182 | /* Record current time in case interrupted by signal, or wedged */ |
1183 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1184 | getrawmonotonic(&before); |
094f9a54 CW |
1185 | for (;;) { |
1186 | struct timer_list timer; | |
b361237b | 1187 | |
094f9a54 CW |
1188 | prepare_to_wait(&ring->irq_queue, &wait, |
1189 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1190 | |
f69061be DV |
1191 | /* We need to check whether any gpu reset happened in between |
1192 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1193 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1194 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1195 | * is truely gone. */ | |
1196 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1197 | if (ret == 0) | |
1198 | ret = -EAGAIN; | |
1199 | break; | |
1200 | } | |
f69061be | 1201 | |
094f9a54 CW |
1202 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1203 | ret = 0; | |
1204 | break; | |
1205 | } | |
b361237b | 1206 | |
094f9a54 CW |
1207 | if (interruptible && signal_pending(current)) { |
1208 | ret = -ERESTARTSYS; | |
1209 | break; | |
1210 | } | |
1211 | ||
47e9766d | 1212 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1213 | ret = -ETIME; |
1214 | break; | |
1215 | } | |
1216 | ||
1217 | timer.function = NULL; | |
1218 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1219 | unsigned long expire; |
1220 | ||
094f9a54 | 1221 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1222 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1223 | mod_timer(&timer, expire); |
1224 | } | |
1225 | ||
5035c275 | 1226 | io_schedule(); |
094f9a54 | 1227 | |
094f9a54 CW |
1228 | if (timer.function) { |
1229 | del_singleshot_timer_sync(&timer); | |
1230 | destroy_timer_on_stack(&timer); | |
1231 | } | |
1232 | } | |
b361237b | 1233 | getrawmonotonic(&now); |
094f9a54 | 1234 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1235 | |
168c3f21 MK |
1236 | if (!irq_test_in_progress) |
1237 | ring->irq_put(ring); | |
094f9a54 CW |
1238 | |
1239 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1240 | |
1241 | if (timeout) { | |
1242 | struct timespec sleep_time = timespec_sub(now, before); | |
1243 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1244 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1245 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1246 | } |
1247 | ||
094f9a54 | 1248 | return ret; |
b361237b CW |
1249 | } |
1250 | ||
1251 | /** | |
1252 | * Waits for a sequence number to be signaled, and cleans up the | |
1253 | * request and object lists appropriately for that event. | |
1254 | */ | |
1255 | int | |
a4872ba6 | 1256 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
b361237b CW |
1257 | { |
1258 | struct drm_device *dev = ring->dev; | |
1259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1260 | bool interruptible = dev_priv->mm.interruptible; | |
1261 | int ret; | |
1262 | ||
1263 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1264 | BUG_ON(seqno == 0); | |
1265 | ||
33196ded | 1266 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1267 | if (ret) |
1268 | return ret; | |
1269 | ||
1270 | ret = i915_gem_check_olr(ring, seqno); | |
1271 | if (ret) | |
1272 | return ret; | |
1273 | ||
f69061be DV |
1274 | return __wait_seqno(ring, seqno, |
1275 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1276 | interruptible, NULL, NULL); |
b361237b CW |
1277 | } |
1278 | ||
d26e3af8 CW |
1279 | static int |
1280 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
a4872ba6 | 1281 | struct intel_engine_cs *ring) |
d26e3af8 | 1282 | { |
c8725f3d CW |
1283 | if (!obj->active) |
1284 | return 0; | |
d26e3af8 CW |
1285 | |
1286 | /* Manually manage the write flush as we may have not yet | |
1287 | * retired the buffer. | |
1288 | * | |
1289 | * Note that the last_write_seqno is always the earlier of | |
1290 | * the two (read/write) seqno, so if we haved successfully waited, | |
1291 | * we know we have passed the last write. | |
1292 | */ | |
1293 | obj->last_write_seqno = 0; | |
d26e3af8 CW |
1294 | |
1295 | return 0; | |
1296 | } | |
1297 | ||
b361237b CW |
1298 | /** |
1299 | * Ensures that all rendering to the object has completed and the object is | |
1300 | * safe to unbind from the GTT or access from the CPU. | |
1301 | */ | |
1302 | static __must_check int | |
1303 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1304 | bool readonly) | |
1305 | { | |
a4872ba6 | 1306 | struct intel_engine_cs *ring = obj->ring; |
b361237b CW |
1307 | u32 seqno; |
1308 | int ret; | |
1309 | ||
1310 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1311 | if (seqno == 0) | |
1312 | return 0; | |
1313 | ||
1314 | ret = i915_wait_seqno(ring, seqno); | |
1315 | if (ret) | |
1316 | return ret; | |
1317 | ||
d26e3af8 | 1318 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1319 | } |
1320 | ||
3236f57a CW |
1321 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1322 | * as the object state may change during this call. | |
1323 | */ | |
1324 | static __must_check int | |
1325 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1326 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1327 | bool readonly) |
1328 | { | |
1329 | struct drm_device *dev = obj->base.dev; | |
1330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1331 | struct intel_engine_cs *ring = obj->ring; |
f69061be | 1332 | unsigned reset_counter; |
3236f57a CW |
1333 | u32 seqno; |
1334 | int ret; | |
1335 | ||
1336 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1337 | BUG_ON(!dev_priv->mm.interruptible); | |
1338 | ||
1339 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1340 | if (seqno == 0) | |
1341 | return 0; | |
1342 | ||
33196ded | 1343 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1344 | if (ret) |
1345 | return ret; | |
1346 | ||
1347 | ret = i915_gem_check_olr(ring, seqno); | |
1348 | if (ret) | |
1349 | return ret; | |
1350 | ||
f69061be | 1351 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1352 | mutex_unlock(&dev->struct_mutex); |
6e4930f6 | 1353 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
3236f57a | 1354 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1355 | if (ret) |
1356 | return ret; | |
3236f57a | 1357 | |
d26e3af8 | 1358 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1359 | } |
1360 | ||
673a394b | 1361 | /** |
2ef7eeaa EA |
1362 | * Called when user space prepares to use an object with the CPU, either |
1363 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1364 | */ |
1365 | int | |
1366 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1367 | struct drm_file *file) |
673a394b EA |
1368 | { |
1369 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1370 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1371 | uint32_t read_domains = args->read_domains; |
1372 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1373 | int ret; |
1374 | ||
2ef7eeaa | 1375 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1376 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1377 | return -EINVAL; |
1378 | ||
21d509e3 | 1379 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1380 | return -EINVAL; |
1381 | ||
1382 | /* Having something in the write domain implies it's in the read | |
1383 | * domain, and only that read domain. Enforce that in the request. | |
1384 | */ | |
1385 | if (write_domain != 0 && read_domains != write_domain) | |
1386 | return -EINVAL; | |
1387 | ||
76c1dec1 | 1388 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1389 | if (ret) |
76c1dec1 | 1390 | return ret; |
1d7cfea1 | 1391 | |
05394f39 | 1392 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1393 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1394 | ret = -ENOENT; |
1395 | goto unlock; | |
76c1dec1 | 1396 | } |
673a394b | 1397 | |
3108e99e | 1398 | intel_edp_psr_exit(dev); |
7c8f8a70 | 1399 | |
3236f57a CW |
1400 | /* Try to flush the object off the GPU without holding the lock. |
1401 | * We will repeat the flush holding the lock in the normal manner | |
1402 | * to catch cases where we are gazumped. | |
1403 | */ | |
6e4930f6 CW |
1404 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1405 | file->driver_priv, | |
1406 | !write_domain); | |
3236f57a CW |
1407 | if (ret) |
1408 | goto unref; | |
1409 | ||
2ef7eeaa EA |
1410 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1411 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1412 | |
1413 | /* Silently promote "you're not bound, there was nothing to do" | |
1414 | * to success, since the client was just asking us to | |
1415 | * make sure everything was done. | |
1416 | */ | |
1417 | if (ret == -EINVAL) | |
1418 | ret = 0; | |
2ef7eeaa | 1419 | } else { |
e47c68e9 | 1420 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1421 | } |
1422 | ||
3236f57a | 1423 | unref: |
05394f39 | 1424 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1425 | unlock: |
673a394b EA |
1426 | mutex_unlock(&dev->struct_mutex); |
1427 | return ret; | |
1428 | } | |
1429 | ||
1430 | /** | |
1431 | * Called when user space has done writes to this buffer | |
1432 | */ | |
1433 | int | |
1434 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1435 | struct drm_file *file) |
673a394b EA |
1436 | { |
1437 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1438 | struct drm_i915_gem_object *obj; |
673a394b EA |
1439 | int ret = 0; |
1440 | ||
76c1dec1 | 1441 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1442 | if (ret) |
76c1dec1 | 1443 | return ret; |
1d7cfea1 | 1444 | |
3108e99e | 1445 | intel_edp_psr_exit(dev); |
7c8f8a70 | 1446 | |
05394f39 | 1447 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1448 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1449 | ret = -ENOENT; |
1450 | goto unlock; | |
673a394b EA |
1451 | } |
1452 | ||
673a394b | 1453 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1454 | if (obj->pin_display) |
1455 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1456 | |
05394f39 | 1457 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1458 | unlock: |
673a394b EA |
1459 | mutex_unlock(&dev->struct_mutex); |
1460 | return ret; | |
1461 | } | |
1462 | ||
1463 | /** | |
1464 | * Maps the contents of an object, returning the address it is mapped | |
1465 | * into. | |
1466 | * | |
1467 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1468 | * imply a ref on the object itself. | |
1469 | */ | |
1470 | int | |
1471 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1472 | struct drm_file *file) |
673a394b EA |
1473 | { |
1474 | struct drm_i915_gem_mmap *args = data; | |
1475 | struct drm_gem_object *obj; | |
673a394b EA |
1476 | unsigned long addr; |
1477 | ||
05394f39 | 1478 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1479 | if (obj == NULL) |
bf79cb91 | 1480 | return -ENOENT; |
673a394b | 1481 | |
1286ff73 DV |
1482 | /* prime objects have no backing filp to GEM mmap |
1483 | * pages from. | |
1484 | */ | |
1485 | if (!obj->filp) { | |
1486 | drm_gem_object_unreference_unlocked(obj); | |
1487 | return -EINVAL; | |
1488 | } | |
1489 | ||
6be5ceb0 | 1490 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1491 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1492 | args->offset); | |
bc9025bd | 1493 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1494 | if (IS_ERR((void *)addr)) |
1495 | return addr; | |
1496 | ||
1497 | args->addr_ptr = (uint64_t) addr; | |
1498 | ||
1499 | return 0; | |
1500 | } | |
1501 | ||
de151cf6 JB |
1502 | /** |
1503 | * i915_gem_fault - fault a page into the GTT | |
1504 | * vma: VMA in question | |
1505 | * vmf: fault info | |
1506 | * | |
1507 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1508 | * from userspace. The fault handler takes care of binding the object to | |
1509 | * the GTT (if needed), allocating and programming a fence register (again, | |
1510 | * only if needed based on whether the old reg is still valid or the object | |
1511 | * is tiled) and inserting a new PTE into the faulting process. | |
1512 | * | |
1513 | * Note that the faulting process may involve evicting existing objects | |
1514 | * from the GTT and/or fence registers to make room. So performance may | |
1515 | * suffer if the GTT working set is large or there are few fence registers | |
1516 | * left. | |
1517 | */ | |
1518 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1519 | { | |
05394f39 CW |
1520 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1521 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1522 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1523 | pgoff_t page_offset; |
1524 | unsigned long pfn; | |
1525 | int ret = 0; | |
0f973f27 | 1526 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1527 | |
f65c9168 PZ |
1528 | intel_runtime_pm_get(dev_priv); |
1529 | ||
de151cf6 JB |
1530 | /* We don't use vmf->pgoff since that has the fake offset */ |
1531 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1532 | PAGE_SHIFT; | |
1533 | ||
d9bc7e9f CW |
1534 | ret = i915_mutex_lock_interruptible(dev); |
1535 | if (ret) | |
1536 | goto out; | |
a00b10c3 | 1537 | |
db53a302 CW |
1538 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1539 | ||
6e4930f6 CW |
1540 | /* Try to flush the object off the GPU first without holding the lock. |
1541 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1542 | * repeat the flush holding the lock in the normal manner to catch cases | |
1543 | * where we are gazumped. | |
1544 | */ | |
1545 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1546 | if (ret) | |
1547 | goto unlock; | |
1548 | ||
eb119bd6 CW |
1549 | /* Access to snoopable pages through the GTT is incoherent. */ |
1550 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1551 | ret = -EFAULT; |
eb119bd6 CW |
1552 | goto unlock; |
1553 | } | |
1554 | ||
d9bc7e9f | 1555 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1556 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1557 | if (ret) |
1558 | goto unlock; | |
4a684a41 | 1559 | |
c9839303 CW |
1560 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1561 | if (ret) | |
1562 | goto unpin; | |
74898d7e | 1563 | |
06d98131 | 1564 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1565 | if (ret) |
c9839303 | 1566 | goto unpin; |
7d1c4804 | 1567 | |
b90b91d8 | 1568 | /* Finally, remap it using the new GTT offset */ |
f343c5f6 BW |
1569 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1570 | pfn >>= PAGE_SHIFT; | |
de151cf6 | 1571 | |
b90b91d8 | 1572 | if (!obj->fault_mappable) { |
beff0d0f VS |
1573 | unsigned long size = min_t(unsigned long, |
1574 | vma->vm_end - vma->vm_start, | |
1575 | obj->base.size); | |
b90b91d8 CW |
1576 | int i; |
1577 | ||
beff0d0f | 1578 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
b90b91d8 CW |
1579 | ret = vm_insert_pfn(vma, |
1580 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1581 | pfn + i); | |
1582 | if (ret) | |
1583 | break; | |
1584 | } | |
1585 | ||
1586 | obj->fault_mappable = true; | |
1587 | } else | |
1588 | ret = vm_insert_pfn(vma, | |
1589 | (unsigned long)vmf->virtual_address, | |
1590 | pfn + page_offset); | |
c9839303 | 1591 | unpin: |
d7f46fc4 | 1592 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1593 | unlock: |
de151cf6 | 1594 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1595 | out: |
de151cf6 | 1596 | switch (ret) { |
d9bc7e9f | 1597 | case -EIO: |
a9340cca DV |
1598 | /* If this -EIO is due to a gpu hang, give the reset code a |
1599 | * chance to clean up the mess. Otherwise return the proper | |
1600 | * SIGBUS. */ | |
f65c9168 PZ |
1601 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
1602 | ret = VM_FAULT_SIGBUS; | |
1603 | break; | |
1604 | } | |
045e769a | 1605 | case -EAGAIN: |
571c608d DV |
1606 | /* |
1607 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1608 | * handler to reset everything when re-faulting in | |
1609 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1610 | */ |
c715089f CW |
1611 | case 0: |
1612 | case -ERESTARTSYS: | |
bed636ab | 1613 | case -EINTR: |
e79e0fe3 DR |
1614 | case -EBUSY: |
1615 | /* | |
1616 | * EBUSY is ok: this just means that another thread | |
1617 | * already did the job. | |
1618 | */ | |
f65c9168 PZ |
1619 | ret = VM_FAULT_NOPAGE; |
1620 | break; | |
de151cf6 | 1621 | case -ENOMEM: |
f65c9168 PZ |
1622 | ret = VM_FAULT_OOM; |
1623 | break; | |
a7c2e1aa | 1624 | case -ENOSPC: |
45d67817 | 1625 | case -EFAULT: |
f65c9168 PZ |
1626 | ret = VM_FAULT_SIGBUS; |
1627 | break; | |
de151cf6 | 1628 | default: |
a7c2e1aa | 1629 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1630 | ret = VM_FAULT_SIGBUS; |
1631 | break; | |
de151cf6 | 1632 | } |
f65c9168 PZ |
1633 | |
1634 | intel_runtime_pm_put(dev_priv); | |
1635 | return ret; | |
de151cf6 JB |
1636 | } |
1637 | ||
901782b2 CW |
1638 | /** |
1639 | * i915_gem_release_mmap - remove physical page mappings | |
1640 | * @obj: obj in question | |
1641 | * | |
af901ca1 | 1642 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1643 | * relinquish ownership of the pages back to the system. |
1644 | * | |
1645 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1646 | * object through the GTT and then lose the fence register due to | |
1647 | * resource pressure. Similarly if the object has been moved out of the | |
1648 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1649 | * mapping will then trigger a page fault on the next user access, allowing | |
1650 | * fixup by i915_gem_fault(). | |
1651 | */ | |
d05ca301 | 1652 | void |
05394f39 | 1653 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1654 | { |
6299f992 CW |
1655 | if (!obj->fault_mappable) |
1656 | return; | |
901782b2 | 1657 | |
6796cb16 DH |
1658 | drm_vma_node_unmap(&obj->base.vma_node, |
1659 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1660 | obj->fault_mappable = false; |
901782b2 CW |
1661 | } |
1662 | ||
6254b204 CW |
1663 | void |
1664 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1665 | { | |
1666 | struct drm_i915_gem_object *obj; | |
1667 | ||
1668 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1669 | i915_gem_release_mmap(obj); | |
1670 | } | |
1671 | ||
0fa87796 | 1672 | uint32_t |
e28f8711 | 1673 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1674 | { |
e28f8711 | 1675 | uint32_t gtt_size; |
92b88aeb CW |
1676 | |
1677 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1678 | tiling_mode == I915_TILING_NONE) |
1679 | return size; | |
92b88aeb CW |
1680 | |
1681 | /* Previous chips need a power-of-two fence region when tiling */ | |
1682 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1683 | gtt_size = 1024*1024; |
92b88aeb | 1684 | else |
e28f8711 | 1685 | gtt_size = 512*1024; |
92b88aeb | 1686 | |
e28f8711 CW |
1687 | while (gtt_size < size) |
1688 | gtt_size <<= 1; | |
92b88aeb | 1689 | |
e28f8711 | 1690 | return gtt_size; |
92b88aeb CW |
1691 | } |
1692 | ||
de151cf6 JB |
1693 | /** |
1694 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1695 | * @obj: object to check | |
1696 | * | |
1697 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1698 | * potential fence register mapping. |
de151cf6 | 1699 | */ |
d865110c ID |
1700 | uint32_t |
1701 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1702 | int tiling_mode, bool fenced) | |
de151cf6 | 1703 | { |
de151cf6 JB |
1704 | /* |
1705 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1706 | * if a fence register is needed for the object. | |
1707 | */ | |
d865110c | 1708 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1709 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1710 | return 4096; |
1711 | ||
a00b10c3 CW |
1712 | /* |
1713 | * Previous chips need to be aligned to the size of the smallest | |
1714 | * fence register that can contain the object. | |
1715 | */ | |
e28f8711 | 1716 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1717 | } |
1718 | ||
d8cb5086 CW |
1719 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1720 | { | |
1721 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1722 | int ret; | |
1723 | ||
0de23977 | 1724 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1725 | return 0; |
1726 | ||
da494d7c DV |
1727 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1728 | ||
d8cb5086 CW |
1729 | ret = drm_gem_create_mmap_offset(&obj->base); |
1730 | if (ret != -ENOSPC) | |
da494d7c | 1731 | goto out; |
d8cb5086 CW |
1732 | |
1733 | /* Badly fragmented mmap space? The only way we can recover | |
1734 | * space is by destroying unwanted objects. We can't randomly release | |
1735 | * mmap_offsets as userspace expects them to be persistent for the | |
1736 | * lifetime of the objects. The closest we can is to release the | |
1737 | * offsets on purgeable objects by truncating it and marking it purged, | |
1738 | * which prevents userspace from ever using that object again. | |
1739 | */ | |
1740 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1741 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1742 | if (ret != -ENOSPC) | |
da494d7c | 1743 | goto out; |
d8cb5086 CW |
1744 | |
1745 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1746 | ret = drm_gem_create_mmap_offset(&obj->base); |
1747 | out: | |
1748 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1749 | ||
1750 | return ret; | |
d8cb5086 CW |
1751 | } |
1752 | ||
1753 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1754 | { | |
d8cb5086 CW |
1755 | drm_gem_free_mmap_offset(&obj->base); |
1756 | } | |
1757 | ||
de151cf6 | 1758 | int |
ff72145b DA |
1759 | i915_gem_mmap_gtt(struct drm_file *file, |
1760 | struct drm_device *dev, | |
1761 | uint32_t handle, | |
1762 | uint64_t *offset) | |
de151cf6 | 1763 | { |
da761a6e | 1764 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1765 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1766 | int ret; |
1767 | ||
76c1dec1 | 1768 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1769 | if (ret) |
76c1dec1 | 1770 | return ret; |
de151cf6 | 1771 | |
ff72145b | 1772 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1773 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1774 | ret = -ENOENT; |
1775 | goto unlock; | |
1776 | } | |
de151cf6 | 1777 | |
5d4545ae | 1778 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1779 | ret = -E2BIG; |
ff56b0bc | 1780 | goto out; |
da761a6e CW |
1781 | } |
1782 | ||
05394f39 | 1783 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1784 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1785 | ret = -EFAULT; |
1d7cfea1 | 1786 | goto out; |
ab18282d CW |
1787 | } |
1788 | ||
d8cb5086 CW |
1789 | ret = i915_gem_object_create_mmap_offset(obj); |
1790 | if (ret) | |
1791 | goto out; | |
de151cf6 | 1792 | |
0de23977 | 1793 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1794 | |
1d7cfea1 | 1795 | out: |
05394f39 | 1796 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1797 | unlock: |
de151cf6 | 1798 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1799 | return ret; |
de151cf6 JB |
1800 | } |
1801 | ||
ff72145b DA |
1802 | /** |
1803 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1804 | * @dev: DRM device | |
1805 | * @data: GTT mapping ioctl data | |
1806 | * @file: GEM object info | |
1807 | * | |
1808 | * Simply returns the fake offset to userspace so it can mmap it. | |
1809 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1810 | * up so we can get faults in the handler above. | |
1811 | * | |
1812 | * The fault handler will take care of binding the object into the GTT | |
1813 | * (since it may have been evicted to make room for something), allocating | |
1814 | * a fence register, and mapping the appropriate aperture address into | |
1815 | * userspace. | |
1816 | */ | |
1817 | int | |
1818 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1819 | struct drm_file *file) | |
1820 | { | |
1821 | struct drm_i915_gem_mmap_gtt *args = data; | |
1822 | ||
ff72145b DA |
1823 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1824 | } | |
1825 | ||
5537252b CW |
1826 | static inline int |
1827 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1828 | { | |
1829 | return obj->madv == I915_MADV_DONTNEED; | |
1830 | } | |
1831 | ||
225067ee DV |
1832 | /* Immediately discard the backing storage */ |
1833 | static void | |
1834 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1835 | { |
4d6294bf | 1836 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1837 | |
4d6294bf CW |
1838 | if (obj->base.filp == NULL) |
1839 | return; | |
e5281ccd | 1840 | |
225067ee DV |
1841 | /* Our goal here is to return as much of the memory as |
1842 | * is possible back to the system as we are called from OOM. | |
1843 | * To do this we must instruct the shmfs to drop all of its | |
1844 | * backing pages, *now*. | |
1845 | */ | |
5537252b | 1846 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1847 | obj->madv = __I915_MADV_PURGED; |
1848 | } | |
e5281ccd | 1849 | |
5537252b CW |
1850 | /* Try to discard unwanted pages */ |
1851 | static void | |
1852 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1853 | { |
5537252b CW |
1854 | struct address_space *mapping; |
1855 | ||
1856 | switch (obj->madv) { | |
1857 | case I915_MADV_DONTNEED: | |
1858 | i915_gem_object_truncate(obj); | |
1859 | case __I915_MADV_PURGED: | |
1860 | return; | |
1861 | } | |
1862 | ||
1863 | if (obj->base.filp == NULL) | |
1864 | return; | |
1865 | ||
1866 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1867 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1868 | } |
1869 | ||
5cdf5881 | 1870 | static void |
05394f39 | 1871 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1872 | { |
90797e6d ID |
1873 | struct sg_page_iter sg_iter; |
1874 | int ret; | |
1286ff73 | 1875 | |
05394f39 | 1876 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1877 | |
6c085a72 CW |
1878 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1879 | if (ret) { | |
1880 | /* In the event of a disaster, abandon all caches and | |
1881 | * hope for the best. | |
1882 | */ | |
1883 | WARN_ON(ret != -EIO); | |
2c22569b | 1884 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1885 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1886 | } | |
1887 | ||
6dacfd2f | 1888 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1889 | i915_gem_object_save_bit_17_swizzle(obj); |
1890 | ||
05394f39 CW |
1891 | if (obj->madv == I915_MADV_DONTNEED) |
1892 | obj->dirty = 0; | |
3ef94daa | 1893 | |
90797e6d | 1894 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1895 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1896 | |
05394f39 | 1897 | if (obj->dirty) |
9da3da66 | 1898 | set_page_dirty(page); |
3ef94daa | 1899 | |
05394f39 | 1900 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1901 | mark_page_accessed(page); |
3ef94daa | 1902 | |
9da3da66 | 1903 | page_cache_release(page); |
3ef94daa | 1904 | } |
05394f39 | 1905 | obj->dirty = 0; |
673a394b | 1906 | |
9da3da66 CW |
1907 | sg_free_table(obj->pages); |
1908 | kfree(obj->pages); | |
37e680a1 | 1909 | } |
6c085a72 | 1910 | |
dd624afd | 1911 | int |
37e680a1 CW |
1912 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1913 | { | |
1914 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1915 | ||
2f745ad3 | 1916 | if (obj->pages == NULL) |
37e680a1 CW |
1917 | return 0; |
1918 | ||
a5570178 CW |
1919 | if (obj->pages_pin_count) |
1920 | return -EBUSY; | |
1921 | ||
9843877d | 1922 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1923 | |
a2165e31 CW |
1924 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1925 | * array, hence protect them from being reaped by removing them from gtt | |
1926 | * lists early. */ | |
35c20a60 | 1927 | list_del(&obj->global_list); |
a2165e31 | 1928 | |
37e680a1 | 1929 | ops->put_pages(obj); |
05394f39 | 1930 | obj->pages = NULL; |
37e680a1 | 1931 | |
5537252b | 1932 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
1933 | |
1934 | return 0; | |
1935 | } | |
1936 | ||
d9973b43 | 1937 | static unsigned long |
93927ca5 DV |
1938 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1939 | bool purgeable_only) | |
6c085a72 | 1940 | { |
c8725f3d CW |
1941 | struct list_head still_in_list; |
1942 | struct drm_i915_gem_object *obj; | |
d9973b43 | 1943 | unsigned long count = 0; |
6c085a72 | 1944 | |
57094f82 | 1945 | /* |
c8725f3d | 1946 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
1947 | * (due to retiring requests) we have to strictly process only |
1948 | * one element of the list at the time, and recheck the list | |
1949 | * on every iteration. | |
c8725f3d CW |
1950 | * |
1951 | * In particular, we must hold a reference whilst removing the | |
1952 | * object as we may end up waiting for and/or retiring the objects. | |
1953 | * This might release the final reference (held by the active list) | |
1954 | * and result in the object being freed from under us. This is | |
1955 | * similar to the precautions the eviction code must take whilst | |
1956 | * removing objects. | |
1957 | * | |
1958 | * Also note that although these lists do not hold a reference to | |
1959 | * the object we can safely grab one here: The final object | |
1960 | * unreferencing and the bound_list are both protected by the | |
1961 | * dev->struct_mutex and so we won't ever be able to observe an | |
1962 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 1963 | */ |
c8725f3d CW |
1964 | INIT_LIST_HEAD(&still_in_list); |
1965 | while (count < target && !list_empty(&dev_priv->mm.unbound_list)) { | |
1966 | obj = list_first_entry(&dev_priv->mm.unbound_list, | |
1967 | typeof(*obj), global_list); | |
1968 | list_move_tail(&obj->global_list, &still_in_list); | |
1969 | ||
1970 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) | |
1971 | continue; | |
1972 | ||
1973 | drm_gem_object_reference(&obj->base); | |
1974 | ||
1975 | if (i915_gem_object_put_pages(obj) == 0) | |
1976 | count += obj->base.size >> PAGE_SHIFT; | |
1977 | ||
1978 | drm_gem_object_unreference(&obj->base); | |
1979 | } | |
1980 | list_splice(&still_in_list, &dev_priv->mm.unbound_list); | |
1981 | ||
1982 | INIT_LIST_HEAD(&still_in_list); | |
57094f82 | 1983 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { |
07fe0b12 | 1984 | struct i915_vma *vma, *v; |
80dcfdbd | 1985 | |
57094f82 CW |
1986 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1987 | typeof(*obj), global_list); | |
c8725f3d | 1988 | list_move_tail(&obj->global_list, &still_in_list); |
57094f82 | 1989 | |
80dcfdbd BW |
1990 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1991 | continue; | |
1992 | ||
57094f82 CW |
1993 | drm_gem_object_reference(&obj->base); |
1994 | ||
07fe0b12 BW |
1995 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1996 | if (i915_vma_unbind(vma)) | |
1997 | break; | |
80dcfdbd | 1998 | |
57094f82 | 1999 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 2000 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
2001 | |
2002 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 2003 | } |
c8725f3d | 2004 | list_splice(&still_in_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
2005 | |
2006 | return count; | |
2007 | } | |
2008 | ||
d9973b43 | 2009 | static unsigned long |
93927ca5 DV |
2010 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
2011 | { | |
2012 | return __i915_gem_shrink(dev_priv, target, true); | |
2013 | } | |
2014 | ||
d9973b43 | 2015 | static unsigned long |
6c085a72 CW |
2016 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
2017 | { | |
6c085a72 | 2018 | i915_gem_evict_everything(dev_priv->dev); |
c8725f3d | 2019 | return __i915_gem_shrink(dev_priv, LONG_MAX, false); |
225067ee DV |
2020 | } |
2021 | ||
37e680a1 | 2022 | static int |
6c085a72 | 2023 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2024 | { |
6c085a72 | 2025 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2026 | int page_count, i; |
2027 | struct address_space *mapping; | |
9da3da66 CW |
2028 | struct sg_table *st; |
2029 | struct scatterlist *sg; | |
90797e6d | 2030 | struct sg_page_iter sg_iter; |
e5281ccd | 2031 | struct page *page; |
90797e6d | 2032 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2033 | gfp_t gfp; |
e5281ccd | 2034 | |
6c085a72 CW |
2035 | /* Assert that the object is not currently in any GPU domain. As it |
2036 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2037 | * a GPU cache | |
2038 | */ | |
2039 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2040 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2041 | ||
9da3da66 CW |
2042 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2043 | if (st == NULL) | |
2044 | return -ENOMEM; | |
2045 | ||
05394f39 | 2046 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2047 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2048 | kfree(st); |
e5281ccd | 2049 | return -ENOMEM; |
9da3da66 | 2050 | } |
e5281ccd | 2051 | |
9da3da66 CW |
2052 | /* Get the list of pages out of our struct file. They'll be pinned |
2053 | * at this point until we release them. | |
2054 | * | |
2055 | * Fail silently without starting the shrinker | |
2056 | */ | |
496ad9aa | 2057 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2058 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2059 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2060 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2061 | sg = st->sgl; |
2062 | st->nents = 0; | |
2063 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2064 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2065 | if (IS_ERR(page)) { | |
2066 | i915_gem_purge(dev_priv, page_count); | |
2067 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
2068 | } | |
2069 | if (IS_ERR(page)) { | |
2070 | /* We've tried hard to allocate the memory by reaping | |
2071 | * our own buffer, now let the real VM do its job and | |
2072 | * go down in flames if truly OOM. | |
2073 | */ | |
6c085a72 | 2074 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2075 | page = shmem_read_mapping_page(mapping, i); |
6c085a72 CW |
2076 | if (IS_ERR(page)) |
2077 | goto err_pages; | |
6c085a72 | 2078 | } |
426729dc KRW |
2079 | #ifdef CONFIG_SWIOTLB |
2080 | if (swiotlb_nr_tbl()) { | |
2081 | st->nents++; | |
2082 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2083 | sg = sg_next(sg); | |
2084 | continue; | |
2085 | } | |
2086 | #endif | |
90797e6d ID |
2087 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2088 | if (i) | |
2089 | sg = sg_next(sg); | |
2090 | st->nents++; | |
2091 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2092 | } else { | |
2093 | sg->length += PAGE_SIZE; | |
2094 | } | |
2095 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2096 | |
2097 | /* Check that the i965g/gm workaround works. */ | |
2098 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2099 | } |
426729dc KRW |
2100 | #ifdef CONFIG_SWIOTLB |
2101 | if (!swiotlb_nr_tbl()) | |
2102 | #endif | |
2103 | sg_mark_end(sg); | |
74ce6b6c CW |
2104 | obj->pages = st; |
2105 | ||
6dacfd2f | 2106 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2107 | i915_gem_object_do_bit_17_swizzle(obj); |
2108 | ||
2109 | return 0; | |
2110 | ||
2111 | err_pages: | |
90797e6d ID |
2112 | sg_mark_end(sg); |
2113 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2114 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2115 | sg_free_table(st); |
2116 | kfree(st); | |
0820baf3 CW |
2117 | |
2118 | /* shmemfs first checks if there is enough memory to allocate the page | |
2119 | * and reports ENOSPC should there be insufficient, along with the usual | |
2120 | * ENOMEM for a genuine allocation failure. | |
2121 | * | |
2122 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2123 | * space and so want to translate the error from shmemfs back to our | |
2124 | * usual understanding of ENOMEM. | |
2125 | */ | |
2126 | if (PTR_ERR(page) == -ENOSPC) | |
2127 | return -ENOMEM; | |
2128 | else | |
2129 | return PTR_ERR(page); | |
673a394b EA |
2130 | } |
2131 | ||
37e680a1 CW |
2132 | /* Ensure that the associated pages are gathered from the backing storage |
2133 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2134 | * multiple times before they are released by a single call to | |
2135 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2136 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2137 | * or as the object is itself released. | |
2138 | */ | |
2139 | int | |
2140 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2141 | { | |
2142 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2143 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2144 | int ret; | |
2145 | ||
2f745ad3 | 2146 | if (obj->pages) |
37e680a1 CW |
2147 | return 0; |
2148 | ||
43e28f09 | 2149 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2150 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2151 | return -EFAULT; |
43e28f09 CW |
2152 | } |
2153 | ||
a5570178 CW |
2154 | BUG_ON(obj->pages_pin_count); |
2155 | ||
37e680a1 CW |
2156 | ret = ops->get_pages(obj); |
2157 | if (ret) | |
2158 | return ret; | |
2159 | ||
35c20a60 | 2160 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2161 | return 0; |
673a394b EA |
2162 | } |
2163 | ||
e2d05a8b | 2164 | static void |
05394f39 | 2165 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2166 | struct intel_engine_cs *ring) |
673a394b | 2167 | { |
05394f39 | 2168 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 2169 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 2170 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 2171 | |
852835f3 | 2172 | BUG_ON(ring == NULL); |
02978ff5 CW |
2173 | if (obj->ring != ring && obj->last_write_seqno) { |
2174 | /* Keep the seqno relative to the current ring */ | |
2175 | obj->last_write_seqno = seqno; | |
2176 | } | |
05394f39 | 2177 | obj->ring = ring; |
673a394b EA |
2178 | |
2179 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2180 | if (!obj->active) { |
2181 | drm_gem_object_reference(&obj->base); | |
2182 | obj->active = 1; | |
673a394b | 2183 | } |
e35a41de | 2184 | |
05394f39 | 2185 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2186 | |
0201f1ec | 2187 | obj->last_read_seqno = seqno; |
caea7476 | 2188 | |
7dd49065 | 2189 | if (obj->fenced_gpu_access) { |
caea7476 | 2190 | obj->last_fenced_seqno = seqno; |
caea7476 | 2191 | |
7dd49065 CW |
2192 | /* Bump MRU to take account of the delayed flush */ |
2193 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2194 | struct drm_i915_fence_reg *reg; | |
2195 | ||
2196 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
2197 | list_move_tail(®->lru_list, | |
2198 | &dev_priv->mm.fence_list); | |
2199 | } | |
caea7476 CW |
2200 | } |
2201 | } | |
2202 | ||
e2d05a8b | 2203 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2204 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2205 | { |
2206 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2207 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2208 | } | |
2209 | ||
caea7476 | 2210 | static void |
caea7476 | 2211 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2212 | { |
ca191b13 | 2213 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2214 | struct i915_address_space *vm; |
2215 | struct i915_vma *vma; | |
ce44b0ea | 2216 | |
65ce3027 | 2217 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2218 | BUG_ON(!obj->active); |
caea7476 | 2219 | |
feb822cf BW |
2220 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2221 | vma = i915_gem_obj_to_vma(obj, vm); | |
2222 | if (vma && !list_empty(&vma->mm_list)) | |
2223 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2224 | } | |
caea7476 | 2225 | |
65ce3027 | 2226 | list_del_init(&obj->ring_list); |
caea7476 CW |
2227 | obj->ring = NULL; |
2228 | ||
65ce3027 CW |
2229 | obj->last_read_seqno = 0; |
2230 | obj->last_write_seqno = 0; | |
2231 | obj->base.write_domain = 0; | |
2232 | ||
2233 | obj->last_fenced_seqno = 0; | |
caea7476 | 2234 | obj->fenced_gpu_access = false; |
caea7476 CW |
2235 | |
2236 | obj->active = 0; | |
2237 | drm_gem_object_unreference(&obj->base); | |
2238 | ||
2239 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2240 | } |
673a394b | 2241 | |
c8725f3d CW |
2242 | static void |
2243 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2244 | { | |
a4872ba6 | 2245 | struct intel_engine_cs *ring = obj->ring; |
c8725f3d CW |
2246 | |
2247 | if (ring == NULL) | |
2248 | return; | |
2249 | ||
2250 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
2251 | obj->last_read_seqno)) | |
2252 | i915_gem_object_move_to_inactive(obj); | |
2253 | } | |
2254 | ||
9d773091 | 2255 | static int |
fca26bb4 | 2256 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2257 | { |
9d773091 | 2258 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2259 | struct intel_engine_cs *ring; |
9d773091 | 2260 | int ret, i, j; |
53d227f2 | 2261 | |
107f27a5 | 2262 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2263 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2264 | ret = intel_ring_idle(ring); |
2265 | if (ret) | |
2266 | return ret; | |
9d773091 | 2267 | } |
9d773091 | 2268 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2269 | |
2270 | /* Finally reset hw state */ | |
9d773091 | 2271 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2272 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2273 | |
ebc348b2 BW |
2274 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2275 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2276 | } |
53d227f2 | 2277 | |
9d773091 | 2278 | return 0; |
53d227f2 DV |
2279 | } |
2280 | ||
fca26bb4 MK |
2281 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2282 | { | |
2283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2284 | int ret; | |
2285 | ||
2286 | if (seqno == 0) | |
2287 | return -EINVAL; | |
2288 | ||
2289 | /* HWS page needs to be set less than what we | |
2290 | * will inject to ring | |
2291 | */ | |
2292 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2293 | if (ret) | |
2294 | return ret; | |
2295 | ||
2296 | /* Carefully set the last_seqno value so that wrap | |
2297 | * detection still works | |
2298 | */ | |
2299 | dev_priv->next_seqno = seqno; | |
2300 | dev_priv->last_seqno = seqno - 1; | |
2301 | if (dev_priv->last_seqno == 0) | |
2302 | dev_priv->last_seqno--; | |
2303 | ||
2304 | return 0; | |
2305 | } | |
2306 | ||
9d773091 CW |
2307 | int |
2308 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2309 | { |
9d773091 CW |
2310 | struct drm_i915_private *dev_priv = dev->dev_private; |
2311 | ||
2312 | /* reserve 0 for non-seqno */ | |
2313 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2314 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2315 | if (ret) |
2316 | return ret; | |
53d227f2 | 2317 | |
9d773091 CW |
2318 | dev_priv->next_seqno = 1; |
2319 | } | |
53d227f2 | 2320 | |
f72b3435 | 2321 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2322 | return 0; |
53d227f2 DV |
2323 | } |
2324 | ||
a4872ba6 | 2325 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2326 | struct drm_file *file, |
7d736f4f | 2327 | struct drm_i915_gem_object *obj, |
0025c077 | 2328 | u32 *out_seqno) |
673a394b | 2329 | { |
3e31c6c0 | 2330 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2331 | struct drm_i915_gem_request *request; |
7d736f4f | 2332 | u32 request_ring_position, request_start; |
3cce469c CW |
2333 | int ret; |
2334 | ||
7d736f4f | 2335 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2336 | /* |
2337 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2338 | * after having emitted the batchbuffer command. Hence we need to fix | |
2339 | * things up similar to emitting the lazy request. The difference here | |
2340 | * is that the flush _must_ happen before the next request, no matter | |
2341 | * what. | |
2342 | */ | |
a7b9761d CW |
2343 | ret = intel_ring_flush_all_caches(ring); |
2344 | if (ret) | |
2345 | return ret; | |
cc889e0f | 2346 | |
3c0e234c CW |
2347 | request = ring->preallocated_lazy_request; |
2348 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2349 | return -ENOMEM; |
cc889e0f | 2350 | |
a71d8d94 CW |
2351 | /* Record the position of the start of the request so that |
2352 | * should we detect the updated seqno part-way through the | |
2353 | * GPU processing the request, we never over-estimate the | |
2354 | * position of the head. | |
2355 | */ | |
2356 | request_ring_position = intel_ring_get_tail(ring); | |
2357 | ||
9d773091 | 2358 | ret = ring->add_request(ring); |
3c0e234c | 2359 | if (ret) |
3bb73aba | 2360 | return ret; |
673a394b | 2361 | |
9d773091 | 2362 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2363 | request->ring = ring; |
7d736f4f | 2364 | request->head = request_start; |
a71d8d94 | 2365 | request->tail = request_ring_position; |
7d736f4f MK |
2366 | |
2367 | /* Whilst this request exists, batch_obj will be on the | |
2368 | * active_list, and so will hold the active reference. Only when this | |
2369 | * request is retired will the the batch_obj be moved onto the | |
2370 | * inactive_list and lose its active reference. Hence we do not need | |
2371 | * to explicitly hold another reference here. | |
2372 | */ | |
9a7e0c2a | 2373 | request->batch_obj = obj; |
0e50e96b | 2374 | |
9a7e0c2a CW |
2375 | /* Hold a reference to the current context so that we can inspect |
2376 | * it later in case a hangcheck error event fires. | |
2377 | */ | |
2378 | request->ctx = ring->last_context; | |
0e50e96b MK |
2379 | if (request->ctx) |
2380 | i915_gem_context_reference(request->ctx); | |
2381 | ||
673a394b | 2382 | request->emitted_jiffies = jiffies; |
852835f3 | 2383 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2384 | request->file_priv = NULL; |
852835f3 | 2385 | |
db53a302 CW |
2386 | if (file) { |
2387 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2388 | ||
1c25595f | 2389 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2390 | request->file_priv = file_priv; |
b962442e | 2391 | list_add_tail(&request->client_list, |
f787a5f5 | 2392 | &file_priv->mm.request_list); |
1c25595f | 2393 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2394 | } |
673a394b | 2395 | |
9d773091 | 2396 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2397 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2398 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2399 | |
db1b76ca | 2400 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2401 | i915_queue_hangcheck(ring->dev); |
2402 | ||
f62a0076 CW |
2403 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2404 | queue_delayed_work(dev_priv->wq, | |
2405 | &dev_priv->mm.retire_work, | |
2406 | round_jiffies_up_relative(HZ)); | |
2407 | intel_mark_busy(dev_priv->dev); | |
f65d9421 | 2408 | } |
cc889e0f | 2409 | |
acb868d3 | 2410 | if (out_seqno) |
9d773091 | 2411 | *out_seqno = request->seqno; |
3cce469c | 2412 | return 0; |
673a394b EA |
2413 | } |
2414 | ||
f787a5f5 CW |
2415 | static inline void |
2416 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2417 | { |
1c25595f | 2418 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2419 | |
1c25595f CW |
2420 | if (!file_priv) |
2421 | return; | |
1c5d22f7 | 2422 | |
1c25595f | 2423 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2424 | list_del(&request->client_list); |
2425 | request->file_priv = NULL; | |
1c25595f | 2426 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2427 | } |
673a394b | 2428 | |
939fd762 | 2429 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2430 | const struct intel_context *ctx) |
be62acb4 | 2431 | { |
44e2c070 | 2432 | unsigned long elapsed; |
be62acb4 | 2433 | |
44e2c070 MK |
2434 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2435 | ||
2436 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2437 | return true; |
2438 | ||
2439 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2440 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2441 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2442 | return true; |
88b4aa87 MK |
2443 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2444 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2445 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2446 | return true; |
3fac8978 | 2447 | } |
be62acb4 MK |
2448 | } |
2449 | ||
2450 | return false; | |
2451 | } | |
2452 | ||
939fd762 | 2453 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2454 | struct intel_context *ctx, |
b6b0fac0 | 2455 | const bool guilty) |
aa60c664 | 2456 | { |
44e2c070 MK |
2457 | struct i915_ctx_hang_stats *hs; |
2458 | ||
2459 | if (WARN_ON(!ctx)) | |
2460 | return; | |
aa60c664 | 2461 | |
44e2c070 MK |
2462 | hs = &ctx->hang_stats; |
2463 | ||
2464 | if (guilty) { | |
939fd762 | 2465 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2466 | hs->batch_active++; |
2467 | hs->guilty_ts = get_seconds(); | |
2468 | } else { | |
2469 | hs->batch_pending++; | |
aa60c664 MK |
2470 | } |
2471 | } | |
2472 | ||
0e50e96b MK |
2473 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2474 | { | |
2475 | list_del(&request->list); | |
2476 | i915_gem_request_remove_from_client(request); | |
2477 | ||
2478 | if (request->ctx) | |
2479 | i915_gem_context_unreference(request->ctx); | |
2480 | ||
2481 | kfree(request); | |
2482 | } | |
2483 | ||
8d9fc7fd | 2484 | struct drm_i915_gem_request * |
a4872ba6 | 2485 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2486 | { |
4db080f9 | 2487 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2488 | u32 completed_seqno; |
2489 | ||
2490 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2491 | |
2492 | list_for_each_entry(request, &ring->request_list, list) { | |
2493 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2494 | continue; | |
aa60c664 | 2495 | |
b6b0fac0 | 2496 | return request; |
4db080f9 | 2497 | } |
b6b0fac0 MK |
2498 | |
2499 | return NULL; | |
2500 | } | |
2501 | ||
2502 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2503 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2504 | { |
2505 | struct drm_i915_gem_request *request; | |
2506 | bool ring_hung; | |
2507 | ||
8d9fc7fd | 2508 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2509 | |
2510 | if (request == NULL) | |
2511 | return; | |
2512 | ||
2513 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2514 | ||
939fd762 | 2515 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2516 | |
2517 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2518 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2519 | } |
aa60c664 | 2520 | |
4db080f9 | 2521 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2522 | struct intel_engine_cs *ring) |
4db080f9 | 2523 | { |
dfaae392 | 2524 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2525 | struct drm_i915_gem_object *obj; |
9375e446 | 2526 | |
05394f39 CW |
2527 | obj = list_first_entry(&ring->active_list, |
2528 | struct drm_i915_gem_object, | |
2529 | ring_list); | |
9375e446 | 2530 | |
05394f39 | 2531 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2532 | } |
1d62beea BW |
2533 | |
2534 | /* | |
2535 | * We must free the requests after all the corresponding objects have | |
2536 | * been moved off active lists. Which is the same order as the normal | |
2537 | * retire_requests function does. This is important if object hold | |
2538 | * implicit references on things like e.g. ppgtt address spaces through | |
2539 | * the request. | |
2540 | */ | |
2541 | while (!list_empty(&ring->request_list)) { | |
2542 | struct drm_i915_gem_request *request; | |
2543 | ||
2544 | request = list_first_entry(&ring->request_list, | |
2545 | struct drm_i915_gem_request, | |
2546 | list); | |
2547 | ||
2548 | i915_gem_free_request(request); | |
2549 | } | |
e3efda49 CW |
2550 | |
2551 | /* These may not have been flush before the reset, do so now */ | |
2552 | kfree(ring->preallocated_lazy_request); | |
2553 | ring->preallocated_lazy_request = NULL; | |
2554 | ring->outstanding_lazy_seqno = 0; | |
673a394b EA |
2555 | } |
2556 | ||
19b2dbde | 2557 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2558 | { |
2559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2560 | int i; | |
2561 | ||
4b9de737 | 2562 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2563 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2564 | |
94a335db DV |
2565 | /* |
2566 | * Commit delayed tiling changes if we have an object still | |
2567 | * attached to the fence, otherwise just clear the fence. | |
2568 | */ | |
2569 | if (reg->obj) { | |
2570 | i915_gem_object_update_fence(reg->obj, reg, | |
2571 | reg->obj->tiling_mode); | |
2572 | } else { | |
2573 | i915_gem_write_fence(dev, i, NULL); | |
2574 | } | |
312817a3 CW |
2575 | } |
2576 | } | |
2577 | ||
069efc1d | 2578 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2579 | { |
77f01230 | 2580 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2581 | struct intel_engine_cs *ring; |
1ec14ad3 | 2582 | int i; |
673a394b | 2583 | |
4db080f9 CW |
2584 | /* |
2585 | * Before we free the objects from the requests, we need to inspect | |
2586 | * them for finding the guilty party. As the requests only borrow | |
2587 | * their reference to the objects, the inspection must be done first. | |
2588 | */ | |
2589 | for_each_ring(ring, dev_priv, i) | |
2590 | i915_gem_reset_ring_status(dev_priv, ring); | |
2591 | ||
b4519513 | 2592 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2593 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2594 | |
acce9ffa BW |
2595 | i915_gem_context_reset(dev); |
2596 | ||
19b2dbde | 2597 | i915_gem_restore_fences(dev); |
673a394b EA |
2598 | } |
2599 | ||
2600 | /** | |
2601 | * This function clears the request list as sequence numbers are passed. | |
2602 | */ | |
1cf0ba14 | 2603 | void |
a4872ba6 | 2604 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2605 | { |
673a394b EA |
2606 | uint32_t seqno; |
2607 | ||
db53a302 | 2608 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2609 | return; |
2610 | ||
db53a302 | 2611 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2612 | |
b2eadbc8 | 2613 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2614 | |
e9103038 CW |
2615 | /* Move any buffers on the active list that are no longer referenced |
2616 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2617 | * before we free the context associated with the requests. | |
2618 | */ | |
2619 | while (!list_empty(&ring->active_list)) { | |
2620 | struct drm_i915_gem_object *obj; | |
2621 | ||
2622 | obj = list_first_entry(&ring->active_list, | |
2623 | struct drm_i915_gem_object, | |
2624 | ring_list); | |
2625 | ||
2626 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) | |
2627 | break; | |
2628 | ||
2629 | i915_gem_object_move_to_inactive(obj); | |
2630 | } | |
2631 | ||
2632 | ||
852835f3 | 2633 | while (!list_empty(&ring->request_list)) { |
673a394b | 2634 | struct drm_i915_gem_request *request; |
673a394b | 2635 | |
852835f3 | 2636 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2637 | struct drm_i915_gem_request, |
2638 | list); | |
673a394b | 2639 | |
dfaae392 | 2640 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2641 | break; |
2642 | ||
db53a302 | 2643 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2644 | /* We know the GPU must have read the request to have |
2645 | * sent us the seqno + interrupt, so use the position | |
2646 | * of tail of the request to update the last known position | |
2647 | * of the GPU head. | |
2648 | */ | |
ee1b1e5e | 2649 | ring->buffer->last_retired_head = request->tail; |
b84d5f0c | 2650 | |
0e50e96b | 2651 | i915_gem_free_request(request); |
b84d5f0c | 2652 | } |
673a394b | 2653 | |
db53a302 CW |
2654 | if (unlikely(ring->trace_irq_seqno && |
2655 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2656 | ring->irq_put(ring); |
db53a302 | 2657 | ring->trace_irq_seqno = 0; |
9d34e5db | 2658 | } |
23bc5982 | 2659 | |
db53a302 | 2660 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2661 | } |
2662 | ||
b29c19b6 | 2663 | bool |
b09a1fec CW |
2664 | i915_gem_retire_requests(struct drm_device *dev) |
2665 | { | |
3e31c6c0 | 2666 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2667 | struct intel_engine_cs *ring; |
b29c19b6 | 2668 | bool idle = true; |
1ec14ad3 | 2669 | int i; |
b09a1fec | 2670 | |
b29c19b6 | 2671 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2672 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2673 | idle &= list_empty(&ring->request_list); |
2674 | } | |
2675 | ||
2676 | if (idle) | |
2677 | mod_delayed_work(dev_priv->wq, | |
2678 | &dev_priv->mm.idle_work, | |
2679 | msecs_to_jiffies(100)); | |
2680 | ||
2681 | return idle; | |
b09a1fec CW |
2682 | } |
2683 | ||
75ef9da2 | 2684 | static void |
673a394b EA |
2685 | i915_gem_retire_work_handler(struct work_struct *work) |
2686 | { | |
b29c19b6 CW |
2687 | struct drm_i915_private *dev_priv = |
2688 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2689 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2690 | bool idle; |
673a394b | 2691 | |
891b48cf | 2692 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2693 | idle = false; |
2694 | if (mutex_trylock(&dev->struct_mutex)) { | |
2695 | idle = i915_gem_retire_requests(dev); | |
2696 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2697 | } |
b29c19b6 | 2698 | if (!idle) |
bcb45086 CW |
2699 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2700 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2701 | } |
0a58705b | 2702 | |
b29c19b6 CW |
2703 | static void |
2704 | i915_gem_idle_work_handler(struct work_struct *work) | |
2705 | { | |
2706 | struct drm_i915_private *dev_priv = | |
2707 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2708 | ||
2709 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2710 | } |
2711 | ||
30dfebf3 DV |
2712 | /** |
2713 | * Ensures that an object will eventually get non-busy by flushing any required | |
2714 | * write domains, emitting any outstanding lazy request and retiring and | |
2715 | * completed requests. | |
2716 | */ | |
2717 | static int | |
2718 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2719 | { | |
2720 | int ret; | |
2721 | ||
2722 | if (obj->active) { | |
0201f1ec | 2723 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2724 | if (ret) |
2725 | return ret; | |
2726 | ||
30dfebf3 DV |
2727 | i915_gem_retire_requests_ring(obj->ring); |
2728 | } | |
2729 | ||
2730 | return 0; | |
2731 | } | |
2732 | ||
23ba4fd0 BW |
2733 | /** |
2734 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2735 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2736 | * | |
2737 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2738 | * the timeout parameter. | |
2739 | * -ETIME: object is still busy after timeout | |
2740 | * -ERESTARTSYS: signal interrupted the wait | |
2741 | * -ENONENT: object doesn't exist | |
2742 | * Also possible, but rare: | |
2743 | * -EAGAIN: GPU wedged | |
2744 | * -ENOMEM: damn | |
2745 | * -ENODEV: Internal IRQ fail | |
2746 | * -E?: The add request failed | |
2747 | * | |
2748 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2749 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2750 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2751 | * without holding struct_mutex the object may become re-busied before this | |
2752 | * function completes. A similar but shorter * race condition exists in the busy | |
2753 | * ioctl | |
2754 | */ | |
2755 | int | |
2756 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2757 | { | |
3e31c6c0 | 2758 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2759 | struct drm_i915_gem_wait *args = data; |
2760 | struct drm_i915_gem_object *obj; | |
a4872ba6 | 2761 | struct intel_engine_cs *ring = NULL; |
eac1f14f | 2762 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2763 | unsigned reset_counter; |
23ba4fd0 BW |
2764 | u32 seqno = 0; |
2765 | int ret = 0; | |
2766 | ||
eac1f14f BW |
2767 | if (args->timeout_ns >= 0) { |
2768 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2769 | timeout = &timeout_stack; | |
2770 | } | |
23ba4fd0 BW |
2771 | |
2772 | ret = i915_mutex_lock_interruptible(dev); | |
2773 | if (ret) | |
2774 | return ret; | |
2775 | ||
2776 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2777 | if (&obj->base == NULL) { | |
2778 | mutex_unlock(&dev->struct_mutex); | |
2779 | return -ENOENT; | |
2780 | } | |
2781 | ||
30dfebf3 DV |
2782 | /* Need to make sure the object gets inactive eventually. */ |
2783 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2784 | if (ret) |
2785 | goto out; | |
2786 | ||
2787 | if (obj->active) { | |
0201f1ec | 2788 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2789 | ring = obj->ring; |
2790 | } | |
2791 | ||
2792 | if (seqno == 0) | |
2793 | goto out; | |
2794 | ||
23ba4fd0 BW |
2795 | /* Do this after OLR check to make sure we make forward progress polling |
2796 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2797 | */ | |
2798 | if (!args->timeout_ns) { | |
2799 | ret = -ETIME; | |
2800 | goto out; | |
2801 | } | |
2802 | ||
2803 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2804 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2805 | mutex_unlock(&dev->struct_mutex); |
2806 | ||
b29c19b6 | 2807 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2808 | if (timeout) |
eac1f14f | 2809 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2810 | return ret; |
2811 | ||
2812 | out: | |
2813 | drm_gem_object_unreference(&obj->base); | |
2814 | mutex_unlock(&dev->struct_mutex); | |
2815 | return ret; | |
2816 | } | |
2817 | ||
5816d648 BW |
2818 | /** |
2819 | * i915_gem_object_sync - sync an object to a ring. | |
2820 | * | |
2821 | * @obj: object which may be in use on another ring. | |
2822 | * @to: ring we wish to use the object on. May be NULL. | |
2823 | * | |
2824 | * This code is meant to abstract object synchronization with the GPU. | |
2825 | * Calling with NULL implies synchronizing the object with the CPU | |
2826 | * rather than a particular GPU ring. | |
2827 | * | |
2828 | * Returns 0 if successful, else propagates up the lower layer error. | |
2829 | */ | |
2911a35b BW |
2830 | int |
2831 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2832 | struct intel_engine_cs *to) |
2911a35b | 2833 | { |
a4872ba6 | 2834 | struct intel_engine_cs *from = obj->ring; |
2911a35b BW |
2835 | u32 seqno; |
2836 | int ret, idx; | |
2837 | ||
2838 | if (from == NULL || to == from) | |
2839 | return 0; | |
2840 | ||
5816d648 | 2841 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2842 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2843 | |
2844 | idx = intel_ring_sync_index(from, to); | |
2845 | ||
0201f1ec | 2846 | seqno = obj->last_read_seqno; |
ebc348b2 | 2847 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2848 | return 0; |
2849 | ||
b4aca010 BW |
2850 | ret = i915_gem_check_olr(obj->ring, seqno); |
2851 | if (ret) | |
2852 | return ret; | |
2911a35b | 2853 | |
b52b89da | 2854 | trace_i915_gem_ring_sync_to(from, to, seqno); |
ebc348b2 | 2855 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 2856 | if (!ret) |
7b01e260 MK |
2857 | /* We use last_read_seqno because sync_to() |
2858 | * might have just caused seqno wrap under | |
2859 | * the radar. | |
2860 | */ | |
ebc348b2 | 2861 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
2911a35b | 2862 | |
e3a5a225 | 2863 | return ret; |
2911a35b BW |
2864 | } |
2865 | ||
b5ffc9bc CW |
2866 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2867 | { | |
2868 | u32 old_write_domain, old_read_domains; | |
2869 | ||
b5ffc9bc CW |
2870 | /* Force a pagefault for domain tracking on next user access */ |
2871 | i915_gem_release_mmap(obj); | |
2872 | ||
b97c3d9c KP |
2873 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2874 | return; | |
2875 | ||
97c809fd CW |
2876 | /* Wait for any direct GTT access to complete */ |
2877 | mb(); | |
2878 | ||
b5ffc9bc CW |
2879 | old_read_domains = obj->base.read_domains; |
2880 | old_write_domain = obj->base.write_domain; | |
2881 | ||
2882 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2883 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2884 | ||
2885 | trace_i915_gem_object_change_domain(obj, | |
2886 | old_read_domains, | |
2887 | old_write_domain); | |
2888 | } | |
2889 | ||
07fe0b12 | 2890 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2891 | { |
07fe0b12 | 2892 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 2893 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2894 | int ret; |
673a394b | 2895 | |
07fe0b12 | 2896 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2897 | return 0; |
2898 | ||
0ff501cb DV |
2899 | if (!drm_mm_node_allocated(&vma->node)) { |
2900 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
2901 | return 0; |
2902 | } | |
433544bd | 2903 | |
d7f46fc4 | 2904 | if (vma->pin_count) |
31d8d651 | 2905 | return -EBUSY; |
673a394b | 2906 | |
c4670ad0 CW |
2907 | BUG_ON(obj->pages == NULL); |
2908 | ||
a8198eea | 2909 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2910 | if (ret) |
a8198eea CW |
2911 | return ret; |
2912 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2913 | * should be safe and we need to cleanup or else we might | |
2914 | * cause memory corruption through use-after-free. | |
2915 | */ | |
2916 | ||
8b1bc9b4 DV |
2917 | if (i915_is_ggtt(vma->vm)) { |
2918 | i915_gem_object_finish_gtt(obj); | |
5323fd04 | 2919 | |
8b1bc9b4 DV |
2920 | /* release the fence reg _after_ flushing */ |
2921 | ret = i915_gem_object_put_fence(obj); | |
2922 | if (ret) | |
2923 | return ret; | |
2924 | } | |
96b47b65 | 2925 | |
07fe0b12 | 2926 | trace_i915_vma_unbind(vma); |
db53a302 | 2927 | |
6f65e29a BW |
2928 | vma->unbind_vma(vma); |
2929 | ||
74163907 | 2930 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2931 | |
64bf9303 | 2932 | list_del_init(&vma->mm_list); |
75e9e915 | 2933 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2934 | if (i915_is_ggtt(vma->vm)) |
2935 | obj->map_and_fenceable = true; | |
673a394b | 2936 | |
2f633156 BW |
2937 | drm_mm_remove_node(&vma->node); |
2938 | i915_gem_vma_destroy(vma); | |
2939 | ||
2940 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2941 | * no more VMAs exist. */ |
2f633156 BW |
2942 | if (list_empty(&obj->vma_list)) |
2943 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2944 | |
70903c3b CW |
2945 | /* And finally now the object is completely decoupled from this vma, |
2946 | * we can drop its hold on the backing storage and allow it to be | |
2947 | * reaped by the shrinker. | |
2948 | */ | |
2949 | i915_gem_object_unpin_pages(obj); | |
2950 | ||
88241785 | 2951 | return 0; |
54cf91dc CW |
2952 | } |
2953 | ||
b2da9fe5 | 2954 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 2955 | { |
3e31c6c0 | 2956 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2957 | struct intel_engine_cs *ring; |
1ec14ad3 | 2958 | int ret, i; |
4df2faf4 | 2959 | |
4df2faf4 | 2960 | /* Flush everything onto the inactive list. */ |
b4519513 | 2961 | for_each_ring(ring, dev_priv, i) { |
691e6415 | 2962 | ret = i915_switch_context(ring, ring->default_context); |
b6c7488d BW |
2963 | if (ret) |
2964 | return ret; | |
2965 | ||
3e960501 | 2966 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2967 | if (ret) |
2968 | return ret; | |
2969 | } | |
4df2faf4 | 2970 | |
8a1a49f9 | 2971 | return 0; |
4df2faf4 DV |
2972 | } |
2973 | ||
9ce079e4 CW |
2974 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2975 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2976 | { |
3e31c6c0 | 2977 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
2978 | int fence_reg; |
2979 | int fence_pitch_shift; | |
de151cf6 | 2980 | |
56c844e5 ID |
2981 | if (INTEL_INFO(dev)->gen >= 6) { |
2982 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2983 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2984 | } else { | |
2985 | fence_reg = FENCE_REG_965_0; | |
2986 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2987 | } | |
2988 | ||
d18b9619 CW |
2989 | fence_reg += reg * 8; |
2990 | ||
2991 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2992 | * we split the 64-bit update into two 32-bit writes. In order | |
2993 | * for a partial fence not to be evaluated between writes, we | |
2994 | * precede the update with write to turn off the fence register, | |
2995 | * and only enable the fence as the last step. | |
2996 | * | |
2997 | * For extra levels of paranoia, we make sure each step lands | |
2998 | * before applying the next step. | |
2999 | */ | |
3000 | I915_WRITE(fence_reg, 0); | |
3001 | POSTING_READ(fence_reg); | |
3002 | ||
9ce079e4 | 3003 | if (obj) { |
f343c5f6 | 3004 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 3005 | uint64_t val; |
de151cf6 | 3006 | |
f343c5f6 | 3007 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3008 | 0xfffff000) << 32; |
f343c5f6 | 3009 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3010 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3011 | if (obj->tiling_mode == I915_TILING_Y) |
3012 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3013 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3014 | |
d18b9619 CW |
3015 | I915_WRITE(fence_reg + 4, val >> 32); |
3016 | POSTING_READ(fence_reg + 4); | |
3017 | ||
3018 | I915_WRITE(fence_reg + 0, val); | |
3019 | POSTING_READ(fence_reg); | |
3020 | } else { | |
3021 | I915_WRITE(fence_reg + 4, 0); | |
3022 | POSTING_READ(fence_reg + 4); | |
3023 | } | |
de151cf6 JB |
3024 | } |
3025 | ||
9ce079e4 CW |
3026 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3027 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3028 | { |
3e31c6c0 | 3029 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3030 | u32 val; |
de151cf6 | 3031 | |
9ce079e4 | 3032 | if (obj) { |
f343c5f6 | 3033 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3034 | int pitch_val; |
3035 | int tile_width; | |
c6642782 | 3036 | |
f343c5f6 | 3037 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3038 | (size & -size) != size || |
f343c5f6 BW |
3039 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3040 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3041 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3042 | |
9ce079e4 CW |
3043 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3044 | tile_width = 128; | |
3045 | else | |
3046 | tile_width = 512; | |
3047 | ||
3048 | /* Note: pitch better be a power of two tile widths */ | |
3049 | pitch_val = obj->stride / tile_width; | |
3050 | pitch_val = ffs(pitch_val) - 1; | |
3051 | ||
f343c5f6 | 3052 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3053 | if (obj->tiling_mode == I915_TILING_Y) |
3054 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3055 | val |= I915_FENCE_SIZE_BITS(size); | |
3056 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3057 | val |= I830_FENCE_REG_VALID; | |
3058 | } else | |
3059 | val = 0; | |
3060 | ||
3061 | if (reg < 8) | |
3062 | reg = FENCE_REG_830_0 + reg * 4; | |
3063 | else | |
3064 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3065 | ||
3066 | I915_WRITE(reg, val); | |
3067 | POSTING_READ(reg); | |
de151cf6 JB |
3068 | } |
3069 | ||
9ce079e4 CW |
3070 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3071 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3072 | { |
3e31c6c0 | 3073 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3074 | uint32_t val; |
de151cf6 | 3075 | |
9ce079e4 | 3076 | if (obj) { |
f343c5f6 | 3077 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3078 | uint32_t pitch_val; |
de151cf6 | 3079 | |
f343c5f6 | 3080 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3081 | (size & -size) != size || |
f343c5f6 BW |
3082 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3083 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3084 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3085 | |
9ce079e4 CW |
3086 | pitch_val = obj->stride / 128; |
3087 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3088 | |
f343c5f6 | 3089 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3090 | if (obj->tiling_mode == I915_TILING_Y) |
3091 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3092 | val |= I830_FENCE_SIZE_BITS(size); | |
3093 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3094 | val |= I830_FENCE_REG_VALID; | |
3095 | } else | |
3096 | val = 0; | |
c6642782 | 3097 | |
9ce079e4 CW |
3098 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3099 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3100 | } | |
3101 | ||
d0a57789 CW |
3102 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3103 | { | |
3104 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3105 | } | |
3106 | ||
9ce079e4 CW |
3107 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3108 | struct drm_i915_gem_object *obj) | |
3109 | { | |
d0a57789 CW |
3110 | struct drm_i915_private *dev_priv = dev->dev_private; |
3111 | ||
3112 | /* Ensure that all CPU reads are completed before installing a fence | |
3113 | * and all writes before removing the fence. | |
3114 | */ | |
3115 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3116 | mb(); | |
3117 | ||
94a335db DV |
3118 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3119 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3120 | obj->stride, obj->tiling_mode); | |
3121 | ||
9ce079e4 | 3122 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 3123 | case 8: |
9ce079e4 | 3124 | case 7: |
56c844e5 | 3125 | case 6: |
9ce079e4 CW |
3126 | case 5: |
3127 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
3128 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
3129 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 3130 | default: BUG(); |
9ce079e4 | 3131 | } |
d0a57789 CW |
3132 | |
3133 | /* And similarly be paranoid that no direct access to this region | |
3134 | * is reordered to before the fence is installed. | |
3135 | */ | |
3136 | if (i915_gem_object_needs_mb(obj)) | |
3137 | mb(); | |
de151cf6 JB |
3138 | } |
3139 | ||
61050808 CW |
3140 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3141 | struct drm_i915_fence_reg *fence) | |
3142 | { | |
3143 | return fence - dev_priv->fence_regs; | |
3144 | } | |
3145 | ||
3146 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3147 | struct drm_i915_fence_reg *fence, | |
3148 | bool enable) | |
3149 | { | |
2dc8aae0 | 3150 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3151 | int reg = fence_number(dev_priv, fence); |
3152 | ||
3153 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3154 | |
3155 | if (enable) { | |
46a0b638 | 3156 | obj->fence_reg = reg; |
61050808 CW |
3157 | fence->obj = obj; |
3158 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3159 | } else { | |
3160 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3161 | fence->obj = NULL; | |
3162 | list_del_init(&fence->lru_list); | |
3163 | } | |
94a335db | 3164 | obj->fence_dirty = false; |
61050808 CW |
3165 | } |
3166 | ||
d9e86c0e | 3167 | static int |
d0a57789 | 3168 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3169 | { |
1c293ea3 | 3170 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3171 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3172 | if (ret) |
3173 | return ret; | |
d9e86c0e CW |
3174 | |
3175 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3176 | } |
3177 | ||
86d5bc37 | 3178 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3179 | return 0; |
3180 | } | |
3181 | ||
3182 | int | |
3183 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3184 | { | |
61050808 | 3185 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3186 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3187 | int ret; |
3188 | ||
d0a57789 | 3189 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3190 | if (ret) |
3191 | return ret; | |
3192 | ||
61050808 CW |
3193 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3194 | return 0; | |
d9e86c0e | 3195 | |
f9c513e9 CW |
3196 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3197 | ||
aff10b30 DV |
3198 | if (WARN_ON(fence->pin_count)) |
3199 | return -EBUSY; | |
3200 | ||
61050808 | 3201 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3202 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3203 | |
3204 | return 0; | |
3205 | } | |
3206 | ||
3207 | static struct drm_i915_fence_reg * | |
a360bb1a | 3208 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3209 | { |
ae3db24a | 3210 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3211 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3212 | int i; |
ae3db24a DV |
3213 | |
3214 | /* First try to find a free reg */ | |
d9e86c0e | 3215 | avail = NULL; |
ae3db24a DV |
3216 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3217 | reg = &dev_priv->fence_regs[i]; | |
3218 | if (!reg->obj) | |
d9e86c0e | 3219 | return reg; |
ae3db24a | 3220 | |
1690e1eb | 3221 | if (!reg->pin_count) |
d9e86c0e | 3222 | avail = reg; |
ae3db24a DV |
3223 | } |
3224 | ||
d9e86c0e | 3225 | if (avail == NULL) |
5dce5b93 | 3226 | goto deadlock; |
ae3db24a DV |
3227 | |
3228 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3229 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3230 | if (reg->pin_count) |
ae3db24a DV |
3231 | continue; |
3232 | ||
8fe301ad | 3233 | return reg; |
ae3db24a DV |
3234 | } |
3235 | ||
5dce5b93 CW |
3236 | deadlock: |
3237 | /* Wait for completion of pending flips which consume fences */ | |
3238 | if (intel_has_pending_fb_unpin(dev)) | |
3239 | return ERR_PTR(-EAGAIN); | |
3240 | ||
3241 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3242 | } |
3243 | ||
de151cf6 | 3244 | /** |
9a5a53b3 | 3245 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3246 | * @obj: object to map through a fence reg |
3247 | * | |
3248 | * When mapping objects through the GTT, userspace wants to be able to write | |
3249 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3250 | * This function walks the fence regs looking for a free one for @obj, |
3251 | * stealing one if it can't find any. | |
3252 | * | |
3253 | * It then sets up the reg based on the object's properties: address, pitch | |
3254 | * and tiling format. | |
9a5a53b3 CW |
3255 | * |
3256 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3257 | */ |
8c4b8c3f | 3258 | int |
06d98131 | 3259 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3260 | { |
05394f39 | 3261 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3262 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3263 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3264 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3265 | int ret; |
de151cf6 | 3266 | |
14415745 CW |
3267 | /* Have we updated the tiling parameters upon the object and so |
3268 | * will need to serialise the write to the associated fence register? | |
3269 | */ | |
5d82e3e6 | 3270 | if (obj->fence_dirty) { |
d0a57789 | 3271 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3272 | if (ret) |
3273 | return ret; | |
3274 | } | |
9a5a53b3 | 3275 | |
d9e86c0e | 3276 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3277 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3278 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3279 | if (!obj->fence_dirty) { |
14415745 CW |
3280 | list_move_tail(®->lru_list, |
3281 | &dev_priv->mm.fence_list); | |
3282 | return 0; | |
3283 | } | |
3284 | } else if (enable) { | |
3285 | reg = i915_find_fence_reg(dev); | |
5dce5b93 CW |
3286 | if (IS_ERR(reg)) |
3287 | return PTR_ERR(reg); | |
d9e86c0e | 3288 | |
14415745 CW |
3289 | if (reg->obj) { |
3290 | struct drm_i915_gem_object *old = reg->obj; | |
3291 | ||
d0a57789 | 3292 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3293 | if (ret) |
3294 | return ret; | |
3295 | ||
14415745 | 3296 | i915_gem_object_fence_lost(old); |
29c5a587 | 3297 | } |
14415745 | 3298 | } else |
a09ba7fa | 3299 | return 0; |
a09ba7fa | 3300 | |
14415745 | 3301 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3302 | |
9ce079e4 | 3303 | return 0; |
de151cf6 JB |
3304 | } |
3305 | ||
42d6ab48 CW |
3306 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3307 | struct drm_mm_node *gtt_space, | |
3308 | unsigned long cache_level) | |
3309 | { | |
3310 | struct drm_mm_node *other; | |
3311 | ||
3312 | /* On non-LLC machines we have to be careful when putting differing | |
3313 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3314 | * crossing memory domains and dying. |
42d6ab48 CW |
3315 | */ |
3316 | if (HAS_LLC(dev)) | |
3317 | return true; | |
3318 | ||
c6cfb325 | 3319 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3320 | return true; |
3321 | ||
3322 | if (list_empty(>t_space->node_list)) | |
3323 | return true; | |
3324 | ||
3325 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3326 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3327 | return false; | |
3328 | ||
3329 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3330 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3331 | return false; | |
3332 | ||
3333 | return true; | |
3334 | } | |
3335 | ||
3336 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3337 | { | |
3338 | #if WATCH_GTT | |
3339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3340 | struct drm_i915_gem_object *obj; | |
3341 | int err = 0; | |
3342 | ||
35c20a60 | 3343 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3344 | if (obj->gtt_space == NULL) { |
3345 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3346 | err++; | |
3347 | continue; | |
3348 | } | |
3349 | ||
3350 | if (obj->cache_level != obj->gtt_space->color) { | |
3351 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3352 | i915_gem_obj_ggtt_offset(obj), |
3353 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3354 | obj->cache_level, |
3355 | obj->gtt_space->color); | |
3356 | err++; | |
3357 | continue; | |
3358 | } | |
3359 | ||
3360 | if (!i915_gem_valid_gtt_space(dev, | |
3361 | obj->gtt_space, | |
3362 | obj->cache_level)) { | |
3363 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3364 | i915_gem_obj_ggtt_offset(obj), |
3365 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3366 | obj->cache_level); |
3367 | err++; | |
3368 | continue; | |
3369 | } | |
3370 | } | |
3371 | ||
3372 | WARN_ON(err); | |
3373 | #endif | |
3374 | } | |
3375 | ||
673a394b EA |
3376 | /** |
3377 | * Finds free space in the GTT aperture and binds the object there. | |
3378 | */ | |
262de145 | 3379 | static struct i915_vma * |
07fe0b12 BW |
3380 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3381 | struct i915_address_space *vm, | |
3382 | unsigned alignment, | |
d23db88c | 3383 | uint64_t flags) |
673a394b | 3384 | { |
05394f39 | 3385 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3386 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3387 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3388 | unsigned long start = |
3389 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3390 | unsigned long end = | |
1ec9e26d | 3391 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3392 | struct i915_vma *vma; |
07f73f69 | 3393 | int ret; |
673a394b | 3394 | |
e28f8711 CW |
3395 | fence_size = i915_gem_get_gtt_size(dev, |
3396 | obj->base.size, | |
3397 | obj->tiling_mode); | |
3398 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3399 | obj->base.size, | |
d865110c | 3400 | obj->tiling_mode, true); |
e28f8711 | 3401 | unfenced_alignment = |
d865110c | 3402 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3403 | obj->base.size, |
3404 | obj->tiling_mode, false); | |
a00b10c3 | 3405 | |
673a394b | 3406 | if (alignment == 0) |
1ec9e26d | 3407 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3408 | unfenced_alignment; |
1ec9e26d | 3409 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3410 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3411 | return ERR_PTR(-EINVAL); |
673a394b EA |
3412 | } |
3413 | ||
1ec9e26d | 3414 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3415 | |
654fc607 CW |
3416 | /* If the object is bigger than the entire aperture, reject it early |
3417 | * before evicting everything in a vain attempt to find space. | |
3418 | */ | |
d23db88c CW |
3419 | if (obj->base.size > end) { |
3420 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", | |
a36689cb | 3421 | obj->base.size, |
1ec9e26d | 3422 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3423 | end); |
262de145 | 3424 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3425 | } |
3426 | ||
37e680a1 | 3427 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3428 | if (ret) |
262de145 | 3429 | return ERR_PTR(ret); |
6c085a72 | 3430 | |
fbdda6fb CW |
3431 | i915_gem_object_pin_pages(obj); |
3432 | ||
accfef2e | 3433 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3434 | if (IS_ERR(vma)) |
bc6bc15b | 3435 | goto err_unpin; |
2f633156 | 3436 | |
0a9ae0d7 | 3437 | search_free: |
07fe0b12 | 3438 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3439 | size, alignment, |
d23db88c CW |
3440 | obj->cache_level, |
3441 | start, end, | |
62347f9e LK |
3442 | DRM_MM_SEARCH_DEFAULT, |
3443 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3444 | if (ret) { |
f6cd1f15 | 3445 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3446 | obj->cache_level, |
3447 | start, end, | |
3448 | flags); | |
dc9dd7a2 CW |
3449 | if (ret == 0) |
3450 | goto search_free; | |
9731129c | 3451 | |
bc6bc15b | 3452 | goto err_free_vma; |
673a394b | 3453 | } |
2f633156 | 3454 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3455 | obj->cache_level))) { |
2f633156 | 3456 | ret = -EINVAL; |
bc6bc15b | 3457 | goto err_remove_node; |
673a394b EA |
3458 | } |
3459 | ||
74163907 | 3460 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3461 | if (ret) |
bc6bc15b | 3462 | goto err_remove_node; |
673a394b | 3463 | |
35c20a60 | 3464 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3465 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3466 | |
4bd561b3 BW |
3467 | if (i915_is_ggtt(vm)) { |
3468 | bool mappable, fenceable; | |
a00b10c3 | 3469 | |
49987099 DV |
3470 | fenceable = (vma->node.size == fence_size && |
3471 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3472 | |
49987099 DV |
3473 | mappable = (vma->node.start + obj->base.size <= |
3474 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3475 | |
5cacaac7 | 3476 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3477 | } |
75e9e915 | 3478 | |
1ec9e26d | 3479 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
75e9e915 | 3480 | |
1ec9e26d | 3481 | trace_i915_vma_bind(vma, flags); |
8ea99c92 DV |
3482 | vma->bind_vma(vma, obj->cache_level, |
3483 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); | |
3484 | ||
42d6ab48 | 3485 | i915_gem_verify_gtt(dev); |
262de145 | 3486 | return vma; |
2f633156 | 3487 | |
bc6bc15b | 3488 | err_remove_node: |
6286ef9b | 3489 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3490 | err_free_vma: |
2f633156 | 3491 | i915_gem_vma_destroy(vma); |
262de145 | 3492 | vma = ERR_PTR(ret); |
bc6bc15b | 3493 | err_unpin: |
2f633156 | 3494 | i915_gem_object_unpin_pages(obj); |
262de145 | 3495 | return vma; |
673a394b EA |
3496 | } |
3497 | ||
000433b6 | 3498 | bool |
2c22569b CW |
3499 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3500 | bool force) | |
673a394b | 3501 | { |
673a394b EA |
3502 | /* If we don't have a page list set up, then we're not pinned |
3503 | * to GPU, and we can ignore the cache flush because it'll happen | |
3504 | * again at bind time. | |
3505 | */ | |
05394f39 | 3506 | if (obj->pages == NULL) |
000433b6 | 3507 | return false; |
673a394b | 3508 | |
769ce464 ID |
3509 | /* |
3510 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3511 | * marked as wc by the system, or the system is cache-coherent. | |
3512 | */ | |
3513 | if (obj->stolen) | |
000433b6 | 3514 | return false; |
769ce464 | 3515 | |
9c23f7fc CW |
3516 | /* If the GPU is snooping the contents of the CPU cache, |
3517 | * we do not need to manually clear the CPU cache lines. However, | |
3518 | * the caches are only snooped when the render cache is | |
3519 | * flushed/invalidated. As we always have to emit invalidations | |
3520 | * and flushes when moving into and out of the RENDER domain, correct | |
3521 | * snooping behaviour occurs naturally as the result of our domain | |
3522 | * tracking. | |
3523 | */ | |
2c22569b | 3524 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3525 | return false; |
9c23f7fc | 3526 | |
1c5d22f7 | 3527 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3528 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3529 | |
3530 | return true; | |
e47c68e9 EA |
3531 | } |
3532 | ||
3533 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3534 | static void | |
05394f39 | 3535 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3536 | { |
1c5d22f7 CW |
3537 | uint32_t old_write_domain; |
3538 | ||
05394f39 | 3539 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3540 | return; |
3541 | ||
63256ec5 | 3542 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3543 | * to it immediately go to main memory as far as we know, so there's |
3544 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3545 | * |
3546 | * However, we do have to enforce the order so that all writes through | |
3547 | * the GTT land before any writes to the device, such as updates to | |
3548 | * the GATT itself. | |
e47c68e9 | 3549 | */ |
63256ec5 CW |
3550 | wmb(); |
3551 | ||
05394f39 CW |
3552 | old_write_domain = obj->base.write_domain; |
3553 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3554 | |
3555 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3556 | obj->base.read_domains, |
1c5d22f7 | 3557 | old_write_domain); |
e47c68e9 EA |
3558 | } |
3559 | ||
3560 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3561 | static void | |
2c22569b CW |
3562 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3563 | bool force) | |
e47c68e9 | 3564 | { |
1c5d22f7 | 3565 | uint32_t old_write_domain; |
e47c68e9 | 3566 | |
05394f39 | 3567 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3568 | return; |
3569 | ||
000433b6 CW |
3570 | if (i915_gem_clflush_object(obj, force)) |
3571 | i915_gem_chipset_flush(obj->base.dev); | |
3572 | ||
05394f39 CW |
3573 | old_write_domain = obj->base.write_domain; |
3574 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3575 | |
3576 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3577 | obj->base.read_domains, |
1c5d22f7 | 3578 | old_write_domain); |
e47c68e9 EA |
3579 | } |
3580 | ||
2ef7eeaa EA |
3581 | /** |
3582 | * Moves a single object to the GTT read, and possibly write domain. | |
3583 | * | |
3584 | * This function returns when the move is complete, including waiting on | |
3585 | * flushes to occur. | |
3586 | */ | |
79e53945 | 3587 | int |
2021746e | 3588 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3589 | { |
3e31c6c0 | 3590 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3591 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3592 | int ret; |
2ef7eeaa | 3593 | |
02354392 | 3594 | /* Not valid to be called on unbound objects. */ |
9843877d | 3595 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3596 | return -EINVAL; |
3597 | ||
8d7e3de1 CW |
3598 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3599 | return 0; | |
3600 | ||
0201f1ec | 3601 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3602 | if (ret) |
3603 | return ret; | |
3604 | ||
c8725f3d | 3605 | i915_gem_object_retire(obj); |
2c22569b | 3606 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3607 | |
d0a57789 CW |
3608 | /* Serialise direct access to this object with the barriers for |
3609 | * coherent writes from the GPU, by effectively invalidating the | |
3610 | * GTT domain upon first access. | |
3611 | */ | |
3612 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3613 | mb(); | |
3614 | ||
05394f39 CW |
3615 | old_write_domain = obj->base.write_domain; |
3616 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3617 | |
e47c68e9 EA |
3618 | /* It should now be out of any other write domains, and we can update |
3619 | * the domain values for our changes. | |
3620 | */ | |
05394f39 CW |
3621 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3622 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3623 | if (write) { |
05394f39 CW |
3624 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3625 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3626 | obj->dirty = 1; | |
2ef7eeaa EA |
3627 | } |
3628 | ||
1c5d22f7 CW |
3629 | trace_i915_gem_object_change_domain(obj, |
3630 | old_read_domains, | |
3631 | old_write_domain); | |
3632 | ||
8325a09d | 3633 | /* And bump the LRU for this access */ |
ca191b13 | 3634 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3635 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3636 | if (vma) |
3637 | list_move_tail(&vma->mm_list, | |
3638 | &dev_priv->gtt.base.inactive_list); | |
3639 | ||
3640 | } | |
8325a09d | 3641 | |
e47c68e9 EA |
3642 | return 0; |
3643 | } | |
3644 | ||
e4ffd173 CW |
3645 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3646 | enum i915_cache_level cache_level) | |
3647 | { | |
7bddb01f | 3648 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3649 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3650 | int ret; |
3651 | ||
3652 | if (obj->cache_level == cache_level) | |
3653 | return 0; | |
3654 | ||
d7f46fc4 | 3655 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3656 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3657 | return -EBUSY; | |
3658 | } | |
3659 | ||
df6f783a | 3660 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
3089c6f2 | 3661 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
07fe0b12 | 3662 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3663 | if (ret) |
3664 | return ret; | |
3089c6f2 | 3665 | } |
42d6ab48 CW |
3666 | } |
3667 | ||
3089c6f2 | 3668 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3669 | ret = i915_gem_object_finish_gpu(obj); |
3670 | if (ret) | |
3671 | return ret; | |
3672 | ||
3673 | i915_gem_object_finish_gtt(obj); | |
3674 | ||
3675 | /* Before SandyBridge, you could not use tiling or fence | |
3676 | * registers with snooped memory, so relinquish any fences | |
3677 | * currently pointing to our region in the aperture. | |
3678 | */ | |
42d6ab48 | 3679 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3680 | ret = i915_gem_object_put_fence(obj); |
3681 | if (ret) | |
3682 | return ret; | |
3683 | } | |
3684 | ||
6f65e29a | 3685 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3686 | if (drm_mm_node_allocated(&vma->node)) |
3687 | vma->bind_vma(vma, cache_level, | |
3688 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); | |
e4ffd173 CW |
3689 | } |
3690 | ||
2c22569b CW |
3691 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3692 | vma->node.color = cache_level; | |
3693 | obj->cache_level = cache_level; | |
3694 | ||
3695 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3696 | u32 old_read_domains, old_write_domain; |
3697 | ||
3698 | /* If we're coming from LLC cached, then we haven't | |
3699 | * actually been tracking whether the data is in the | |
3700 | * CPU cache or not, since we only allow one bit set | |
3701 | * in obj->write_domain and have been skipping the clflushes. | |
3702 | * Just set it to the CPU cache for now. | |
3703 | */ | |
c8725f3d | 3704 | i915_gem_object_retire(obj); |
e4ffd173 | 3705 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e4ffd173 CW |
3706 | |
3707 | old_read_domains = obj->base.read_domains; | |
3708 | old_write_domain = obj->base.write_domain; | |
3709 | ||
3710 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3711 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3712 | ||
3713 | trace_i915_gem_object_change_domain(obj, | |
3714 | old_read_domains, | |
3715 | old_write_domain); | |
3716 | } | |
3717 | ||
42d6ab48 | 3718 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3719 | return 0; |
3720 | } | |
3721 | ||
199adf40 BW |
3722 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3723 | struct drm_file *file) | |
e6994aee | 3724 | { |
199adf40 | 3725 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3726 | struct drm_i915_gem_object *obj; |
3727 | int ret; | |
3728 | ||
3729 | ret = i915_mutex_lock_interruptible(dev); | |
3730 | if (ret) | |
3731 | return ret; | |
3732 | ||
3733 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3734 | if (&obj->base == NULL) { | |
3735 | ret = -ENOENT; | |
3736 | goto unlock; | |
3737 | } | |
3738 | ||
651d794f CW |
3739 | switch (obj->cache_level) { |
3740 | case I915_CACHE_LLC: | |
3741 | case I915_CACHE_L3_LLC: | |
3742 | args->caching = I915_CACHING_CACHED; | |
3743 | break; | |
3744 | ||
4257d3ba CW |
3745 | case I915_CACHE_WT: |
3746 | args->caching = I915_CACHING_DISPLAY; | |
3747 | break; | |
3748 | ||
651d794f CW |
3749 | default: |
3750 | args->caching = I915_CACHING_NONE; | |
3751 | break; | |
3752 | } | |
e6994aee CW |
3753 | |
3754 | drm_gem_object_unreference(&obj->base); | |
3755 | unlock: | |
3756 | mutex_unlock(&dev->struct_mutex); | |
3757 | return ret; | |
3758 | } | |
3759 | ||
199adf40 BW |
3760 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3761 | struct drm_file *file) | |
e6994aee | 3762 | { |
199adf40 | 3763 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3764 | struct drm_i915_gem_object *obj; |
3765 | enum i915_cache_level level; | |
3766 | int ret; | |
3767 | ||
199adf40 BW |
3768 | switch (args->caching) { |
3769 | case I915_CACHING_NONE: | |
e6994aee CW |
3770 | level = I915_CACHE_NONE; |
3771 | break; | |
199adf40 | 3772 | case I915_CACHING_CACHED: |
e6994aee CW |
3773 | level = I915_CACHE_LLC; |
3774 | break; | |
4257d3ba CW |
3775 | case I915_CACHING_DISPLAY: |
3776 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3777 | break; | |
e6994aee CW |
3778 | default: |
3779 | return -EINVAL; | |
3780 | } | |
3781 | ||
3bc2913e BW |
3782 | ret = i915_mutex_lock_interruptible(dev); |
3783 | if (ret) | |
3784 | return ret; | |
3785 | ||
e6994aee CW |
3786 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3787 | if (&obj->base == NULL) { | |
3788 | ret = -ENOENT; | |
3789 | goto unlock; | |
3790 | } | |
3791 | ||
3792 | ret = i915_gem_object_set_cache_level(obj, level); | |
3793 | ||
3794 | drm_gem_object_unreference(&obj->base); | |
3795 | unlock: | |
3796 | mutex_unlock(&dev->struct_mutex); | |
3797 | return ret; | |
3798 | } | |
3799 | ||
cc98b413 CW |
3800 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3801 | { | |
19656430 OM |
3802 | struct i915_vma *vma; |
3803 | ||
3804 | if (list_empty(&obj->vma_list)) | |
3805 | return false; | |
3806 | ||
3807 | vma = i915_gem_obj_to_ggtt(obj); | |
3808 | if (!vma) | |
3809 | return false; | |
3810 | ||
cc98b413 CW |
3811 | /* There are 3 sources that pin objects: |
3812 | * 1. The display engine (scanouts, sprites, cursors); | |
3813 | * 2. Reservations for execbuffer; | |
3814 | * 3. The user. | |
3815 | * | |
3816 | * We can ignore reservations as we hold the struct_mutex and | |
3817 | * are only called outside of the reservation path. The user | |
3818 | * can only increment pin_count once, and so if after | |
3819 | * subtracting the potential reference by the user, any pin_count | |
3820 | * remains, it must be due to another use by the display engine. | |
3821 | */ | |
19656430 | 3822 | return vma->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3823 | } |
3824 | ||
b9241ea3 | 3825 | /* |
2da3b9b9 CW |
3826 | * Prepare buffer for display plane (scanout, cursors, etc). |
3827 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3828 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3829 | */ |
3830 | int | |
2da3b9b9 CW |
3831 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3832 | u32 alignment, | |
a4872ba6 | 3833 | struct intel_engine_cs *pipelined) |
b9241ea3 | 3834 | { |
2da3b9b9 | 3835 | u32 old_read_domains, old_write_domain; |
19656430 | 3836 | bool was_pin_display; |
b9241ea3 ZW |
3837 | int ret; |
3838 | ||
0be73284 | 3839 | if (pipelined != obj->ring) { |
2911a35b BW |
3840 | ret = i915_gem_object_sync(obj, pipelined); |
3841 | if (ret) | |
b9241ea3 ZW |
3842 | return ret; |
3843 | } | |
3844 | ||
cc98b413 CW |
3845 | /* Mark the pin_display early so that we account for the |
3846 | * display coherency whilst setting up the cache domains. | |
3847 | */ | |
19656430 | 3848 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3849 | obj->pin_display = true; |
3850 | ||
a7ef0640 EA |
3851 | /* The display engine is not coherent with the LLC cache on gen6. As |
3852 | * a result, we make sure that the pinning that is about to occur is | |
3853 | * done with uncached PTEs. This is lowest common denominator for all | |
3854 | * chipsets. | |
3855 | * | |
3856 | * However for gen6+, we could do better by using the GFDT bit instead | |
3857 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3858 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3859 | */ | |
651d794f CW |
3860 | ret = i915_gem_object_set_cache_level(obj, |
3861 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3862 | if (ret) |
cc98b413 | 3863 | goto err_unpin_display; |
a7ef0640 | 3864 | |
2da3b9b9 CW |
3865 | /* As the user may map the buffer once pinned in the display plane |
3866 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3867 | * always use map_and_fenceable for all scanout buffers. | |
3868 | */ | |
1ec9e26d | 3869 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3870 | if (ret) |
cc98b413 | 3871 | goto err_unpin_display; |
2da3b9b9 | 3872 | |
2c22569b | 3873 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3874 | |
2da3b9b9 | 3875 | old_write_domain = obj->base.write_domain; |
05394f39 | 3876 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3877 | |
3878 | /* It should now be out of any other write domains, and we can update | |
3879 | * the domain values for our changes. | |
3880 | */ | |
e5f1d962 | 3881 | obj->base.write_domain = 0; |
05394f39 | 3882 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3883 | |
3884 | trace_i915_gem_object_change_domain(obj, | |
3885 | old_read_domains, | |
2da3b9b9 | 3886 | old_write_domain); |
b9241ea3 ZW |
3887 | |
3888 | return 0; | |
cc98b413 CW |
3889 | |
3890 | err_unpin_display: | |
19656430 OM |
3891 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3892 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
3893 | return ret; |
3894 | } | |
3895 | ||
3896 | void | |
3897 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3898 | { | |
d7f46fc4 | 3899 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3900 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3901 | } |
3902 | ||
85345517 | 3903 | int |
a8198eea | 3904 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3905 | { |
88241785 CW |
3906 | int ret; |
3907 | ||
a8198eea | 3908 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3909 | return 0; |
3910 | ||
0201f1ec | 3911 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3912 | if (ret) |
3913 | return ret; | |
3914 | ||
a8198eea CW |
3915 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3916 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3917 | return 0; |
85345517 CW |
3918 | } |
3919 | ||
e47c68e9 EA |
3920 | /** |
3921 | * Moves a single object to the CPU read, and possibly write domain. | |
3922 | * | |
3923 | * This function returns when the move is complete, including waiting on | |
3924 | * flushes to occur. | |
3925 | */ | |
dabdfe02 | 3926 | int |
919926ae | 3927 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3928 | { |
1c5d22f7 | 3929 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3930 | int ret; |
3931 | ||
8d7e3de1 CW |
3932 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3933 | return 0; | |
3934 | ||
0201f1ec | 3935 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3936 | if (ret) |
3937 | return ret; | |
3938 | ||
c8725f3d | 3939 | i915_gem_object_retire(obj); |
e47c68e9 | 3940 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3941 | |
05394f39 CW |
3942 | old_write_domain = obj->base.write_domain; |
3943 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3944 | |
e47c68e9 | 3945 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3946 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3947 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3948 | |
05394f39 | 3949 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3950 | } |
3951 | ||
3952 | /* It should now be out of any other write domains, and we can update | |
3953 | * the domain values for our changes. | |
3954 | */ | |
05394f39 | 3955 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3956 | |
3957 | /* If we're writing through the CPU, then the GPU read domains will | |
3958 | * need to be invalidated at next use. | |
3959 | */ | |
3960 | if (write) { | |
05394f39 CW |
3961 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3962 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3963 | } |
2ef7eeaa | 3964 | |
1c5d22f7 CW |
3965 | trace_i915_gem_object_change_domain(obj, |
3966 | old_read_domains, | |
3967 | old_write_domain); | |
3968 | ||
2ef7eeaa EA |
3969 | return 0; |
3970 | } | |
3971 | ||
673a394b EA |
3972 | /* Throttle our rendering by waiting until the ring has completed our requests |
3973 | * emitted over 20 msec ago. | |
3974 | * | |
b962442e EA |
3975 | * Note that if we were to use the current jiffies each time around the loop, |
3976 | * we wouldn't escape the function with any frames outstanding if the time to | |
3977 | * render a frame was over 20ms. | |
3978 | * | |
673a394b EA |
3979 | * This should get us reasonable parallelism between CPU and GPU but also |
3980 | * relatively low latency when blocking on a particular request to finish. | |
3981 | */ | |
40a5f0de | 3982 | static int |
f787a5f5 | 3983 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3984 | { |
f787a5f5 CW |
3985 | struct drm_i915_private *dev_priv = dev->dev_private; |
3986 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3987 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 | 3988 | struct drm_i915_gem_request *request; |
a4872ba6 | 3989 | struct intel_engine_cs *ring = NULL; |
f69061be | 3990 | unsigned reset_counter; |
f787a5f5 CW |
3991 | u32 seqno = 0; |
3992 | int ret; | |
93533c29 | 3993 | |
308887aa DV |
3994 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3995 | if (ret) | |
3996 | return ret; | |
3997 | ||
3998 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3999 | if (ret) | |
4000 | return ret; | |
e110e8d6 | 4001 | |
1c25595f | 4002 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4003 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4004 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4005 | break; | |
40a5f0de | 4006 | |
f787a5f5 CW |
4007 | ring = request->ring; |
4008 | seqno = request->seqno; | |
b962442e | 4009 | } |
f69061be | 4010 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 4011 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4012 | |
f787a5f5 CW |
4013 | if (seqno == 0) |
4014 | return 0; | |
2bc43b5c | 4015 | |
b29c19b6 | 4016 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4017 | if (ret == 0) |
4018 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
4019 | |
4020 | return ret; | |
4021 | } | |
4022 | ||
d23db88c CW |
4023 | static bool |
4024 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4025 | { | |
4026 | struct drm_i915_gem_object *obj = vma->obj; | |
4027 | ||
4028 | if (alignment && | |
4029 | vma->node.start & (alignment - 1)) | |
4030 | return true; | |
4031 | ||
4032 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4033 | return true; | |
4034 | ||
4035 | if (flags & PIN_OFFSET_BIAS && | |
4036 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4037 | return true; | |
4038 | ||
4039 | return false; | |
4040 | } | |
4041 | ||
673a394b | 4042 | int |
05394f39 | 4043 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 4044 | struct i915_address_space *vm, |
05394f39 | 4045 | uint32_t alignment, |
d23db88c | 4046 | uint64_t flags) |
673a394b | 4047 | { |
6e7186af | 4048 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4049 | struct i915_vma *vma; |
673a394b EA |
4050 | int ret; |
4051 | ||
6e7186af BW |
4052 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4053 | return -ENODEV; | |
4054 | ||
bf3d149b | 4055 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4056 | return -EINVAL; |
07fe0b12 BW |
4057 | |
4058 | vma = i915_gem_obj_to_vma(obj, vm); | |
07fe0b12 | 4059 | if (vma) { |
d7f46fc4 BW |
4060 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4061 | return -EBUSY; | |
4062 | ||
d23db88c | 4063 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4064 | WARN(vma->pin_count, |
ae7d49d8 | 4065 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 4066 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4067 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 4068 | i915_gem_obj_offset(obj, vm), alignment, |
d23db88c | 4069 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4070 | obj->map_and_fenceable); |
07fe0b12 | 4071 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4072 | if (ret) |
4073 | return ret; | |
8ea99c92 DV |
4074 | |
4075 | vma = NULL; | |
ac0c6b5a CW |
4076 | } |
4077 | } | |
4078 | ||
8ea99c92 | 4079 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
4080 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
4081 | if (IS_ERR(vma)) | |
4082 | return PTR_ERR(vma); | |
22c344e9 | 4083 | } |
76446cac | 4084 | |
8ea99c92 DV |
4085 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
4086 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
74898d7e | 4087 | |
8ea99c92 | 4088 | vma->pin_count++; |
1ec9e26d DV |
4089 | if (flags & PIN_MAPPABLE) |
4090 | obj->pin_mappable |= true; | |
673a394b EA |
4091 | |
4092 | return 0; | |
4093 | } | |
4094 | ||
4095 | void | |
d7f46fc4 | 4096 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4097 | { |
d7f46fc4 | 4098 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 4099 | |
d7f46fc4 BW |
4100 | BUG_ON(!vma); |
4101 | BUG_ON(vma->pin_count == 0); | |
4102 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
4103 | ||
4104 | if (--vma->pin_count == 0) | |
6299f992 | 4105 | obj->pin_mappable = false; |
673a394b EA |
4106 | } |
4107 | ||
d8ffa60b DV |
4108 | bool |
4109 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4110 | { | |
4111 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4112 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4113 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4114 | ||
4115 | WARN_ON(!ggtt_vma || | |
4116 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4117 | ggtt_vma->pin_count); | |
4118 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4119 | return true; | |
4120 | } else | |
4121 | return false; | |
4122 | } | |
4123 | ||
4124 | void | |
4125 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4126 | { | |
4127 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4128 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4129 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4130 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4131 | } | |
4132 | } | |
4133 | ||
673a394b EA |
4134 | int |
4135 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4136 | struct drm_file *file) |
673a394b EA |
4137 | { |
4138 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4139 | struct drm_i915_gem_object *obj; |
673a394b EA |
4140 | int ret; |
4141 | ||
02f6bccc DV |
4142 | if (INTEL_INFO(dev)->gen >= 6) |
4143 | return -ENODEV; | |
4144 | ||
1d7cfea1 CW |
4145 | ret = i915_mutex_lock_interruptible(dev); |
4146 | if (ret) | |
4147 | return ret; | |
673a394b | 4148 | |
05394f39 | 4149 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4150 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4151 | ret = -ENOENT; |
4152 | goto unlock; | |
673a394b | 4153 | } |
673a394b | 4154 | |
05394f39 | 4155 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 4156 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
8c99e57d | 4157 | ret = -EFAULT; |
1d7cfea1 | 4158 | goto out; |
3ef94daa CW |
4159 | } |
4160 | ||
05394f39 | 4161 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
bd9b6a4e | 4162 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4163 | args->handle); |
1d7cfea1 CW |
4164 | ret = -EINVAL; |
4165 | goto out; | |
79e53945 JB |
4166 | } |
4167 | ||
aa5f8021 DV |
4168 | if (obj->user_pin_count == ULONG_MAX) { |
4169 | ret = -EBUSY; | |
4170 | goto out; | |
4171 | } | |
4172 | ||
93be8788 | 4173 | if (obj->user_pin_count == 0) { |
1ec9e26d | 4174 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
1d7cfea1 CW |
4175 | if (ret) |
4176 | goto out; | |
673a394b EA |
4177 | } |
4178 | ||
93be8788 CW |
4179 | obj->user_pin_count++; |
4180 | obj->pin_filp = file; | |
4181 | ||
f343c5f6 | 4182 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 4183 | out: |
05394f39 | 4184 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4185 | unlock: |
673a394b | 4186 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4187 | return ret; |
673a394b EA |
4188 | } |
4189 | ||
4190 | int | |
4191 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4192 | struct drm_file *file) |
673a394b EA |
4193 | { |
4194 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4195 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4196 | int ret; |
673a394b | 4197 | |
1d7cfea1 CW |
4198 | ret = i915_mutex_lock_interruptible(dev); |
4199 | if (ret) | |
4200 | return ret; | |
673a394b | 4201 | |
05394f39 | 4202 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4203 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4204 | ret = -ENOENT; |
4205 | goto unlock; | |
673a394b | 4206 | } |
76c1dec1 | 4207 | |
05394f39 | 4208 | if (obj->pin_filp != file) { |
bd9b6a4e | 4209 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4210 | args->handle); |
1d7cfea1 CW |
4211 | ret = -EINVAL; |
4212 | goto out; | |
79e53945 | 4213 | } |
05394f39 CW |
4214 | obj->user_pin_count--; |
4215 | if (obj->user_pin_count == 0) { | |
4216 | obj->pin_filp = NULL; | |
d7f46fc4 | 4217 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 4218 | } |
673a394b | 4219 | |
1d7cfea1 | 4220 | out: |
05394f39 | 4221 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4222 | unlock: |
673a394b | 4223 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4224 | return ret; |
673a394b EA |
4225 | } |
4226 | ||
4227 | int | |
4228 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4229 | struct drm_file *file) |
673a394b EA |
4230 | { |
4231 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4232 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4233 | int ret; |
4234 | ||
76c1dec1 | 4235 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4236 | if (ret) |
76c1dec1 | 4237 | return ret; |
673a394b | 4238 | |
3108e99e | 4239 | intel_edp_psr_exit(dev); |
7c8f8a70 | 4240 | |
05394f39 | 4241 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4242 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4243 | ret = -ENOENT; |
4244 | goto unlock; | |
673a394b | 4245 | } |
d1b851fc | 4246 | |
0be555b6 CW |
4247 | /* Count all active objects as busy, even if they are currently not used |
4248 | * by the gpu. Users of this interface expect objects to eventually | |
4249 | * become non-busy without any further actions, therefore emit any | |
4250 | * necessary flushes here. | |
c4de0a5d | 4251 | */ |
30dfebf3 | 4252 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4253 | |
30dfebf3 | 4254 | args->busy = obj->active; |
e9808edd CW |
4255 | if (obj->ring) { |
4256 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4257 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4258 | } | |
673a394b | 4259 | |
05394f39 | 4260 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4261 | unlock: |
673a394b | 4262 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4263 | return ret; |
673a394b EA |
4264 | } |
4265 | ||
4266 | int | |
4267 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4268 | struct drm_file *file_priv) | |
4269 | { | |
0206e353 | 4270 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4271 | } |
4272 | ||
3ef94daa CW |
4273 | int |
4274 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4275 | struct drm_file *file_priv) | |
4276 | { | |
4277 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4278 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4279 | int ret; |
3ef94daa CW |
4280 | |
4281 | switch (args->madv) { | |
4282 | case I915_MADV_DONTNEED: | |
4283 | case I915_MADV_WILLNEED: | |
4284 | break; | |
4285 | default: | |
4286 | return -EINVAL; | |
4287 | } | |
4288 | ||
1d7cfea1 CW |
4289 | ret = i915_mutex_lock_interruptible(dev); |
4290 | if (ret) | |
4291 | return ret; | |
4292 | ||
05394f39 | 4293 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4294 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4295 | ret = -ENOENT; |
4296 | goto unlock; | |
3ef94daa | 4297 | } |
3ef94daa | 4298 | |
d7f46fc4 | 4299 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4300 | ret = -EINVAL; |
4301 | goto out; | |
3ef94daa CW |
4302 | } |
4303 | ||
05394f39 CW |
4304 | if (obj->madv != __I915_MADV_PURGED) |
4305 | obj->madv = args->madv; | |
3ef94daa | 4306 | |
6c085a72 CW |
4307 | /* if the object is no longer attached, discard its backing storage */ |
4308 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4309 | i915_gem_object_truncate(obj); |
4310 | ||
05394f39 | 4311 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4312 | |
1d7cfea1 | 4313 | out: |
05394f39 | 4314 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4315 | unlock: |
3ef94daa | 4316 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4317 | return ret; |
3ef94daa CW |
4318 | } |
4319 | ||
37e680a1 CW |
4320 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4321 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4322 | { |
35c20a60 | 4323 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4324 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4325 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4326 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4327 | |
37e680a1 CW |
4328 | obj->ops = ops; |
4329 | ||
0327d6ba CW |
4330 | obj->fence_reg = I915_FENCE_REG_NONE; |
4331 | obj->madv = I915_MADV_WILLNEED; | |
4332 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4333 | obj->map_and_fenceable = true; | |
4334 | ||
4335 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4336 | } | |
4337 | ||
37e680a1 CW |
4338 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4339 | .get_pages = i915_gem_object_get_pages_gtt, | |
4340 | .put_pages = i915_gem_object_put_pages_gtt, | |
4341 | }; | |
4342 | ||
05394f39 CW |
4343 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4344 | size_t size) | |
ac52bc56 | 4345 | { |
c397b908 | 4346 | struct drm_i915_gem_object *obj; |
5949eac4 | 4347 | struct address_space *mapping; |
1a240d4d | 4348 | gfp_t mask; |
ac52bc56 | 4349 | |
42dcedd4 | 4350 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4351 | if (obj == NULL) |
4352 | return NULL; | |
673a394b | 4353 | |
c397b908 | 4354 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4355 | i915_gem_object_free(obj); |
c397b908 DV |
4356 | return NULL; |
4357 | } | |
673a394b | 4358 | |
bed1ea95 CW |
4359 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4360 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4361 | /* 965gm cannot relocate objects above 4GiB. */ | |
4362 | mask &= ~__GFP_HIGHMEM; | |
4363 | mask |= __GFP_DMA32; | |
4364 | } | |
4365 | ||
496ad9aa | 4366 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4367 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4368 | |
37e680a1 | 4369 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4370 | |
c397b908 DV |
4371 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4372 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4373 | |
3d29b842 ED |
4374 | if (HAS_LLC(dev)) { |
4375 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4376 | * cache) for about a 10% performance improvement |
4377 | * compared to uncached. Graphics requests other than | |
4378 | * display scanout are coherent with the CPU in | |
4379 | * accessing this cache. This means in this mode we | |
4380 | * don't need to clflush on the CPU side, and on the | |
4381 | * GPU side we only need to flush internal caches to | |
4382 | * get data visible to the CPU. | |
4383 | * | |
4384 | * However, we maintain the display planes as UC, and so | |
4385 | * need to rebind when first used as such. | |
4386 | */ | |
4387 | obj->cache_level = I915_CACHE_LLC; | |
4388 | } else | |
4389 | obj->cache_level = I915_CACHE_NONE; | |
4390 | ||
d861e338 DV |
4391 | trace_i915_gem_object_create(obj); |
4392 | ||
05394f39 | 4393 | return obj; |
c397b908 DV |
4394 | } |
4395 | ||
340fbd8c CW |
4396 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4397 | { | |
4398 | /* If we are the last user of the backing storage (be it shmemfs | |
4399 | * pages or stolen etc), we know that the pages are going to be | |
4400 | * immediately released. In this case, we can then skip copying | |
4401 | * back the contents from the GPU. | |
4402 | */ | |
4403 | ||
4404 | if (obj->madv != I915_MADV_WILLNEED) | |
4405 | return false; | |
4406 | ||
4407 | if (obj->base.filp == NULL) | |
4408 | return true; | |
4409 | ||
4410 | /* At first glance, this looks racy, but then again so would be | |
4411 | * userspace racing mmap against close. However, the first external | |
4412 | * reference to the filp can only be obtained through the | |
4413 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4414 | * acquiring such a reference whilst we are in the middle of | |
4415 | * freeing the object. | |
4416 | */ | |
4417 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4418 | } | |
4419 | ||
1488fc08 | 4420 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4421 | { |
1488fc08 | 4422 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4423 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4424 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4425 | struct i915_vma *vma, *next; |
673a394b | 4426 | |
f65c9168 PZ |
4427 | intel_runtime_pm_get(dev_priv); |
4428 | ||
26e12f89 CW |
4429 | trace_i915_gem_object_destroy(obj); |
4430 | ||
07fe0b12 | 4431 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4432 | int ret; |
4433 | ||
4434 | vma->pin_count = 0; | |
4435 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4436 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4437 | bool was_interruptible; | |
1488fc08 | 4438 | |
07fe0b12 BW |
4439 | was_interruptible = dev_priv->mm.interruptible; |
4440 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4441 | |
07fe0b12 | 4442 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4443 | |
07fe0b12 BW |
4444 | dev_priv->mm.interruptible = was_interruptible; |
4445 | } | |
1488fc08 CW |
4446 | } |
4447 | ||
00731155 CW |
4448 | i915_gem_object_detach_phys(obj); |
4449 | ||
1d64ae71 BW |
4450 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4451 | * before progressing. */ | |
4452 | if (obj->stolen) | |
4453 | i915_gem_object_unpin_pages(obj); | |
4454 | ||
401c29f6 BW |
4455 | if (WARN_ON(obj->pages_pin_count)) |
4456 | obj->pages_pin_count = 0; | |
340fbd8c | 4457 | if (discard_backing_storage(obj)) |
5537252b | 4458 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4459 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4460 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4461 | |
9da3da66 CW |
4462 | BUG_ON(obj->pages); |
4463 | ||
2f745ad3 CW |
4464 | if (obj->base.import_attach) |
4465 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4466 | |
5cc9ed4b CW |
4467 | if (obj->ops->release) |
4468 | obj->ops->release(obj); | |
4469 | ||
05394f39 CW |
4470 | drm_gem_object_release(&obj->base); |
4471 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4472 | |
05394f39 | 4473 | kfree(obj->bit_17); |
42dcedd4 | 4474 | i915_gem_object_free(obj); |
f65c9168 PZ |
4475 | |
4476 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4477 | } |
4478 | ||
e656a6cb | 4479 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4480 | struct i915_address_space *vm) |
e656a6cb DV |
4481 | { |
4482 | struct i915_vma *vma; | |
4483 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4484 | if (vma->vm == vm) | |
4485 | return vma; | |
4486 | ||
4487 | return NULL; | |
4488 | } | |
4489 | ||
2f633156 BW |
4490 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4491 | { | |
4492 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4493 | |
4494 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4495 | if (!list_empty(&vma->exec_list)) | |
4496 | return; | |
4497 | ||
8b9c2b94 | 4498 | list_del(&vma->vma_link); |
b93dab6e | 4499 | |
2f633156 BW |
4500 | kfree(vma); |
4501 | } | |
4502 | ||
e3efda49 CW |
4503 | static void |
4504 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4505 | { | |
4506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4507 | struct intel_engine_cs *ring; |
e3efda49 CW |
4508 | int i; |
4509 | ||
4510 | for_each_ring(ring, dev_priv, i) | |
4511 | intel_stop_ring_buffer(ring); | |
4512 | } | |
4513 | ||
29105ccc | 4514 | int |
45c5f202 | 4515 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4516 | { |
3e31c6c0 | 4517 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4518 | int ret = 0; |
28dfe52a | 4519 | |
45c5f202 | 4520 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4521 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4522 | goto err; |
28dfe52a | 4523 | |
b2da9fe5 | 4524 | ret = i915_gpu_idle(dev); |
f7403347 | 4525 | if (ret) |
45c5f202 | 4526 | goto err; |
f7403347 | 4527 | |
b2da9fe5 | 4528 | i915_gem_retire_requests(dev); |
673a394b | 4529 | |
29105ccc | 4530 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4531 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4532 | i915_gem_evict_everything(dev); |
29105ccc | 4533 | |
29105ccc | 4534 | i915_kernel_lost_context(dev); |
e3efda49 | 4535 | i915_gem_stop_ringbuffers(dev); |
29105ccc | 4536 | |
45c5f202 CW |
4537 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4538 | * We need to replace this with a semaphore, or something. | |
4539 | * And not confound ums.mm_suspended! | |
4540 | */ | |
4541 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4542 | DRIVER_MODESET); | |
4543 | mutex_unlock(&dev->struct_mutex); | |
4544 | ||
4545 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4546 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
b29c19b6 | 4547 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4548 | |
673a394b | 4549 | return 0; |
45c5f202 CW |
4550 | |
4551 | err: | |
4552 | mutex_unlock(&dev->struct_mutex); | |
4553 | return ret; | |
673a394b EA |
4554 | } |
4555 | ||
a4872ba6 | 4556 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4557 | { |
c3787e2e | 4558 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4559 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4560 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4561 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4562 | int i, ret; |
b9524a1e | 4563 | |
040d2baa | 4564 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4565 | return 0; |
b9524a1e | 4566 | |
c3787e2e BW |
4567 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4568 | if (ret) | |
4569 | return ret; | |
b9524a1e | 4570 | |
c3787e2e BW |
4571 | /* |
4572 | * Note: We do not worry about the concurrent register cacheline hang | |
4573 | * here because no other code should access these registers other than | |
4574 | * at initialization time. | |
4575 | */ | |
b9524a1e | 4576 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4577 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4578 | intel_ring_emit(ring, reg_base + i); | |
4579 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4580 | } |
4581 | ||
c3787e2e | 4582 | intel_ring_advance(ring); |
b9524a1e | 4583 | |
c3787e2e | 4584 | return ret; |
b9524a1e BW |
4585 | } |
4586 | ||
f691e2f4 DV |
4587 | void i915_gem_init_swizzling(struct drm_device *dev) |
4588 | { | |
3e31c6c0 | 4589 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4590 | |
11782b02 | 4591 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4592 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4593 | return; | |
4594 | ||
4595 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4596 | DISP_TILE_SURFACE_SWIZZLING); | |
4597 | ||
11782b02 DV |
4598 | if (IS_GEN5(dev)) |
4599 | return; | |
4600 | ||
f691e2f4 DV |
4601 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4602 | if (IS_GEN6(dev)) | |
6b26c86d | 4603 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4604 | else if (IS_GEN7(dev)) |
6b26c86d | 4605 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4606 | else if (IS_GEN8(dev)) |
4607 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4608 | else |
4609 | BUG(); | |
f691e2f4 | 4610 | } |
e21af88d | 4611 | |
67b1b571 CW |
4612 | static bool |
4613 | intel_enable_blt(struct drm_device *dev) | |
4614 | { | |
4615 | if (!HAS_BLT(dev)) | |
4616 | return false; | |
4617 | ||
4618 | /* The blitter was dysfunctional on early prototypes */ | |
4619 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4620 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4621 | " graphics performance will be degraded.\n"); | |
4622 | return false; | |
4623 | } | |
4624 | ||
4625 | return true; | |
4626 | } | |
4627 | ||
4fc7c971 | 4628 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4629 | { |
4fc7c971 | 4630 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4631 | int ret; |
68f95ba9 | 4632 | |
5c1143bb | 4633 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4634 | if (ret) |
b6913e4b | 4635 | return ret; |
68f95ba9 CW |
4636 | |
4637 | if (HAS_BSD(dev)) { | |
5c1143bb | 4638 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4639 | if (ret) |
4640 | goto cleanup_render_ring; | |
d1b851fc | 4641 | } |
68f95ba9 | 4642 | |
67b1b571 | 4643 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4644 | ret = intel_init_blt_ring_buffer(dev); |
4645 | if (ret) | |
4646 | goto cleanup_bsd_ring; | |
4647 | } | |
4648 | ||
9a8a2213 BW |
4649 | if (HAS_VEBOX(dev)) { |
4650 | ret = intel_init_vebox_ring_buffer(dev); | |
4651 | if (ret) | |
4652 | goto cleanup_blt_ring; | |
4653 | } | |
4654 | ||
845f74a7 ZY |
4655 | if (HAS_BSD2(dev)) { |
4656 | ret = intel_init_bsd2_ring_buffer(dev); | |
4657 | if (ret) | |
4658 | goto cleanup_vebox_ring; | |
4659 | } | |
9a8a2213 | 4660 | |
99433931 | 4661 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4662 | if (ret) |
845f74a7 | 4663 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4664 | |
4665 | return 0; | |
4666 | ||
845f74a7 ZY |
4667 | cleanup_bsd2_ring: |
4668 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4669 | cleanup_vebox_ring: |
4670 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4671 | cleanup_blt_ring: |
4672 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4673 | cleanup_bsd_ring: | |
4674 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4675 | cleanup_render_ring: | |
4676 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4677 | ||
4678 | return ret; | |
4679 | } | |
4680 | ||
4681 | int | |
4682 | i915_gem_init_hw(struct drm_device *dev) | |
4683 | { | |
3e31c6c0 | 4684 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4685 | int ret, i; |
4fc7c971 BW |
4686 | |
4687 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4688 | return -EIO; | |
4689 | ||
59124506 | 4690 | if (dev_priv->ellc_size) |
05e21cc4 | 4691 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4692 | |
0bf21347 VS |
4693 | if (IS_HASWELL(dev)) |
4694 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4695 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4696 | |
88a2b2a3 | 4697 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4698 | if (IS_IVYBRIDGE(dev)) { |
4699 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4700 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4701 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4702 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4703 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4704 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4705 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4706 | } | |
88a2b2a3 BW |
4707 | } |
4708 | ||
4fc7c971 BW |
4709 | i915_gem_init_swizzling(dev); |
4710 | ||
4711 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4712 | if (ret) |
4713 | return ret; | |
4714 | ||
c3787e2e BW |
4715 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4716 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4717 | ||
254f965c | 4718 | /* |
2fa48d8d BW |
4719 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4720 | * default context switch however is something we'd like to do after | |
4721 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4722 | * goes with our code better). Context switching requires rings (for | |
4723 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4724 | */ |
2fa48d8d | 4725 | ret = i915_gem_context_enable(dev_priv); |
60990320 | 4726 | if (ret && ret != -EIO) { |
2fa48d8d | 4727 | DRM_ERROR("Context enable failed %d\n", ret); |
60990320 | 4728 | i915_gem_cleanup_ringbuffer(dev); |
b7c36d25 | 4729 | } |
e21af88d | 4730 | |
2fa48d8d | 4731 | return ret; |
8187a2b7 ZN |
4732 | } |
4733 | ||
1070a42b CW |
4734 | int i915_gem_init(struct drm_device *dev) |
4735 | { | |
4736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4737 | int ret; |
4738 | ||
1070a42b | 4739 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4740 | |
4741 | if (IS_VALLEYVIEW(dev)) { | |
4742 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4743 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4744 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4745 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4746 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4747 | } | |
4748 | ||
5cc9ed4b | 4749 | i915_gem_init_userptr(dev); |
d7e5008f | 4750 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4751 | |
2fa48d8d | 4752 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4753 | if (ret) { |
4754 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4755 | return ret; |
e3848694 | 4756 | } |
2fa48d8d | 4757 | |
1070a42b | 4758 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4759 | if (ret == -EIO) { |
4760 | /* Allow ring initialisation to fail by marking the GPU as | |
4761 | * wedged. But we only want to do this where the GPU is angry, | |
4762 | * for all other failure, such as an allocation failure, bail. | |
4763 | */ | |
4764 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4765 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4766 | ret = 0; | |
1070a42b | 4767 | } |
60990320 | 4768 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4769 | |
53ca26ca DV |
4770 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4771 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4772 | dev_priv->dri1.allow_batchbuffer = 1; | |
60990320 | 4773 | return ret; |
1070a42b CW |
4774 | } |
4775 | ||
8187a2b7 ZN |
4776 | void |
4777 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4778 | { | |
3e31c6c0 | 4779 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4780 | struct intel_engine_cs *ring; |
1ec14ad3 | 4781 | int i; |
8187a2b7 | 4782 | |
b4519513 CW |
4783 | for_each_ring(ring, dev_priv, i) |
4784 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4785 | } |
4786 | ||
673a394b EA |
4787 | int |
4788 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4789 | struct drm_file *file_priv) | |
4790 | { | |
db1b76ca | 4791 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4792 | int ret; |
673a394b | 4793 | |
79e53945 JB |
4794 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4795 | return 0; | |
4796 | ||
1f83fee0 | 4797 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4798 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4799 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4800 | } |
4801 | ||
673a394b | 4802 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4803 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4804 | |
f691e2f4 | 4805 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4806 | if (ret != 0) { |
4807 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4808 | return ret; |
d816f6ac | 4809 | } |
9bb2d6f9 | 4810 | |
5cef07e1 | 4811 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
dbb19d30 | 4812 | |
bb0f1b5c | 4813 | ret = drm_irq_install(dev, dev->pdev->irq); |
5f35308b CW |
4814 | if (ret) |
4815 | goto cleanup_ringbuffer; | |
e090c53b | 4816 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4817 | |
673a394b | 4818 | return 0; |
5f35308b CW |
4819 | |
4820 | cleanup_ringbuffer: | |
5f35308b | 4821 | i915_gem_cleanup_ringbuffer(dev); |
db1b76ca | 4822 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4823 | mutex_unlock(&dev->struct_mutex); |
4824 | ||
4825 | return ret; | |
673a394b EA |
4826 | } |
4827 | ||
4828 | int | |
4829 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4830 | struct drm_file *file_priv) | |
4831 | { | |
79e53945 JB |
4832 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4833 | return 0; | |
4834 | ||
e090c53b | 4835 | mutex_lock(&dev->struct_mutex); |
dbb19d30 | 4836 | drm_irq_uninstall(dev); |
e090c53b | 4837 | mutex_unlock(&dev->struct_mutex); |
db1b76ca | 4838 | |
45c5f202 | 4839 | return i915_gem_suspend(dev); |
673a394b EA |
4840 | } |
4841 | ||
4842 | void | |
4843 | i915_gem_lastclose(struct drm_device *dev) | |
4844 | { | |
4845 | int ret; | |
673a394b | 4846 | |
e806b495 EA |
4847 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4848 | return; | |
4849 | ||
45c5f202 | 4850 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4851 | if (ret) |
4852 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4853 | } |
4854 | ||
64193406 | 4855 | static void |
a4872ba6 | 4856 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4857 | { |
4858 | INIT_LIST_HEAD(&ring->active_list); | |
4859 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4860 | } |
4861 | ||
7e0d96bc BW |
4862 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4863 | struct i915_address_space *vm) | |
fc8c067e | 4864 | { |
7e0d96bc BW |
4865 | if (!i915_is_ggtt(vm)) |
4866 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4867 | vm->dev = dev_priv->dev; |
4868 | INIT_LIST_HEAD(&vm->active_list); | |
4869 | INIT_LIST_HEAD(&vm->inactive_list); | |
4870 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4871 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4872 | } |
4873 | ||
673a394b EA |
4874 | void |
4875 | i915_gem_load(struct drm_device *dev) | |
4876 | { | |
3e31c6c0 | 4877 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4878 | int i; |
4879 | ||
4880 | dev_priv->slab = | |
4881 | kmem_cache_create("i915_gem_object", | |
4882 | sizeof(struct drm_i915_gem_object), 0, | |
4883 | SLAB_HWCACHE_ALIGN, | |
4884 | NULL); | |
673a394b | 4885 | |
fc8c067e BW |
4886 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4887 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4888 | ||
a33afea5 | 4889 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4890 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4891 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4892 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4893 | for (i = 0; i < I915_NUM_RINGS; i++) |
4894 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4895 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4896 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4897 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4898 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4899 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4900 | i915_gem_idle_work_handler); | |
1f83fee0 | 4901 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4902 | |
94400120 | 4903 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
dbb42748 | 4904 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
50743298 DV |
4905 | I915_WRITE(MI_ARB_STATE, |
4906 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4907 | } |
4908 | ||
72bfa19c CW |
4909 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4910 | ||
de151cf6 | 4911 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4912 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4913 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4914 | |
42b5aeab VS |
4915 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4916 | dev_priv->num_fence_regs = 32; | |
4917 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4918 | dev_priv->num_fence_regs = 16; |
4919 | else | |
4920 | dev_priv->num_fence_regs = 8; | |
4921 | ||
b5aa8a0f | 4922 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4923 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4924 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4925 | |
673a394b | 4926 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4927 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4928 | |
ce453d81 CW |
4929 | dev_priv->mm.interruptible = true; |
4930 | ||
ceabbba5 CW |
4931 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
4932 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
4933 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
4934 | register_shrinker(&dev_priv->mm.shrinker); | |
2cfcd32a CW |
4935 | |
4936 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; | |
4937 | register_oom_notifier(&dev_priv->mm.oom_notifier); | |
673a394b | 4938 | } |
71acb5eb | 4939 | |
f787a5f5 | 4940 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4941 | { |
f787a5f5 | 4942 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4943 | |
b29c19b6 CW |
4944 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4945 | ||
b962442e EA |
4946 | /* Clean up our request list when the client is going away, so that |
4947 | * later retire_requests won't dereference our soon-to-be-gone | |
4948 | * file_priv. | |
4949 | */ | |
1c25595f | 4950 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4951 | while (!list_empty(&file_priv->mm.request_list)) { |
4952 | struct drm_i915_gem_request *request; | |
4953 | ||
4954 | request = list_first_entry(&file_priv->mm.request_list, | |
4955 | struct drm_i915_gem_request, | |
4956 | client_list); | |
4957 | list_del(&request->client_list); | |
4958 | request->file_priv = NULL; | |
4959 | } | |
1c25595f | 4960 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4961 | } |
31169714 | 4962 | |
b29c19b6 CW |
4963 | static void |
4964 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
4965 | { | |
4966 | struct drm_i915_file_private *file_priv = | |
4967 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
4968 | ||
4969 | atomic_set(&file_priv->rps_wait_boost, false); | |
4970 | } | |
4971 | ||
4972 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4973 | { | |
4974 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4975 | int ret; |
b29c19b6 CW |
4976 | |
4977 | DRM_DEBUG_DRIVER("\n"); | |
4978 | ||
4979 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4980 | if (!file_priv) | |
4981 | return -ENOMEM; | |
4982 | ||
4983 | file->driver_priv = file_priv; | |
4984 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 4985 | file_priv->file = file; |
b29c19b6 CW |
4986 | |
4987 | spin_lock_init(&file_priv->mm.lock); | |
4988 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4989 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
4990 | i915_gem_file_idle_work_handler); | |
4991 | ||
e422b888 BW |
4992 | ret = i915_gem_context_open(dev, file); |
4993 | if (ret) | |
4994 | kfree(file_priv); | |
b29c19b6 | 4995 | |
e422b888 | 4996 | return ret; |
b29c19b6 CW |
4997 | } |
4998 | ||
5774506f CW |
4999 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
5000 | { | |
5001 | if (!mutex_is_locked(mutex)) | |
5002 | return false; | |
5003 | ||
5004 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
5005 | return mutex->owner == task; | |
5006 | #else | |
5007 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5008 | return false; | |
5009 | #endif | |
5010 | } | |
5011 | ||
b453c4db CW |
5012 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
5013 | { | |
5014 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5015 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
5016 | return false; | |
5017 | ||
5018 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) | |
5019 | return false; | |
5020 | ||
5021 | *unlock = false; | |
5022 | } else | |
5023 | *unlock = true; | |
5024 | ||
5025 | return true; | |
5026 | } | |
5027 | ||
ceabbba5 CW |
5028 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5029 | { | |
5030 | struct i915_vma *vma; | |
5031 | int count = 0; | |
5032 | ||
5033 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5034 | if (drm_mm_node_allocated(&vma->node)) | |
5035 | count++; | |
5036 | ||
5037 | return count; | |
5038 | } | |
5039 | ||
7dc19d5a | 5040 | static unsigned long |
ceabbba5 | 5041 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5042 | { |
17250b71 | 5043 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5044 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5045 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5046 | struct drm_i915_gem_object *obj; |
7dc19d5a | 5047 | unsigned long count; |
b453c4db | 5048 | bool unlock; |
17250b71 | 5049 | |
b453c4db CW |
5050 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5051 | return 0; | |
31169714 | 5052 | |
7dc19d5a | 5053 | count = 0; |
35c20a60 | 5054 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5055 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5056 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5057 | |
5058 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5059 | if (!i915_gem_obj_is_pinned(obj) && |
5060 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5061 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5062 | } |
17250b71 | 5063 | |
5774506f CW |
5064 | if (unlock) |
5065 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5066 | |
7dc19d5a | 5067 | return count; |
31169714 | 5068 | } |
a70a3148 BW |
5069 | |
5070 | /* All the new VM stuff */ | |
5071 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5072 | struct i915_address_space *vm) | |
5073 | { | |
5074 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5075 | struct i915_vma *vma; | |
5076 | ||
6f425321 BW |
5077 | if (!dev_priv->mm.aliasing_ppgtt || |
5078 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5079 | vm = &dev_priv->gtt.base; |
5080 | ||
a70a3148 BW |
5081 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
5082 | if (vma->vm == vm) | |
5083 | return vma->node.start; | |
5084 | ||
5085 | } | |
f25748ea DV |
5086 | WARN(1, "%s vma for this object not found.\n", |
5087 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5088 | return -1; |
5089 | } | |
5090 | ||
5091 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5092 | struct i915_address_space *vm) | |
5093 | { | |
5094 | struct i915_vma *vma; | |
5095 | ||
5096 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5097 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5098 | return true; |
5099 | ||
5100 | return false; | |
5101 | } | |
5102 | ||
5103 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5104 | { | |
5a1d5eb0 | 5105 | struct i915_vma *vma; |
a70a3148 | 5106 | |
5a1d5eb0 CW |
5107 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5108 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5109 | return true; |
5110 | ||
5111 | return false; | |
5112 | } | |
5113 | ||
5114 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5115 | struct i915_address_space *vm) | |
5116 | { | |
5117 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5118 | struct i915_vma *vma; | |
5119 | ||
6f425321 BW |
5120 | if (!dev_priv->mm.aliasing_ppgtt || |
5121 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5122 | vm = &dev_priv->gtt.base; |
5123 | ||
5124 | BUG_ON(list_empty(&o->vma_list)); | |
5125 | ||
5126 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5127 | if (vma->vm == vm) | |
5128 | return vma->node.size; | |
5129 | ||
5130 | return 0; | |
5131 | } | |
5132 | ||
7dc19d5a | 5133 | static unsigned long |
ceabbba5 | 5134 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5135 | { |
5136 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5137 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5138 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a | 5139 | unsigned long freed; |
b453c4db | 5140 | bool unlock; |
7dc19d5a | 5141 | |
b453c4db CW |
5142 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5143 | return SHRINK_STOP; | |
7dc19d5a | 5144 | |
d9973b43 CW |
5145 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
5146 | if (freed < sc->nr_to_scan) | |
5147 | freed += __i915_gem_shrink(dev_priv, | |
5148 | sc->nr_to_scan - freed, | |
5149 | false); | |
7dc19d5a DC |
5150 | if (unlock) |
5151 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5152 | |
7dc19d5a DC |
5153 | return freed; |
5154 | } | |
5c2abbea | 5155 | |
2cfcd32a CW |
5156 | static int |
5157 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) | |
5158 | { | |
5159 | struct drm_i915_private *dev_priv = | |
5160 | container_of(nb, struct drm_i915_private, mm.oom_notifier); | |
5161 | struct drm_device *dev = dev_priv->dev; | |
5162 | struct drm_i915_gem_object *obj; | |
5163 | unsigned long timeout = msecs_to_jiffies(5000) + 1; | |
5164 | unsigned long pinned, bound, unbound, freed; | |
5165 | bool was_interruptible; | |
5166 | bool unlock; | |
5167 | ||
5168 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) | |
5169 | schedule_timeout_killable(1); | |
5170 | if (timeout == 0) { | |
5171 | pr_err("Unable to purge GPU memory due lock contention.\n"); | |
5172 | return NOTIFY_DONE; | |
5173 | } | |
5174 | ||
5175 | was_interruptible = dev_priv->mm.interruptible; | |
5176 | dev_priv->mm.interruptible = false; | |
5177 | ||
5178 | freed = i915_gem_shrink_all(dev_priv); | |
5179 | ||
5180 | dev_priv->mm.interruptible = was_interruptible; | |
5181 | ||
5182 | /* Because we may be allocating inside our own driver, we cannot | |
5183 | * assert that there are no objects with pinned pages that are not | |
5184 | * being pointed to by hardware. | |
5185 | */ | |
5186 | unbound = bound = pinned = 0; | |
5187 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5188 | if (!obj->base.filp) /* not backed by a freeable object */ | |
5189 | continue; | |
5190 | ||
5191 | if (obj->pages_pin_count) | |
5192 | pinned += obj->base.size; | |
5193 | else | |
5194 | unbound += obj->base.size; | |
5195 | } | |
5196 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5197 | if (!obj->base.filp) | |
5198 | continue; | |
5199 | ||
5200 | if (obj->pages_pin_count) | |
5201 | pinned += obj->base.size; | |
5202 | else | |
5203 | bound += obj->base.size; | |
5204 | } | |
5205 | ||
5206 | if (unlock) | |
5207 | mutex_unlock(&dev->struct_mutex); | |
5208 | ||
5209 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", | |
5210 | freed, pinned); | |
5211 | if (unbound || bound) | |
5212 | pr_err("%lu and %lu bytes still available in the " | |
5213 | "bound and unbound GPU page lists.\n", | |
5214 | bound, unbound); | |
5215 | ||
5216 | *(unsigned long *)ptr += freed; | |
5217 | return NOTIFY_DONE; | |
5218 | } | |
5219 | ||
5c2abbea BW |
5220 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
5221 | { | |
5222 | struct i915_vma *vma; | |
5223 | ||
19656430 OM |
5224 | /* This WARN has probably outlived its usefulness (callers already |
5225 | * WARN if they don't find the GGTT vma they expect). When removing, | |
5226 | * remember to remove the pre-check in is_pin_display() as well */ | |
5c2abbea BW |
5227 | if (WARN_ON(list_empty(&obj->vma_list))) |
5228 | return NULL; | |
5229 | ||
5230 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
6e164c33 | 5231 | if (vma->vm != obj_to_ggtt(obj)) |
5c2abbea BW |
5232 | return NULL; |
5233 | ||
5234 | return vma; | |
5235 | } |