Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
86a1ee26 CW |
44 | bool map_and_fenceable, |
45 | bool nonblocking); | |
05394f39 CW |
46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
47 | struct drm_i915_gem_object *obj, | |
71acb5eb | 48 | struct drm_i915_gem_pwrite *args, |
05394f39 | 49 | struct drm_file *file); |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
6c085a72 CW |
59 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
60 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 61 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 62 | |
61050808 CW |
63 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
64 | { | |
65 | if (obj->tiling_mode) | |
66 | i915_gem_release_mmap(obj); | |
67 | ||
68 | /* As we do not have an associated fence register, we will force | |
69 | * a tiling change if we ever need to acquire one. | |
70 | */ | |
5d82e3e6 | 71 | obj->fence_dirty = false; |
61050808 CW |
72 | obj->fence_reg = I915_FENCE_REG_NONE; |
73 | } | |
74 | ||
73aa808f CW |
75 | /* some bookkeeping */ |
76 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
77 | size_t size) | |
78 | { | |
79 | dev_priv->mm.object_count++; | |
80 | dev_priv->mm.object_memory += size; | |
81 | } | |
82 | ||
83 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
84 | size_t size) | |
85 | { | |
86 | dev_priv->mm.object_count--; | |
87 | dev_priv->mm.object_memory -= size; | |
88 | } | |
89 | ||
21dd3734 | 90 | static int |
33196ded | 91 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 92 | { |
30dbf0c0 CW |
93 | int ret; |
94 | ||
7abb690a DV |
95 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
96 | i915_terminally_wedged(error)) | |
1f83fee0 | 97 | if (EXIT_COND) |
30dbf0c0 CW |
98 | return 0; |
99 | ||
0a6759c6 DV |
100 | /* |
101 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
102 | * userspace. If it takes that long something really bad is going on and | |
103 | * we should simply try to bail out and fail as gracefully as possible. | |
104 | */ | |
1f83fee0 DV |
105 | ret = wait_event_interruptible_timeout(error->reset_queue, |
106 | EXIT_COND, | |
107 | 10*HZ); | |
0a6759c6 DV |
108 | if (ret == 0) { |
109 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
110 | return -EIO; | |
111 | } else if (ret < 0) { | |
30dbf0c0 | 112 | return ret; |
0a6759c6 | 113 | } |
1f83fee0 | 114 | #undef EXIT_COND |
30dbf0c0 | 115 | |
21dd3734 | 116 | return 0; |
30dbf0c0 CW |
117 | } |
118 | ||
54cf91dc | 119 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 120 | { |
33196ded | 121 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
122 | int ret; |
123 | ||
33196ded | 124 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
125 | if (ret) |
126 | return ret; | |
127 | ||
128 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
129 | if (ret) | |
130 | return ret; | |
131 | ||
23bc5982 | 132 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
133 | return 0; |
134 | } | |
30dbf0c0 | 135 | |
7d1c4804 | 136 | static inline bool |
05394f39 | 137 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 138 | { |
f343c5f6 | 139 | return i915_gem_obj_ggtt_bound(obj) && !obj->active; |
7d1c4804 CW |
140 | } |
141 | ||
79e53945 JB |
142 | int |
143 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 144 | struct drm_file *file) |
79e53945 | 145 | { |
93d18799 | 146 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 147 | struct drm_i915_gem_init *args = data; |
2021746e | 148 | |
7bb6fb8d DV |
149 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
150 | return -ENODEV; | |
151 | ||
2021746e CW |
152 | if (args->gtt_start >= args->gtt_end || |
153 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
154 | return -EINVAL; | |
79e53945 | 155 | |
f534bc0b DV |
156 | /* GEM with user mode setting was never supported on ilk and later. */ |
157 | if (INTEL_INFO(dev)->gen >= 5) | |
158 | return -ENODEV; | |
159 | ||
79e53945 | 160 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
161 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
162 | args->gtt_end); | |
93d18799 | 163 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
164 | mutex_unlock(&dev->struct_mutex); |
165 | ||
2021746e | 166 | return 0; |
673a394b EA |
167 | } |
168 | ||
5a125c3c EA |
169 | int |
170 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 171 | struct drm_file *file) |
5a125c3c | 172 | { |
73aa808f | 173 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 174 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
175 | struct drm_i915_gem_object *obj; |
176 | size_t pinned; | |
5a125c3c | 177 | |
6299f992 | 178 | pinned = 0; |
73aa808f | 179 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 180 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
1b50247a | 181 | if (obj->pin_count) |
f343c5f6 | 182 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 183 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 184 | |
5d4545ae | 185 | args->aper_size = dev_priv->gtt.total; |
0206e353 | 186 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 187 | |
5a125c3c EA |
188 | return 0; |
189 | } | |
190 | ||
42dcedd4 CW |
191 | void *i915_gem_object_alloc(struct drm_device *dev) |
192 | { | |
193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
194 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); | |
195 | } | |
196 | ||
197 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
198 | { | |
199 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
200 | kmem_cache_free(dev_priv->slab, obj); | |
201 | } | |
202 | ||
ff72145b DA |
203 | static int |
204 | i915_gem_create(struct drm_file *file, | |
205 | struct drm_device *dev, | |
206 | uint64_t size, | |
207 | uint32_t *handle_p) | |
673a394b | 208 | { |
05394f39 | 209 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
210 | int ret; |
211 | u32 handle; | |
673a394b | 212 | |
ff72145b | 213 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
214 | if (size == 0) |
215 | return -EINVAL; | |
673a394b EA |
216 | |
217 | /* Allocate the new object */ | |
ff72145b | 218 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
219 | if (obj == NULL) |
220 | return -ENOMEM; | |
221 | ||
05394f39 | 222 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 223 | if (ret) { |
05394f39 CW |
224 | drm_gem_object_release(&obj->base); |
225 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
42dcedd4 | 226 | i915_gem_object_free(obj); |
673a394b | 227 | return ret; |
1dfd9754 | 228 | } |
673a394b | 229 | |
202f2fef | 230 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 231 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
232 | trace_i915_gem_object_create(obj); |
233 | ||
ff72145b | 234 | *handle_p = handle; |
673a394b EA |
235 | return 0; |
236 | } | |
237 | ||
ff72145b DA |
238 | int |
239 | i915_gem_dumb_create(struct drm_file *file, | |
240 | struct drm_device *dev, | |
241 | struct drm_mode_create_dumb *args) | |
242 | { | |
243 | /* have to work out size/pitch and return them */ | |
ed0291fd | 244 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
245 | args->size = args->pitch * args->height; |
246 | return i915_gem_create(file, dev, | |
247 | args->size, &args->handle); | |
248 | } | |
249 | ||
ff72145b DA |
250 | /** |
251 | * Creates a new mm object and returns a handle to it. | |
252 | */ | |
253 | int | |
254 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
255 | struct drm_file *file) | |
256 | { | |
257 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 258 | |
ff72145b DA |
259 | return i915_gem_create(file, dev, |
260 | args->size, &args->handle); | |
261 | } | |
262 | ||
8461d226 DV |
263 | static inline int |
264 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
265 | const char *gpu_vaddr, int gpu_offset, | |
266 | int length) | |
267 | { | |
268 | int ret, cpu_offset = 0; | |
269 | ||
270 | while (length > 0) { | |
271 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
272 | int this_length = min(cacheline_end - gpu_offset, length); | |
273 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
274 | ||
275 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
276 | gpu_vaddr + swizzled_gpu_offset, | |
277 | this_length); | |
278 | if (ret) | |
279 | return ret + length; | |
280 | ||
281 | cpu_offset += this_length; | |
282 | gpu_offset += this_length; | |
283 | length -= this_length; | |
284 | } | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
8c59967c | 289 | static inline int |
4f0c7cfb BW |
290 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
291 | const char __user *cpu_vaddr, | |
8c59967c DV |
292 | int length) |
293 | { | |
294 | int ret, cpu_offset = 0; | |
295 | ||
296 | while (length > 0) { | |
297 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
298 | int this_length = min(cacheline_end - gpu_offset, length); | |
299 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
300 | ||
301 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
302 | cpu_vaddr + cpu_offset, | |
303 | this_length); | |
304 | if (ret) | |
305 | return ret + length; | |
306 | ||
307 | cpu_offset += this_length; | |
308 | gpu_offset += this_length; | |
309 | length -= this_length; | |
310 | } | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
d174bd64 DV |
315 | /* Per-page copy function for the shmem pread fastpath. |
316 | * Flushes invalid cachelines before reading the target if | |
317 | * needs_clflush is set. */ | |
eb01459f | 318 | static int |
d174bd64 DV |
319 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
320 | char __user *user_data, | |
321 | bool page_do_bit17_swizzling, bool needs_clflush) | |
322 | { | |
323 | char *vaddr; | |
324 | int ret; | |
325 | ||
e7e58eb5 | 326 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
327 | return -EINVAL; |
328 | ||
329 | vaddr = kmap_atomic(page); | |
330 | if (needs_clflush) | |
331 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
332 | page_length); | |
333 | ret = __copy_to_user_inatomic(user_data, | |
334 | vaddr + shmem_page_offset, | |
335 | page_length); | |
336 | kunmap_atomic(vaddr); | |
337 | ||
f60d7f0c | 338 | return ret ? -EFAULT : 0; |
d174bd64 DV |
339 | } |
340 | ||
23c18c71 DV |
341 | static void |
342 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
343 | bool swizzled) | |
344 | { | |
e7e58eb5 | 345 | if (unlikely(swizzled)) { |
23c18c71 DV |
346 | unsigned long start = (unsigned long) addr; |
347 | unsigned long end = (unsigned long) addr + length; | |
348 | ||
349 | /* For swizzling simply ensure that we always flush both | |
350 | * channels. Lame, but simple and it works. Swizzled | |
351 | * pwrite/pread is far from a hotpath - current userspace | |
352 | * doesn't use it at all. */ | |
353 | start = round_down(start, 128); | |
354 | end = round_up(end, 128); | |
355 | ||
356 | drm_clflush_virt_range((void *)start, end - start); | |
357 | } else { | |
358 | drm_clflush_virt_range(addr, length); | |
359 | } | |
360 | ||
361 | } | |
362 | ||
d174bd64 DV |
363 | /* Only difference to the fast-path function is that this can handle bit17 |
364 | * and uses non-atomic copy and kmap functions. */ | |
365 | static int | |
366 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
367 | char __user *user_data, | |
368 | bool page_do_bit17_swizzling, bool needs_clflush) | |
369 | { | |
370 | char *vaddr; | |
371 | int ret; | |
372 | ||
373 | vaddr = kmap(page); | |
374 | if (needs_clflush) | |
23c18c71 DV |
375 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
376 | page_length, | |
377 | page_do_bit17_swizzling); | |
d174bd64 DV |
378 | |
379 | if (page_do_bit17_swizzling) | |
380 | ret = __copy_to_user_swizzled(user_data, | |
381 | vaddr, shmem_page_offset, | |
382 | page_length); | |
383 | else | |
384 | ret = __copy_to_user(user_data, | |
385 | vaddr + shmem_page_offset, | |
386 | page_length); | |
387 | kunmap(page); | |
388 | ||
f60d7f0c | 389 | return ret ? - EFAULT : 0; |
d174bd64 DV |
390 | } |
391 | ||
eb01459f | 392 | static int |
dbf7bff0 DV |
393 | i915_gem_shmem_pread(struct drm_device *dev, |
394 | struct drm_i915_gem_object *obj, | |
395 | struct drm_i915_gem_pread *args, | |
396 | struct drm_file *file) | |
eb01459f | 397 | { |
8461d226 | 398 | char __user *user_data; |
eb01459f | 399 | ssize_t remain; |
8461d226 | 400 | loff_t offset; |
eb2c0c81 | 401 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 402 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 403 | int prefaulted = 0; |
8489731c | 404 | int needs_clflush = 0; |
67d5a50c | 405 | struct sg_page_iter sg_iter; |
eb01459f | 406 | |
2bb4629a | 407 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
408 | remain = args->size; |
409 | ||
8461d226 | 410 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 411 | |
8489731c DV |
412 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
413 | /* If we're not in the cpu read domain, set ourself into the gtt | |
414 | * read domain and manually flush cachelines (if required). This | |
415 | * optimizes for the case when the gpu will dirty the data | |
416 | * anyway again before the next pread happens. */ | |
417 | if (obj->cache_level == I915_CACHE_NONE) | |
418 | needs_clflush = 1; | |
f343c5f6 | 419 | if (i915_gem_obj_ggtt_bound(obj)) { |
6c085a72 CW |
420 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
421 | if (ret) | |
422 | return ret; | |
423 | } | |
8489731c | 424 | } |
eb01459f | 425 | |
f60d7f0c CW |
426 | ret = i915_gem_object_get_pages(obj); |
427 | if (ret) | |
428 | return ret; | |
429 | ||
430 | i915_gem_object_pin_pages(obj); | |
431 | ||
8461d226 | 432 | offset = args->offset; |
eb01459f | 433 | |
67d5a50c ID |
434 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
435 | offset >> PAGE_SHIFT) { | |
2db76d7c | 436 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
437 | |
438 | if (remain <= 0) | |
439 | break; | |
440 | ||
eb01459f EA |
441 | /* Operation in this page |
442 | * | |
eb01459f | 443 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
444 | * page_length = bytes to copy for this page |
445 | */ | |
c8cbbb8b | 446 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
447 | page_length = remain; |
448 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
449 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 450 | |
8461d226 DV |
451 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
452 | (page_to_phys(page) & (1 << 17)) != 0; | |
453 | ||
d174bd64 DV |
454 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
455 | user_data, page_do_bit17_swizzling, | |
456 | needs_clflush); | |
457 | if (ret == 0) | |
458 | goto next_page; | |
dbf7bff0 | 459 | |
dbf7bff0 DV |
460 | mutex_unlock(&dev->struct_mutex); |
461 | ||
96d79b52 | 462 | if (!prefaulted) { |
f56f821f | 463 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
464 | /* Userspace is tricking us, but we've already clobbered |
465 | * its pages with the prefault and promised to write the | |
466 | * data up to the first fault. Hence ignore any errors | |
467 | * and just continue. */ | |
468 | (void)ret; | |
469 | prefaulted = 1; | |
470 | } | |
eb01459f | 471 | |
d174bd64 DV |
472 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
473 | user_data, page_do_bit17_swizzling, | |
474 | needs_clflush); | |
eb01459f | 475 | |
dbf7bff0 | 476 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 477 | |
dbf7bff0 | 478 | next_page: |
e5281ccd | 479 | mark_page_accessed(page); |
e5281ccd | 480 | |
f60d7f0c | 481 | if (ret) |
8461d226 | 482 | goto out; |
8461d226 | 483 | |
eb01459f | 484 | remain -= page_length; |
8461d226 | 485 | user_data += page_length; |
eb01459f EA |
486 | offset += page_length; |
487 | } | |
488 | ||
4f27b75d | 489 | out: |
f60d7f0c CW |
490 | i915_gem_object_unpin_pages(obj); |
491 | ||
eb01459f EA |
492 | return ret; |
493 | } | |
494 | ||
673a394b EA |
495 | /** |
496 | * Reads data from the object referenced by handle. | |
497 | * | |
498 | * On error, the contents of *data are undefined. | |
499 | */ | |
500 | int | |
501 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 502 | struct drm_file *file) |
673a394b EA |
503 | { |
504 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 505 | struct drm_i915_gem_object *obj; |
35b62a89 | 506 | int ret = 0; |
673a394b | 507 | |
51311d0a CW |
508 | if (args->size == 0) |
509 | return 0; | |
510 | ||
511 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 512 | to_user_ptr(args->data_ptr), |
51311d0a CW |
513 | args->size)) |
514 | return -EFAULT; | |
515 | ||
4f27b75d | 516 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 517 | if (ret) |
4f27b75d | 518 | return ret; |
673a394b | 519 | |
05394f39 | 520 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 521 | if (&obj->base == NULL) { |
1d7cfea1 CW |
522 | ret = -ENOENT; |
523 | goto unlock; | |
4f27b75d | 524 | } |
673a394b | 525 | |
7dcd2499 | 526 | /* Bounds check source. */ |
05394f39 CW |
527 | if (args->offset > obj->base.size || |
528 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 529 | ret = -EINVAL; |
35b62a89 | 530 | goto out; |
ce9d419d CW |
531 | } |
532 | ||
1286ff73 DV |
533 | /* prime objects have no backing filp to GEM pread/pwrite |
534 | * pages from. | |
535 | */ | |
536 | if (!obj->base.filp) { | |
537 | ret = -EINVAL; | |
538 | goto out; | |
539 | } | |
540 | ||
db53a302 CW |
541 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
542 | ||
dbf7bff0 | 543 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 544 | |
35b62a89 | 545 | out: |
05394f39 | 546 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 547 | unlock: |
4f27b75d | 548 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 549 | return ret; |
673a394b EA |
550 | } |
551 | ||
0839ccb8 KP |
552 | /* This is the fast write path which cannot handle |
553 | * page faults in the source data | |
9b7530cc | 554 | */ |
0839ccb8 KP |
555 | |
556 | static inline int | |
557 | fast_user_write(struct io_mapping *mapping, | |
558 | loff_t page_base, int page_offset, | |
559 | char __user *user_data, | |
560 | int length) | |
9b7530cc | 561 | { |
4f0c7cfb BW |
562 | void __iomem *vaddr_atomic; |
563 | void *vaddr; | |
0839ccb8 | 564 | unsigned long unwritten; |
9b7530cc | 565 | |
3e4d3af5 | 566 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
567 | /* We can use the cpu mem copy function because this is X86. */ |
568 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
569 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 570 | user_data, length); |
3e4d3af5 | 571 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 572 | return unwritten; |
0839ccb8 KP |
573 | } |
574 | ||
3de09aa3 EA |
575 | /** |
576 | * This is the fast pwrite path, where we copy the data directly from the | |
577 | * user into the GTT, uncached. | |
578 | */ | |
673a394b | 579 | static int |
05394f39 CW |
580 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
581 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 582 | struct drm_i915_gem_pwrite *args, |
05394f39 | 583 | struct drm_file *file) |
673a394b | 584 | { |
0839ccb8 | 585 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 586 | ssize_t remain; |
0839ccb8 | 587 | loff_t offset, page_base; |
673a394b | 588 | char __user *user_data; |
935aaa69 DV |
589 | int page_offset, page_length, ret; |
590 | ||
86a1ee26 | 591 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
592 | if (ret) |
593 | goto out; | |
594 | ||
595 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
596 | if (ret) | |
597 | goto out_unpin; | |
598 | ||
599 | ret = i915_gem_object_put_fence(obj); | |
600 | if (ret) | |
601 | goto out_unpin; | |
673a394b | 602 | |
2bb4629a | 603 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 604 | remain = args->size; |
673a394b | 605 | |
f343c5f6 | 606 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
607 | |
608 | while (remain > 0) { | |
609 | /* Operation in this page | |
610 | * | |
0839ccb8 KP |
611 | * page_base = page offset within aperture |
612 | * page_offset = offset within page | |
613 | * page_length = bytes to copy for this page | |
673a394b | 614 | */ |
c8cbbb8b CW |
615 | page_base = offset & PAGE_MASK; |
616 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
617 | page_length = remain; |
618 | if ((page_offset + remain) > PAGE_SIZE) | |
619 | page_length = PAGE_SIZE - page_offset; | |
620 | ||
0839ccb8 | 621 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
622 | * source page isn't available. Return the error and we'll |
623 | * retry in the slow path. | |
0839ccb8 | 624 | */ |
5d4545ae | 625 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
626 | page_offset, user_data, page_length)) { |
627 | ret = -EFAULT; | |
628 | goto out_unpin; | |
629 | } | |
673a394b | 630 | |
0839ccb8 KP |
631 | remain -= page_length; |
632 | user_data += page_length; | |
633 | offset += page_length; | |
673a394b | 634 | } |
673a394b | 635 | |
935aaa69 DV |
636 | out_unpin: |
637 | i915_gem_object_unpin(obj); | |
638 | out: | |
3de09aa3 | 639 | return ret; |
673a394b EA |
640 | } |
641 | ||
d174bd64 DV |
642 | /* Per-page copy function for the shmem pwrite fastpath. |
643 | * Flushes invalid cachelines before writing to the target if | |
644 | * needs_clflush_before is set and flushes out any written cachelines after | |
645 | * writing if needs_clflush is set. */ | |
3043c60c | 646 | static int |
d174bd64 DV |
647 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
648 | char __user *user_data, | |
649 | bool page_do_bit17_swizzling, | |
650 | bool needs_clflush_before, | |
651 | bool needs_clflush_after) | |
673a394b | 652 | { |
d174bd64 | 653 | char *vaddr; |
673a394b | 654 | int ret; |
3de09aa3 | 655 | |
e7e58eb5 | 656 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 657 | return -EINVAL; |
3de09aa3 | 658 | |
d174bd64 DV |
659 | vaddr = kmap_atomic(page); |
660 | if (needs_clflush_before) | |
661 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
662 | page_length); | |
663 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
664 | user_data, | |
665 | page_length); | |
666 | if (needs_clflush_after) | |
667 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
668 | page_length); | |
669 | kunmap_atomic(vaddr); | |
3de09aa3 | 670 | |
755d2218 | 671 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
672 | } |
673 | ||
d174bd64 DV |
674 | /* Only difference to the fast-path function is that this can handle bit17 |
675 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 676 | static int |
d174bd64 DV |
677 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
678 | char __user *user_data, | |
679 | bool page_do_bit17_swizzling, | |
680 | bool needs_clflush_before, | |
681 | bool needs_clflush_after) | |
673a394b | 682 | { |
d174bd64 DV |
683 | char *vaddr; |
684 | int ret; | |
e5281ccd | 685 | |
d174bd64 | 686 | vaddr = kmap(page); |
e7e58eb5 | 687 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
688 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
689 | page_length, | |
690 | page_do_bit17_swizzling); | |
d174bd64 DV |
691 | if (page_do_bit17_swizzling) |
692 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
693 | user_data, |
694 | page_length); | |
d174bd64 DV |
695 | else |
696 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
697 | user_data, | |
698 | page_length); | |
699 | if (needs_clflush_after) | |
23c18c71 DV |
700 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
701 | page_length, | |
702 | page_do_bit17_swizzling); | |
d174bd64 | 703 | kunmap(page); |
40123c1f | 704 | |
755d2218 | 705 | return ret ? -EFAULT : 0; |
40123c1f EA |
706 | } |
707 | ||
40123c1f | 708 | static int |
e244a443 DV |
709 | i915_gem_shmem_pwrite(struct drm_device *dev, |
710 | struct drm_i915_gem_object *obj, | |
711 | struct drm_i915_gem_pwrite *args, | |
712 | struct drm_file *file) | |
40123c1f | 713 | { |
40123c1f | 714 | ssize_t remain; |
8c59967c DV |
715 | loff_t offset; |
716 | char __user *user_data; | |
eb2c0c81 | 717 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 718 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 719 | int hit_slowpath = 0; |
58642885 DV |
720 | int needs_clflush_after = 0; |
721 | int needs_clflush_before = 0; | |
67d5a50c | 722 | struct sg_page_iter sg_iter; |
40123c1f | 723 | |
2bb4629a | 724 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
725 | remain = args->size; |
726 | ||
8c59967c | 727 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 728 | |
58642885 DV |
729 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
730 | /* If we're not in the cpu write domain, set ourself into the gtt | |
731 | * write domain and manually flush cachelines (if required). This | |
732 | * optimizes for the case when the gpu will use the data | |
733 | * right away and we therefore have to clflush anyway. */ | |
734 | if (obj->cache_level == I915_CACHE_NONE) | |
735 | needs_clflush_after = 1; | |
f343c5f6 | 736 | if (i915_gem_obj_ggtt_bound(obj)) { |
6c085a72 CW |
737 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
738 | if (ret) | |
739 | return ret; | |
740 | } | |
58642885 DV |
741 | } |
742 | /* Same trick applies for invalidate partially written cachelines before | |
743 | * writing. */ | |
744 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
745 | && obj->cache_level == I915_CACHE_NONE) | |
746 | needs_clflush_before = 1; | |
747 | ||
755d2218 CW |
748 | ret = i915_gem_object_get_pages(obj); |
749 | if (ret) | |
750 | return ret; | |
751 | ||
752 | i915_gem_object_pin_pages(obj); | |
753 | ||
673a394b | 754 | offset = args->offset; |
05394f39 | 755 | obj->dirty = 1; |
673a394b | 756 | |
67d5a50c ID |
757 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
758 | offset >> PAGE_SHIFT) { | |
2db76d7c | 759 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 760 | int partial_cacheline_write; |
e5281ccd | 761 | |
9da3da66 CW |
762 | if (remain <= 0) |
763 | break; | |
764 | ||
40123c1f EA |
765 | /* Operation in this page |
766 | * | |
40123c1f | 767 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
768 | * page_length = bytes to copy for this page |
769 | */ | |
c8cbbb8b | 770 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
771 | |
772 | page_length = remain; | |
773 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
774 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 775 | |
58642885 DV |
776 | /* If we don't overwrite a cacheline completely we need to be |
777 | * careful to have up-to-date data by first clflushing. Don't | |
778 | * overcomplicate things and flush the entire patch. */ | |
779 | partial_cacheline_write = needs_clflush_before && | |
780 | ((shmem_page_offset | page_length) | |
781 | & (boot_cpu_data.x86_clflush_size - 1)); | |
782 | ||
8c59967c DV |
783 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
784 | (page_to_phys(page) & (1 << 17)) != 0; | |
785 | ||
d174bd64 DV |
786 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
787 | user_data, page_do_bit17_swizzling, | |
788 | partial_cacheline_write, | |
789 | needs_clflush_after); | |
790 | if (ret == 0) | |
791 | goto next_page; | |
e244a443 DV |
792 | |
793 | hit_slowpath = 1; | |
e244a443 | 794 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
795 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
796 | user_data, page_do_bit17_swizzling, | |
797 | partial_cacheline_write, | |
798 | needs_clflush_after); | |
40123c1f | 799 | |
e244a443 | 800 | mutex_lock(&dev->struct_mutex); |
755d2218 | 801 | |
e244a443 | 802 | next_page: |
e5281ccd CW |
803 | set_page_dirty(page); |
804 | mark_page_accessed(page); | |
e5281ccd | 805 | |
755d2218 | 806 | if (ret) |
8c59967c | 807 | goto out; |
8c59967c | 808 | |
40123c1f | 809 | remain -= page_length; |
8c59967c | 810 | user_data += page_length; |
40123c1f | 811 | offset += page_length; |
673a394b EA |
812 | } |
813 | ||
fbd5a26d | 814 | out: |
755d2218 CW |
815 | i915_gem_object_unpin_pages(obj); |
816 | ||
e244a443 | 817 | if (hit_slowpath) { |
8dcf015e DV |
818 | /* |
819 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
820 | * cachelines in-line while writing and the object moved | |
821 | * out of the cpu write domain while we've dropped the lock. | |
822 | */ | |
823 | if (!needs_clflush_after && | |
824 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
e244a443 | 825 | i915_gem_clflush_object(obj); |
e76e9aeb | 826 | i915_gem_chipset_flush(dev); |
e244a443 | 827 | } |
8c59967c | 828 | } |
673a394b | 829 | |
58642885 | 830 | if (needs_clflush_after) |
e76e9aeb | 831 | i915_gem_chipset_flush(dev); |
58642885 | 832 | |
40123c1f | 833 | return ret; |
673a394b EA |
834 | } |
835 | ||
836 | /** | |
837 | * Writes data to the object referenced by handle. | |
838 | * | |
839 | * On error, the contents of the buffer that were to be modified are undefined. | |
840 | */ | |
841 | int | |
842 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 843 | struct drm_file *file) |
673a394b EA |
844 | { |
845 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 846 | struct drm_i915_gem_object *obj; |
51311d0a CW |
847 | int ret; |
848 | ||
849 | if (args->size == 0) | |
850 | return 0; | |
851 | ||
852 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 853 | to_user_ptr(args->data_ptr), |
51311d0a CW |
854 | args->size)) |
855 | return -EFAULT; | |
856 | ||
2bb4629a | 857 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
f56f821f | 858 | args->size); |
51311d0a CW |
859 | if (ret) |
860 | return -EFAULT; | |
673a394b | 861 | |
fbd5a26d | 862 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 863 | if (ret) |
fbd5a26d | 864 | return ret; |
1d7cfea1 | 865 | |
05394f39 | 866 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 867 | if (&obj->base == NULL) { |
1d7cfea1 CW |
868 | ret = -ENOENT; |
869 | goto unlock; | |
fbd5a26d | 870 | } |
673a394b | 871 | |
7dcd2499 | 872 | /* Bounds check destination. */ |
05394f39 CW |
873 | if (args->offset > obj->base.size || |
874 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 875 | ret = -EINVAL; |
35b62a89 | 876 | goto out; |
ce9d419d CW |
877 | } |
878 | ||
1286ff73 DV |
879 | /* prime objects have no backing filp to GEM pread/pwrite |
880 | * pages from. | |
881 | */ | |
882 | if (!obj->base.filp) { | |
883 | ret = -EINVAL; | |
884 | goto out; | |
885 | } | |
886 | ||
db53a302 CW |
887 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
888 | ||
935aaa69 | 889 | ret = -EFAULT; |
673a394b EA |
890 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
891 | * it would end up going through the fenced access, and we'll get | |
892 | * different detiling behavior between reading and writing. | |
893 | * pread/pwrite currently are reading and writing from the CPU | |
894 | * perspective, requiring manual detiling by the client. | |
895 | */ | |
5c0480f2 | 896 | if (obj->phys_obj) { |
fbd5a26d | 897 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
898 | goto out; |
899 | } | |
900 | ||
86a1ee26 | 901 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 902 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 903 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 904 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
905 | /* Note that the gtt paths might fail with non-page-backed user |
906 | * pointers (e.g. gtt mappings when moving data between | |
907 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 908 | } |
673a394b | 909 | |
86a1ee26 | 910 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 911 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 912 | |
35b62a89 | 913 | out: |
05394f39 | 914 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 915 | unlock: |
fbd5a26d | 916 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
917 | return ret; |
918 | } | |
919 | ||
b361237b | 920 | int |
33196ded | 921 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
922 | bool interruptible) |
923 | { | |
1f83fee0 | 924 | if (i915_reset_in_progress(error)) { |
b361237b CW |
925 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
926 | * -EIO unconditionally for these. */ | |
927 | if (!interruptible) | |
928 | return -EIO; | |
929 | ||
1f83fee0 DV |
930 | /* Recovery complete, but the reset failed ... */ |
931 | if (i915_terminally_wedged(error)) | |
b361237b CW |
932 | return -EIO; |
933 | ||
934 | return -EAGAIN; | |
935 | } | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | /* | |
941 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
942 | * equal. | |
943 | */ | |
944 | static int | |
945 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
946 | { | |
947 | int ret; | |
948 | ||
949 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
950 | ||
951 | ret = 0; | |
952 | if (seqno == ring->outstanding_lazy_request) | |
0025c077 | 953 | ret = i915_add_request(ring, NULL); |
b361237b CW |
954 | |
955 | return ret; | |
956 | } | |
957 | ||
958 | /** | |
959 | * __wait_seqno - wait until execution of seqno has finished | |
960 | * @ring: the ring expected to report seqno | |
961 | * @seqno: duh! | |
f69061be | 962 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
963 | * @interruptible: do an interruptible wait (normally yes) |
964 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
965 | * | |
f69061be DV |
966 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
967 | * values have been read by the caller in an smp safe manner. Where read-side | |
968 | * locks are involved, it is sufficient to read the reset_counter before | |
969 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
970 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
971 | * inserted. | |
972 | * | |
b361237b CW |
973 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
974 | * errno with remaining time filled in timeout argument. | |
975 | */ | |
976 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 977 | unsigned reset_counter, |
b361237b CW |
978 | bool interruptible, struct timespec *timeout) |
979 | { | |
980 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
981 | struct timespec before, now, wait_time={1,0}; | |
982 | unsigned long timeout_jiffies; | |
983 | long end; | |
984 | bool wait_forever = true; | |
985 | int ret; | |
986 | ||
987 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
988 | return 0; | |
989 | ||
990 | trace_i915_gem_request_wait_begin(ring, seqno); | |
991 | ||
992 | if (timeout != NULL) { | |
993 | wait_time = *timeout; | |
994 | wait_forever = false; | |
995 | } | |
996 | ||
e054cc39 | 997 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
b361237b CW |
998 | |
999 | if (WARN_ON(!ring->irq_get(ring))) | |
1000 | return -ENODEV; | |
1001 | ||
1002 | /* Record current time in case interrupted by signal, or wedged * */ | |
1003 | getrawmonotonic(&before); | |
1004 | ||
1005 | #define EXIT_COND \ | |
1006 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
f69061be DV |
1007 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1008 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
b361237b CW |
1009 | do { |
1010 | if (interruptible) | |
1011 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1012 | EXIT_COND, | |
1013 | timeout_jiffies); | |
1014 | else | |
1015 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1016 | timeout_jiffies); | |
1017 | ||
f69061be DV |
1018 | /* We need to check whether any gpu reset happened in between |
1019 | * the caller grabbing the seqno and now ... */ | |
1020 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
1021 | end = -EAGAIN; | |
1022 | ||
1023 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely | |
1024 | * gone. */ | |
33196ded | 1025 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1026 | if (ret) |
1027 | end = ret; | |
1028 | } while (end == 0 && wait_forever); | |
1029 | ||
1030 | getrawmonotonic(&now); | |
1031 | ||
1032 | ring->irq_put(ring); | |
1033 | trace_i915_gem_request_wait_end(ring, seqno); | |
1034 | #undef EXIT_COND | |
1035 | ||
1036 | if (timeout) { | |
1037 | struct timespec sleep_time = timespec_sub(now, before); | |
1038 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1039 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1040 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1041 | } |
1042 | ||
1043 | switch (end) { | |
1044 | case -EIO: | |
1045 | case -EAGAIN: /* Wedged */ | |
1046 | case -ERESTARTSYS: /* Signal */ | |
1047 | return (int)end; | |
1048 | case 0: /* Timeout */ | |
b361237b CW |
1049 | return -ETIME; |
1050 | default: /* Completed */ | |
1051 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1052 | return 0; | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | /** | |
1057 | * Waits for a sequence number to be signaled, and cleans up the | |
1058 | * request and object lists appropriately for that event. | |
1059 | */ | |
1060 | int | |
1061 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1062 | { | |
1063 | struct drm_device *dev = ring->dev; | |
1064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1065 | bool interruptible = dev_priv->mm.interruptible; | |
1066 | int ret; | |
1067 | ||
1068 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1069 | BUG_ON(seqno == 0); | |
1070 | ||
33196ded | 1071 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1072 | if (ret) |
1073 | return ret; | |
1074 | ||
1075 | ret = i915_gem_check_olr(ring, seqno); | |
1076 | if (ret) | |
1077 | return ret; | |
1078 | ||
f69061be DV |
1079 | return __wait_seqno(ring, seqno, |
1080 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
1081 | interruptible, NULL); | |
b361237b CW |
1082 | } |
1083 | ||
d26e3af8 CW |
1084 | static int |
1085 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1086 | struct intel_ring_buffer *ring) | |
1087 | { | |
1088 | i915_gem_retire_requests_ring(ring); | |
1089 | ||
1090 | /* Manually manage the write flush as we may have not yet | |
1091 | * retired the buffer. | |
1092 | * | |
1093 | * Note that the last_write_seqno is always the earlier of | |
1094 | * the two (read/write) seqno, so if we haved successfully waited, | |
1095 | * we know we have passed the last write. | |
1096 | */ | |
1097 | obj->last_write_seqno = 0; | |
1098 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
b361237b CW |
1103 | /** |
1104 | * Ensures that all rendering to the object has completed and the object is | |
1105 | * safe to unbind from the GTT or access from the CPU. | |
1106 | */ | |
1107 | static __must_check int | |
1108 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1109 | bool readonly) | |
1110 | { | |
1111 | struct intel_ring_buffer *ring = obj->ring; | |
1112 | u32 seqno; | |
1113 | int ret; | |
1114 | ||
1115 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1116 | if (seqno == 0) | |
1117 | return 0; | |
1118 | ||
1119 | ret = i915_wait_seqno(ring, seqno); | |
1120 | if (ret) | |
1121 | return ret; | |
1122 | ||
d26e3af8 | 1123 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1124 | } |
1125 | ||
3236f57a CW |
1126 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1127 | * as the object state may change during this call. | |
1128 | */ | |
1129 | static __must_check int | |
1130 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1131 | bool readonly) | |
1132 | { | |
1133 | struct drm_device *dev = obj->base.dev; | |
1134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1135 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1136 | unsigned reset_counter; |
3236f57a CW |
1137 | u32 seqno; |
1138 | int ret; | |
1139 | ||
1140 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1141 | BUG_ON(!dev_priv->mm.interruptible); | |
1142 | ||
1143 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1144 | if (seqno == 0) | |
1145 | return 0; | |
1146 | ||
33196ded | 1147 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1148 | if (ret) |
1149 | return ret; | |
1150 | ||
1151 | ret = i915_gem_check_olr(ring, seqno); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | ||
f69061be | 1155 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1156 | mutex_unlock(&dev->struct_mutex); |
f69061be | 1157 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3236f57a | 1158 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1159 | if (ret) |
1160 | return ret; | |
3236f57a | 1161 | |
d26e3af8 | 1162 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1163 | } |
1164 | ||
673a394b | 1165 | /** |
2ef7eeaa EA |
1166 | * Called when user space prepares to use an object with the CPU, either |
1167 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1168 | */ |
1169 | int | |
1170 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1171 | struct drm_file *file) |
673a394b EA |
1172 | { |
1173 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1174 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1175 | uint32_t read_domains = args->read_domains; |
1176 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1177 | int ret; |
1178 | ||
2ef7eeaa | 1179 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1180 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1181 | return -EINVAL; |
1182 | ||
21d509e3 | 1183 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1184 | return -EINVAL; |
1185 | ||
1186 | /* Having something in the write domain implies it's in the read | |
1187 | * domain, and only that read domain. Enforce that in the request. | |
1188 | */ | |
1189 | if (write_domain != 0 && read_domains != write_domain) | |
1190 | return -EINVAL; | |
1191 | ||
76c1dec1 | 1192 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1193 | if (ret) |
76c1dec1 | 1194 | return ret; |
1d7cfea1 | 1195 | |
05394f39 | 1196 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1197 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1198 | ret = -ENOENT; |
1199 | goto unlock; | |
76c1dec1 | 1200 | } |
673a394b | 1201 | |
3236f57a CW |
1202 | /* Try to flush the object off the GPU without holding the lock. |
1203 | * We will repeat the flush holding the lock in the normal manner | |
1204 | * to catch cases where we are gazumped. | |
1205 | */ | |
1206 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1207 | if (ret) | |
1208 | goto unref; | |
1209 | ||
2ef7eeaa EA |
1210 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1211 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1212 | |
1213 | /* Silently promote "you're not bound, there was nothing to do" | |
1214 | * to success, since the client was just asking us to | |
1215 | * make sure everything was done. | |
1216 | */ | |
1217 | if (ret == -EINVAL) | |
1218 | ret = 0; | |
2ef7eeaa | 1219 | } else { |
e47c68e9 | 1220 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1221 | } |
1222 | ||
3236f57a | 1223 | unref: |
05394f39 | 1224 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1225 | unlock: |
673a394b EA |
1226 | mutex_unlock(&dev->struct_mutex); |
1227 | return ret; | |
1228 | } | |
1229 | ||
1230 | /** | |
1231 | * Called when user space has done writes to this buffer | |
1232 | */ | |
1233 | int | |
1234 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1235 | struct drm_file *file) |
673a394b EA |
1236 | { |
1237 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1238 | struct drm_i915_gem_object *obj; |
673a394b EA |
1239 | int ret = 0; |
1240 | ||
76c1dec1 | 1241 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1242 | if (ret) |
76c1dec1 | 1243 | return ret; |
1d7cfea1 | 1244 | |
05394f39 | 1245 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1246 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1247 | ret = -ENOENT; |
1248 | goto unlock; | |
673a394b EA |
1249 | } |
1250 | ||
673a394b | 1251 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1252 | if (obj->pin_count) |
e47c68e9 EA |
1253 | i915_gem_object_flush_cpu_write_domain(obj); |
1254 | ||
05394f39 | 1255 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1256 | unlock: |
673a394b EA |
1257 | mutex_unlock(&dev->struct_mutex); |
1258 | return ret; | |
1259 | } | |
1260 | ||
1261 | /** | |
1262 | * Maps the contents of an object, returning the address it is mapped | |
1263 | * into. | |
1264 | * | |
1265 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1266 | * imply a ref on the object itself. | |
1267 | */ | |
1268 | int | |
1269 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1270 | struct drm_file *file) |
673a394b EA |
1271 | { |
1272 | struct drm_i915_gem_mmap *args = data; | |
1273 | struct drm_gem_object *obj; | |
673a394b EA |
1274 | unsigned long addr; |
1275 | ||
05394f39 | 1276 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1277 | if (obj == NULL) |
bf79cb91 | 1278 | return -ENOENT; |
673a394b | 1279 | |
1286ff73 DV |
1280 | /* prime objects have no backing filp to GEM mmap |
1281 | * pages from. | |
1282 | */ | |
1283 | if (!obj->filp) { | |
1284 | drm_gem_object_unreference_unlocked(obj); | |
1285 | return -EINVAL; | |
1286 | } | |
1287 | ||
6be5ceb0 | 1288 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1289 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1290 | args->offset); | |
bc9025bd | 1291 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1292 | if (IS_ERR((void *)addr)) |
1293 | return addr; | |
1294 | ||
1295 | args->addr_ptr = (uint64_t) addr; | |
1296 | ||
1297 | return 0; | |
1298 | } | |
1299 | ||
de151cf6 JB |
1300 | /** |
1301 | * i915_gem_fault - fault a page into the GTT | |
1302 | * vma: VMA in question | |
1303 | * vmf: fault info | |
1304 | * | |
1305 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1306 | * from userspace. The fault handler takes care of binding the object to | |
1307 | * the GTT (if needed), allocating and programming a fence register (again, | |
1308 | * only if needed based on whether the old reg is still valid or the object | |
1309 | * is tiled) and inserting a new PTE into the faulting process. | |
1310 | * | |
1311 | * Note that the faulting process may involve evicting existing objects | |
1312 | * from the GTT and/or fence registers to make room. So performance may | |
1313 | * suffer if the GTT working set is large or there are few fence registers | |
1314 | * left. | |
1315 | */ | |
1316 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1317 | { | |
05394f39 CW |
1318 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1319 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1320 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1321 | pgoff_t page_offset; |
1322 | unsigned long pfn; | |
1323 | int ret = 0; | |
0f973f27 | 1324 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1325 | |
1326 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1327 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1328 | PAGE_SHIFT; | |
1329 | ||
d9bc7e9f CW |
1330 | ret = i915_mutex_lock_interruptible(dev); |
1331 | if (ret) | |
1332 | goto out; | |
a00b10c3 | 1333 | |
db53a302 CW |
1334 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1335 | ||
eb119bd6 CW |
1336 | /* Access to snoopable pages through the GTT is incoherent. */ |
1337 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1338 | ret = -EINVAL; | |
1339 | goto unlock; | |
1340 | } | |
1341 | ||
d9bc7e9f | 1342 | /* Now bind it into the GTT if needed */ |
c9839303 CW |
1343 | ret = i915_gem_object_pin(obj, 0, true, false); |
1344 | if (ret) | |
1345 | goto unlock; | |
4a684a41 | 1346 | |
c9839303 CW |
1347 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1348 | if (ret) | |
1349 | goto unpin; | |
74898d7e | 1350 | |
06d98131 | 1351 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1352 | if (ret) |
c9839303 | 1353 | goto unpin; |
7d1c4804 | 1354 | |
6299f992 CW |
1355 | obj->fault_mappable = true; |
1356 | ||
f343c5f6 BW |
1357 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1358 | pfn >>= PAGE_SHIFT; | |
1359 | pfn += page_offset; | |
de151cf6 JB |
1360 | |
1361 | /* Finally, remap it using the new GTT offset */ | |
1362 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1363 | unpin: |
1364 | i915_gem_object_unpin(obj); | |
c715089f | 1365 | unlock: |
de151cf6 | 1366 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1367 | out: |
de151cf6 | 1368 | switch (ret) { |
d9bc7e9f | 1369 | case -EIO: |
a9340cca DV |
1370 | /* If this -EIO is due to a gpu hang, give the reset code a |
1371 | * chance to clean up the mess. Otherwise return the proper | |
1372 | * SIGBUS. */ | |
1f83fee0 | 1373 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1374 | return VM_FAULT_SIGBUS; |
045e769a | 1375 | case -EAGAIN: |
d9bc7e9f CW |
1376 | /* Give the error handler a chance to run and move the |
1377 | * objects off the GPU active list. Next time we service the | |
1378 | * fault, we should be able to transition the page into the | |
1379 | * GTT without touching the GPU (and so avoid further | |
1380 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1381 | * with coherency, just lost writes. | |
1382 | */ | |
045e769a | 1383 | set_need_resched(); |
c715089f CW |
1384 | case 0: |
1385 | case -ERESTARTSYS: | |
bed636ab | 1386 | case -EINTR: |
e79e0fe3 DR |
1387 | case -EBUSY: |
1388 | /* | |
1389 | * EBUSY is ok: this just means that another thread | |
1390 | * already did the job. | |
1391 | */ | |
c715089f | 1392 | return VM_FAULT_NOPAGE; |
de151cf6 | 1393 | case -ENOMEM: |
de151cf6 | 1394 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1395 | case -ENOSPC: |
1396 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1397 | default: |
a7c2e1aa | 1398 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1399 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1400 | } |
1401 | } | |
1402 | ||
901782b2 CW |
1403 | /** |
1404 | * i915_gem_release_mmap - remove physical page mappings | |
1405 | * @obj: obj in question | |
1406 | * | |
af901ca1 | 1407 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1408 | * relinquish ownership of the pages back to the system. |
1409 | * | |
1410 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1411 | * object through the GTT and then lose the fence register due to | |
1412 | * resource pressure. Similarly if the object has been moved out of the | |
1413 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1414 | * mapping will then trigger a page fault on the next user access, allowing | |
1415 | * fixup by i915_gem_fault(). | |
1416 | */ | |
d05ca301 | 1417 | void |
05394f39 | 1418 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1419 | { |
6299f992 CW |
1420 | if (!obj->fault_mappable) |
1421 | return; | |
901782b2 | 1422 | |
51335df9 | 1423 | drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
6299f992 | 1424 | obj->fault_mappable = false; |
901782b2 CW |
1425 | } |
1426 | ||
0fa87796 | 1427 | uint32_t |
e28f8711 | 1428 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1429 | { |
e28f8711 | 1430 | uint32_t gtt_size; |
92b88aeb CW |
1431 | |
1432 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1433 | tiling_mode == I915_TILING_NONE) |
1434 | return size; | |
92b88aeb CW |
1435 | |
1436 | /* Previous chips need a power-of-two fence region when tiling */ | |
1437 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1438 | gtt_size = 1024*1024; |
92b88aeb | 1439 | else |
e28f8711 | 1440 | gtt_size = 512*1024; |
92b88aeb | 1441 | |
e28f8711 CW |
1442 | while (gtt_size < size) |
1443 | gtt_size <<= 1; | |
92b88aeb | 1444 | |
e28f8711 | 1445 | return gtt_size; |
92b88aeb CW |
1446 | } |
1447 | ||
de151cf6 JB |
1448 | /** |
1449 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1450 | * @obj: object to check | |
1451 | * | |
1452 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1453 | * potential fence register mapping. |
de151cf6 | 1454 | */ |
d865110c ID |
1455 | uint32_t |
1456 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1457 | int tiling_mode, bool fenced) | |
de151cf6 | 1458 | { |
de151cf6 JB |
1459 | /* |
1460 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1461 | * if a fence register is needed for the object. | |
1462 | */ | |
d865110c | 1463 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1464 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1465 | return 4096; |
1466 | ||
a00b10c3 CW |
1467 | /* |
1468 | * Previous chips need to be aligned to the size of the smallest | |
1469 | * fence register that can contain the object. | |
1470 | */ | |
e28f8711 | 1471 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1472 | } |
1473 | ||
d8cb5086 CW |
1474 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1475 | { | |
1476 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1477 | int ret; | |
1478 | ||
0de23977 | 1479 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1480 | return 0; |
1481 | ||
da494d7c DV |
1482 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1483 | ||
d8cb5086 CW |
1484 | ret = drm_gem_create_mmap_offset(&obj->base); |
1485 | if (ret != -ENOSPC) | |
da494d7c | 1486 | goto out; |
d8cb5086 CW |
1487 | |
1488 | /* Badly fragmented mmap space? The only way we can recover | |
1489 | * space is by destroying unwanted objects. We can't randomly release | |
1490 | * mmap_offsets as userspace expects them to be persistent for the | |
1491 | * lifetime of the objects. The closest we can is to release the | |
1492 | * offsets on purgeable objects by truncating it and marking it purged, | |
1493 | * which prevents userspace from ever using that object again. | |
1494 | */ | |
1495 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1496 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1497 | if (ret != -ENOSPC) | |
da494d7c | 1498 | goto out; |
d8cb5086 CW |
1499 | |
1500 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1501 | ret = drm_gem_create_mmap_offset(&obj->base); |
1502 | out: | |
1503 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1504 | ||
1505 | return ret; | |
d8cb5086 CW |
1506 | } |
1507 | ||
1508 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1509 | { | |
d8cb5086 CW |
1510 | drm_gem_free_mmap_offset(&obj->base); |
1511 | } | |
1512 | ||
de151cf6 | 1513 | int |
ff72145b DA |
1514 | i915_gem_mmap_gtt(struct drm_file *file, |
1515 | struct drm_device *dev, | |
1516 | uint32_t handle, | |
1517 | uint64_t *offset) | |
de151cf6 | 1518 | { |
da761a6e | 1519 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1520 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1521 | int ret; |
1522 | ||
76c1dec1 | 1523 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1524 | if (ret) |
76c1dec1 | 1525 | return ret; |
de151cf6 | 1526 | |
ff72145b | 1527 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1528 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1529 | ret = -ENOENT; |
1530 | goto unlock; | |
1531 | } | |
de151cf6 | 1532 | |
5d4545ae | 1533 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1534 | ret = -E2BIG; |
ff56b0bc | 1535 | goto out; |
da761a6e CW |
1536 | } |
1537 | ||
05394f39 | 1538 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1539 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1540 | ret = -EINVAL; |
1541 | goto out; | |
ab18282d CW |
1542 | } |
1543 | ||
d8cb5086 CW |
1544 | ret = i915_gem_object_create_mmap_offset(obj); |
1545 | if (ret) | |
1546 | goto out; | |
de151cf6 | 1547 | |
0de23977 | 1548 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1549 | |
1d7cfea1 | 1550 | out: |
05394f39 | 1551 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1552 | unlock: |
de151cf6 | 1553 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1554 | return ret; |
de151cf6 JB |
1555 | } |
1556 | ||
ff72145b DA |
1557 | /** |
1558 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1559 | * @dev: DRM device | |
1560 | * @data: GTT mapping ioctl data | |
1561 | * @file: GEM object info | |
1562 | * | |
1563 | * Simply returns the fake offset to userspace so it can mmap it. | |
1564 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1565 | * up so we can get faults in the handler above. | |
1566 | * | |
1567 | * The fault handler will take care of binding the object into the GTT | |
1568 | * (since it may have been evicted to make room for something), allocating | |
1569 | * a fence register, and mapping the appropriate aperture address into | |
1570 | * userspace. | |
1571 | */ | |
1572 | int | |
1573 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1574 | struct drm_file *file) | |
1575 | { | |
1576 | struct drm_i915_gem_mmap_gtt *args = data; | |
1577 | ||
ff72145b DA |
1578 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1579 | } | |
1580 | ||
225067ee DV |
1581 | /* Immediately discard the backing storage */ |
1582 | static void | |
1583 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1584 | { |
e5281ccd | 1585 | struct inode *inode; |
e5281ccd | 1586 | |
4d6294bf | 1587 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1588 | |
4d6294bf CW |
1589 | if (obj->base.filp == NULL) |
1590 | return; | |
e5281ccd | 1591 | |
225067ee DV |
1592 | /* Our goal here is to return as much of the memory as |
1593 | * is possible back to the system as we are called from OOM. | |
1594 | * To do this we must instruct the shmfs to drop all of its | |
1595 | * backing pages, *now*. | |
1596 | */ | |
496ad9aa | 1597 | inode = file_inode(obj->base.filp); |
225067ee | 1598 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1599 | |
225067ee DV |
1600 | obj->madv = __I915_MADV_PURGED; |
1601 | } | |
e5281ccd | 1602 | |
225067ee DV |
1603 | static inline int |
1604 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1605 | { | |
1606 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1607 | } |
1608 | ||
5cdf5881 | 1609 | static void |
05394f39 | 1610 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1611 | { |
90797e6d ID |
1612 | struct sg_page_iter sg_iter; |
1613 | int ret; | |
1286ff73 | 1614 | |
05394f39 | 1615 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1616 | |
6c085a72 CW |
1617 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1618 | if (ret) { | |
1619 | /* In the event of a disaster, abandon all caches and | |
1620 | * hope for the best. | |
1621 | */ | |
1622 | WARN_ON(ret != -EIO); | |
1623 | i915_gem_clflush_object(obj); | |
1624 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1625 | } | |
1626 | ||
6dacfd2f | 1627 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1628 | i915_gem_object_save_bit_17_swizzle(obj); |
1629 | ||
05394f39 CW |
1630 | if (obj->madv == I915_MADV_DONTNEED) |
1631 | obj->dirty = 0; | |
3ef94daa | 1632 | |
90797e6d | 1633 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1634 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1635 | |
05394f39 | 1636 | if (obj->dirty) |
9da3da66 | 1637 | set_page_dirty(page); |
3ef94daa | 1638 | |
05394f39 | 1639 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1640 | mark_page_accessed(page); |
3ef94daa | 1641 | |
9da3da66 | 1642 | page_cache_release(page); |
3ef94daa | 1643 | } |
05394f39 | 1644 | obj->dirty = 0; |
673a394b | 1645 | |
9da3da66 CW |
1646 | sg_free_table(obj->pages); |
1647 | kfree(obj->pages); | |
37e680a1 | 1648 | } |
6c085a72 | 1649 | |
dd624afd | 1650 | int |
37e680a1 CW |
1651 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1652 | { | |
1653 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1654 | ||
2f745ad3 | 1655 | if (obj->pages == NULL) |
37e680a1 CW |
1656 | return 0; |
1657 | ||
f343c5f6 | 1658 | BUG_ON(i915_gem_obj_ggtt_bound(obj)); |
6c085a72 | 1659 | |
a5570178 CW |
1660 | if (obj->pages_pin_count) |
1661 | return -EBUSY; | |
1662 | ||
a2165e31 CW |
1663 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1664 | * array, hence protect them from being reaped by removing them from gtt | |
1665 | * lists early. */ | |
35c20a60 | 1666 | list_del(&obj->global_list); |
a2165e31 | 1667 | |
37e680a1 | 1668 | ops->put_pages(obj); |
05394f39 | 1669 | obj->pages = NULL; |
37e680a1 | 1670 | |
6c085a72 CW |
1671 | if (i915_gem_object_is_purgeable(obj)) |
1672 | i915_gem_object_truncate(obj); | |
1673 | ||
1674 | return 0; | |
1675 | } | |
1676 | ||
1677 | static long | |
93927ca5 DV |
1678 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1679 | bool purgeable_only) | |
6c085a72 CW |
1680 | { |
1681 | struct drm_i915_gem_object *obj, *next; | |
1682 | long count = 0; | |
1683 | ||
1684 | list_for_each_entry_safe(obj, next, | |
1685 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1686 | global_list) { |
93927ca5 | 1687 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1688 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1689 | count += obj->base.size >> PAGE_SHIFT; |
1690 | if (count >= target) | |
1691 | return count; | |
1692 | } | |
1693 | } | |
1694 | ||
1695 | list_for_each_entry_safe(obj, next, | |
1696 | &dev_priv->mm.inactive_list, | |
1697 | mm_list) { | |
93927ca5 | 1698 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
6c085a72 | 1699 | i915_gem_object_unbind(obj) == 0 && |
37e680a1 | 1700 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1701 | count += obj->base.size >> PAGE_SHIFT; |
1702 | if (count >= target) | |
1703 | return count; | |
1704 | } | |
1705 | } | |
1706 | ||
1707 | return count; | |
1708 | } | |
1709 | ||
93927ca5 DV |
1710 | static long |
1711 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1712 | { | |
1713 | return __i915_gem_shrink(dev_priv, target, true); | |
1714 | } | |
1715 | ||
6c085a72 CW |
1716 | static void |
1717 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1718 | { | |
1719 | struct drm_i915_gem_object *obj, *next; | |
1720 | ||
1721 | i915_gem_evict_everything(dev_priv->dev); | |
1722 | ||
35c20a60 BW |
1723 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1724 | global_list) | |
37e680a1 | 1725 | i915_gem_object_put_pages(obj); |
225067ee DV |
1726 | } |
1727 | ||
37e680a1 | 1728 | static int |
6c085a72 | 1729 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1730 | { |
6c085a72 | 1731 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1732 | int page_count, i; |
1733 | struct address_space *mapping; | |
9da3da66 CW |
1734 | struct sg_table *st; |
1735 | struct scatterlist *sg; | |
90797e6d | 1736 | struct sg_page_iter sg_iter; |
e5281ccd | 1737 | struct page *page; |
90797e6d | 1738 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1739 | gfp_t gfp; |
e5281ccd | 1740 | |
6c085a72 CW |
1741 | /* Assert that the object is not currently in any GPU domain. As it |
1742 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1743 | * a GPU cache | |
1744 | */ | |
1745 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1746 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1747 | ||
9da3da66 CW |
1748 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1749 | if (st == NULL) | |
1750 | return -ENOMEM; | |
1751 | ||
05394f39 | 1752 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1753 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1754 | sg_free_table(st); | |
1755 | kfree(st); | |
e5281ccd | 1756 | return -ENOMEM; |
9da3da66 | 1757 | } |
e5281ccd | 1758 | |
9da3da66 CW |
1759 | /* Get the list of pages out of our struct file. They'll be pinned |
1760 | * at this point until we release them. | |
1761 | * | |
1762 | * Fail silently without starting the shrinker | |
1763 | */ | |
496ad9aa | 1764 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1765 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1766 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1767 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1768 | sg = st->sgl; |
1769 | st->nents = 0; | |
1770 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1771 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1772 | if (IS_ERR(page)) { | |
1773 | i915_gem_purge(dev_priv, page_count); | |
1774 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1775 | } | |
1776 | if (IS_ERR(page)) { | |
1777 | /* We've tried hard to allocate the memory by reaping | |
1778 | * our own buffer, now let the real VM do its job and | |
1779 | * go down in flames if truly OOM. | |
1780 | */ | |
caf49191 | 1781 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1782 | gfp |= __GFP_IO | __GFP_WAIT; |
1783 | ||
1784 | i915_gem_shrink_all(dev_priv); | |
1785 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1786 | if (IS_ERR(page)) | |
1787 | goto err_pages; | |
1788 | ||
caf49191 | 1789 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1790 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1791 | } | |
426729dc KRW |
1792 | #ifdef CONFIG_SWIOTLB |
1793 | if (swiotlb_nr_tbl()) { | |
1794 | st->nents++; | |
1795 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1796 | sg = sg_next(sg); | |
1797 | continue; | |
1798 | } | |
1799 | #endif | |
90797e6d ID |
1800 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1801 | if (i) | |
1802 | sg = sg_next(sg); | |
1803 | st->nents++; | |
1804 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1805 | } else { | |
1806 | sg->length += PAGE_SIZE; | |
1807 | } | |
1808 | last_pfn = page_to_pfn(page); | |
e5281ccd | 1809 | } |
426729dc KRW |
1810 | #ifdef CONFIG_SWIOTLB |
1811 | if (!swiotlb_nr_tbl()) | |
1812 | #endif | |
1813 | sg_mark_end(sg); | |
74ce6b6c CW |
1814 | obj->pages = st; |
1815 | ||
6dacfd2f | 1816 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1817 | i915_gem_object_do_bit_17_swizzle(obj); |
1818 | ||
1819 | return 0; | |
1820 | ||
1821 | err_pages: | |
90797e6d ID |
1822 | sg_mark_end(sg); |
1823 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1824 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1825 | sg_free_table(st); |
1826 | kfree(st); | |
e5281ccd | 1827 | return PTR_ERR(page); |
673a394b EA |
1828 | } |
1829 | ||
37e680a1 CW |
1830 | /* Ensure that the associated pages are gathered from the backing storage |
1831 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1832 | * multiple times before they are released by a single call to | |
1833 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1834 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1835 | * or as the object is itself released. | |
1836 | */ | |
1837 | int | |
1838 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1839 | { | |
1840 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1841 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1842 | int ret; | |
1843 | ||
2f745ad3 | 1844 | if (obj->pages) |
37e680a1 CW |
1845 | return 0; |
1846 | ||
43e28f09 CW |
1847 | if (obj->madv != I915_MADV_WILLNEED) { |
1848 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1849 | return -EINVAL; | |
1850 | } | |
1851 | ||
a5570178 CW |
1852 | BUG_ON(obj->pages_pin_count); |
1853 | ||
37e680a1 CW |
1854 | ret = ops->get_pages(obj); |
1855 | if (ret) | |
1856 | return ret; | |
1857 | ||
35c20a60 | 1858 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 1859 | return 0; |
673a394b EA |
1860 | } |
1861 | ||
54cf91dc | 1862 | void |
05394f39 | 1863 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1864 | struct intel_ring_buffer *ring) |
673a394b | 1865 | { |
05394f39 | 1866 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1868 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1869 | |
852835f3 | 1870 | BUG_ON(ring == NULL); |
02978ff5 CW |
1871 | if (obj->ring != ring && obj->last_write_seqno) { |
1872 | /* Keep the seqno relative to the current ring */ | |
1873 | obj->last_write_seqno = seqno; | |
1874 | } | |
05394f39 | 1875 | obj->ring = ring; |
673a394b EA |
1876 | |
1877 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1878 | if (!obj->active) { |
1879 | drm_gem_object_reference(&obj->base); | |
1880 | obj->active = 1; | |
673a394b | 1881 | } |
e35a41de | 1882 | |
673a394b | 1883 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1884 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1885 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1886 | |
0201f1ec | 1887 | obj->last_read_seqno = seqno; |
caea7476 | 1888 | |
7dd49065 | 1889 | if (obj->fenced_gpu_access) { |
caea7476 | 1890 | obj->last_fenced_seqno = seqno; |
caea7476 | 1891 | |
7dd49065 CW |
1892 | /* Bump MRU to take account of the delayed flush */ |
1893 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1894 | struct drm_i915_fence_reg *reg; | |
1895 | ||
1896 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1897 | list_move_tail(®->lru_list, | |
1898 | &dev_priv->mm.fence_list); | |
1899 | } | |
caea7476 CW |
1900 | } |
1901 | } | |
1902 | ||
1903 | static void | |
caea7476 | 1904 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1905 | { |
05394f39 | 1906 | struct drm_device *dev = obj->base.dev; |
caea7476 | 1907 | struct drm_i915_private *dev_priv = dev->dev_private; |
ce44b0ea | 1908 | |
65ce3027 | 1909 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1910 | BUG_ON(!obj->active); |
caea7476 | 1911 | |
1b50247a | 1912 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 | 1913 | |
65ce3027 | 1914 | list_del_init(&obj->ring_list); |
caea7476 CW |
1915 | obj->ring = NULL; |
1916 | ||
65ce3027 CW |
1917 | obj->last_read_seqno = 0; |
1918 | obj->last_write_seqno = 0; | |
1919 | obj->base.write_domain = 0; | |
1920 | ||
1921 | obj->last_fenced_seqno = 0; | |
caea7476 | 1922 | obj->fenced_gpu_access = false; |
caea7476 CW |
1923 | |
1924 | obj->active = 0; | |
1925 | drm_gem_object_unreference(&obj->base); | |
1926 | ||
1927 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1928 | } |
673a394b | 1929 | |
9d773091 | 1930 | static int |
fca26bb4 | 1931 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1932 | { |
9d773091 CW |
1933 | struct drm_i915_private *dev_priv = dev->dev_private; |
1934 | struct intel_ring_buffer *ring; | |
1935 | int ret, i, j; | |
53d227f2 | 1936 | |
107f27a5 | 1937 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1938 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1939 | ret = intel_ring_idle(ring); |
1940 | if (ret) | |
1941 | return ret; | |
9d773091 | 1942 | } |
9d773091 | 1943 | i915_gem_retire_requests(dev); |
107f27a5 CW |
1944 | |
1945 | /* Finally reset hw state */ | |
9d773091 | 1946 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 1947 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 1948 | |
9d773091 CW |
1949 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1950 | ring->sync_seqno[j] = 0; | |
1951 | } | |
53d227f2 | 1952 | |
9d773091 | 1953 | return 0; |
53d227f2 DV |
1954 | } |
1955 | ||
fca26bb4 MK |
1956 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1957 | { | |
1958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1959 | int ret; | |
1960 | ||
1961 | if (seqno == 0) | |
1962 | return -EINVAL; | |
1963 | ||
1964 | /* HWS page needs to be set less than what we | |
1965 | * will inject to ring | |
1966 | */ | |
1967 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
1968 | if (ret) | |
1969 | return ret; | |
1970 | ||
1971 | /* Carefully set the last_seqno value so that wrap | |
1972 | * detection still works | |
1973 | */ | |
1974 | dev_priv->next_seqno = seqno; | |
1975 | dev_priv->last_seqno = seqno - 1; | |
1976 | if (dev_priv->last_seqno == 0) | |
1977 | dev_priv->last_seqno--; | |
1978 | ||
1979 | return 0; | |
1980 | } | |
1981 | ||
9d773091 CW |
1982 | int |
1983 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 1984 | { |
9d773091 CW |
1985 | struct drm_i915_private *dev_priv = dev->dev_private; |
1986 | ||
1987 | /* reserve 0 for non-seqno */ | |
1988 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 1989 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
1990 | if (ret) |
1991 | return ret; | |
53d227f2 | 1992 | |
9d773091 CW |
1993 | dev_priv->next_seqno = 1; |
1994 | } | |
53d227f2 | 1995 | |
f72b3435 | 1996 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 1997 | return 0; |
53d227f2 DV |
1998 | } |
1999 | ||
0025c077 MK |
2000 | int __i915_add_request(struct intel_ring_buffer *ring, |
2001 | struct drm_file *file, | |
7d736f4f | 2002 | struct drm_i915_gem_object *obj, |
0025c077 | 2003 | u32 *out_seqno) |
673a394b | 2004 | { |
db53a302 | 2005 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2006 | struct drm_i915_gem_request *request; |
7d736f4f | 2007 | u32 request_ring_position, request_start; |
673a394b | 2008 | int was_empty; |
3cce469c CW |
2009 | int ret; |
2010 | ||
7d736f4f | 2011 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2012 | /* |
2013 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2014 | * after having emitted the batchbuffer command. Hence we need to fix | |
2015 | * things up similar to emitting the lazy request. The difference here | |
2016 | * is that the flush _must_ happen before the next request, no matter | |
2017 | * what. | |
2018 | */ | |
a7b9761d CW |
2019 | ret = intel_ring_flush_all_caches(ring); |
2020 | if (ret) | |
2021 | return ret; | |
cc889e0f | 2022 | |
acb868d3 CW |
2023 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
2024 | if (request == NULL) | |
2025 | return -ENOMEM; | |
cc889e0f | 2026 | |
673a394b | 2027 | |
a71d8d94 CW |
2028 | /* Record the position of the start of the request so that |
2029 | * should we detect the updated seqno part-way through the | |
2030 | * GPU processing the request, we never over-estimate the | |
2031 | * position of the head. | |
2032 | */ | |
2033 | request_ring_position = intel_ring_get_tail(ring); | |
2034 | ||
9d773091 | 2035 | ret = ring->add_request(ring); |
3bb73aba CW |
2036 | if (ret) { |
2037 | kfree(request); | |
2038 | return ret; | |
2039 | } | |
673a394b | 2040 | |
9d773091 | 2041 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2042 | request->ring = ring; |
7d736f4f | 2043 | request->head = request_start; |
a71d8d94 | 2044 | request->tail = request_ring_position; |
0e50e96b | 2045 | request->ctx = ring->last_context; |
7d736f4f MK |
2046 | request->batch_obj = obj; |
2047 | ||
2048 | /* Whilst this request exists, batch_obj will be on the | |
2049 | * active_list, and so will hold the active reference. Only when this | |
2050 | * request is retired will the the batch_obj be moved onto the | |
2051 | * inactive_list and lose its active reference. Hence we do not need | |
2052 | * to explicitly hold another reference here. | |
2053 | */ | |
0e50e96b MK |
2054 | |
2055 | if (request->ctx) | |
2056 | i915_gem_context_reference(request->ctx); | |
2057 | ||
673a394b | 2058 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2059 | was_empty = list_empty(&ring->request_list); |
2060 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2061 | request->file_priv = NULL; |
852835f3 | 2062 | |
db53a302 CW |
2063 | if (file) { |
2064 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2065 | ||
1c25595f | 2066 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2067 | request->file_priv = file_priv; |
b962442e | 2068 | list_add_tail(&request->client_list, |
f787a5f5 | 2069 | &file_priv->mm.request_list); |
1c25595f | 2070 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2071 | } |
673a394b | 2072 | |
9d773091 | 2073 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2074 | ring->outstanding_lazy_request = 0; |
db53a302 | 2075 | |
db1b76ca | 2076 | if (!dev_priv->ums.mm_suspended) { |
3e0dc6b0 | 2077 | if (i915_enable_hangcheck) { |
99584db3 | 2078 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
cecc21fe | 2079 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 2080 | } |
f047e395 | 2081 | if (was_empty) { |
b3b079db | 2082 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2083 | &dev_priv->mm.retire_work, |
2084 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2085 | intel_mark_busy(dev_priv->dev); |
2086 | } | |
f65d9421 | 2087 | } |
cc889e0f | 2088 | |
acb868d3 | 2089 | if (out_seqno) |
9d773091 | 2090 | *out_seqno = request->seqno; |
3cce469c | 2091 | return 0; |
673a394b EA |
2092 | } |
2093 | ||
f787a5f5 CW |
2094 | static inline void |
2095 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2096 | { |
1c25595f | 2097 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2098 | |
1c25595f CW |
2099 | if (!file_priv) |
2100 | return; | |
1c5d22f7 | 2101 | |
1c25595f | 2102 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2103 | if (request->file_priv) { |
2104 | list_del(&request->client_list); | |
2105 | request->file_priv = NULL; | |
2106 | } | |
1c25595f | 2107 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2108 | } |
673a394b | 2109 | |
aa60c664 MK |
2110 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj) |
2111 | { | |
f343c5f6 BW |
2112 | if (acthd >= i915_gem_obj_ggtt_offset(obj) && |
2113 | acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size) | |
aa60c664 MK |
2114 | return true; |
2115 | ||
2116 | return false; | |
2117 | } | |
2118 | ||
2119 | static bool i915_head_inside_request(const u32 acthd_unmasked, | |
2120 | const u32 request_start, | |
2121 | const u32 request_end) | |
2122 | { | |
2123 | const u32 acthd = acthd_unmasked & HEAD_ADDR; | |
2124 | ||
2125 | if (request_start < request_end) { | |
2126 | if (acthd >= request_start && acthd < request_end) | |
2127 | return true; | |
2128 | } else if (request_start > request_end) { | |
2129 | if (acthd >= request_start || acthd < request_end) | |
2130 | return true; | |
2131 | } | |
2132 | ||
2133 | return false; | |
2134 | } | |
2135 | ||
2136 | static bool i915_request_guilty(struct drm_i915_gem_request *request, | |
2137 | const u32 acthd, bool *inside) | |
2138 | { | |
2139 | /* There is a possibility that unmasked head address | |
2140 | * pointing inside the ring, matches the batch_obj address range. | |
2141 | * However this is extremely unlikely. | |
2142 | */ | |
2143 | ||
2144 | if (request->batch_obj) { | |
2145 | if (i915_head_inside_object(acthd, request->batch_obj)) { | |
2146 | *inside = true; | |
2147 | return true; | |
2148 | } | |
2149 | } | |
2150 | ||
2151 | if (i915_head_inside_request(acthd, request->head, request->tail)) { | |
2152 | *inside = false; | |
2153 | return true; | |
2154 | } | |
2155 | ||
2156 | return false; | |
2157 | } | |
2158 | ||
2159 | static void i915_set_reset_status(struct intel_ring_buffer *ring, | |
2160 | struct drm_i915_gem_request *request, | |
2161 | u32 acthd) | |
2162 | { | |
2163 | struct i915_ctx_hang_stats *hs = NULL; | |
2164 | bool inside, guilty; | |
2165 | ||
2166 | /* Innocent until proven guilty */ | |
2167 | guilty = false; | |
2168 | ||
2169 | if (ring->hangcheck.action != wait && | |
2170 | i915_request_guilty(request, acthd, &inside)) { | |
f343c5f6 | 2171 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
aa60c664 MK |
2172 | ring->name, |
2173 | inside ? "inside" : "flushing", | |
2174 | request->batch_obj ? | |
f343c5f6 | 2175 | i915_gem_obj_ggtt_offset(request->batch_obj) : 0, |
aa60c664 MK |
2176 | request->ctx ? request->ctx->id : 0, |
2177 | acthd); | |
2178 | ||
2179 | guilty = true; | |
2180 | } | |
2181 | ||
2182 | /* If contexts are disabled or this is the default context, use | |
2183 | * file_priv->reset_state | |
2184 | */ | |
2185 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) | |
2186 | hs = &request->ctx->hang_stats; | |
2187 | else if (request->file_priv) | |
2188 | hs = &request->file_priv->hang_stats; | |
2189 | ||
2190 | if (hs) { | |
2191 | if (guilty) | |
2192 | hs->batch_active++; | |
2193 | else | |
2194 | hs->batch_pending++; | |
2195 | } | |
2196 | } | |
2197 | ||
0e50e96b MK |
2198 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2199 | { | |
2200 | list_del(&request->list); | |
2201 | i915_gem_request_remove_from_client(request); | |
2202 | ||
2203 | if (request->ctx) | |
2204 | i915_gem_context_unreference(request->ctx); | |
2205 | ||
2206 | kfree(request); | |
2207 | } | |
2208 | ||
dfaae392 CW |
2209 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2210 | struct intel_ring_buffer *ring) | |
9375e446 | 2211 | { |
aa60c664 MK |
2212 | u32 completed_seqno; |
2213 | u32 acthd; | |
2214 | ||
2215 | acthd = intel_ring_get_active_head(ring); | |
2216 | completed_seqno = ring->get_seqno(ring, false); | |
2217 | ||
dfaae392 CW |
2218 | while (!list_empty(&ring->request_list)) { |
2219 | struct drm_i915_gem_request *request; | |
673a394b | 2220 | |
dfaae392 CW |
2221 | request = list_first_entry(&ring->request_list, |
2222 | struct drm_i915_gem_request, | |
2223 | list); | |
de151cf6 | 2224 | |
aa60c664 MK |
2225 | if (request->seqno > completed_seqno) |
2226 | i915_set_reset_status(ring, request, acthd); | |
2227 | ||
0e50e96b | 2228 | i915_gem_free_request(request); |
dfaae392 | 2229 | } |
673a394b | 2230 | |
dfaae392 | 2231 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2232 | struct drm_i915_gem_object *obj; |
9375e446 | 2233 | |
05394f39 CW |
2234 | obj = list_first_entry(&ring->active_list, |
2235 | struct drm_i915_gem_object, | |
2236 | ring_list); | |
9375e446 | 2237 | |
05394f39 | 2238 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2239 | } |
2240 | } | |
2241 | ||
19b2dbde | 2242 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2243 | { |
2244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2245 | int i; | |
2246 | ||
4b9de737 | 2247 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2248 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
19b2dbde | 2249 | i915_gem_write_fence(dev, i, reg->obj); |
312817a3 CW |
2250 | } |
2251 | } | |
2252 | ||
069efc1d | 2253 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2254 | { |
77f01230 | 2255 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2256 | struct drm_i915_gem_object *obj; |
b4519513 | 2257 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2258 | int i; |
673a394b | 2259 | |
b4519513 CW |
2260 | for_each_ring(ring, dev_priv, i) |
2261 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2262 | |
dfaae392 CW |
2263 | /* Move everything out of the GPU domains to ensure we do any |
2264 | * necessary invalidation upon reuse. | |
2265 | */ | |
05394f39 | 2266 | list_for_each_entry(obj, |
77f01230 | 2267 | &dev_priv->mm.inactive_list, |
69dc4987 | 2268 | mm_list) |
77f01230 | 2269 | { |
05394f39 | 2270 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2271 | } |
069efc1d | 2272 | |
19b2dbde | 2273 | i915_gem_restore_fences(dev); |
673a394b EA |
2274 | } |
2275 | ||
2276 | /** | |
2277 | * This function clears the request list as sequence numbers are passed. | |
2278 | */ | |
a71d8d94 | 2279 | void |
db53a302 | 2280 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2281 | { |
673a394b EA |
2282 | uint32_t seqno; |
2283 | ||
db53a302 | 2284 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2285 | return; |
2286 | ||
db53a302 | 2287 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2288 | |
b2eadbc8 | 2289 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2290 | |
852835f3 | 2291 | while (!list_empty(&ring->request_list)) { |
673a394b | 2292 | struct drm_i915_gem_request *request; |
673a394b | 2293 | |
852835f3 | 2294 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2295 | struct drm_i915_gem_request, |
2296 | list); | |
673a394b | 2297 | |
dfaae392 | 2298 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2299 | break; |
2300 | ||
db53a302 | 2301 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2302 | /* We know the GPU must have read the request to have |
2303 | * sent us the seqno + interrupt, so use the position | |
2304 | * of tail of the request to update the last known position | |
2305 | * of the GPU head. | |
2306 | */ | |
2307 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2308 | |
0e50e96b | 2309 | i915_gem_free_request(request); |
b84d5f0c | 2310 | } |
673a394b | 2311 | |
b84d5f0c CW |
2312 | /* Move any buffers on the active list that are no longer referenced |
2313 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2314 | */ | |
2315 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2316 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2317 | |
0206e353 | 2318 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2319 | struct drm_i915_gem_object, |
2320 | ring_list); | |
673a394b | 2321 | |
0201f1ec | 2322 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2323 | break; |
b84d5f0c | 2324 | |
65ce3027 | 2325 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2326 | } |
9d34e5db | 2327 | |
db53a302 CW |
2328 | if (unlikely(ring->trace_irq_seqno && |
2329 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2330 | ring->irq_put(ring); |
db53a302 | 2331 | ring->trace_irq_seqno = 0; |
9d34e5db | 2332 | } |
23bc5982 | 2333 | |
db53a302 | 2334 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2335 | } |
2336 | ||
b09a1fec CW |
2337 | void |
2338 | i915_gem_retire_requests(struct drm_device *dev) | |
2339 | { | |
2340 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2341 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2342 | int i; |
b09a1fec | 2343 | |
b4519513 CW |
2344 | for_each_ring(ring, dev_priv, i) |
2345 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2346 | } |
2347 | ||
75ef9da2 | 2348 | static void |
673a394b EA |
2349 | i915_gem_retire_work_handler(struct work_struct *work) |
2350 | { | |
2351 | drm_i915_private_t *dev_priv; | |
2352 | struct drm_device *dev; | |
b4519513 | 2353 | struct intel_ring_buffer *ring; |
0a58705b CW |
2354 | bool idle; |
2355 | int i; | |
673a394b EA |
2356 | |
2357 | dev_priv = container_of(work, drm_i915_private_t, | |
2358 | mm.retire_work.work); | |
2359 | dev = dev_priv->dev; | |
2360 | ||
891b48cf CW |
2361 | /* Come back later if the device is busy... */ |
2362 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2363 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2364 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2365 | return; |
2366 | } | |
673a394b | 2367 | |
b09a1fec | 2368 | i915_gem_retire_requests(dev); |
673a394b | 2369 | |
0a58705b CW |
2370 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2371 | * objects indefinitely. | |
673a394b | 2372 | */ |
0a58705b | 2373 | idle = true; |
b4519513 | 2374 | for_each_ring(ring, dev_priv, i) { |
3bb73aba | 2375 | if (ring->gpu_caches_dirty) |
0025c077 | 2376 | i915_add_request(ring, NULL); |
0a58705b CW |
2377 | |
2378 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2379 | } |
2380 | ||
db1b76ca | 2381 | if (!dev_priv->ums.mm_suspended && !idle) |
bcb45086 CW |
2382 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2383 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2384 | if (idle) |
2385 | intel_mark_idle(dev); | |
0a58705b | 2386 | |
673a394b | 2387 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2388 | } |
2389 | ||
30dfebf3 DV |
2390 | /** |
2391 | * Ensures that an object will eventually get non-busy by flushing any required | |
2392 | * write domains, emitting any outstanding lazy request and retiring and | |
2393 | * completed requests. | |
2394 | */ | |
2395 | static int | |
2396 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2397 | { | |
2398 | int ret; | |
2399 | ||
2400 | if (obj->active) { | |
0201f1ec | 2401 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2402 | if (ret) |
2403 | return ret; | |
2404 | ||
30dfebf3 DV |
2405 | i915_gem_retire_requests_ring(obj->ring); |
2406 | } | |
2407 | ||
2408 | return 0; | |
2409 | } | |
2410 | ||
23ba4fd0 BW |
2411 | /** |
2412 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2413 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2414 | * | |
2415 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2416 | * the timeout parameter. | |
2417 | * -ETIME: object is still busy after timeout | |
2418 | * -ERESTARTSYS: signal interrupted the wait | |
2419 | * -ENONENT: object doesn't exist | |
2420 | * Also possible, but rare: | |
2421 | * -EAGAIN: GPU wedged | |
2422 | * -ENOMEM: damn | |
2423 | * -ENODEV: Internal IRQ fail | |
2424 | * -E?: The add request failed | |
2425 | * | |
2426 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2427 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2428 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2429 | * without holding struct_mutex the object may become re-busied before this | |
2430 | * function completes. A similar but shorter * race condition exists in the busy | |
2431 | * ioctl | |
2432 | */ | |
2433 | int | |
2434 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2435 | { | |
f69061be | 2436 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2437 | struct drm_i915_gem_wait *args = data; |
2438 | struct drm_i915_gem_object *obj; | |
2439 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2440 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2441 | unsigned reset_counter; |
23ba4fd0 BW |
2442 | u32 seqno = 0; |
2443 | int ret = 0; | |
2444 | ||
eac1f14f BW |
2445 | if (args->timeout_ns >= 0) { |
2446 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2447 | timeout = &timeout_stack; | |
2448 | } | |
23ba4fd0 BW |
2449 | |
2450 | ret = i915_mutex_lock_interruptible(dev); | |
2451 | if (ret) | |
2452 | return ret; | |
2453 | ||
2454 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2455 | if (&obj->base == NULL) { | |
2456 | mutex_unlock(&dev->struct_mutex); | |
2457 | return -ENOENT; | |
2458 | } | |
2459 | ||
30dfebf3 DV |
2460 | /* Need to make sure the object gets inactive eventually. */ |
2461 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2462 | if (ret) |
2463 | goto out; | |
2464 | ||
2465 | if (obj->active) { | |
0201f1ec | 2466 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2467 | ring = obj->ring; |
2468 | } | |
2469 | ||
2470 | if (seqno == 0) | |
2471 | goto out; | |
2472 | ||
23ba4fd0 BW |
2473 | /* Do this after OLR check to make sure we make forward progress polling |
2474 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2475 | */ | |
2476 | if (!args->timeout_ns) { | |
2477 | ret = -ETIME; | |
2478 | goto out; | |
2479 | } | |
2480 | ||
2481 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2482 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2483 | mutex_unlock(&dev->struct_mutex); |
2484 | ||
f69061be | 2485 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
4f42f4ef | 2486 | if (timeout) |
eac1f14f | 2487 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2488 | return ret; |
2489 | ||
2490 | out: | |
2491 | drm_gem_object_unreference(&obj->base); | |
2492 | mutex_unlock(&dev->struct_mutex); | |
2493 | return ret; | |
2494 | } | |
2495 | ||
5816d648 BW |
2496 | /** |
2497 | * i915_gem_object_sync - sync an object to a ring. | |
2498 | * | |
2499 | * @obj: object which may be in use on another ring. | |
2500 | * @to: ring we wish to use the object on. May be NULL. | |
2501 | * | |
2502 | * This code is meant to abstract object synchronization with the GPU. | |
2503 | * Calling with NULL implies synchronizing the object with the CPU | |
2504 | * rather than a particular GPU ring. | |
2505 | * | |
2506 | * Returns 0 if successful, else propagates up the lower layer error. | |
2507 | */ | |
2911a35b BW |
2508 | int |
2509 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2510 | struct intel_ring_buffer *to) | |
2511 | { | |
2512 | struct intel_ring_buffer *from = obj->ring; | |
2513 | u32 seqno; | |
2514 | int ret, idx; | |
2515 | ||
2516 | if (from == NULL || to == from) | |
2517 | return 0; | |
2518 | ||
5816d648 | 2519 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2520 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2521 | |
2522 | idx = intel_ring_sync_index(from, to); | |
2523 | ||
0201f1ec | 2524 | seqno = obj->last_read_seqno; |
2911a35b BW |
2525 | if (seqno <= from->sync_seqno[idx]) |
2526 | return 0; | |
2527 | ||
b4aca010 BW |
2528 | ret = i915_gem_check_olr(obj->ring, seqno); |
2529 | if (ret) | |
2530 | return ret; | |
2911a35b | 2531 | |
1500f7ea | 2532 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2533 | if (!ret) |
7b01e260 MK |
2534 | /* We use last_read_seqno because sync_to() |
2535 | * might have just caused seqno wrap under | |
2536 | * the radar. | |
2537 | */ | |
2538 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2539 | |
e3a5a225 | 2540 | return ret; |
2911a35b BW |
2541 | } |
2542 | ||
b5ffc9bc CW |
2543 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2544 | { | |
2545 | u32 old_write_domain, old_read_domains; | |
2546 | ||
b5ffc9bc CW |
2547 | /* Force a pagefault for domain tracking on next user access */ |
2548 | i915_gem_release_mmap(obj); | |
2549 | ||
b97c3d9c KP |
2550 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2551 | return; | |
2552 | ||
97c809fd CW |
2553 | /* Wait for any direct GTT access to complete */ |
2554 | mb(); | |
2555 | ||
b5ffc9bc CW |
2556 | old_read_domains = obj->base.read_domains; |
2557 | old_write_domain = obj->base.write_domain; | |
2558 | ||
2559 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2560 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2561 | ||
2562 | trace_i915_gem_object_change_domain(obj, | |
2563 | old_read_domains, | |
2564 | old_write_domain); | |
2565 | } | |
2566 | ||
673a394b EA |
2567 | /** |
2568 | * Unbinds an object from the GTT aperture. | |
2569 | */ | |
0f973f27 | 2570 | int |
05394f39 | 2571 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2572 | { |
7bddb01f | 2573 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2574 | int ret; |
673a394b | 2575 | |
f343c5f6 | 2576 | if (!i915_gem_obj_ggtt_bound(obj)) |
673a394b EA |
2577 | return 0; |
2578 | ||
31d8d651 CW |
2579 | if (obj->pin_count) |
2580 | return -EBUSY; | |
673a394b | 2581 | |
c4670ad0 CW |
2582 | BUG_ON(obj->pages == NULL); |
2583 | ||
a8198eea | 2584 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2585 | if (ret) |
a8198eea CW |
2586 | return ret; |
2587 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2588 | * should be safe and we need to cleanup or else we might | |
2589 | * cause memory corruption through use-after-free. | |
2590 | */ | |
2591 | ||
b5ffc9bc | 2592 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2593 | |
96b47b65 | 2594 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2595 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2596 | if (ret) |
d9e86c0e | 2597 | return ret; |
96b47b65 | 2598 | |
db53a302 CW |
2599 | trace_i915_gem_object_unbind(obj); |
2600 | ||
74898d7e DV |
2601 | if (obj->has_global_gtt_mapping) |
2602 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2603 | if (obj->has_aliasing_ppgtt_mapping) { |
2604 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2605 | obj->has_aliasing_ppgtt_mapping = 0; | |
2606 | } | |
74163907 | 2607 | i915_gem_gtt_finish_object(obj); |
401c29f6 | 2608 | i915_gem_object_unpin_pages(obj); |
7bddb01f | 2609 | |
6c085a72 | 2610 | list_del(&obj->mm_list); |
35c20a60 | 2611 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
75e9e915 | 2612 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2613 | obj->map_and_fenceable = true; |
673a394b | 2614 | |
c6cfb325 | 2615 | drm_mm_remove_node(&obj->gtt_space); |
673a394b | 2616 | |
88241785 | 2617 | return 0; |
54cf91dc CW |
2618 | } |
2619 | ||
b2da9fe5 | 2620 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2621 | { |
2622 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2623 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2624 | int ret, i; |
4df2faf4 | 2625 | |
4df2faf4 | 2626 | /* Flush everything onto the inactive list. */ |
b4519513 | 2627 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2628 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2629 | if (ret) | |
2630 | return ret; | |
2631 | ||
3e960501 | 2632 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2633 | if (ret) |
2634 | return ret; | |
2635 | } | |
4df2faf4 | 2636 | |
8a1a49f9 | 2637 | return 0; |
4df2faf4 DV |
2638 | } |
2639 | ||
9ce079e4 CW |
2640 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2641 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2642 | { |
de151cf6 | 2643 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2644 | int fence_reg; |
2645 | int fence_pitch_shift; | |
de151cf6 | 2646 | |
56c844e5 ID |
2647 | if (INTEL_INFO(dev)->gen >= 6) { |
2648 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2649 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2650 | } else { | |
2651 | fence_reg = FENCE_REG_965_0; | |
2652 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2653 | } | |
2654 | ||
d18b9619 CW |
2655 | fence_reg += reg * 8; |
2656 | ||
2657 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2658 | * we split the 64-bit update into two 32-bit writes. In order | |
2659 | * for a partial fence not to be evaluated between writes, we | |
2660 | * precede the update with write to turn off the fence register, | |
2661 | * and only enable the fence as the last step. | |
2662 | * | |
2663 | * For extra levels of paranoia, we make sure each step lands | |
2664 | * before applying the next step. | |
2665 | */ | |
2666 | I915_WRITE(fence_reg, 0); | |
2667 | POSTING_READ(fence_reg); | |
2668 | ||
9ce079e4 | 2669 | if (obj) { |
f343c5f6 | 2670 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2671 | uint64_t val; |
de151cf6 | 2672 | |
f343c5f6 | 2673 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2674 | 0xfffff000) << 32; |
f343c5f6 | 2675 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2676 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2677 | if (obj->tiling_mode == I915_TILING_Y) |
2678 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2679 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2680 | |
d18b9619 CW |
2681 | I915_WRITE(fence_reg + 4, val >> 32); |
2682 | POSTING_READ(fence_reg + 4); | |
2683 | ||
2684 | I915_WRITE(fence_reg + 0, val); | |
2685 | POSTING_READ(fence_reg); | |
2686 | } else { | |
2687 | I915_WRITE(fence_reg + 4, 0); | |
2688 | POSTING_READ(fence_reg + 4); | |
2689 | } | |
de151cf6 JB |
2690 | } |
2691 | ||
9ce079e4 CW |
2692 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2693 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2694 | { |
de151cf6 | 2695 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2696 | u32 val; |
de151cf6 | 2697 | |
9ce079e4 | 2698 | if (obj) { |
f343c5f6 | 2699 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2700 | int pitch_val; |
2701 | int tile_width; | |
c6642782 | 2702 | |
f343c5f6 | 2703 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2704 | (size & -size) != size || |
f343c5f6 BW |
2705 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2706 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2707 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2708 | |
9ce079e4 CW |
2709 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2710 | tile_width = 128; | |
2711 | else | |
2712 | tile_width = 512; | |
2713 | ||
2714 | /* Note: pitch better be a power of two tile widths */ | |
2715 | pitch_val = obj->stride / tile_width; | |
2716 | pitch_val = ffs(pitch_val) - 1; | |
2717 | ||
f343c5f6 | 2718 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2719 | if (obj->tiling_mode == I915_TILING_Y) |
2720 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2721 | val |= I915_FENCE_SIZE_BITS(size); | |
2722 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2723 | val |= I830_FENCE_REG_VALID; | |
2724 | } else | |
2725 | val = 0; | |
2726 | ||
2727 | if (reg < 8) | |
2728 | reg = FENCE_REG_830_0 + reg * 4; | |
2729 | else | |
2730 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2731 | ||
2732 | I915_WRITE(reg, val); | |
2733 | POSTING_READ(reg); | |
de151cf6 JB |
2734 | } |
2735 | ||
9ce079e4 CW |
2736 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2737 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2738 | { |
de151cf6 | 2739 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2740 | uint32_t val; |
de151cf6 | 2741 | |
9ce079e4 | 2742 | if (obj) { |
f343c5f6 | 2743 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2744 | uint32_t pitch_val; |
de151cf6 | 2745 | |
f343c5f6 | 2746 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2747 | (size & -size) != size || |
f343c5f6 BW |
2748 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2749 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2750 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2751 | |
9ce079e4 CW |
2752 | pitch_val = obj->stride / 128; |
2753 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2754 | |
f343c5f6 | 2755 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2756 | if (obj->tiling_mode == I915_TILING_Y) |
2757 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2758 | val |= I830_FENCE_SIZE_BITS(size); | |
2759 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2760 | val |= I830_FENCE_REG_VALID; | |
2761 | } else | |
2762 | val = 0; | |
c6642782 | 2763 | |
9ce079e4 CW |
2764 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2765 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2766 | } | |
2767 | ||
d0a57789 CW |
2768 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2769 | { | |
2770 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2771 | } | |
2772 | ||
9ce079e4 CW |
2773 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2774 | struct drm_i915_gem_object *obj) | |
2775 | { | |
d0a57789 CW |
2776 | struct drm_i915_private *dev_priv = dev->dev_private; |
2777 | ||
2778 | /* Ensure that all CPU reads are completed before installing a fence | |
2779 | * and all writes before removing the fence. | |
2780 | */ | |
2781 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2782 | mb(); | |
2783 | ||
9ce079e4 CW |
2784 | switch (INTEL_INFO(dev)->gen) { |
2785 | case 7: | |
56c844e5 | 2786 | case 6: |
9ce079e4 CW |
2787 | case 5: |
2788 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2789 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2790 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2791 | default: BUG(); |
9ce079e4 | 2792 | } |
d0a57789 CW |
2793 | |
2794 | /* And similarly be paranoid that no direct access to this region | |
2795 | * is reordered to before the fence is installed. | |
2796 | */ | |
2797 | if (i915_gem_object_needs_mb(obj)) | |
2798 | mb(); | |
de151cf6 JB |
2799 | } |
2800 | ||
61050808 CW |
2801 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2802 | struct drm_i915_fence_reg *fence) | |
2803 | { | |
2804 | return fence - dev_priv->fence_regs; | |
2805 | } | |
2806 | ||
2807 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2808 | struct drm_i915_fence_reg *fence, | |
2809 | bool enable) | |
2810 | { | |
2dc8aae0 | 2811 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
2812 | int reg = fence_number(dev_priv, fence); |
2813 | ||
2814 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
2815 | |
2816 | if (enable) { | |
46a0b638 | 2817 | obj->fence_reg = reg; |
61050808 CW |
2818 | fence->obj = obj; |
2819 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2820 | } else { | |
2821 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2822 | fence->obj = NULL; | |
2823 | list_del_init(&fence->lru_list); | |
2824 | } | |
2825 | } | |
2826 | ||
d9e86c0e | 2827 | static int |
d0a57789 | 2828 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2829 | { |
1c293ea3 | 2830 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2831 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2832 | if (ret) |
2833 | return ret; | |
d9e86c0e CW |
2834 | |
2835 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2836 | } |
2837 | ||
86d5bc37 | 2838 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2839 | return 0; |
2840 | } | |
2841 | ||
2842 | int | |
2843 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2844 | { | |
61050808 | 2845 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 2846 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
2847 | int ret; |
2848 | ||
d0a57789 | 2849 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
2850 | if (ret) |
2851 | return ret; | |
2852 | ||
61050808 CW |
2853 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2854 | return 0; | |
d9e86c0e | 2855 | |
f9c513e9 CW |
2856 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2857 | ||
61050808 | 2858 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 2859 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
2860 | |
2861 | return 0; | |
2862 | } | |
2863 | ||
2864 | static struct drm_i915_fence_reg * | |
a360bb1a | 2865 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2866 | { |
ae3db24a | 2867 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2868 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2869 | int i; |
ae3db24a DV |
2870 | |
2871 | /* First try to find a free reg */ | |
d9e86c0e | 2872 | avail = NULL; |
ae3db24a DV |
2873 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2874 | reg = &dev_priv->fence_regs[i]; | |
2875 | if (!reg->obj) | |
d9e86c0e | 2876 | return reg; |
ae3db24a | 2877 | |
1690e1eb | 2878 | if (!reg->pin_count) |
d9e86c0e | 2879 | avail = reg; |
ae3db24a DV |
2880 | } |
2881 | ||
d9e86c0e CW |
2882 | if (avail == NULL) |
2883 | return NULL; | |
ae3db24a DV |
2884 | |
2885 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2886 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2887 | if (reg->pin_count) |
ae3db24a DV |
2888 | continue; |
2889 | ||
8fe301ad | 2890 | return reg; |
ae3db24a DV |
2891 | } |
2892 | ||
8fe301ad | 2893 | return NULL; |
ae3db24a DV |
2894 | } |
2895 | ||
de151cf6 | 2896 | /** |
9a5a53b3 | 2897 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2898 | * @obj: object to map through a fence reg |
2899 | * | |
2900 | * When mapping objects through the GTT, userspace wants to be able to write | |
2901 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2902 | * This function walks the fence regs looking for a free one for @obj, |
2903 | * stealing one if it can't find any. | |
2904 | * | |
2905 | * It then sets up the reg based on the object's properties: address, pitch | |
2906 | * and tiling format. | |
9a5a53b3 CW |
2907 | * |
2908 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2909 | */ |
8c4b8c3f | 2910 | int |
06d98131 | 2911 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2912 | { |
05394f39 | 2913 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2914 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2915 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2916 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2917 | int ret; |
de151cf6 | 2918 | |
14415745 CW |
2919 | /* Have we updated the tiling parameters upon the object and so |
2920 | * will need to serialise the write to the associated fence register? | |
2921 | */ | |
5d82e3e6 | 2922 | if (obj->fence_dirty) { |
d0a57789 | 2923 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
2924 | if (ret) |
2925 | return ret; | |
2926 | } | |
9a5a53b3 | 2927 | |
d9e86c0e | 2928 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2929 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2930 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2931 | if (!obj->fence_dirty) { |
14415745 CW |
2932 | list_move_tail(®->lru_list, |
2933 | &dev_priv->mm.fence_list); | |
2934 | return 0; | |
2935 | } | |
2936 | } else if (enable) { | |
2937 | reg = i915_find_fence_reg(dev); | |
2938 | if (reg == NULL) | |
2939 | return -EDEADLK; | |
d9e86c0e | 2940 | |
14415745 CW |
2941 | if (reg->obj) { |
2942 | struct drm_i915_gem_object *old = reg->obj; | |
2943 | ||
d0a57789 | 2944 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
2945 | if (ret) |
2946 | return ret; | |
2947 | ||
14415745 | 2948 | i915_gem_object_fence_lost(old); |
29c5a587 | 2949 | } |
14415745 | 2950 | } else |
a09ba7fa | 2951 | return 0; |
a09ba7fa | 2952 | |
14415745 | 2953 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2954 | obj->fence_dirty = false; |
14415745 | 2955 | |
9ce079e4 | 2956 | return 0; |
de151cf6 JB |
2957 | } |
2958 | ||
42d6ab48 CW |
2959 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2960 | struct drm_mm_node *gtt_space, | |
2961 | unsigned long cache_level) | |
2962 | { | |
2963 | struct drm_mm_node *other; | |
2964 | ||
2965 | /* On non-LLC machines we have to be careful when putting differing | |
2966 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 2967 | * crossing memory domains and dying. |
42d6ab48 CW |
2968 | */ |
2969 | if (HAS_LLC(dev)) | |
2970 | return true; | |
2971 | ||
c6cfb325 | 2972 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
2973 | return true; |
2974 | ||
2975 | if (list_empty(>t_space->node_list)) | |
2976 | return true; | |
2977 | ||
2978 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2979 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2980 | return false; | |
2981 | ||
2982 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2983 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2984 | return false; | |
2985 | ||
2986 | return true; | |
2987 | } | |
2988 | ||
2989 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2990 | { | |
2991 | #if WATCH_GTT | |
2992 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2993 | struct drm_i915_gem_object *obj; | |
2994 | int err = 0; | |
2995 | ||
35c20a60 | 2996 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
2997 | if (obj->gtt_space == NULL) { |
2998 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2999 | err++; | |
3000 | continue; | |
3001 | } | |
3002 | ||
3003 | if (obj->cache_level != obj->gtt_space->color) { | |
3004 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3005 | i915_gem_obj_ggtt_offset(obj), |
3006 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3007 | obj->cache_level, |
3008 | obj->gtt_space->color); | |
3009 | err++; | |
3010 | continue; | |
3011 | } | |
3012 | ||
3013 | if (!i915_gem_valid_gtt_space(dev, | |
3014 | obj->gtt_space, | |
3015 | obj->cache_level)) { | |
3016 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3017 | i915_gem_obj_ggtt_offset(obj), |
3018 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3019 | obj->cache_level); |
3020 | err++; | |
3021 | continue; | |
3022 | } | |
3023 | } | |
3024 | ||
3025 | WARN_ON(err); | |
3026 | #endif | |
3027 | } | |
3028 | ||
673a394b EA |
3029 | /** |
3030 | * Finds free space in the GTT aperture and binds the object there. | |
3031 | */ | |
3032 | static int | |
05394f39 | 3033 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 3034 | unsigned alignment, |
86a1ee26 CW |
3035 | bool map_and_fenceable, |
3036 | bool nonblocking) | |
673a394b | 3037 | { |
05394f39 | 3038 | struct drm_device *dev = obj->base.dev; |
673a394b | 3039 | drm_i915_private_t *dev_priv = dev->dev_private; |
5e783301 | 3040 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 3041 | bool mappable, fenceable; |
0a9ae0d7 BW |
3042 | size_t gtt_max = map_and_fenceable ? |
3043 | dev_priv->gtt.mappable_end : dev_priv->gtt.total; | |
07f73f69 | 3044 | int ret; |
673a394b | 3045 | |
e28f8711 CW |
3046 | fence_size = i915_gem_get_gtt_size(dev, |
3047 | obj->base.size, | |
3048 | obj->tiling_mode); | |
3049 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3050 | obj->base.size, | |
d865110c | 3051 | obj->tiling_mode, true); |
e28f8711 | 3052 | unfenced_alignment = |
d865110c | 3053 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 3054 | obj->base.size, |
d865110c | 3055 | obj->tiling_mode, false); |
a00b10c3 | 3056 | |
673a394b | 3057 | if (alignment == 0) |
5e783301 DV |
3058 | alignment = map_and_fenceable ? fence_alignment : |
3059 | unfenced_alignment; | |
75e9e915 | 3060 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
3061 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3062 | return -EINVAL; | |
3063 | } | |
3064 | ||
05394f39 | 3065 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 3066 | |
654fc607 CW |
3067 | /* If the object is bigger than the entire aperture, reject it early |
3068 | * before evicting everything in a vain attempt to find space. | |
3069 | */ | |
0a9ae0d7 | 3070 | if (obj->base.size > gtt_max) { |
3765f304 | 3071 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb CW |
3072 | obj->base.size, |
3073 | map_and_fenceable ? "mappable" : "total", | |
0a9ae0d7 | 3074 | gtt_max); |
654fc607 CW |
3075 | return -E2BIG; |
3076 | } | |
3077 | ||
37e680a1 | 3078 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
3079 | if (ret) |
3080 | return ret; | |
3081 | ||
fbdda6fb CW |
3082 | i915_gem_object_pin_pages(obj); |
3083 | ||
0a9ae0d7 | 3084 | search_free: |
c6cfb325 BW |
3085 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, |
3086 | &obj->gtt_space, | |
0a9ae0d7 BW |
3087 | size, alignment, |
3088 | obj->cache_level, 0, gtt_max); | |
dc9dd7a2 | 3089 | if (ret) { |
75e9e915 | 3090 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 3091 | obj->cache_level, |
86a1ee26 CW |
3092 | map_and_fenceable, |
3093 | nonblocking); | |
dc9dd7a2 CW |
3094 | if (ret == 0) |
3095 | goto search_free; | |
9731129c | 3096 | |
dc9dd7a2 | 3097 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 3098 | return ret; |
673a394b | 3099 | } |
c6cfb325 BW |
3100 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &obj->gtt_space, |
3101 | obj->cache_level))) { | |
fbdda6fb | 3102 | i915_gem_object_unpin_pages(obj); |
c6cfb325 | 3103 | drm_mm_remove_node(&obj->gtt_space); |
42d6ab48 | 3104 | return -EINVAL; |
673a394b EA |
3105 | } |
3106 | ||
74163907 | 3107 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 3108 | if (ret) { |
fbdda6fb | 3109 | i915_gem_object_unpin_pages(obj); |
c6cfb325 | 3110 | drm_mm_remove_node(&obj->gtt_space); |
6c085a72 | 3111 | return ret; |
673a394b | 3112 | } |
673a394b | 3113 | |
35c20a60 | 3114 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
05394f39 | 3115 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 3116 | |
75e9e915 | 3117 | fenceable = |
c6cfb325 BW |
3118 | i915_gem_obj_ggtt_size(obj) == fence_size && |
3119 | (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0; | |
a00b10c3 | 3120 | |
f343c5f6 BW |
3121 | mappable = i915_gem_obj_ggtt_offset(obj) + obj->base.size <= |
3122 | dev_priv->gtt.mappable_end; | |
a00b10c3 | 3123 | |
05394f39 | 3124 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 3125 | |
db53a302 | 3126 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 3127 | i915_gem_verify_gtt(dev); |
673a394b EA |
3128 | return 0; |
3129 | } | |
3130 | ||
3131 | void | |
05394f39 | 3132 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 3133 | { |
673a394b EA |
3134 | /* If we don't have a page list set up, then we're not pinned |
3135 | * to GPU, and we can ignore the cache flush because it'll happen | |
3136 | * again at bind time. | |
3137 | */ | |
05394f39 | 3138 | if (obj->pages == NULL) |
673a394b EA |
3139 | return; |
3140 | ||
769ce464 ID |
3141 | /* |
3142 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3143 | * marked as wc by the system, or the system is cache-coherent. | |
3144 | */ | |
3145 | if (obj->stolen) | |
3146 | return; | |
3147 | ||
9c23f7fc CW |
3148 | /* If the GPU is snooping the contents of the CPU cache, |
3149 | * we do not need to manually clear the CPU cache lines. However, | |
3150 | * the caches are only snooped when the render cache is | |
3151 | * flushed/invalidated. As we always have to emit invalidations | |
3152 | * and flushes when moving into and out of the RENDER domain, correct | |
3153 | * snooping behaviour occurs naturally as the result of our domain | |
3154 | * tracking. | |
3155 | */ | |
3156 | if (obj->cache_level != I915_CACHE_NONE) | |
3157 | return; | |
3158 | ||
1c5d22f7 | 3159 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3160 | |
9da3da66 | 3161 | drm_clflush_sg(obj->pages); |
e47c68e9 EA |
3162 | } |
3163 | ||
3164 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3165 | static void | |
05394f39 | 3166 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3167 | { |
1c5d22f7 CW |
3168 | uint32_t old_write_domain; |
3169 | ||
05394f39 | 3170 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3171 | return; |
3172 | ||
63256ec5 | 3173 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3174 | * to it immediately go to main memory as far as we know, so there's |
3175 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3176 | * |
3177 | * However, we do have to enforce the order so that all writes through | |
3178 | * the GTT land before any writes to the device, such as updates to | |
3179 | * the GATT itself. | |
e47c68e9 | 3180 | */ |
63256ec5 CW |
3181 | wmb(); |
3182 | ||
05394f39 CW |
3183 | old_write_domain = obj->base.write_domain; |
3184 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3185 | |
3186 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3187 | obj->base.read_domains, |
1c5d22f7 | 3188 | old_write_domain); |
e47c68e9 EA |
3189 | } |
3190 | ||
3191 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3192 | static void | |
05394f39 | 3193 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3194 | { |
1c5d22f7 | 3195 | uint32_t old_write_domain; |
e47c68e9 | 3196 | |
05394f39 | 3197 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3198 | return; |
3199 | ||
3200 | i915_gem_clflush_object(obj); | |
e76e9aeb | 3201 | i915_gem_chipset_flush(obj->base.dev); |
05394f39 CW |
3202 | old_write_domain = obj->base.write_domain; |
3203 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3204 | |
3205 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3206 | obj->base.read_domains, |
1c5d22f7 | 3207 | old_write_domain); |
e47c68e9 EA |
3208 | } |
3209 | ||
2ef7eeaa EA |
3210 | /** |
3211 | * Moves a single object to the GTT read, and possibly write domain. | |
3212 | * | |
3213 | * This function returns when the move is complete, including waiting on | |
3214 | * flushes to occur. | |
3215 | */ | |
79e53945 | 3216 | int |
2021746e | 3217 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3218 | { |
8325a09d | 3219 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3220 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3221 | int ret; |
2ef7eeaa | 3222 | |
02354392 | 3223 | /* Not valid to be called on unbound objects. */ |
f343c5f6 | 3224 | if (!i915_gem_obj_ggtt_bound(obj)) |
02354392 EA |
3225 | return -EINVAL; |
3226 | ||
8d7e3de1 CW |
3227 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3228 | return 0; | |
3229 | ||
0201f1ec | 3230 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3231 | if (ret) |
3232 | return ret; | |
3233 | ||
7213342d | 3234 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3235 | |
d0a57789 CW |
3236 | /* Serialise direct access to this object with the barriers for |
3237 | * coherent writes from the GPU, by effectively invalidating the | |
3238 | * GTT domain upon first access. | |
3239 | */ | |
3240 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3241 | mb(); | |
3242 | ||
05394f39 CW |
3243 | old_write_domain = obj->base.write_domain; |
3244 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3245 | |
e47c68e9 EA |
3246 | /* It should now be out of any other write domains, and we can update |
3247 | * the domain values for our changes. | |
3248 | */ | |
05394f39 CW |
3249 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3250 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3251 | if (write) { |
05394f39 CW |
3252 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3253 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3254 | obj->dirty = 1; | |
2ef7eeaa EA |
3255 | } |
3256 | ||
1c5d22f7 CW |
3257 | trace_i915_gem_object_change_domain(obj, |
3258 | old_read_domains, | |
3259 | old_write_domain); | |
3260 | ||
8325a09d CW |
3261 | /* And bump the LRU for this access */ |
3262 | if (i915_gem_object_is_inactive(obj)) | |
3263 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3264 | ||
e47c68e9 EA |
3265 | return 0; |
3266 | } | |
3267 | ||
e4ffd173 CW |
3268 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3269 | enum i915_cache_level cache_level) | |
3270 | { | |
7bddb01f DV |
3271 | struct drm_device *dev = obj->base.dev; |
3272 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3273 | int ret; |
3274 | ||
3275 | if (obj->cache_level == cache_level) | |
3276 | return 0; | |
3277 | ||
3278 | if (obj->pin_count) { | |
3279 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3280 | return -EBUSY; | |
3281 | } | |
3282 | ||
c6cfb325 | 3283 | if (!i915_gem_valid_gtt_space(dev, &obj->gtt_space, cache_level)) { |
42d6ab48 CW |
3284 | ret = i915_gem_object_unbind(obj); |
3285 | if (ret) | |
3286 | return ret; | |
3287 | } | |
3288 | ||
f343c5f6 | 3289 | if (i915_gem_obj_ggtt_bound(obj)) { |
e4ffd173 CW |
3290 | ret = i915_gem_object_finish_gpu(obj); |
3291 | if (ret) | |
3292 | return ret; | |
3293 | ||
3294 | i915_gem_object_finish_gtt(obj); | |
3295 | ||
3296 | /* Before SandyBridge, you could not use tiling or fence | |
3297 | * registers with snooped memory, so relinquish any fences | |
3298 | * currently pointing to our region in the aperture. | |
3299 | */ | |
42d6ab48 | 3300 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3301 | ret = i915_gem_object_put_fence(obj); |
3302 | if (ret) | |
3303 | return ret; | |
3304 | } | |
3305 | ||
74898d7e DV |
3306 | if (obj->has_global_gtt_mapping) |
3307 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3308 | if (obj->has_aliasing_ppgtt_mapping) |
3309 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3310 | obj, cache_level); | |
42d6ab48 | 3311 | |
f343c5f6 | 3312 | i915_gem_obj_ggtt_set_color(obj, cache_level); |
e4ffd173 CW |
3313 | } |
3314 | ||
3315 | if (cache_level == I915_CACHE_NONE) { | |
3316 | u32 old_read_domains, old_write_domain; | |
3317 | ||
3318 | /* If we're coming from LLC cached, then we haven't | |
3319 | * actually been tracking whether the data is in the | |
3320 | * CPU cache or not, since we only allow one bit set | |
3321 | * in obj->write_domain and have been skipping the clflushes. | |
3322 | * Just set it to the CPU cache for now. | |
3323 | */ | |
3324 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3325 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3326 | ||
3327 | old_read_domains = obj->base.read_domains; | |
3328 | old_write_domain = obj->base.write_domain; | |
3329 | ||
3330 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3331 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3332 | ||
3333 | trace_i915_gem_object_change_domain(obj, | |
3334 | old_read_domains, | |
3335 | old_write_domain); | |
3336 | } | |
3337 | ||
3338 | obj->cache_level = cache_level; | |
42d6ab48 | 3339 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3340 | return 0; |
3341 | } | |
3342 | ||
199adf40 BW |
3343 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3344 | struct drm_file *file) | |
e6994aee | 3345 | { |
199adf40 | 3346 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3347 | struct drm_i915_gem_object *obj; |
3348 | int ret; | |
3349 | ||
3350 | ret = i915_mutex_lock_interruptible(dev); | |
3351 | if (ret) | |
3352 | return ret; | |
3353 | ||
3354 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3355 | if (&obj->base == NULL) { | |
3356 | ret = -ENOENT; | |
3357 | goto unlock; | |
3358 | } | |
3359 | ||
199adf40 | 3360 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3361 | |
3362 | drm_gem_object_unreference(&obj->base); | |
3363 | unlock: | |
3364 | mutex_unlock(&dev->struct_mutex); | |
3365 | return ret; | |
3366 | } | |
3367 | ||
199adf40 BW |
3368 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3369 | struct drm_file *file) | |
e6994aee | 3370 | { |
199adf40 | 3371 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3372 | struct drm_i915_gem_object *obj; |
3373 | enum i915_cache_level level; | |
3374 | int ret; | |
3375 | ||
199adf40 BW |
3376 | switch (args->caching) { |
3377 | case I915_CACHING_NONE: | |
e6994aee CW |
3378 | level = I915_CACHE_NONE; |
3379 | break; | |
199adf40 | 3380 | case I915_CACHING_CACHED: |
e6994aee CW |
3381 | level = I915_CACHE_LLC; |
3382 | break; | |
3383 | default: | |
3384 | return -EINVAL; | |
3385 | } | |
3386 | ||
3bc2913e BW |
3387 | ret = i915_mutex_lock_interruptible(dev); |
3388 | if (ret) | |
3389 | return ret; | |
3390 | ||
e6994aee CW |
3391 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3392 | if (&obj->base == NULL) { | |
3393 | ret = -ENOENT; | |
3394 | goto unlock; | |
3395 | } | |
3396 | ||
3397 | ret = i915_gem_object_set_cache_level(obj, level); | |
3398 | ||
3399 | drm_gem_object_unreference(&obj->base); | |
3400 | unlock: | |
3401 | mutex_unlock(&dev->struct_mutex); | |
3402 | return ret; | |
3403 | } | |
3404 | ||
b9241ea3 | 3405 | /* |
2da3b9b9 CW |
3406 | * Prepare buffer for display plane (scanout, cursors, etc). |
3407 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3408 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3409 | */ |
3410 | int | |
2da3b9b9 CW |
3411 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3412 | u32 alignment, | |
919926ae | 3413 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3414 | { |
2da3b9b9 | 3415 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3416 | int ret; |
3417 | ||
0be73284 | 3418 | if (pipelined != obj->ring) { |
2911a35b BW |
3419 | ret = i915_gem_object_sync(obj, pipelined); |
3420 | if (ret) | |
b9241ea3 ZW |
3421 | return ret; |
3422 | } | |
3423 | ||
a7ef0640 EA |
3424 | /* The display engine is not coherent with the LLC cache on gen6. As |
3425 | * a result, we make sure that the pinning that is about to occur is | |
3426 | * done with uncached PTEs. This is lowest common denominator for all | |
3427 | * chipsets. | |
3428 | * | |
3429 | * However for gen6+, we could do better by using the GFDT bit instead | |
3430 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3431 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3432 | */ | |
3433 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3434 | if (ret) | |
3435 | return ret; | |
3436 | ||
2da3b9b9 CW |
3437 | /* As the user may map the buffer once pinned in the display plane |
3438 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3439 | * always use map_and_fenceable for all scanout buffers. | |
3440 | */ | |
86a1ee26 | 3441 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3442 | if (ret) |
3443 | return ret; | |
3444 | ||
b118c1e3 CW |
3445 | i915_gem_object_flush_cpu_write_domain(obj); |
3446 | ||
2da3b9b9 | 3447 | old_write_domain = obj->base.write_domain; |
05394f39 | 3448 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3449 | |
3450 | /* It should now be out of any other write domains, and we can update | |
3451 | * the domain values for our changes. | |
3452 | */ | |
e5f1d962 | 3453 | obj->base.write_domain = 0; |
05394f39 | 3454 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3455 | |
3456 | trace_i915_gem_object_change_domain(obj, | |
3457 | old_read_domains, | |
2da3b9b9 | 3458 | old_write_domain); |
b9241ea3 ZW |
3459 | |
3460 | return 0; | |
3461 | } | |
3462 | ||
85345517 | 3463 | int |
a8198eea | 3464 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3465 | { |
88241785 CW |
3466 | int ret; |
3467 | ||
a8198eea | 3468 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3469 | return 0; |
3470 | ||
0201f1ec | 3471 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3472 | if (ret) |
3473 | return ret; | |
3474 | ||
a8198eea CW |
3475 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3476 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3477 | return 0; |
85345517 CW |
3478 | } |
3479 | ||
e47c68e9 EA |
3480 | /** |
3481 | * Moves a single object to the CPU read, and possibly write domain. | |
3482 | * | |
3483 | * This function returns when the move is complete, including waiting on | |
3484 | * flushes to occur. | |
3485 | */ | |
dabdfe02 | 3486 | int |
919926ae | 3487 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3488 | { |
1c5d22f7 | 3489 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3490 | int ret; |
3491 | ||
8d7e3de1 CW |
3492 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3493 | return 0; | |
3494 | ||
0201f1ec | 3495 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3496 | if (ret) |
3497 | return ret; | |
3498 | ||
e47c68e9 | 3499 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3500 | |
05394f39 CW |
3501 | old_write_domain = obj->base.write_domain; |
3502 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3503 | |
e47c68e9 | 3504 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3505 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3506 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3507 | |
05394f39 | 3508 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3509 | } |
3510 | ||
3511 | /* It should now be out of any other write domains, and we can update | |
3512 | * the domain values for our changes. | |
3513 | */ | |
05394f39 | 3514 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3515 | |
3516 | /* If we're writing through the CPU, then the GPU read domains will | |
3517 | * need to be invalidated at next use. | |
3518 | */ | |
3519 | if (write) { | |
05394f39 CW |
3520 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3521 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3522 | } |
2ef7eeaa | 3523 | |
1c5d22f7 CW |
3524 | trace_i915_gem_object_change_domain(obj, |
3525 | old_read_domains, | |
3526 | old_write_domain); | |
3527 | ||
2ef7eeaa EA |
3528 | return 0; |
3529 | } | |
3530 | ||
673a394b EA |
3531 | /* Throttle our rendering by waiting until the ring has completed our requests |
3532 | * emitted over 20 msec ago. | |
3533 | * | |
b962442e EA |
3534 | * Note that if we were to use the current jiffies each time around the loop, |
3535 | * we wouldn't escape the function with any frames outstanding if the time to | |
3536 | * render a frame was over 20ms. | |
3537 | * | |
673a394b EA |
3538 | * This should get us reasonable parallelism between CPU and GPU but also |
3539 | * relatively low latency when blocking on a particular request to finish. | |
3540 | */ | |
40a5f0de | 3541 | static int |
f787a5f5 | 3542 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3543 | { |
f787a5f5 CW |
3544 | struct drm_i915_private *dev_priv = dev->dev_private; |
3545 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3546 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3547 | struct drm_i915_gem_request *request; |
3548 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3549 | unsigned reset_counter; |
f787a5f5 CW |
3550 | u32 seqno = 0; |
3551 | int ret; | |
93533c29 | 3552 | |
308887aa DV |
3553 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3554 | if (ret) | |
3555 | return ret; | |
3556 | ||
3557 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3558 | if (ret) | |
3559 | return ret; | |
e110e8d6 | 3560 | |
1c25595f | 3561 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3562 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3563 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3564 | break; | |
40a5f0de | 3565 | |
f787a5f5 CW |
3566 | ring = request->ring; |
3567 | seqno = request->seqno; | |
b962442e | 3568 | } |
f69061be | 3569 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3570 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3571 | |
f787a5f5 CW |
3572 | if (seqno == 0) |
3573 | return 0; | |
2bc43b5c | 3574 | |
f69061be | 3575 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
f787a5f5 CW |
3576 | if (ret == 0) |
3577 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3578 | |
3579 | return ret; | |
3580 | } | |
3581 | ||
673a394b | 3582 | int |
05394f39 CW |
3583 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3584 | uint32_t alignment, | |
86a1ee26 CW |
3585 | bool map_and_fenceable, |
3586 | bool nonblocking) | |
673a394b | 3587 | { |
673a394b EA |
3588 | int ret; |
3589 | ||
7e81a42e CW |
3590 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3591 | return -EBUSY; | |
ac0c6b5a | 3592 | |
f343c5f6 BW |
3593 | if (i915_gem_obj_ggtt_bound(obj)) { |
3594 | if ((alignment && i915_gem_obj_ggtt_offset(obj) & (alignment - 1)) || | |
05394f39 CW |
3595 | (map_and_fenceable && !obj->map_and_fenceable)) { |
3596 | WARN(obj->pin_count, | |
ae7d49d8 | 3597 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3598 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3599 | " obj->map_and_fenceable=%d\n", |
f343c5f6 | 3600 | i915_gem_obj_ggtt_offset(obj), alignment, |
75e9e915 | 3601 | map_and_fenceable, |
05394f39 | 3602 | obj->map_and_fenceable); |
ac0c6b5a CW |
3603 | ret = i915_gem_object_unbind(obj); |
3604 | if (ret) | |
3605 | return ret; | |
3606 | } | |
3607 | } | |
3608 | ||
f343c5f6 | 3609 | if (!i915_gem_obj_ggtt_bound(obj)) { |
8742267a CW |
3610 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3611 | ||
a00b10c3 | 3612 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3613 | map_and_fenceable, |
3614 | nonblocking); | |
9731129c | 3615 | if (ret) |
673a394b | 3616 | return ret; |
8742267a CW |
3617 | |
3618 | if (!dev_priv->mm.aliasing_ppgtt) | |
3619 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3620 | } |
76446cac | 3621 | |
74898d7e DV |
3622 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3623 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3624 | ||
1b50247a | 3625 | obj->pin_count++; |
6299f992 | 3626 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3627 | |
3628 | return 0; | |
3629 | } | |
3630 | ||
3631 | void | |
05394f39 | 3632 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3633 | { |
05394f39 | 3634 | BUG_ON(obj->pin_count == 0); |
f343c5f6 | 3635 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); |
673a394b | 3636 | |
1b50247a | 3637 | if (--obj->pin_count == 0) |
6299f992 | 3638 | obj->pin_mappable = false; |
673a394b EA |
3639 | } |
3640 | ||
3641 | int | |
3642 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3643 | struct drm_file *file) |
673a394b EA |
3644 | { |
3645 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3646 | struct drm_i915_gem_object *obj; |
673a394b EA |
3647 | int ret; |
3648 | ||
1d7cfea1 CW |
3649 | ret = i915_mutex_lock_interruptible(dev); |
3650 | if (ret) | |
3651 | return ret; | |
673a394b | 3652 | |
05394f39 | 3653 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3654 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3655 | ret = -ENOENT; |
3656 | goto unlock; | |
673a394b | 3657 | } |
673a394b | 3658 | |
05394f39 | 3659 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3660 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3661 | ret = -EINVAL; |
3662 | goto out; | |
3ef94daa CW |
3663 | } |
3664 | ||
05394f39 | 3665 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3666 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3667 | args->handle); | |
1d7cfea1 CW |
3668 | ret = -EINVAL; |
3669 | goto out; | |
79e53945 JB |
3670 | } |
3671 | ||
93be8788 | 3672 | if (obj->user_pin_count == 0) { |
86a1ee26 | 3673 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3674 | if (ret) |
3675 | goto out; | |
673a394b EA |
3676 | } |
3677 | ||
93be8788 CW |
3678 | obj->user_pin_count++; |
3679 | obj->pin_filp = file; | |
3680 | ||
673a394b EA |
3681 | /* XXX - flush the CPU caches for pinned objects |
3682 | * as the X server doesn't manage domains yet | |
3683 | */ | |
e47c68e9 | 3684 | i915_gem_object_flush_cpu_write_domain(obj); |
f343c5f6 | 3685 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 3686 | out: |
05394f39 | 3687 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3688 | unlock: |
673a394b | 3689 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3690 | return ret; |
673a394b EA |
3691 | } |
3692 | ||
3693 | int | |
3694 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3695 | struct drm_file *file) |
673a394b EA |
3696 | { |
3697 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3698 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3699 | int ret; |
673a394b | 3700 | |
1d7cfea1 CW |
3701 | ret = i915_mutex_lock_interruptible(dev); |
3702 | if (ret) | |
3703 | return ret; | |
673a394b | 3704 | |
05394f39 | 3705 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3706 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3707 | ret = -ENOENT; |
3708 | goto unlock; | |
673a394b | 3709 | } |
76c1dec1 | 3710 | |
05394f39 | 3711 | if (obj->pin_filp != file) { |
79e53945 JB |
3712 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3713 | args->handle); | |
1d7cfea1 CW |
3714 | ret = -EINVAL; |
3715 | goto out; | |
79e53945 | 3716 | } |
05394f39 CW |
3717 | obj->user_pin_count--; |
3718 | if (obj->user_pin_count == 0) { | |
3719 | obj->pin_filp = NULL; | |
79e53945 JB |
3720 | i915_gem_object_unpin(obj); |
3721 | } | |
673a394b | 3722 | |
1d7cfea1 | 3723 | out: |
05394f39 | 3724 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3725 | unlock: |
673a394b | 3726 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3727 | return ret; |
673a394b EA |
3728 | } |
3729 | ||
3730 | int | |
3731 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3732 | struct drm_file *file) |
673a394b EA |
3733 | { |
3734 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3735 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3736 | int ret; |
3737 | ||
76c1dec1 | 3738 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3739 | if (ret) |
76c1dec1 | 3740 | return ret; |
673a394b | 3741 | |
05394f39 | 3742 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3743 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3744 | ret = -ENOENT; |
3745 | goto unlock; | |
673a394b | 3746 | } |
d1b851fc | 3747 | |
0be555b6 CW |
3748 | /* Count all active objects as busy, even if they are currently not used |
3749 | * by the gpu. Users of this interface expect objects to eventually | |
3750 | * become non-busy without any further actions, therefore emit any | |
3751 | * necessary flushes here. | |
c4de0a5d | 3752 | */ |
30dfebf3 | 3753 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3754 | |
30dfebf3 | 3755 | args->busy = obj->active; |
e9808edd CW |
3756 | if (obj->ring) { |
3757 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3758 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3759 | } | |
673a394b | 3760 | |
05394f39 | 3761 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3762 | unlock: |
673a394b | 3763 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3764 | return ret; |
673a394b EA |
3765 | } |
3766 | ||
3767 | int | |
3768 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3769 | struct drm_file *file_priv) | |
3770 | { | |
0206e353 | 3771 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3772 | } |
3773 | ||
3ef94daa CW |
3774 | int |
3775 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3776 | struct drm_file *file_priv) | |
3777 | { | |
3778 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3779 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3780 | int ret; |
3ef94daa CW |
3781 | |
3782 | switch (args->madv) { | |
3783 | case I915_MADV_DONTNEED: | |
3784 | case I915_MADV_WILLNEED: | |
3785 | break; | |
3786 | default: | |
3787 | return -EINVAL; | |
3788 | } | |
3789 | ||
1d7cfea1 CW |
3790 | ret = i915_mutex_lock_interruptible(dev); |
3791 | if (ret) | |
3792 | return ret; | |
3793 | ||
05394f39 | 3794 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3795 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3796 | ret = -ENOENT; |
3797 | goto unlock; | |
3ef94daa | 3798 | } |
3ef94daa | 3799 | |
05394f39 | 3800 | if (obj->pin_count) { |
1d7cfea1 CW |
3801 | ret = -EINVAL; |
3802 | goto out; | |
3ef94daa CW |
3803 | } |
3804 | ||
05394f39 CW |
3805 | if (obj->madv != __I915_MADV_PURGED) |
3806 | obj->madv = args->madv; | |
3ef94daa | 3807 | |
6c085a72 CW |
3808 | /* if the object is no longer attached, discard its backing storage */ |
3809 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3810 | i915_gem_object_truncate(obj); |
3811 | ||
05394f39 | 3812 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3813 | |
1d7cfea1 | 3814 | out: |
05394f39 | 3815 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3816 | unlock: |
3ef94daa | 3817 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3818 | return ret; |
3ef94daa CW |
3819 | } |
3820 | ||
37e680a1 CW |
3821 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3822 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3823 | { |
0327d6ba | 3824 | INIT_LIST_HEAD(&obj->mm_list); |
35c20a60 | 3825 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba CW |
3826 | INIT_LIST_HEAD(&obj->ring_list); |
3827 | INIT_LIST_HEAD(&obj->exec_list); | |
3828 | ||
37e680a1 CW |
3829 | obj->ops = ops; |
3830 | ||
0327d6ba CW |
3831 | obj->fence_reg = I915_FENCE_REG_NONE; |
3832 | obj->madv = I915_MADV_WILLNEED; | |
3833 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3834 | obj->map_and_fenceable = true; | |
3835 | ||
3836 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3837 | } | |
3838 | ||
37e680a1 CW |
3839 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3840 | .get_pages = i915_gem_object_get_pages_gtt, | |
3841 | .put_pages = i915_gem_object_put_pages_gtt, | |
3842 | }; | |
3843 | ||
05394f39 CW |
3844 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3845 | size_t size) | |
ac52bc56 | 3846 | { |
c397b908 | 3847 | struct drm_i915_gem_object *obj; |
5949eac4 | 3848 | struct address_space *mapping; |
1a240d4d | 3849 | gfp_t mask; |
ac52bc56 | 3850 | |
42dcedd4 | 3851 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
3852 | if (obj == NULL) |
3853 | return NULL; | |
673a394b | 3854 | |
c397b908 | 3855 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 3856 | i915_gem_object_free(obj); |
c397b908 DV |
3857 | return NULL; |
3858 | } | |
673a394b | 3859 | |
bed1ea95 CW |
3860 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3861 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3862 | /* 965gm cannot relocate objects above 4GiB. */ | |
3863 | mask &= ~__GFP_HIGHMEM; | |
3864 | mask |= __GFP_DMA32; | |
3865 | } | |
3866 | ||
496ad9aa | 3867 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 3868 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3869 | |
37e680a1 | 3870 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3871 | |
c397b908 DV |
3872 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3873 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3874 | |
3d29b842 ED |
3875 | if (HAS_LLC(dev)) { |
3876 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3877 | * cache) for about a 10% performance improvement |
3878 | * compared to uncached. Graphics requests other than | |
3879 | * display scanout are coherent with the CPU in | |
3880 | * accessing this cache. This means in this mode we | |
3881 | * don't need to clflush on the CPU side, and on the | |
3882 | * GPU side we only need to flush internal caches to | |
3883 | * get data visible to the CPU. | |
3884 | * | |
3885 | * However, we maintain the display planes as UC, and so | |
3886 | * need to rebind when first used as such. | |
3887 | */ | |
3888 | obj->cache_level = I915_CACHE_LLC; | |
3889 | } else | |
3890 | obj->cache_level = I915_CACHE_NONE; | |
3891 | ||
05394f39 | 3892 | return obj; |
c397b908 DV |
3893 | } |
3894 | ||
3895 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3896 | { | |
3897 | BUG(); | |
de151cf6 | 3898 | |
673a394b EA |
3899 | return 0; |
3900 | } | |
3901 | ||
1488fc08 | 3902 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3903 | { |
1488fc08 | 3904 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3905 | struct drm_device *dev = obj->base.dev; |
be72615b | 3906 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3907 | |
26e12f89 CW |
3908 | trace_i915_gem_object_destroy(obj); |
3909 | ||
1488fc08 CW |
3910 | if (obj->phys_obj) |
3911 | i915_gem_detach_phys_object(dev, obj); | |
3912 | ||
3913 | obj->pin_count = 0; | |
3914 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3915 | bool was_interruptible; | |
3916 | ||
3917 | was_interruptible = dev_priv->mm.interruptible; | |
3918 | dev_priv->mm.interruptible = false; | |
3919 | ||
3920 | WARN_ON(i915_gem_object_unbind(obj)); | |
3921 | ||
3922 | dev_priv->mm.interruptible = was_interruptible; | |
3923 | } | |
3924 | ||
1d64ae71 BW |
3925 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
3926 | * before progressing. */ | |
3927 | if (obj->stolen) | |
3928 | i915_gem_object_unpin_pages(obj); | |
3929 | ||
401c29f6 BW |
3930 | if (WARN_ON(obj->pages_pin_count)) |
3931 | obj->pages_pin_count = 0; | |
37e680a1 | 3932 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3933 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 3934 | i915_gem_object_release_stolen(obj); |
de151cf6 | 3935 | |
9da3da66 CW |
3936 | BUG_ON(obj->pages); |
3937 | ||
2f745ad3 CW |
3938 | if (obj->base.import_attach) |
3939 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 3940 | |
05394f39 CW |
3941 | drm_gem_object_release(&obj->base); |
3942 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3943 | |
05394f39 | 3944 | kfree(obj->bit_17); |
42dcedd4 | 3945 | i915_gem_object_free(obj); |
673a394b EA |
3946 | } |
3947 | ||
29105ccc CW |
3948 | int |
3949 | i915_gem_idle(struct drm_device *dev) | |
3950 | { | |
3951 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3952 | int ret; | |
28dfe52a | 3953 | |
db1b76ca | 3954 | if (dev_priv->ums.mm_suspended) { |
29105ccc CW |
3955 | mutex_unlock(&dev->struct_mutex); |
3956 | return 0; | |
28dfe52a EA |
3957 | } |
3958 | ||
b2da9fe5 | 3959 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3960 | if (ret) { |
3961 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3962 | return ret; |
6dbe2772 | 3963 | } |
b2da9fe5 | 3964 | i915_gem_retire_requests(dev); |
673a394b | 3965 | |
29105ccc | 3966 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3967 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3968 | i915_gem_evict_everything(dev); |
29105ccc | 3969 | |
99584db3 | 3970 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
3971 | |
3972 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3973 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3974 | |
29105ccc CW |
3975 | /* Cancel the retire work handler, which should be idle now. */ |
3976 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3977 | ||
673a394b EA |
3978 | return 0; |
3979 | } | |
3980 | ||
b9524a1e BW |
3981 | void i915_gem_l3_remap(struct drm_device *dev) |
3982 | { | |
3983 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3984 | u32 misccpctl; | |
3985 | int i; | |
3986 | ||
eb32e458 | 3987 | if (!HAS_L3_GPU_CACHE(dev)) |
b9524a1e BW |
3988 | return; |
3989 | ||
a4da4fa4 | 3990 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
3991 | return; |
3992 | ||
3993 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3994 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3995 | POSTING_READ(GEN7_MISCCPCTL); | |
3996 | ||
3997 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3998 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 3999 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
4000 | DRM_DEBUG("0x%x was already programmed to %x\n", |
4001 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 4002 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 4003 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 4004 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
4005 | } |
4006 | ||
4007 | /* Make sure all the writes land before disabling dop clock gating */ | |
4008 | POSTING_READ(GEN7_L3LOG_BASE); | |
4009 | ||
4010 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
4011 | } | |
4012 | ||
f691e2f4 DV |
4013 | void i915_gem_init_swizzling(struct drm_device *dev) |
4014 | { | |
4015 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4016 | ||
11782b02 | 4017 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4018 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4019 | return; | |
4020 | ||
4021 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4022 | DISP_TILE_SURFACE_SWIZZLING); | |
4023 | ||
11782b02 DV |
4024 | if (IS_GEN5(dev)) |
4025 | return; | |
4026 | ||
f691e2f4 DV |
4027 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4028 | if (IS_GEN6(dev)) | |
6b26c86d | 4029 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4030 | else if (IS_GEN7(dev)) |
6b26c86d | 4031 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
4032 | else |
4033 | BUG(); | |
f691e2f4 | 4034 | } |
e21af88d | 4035 | |
67b1b571 CW |
4036 | static bool |
4037 | intel_enable_blt(struct drm_device *dev) | |
4038 | { | |
4039 | if (!HAS_BLT(dev)) | |
4040 | return false; | |
4041 | ||
4042 | /* The blitter was dysfunctional on early prototypes */ | |
4043 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4044 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4045 | " graphics performance will be degraded.\n"); | |
4046 | return false; | |
4047 | } | |
4048 | ||
4049 | return true; | |
4050 | } | |
4051 | ||
4fc7c971 | 4052 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4053 | { |
4fc7c971 | 4054 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4055 | int ret; |
68f95ba9 | 4056 | |
5c1143bb | 4057 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4058 | if (ret) |
b6913e4b | 4059 | return ret; |
68f95ba9 CW |
4060 | |
4061 | if (HAS_BSD(dev)) { | |
5c1143bb | 4062 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4063 | if (ret) |
4064 | goto cleanup_render_ring; | |
d1b851fc | 4065 | } |
68f95ba9 | 4066 | |
67b1b571 | 4067 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4068 | ret = intel_init_blt_ring_buffer(dev); |
4069 | if (ret) | |
4070 | goto cleanup_bsd_ring; | |
4071 | } | |
4072 | ||
9a8a2213 BW |
4073 | if (HAS_VEBOX(dev)) { |
4074 | ret = intel_init_vebox_ring_buffer(dev); | |
4075 | if (ret) | |
4076 | goto cleanup_blt_ring; | |
4077 | } | |
4078 | ||
4079 | ||
99433931 | 4080 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4081 | if (ret) |
9a8a2213 | 4082 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4083 | |
4084 | return 0; | |
4085 | ||
9a8a2213 BW |
4086 | cleanup_vebox_ring: |
4087 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4088 | cleanup_blt_ring: |
4089 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4090 | cleanup_bsd_ring: | |
4091 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4092 | cleanup_render_ring: | |
4093 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4094 | ||
4095 | return ret; | |
4096 | } | |
4097 | ||
4098 | int | |
4099 | i915_gem_init_hw(struct drm_device *dev) | |
4100 | { | |
4101 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4102 | int ret; | |
4103 | ||
4104 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4105 | return -EIO; | |
4106 | ||
4107 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) | |
4108 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
4109 | ||
88a2b2a3 BW |
4110 | if (HAS_PCH_NOP(dev)) { |
4111 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4112 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4113 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4114 | } | |
4115 | ||
4fc7c971 BW |
4116 | i915_gem_l3_remap(dev); |
4117 | ||
4118 | i915_gem_init_swizzling(dev); | |
4119 | ||
4120 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4121 | if (ret) |
4122 | return ret; | |
4123 | ||
254f965c BW |
4124 | /* |
4125 | * XXX: There was some w/a described somewhere suggesting loading | |
4126 | * contexts before PPGTT. | |
4127 | */ | |
4128 | i915_gem_context_init(dev); | |
b7c36d25 BW |
4129 | if (dev_priv->mm.aliasing_ppgtt) { |
4130 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4131 | if (ret) { | |
4132 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4133 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4134 | } | |
4135 | } | |
e21af88d | 4136 | |
68f95ba9 | 4137 | return 0; |
8187a2b7 ZN |
4138 | } |
4139 | ||
1070a42b CW |
4140 | int i915_gem_init(struct drm_device *dev) |
4141 | { | |
4142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4143 | int ret; |
4144 | ||
1070a42b | 4145 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4146 | |
4147 | if (IS_VALLEYVIEW(dev)) { | |
4148 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4149 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4150 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4151 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4152 | } | |
4153 | ||
d7e5008f | 4154 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4155 | |
1070a42b CW |
4156 | ret = i915_gem_init_hw(dev); |
4157 | mutex_unlock(&dev->struct_mutex); | |
4158 | if (ret) { | |
4159 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4160 | return ret; | |
4161 | } | |
4162 | ||
53ca26ca DV |
4163 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4164 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4165 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4166 | return 0; |
4167 | } | |
4168 | ||
8187a2b7 ZN |
4169 | void |
4170 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4171 | { | |
4172 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4173 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4174 | int i; |
8187a2b7 | 4175 | |
b4519513 CW |
4176 | for_each_ring(ring, dev_priv, i) |
4177 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4178 | } |
4179 | ||
673a394b EA |
4180 | int |
4181 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4182 | struct drm_file *file_priv) | |
4183 | { | |
db1b76ca | 4184 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4185 | int ret; |
673a394b | 4186 | |
79e53945 JB |
4187 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4188 | return 0; | |
4189 | ||
1f83fee0 | 4190 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4191 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4192 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4193 | } |
4194 | ||
673a394b | 4195 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4196 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4197 | |
f691e2f4 | 4198 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4199 | if (ret != 0) { |
4200 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4201 | return ret; |
d816f6ac | 4202 | } |
9bb2d6f9 | 4203 | |
69dc4987 | 4204 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4205 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4206 | |
5f35308b CW |
4207 | ret = drm_irq_install(dev); |
4208 | if (ret) | |
4209 | goto cleanup_ringbuffer; | |
dbb19d30 | 4210 | |
673a394b | 4211 | return 0; |
5f35308b CW |
4212 | |
4213 | cleanup_ringbuffer: | |
4214 | mutex_lock(&dev->struct_mutex); | |
4215 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4216 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4217 | mutex_unlock(&dev->struct_mutex); |
4218 | ||
4219 | return ret; | |
673a394b EA |
4220 | } |
4221 | ||
4222 | int | |
4223 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4224 | struct drm_file *file_priv) | |
4225 | { | |
db1b76ca DV |
4226 | struct drm_i915_private *dev_priv = dev->dev_private; |
4227 | int ret; | |
4228 | ||
79e53945 JB |
4229 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4230 | return 0; | |
4231 | ||
dbb19d30 | 4232 | drm_irq_uninstall(dev); |
db1b76ca DV |
4233 | |
4234 | mutex_lock(&dev->struct_mutex); | |
4235 | ret = i915_gem_idle(dev); | |
4236 | ||
4237 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4238 | * We need to replace this with a semaphore, or something. | |
4239 | * And not confound ums.mm_suspended! | |
4240 | */ | |
4241 | if (ret != 0) | |
4242 | dev_priv->ums.mm_suspended = 1; | |
4243 | mutex_unlock(&dev->struct_mutex); | |
4244 | ||
4245 | return ret; | |
673a394b EA |
4246 | } |
4247 | ||
4248 | void | |
4249 | i915_gem_lastclose(struct drm_device *dev) | |
4250 | { | |
4251 | int ret; | |
673a394b | 4252 | |
e806b495 EA |
4253 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4254 | return; | |
4255 | ||
db1b76ca | 4256 | mutex_lock(&dev->struct_mutex); |
6dbe2772 KP |
4257 | ret = i915_gem_idle(dev); |
4258 | if (ret) | |
4259 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
db1b76ca | 4260 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
4261 | } |
4262 | ||
64193406 CW |
4263 | static void |
4264 | init_ring_lists(struct intel_ring_buffer *ring) | |
4265 | { | |
4266 | INIT_LIST_HEAD(&ring->active_list); | |
4267 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4268 | } |
4269 | ||
673a394b EA |
4270 | void |
4271 | i915_gem_load(struct drm_device *dev) | |
4272 | { | |
4273 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4274 | int i; |
4275 | ||
4276 | dev_priv->slab = | |
4277 | kmem_cache_create("i915_gem_object", | |
4278 | sizeof(struct drm_i915_gem_object), 0, | |
4279 | SLAB_HWCACHE_ALIGN, | |
4280 | NULL); | |
673a394b | 4281 | |
69dc4987 | 4282 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4283 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4284 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4285 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4286 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4287 | for (i = 0; i < I915_NUM_RINGS; i++) |
4288 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4289 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4290 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4291 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4292 | i915_gem_retire_work_handler); | |
1f83fee0 | 4293 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4294 | |
94400120 DA |
4295 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4296 | if (IS_GEN3(dev)) { | |
50743298 DV |
4297 | I915_WRITE(MI_ARB_STATE, |
4298 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4299 | } |
4300 | ||
72bfa19c CW |
4301 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4302 | ||
de151cf6 | 4303 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4304 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4305 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4306 | |
42b5aeab VS |
4307 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4308 | dev_priv->num_fence_regs = 32; | |
4309 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4310 | dev_priv->num_fence_regs = 16; |
4311 | else | |
4312 | dev_priv->num_fence_regs = 8; | |
4313 | ||
b5aa8a0f | 4314 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4315 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4316 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4317 | |
673a394b | 4318 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4319 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4320 | |
ce453d81 CW |
4321 | dev_priv->mm.interruptible = true; |
4322 | ||
17250b71 CW |
4323 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4324 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4325 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4326 | } |
71acb5eb DA |
4327 | |
4328 | /* | |
4329 | * Create a physically contiguous memory object for this object | |
4330 | * e.g. for cursor + overlay regs | |
4331 | */ | |
995b6762 CW |
4332 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4333 | int id, int size, int align) | |
71acb5eb DA |
4334 | { |
4335 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4336 | struct drm_i915_gem_phys_object *phys_obj; | |
4337 | int ret; | |
4338 | ||
4339 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4340 | return 0; | |
4341 | ||
9a298b2a | 4342 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4343 | if (!phys_obj) |
4344 | return -ENOMEM; | |
4345 | ||
4346 | phys_obj->id = id; | |
4347 | ||
6eeefaf3 | 4348 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4349 | if (!phys_obj->handle) { |
4350 | ret = -ENOMEM; | |
4351 | goto kfree_obj; | |
4352 | } | |
4353 | #ifdef CONFIG_X86 | |
4354 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4355 | #endif | |
4356 | ||
4357 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4358 | ||
4359 | return 0; | |
4360 | kfree_obj: | |
9a298b2a | 4361 | kfree(phys_obj); |
71acb5eb DA |
4362 | return ret; |
4363 | } | |
4364 | ||
995b6762 | 4365 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4366 | { |
4367 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4368 | struct drm_i915_gem_phys_object *phys_obj; | |
4369 | ||
4370 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4371 | return; | |
4372 | ||
4373 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4374 | if (phys_obj->cur_obj) { | |
4375 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4376 | } | |
4377 | ||
4378 | #ifdef CONFIG_X86 | |
4379 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4380 | #endif | |
4381 | drm_pci_free(dev, phys_obj->handle); | |
4382 | kfree(phys_obj); | |
4383 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4384 | } | |
4385 | ||
4386 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4387 | { | |
4388 | int i; | |
4389 | ||
260883c8 | 4390 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4391 | i915_gem_free_phys_object(dev, i); |
4392 | } | |
4393 | ||
4394 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4395 | struct drm_i915_gem_object *obj) |
71acb5eb | 4396 | { |
496ad9aa | 4397 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4398 | char *vaddr; |
71acb5eb | 4399 | int i; |
71acb5eb DA |
4400 | int page_count; |
4401 | ||
05394f39 | 4402 | if (!obj->phys_obj) |
71acb5eb | 4403 | return; |
05394f39 | 4404 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4405 | |
05394f39 | 4406 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4407 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4408 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4409 | if (!IS_ERR(page)) { |
4410 | char *dst = kmap_atomic(page); | |
4411 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4412 | kunmap_atomic(dst); | |
4413 | ||
4414 | drm_clflush_pages(&page, 1); | |
4415 | ||
4416 | set_page_dirty(page); | |
4417 | mark_page_accessed(page); | |
4418 | page_cache_release(page); | |
4419 | } | |
71acb5eb | 4420 | } |
e76e9aeb | 4421 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4422 | |
05394f39 CW |
4423 | obj->phys_obj->cur_obj = NULL; |
4424 | obj->phys_obj = NULL; | |
71acb5eb DA |
4425 | } |
4426 | ||
4427 | int | |
4428 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4429 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4430 | int id, |
4431 | int align) | |
71acb5eb | 4432 | { |
496ad9aa | 4433 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4434 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4435 | int ret = 0; |
4436 | int page_count; | |
4437 | int i; | |
4438 | ||
4439 | if (id > I915_MAX_PHYS_OBJECT) | |
4440 | return -EINVAL; | |
4441 | ||
05394f39 CW |
4442 | if (obj->phys_obj) { |
4443 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4444 | return 0; |
4445 | i915_gem_detach_phys_object(dev, obj); | |
4446 | } | |
4447 | ||
71acb5eb DA |
4448 | /* create a new object */ |
4449 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4450 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4451 | obj->base.size, align); |
71acb5eb | 4452 | if (ret) { |
05394f39 CW |
4453 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4454 | id, obj->base.size); | |
e5281ccd | 4455 | return ret; |
71acb5eb DA |
4456 | } |
4457 | } | |
4458 | ||
4459 | /* bind to the object */ | |
05394f39 CW |
4460 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4461 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4462 | |
05394f39 | 4463 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4464 | |
4465 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4466 | struct page *page; |
4467 | char *dst, *src; | |
4468 | ||
5949eac4 | 4469 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4470 | if (IS_ERR(page)) |
4471 | return PTR_ERR(page); | |
71acb5eb | 4472 | |
ff75b9bc | 4473 | src = kmap_atomic(page); |
05394f39 | 4474 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4475 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4476 | kunmap_atomic(src); |
71acb5eb | 4477 | |
e5281ccd CW |
4478 | mark_page_accessed(page); |
4479 | page_cache_release(page); | |
4480 | } | |
d78b47b9 | 4481 | |
71acb5eb | 4482 | return 0; |
71acb5eb DA |
4483 | } |
4484 | ||
4485 | static int | |
05394f39 CW |
4486 | i915_gem_phys_pwrite(struct drm_device *dev, |
4487 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4488 | struct drm_i915_gem_pwrite *args, |
4489 | struct drm_file *file_priv) | |
4490 | { | |
05394f39 | 4491 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4492 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4493 | |
b47b30cc CW |
4494 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4495 | unsigned long unwritten; | |
4496 | ||
4497 | /* The physical object once assigned is fixed for the lifetime | |
4498 | * of the obj, so we can safely drop the lock and continue | |
4499 | * to access vaddr. | |
4500 | */ | |
4501 | mutex_unlock(&dev->struct_mutex); | |
4502 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4503 | mutex_lock(&dev->struct_mutex); | |
4504 | if (unwritten) | |
4505 | return -EFAULT; | |
4506 | } | |
71acb5eb | 4507 | |
e76e9aeb | 4508 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4509 | return 0; |
4510 | } | |
b962442e | 4511 | |
f787a5f5 | 4512 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4513 | { |
f787a5f5 | 4514 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4515 | |
4516 | /* Clean up our request list when the client is going away, so that | |
4517 | * later retire_requests won't dereference our soon-to-be-gone | |
4518 | * file_priv. | |
4519 | */ | |
1c25595f | 4520 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4521 | while (!list_empty(&file_priv->mm.request_list)) { |
4522 | struct drm_i915_gem_request *request; | |
4523 | ||
4524 | request = list_first_entry(&file_priv->mm.request_list, | |
4525 | struct drm_i915_gem_request, | |
4526 | client_list); | |
4527 | list_del(&request->client_list); | |
4528 | request->file_priv = NULL; | |
4529 | } | |
1c25595f | 4530 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4531 | } |
31169714 | 4532 | |
5774506f CW |
4533 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4534 | { | |
4535 | if (!mutex_is_locked(mutex)) | |
4536 | return false; | |
4537 | ||
4538 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4539 | return mutex->owner == task; | |
4540 | #else | |
4541 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4542 | return false; | |
4543 | #endif | |
4544 | } | |
4545 | ||
31169714 | 4546 | static int |
1495f230 | 4547 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4548 | { |
17250b71 CW |
4549 | struct drm_i915_private *dev_priv = |
4550 | container_of(shrinker, | |
4551 | struct drm_i915_private, | |
4552 | mm.inactive_shrinker); | |
4553 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4554 | struct drm_i915_gem_object *obj; |
1495f230 | 4555 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4556 | bool unlock = true; |
17250b71 CW |
4557 | int cnt; |
4558 | ||
5774506f CW |
4559 | if (!mutex_trylock(&dev->struct_mutex)) { |
4560 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4561 | return 0; | |
4562 | ||
677feac2 DV |
4563 | if (dev_priv->mm.shrinker_no_lock_stealing) |
4564 | return 0; | |
4565 | ||
5774506f CW |
4566 | unlock = false; |
4567 | } | |
31169714 | 4568 | |
6c085a72 CW |
4569 | if (nr_to_scan) { |
4570 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
93927ca5 DV |
4571 | if (nr_to_scan > 0) |
4572 | nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan, | |
4573 | false); | |
6c085a72 CW |
4574 | if (nr_to_scan > 0) |
4575 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4576 | } |
4577 | ||
17250b71 | 4578 | cnt = 0; |
35c20a60 | 4579 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 CW |
4580 | if (obj->pages_pin_count == 0) |
4581 | cnt += obj->base.size >> PAGE_SHIFT; | |
06755608 | 4582 | list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) |
a5570178 | 4583 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4584 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4585 | |
5774506f CW |
4586 | if (unlock) |
4587 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4588 | return cnt; |
31169714 | 4589 | } |