Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
2cfcd32a | 34 | #include <linux/oom.h> |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
43 | bool force); | |
07fe0b12 | 44 | static __must_check int |
23f54483 BW |
45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
46 | bool readonly); | |
c8725f3d CW |
47 | static void |
48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
49 | ||
05394f39 CW |
50 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
51 | struct drm_i915_gem_object *obj, | |
71acb5eb | 52 | struct drm_i915_gem_pwrite *args, |
05394f39 | 53 | struct drm_file *file); |
673a394b | 54 | |
61050808 CW |
55 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
56 | struct drm_i915_gem_object *obj); | |
57 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
58 | struct drm_i915_fence_reg *fence, | |
59 | bool enable); | |
60 | ||
ceabbba5 | 61 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 62 | struct shrink_control *sc); |
ceabbba5 | 63 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 64 | struct shrink_control *sc); |
2cfcd32a CW |
65 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
66 | unsigned long event, | |
67 | void *ptr); | |
d9973b43 CW |
68 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
69 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
31169714 | 70 | |
c76ce038 CW |
71 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
72 | enum i915_cache_level level) | |
73 | { | |
74 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
75 | } | |
76 | ||
2c22569b CW |
77 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
78 | { | |
79 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
80 | return true; | |
81 | ||
82 | return obj->pin_display; | |
83 | } | |
84 | ||
61050808 CW |
85 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
86 | { | |
87 | if (obj->tiling_mode) | |
88 | i915_gem_release_mmap(obj); | |
89 | ||
90 | /* As we do not have an associated fence register, we will force | |
91 | * a tiling change if we ever need to acquire one. | |
92 | */ | |
5d82e3e6 | 93 | obj->fence_dirty = false; |
61050808 CW |
94 | obj->fence_reg = I915_FENCE_REG_NONE; |
95 | } | |
96 | ||
73aa808f CW |
97 | /* some bookkeeping */ |
98 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
99 | size_t size) | |
100 | { | |
c20e8355 | 101 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
102 | dev_priv->mm.object_count++; |
103 | dev_priv->mm.object_memory += size; | |
c20e8355 | 104 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | } |
106 | ||
107 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
108 | size_t size) | |
109 | { | |
c20e8355 | 110 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
111 | dev_priv->mm.object_count--; |
112 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 113 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
114 | } |
115 | ||
21dd3734 | 116 | static int |
33196ded | 117 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 118 | { |
30dbf0c0 CW |
119 | int ret; |
120 | ||
7abb690a DV |
121 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
122 | i915_terminally_wedged(error)) | |
1f83fee0 | 123 | if (EXIT_COND) |
30dbf0c0 CW |
124 | return 0; |
125 | ||
0a6759c6 DV |
126 | /* |
127 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
128 | * userspace. If it takes that long something really bad is going on and | |
129 | * we should simply try to bail out and fail as gracefully as possible. | |
130 | */ | |
1f83fee0 DV |
131 | ret = wait_event_interruptible_timeout(error->reset_queue, |
132 | EXIT_COND, | |
133 | 10*HZ); | |
0a6759c6 DV |
134 | if (ret == 0) { |
135 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
136 | return -EIO; | |
137 | } else if (ret < 0) { | |
30dbf0c0 | 138 | return ret; |
0a6759c6 | 139 | } |
1f83fee0 | 140 | #undef EXIT_COND |
30dbf0c0 | 141 | |
21dd3734 | 142 | return 0; |
30dbf0c0 CW |
143 | } |
144 | ||
54cf91dc | 145 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 146 | { |
33196ded | 147 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
148 | int ret; |
149 | ||
33196ded | 150 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
151 | if (ret) |
152 | return ret; | |
153 | ||
154 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
155 | if (ret) | |
156 | return ret; | |
157 | ||
23bc5982 | 158 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
159 | return 0; |
160 | } | |
30dbf0c0 | 161 | |
7d1c4804 | 162 | static inline bool |
05394f39 | 163 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 164 | { |
9843877d | 165 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
166 | } |
167 | ||
79e53945 JB |
168 | int |
169 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 170 | struct drm_file *file) |
79e53945 | 171 | { |
93d18799 | 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 173 | struct drm_i915_gem_init *args = data; |
2021746e | 174 | |
7bb6fb8d DV |
175 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
176 | return -ENODEV; | |
177 | ||
2021746e CW |
178 | if (args->gtt_start >= args->gtt_end || |
179 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
180 | return -EINVAL; | |
79e53945 | 181 | |
f534bc0b DV |
182 | /* GEM with user mode setting was never supported on ilk and later. */ |
183 | if (INTEL_INFO(dev)->gen >= 5) | |
184 | return -ENODEV; | |
185 | ||
79e53945 | 186 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
187 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
188 | args->gtt_end); | |
93d18799 | 189 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
190 | mutex_unlock(&dev->struct_mutex); |
191 | ||
2021746e | 192 | return 0; |
673a394b EA |
193 | } |
194 | ||
5a125c3c EA |
195 | int |
196 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 197 | struct drm_file *file) |
5a125c3c | 198 | { |
73aa808f | 199 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 200 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
201 | struct drm_i915_gem_object *obj; |
202 | size_t pinned; | |
5a125c3c | 203 | |
6299f992 | 204 | pinned = 0; |
73aa808f | 205 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 206 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 207 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 208 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 209 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 210 | |
853ba5d2 | 211 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 212 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 213 | |
5a125c3c EA |
214 | return 0; |
215 | } | |
216 | ||
42dcedd4 CW |
217 | void *i915_gem_object_alloc(struct drm_device *dev) |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 220 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
221 | } |
222 | ||
223 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
224 | { | |
225 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
226 | kmem_cache_free(dev_priv->slab, obj); | |
227 | } | |
228 | ||
ff72145b DA |
229 | static int |
230 | i915_gem_create(struct drm_file *file, | |
231 | struct drm_device *dev, | |
232 | uint64_t size, | |
233 | uint32_t *handle_p) | |
673a394b | 234 | { |
05394f39 | 235 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
236 | int ret; |
237 | u32 handle; | |
673a394b | 238 | |
ff72145b | 239 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
240 | if (size == 0) |
241 | return -EINVAL; | |
673a394b EA |
242 | |
243 | /* Allocate the new object */ | |
ff72145b | 244 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
245 | if (obj == NULL) |
246 | return -ENOMEM; | |
247 | ||
05394f39 | 248 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 249 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
250 | drm_gem_object_unreference_unlocked(&obj->base); |
251 | if (ret) | |
252 | return ret; | |
202f2fef | 253 | |
ff72145b | 254 | *handle_p = handle; |
673a394b EA |
255 | return 0; |
256 | } | |
257 | ||
ff72145b DA |
258 | int |
259 | i915_gem_dumb_create(struct drm_file *file, | |
260 | struct drm_device *dev, | |
261 | struct drm_mode_create_dumb *args) | |
262 | { | |
263 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 264 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
265 | args->size = args->pitch * args->height; |
266 | return i915_gem_create(file, dev, | |
267 | args->size, &args->handle); | |
268 | } | |
269 | ||
ff72145b DA |
270 | /** |
271 | * Creates a new mm object and returns a handle to it. | |
272 | */ | |
273 | int | |
274 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
275 | struct drm_file *file) | |
276 | { | |
277 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 278 | |
ff72145b DA |
279 | return i915_gem_create(file, dev, |
280 | args->size, &args->handle); | |
281 | } | |
282 | ||
8461d226 DV |
283 | static inline int |
284 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
285 | const char *gpu_vaddr, int gpu_offset, | |
286 | int length) | |
287 | { | |
288 | int ret, cpu_offset = 0; | |
289 | ||
290 | while (length > 0) { | |
291 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
292 | int this_length = min(cacheline_end - gpu_offset, length); | |
293 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
294 | ||
295 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
296 | gpu_vaddr + swizzled_gpu_offset, | |
297 | this_length); | |
298 | if (ret) | |
299 | return ret + length; | |
300 | ||
301 | cpu_offset += this_length; | |
302 | gpu_offset += this_length; | |
303 | length -= this_length; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
8c59967c | 309 | static inline int |
4f0c7cfb BW |
310 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
311 | const char __user *cpu_vaddr, | |
8c59967c DV |
312 | int length) |
313 | { | |
314 | int ret, cpu_offset = 0; | |
315 | ||
316 | while (length > 0) { | |
317 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
318 | int this_length = min(cacheline_end - gpu_offset, length); | |
319 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
320 | ||
321 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
322 | cpu_vaddr + cpu_offset, | |
323 | this_length); | |
324 | if (ret) | |
325 | return ret + length; | |
326 | ||
327 | cpu_offset += this_length; | |
328 | gpu_offset += this_length; | |
329 | length -= this_length; | |
330 | } | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
4c914c0c BV |
335 | /* |
336 | * Pins the specified object's pages and synchronizes the object with | |
337 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
338 | * flush the object from the CPU cache. | |
339 | */ | |
340 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
341 | int *needs_clflush) | |
342 | { | |
343 | int ret; | |
344 | ||
345 | *needs_clflush = 0; | |
346 | ||
347 | if (!obj->base.filp) | |
348 | return -EINVAL; | |
349 | ||
350 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
351 | /* If we're not in the cpu read domain, set ourself into the gtt | |
352 | * read domain and manually flush cachelines (if required). This | |
353 | * optimizes for the case when the gpu will dirty the data | |
354 | * anyway again before the next pread happens. */ | |
355 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
356 | obj->cache_level); | |
357 | ret = i915_gem_object_wait_rendering(obj, true); | |
358 | if (ret) | |
359 | return ret; | |
c8725f3d CW |
360 | |
361 | i915_gem_object_retire(obj); | |
4c914c0c BV |
362 | } |
363 | ||
364 | ret = i915_gem_object_get_pages(obj); | |
365 | if (ret) | |
366 | return ret; | |
367 | ||
368 | i915_gem_object_pin_pages(obj); | |
369 | ||
370 | return ret; | |
371 | } | |
372 | ||
d174bd64 DV |
373 | /* Per-page copy function for the shmem pread fastpath. |
374 | * Flushes invalid cachelines before reading the target if | |
375 | * needs_clflush is set. */ | |
eb01459f | 376 | static int |
d174bd64 DV |
377 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
378 | char __user *user_data, | |
379 | bool page_do_bit17_swizzling, bool needs_clflush) | |
380 | { | |
381 | char *vaddr; | |
382 | int ret; | |
383 | ||
e7e58eb5 | 384 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
385 | return -EINVAL; |
386 | ||
387 | vaddr = kmap_atomic(page); | |
388 | if (needs_clflush) | |
389 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
390 | page_length); | |
391 | ret = __copy_to_user_inatomic(user_data, | |
392 | vaddr + shmem_page_offset, | |
393 | page_length); | |
394 | kunmap_atomic(vaddr); | |
395 | ||
f60d7f0c | 396 | return ret ? -EFAULT : 0; |
d174bd64 DV |
397 | } |
398 | ||
23c18c71 DV |
399 | static void |
400 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
401 | bool swizzled) | |
402 | { | |
e7e58eb5 | 403 | if (unlikely(swizzled)) { |
23c18c71 DV |
404 | unsigned long start = (unsigned long) addr; |
405 | unsigned long end = (unsigned long) addr + length; | |
406 | ||
407 | /* For swizzling simply ensure that we always flush both | |
408 | * channels. Lame, but simple and it works. Swizzled | |
409 | * pwrite/pread is far from a hotpath - current userspace | |
410 | * doesn't use it at all. */ | |
411 | start = round_down(start, 128); | |
412 | end = round_up(end, 128); | |
413 | ||
414 | drm_clflush_virt_range((void *)start, end - start); | |
415 | } else { | |
416 | drm_clflush_virt_range(addr, length); | |
417 | } | |
418 | ||
419 | } | |
420 | ||
d174bd64 DV |
421 | /* Only difference to the fast-path function is that this can handle bit17 |
422 | * and uses non-atomic copy and kmap functions. */ | |
423 | static int | |
424 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
425 | char __user *user_data, | |
426 | bool page_do_bit17_swizzling, bool needs_clflush) | |
427 | { | |
428 | char *vaddr; | |
429 | int ret; | |
430 | ||
431 | vaddr = kmap(page); | |
432 | if (needs_clflush) | |
23c18c71 DV |
433 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
434 | page_length, | |
435 | page_do_bit17_swizzling); | |
d174bd64 DV |
436 | |
437 | if (page_do_bit17_swizzling) | |
438 | ret = __copy_to_user_swizzled(user_data, | |
439 | vaddr, shmem_page_offset, | |
440 | page_length); | |
441 | else | |
442 | ret = __copy_to_user(user_data, | |
443 | vaddr + shmem_page_offset, | |
444 | page_length); | |
445 | kunmap(page); | |
446 | ||
f60d7f0c | 447 | return ret ? - EFAULT : 0; |
d174bd64 DV |
448 | } |
449 | ||
eb01459f | 450 | static int |
dbf7bff0 DV |
451 | i915_gem_shmem_pread(struct drm_device *dev, |
452 | struct drm_i915_gem_object *obj, | |
453 | struct drm_i915_gem_pread *args, | |
454 | struct drm_file *file) | |
eb01459f | 455 | { |
8461d226 | 456 | char __user *user_data; |
eb01459f | 457 | ssize_t remain; |
8461d226 | 458 | loff_t offset; |
eb2c0c81 | 459 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 460 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 461 | int prefaulted = 0; |
8489731c | 462 | int needs_clflush = 0; |
67d5a50c | 463 | struct sg_page_iter sg_iter; |
eb01459f | 464 | |
2bb4629a | 465 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
466 | remain = args->size; |
467 | ||
8461d226 | 468 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 469 | |
4c914c0c | 470 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
471 | if (ret) |
472 | return ret; | |
473 | ||
8461d226 | 474 | offset = args->offset; |
eb01459f | 475 | |
67d5a50c ID |
476 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
477 | offset >> PAGE_SHIFT) { | |
2db76d7c | 478 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
479 | |
480 | if (remain <= 0) | |
481 | break; | |
482 | ||
eb01459f EA |
483 | /* Operation in this page |
484 | * | |
eb01459f | 485 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
486 | * page_length = bytes to copy for this page |
487 | */ | |
c8cbbb8b | 488 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
489 | page_length = remain; |
490 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
491 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 492 | |
8461d226 DV |
493 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
494 | (page_to_phys(page) & (1 << 17)) != 0; | |
495 | ||
d174bd64 DV |
496 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
497 | user_data, page_do_bit17_swizzling, | |
498 | needs_clflush); | |
499 | if (ret == 0) | |
500 | goto next_page; | |
dbf7bff0 | 501 | |
dbf7bff0 DV |
502 | mutex_unlock(&dev->struct_mutex); |
503 | ||
d330a953 | 504 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 505 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
506 | /* Userspace is tricking us, but we've already clobbered |
507 | * its pages with the prefault and promised to write the | |
508 | * data up to the first fault. Hence ignore any errors | |
509 | * and just continue. */ | |
510 | (void)ret; | |
511 | prefaulted = 1; | |
512 | } | |
eb01459f | 513 | |
d174bd64 DV |
514 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
515 | user_data, page_do_bit17_swizzling, | |
516 | needs_clflush); | |
eb01459f | 517 | |
dbf7bff0 | 518 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 519 | |
f60d7f0c | 520 | if (ret) |
8461d226 | 521 | goto out; |
8461d226 | 522 | |
17793c9a | 523 | next_page: |
eb01459f | 524 | remain -= page_length; |
8461d226 | 525 | user_data += page_length; |
eb01459f EA |
526 | offset += page_length; |
527 | } | |
528 | ||
4f27b75d | 529 | out: |
f60d7f0c CW |
530 | i915_gem_object_unpin_pages(obj); |
531 | ||
eb01459f EA |
532 | return ret; |
533 | } | |
534 | ||
673a394b EA |
535 | /** |
536 | * Reads data from the object referenced by handle. | |
537 | * | |
538 | * On error, the contents of *data are undefined. | |
539 | */ | |
540 | int | |
541 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 542 | struct drm_file *file) |
673a394b EA |
543 | { |
544 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 545 | struct drm_i915_gem_object *obj; |
35b62a89 | 546 | int ret = 0; |
673a394b | 547 | |
51311d0a CW |
548 | if (args->size == 0) |
549 | return 0; | |
550 | ||
551 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 552 | to_user_ptr(args->data_ptr), |
51311d0a CW |
553 | args->size)) |
554 | return -EFAULT; | |
555 | ||
4f27b75d | 556 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 557 | if (ret) |
4f27b75d | 558 | return ret; |
673a394b | 559 | |
05394f39 | 560 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 561 | if (&obj->base == NULL) { |
1d7cfea1 CW |
562 | ret = -ENOENT; |
563 | goto unlock; | |
4f27b75d | 564 | } |
673a394b | 565 | |
7dcd2499 | 566 | /* Bounds check source. */ |
05394f39 CW |
567 | if (args->offset > obj->base.size || |
568 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 569 | ret = -EINVAL; |
35b62a89 | 570 | goto out; |
ce9d419d CW |
571 | } |
572 | ||
1286ff73 DV |
573 | /* prime objects have no backing filp to GEM pread/pwrite |
574 | * pages from. | |
575 | */ | |
576 | if (!obj->base.filp) { | |
577 | ret = -EINVAL; | |
578 | goto out; | |
579 | } | |
580 | ||
db53a302 CW |
581 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
582 | ||
dbf7bff0 | 583 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 584 | |
35b62a89 | 585 | out: |
05394f39 | 586 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 587 | unlock: |
4f27b75d | 588 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 589 | return ret; |
673a394b EA |
590 | } |
591 | ||
0839ccb8 KP |
592 | /* This is the fast write path which cannot handle |
593 | * page faults in the source data | |
9b7530cc | 594 | */ |
0839ccb8 KP |
595 | |
596 | static inline int | |
597 | fast_user_write(struct io_mapping *mapping, | |
598 | loff_t page_base, int page_offset, | |
599 | char __user *user_data, | |
600 | int length) | |
9b7530cc | 601 | { |
4f0c7cfb BW |
602 | void __iomem *vaddr_atomic; |
603 | void *vaddr; | |
0839ccb8 | 604 | unsigned long unwritten; |
9b7530cc | 605 | |
3e4d3af5 | 606 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
607 | /* We can use the cpu mem copy function because this is X86. */ |
608 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
609 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 610 | user_data, length); |
3e4d3af5 | 611 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 612 | return unwritten; |
0839ccb8 KP |
613 | } |
614 | ||
3de09aa3 EA |
615 | /** |
616 | * This is the fast pwrite path, where we copy the data directly from the | |
617 | * user into the GTT, uncached. | |
618 | */ | |
673a394b | 619 | static int |
05394f39 CW |
620 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
621 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 622 | struct drm_i915_gem_pwrite *args, |
05394f39 | 623 | struct drm_file *file) |
673a394b | 624 | { |
3e31c6c0 | 625 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 626 | ssize_t remain; |
0839ccb8 | 627 | loff_t offset, page_base; |
673a394b | 628 | char __user *user_data; |
935aaa69 DV |
629 | int page_offset, page_length, ret; |
630 | ||
1ec9e26d | 631 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
632 | if (ret) |
633 | goto out; | |
634 | ||
635 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
636 | if (ret) | |
637 | goto out_unpin; | |
638 | ||
639 | ret = i915_gem_object_put_fence(obj); | |
640 | if (ret) | |
641 | goto out_unpin; | |
673a394b | 642 | |
2bb4629a | 643 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 644 | remain = args->size; |
673a394b | 645 | |
f343c5f6 | 646 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
647 | |
648 | while (remain > 0) { | |
649 | /* Operation in this page | |
650 | * | |
0839ccb8 KP |
651 | * page_base = page offset within aperture |
652 | * page_offset = offset within page | |
653 | * page_length = bytes to copy for this page | |
673a394b | 654 | */ |
c8cbbb8b CW |
655 | page_base = offset & PAGE_MASK; |
656 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
657 | page_length = remain; |
658 | if ((page_offset + remain) > PAGE_SIZE) | |
659 | page_length = PAGE_SIZE - page_offset; | |
660 | ||
0839ccb8 | 661 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
662 | * source page isn't available. Return the error and we'll |
663 | * retry in the slow path. | |
0839ccb8 | 664 | */ |
5d4545ae | 665 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
666 | page_offset, user_data, page_length)) { |
667 | ret = -EFAULT; | |
668 | goto out_unpin; | |
669 | } | |
673a394b | 670 | |
0839ccb8 KP |
671 | remain -= page_length; |
672 | user_data += page_length; | |
673 | offset += page_length; | |
673a394b | 674 | } |
673a394b | 675 | |
935aaa69 | 676 | out_unpin: |
d7f46fc4 | 677 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 678 | out: |
3de09aa3 | 679 | return ret; |
673a394b EA |
680 | } |
681 | ||
d174bd64 DV |
682 | /* Per-page copy function for the shmem pwrite fastpath. |
683 | * Flushes invalid cachelines before writing to the target if | |
684 | * needs_clflush_before is set and flushes out any written cachelines after | |
685 | * writing if needs_clflush is set. */ | |
3043c60c | 686 | static int |
d174bd64 DV |
687 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
688 | char __user *user_data, | |
689 | bool page_do_bit17_swizzling, | |
690 | bool needs_clflush_before, | |
691 | bool needs_clflush_after) | |
673a394b | 692 | { |
d174bd64 | 693 | char *vaddr; |
673a394b | 694 | int ret; |
3de09aa3 | 695 | |
e7e58eb5 | 696 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 697 | return -EINVAL; |
3de09aa3 | 698 | |
d174bd64 DV |
699 | vaddr = kmap_atomic(page); |
700 | if (needs_clflush_before) | |
701 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
702 | page_length); | |
c2831a94 CW |
703 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
704 | user_data, page_length); | |
d174bd64 DV |
705 | if (needs_clflush_after) |
706 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
707 | page_length); | |
708 | kunmap_atomic(vaddr); | |
3de09aa3 | 709 | |
755d2218 | 710 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
711 | } |
712 | ||
d174bd64 DV |
713 | /* Only difference to the fast-path function is that this can handle bit17 |
714 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 715 | static int |
d174bd64 DV |
716 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
717 | char __user *user_data, | |
718 | bool page_do_bit17_swizzling, | |
719 | bool needs_clflush_before, | |
720 | bool needs_clflush_after) | |
673a394b | 721 | { |
d174bd64 DV |
722 | char *vaddr; |
723 | int ret; | |
e5281ccd | 724 | |
d174bd64 | 725 | vaddr = kmap(page); |
e7e58eb5 | 726 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
727 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
728 | page_length, | |
729 | page_do_bit17_swizzling); | |
d174bd64 DV |
730 | if (page_do_bit17_swizzling) |
731 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
732 | user_data, |
733 | page_length); | |
d174bd64 DV |
734 | else |
735 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
736 | user_data, | |
737 | page_length); | |
738 | if (needs_clflush_after) | |
23c18c71 DV |
739 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
740 | page_length, | |
741 | page_do_bit17_swizzling); | |
d174bd64 | 742 | kunmap(page); |
40123c1f | 743 | |
755d2218 | 744 | return ret ? -EFAULT : 0; |
40123c1f EA |
745 | } |
746 | ||
40123c1f | 747 | static int |
e244a443 DV |
748 | i915_gem_shmem_pwrite(struct drm_device *dev, |
749 | struct drm_i915_gem_object *obj, | |
750 | struct drm_i915_gem_pwrite *args, | |
751 | struct drm_file *file) | |
40123c1f | 752 | { |
40123c1f | 753 | ssize_t remain; |
8c59967c DV |
754 | loff_t offset; |
755 | char __user *user_data; | |
eb2c0c81 | 756 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 757 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 758 | int hit_slowpath = 0; |
58642885 DV |
759 | int needs_clflush_after = 0; |
760 | int needs_clflush_before = 0; | |
67d5a50c | 761 | struct sg_page_iter sg_iter; |
40123c1f | 762 | |
2bb4629a | 763 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
764 | remain = args->size; |
765 | ||
8c59967c | 766 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 767 | |
58642885 DV |
768 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
769 | /* If we're not in the cpu write domain, set ourself into the gtt | |
770 | * write domain and manually flush cachelines (if required). This | |
771 | * optimizes for the case when the gpu will use the data | |
772 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 773 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
774 | ret = i915_gem_object_wait_rendering(obj, false); |
775 | if (ret) | |
776 | return ret; | |
c8725f3d CW |
777 | |
778 | i915_gem_object_retire(obj); | |
58642885 | 779 | } |
c76ce038 CW |
780 | /* Same trick applies to invalidate partially written cachelines read |
781 | * before writing. */ | |
782 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
783 | needs_clflush_before = | |
784 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 785 | |
755d2218 CW |
786 | ret = i915_gem_object_get_pages(obj); |
787 | if (ret) | |
788 | return ret; | |
789 | ||
790 | i915_gem_object_pin_pages(obj); | |
791 | ||
673a394b | 792 | offset = args->offset; |
05394f39 | 793 | obj->dirty = 1; |
673a394b | 794 | |
67d5a50c ID |
795 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
796 | offset >> PAGE_SHIFT) { | |
2db76d7c | 797 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 798 | int partial_cacheline_write; |
e5281ccd | 799 | |
9da3da66 CW |
800 | if (remain <= 0) |
801 | break; | |
802 | ||
40123c1f EA |
803 | /* Operation in this page |
804 | * | |
40123c1f | 805 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
806 | * page_length = bytes to copy for this page |
807 | */ | |
c8cbbb8b | 808 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
809 | |
810 | page_length = remain; | |
811 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
812 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 813 | |
58642885 DV |
814 | /* If we don't overwrite a cacheline completely we need to be |
815 | * careful to have up-to-date data by first clflushing. Don't | |
816 | * overcomplicate things and flush the entire patch. */ | |
817 | partial_cacheline_write = needs_clflush_before && | |
818 | ((shmem_page_offset | page_length) | |
819 | & (boot_cpu_data.x86_clflush_size - 1)); | |
820 | ||
8c59967c DV |
821 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
822 | (page_to_phys(page) & (1 << 17)) != 0; | |
823 | ||
d174bd64 DV |
824 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
825 | user_data, page_do_bit17_swizzling, | |
826 | partial_cacheline_write, | |
827 | needs_clflush_after); | |
828 | if (ret == 0) | |
829 | goto next_page; | |
e244a443 DV |
830 | |
831 | hit_slowpath = 1; | |
e244a443 | 832 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
833 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
834 | user_data, page_do_bit17_swizzling, | |
835 | partial_cacheline_write, | |
836 | needs_clflush_after); | |
40123c1f | 837 | |
e244a443 | 838 | mutex_lock(&dev->struct_mutex); |
755d2218 | 839 | |
755d2218 | 840 | if (ret) |
8c59967c | 841 | goto out; |
8c59967c | 842 | |
17793c9a | 843 | next_page: |
40123c1f | 844 | remain -= page_length; |
8c59967c | 845 | user_data += page_length; |
40123c1f | 846 | offset += page_length; |
673a394b EA |
847 | } |
848 | ||
fbd5a26d | 849 | out: |
755d2218 CW |
850 | i915_gem_object_unpin_pages(obj); |
851 | ||
e244a443 | 852 | if (hit_slowpath) { |
8dcf015e DV |
853 | /* |
854 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
855 | * cachelines in-line while writing and the object moved | |
856 | * out of the cpu write domain while we've dropped the lock. | |
857 | */ | |
858 | if (!needs_clflush_after && | |
859 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
860 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
861 | i915_gem_chipset_flush(dev); | |
e244a443 | 862 | } |
8c59967c | 863 | } |
673a394b | 864 | |
58642885 | 865 | if (needs_clflush_after) |
e76e9aeb | 866 | i915_gem_chipset_flush(dev); |
58642885 | 867 | |
40123c1f | 868 | return ret; |
673a394b EA |
869 | } |
870 | ||
871 | /** | |
872 | * Writes data to the object referenced by handle. | |
873 | * | |
874 | * On error, the contents of the buffer that were to be modified are undefined. | |
875 | */ | |
876 | int | |
877 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 878 | struct drm_file *file) |
673a394b EA |
879 | { |
880 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 881 | struct drm_i915_gem_object *obj; |
51311d0a CW |
882 | int ret; |
883 | ||
884 | if (args->size == 0) | |
885 | return 0; | |
886 | ||
887 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 888 | to_user_ptr(args->data_ptr), |
51311d0a CW |
889 | args->size)) |
890 | return -EFAULT; | |
891 | ||
d330a953 | 892 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
893 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
894 | args->size); | |
895 | if (ret) | |
896 | return -EFAULT; | |
897 | } | |
673a394b | 898 | |
fbd5a26d | 899 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 900 | if (ret) |
fbd5a26d | 901 | return ret; |
1d7cfea1 | 902 | |
05394f39 | 903 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 904 | if (&obj->base == NULL) { |
1d7cfea1 CW |
905 | ret = -ENOENT; |
906 | goto unlock; | |
fbd5a26d | 907 | } |
673a394b | 908 | |
7dcd2499 | 909 | /* Bounds check destination. */ |
05394f39 CW |
910 | if (args->offset > obj->base.size || |
911 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 912 | ret = -EINVAL; |
35b62a89 | 913 | goto out; |
ce9d419d CW |
914 | } |
915 | ||
1286ff73 DV |
916 | /* prime objects have no backing filp to GEM pread/pwrite |
917 | * pages from. | |
918 | */ | |
919 | if (!obj->base.filp) { | |
920 | ret = -EINVAL; | |
921 | goto out; | |
922 | } | |
923 | ||
db53a302 CW |
924 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
925 | ||
935aaa69 | 926 | ret = -EFAULT; |
673a394b EA |
927 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
928 | * it would end up going through the fenced access, and we'll get | |
929 | * different detiling behavior between reading and writing. | |
930 | * pread/pwrite currently are reading and writing from the CPU | |
931 | * perspective, requiring manual detiling by the client. | |
932 | */ | |
5c0480f2 | 933 | if (obj->phys_obj) { |
fbd5a26d | 934 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
935 | goto out; |
936 | } | |
937 | ||
2c22569b CW |
938 | if (obj->tiling_mode == I915_TILING_NONE && |
939 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
940 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 941 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
942 | /* Note that the gtt paths might fail with non-page-backed user |
943 | * pointers (e.g. gtt mappings when moving data between | |
944 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 945 | } |
673a394b | 946 | |
86a1ee26 | 947 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 948 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 949 | |
35b62a89 | 950 | out: |
05394f39 | 951 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 952 | unlock: |
fbd5a26d | 953 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
954 | return ret; |
955 | } | |
956 | ||
b361237b | 957 | int |
33196ded | 958 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
959 | bool interruptible) |
960 | { | |
1f83fee0 | 961 | if (i915_reset_in_progress(error)) { |
b361237b CW |
962 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
963 | * -EIO unconditionally for these. */ | |
964 | if (!interruptible) | |
965 | return -EIO; | |
966 | ||
1f83fee0 DV |
967 | /* Recovery complete, but the reset failed ... */ |
968 | if (i915_terminally_wedged(error)) | |
b361237b CW |
969 | return -EIO; |
970 | ||
971 | return -EAGAIN; | |
972 | } | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
977 | /* | |
978 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
979 | * equal. | |
980 | */ | |
981 | static int | |
a4872ba6 | 982 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
b361237b CW |
983 | { |
984 | int ret; | |
985 | ||
986 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
987 | ||
988 | ret = 0; | |
1823521d | 989 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 990 | ret = i915_add_request(ring, NULL); |
b361237b CW |
991 | |
992 | return ret; | |
993 | } | |
994 | ||
094f9a54 CW |
995 | static void fake_irq(unsigned long data) |
996 | { | |
997 | wake_up_process((struct task_struct *)data); | |
998 | } | |
999 | ||
1000 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1001 | struct intel_engine_cs *ring) |
094f9a54 CW |
1002 | { |
1003 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1004 | } | |
1005 | ||
b29c19b6 CW |
1006 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1007 | { | |
1008 | if (file_priv == NULL) | |
1009 | return true; | |
1010 | ||
1011 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1012 | } | |
1013 | ||
b361237b CW |
1014 | /** |
1015 | * __wait_seqno - wait until execution of seqno has finished | |
1016 | * @ring: the ring expected to report seqno | |
1017 | * @seqno: duh! | |
f69061be | 1018 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
1019 | * @interruptible: do an interruptible wait (normally yes) |
1020 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1021 | * | |
f69061be DV |
1022 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1023 | * values have been read by the caller in an smp safe manner. Where read-side | |
1024 | * locks are involved, it is sufficient to read the reset_counter before | |
1025 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1026 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1027 | * inserted. | |
1028 | * | |
b361237b CW |
1029 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1030 | * errno with remaining time filled in timeout argument. | |
1031 | */ | |
a4872ba6 | 1032 | static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
f69061be | 1033 | unsigned reset_counter, |
b29c19b6 CW |
1034 | bool interruptible, |
1035 | struct timespec *timeout, | |
1036 | struct drm_i915_file_private *file_priv) | |
b361237b | 1037 | { |
3d13ef2e | 1038 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1039 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1040 | const bool irq_test_in_progress = |
1041 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 CW |
1042 | struct timespec before, now; |
1043 | DEFINE_WAIT(wait); | |
47e9766d | 1044 | unsigned long timeout_expire; |
b361237b CW |
1045 | int ret; |
1046 | ||
5d584b2e | 1047 | WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n"); |
c67a470b | 1048 | |
b361237b CW |
1049 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1050 | return 0; | |
1051 | ||
47e9766d | 1052 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
b361237b | 1053 | |
3d13ef2e | 1054 | if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1055 | gen6_rps_boost(dev_priv); |
1056 | if (file_priv) | |
1057 | mod_delayed_work(dev_priv->wq, | |
1058 | &file_priv->mm.idle_work, | |
1059 | msecs_to_jiffies(100)); | |
1060 | } | |
1061 | ||
168c3f21 | 1062 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1063 | return -ENODEV; |
1064 | ||
094f9a54 CW |
1065 | /* Record current time in case interrupted by signal, or wedged */ |
1066 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1067 | getrawmonotonic(&before); |
094f9a54 CW |
1068 | for (;;) { |
1069 | struct timer_list timer; | |
b361237b | 1070 | |
094f9a54 CW |
1071 | prepare_to_wait(&ring->irq_queue, &wait, |
1072 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1073 | |
f69061be DV |
1074 | /* We need to check whether any gpu reset happened in between |
1075 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1076 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1077 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1078 | * is truely gone. */ | |
1079 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1080 | if (ret == 0) | |
1081 | ret = -EAGAIN; | |
1082 | break; | |
1083 | } | |
f69061be | 1084 | |
094f9a54 CW |
1085 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1086 | ret = 0; | |
1087 | break; | |
1088 | } | |
b361237b | 1089 | |
094f9a54 CW |
1090 | if (interruptible && signal_pending(current)) { |
1091 | ret = -ERESTARTSYS; | |
1092 | break; | |
1093 | } | |
1094 | ||
47e9766d | 1095 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1096 | ret = -ETIME; |
1097 | break; | |
1098 | } | |
1099 | ||
1100 | timer.function = NULL; | |
1101 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1102 | unsigned long expire; |
1103 | ||
094f9a54 | 1104 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1105 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1106 | mod_timer(&timer, expire); |
1107 | } | |
1108 | ||
5035c275 | 1109 | io_schedule(); |
094f9a54 | 1110 | |
094f9a54 CW |
1111 | if (timer.function) { |
1112 | del_singleshot_timer_sync(&timer); | |
1113 | destroy_timer_on_stack(&timer); | |
1114 | } | |
1115 | } | |
b361237b | 1116 | getrawmonotonic(&now); |
094f9a54 | 1117 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1118 | |
168c3f21 MK |
1119 | if (!irq_test_in_progress) |
1120 | ring->irq_put(ring); | |
094f9a54 CW |
1121 | |
1122 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1123 | |
1124 | if (timeout) { | |
1125 | struct timespec sleep_time = timespec_sub(now, before); | |
1126 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1127 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1128 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1129 | } |
1130 | ||
094f9a54 | 1131 | return ret; |
b361237b CW |
1132 | } |
1133 | ||
1134 | /** | |
1135 | * Waits for a sequence number to be signaled, and cleans up the | |
1136 | * request and object lists appropriately for that event. | |
1137 | */ | |
1138 | int | |
a4872ba6 | 1139 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
b361237b CW |
1140 | { |
1141 | struct drm_device *dev = ring->dev; | |
1142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1143 | bool interruptible = dev_priv->mm.interruptible; | |
1144 | int ret; | |
1145 | ||
1146 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1147 | BUG_ON(seqno == 0); | |
1148 | ||
33196ded | 1149 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1150 | if (ret) |
1151 | return ret; | |
1152 | ||
1153 | ret = i915_gem_check_olr(ring, seqno); | |
1154 | if (ret) | |
1155 | return ret; | |
1156 | ||
f69061be DV |
1157 | return __wait_seqno(ring, seqno, |
1158 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1159 | interruptible, NULL, NULL); |
b361237b CW |
1160 | } |
1161 | ||
d26e3af8 CW |
1162 | static int |
1163 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
a4872ba6 | 1164 | struct intel_engine_cs *ring) |
d26e3af8 | 1165 | { |
c8725f3d CW |
1166 | if (!obj->active) |
1167 | return 0; | |
d26e3af8 CW |
1168 | |
1169 | /* Manually manage the write flush as we may have not yet | |
1170 | * retired the buffer. | |
1171 | * | |
1172 | * Note that the last_write_seqno is always the earlier of | |
1173 | * the two (read/write) seqno, so if we haved successfully waited, | |
1174 | * we know we have passed the last write. | |
1175 | */ | |
1176 | obj->last_write_seqno = 0; | |
d26e3af8 CW |
1177 | |
1178 | return 0; | |
1179 | } | |
1180 | ||
b361237b CW |
1181 | /** |
1182 | * Ensures that all rendering to the object has completed and the object is | |
1183 | * safe to unbind from the GTT or access from the CPU. | |
1184 | */ | |
1185 | static __must_check int | |
1186 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1187 | bool readonly) | |
1188 | { | |
a4872ba6 | 1189 | struct intel_engine_cs *ring = obj->ring; |
b361237b CW |
1190 | u32 seqno; |
1191 | int ret; | |
1192 | ||
1193 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1194 | if (seqno == 0) | |
1195 | return 0; | |
1196 | ||
1197 | ret = i915_wait_seqno(ring, seqno); | |
1198 | if (ret) | |
1199 | return ret; | |
1200 | ||
d26e3af8 | 1201 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1202 | } |
1203 | ||
3236f57a CW |
1204 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1205 | * as the object state may change during this call. | |
1206 | */ | |
1207 | static __must_check int | |
1208 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1209 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1210 | bool readonly) |
1211 | { | |
1212 | struct drm_device *dev = obj->base.dev; | |
1213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1214 | struct intel_engine_cs *ring = obj->ring; |
f69061be | 1215 | unsigned reset_counter; |
3236f57a CW |
1216 | u32 seqno; |
1217 | int ret; | |
1218 | ||
1219 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1220 | BUG_ON(!dev_priv->mm.interruptible); | |
1221 | ||
1222 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1223 | if (seqno == 0) | |
1224 | return 0; | |
1225 | ||
33196ded | 1226 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1227 | if (ret) |
1228 | return ret; | |
1229 | ||
1230 | ret = i915_gem_check_olr(ring, seqno); | |
1231 | if (ret) | |
1232 | return ret; | |
1233 | ||
f69061be | 1234 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1235 | mutex_unlock(&dev->struct_mutex); |
6e4930f6 | 1236 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
3236f57a | 1237 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1238 | if (ret) |
1239 | return ret; | |
3236f57a | 1240 | |
d26e3af8 | 1241 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1242 | } |
1243 | ||
673a394b | 1244 | /** |
2ef7eeaa EA |
1245 | * Called when user space prepares to use an object with the CPU, either |
1246 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1247 | */ |
1248 | int | |
1249 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1250 | struct drm_file *file) |
673a394b EA |
1251 | { |
1252 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1253 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1254 | uint32_t read_domains = args->read_domains; |
1255 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1256 | int ret; |
1257 | ||
2ef7eeaa | 1258 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1259 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1260 | return -EINVAL; |
1261 | ||
21d509e3 | 1262 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1263 | return -EINVAL; |
1264 | ||
1265 | /* Having something in the write domain implies it's in the read | |
1266 | * domain, and only that read domain. Enforce that in the request. | |
1267 | */ | |
1268 | if (write_domain != 0 && read_domains != write_domain) | |
1269 | return -EINVAL; | |
1270 | ||
76c1dec1 | 1271 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1272 | if (ret) |
76c1dec1 | 1273 | return ret; |
1d7cfea1 | 1274 | |
05394f39 | 1275 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1276 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1277 | ret = -ENOENT; |
1278 | goto unlock; | |
76c1dec1 | 1279 | } |
673a394b | 1280 | |
3236f57a CW |
1281 | /* Try to flush the object off the GPU without holding the lock. |
1282 | * We will repeat the flush holding the lock in the normal manner | |
1283 | * to catch cases where we are gazumped. | |
1284 | */ | |
6e4930f6 CW |
1285 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1286 | file->driver_priv, | |
1287 | !write_domain); | |
3236f57a CW |
1288 | if (ret) |
1289 | goto unref; | |
1290 | ||
2ef7eeaa EA |
1291 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1292 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1293 | |
1294 | /* Silently promote "you're not bound, there was nothing to do" | |
1295 | * to success, since the client was just asking us to | |
1296 | * make sure everything was done. | |
1297 | */ | |
1298 | if (ret == -EINVAL) | |
1299 | ret = 0; | |
2ef7eeaa | 1300 | } else { |
e47c68e9 | 1301 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1302 | } |
1303 | ||
3236f57a | 1304 | unref: |
05394f39 | 1305 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1306 | unlock: |
673a394b EA |
1307 | mutex_unlock(&dev->struct_mutex); |
1308 | return ret; | |
1309 | } | |
1310 | ||
1311 | /** | |
1312 | * Called when user space has done writes to this buffer | |
1313 | */ | |
1314 | int | |
1315 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1316 | struct drm_file *file) |
673a394b EA |
1317 | { |
1318 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1319 | struct drm_i915_gem_object *obj; |
673a394b EA |
1320 | int ret = 0; |
1321 | ||
76c1dec1 | 1322 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1323 | if (ret) |
76c1dec1 | 1324 | return ret; |
1d7cfea1 | 1325 | |
05394f39 | 1326 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1327 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1328 | ret = -ENOENT; |
1329 | goto unlock; | |
673a394b EA |
1330 | } |
1331 | ||
673a394b | 1332 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1333 | if (obj->pin_display) |
1334 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1335 | |
05394f39 | 1336 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1337 | unlock: |
673a394b EA |
1338 | mutex_unlock(&dev->struct_mutex); |
1339 | return ret; | |
1340 | } | |
1341 | ||
1342 | /** | |
1343 | * Maps the contents of an object, returning the address it is mapped | |
1344 | * into. | |
1345 | * | |
1346 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1347 | * imply a ref on the object itself. | |
1348 | */ | |
1349 | int | |
1350 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1351 | struct drm_file *file) |
673a394b EA |
1352 | { |
1353 | struct drm_i915_gem_mmap *args = data; | |
1354 | struct drm_gem_object *obj; | |
673a394b EA |
1355 | unsigned long addr; |
1356 | ||
05394f39 | 1357 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1358 | if (obj == NULL) |
bf79cb91 | 1359 | return -ENOENT; |
673a394b | 1360 | |
1286ff73 DV |
1361 | /* prime objects have no backing filp to GEM mmap |
1362 | * pages from. | |
1363 | */ | |
1364 | if (!obj->filp) { | |
1365 | drm_gem_object_unreference_unlocked(obj); | |
1366 | return -EINVAL; | |
1367 | } | |
1368 | ||
6be5ceb0 | 1369 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1370 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1371 | args->offset); | |
bc9025bd | 1372 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1373 | if (IS_ERR((void *)addr)) |
1374 | return addr; | |
1375 | ||
1376 | args->addr_ptr = (uint64_t) addr; | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | ||
de151cf6 JB |
1381 | /** |
1382 | * i915_gem_fault - fault a page into the GTT | |
1383 | * vma: VMA in question | |
1384 | * vmf: fault info | |
1385 | * | |
1386 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1387 | * from userspace. The fault handler takes care of binding the object to | |
1388 | * the GTT (if needed), allocating and programming a fence register (again, | |
1389 | * only if needed based on whether the old reg is still valid or the object | |
1390 | * is tiled) and inserting a new PTE into the faulting process. | |
1391 | * | |
1392 | * Note that the faulting process may involve evicting existing objects | |
1393 | * from the GTT and/or fence registers to make room. So performance may | |
1394 | * suffer if the GTT working set is large or there are few fence registers | |
1395 | * left. | |
1396 | */ | |
1397 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1398 | { | |
05394f39 CW |
1399 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1400 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1401 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1402 | pgoff_t page_offset; |
1403 | unsigned long pfn; | |
1404 | int ret = 0; | |
0f973f27 | 1405 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1406 | |
f65c9168 PZ |
1407 | intel_runtime_pm_get(dev_priv); |
1408 | ||
de151cf6 JB |
1409 | /* We don't use vmf->pgoff since that has the fake offset */ |
1410 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1411 | PAGE_SHIFT; | |
1412 | ||
d9bc7e9f CW |
1413 | ret = i915_mutex_lock_interruptible(dev); |
1414 | if (ret) | |
1415 | goto out; | |
a00b10c3 | 1416 | |
db53a302 CW |
1417 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1418 | ||
6e4930f6 CW |
1419 | /* Try to flush the object off the GPU first without holding the lock. |
1420 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1421 | * repeat the flush holding the lock in the normal manner to catch cases | |
1422 | * where we are gazumped. | |
1423 | */ | |
1424 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1425 | if (ret) | |
1426 | goto unlock; | |
1427 | ||
eb119bd6 CW |
1428 | /* Access to snoopable pages through the GTT is incoherent. */ |
1429 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1430 | ret = -EINVAL; | |
1431 | goto unlock; | |
1432 | } | |
1433 | ||
d9bc7e9f | 1434 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1435 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1436 | if (ret) |
1437 | goto unlock; | |
4a684a41 | 1438 | |
c9839303 CW |
1439 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1440 | if (ret) | |
1441 | goto unpin; | |
74898d7e | 1442 | |
06d98131 | 1443 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1444 | if (ret) |
c9839303 | 1445 | goto unpin; |
7d1c4804 | 1446 | |
6299f992 CW |
1447 | obj->fault_mappable = true; |
1448 | ||
f343c5f6 BW |
1449 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1450 | pfn >>= PAGE_SHIFT; | |
1451 | pfn += page_offset; | |
de151cf6 JB |
1452 | |
1453 | /* Finally, remap it using the new GTT offset */ | |
1454 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 | 1455 | unpin: |
d7f46fc4 | 1456 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1457 | unlock: |
de151cf6 | 1458 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1459 | out: |
de151cf6 | 1460 | switch (ret) { |
d9bc7e9f | 1461 | case -EIO: |
a9340cca DV |
1462 | /* If this -EIO is due to a gpu hang, give the reset code a |
1463 | * chance to clean up the mess. Otherwise return the proper | |
1464 | * SIGBUS. */ | |
f65c9168 PZ |
1465 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
1466 | ret = VM_FAULT_SIGBUS; | |
1467 | break; | |
1468 | } | |
045e769a | 1469 | case -EAGAIN: |
571c608d DV |
1470 | /* |
1471 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1472 | * handler to reset everything when re-faulting in | |
1473 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1474 | */ |
c715089f CW |
1475 | case 0: |
1476 | case -ERESTARTSYS: | |
bed636ab | 1477 | case -EINTR: |
e79e0fe3 DR |
1478 | case -EBUSY: |
1479 | /* | |
1480 | * EBUSY is ok: this just means that another thread | |
1481 | * already did the job. | |
1482 | */ | |
f65c9168 PZ |
1483 | ret = VM_FAULT_NOPAGE; |
1484 | break; | |
de151cf6 | 1485 | case -ENOMEM: |
f65c9168 PZ |
1486 | ret = VM_FAULT_OOM; |
1487 | break; | |
a7c2e1aa | 1488 | case -ENOSPC: |
45d67817 | 1489 | case -EFAULT: |
f65c9168 PZ |
1490 | ret = VM_FAULT_SIGBUS; |
1491 | break; | |
de151cf6 | 1492 | default: |
a7c2e1aa | 1493 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1494 | ret = VM_FAULT_SIGBUS; |
1495 | break; | |
de151cf6 | 1496 | } |
f65c9168 PZ |
1497 | |
1498 | intel_runtime_pm_put(dev_priv); | |
1499 | return ret; | |
de151cf6 JB |
1500 | } |
1501 | ||
48018a57 PZ |
1502 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
1503 | { | |
1504 | struct i915_vma *vma; | |
1505 | ||
1506 | /* | |
1507 | * Only the global gtt is relevant for gtt memory mappings, so restrict | |
1508 | * list traversal to objects bound into the global address space. Note | |
1509 | * that the active list should be empty, but better safe than sorry. | |
1510 | */ | |
1511 | WARN_ON(!list_empty(&dev_priv->gtt.base.active_list)); | |
1512 | list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list) | |
1513 | i915_gem_release_mmap(vma->obj); | |
1514 | list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list) | |
1515 | i915_gem_release_mmap(vma->obj); | |
1516 | } | |
1517 | ||
901782b2 CW |
1518 | /** |
1519 | * i915_gem_release_mmap - remove physical page mappings | |
1520 | * @obj: obj in question | |
1521 | * | |
af901ca1 | 1522 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1523 | * relinquish ownership of the pages back to the system. |
1524 | * | |
1525 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1526 | * object through the GTT and then lose the fence register due to | |
1527 | * resource pressure. Similarly if the object has been moved out of the | |
1528 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1529 | * mapping will then trigger a page fault on the next user access, allowing | |
1530 | * fixup by i915_gem_fault(). | |
1531 | */ | |
d05ca301 | 1532 | void |
05394f39 | 1533 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1534 | { |
6299f992 CW |
1535 | if (!obj->fault_mappable) |
1536 | return; | |
901782b2 | 1537 | |
6796cb16 DH |
1538 | drm_vma_node_unmap(&obj->base.vma_node, |
1539 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1540 | obj->fault_mappable = false; |
901782b2 CW |
1541 | } |
1542 | ||
0fa87796 | 1543 | uint32_t |
e28f8711 | 1544 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1545 | { |
e28f8711 | 1546 | uint32_t gtt_size; |
92b88aeb CW |
1547 | |
1548 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1549 | tiling_mode == I915_TILING_NONE) |
1550 | return size; | |
92b88aeb CW |
1551 | |
1552 | /* Previous chips need a power-of-two fence region when tiling */ | |
1553 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1554 | gtt_size = 1024*1024; |
92b88aeb | 1555 | else |
e28f8711 | 1556 | gtt_size = 512*1024; |
92b88aeb | 1557 | |
e28f8711 CW |
1558 | while (gtt_size < size) |
1559 | gtt_size <<= 1; | |
92b88aeb | 1560 | |
e28f8711 | 1561 | return gtt_size; |
92b88aeb CW |
1562 | } |
1563 | ||
de151cf6 JB |
1564 | /** |
1565 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1566 | * @obj: object to check | |
1567 | * | |
1568 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1569 | * potential fence register mapping. |
de151cf6 | 1570 | */ |
d865110c ID |
1571 | uint32_t |
1572 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1573 | int tiling_mode, bool fenced) | |
de151cf6 | 1574 | { |
de151cf6 JB |
1575 | /* |
1576 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1577 | * if a fence register is needed for the object. | |
1578 | */ | |
d865110c | 1579 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1580 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1581 | return 4096; |
1582 | ||
a00b10c3 CW |
1583 | /* |
1584 | * Previous chips need to be aligned to the size of the smallest | |
1585 | * fence register that can contain the object. | |
1586 | */ | |
e28f8711 | 1587 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1588 | } |
1589 | ||
d8cb5086 CW |
1590 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1591 | { | |
1592 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1593 | int ret; | |
1594 | ||
0de23977 | 1595 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1596 | return 0; |
1597 | ||
da494d7c DV |
1598 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1599 | ||
d8cb5086 CW |
1600 | ret = drm_gem_create_mmap_offset(&obj->base); |
1601 | if (ret != -ENOSPC) | |
da494d7c | 1602 | goto out; |
d8cb5086 CW |
1603 | |
1604 | /* Badly fragmented mmap space? The only way we can recover | |
1605 | * space is by destroying unwanted objects. We can't randomly release | |
1606 | * mmap_offsets as userspace expects them to be persistent for the | |
1607 | * lifetime of the objects. The closest we can is to release the | |
1608 | * offsets on purgeable objects by truncating it and marking it purged, | |
1609 | * which prevents userspace from ever using that object again. | |
1610 | */ | |
1611 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1612 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1613 | if (ret != -ENOSPC) | |
da494d7c | 1614 | goto out; |
d8cb5086 CW |
1615 | |
1616 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1617 | ret = drm_gem_create_mmap_offset(&obj->base); |
1618 | out: | |
1619 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1620 | ||
1621 | return ret; | |
d8cb5086 CW |
1622 | } |
1623 | ||
1624 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1625 | { | |
d8cb5086 CW |
1626 | drm_gem_free_mmap_offset(&obj->base); |
1627 | } | |
1628 | ||
de151cf6 | 1629 | int |
ff72145b DA |
1630 | i915_gem_mmap_gtt(struct drm_file *file, |
1631 | struct drm_device *dev, | |
1632 | uint32_t handle, | |
1633 | uint64_t *offset) | |
de151cf6 | 1634 | { |
da761a6e | 1635 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1636 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1637 | int ret; |
1638 | ||
76c1dec1 | 1639 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1640 | if (ret) |
76c1dec1 | 1641 | return ret; |
de151cf6 | 1642 | |
ff72145b | 1643 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1644 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1645 | ret = -ENOENT; |
1646 | goto unlock; | |
1647 | } | |
de151cf6 | 1648 | |
5d4545ae | 1649 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1650 | ret = -E2BIG; |
ff56b0bc | 1651 | goto out; |
da761a6e CW |
1652 | } |
1653 | ||
05394f39 | 1654 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1655 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1656 | ret = -EFAULT; |
1d7cfea1 | 1657 | goto out; |
ab18282d CW |
1658 | } |
1659 | ||
d8cb5086 CW |
1660 | ret = i915_gem_object_create_mmap_offset(obj); |
1661 | if (ret) | |
1662 | goto out; | |
de151cf6 | 1663 | |
0de23977 | 1664 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1665 | |
1d7cfea1 | 1666 | out: |
05394f39 | 1667 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1668 | unlock: |
de151cf6 | 1669 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1670 | return ret; |
de151cf6 JB |
1671 | } |
1672 | ||
ff72145b DA |
1673 | /** |
1674 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1675 | * @dev: DRM device | |
1676 | * @data: GTT mapping ioctl data | |
1677 | * @file: GEM object info | |
1678 | * | |
1679 | * Simply returns the fake offset to userspace so it can mmap it. | |
1680 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1681 | * up so we can get faults in the handler above. | |
1682 | * | |
1683 | * The fault handler will take care of binding the object into the GTT | |
1684 | * (since it may have been evicted to make room for something), allocating | |
1685 | * a fence register, and mapping the appropriate aperture address into | |
1686 | * userspace. | |
1687 | */ | |
1688 | int | |
1689 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1690 | struct drm_file *file) | |
1691 | { | |
1692 | struct drm_i915_gem_mmap_gtt *args = data; | |
1693 | ||
ff72145b DA |
1694 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1695 | } | |
1696 | ||
5537252b CW |
1697 | static inline int |
1698 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1699 | { | |
1700 | return obj->madv == I915_MADV_DONTNEED; | |
1701 | } | |
1702 | ||
225067ee DV |
1703 | /* Immediately discard the backing storage */ |
1704 | static void | |
1705 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1706 | { |
4d6294bf | 1707 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1708 | |
4d6294bf CW |
1709 | if (obj->base.filp == NULL) |
1710 | return; | |
e5281ccd | 1711 | |
225067ee DV |
1712 | /* Our goal here is to return as much of the memory as |
1713 | * is possible back to the system as we are called from OOM. | |
1714 | * To do this we must instruct the shmfs to drop all of its | |
1715 | * backing pages, *now*. | |
1716 | */ | |
5537252b | 1717 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1718 | obj->madv = __I915_MADV_PURGED; |
1719 | } | |
e5281ccd | 1720 | |
5537252b CW |
1721 | /* Try to discard unwanted pages */ |
1722 | static void | |
1723 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1724 | { |
5537252b CW |
1725 | struct address_space *mapping; |
1726 | ||
1727 | switch (obj->madv) { | |
1728 | case I915_MADV_DONTNEED: | |
1729 | i915_gem_object_truncate(obj); | |
1730 | case __I915_MADV_PURGED: | |
1731 | return; | |
1732 | } | |
1733 | ||
1734 | if (obj->base.filp == NULL) | |
1735 | return; | |
1736 | ||
1737 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1738 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1739 | } |
1740 | ||
5cdf5881 | 1741 | static void |
05394f39 | 1742 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1743 | { |
90797e6d ID |
1744 | struct sg_page_iter sg_iter; |
1745 | int ret; | |
1286ff73 | 1746 | |
05394f39 | 1747 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1748 | |
6c085a72 CW |
1749 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1750 | if (ret) { | |
1751 | /* In the event of a disaster, abandon all caches and | |
1752 | * hope for the best. | |
1753 | */ | |
1754 | WARN_ON(ret != -EIO); | |
2c22569b | 1755 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1756 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1757 | } | |
1758 | ||
6dacfd2f | 1759 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1760 | i915_gem_object_save_bit_17_swizzle(obj); |
1761 | ||
05394f39 CW |
1762 | if (obj->madv == I915_MADV_DONTNEED) |
1763 | obj->dirty = 0; | |
3ef94daa | 1764 | |
90797e6d | 1765 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1766 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1767 | |
05394f39 | 1768 | if (obj->dirty) |
9da3da66 | 1769 | set_page_dirty(page); |
3ef94daa | 1770 | |
05394f39 | 1771 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1772 | mark_page_accessed(page); |
3ef94daa | 1773 | |
9da3da66 | 1774 | page_cache_release(page); |
3ef94daa | 1775 | } |
05394f39 | 1776 | obj->dirty = 0; |
673a394b | 1777 | |
9da3da66 CW |
1778 | sg_free_table(obj->pages); |
1779 | kfree(obj->pages); | |
37e680a1 | 1780 | } |
6c085a72 | 1781 | |
dd624afd | 1782 | int |
37e680a1 CW |
1783 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1784 | { | |
1785 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1786 | ||
2f745ad3 | 1787 | if (obj->pages == NULL) |
37e680a1 CW |
1788 | return 0; |
1789 | ||
a5570178 CW |
1790 | if (obj->pages_pin_count) |
1791 | return -EBUSY; | |
1792 | ||
9843877d | 1793 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1794 | |
a2165e31 CW |
1795 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1796 | * array, hence protect them from being reaped by removing them from gtt | |
1797 | * lists early. */ | |
35c20a60 | 1798 | list_del(&obj->global_list); |
a2165e31 | 1799 | |
37e680a1 | 1800 | ops->put_pages(obj); |
05394f39 | 1801 | obj->pages = NULL; |
37e680a1 | 1802 | |
5537252b | 1803 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
1804 | |
1805 | return 0; | |
1806 | } | |
1807 | ||
d9973b43 | 1808 | static unsigned long |
93927ca5 DV |
1809 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1810 | bool purgeable_only) | |
6c085a72 | 1811 | { |
c8725f3d CW |
1812 | struct list_head still_in_list; |
1813 | struct drm_i915_gem_object *obj; | |
d9973b43 | 1814 | unsigned long count = 0; |
6c085a72 | 1815 | |
57094f82 | 1816 | /* |
c8725f3d | 1817 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
1818 | * (due to retiring requests) we have to strictly process only |
1819 | * one element of the list at the time, and recheck the list | |
1820 | * on every iteration. | |
c8725f3d CW |
1821 | * |
1822 | * In particular, we must hold a reference whilst removing the | |
1823 | * object as we may end up waiting for and/or retiring the objects. | |
1824 | * This might release the final reference (held by the active list) | |
1825 | * and result in the object being freed from under us. This is | |
1826 | * similar to the precautions the eviction code must take whilst | |
1827 | * removing objects. | |
1828 | * | |
1829 | * Also note that although these lists do not hold a reference to | |
1830 | * the object we can safely grab one here: The final object | |
1831 | * unreferencing and the bound_list are both protected by the | |
1832 | * dev->struct_mutex and so we won't ever be able to observe an | |
1833 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 1834 | */ |
c8725f3d CW |
1835 | INIT_LIST_HEAD(&still_in_list); |
1836 | while (count < target && !list_empty(&dev_priv->mm.unbound_list)) { | |
1837 | obj = list_first_entry(&dev_priv->mm.unbound_list, | |
1838 | typeof(*obj), global_list); | |
1839 | list_move_tail(&obj->global_list, &still_in_list); | |
1840 | ||
1841 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) | |
1842 | continue; | |
1843 | ||
1844 | drm_gem_object_reference(&obj->base); | |
1845 | ||
1846 | if (i915_gem_object_put_pages(obj) == 0) | |
1847 | count += obj->base.size >> PAGE_SHIFT; | |
1848 | ||
1849 | drm_gem_object_unreference(&obj->base); | |
1850 | } | |
1851 | list_splice(&still_in_list, &dev_priv->mm.unbound_list); | |
1852 | ||
1853 | INIT_LIST_HEAD(&still_in_list); | |
57094f82 | 1854 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { |
07fe0b12 | 1855 | struct i915_vma *vma, *v; |
80dcfdbd | 1856 | |
57094f82 CW |
1857 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1858 | typeof(*obj), global_list); | |
c8725f3d | 1859 | list_move_tail(&obj->global_list, &still_in_list); |
57094f82 | 1860 | |
80dcfdbd BW |
1861 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1862 | continue; | |
1863 | ||
57094f82 CW |
1864 | drm_gem_object_reference(&obj->base); |
1865 | ||
07fe0b12 BW |
1866 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1867 | if (i915_vma_unbind(vma)) | |
1868 | break; | |
80dcfdbd | 1869 | |
57094f82 | 1870 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1871 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1872 | |
1873 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1874 | } |
c8725f3d | 1875 | list_splice(&still_in_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1876 | |
1877 | return count; | |
1878 | } | |
1879 | ||
d9973b43 | 1880 | static unsigned long |
93927ca5 DV |
1881 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
1882 | { | |
1883 | return __i915_gem_shrink(dev_priv, target, true); | |
1884 | } | |
1885 | ||
d9973b43 | 1886 | static unsigned long |
6c085a72 CW |
1887 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
1888 | { | |
6c085a72 | 1889 | i915_gem_evict_everything(dev_priv->dev); |
c8725f3d | 1890 | return __i915_gem_shrink(dev_priv, LONG_MAX, false); |
225067ee DV |
1891 | } |
1892 | ||
37e680a1 | 1893 | static int |
6c085a72 | 1894 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1895 | { |
6c085a72 | 1896 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1897 | int page_count, i; |
1898 | struct address_space *mapping; | |
9da3da66 CW |
1899 | struct sg_table *st; |
1900 | struct scatterlist *sg; | |
90797e6d | 1901 | struct sg_page_iter sg_iter; |
e5281ccd | 1902 | struct page *page; |
90797e6d | 1903 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1904 | gfp_t gfp; |
e5281ccd | 1905 | |
6c085a72 CW |
1906 | /* Assert that the object is not currently in any GPU domain. As it |
1907 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1908 | * a GPU cache | |
1909 | */ | |
1910 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1911 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1912 | ||
9da3da66 CW |
1913 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1914 | if (st == NULL) | |
1915 | return -ENOMEM; | |
1916 | ||
05394f39 | 1917 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1918 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 1919 | kfree(st); |
e5281ccd | 1920 | return -ENOMEM; |
9da3da66 | 1921 | } |
e5281ccd | 1922 | |
9da3da66 CW |
1923 | /* Get the list of pages out of our struct file. They'll be pinned |
1924 | * at this point until we release them. | |
1925 | * | |
1926 | * Fail silently without starting the shrinker | |
1927 | */ | |
496ad9aa | 1928 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1929 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1930 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1931 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1932 | sg = st->sgl; |
1933 | st->nents = 0; | |
1934 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1935 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1936 | if (IS_ERR(page)) { | |
1937 | i915_gem_purge(dev_priv, page_count); | |
1938 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1939 | } | |
1940 | if (IS_ERR(page)) { | |
1941 | /* We've tried hard to allocate the memory by reaping | |
1942 | * our own buffer, now let the real VM do its job and | |
1943 | * go down in flames if truly OOM. | |
1944 | */ | |
caf49191 | 1945 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1946 | gfp |= __GFP_IO | __GFP_WAIT; |
1947 | ||
1948 | i915_gem_shrink_all(dev_priv); | |
1949 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1950 | if (IS_ERR(page)) | |
1951 | goto err_pages; | |
1952 | ||
caf49191 | 1953 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1954 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1955 | } | |
426729dc KRW |
1956 | #ifdef CONFIG_SWIOTLB |
1957 | if (swiotlb_nr_tbl()) { | |
1958 | st->nents++; | |
1959 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1960 | sg = sg_next(sg); | |
1961 | continue; | |
1962 | } | |
1963 | #endif | |
90797e6d ID |
1964 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1965 | if (i) | |
1966 | sg = sg_next(sg); | |
1967 | st->nents++; | |
1968 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1969 | } else { | |
1970 | sg->length += PAGE_SIZE; | |
1971 | } | |
1972 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
1973 | |
1974 | /* Check that the i965g/gm workaround works. */ | |
1975 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 1976 | } |
426729dc KRW |
1977 | #ifdef CONFIG_SWIOTLB |
1978 | if (!swiotlb_nr_tbl()) | |
1979 | #endif | |
1980 | sg_mark_end(sg); | |
74ce6b6c CW |
1981 | obj->pages = st; |
1982 | ||
6dacfd2f | 1983 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1984 | i915_gem_object_do_bit_17_swizzle(obj); |
1985 | ||
1986 | return 0; | |
1987 | ||
1988 | err_pages: | |
90797e6d ID |
1989 | sg_mark_end(sg); |
1990 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1991 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1992 | sg_free_table(st); |
1993 | kfree(st); | |
0820baf3 CW |
1994 | |
1995 | /* shmemfs first checks if there is enough memory to allocate the page | |
1996 | * and reports ENOSPC should there be insufficient, along with the usual | |
1997 | * ENOMEM for a genuine allocation failure. | |
1998 | * | |
1999 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2000 | * space and so want to translate the error from shmemfs back to our | |
2001 | * usual understanding of ENOMEM. | |
2002 | */ | |
2003 | if (PTR_ERR(page) == -ENOSPC) | |
2004 | return -ENOMEM; | |
2005 | else | |
2006 | return PTR_ERR(page); | |
673a394b EA |
2007 | } |
2008 | ||
37e680a1 CW |
2009 | /* Ensure that the associated pages are gathered from the backing storage |
2010 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2011 | * multiple times before they are released by a single call to | |
2012 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2013 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2014 | * or as the object is itself released. | |
2015 | */ | |
2016 | int | |
2017 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2018 | { | |
2019 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2020 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2021 | int ret; | |
2022 | ||
2f745ad3 | 2023 | if (obj->pages) |
37e680a1 CW |
2024 | return 0; |
2025 | ||
43e28f09 | 2026 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2027 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2028 | return -EFAULT; |
43e28f09 CW |
2029 | } |
2030 | ||
a5570178 CW |
2031 | BUG_ON(obj->pages_pin_count); |
2032 | ||
37e680a1 CW |
2033 | ret = ops->get_pages(obj); |
2034 | if (ret) | |
2035 | return ret; | |
2036 | ||
35c20a60 | 2037 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2038 | return 0; |
673a394b EA |
2039 | } |
2040 | ||
e2d05a8b | 2041 | static void |
05394f39 | 2042 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2043 | struct intel_engine_cs *ring) |
673a394b | 2044 | { |
05394f39 | 2045 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 2046 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 2047 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 2048 | |
852835f3 | 2049 | BUG_ON(ring == NULL); |
02978ff5 CW |
2050 | if (obj->ring != ring && obj->last_write_seqno) { |
2051 | /* Keep the seqno relative to the current ring */ | |
2052 | obj->last_write_seqno = seqno; | |
2053 | } | |
05394f39 | 2054 | obj->ring = ring; |
673a394b EA |
2055 | |
2056 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2057 | if (!obj->active) { |
2058 | drm_gem_object_reference(&obj->base); | |
2059 | obj->active = 1; | |
673a394b | 2060 | } |
e35a41de | 2061 | |
05394f39 | 2062 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2063 | |
0201f1ec | 2064 | obj->last_read_seqno = seqno; |
caea7476 | 2065 | |
7dd49065 | 2066 | if (obj->fenced_gpu_access) { |
caea7476 | 2067 | obj->last_fenced_seqno = seqno; |
caea7476 | 2068 | |
7dd49065 CW |
2069 | /* Bump MRU to take account of the delayed flush */ |
2070 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2071 | struct drm_i915_fence_reg *reg; | |
2072 | ||
2073 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
2074 | list_move_tail(®->lru_list, | |
2075 | &dev_priv->mm.fence_list); | |
2076 | } | |
caea7476 CW |
2077 | } |
2078 | } | |
2079 | ||
e2d05a8b | 2080 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2081 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2082 | { |
2083 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2084 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2085 | } | |
2086 | ||
caea7476 | 2087 | static void |
caea7476 | 2088 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2089 | { |
ca191b13 | 2090 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2091 | struct i915_address_space *vm; |
2092 | struct i915_vma *vma; | |
ce44b0ea | 2093 | |
65ce3027 | 2094 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2095 | BUG_ON(!obj->active); |
caea7476 | 2096 | |
feb822cf BW |
2097 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2098 | vma = i915_gem_obj_to_vma(obj, vm); | |
2099 | if (vma && !list_empty(&vma->mm_list)) | |
2100 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2101 | } | |
caea7476 | 2102 | |
65ce3027 | 2103 | list_del_init(&obj->ring_list); |
caea7476 CW |
2104 | obj->ring = NULL; |
2105 | ||
65ce3027 CW |
2106 | obj->last_read_seqno = 0; |
2107 | obj->last_write_seqno = 0; | |
2108 | obj->base.write_domain = 0; | |
2109 | ||
2110 | obj->last_fenced_seqno = 0; | |
caea7476 | 2111 | obj->fenced_gpu_access = false; |
caea7476 CW |
2112 | |
2113 | obj->active = 0; | |
2114 | drm_gem_object_unreference(&obj->base); | |
2115 | ||
2116 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2117 | } |
673a394b | 2118 | |
c8725f3d CW |
2119 | static void |
2120 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2121 | { | |
a4872ba6 | 2122 | struct intel_engine_cs *ring = obj->ring; |
c8725f3d CW |
2123 | |
2124 | if (ring == NULL) | |
2125 | return; | |
2126 | ||
2127 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
2128 | obj->last_read_seqno)) | |
2129 | i915_gem_object_move_to_inactive(obj); | |
2130 | } | |
2131 | ||
9d773091 | 2132 | static int |
fca26bb4 | 2133 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2134 | { |
9d773091 | 2135 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2136 | struct intel_engine_cs *ring; |
9d773091 | 2137 | int ret, i, j; |
53d227f2 | 2138 | |
107f27a5 | 2139 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2140 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2141 | ret = intel_ring_idle(ring); |
2142 | if (ret) | |
2143 | return ret; | |
9d773091 | 2144 | } |
9d773091 | 2145 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2146 | |
2147 | /* Finally reset hw state */ | |
9d773091 | 2148 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2149 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2150 | |
ebc348b2 BW |
2151 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2152 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2153 | } |
53d227f2 | 2154 | |
9d773091 | 2155 | return 0; |
53d227f2 DV |
2156 | } |
2157 | ||
fca26bb4 MK |
2158 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2159 | { | |
2160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2161 | int ret; | |
2162 | ||
2163 | if (seqno == 0) | |
2164 | return -EINVAL; | |
2165 | ||
2166 | /* HWS page needs to be set less than what we | |
2167 | * will inject to ring | |
2168 | */ | |
2169 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2170 | if (ret) | |
2171 | return ret; | |
2172 | ||
2173 | /* Carefully set the last_seqno value so that wrap | |
2174 | * detection still works | |
2175 | */ | |
2176 | dev_priv->next_seqno = seqno; | |
2177 | dev_priv->last_seqno = seqno - 1; | |
2178 | if (dev_priv->last_seqno == 0) | |
2179 | dev_priv->last_seqno--; | |
2180 | ||
2181 | return 0; | |
2182 | } | |
2183 | ||
9d773091 CW |
2184 | int |
2185 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2186 | { |
9d773091 CW |
2187 | struct drm_i915_private *dev_priv = dev->dev_private; |
2188 | ||
2189 | /* reserve 0 for non-seqno */ | |
2190 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2191 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2192 | if (ret) |
2193 | return ret; | |
53d227f2 | 2194 | |
9d773091 CW |
2195 | dev_priv->next_seqno = 1; |
2196 | } | |
53d227f2 | 2197 | |
f72b3435 | 2198 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2199 | return 0; |
53d227f2 DV |
2200 | } |
2201 | ||
a4872ba6 | 2202 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2203 | struct drm_file *file, |
7d736f4f | 2204 | struct drm_i915_gem_object *obj, |
0025c077 | 2205 | u32 *out_seqno) |
673a394b | 2206 | { |
3e31c6c0 | 2207 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2208 | struct drm_i915_gem_request *request; |
7d736f4f | 2209 | u32 request_ring_position, request_start; |
3cce469c CW |
2210 | int ret; |
2211 | ||
7d736f4f | 2212 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2213 | /* |
2214 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2215 | * after having emitted the batchbuffer command. Hence we need to fix | |
2216 | * things up similar to emitting the lazy request. The difference here | |
2217 | * is that the flush _must_ happen before the next request, no matter | |
2218 | * what. | |
2219 | */ | |
a7b9761d CW |
2220 | ret = intel_ring_flush_all_caches(ring); |
2221 | if (ret) | |
2222 | return ret; | |
cc889e0f | 2223 | |
3c0e234c CW |
2224 | request = ring->preallocated_lazy_request; |
2225 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2226 | return -ENOMEM; |
cc889e0f | 2227 | |
a71d8d94 CW |
2228 | /* Record the position of the start of the request so that |
2229 | * should we detect the updated seqno part-way through the | |
2230 | * GPU processing the request, we never over-estimate the | |
2231 | * position of the head. | |
2232 | */ | |
2233 | request_ring_position = intel_ring_get_tail(ring); | |
2234 | ||
9d773091 | 2235 | ret = ring->add_request(ring); |
3c0e234c | 2236 | if (ret) |
3bb73aba | 2237 | return ret; |
673a394b | 2238 | |
9d773091 | 2239 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2240 | request->ring = ring; |
7d736f4f | 2241 | request->head = request_start; |
a71d8d94 | 2242 | request->tail = request_ring_position; |
7d736f4f MK |
2243 | |
2244 | /* Whilst this request exists, batch_obj will be on the | |
2245 | * active_list, and so will hold the active reference. Only when this | |
2246 | * request is retired will the the batch_obj be moved onto the | |
2247 | * inactive_list and lose its active reference. Hence we do not need | |
2248 | * to explicitly hold another reference here. | |
2249 | */ | |
9a7e0c2a | 2250 | request->batch_obj = obj; |
0e50e96b | 2251 | |
9a7e0c2a CW |
2252 | /* Hold a reference to the current context so that we can inspect |
2253 | * it later in case a hangcheck error event fires. | |
2254 | */ | |
2255 | request->ctx = ring->last_context; | |
0e50e96b MK |
2256 | if (request->ctx) |
2257 | i915_gem_context_reference(request->ctx); | |
2258 | ||
673a394b | 2259 | request->emitted_jiffies = jiffies; |
852835f3 | 2260 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2261 | request->file_priv = NULL; |
852835f3 | 2262 | |
db53a302 CW |
2263 | if (file) { |
2264 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2265 | ||
1c25595f | 2266 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2267 | request->file_priv = file_priv; |
b962442e | 2268 | list_add_tail(&request->client_list, |
f787a5f5 | 2269 | &file_priv->mm.request_list); |
1c25595f | 2270 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2271 | } |
673a394b | 2272 | |
9d773091 | 2273 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2274 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2275 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2276 | |
db1b76ca | 2277 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2278 | i915_queue_hangcheck(ring->dev); |
2279 | ||
f62a0076 CW |
2280 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2281 | queue_delayed_work(dev_priv->wq, | |
2282 | &dev_priv->mm.retire_work, | |
2283 | round_jiffies_up_relative(HZ)); | |
2284 | intel_mark_busy(dev_priv->dev); | |
f65d9421 | 2285 | } |
cc889e0f | 2286 | |
acb868d3 | 2287 | if (out_seqno) |
9d773091 | 2288 | *out_seqno = request->seqno; |
3cce469c | 2289 | return 0; |
673a394b EA |
2290 | } |
2291 | ||
f787a5f5 CW |
2292 | static inline void |
2293 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2294 | { |
1c25595f | 2295 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2296 | |
1c25595f CW |
2297 | if (!file_priv) |
2298 | return; | |
1c5d22f7 | 2299 | |
1c25595f | 2300 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2301 | list_del(&request->client_list); |
2302 | request->file_priv = NULL; | |
1c25595f | 2303 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2304 | } |
673a394b | 2305 | |
939fd762 | 2306 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2307 | const struct intel_context *ctx) |
be62acb4 | 2308 | { |
44e2c070 | 2309 | unsigned long elapsed; |
be62acb4 | 2310 | |
44e2c070 MK |
2311 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2312 | ||
2313 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2314 | return true; |
2315 | ||
2316 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2317 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2318 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2319 | return true; |
88b4aa87 MK |
2320 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2321 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2322 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2323 | return true; |
3fac8978 | 2324 | } |
be62acb4 MK |
2325 | } |
2326 | ||
2327 | return false; | |
2328 | } | |
2329 | ||
939fd762 | 2330 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2331 | struct intel_context *ctx, |
b6b0fac0 | 2332 | const bool guilty) |
aa60c664 | 2333 | { |
44e2c070 MK |
2334 | struct i915_ctx_hang_stats *hs; |
2335 | ||
2336 | if (WARN_ON(!ctx)) | |
2337 | return; | |
aa60c664 | 2338 | |
44e2c070 MK |
2339 | hs = &ctx->hang_stats; |
2340 | ||
2341 | if (guilty) { | |
939fd762 | 2342 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2343 | hs->batch_active++; |
2344 | hs->guilty_ts = get_seconds(); | |
2345 | } else { | |
2346 | hs->batch_pending++; | |
aa60c664 MK |
2347 | } |
2348 | } | |
2349 | ||
0e50e96b MK |
2350 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2351 | { | |
2352 | list_del(&request->list); | |
2353 | i915_gem_request_remove_from_client(request); | |
2354 | ||
2355 | if (request->ctx) | |
2356 | i915_gem_context_unreference(request->ctx); | |
2357 | ||
2358 | kfree(request); | |
2359 | } | |
2360 | ||
8d9fc7fd | 2361 | struct drm_i915_gem_request * |
a4872ba6 | 2362 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2363 | { |
4db080f9 | 2364 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2365 | u32 completed_seqno; |
2366 | ||
2367 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2368 | |
2369 | list_for_each_entry(request, &ring->request_list, list) { | |
2370 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2371 | continue; | |
aa60c664 | 2372 | |
b6b0fac0 | 2373 | return request; |
4db080f9 | 2374 | } |
b6b0fac0 MK |
2375 | |
2376 | return NULL; | |
2377 | } | |
2378 | ||
2379 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2380 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2381 | { |
2382 | struct drm_i915_gem_request *request; | |
2383 | bool ring_hung; | |
2384 | ||
8d9fc7fd | 2385 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2386 | |
2387 | if (request == NULL) | |
2388 | return; | |
2389 | ||
2390 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2391 | ||
939fd762 | 2392 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2393 | |
2394 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2395 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2396 | } |
aa60c664 | 2397 | |
4db080f9 | 2398 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2399 | struct intel_engine_cs *ring) |
4db080f9 | 2400 | { |
dfaae392 | 2401 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2402 | struct drm_i915_gem_object *obj; |
9375e446 | 2403 | |
05394f39 CW |
2404 | obj = list_first_entry(&ring->active_list, |
2405 | struct drm_i915_gem_object, | |
2406 | ring_list); | |
9375e446 | 2407 | |
05394f39 | 2408 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2409 | } |
1d62beea BW |
2410 | |
2411 | /* | |
2412 | * We must free the requests after all the corresponding objects have | |
2413 | * been moved off active lists. Which is the same order as the normal | |
2414 | * retire_requests function does. This is important if object hold | |
2415 | * implicit references on things like e.g. ppgtt address spaces through | |
2416 | * the request. | |
2417 | */ | |
2418 | while (!list_empty(&ring->request_list)) { | |
2419 | struct drm_i915_gem_request *request; | |
2420 | ||
2421 | request = list_first_entry(&ring->request_list, | |
2422 | struct drm_i915_gem_request, | |
2423 | list); | |
2424 | ||
2425 | i915_gem_free_request(request); | |
2426 | } | |
e3efda49 CW |
2427 | |
2428 | /* These may not have been flush before the reset, do so now */ | |
2429 | kfree(ring->preallocated_lazy_request); | |
2430 | ring->preallocated_lazy_request = NULL; | |
2431 | ring->outstanding_lazy_seqno = 0; | |
673a394b EA |
2432 | } |
2433 | ||
19b2dbde | 2434 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2435 | { |
2436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2437 | int i; | |
2438 | ||
4b9de737 | 2439 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2440 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2441 | |
94a335db DV |
2442 | /* |
2443 | * Commit delayed tiling changes if we have an object still | |
2444 | * attached to the fence, otherwise just clear the fence. | |
2445 | */ | |
2446 | if (reg->obj) { | |
2447 | i915_gem_object_update_fence(reg->obj, reg, | |
2448 | reg->obj->tiling_mode); | |
2449 | } else { | |
2450 | i915_gem_write_fence(dev, i, NULL); | |
2451 | } | |
312817a3 CW |
2452 | } |
2453 | } | |
2454 | ||
069efc1d | 2455 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2456 | { |
77f01230 | 2457 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2458 | struct intel_engine_cs *ring; |
1ec14ad3 | 2459 | int i; |
673a394b | 2460 | |
4db080f9 CW |
2461 | /* |
2462 | * Before we free the objects from the requests, we need to inspect | |
2463 | * them for finding the guilty party. As the requests only borrow | |
2464 | * their reference to the objects, the inspection must be done first. | |
2465 | */ | |
2466 | for_each_ring(ring, dev_priv, i) | |
2467 | i915_gem_reset_ring_status(dev_priv, ring); | |
2468 | ||
b4519513 | 2469 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2470 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2471 | |
acce9ffa BW |
2472 | i915_gem_context_reset(dev); |
2473 | ||
19b2dbde | 2474 | i915_gem_restore_fences(dev); |
673a394b EA |
2475 | } |
2476 | ||
2477 | /** | |
2478 | * This function clears the request list as sequence numbers are passed. | |
2479 | */ | |
1cf0ba14 | 2480 | void |
a4872ba6 | 2481 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2482 | { |
673a394b EA |
2483 | uint32_t seqno; |
2484 | ||
db53a302 | 2485 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2486 | return; |
2487 | ||
db53a302 | 2488 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2489 | |
b2eadbc8 | 2490 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2491 | |
e9103038 CW |
2492 | /* Move any buffers on the active list that are no longer referenced |
2493 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2494 | * before we free the context associated with the requests. | |
2495 | */ | |
2496 | while (!list_empty(&ring->active_list)) { | |
2497 | struct drm_i915_gem_object *obj; | |
2498 | ||
2499 | obj = list_first_entry(&ring->active_list, | |
2500 | struct drm_i915_gem_object, | |
2501 | ring_list); | |
2502 | ||
2503 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) | |
2504 | break; | |
2505 | ||
2506 | i915_gem_object_move_to_inactive(obj); | |
2507 | } | |
2508 | ||
2509 | ||
852835f3 | 2510 | while (!list_empty(&ring->request_list)) { |
673a394b | 2511 | struct drm_i915_gem_request *request; |
673a394b | 2512 | |
852835f3 | 2513 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2514 | struct drm_i915_gem_request, |
2515 | list); | |
673a394b | 2516 | |
dfaae392 | 2517 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2518 | break; |
2519 | ||
db53a302 | 2520 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2521 | /* We know the GPU must have read the request to have |
2522 | * sent us the seqno + interrupt, so use the position | |
2523 | * of tail of the request to update the last known position | |
2524 | * of the GPU head. | |
2525 | */ | |
ee1b1e5e | 2526 | ring->buffer->last_retired_head = request->tail; |
b84d5f0c | 2527 | |
0e50e96b | 2528 | i915_gem_free_request(request); |
b84d5f0c | 2529 | } |
673a394b | 2530 | |
db53a302 CW |
2531 | if (unlikely(ring->trace_irq_seqno && |
2532 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2533 | ring->irq_put(ring); |
db53a302 | 2534 | ring->trace_irq_seqno = 0; |
9d34e5db | 2535 | } |
23bc5982 | 2536 | |
db53a302 | 2537 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2538 | } |
2539 | ||
b29c19b6 | 2540 | bool |
b09a1fec CW |
2541 | i915_gem_retire_requests(struct drm_device *dev) |
2542 | { | |
3e31c6c0 | 2543 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2544 | struct intel_engine_cs *ring; |
b29c19b6 | 2545 | bool idle = true; |
1ec14ad3 | 2546 | int i; |
b09a1fec | 2547 | |
b29c19b6 | 2548 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2549 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2550 | idle &= list_empty(&ring->request_list); |
2551 | } | |
2552 | ||
2553 | if (idle) | |
2554 | mod_delayed_work(dev_priv->wq, | |
2555 | &dev_priv->mm.idle_work, | |
2556 | msecs_to_jiffies(100)); | |
2557 | ||
2558 | return idle; | |
b09a1fec CW |
2559 | } |
2560 | ||
75ef9da2 | 2561 | static void |
673a394b EA |
2562 | i915_gem_retire_work_handler(struct work_struct *work) |
2563 | { | |
b29c19b6 CW |
2564 | struct drm_i915_private *dev_priv = |
2565 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2566 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2567 | bool idle; |
673a394b | 2568 | |
891b48cf | 2569 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2570 | idle = false; |
2571 | if (mutex_trylock(&dev->struct_mutex)) { | |
2572 | idle = i915_gem_retire_requests(dev); | |
2573 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2574 | } |
b29c19b6 | 2575 | if (!idle) |
bcb45086 CW |
2576 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2577 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2578 | } |
0a58705b | 2579 | |
b29c19b6 CW |
2580 | static void |
2581 | i915_gem_idle_work_handler(struct work_struct *work) | |
2582 | { | |
2583 | struct drm_i915_private *dev_priv = | |
2584 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2585 | ||
2586 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2587 | } |
2588 | ||
30dfebf3 DV |
2589 | /** |
2590 | * Ensures that an object will eventually get non-busy by flushing any required | |
2591 | * write domains, emitting any outstanding lazy request and retiring and | |
2592 | * completed requests. | |
2593 | */ | |
2594 | static int | |
2595 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2596 | { | |
2597 | int ret; | |
2598 | ||
2599 | if (obj->active) { | |
0201f1ec | 2600 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2601 | if (ret) |
2602 | return ret; | |
2603 | ||
30dfebf3 DV |
2604 | i915_gem_retire_requests_ring(obj->ring); |
2605 | } | |
2606 | ||
2607 | return 0; | |
2608 | } | |
2609 | ||
23ba4fd0 BW |
2610 | /** |
2611 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2612 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2613 | * | |
2614 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2615 | * the timeout parameter. | |
2616 | * -ETIME: object is still busy after timeout | |
2617 | * -ERESTARTSYS: signal interrupted the wait | |
2618 | * -ENONENT: object doesn't exist | |
2619 | * Also possible, but rare: | |
2620 | * -EAGAIN: GPU wedged | |
2621 | * -ENOMEM: damn | |
2622 | * -ENODEV: Internal IRQ fail | |
2623 | * -E?: The add request failed | |
2624 | * | |
2625 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2626 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2627 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2628 | * without holding struct_mutex the object may become re-busied before this | |
2629 | * function completes. A similar but shorter * race condition exists in the busy | |
2630 | * ioctl | |
2631 | */ | |
2632 | int | |
2633 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2634 | { | |
3e31c6c0 | 2635 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2636 | struct drm_i915_gem_wait *args = data; |
2637 | struct drm_i915_gem_object *obj; | |
a4872ba6 | 2638 | struct intel_engine_cs *ring = NULL; |
eac1f14f | 2639 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2640 | unsigned reset_counter; |
23ba4fd0 BW |
2641 | u32 seqno = 0; |
2642 | int ret = 0; | |
2643 | ||
eac1f14f BW |
2644 | if (args->timeout_ns >= 0) { |
2645 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2646 | timeout = &timeout_stack; | |
2647 | } | |
23ba4fd0 BW |
2648 | |
2649 | ret = i915_mutex_lock_interruptible(dev); | |
2650 | if (ret) | |
2651 | return ret; | |
2652 | ||
2653 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2654 | if (&obj->base == NULL) { | |
2655 | mutex_unlock(&dev->struct_mutex); | |
2656 | return -ENOENT; | |
2657 | } | |
2658 | ||
30dfebf3 DV |
2659 | /* Need to make sure the object gets inactive eventually. */ |
2660 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2661 | if (ret) |
2662 | goto out; | |
2663 | ||
2664 | if (obj->active) { | |
0201f1ec | 2665 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2666 | ring = obj->ring; |
2667 | } | |
2668 | ||
2669 | if (seqno == 0) | |
2670 | goto out; | |
2671 | ||
23ba4fd0 BW |
2672 | /* Do this after OLR check to make sure we make forward progress polling |
2673 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2674 | */ | |
2675 | if (!args->timeout_ns) { | |
2676 | ret = -ETIME; | |
2677 | goto out; | |
2678 | } | |
2679 | ||
2680 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2681 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2682 | mutex_unlock(&dev->struct_mutex); |
2683 | ||
b29c19b6 | 2684 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2685 | if (timeout) |
eac1f14f | 2686 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2687 | return ret; |
2688 | ||
2689 | out: | |
2690 | drm_gem_object_unreference(&obj->base); | |
2691 | mutex_unlock(&dev->struct_mutex); | |
2692 | return ret; | |
2693 | } | |
2694 | ||
5816d648 BW |
2695 | /** |
2696 | * i915_gem_object_sync - sync an object to a ring. | |
2697 | * | |
2698 | * @obj: object which may be in use on another ring. | |
2699 | * @to: ring we wish to use the object on. May be NULL. | |
2700 | * | |
2701 | * This code is meant to abstract object synchronization with the GPU. | |
2702 | * Calling with NULL implies synchronizing the object with the CPU | |
2703 | * rather than a particular GPU ring. | |
2704 | * | |
2705 | * Returns 0 if successful, else propagates up the lower layer error. | |
2706 | */ | |
2911a35b BW |
2707 | int |
2708 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2709 | struct intel_engine_cs *to) |
2911a35b | 2710 | { |
a4872ba6 | 2711 | struct intel_engine_cs *from = obj->ring; |
2911a35b BW |
2712 | u32 seqno; |
2713 | int ret, idx; | |
2714 | ||
2715 | if (from == NULL || to == from) | |
2716 | return 0; | |
2717 | ||
5816d648 | 2718 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2719 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2720 | |
2721 | idx = intel_ring_sync_index(from, to); | |
2722 | ||
0201f1ec | 2723 | seqno = obj->last_read_seqno; |
ebc348b2 | 2724 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2725 | return 0; |
2726 | ||
b4aca010 BW |
2727 | ret = i915_gem_check_olr(obj->ring, seqno); |
2728 | if (ret) | |
2729 | return ret; | |
2911a35b | 2730 | |
b52b89da | 2731 | trace_i915_gem_ring_sync_to(from, to, seqno); |
ebc348b2 | 2732 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 2733 | if (!ret) |
7b01e260 MK |
2734 | /* We use last_read_seqno because sync_to() |
2735 | * might have just caused seqno wrap under | |
2736 | * the radar. | |
2737 | */ | |
ebc348b2 | 2738 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
2911a35b | 2739 | |
e3a5a225 | 2740 | return ret; |
2911a35b BW |
2741 | } |
2742 | ||
b5ffc9bc CW |
2743 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2744 | { | |
2745 | u32 old_write_domain, old_read_domains; | |
2746 | ||
b5ffc9bc CW |
2747 | /* Force a pagefault for domain tracking on next user access */ |
2748 | i915_gem_release_mmap(obj); | |
2749 | ||
b97c3d9c KP |
2750 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2751 | return; | |
2752 | ||
97c809fd CW |
2753 | /* Wait for any direct GTT access to complete */ |
2754 | mb(); | |
2755 | ||
b5ffc9bc CW |
2756 | old_read_domains = obj->base.read_domains; |
2757 | old_write_domain = obj->base.write_domain; | |
2758 | ||
2759 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2760 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2761 | ||
2762 | trace_i915_gem_object_change_domain(obj, | |
2763 | old_read_domains, | |
2764 | old_write_domain); | |
2765 | } | |
2766 | ||
07fe0b12 | 2767 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2768 | { |
07fe0b12 | 2769 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 2770 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2771 | int ret; |
673a394b | 2772 | |
07fe0b12 | 2773 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2774 | return 0; |
2775 | ||
0ff501cb DV |
2776 | if (!drm_mm_node_allocated(&vma->node)) { |
2777 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
2778 | return 0; |
2779 | } | |
433544bd | 2780 | |
d7f46fc4 | 2781 | if (vma->pin_count) |
31d8d651 | 2782 | return -EBUSY; |
673a394b | 2783 | |
c4670ad0 CW |
2784 | BUG_ON(obj->pages == NULL); |
2785 | ||
a8198eea | 2786 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2787 | if (ret) |
a8198eea CW |
2788 | return ret; |
2789 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2790 | * should be safe and we need to cleanup or else we might | |
2791 | * cause memory corruption through use-after-free. | |
2792 | */ | |
2793 | ||
8b1bc9b4 DV |
2794 | if (i915_is_ggtt(vma->vm)) { |
2795 | i915_gem_object_finish_gtt(obj); | |
5323fd04 | 2796 | |
8b1bc9b4 DV |
2797 | /* release the fence reg _after_ flushing */ |
2798 | ret = i915_gem_object_put_fence(obj); | |
2799 | if (ret) | |
2800 | return ret; | |
2801 | } | |
96b47b65 | 2802 | |
07fe0b12 | 2803 | trace_i915_vma_unbind(vma); |
db53a302 | 2804 | |
6f65e29a BW |
2805 | vma->unbind_vma(vma); |
2806 | ||
74163907 | 2807 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2808 | |
64bf9303 | 2809 | list_del_init(&vma->mm_list); |
75e9e915 | 2810 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2811 | if (i915_is_ggtt(vma->vm)) |
2812 | obj->map_and_fenceable = true; | |
673a394b | 2813 | |
2f633156 BW |
2814 | drm_mm_remove_node(&vma->node); |
2815 | i915_gem_vma_destroy(vma); | |
2816 | ||
2817 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2818 | * no more VMAs exist. */ |
2f633156 BW |
2819 | if (list_empty(&obj->vma_list)) |
2820 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2821 | |
70903c3b CW |
2822 | /* And finally now the object is completely decoupled from this vma, |
2823 | * we can drop its hold on the backing storage and allow it to be | |
2824 | * reaped by the shrinker. | |
2825 | */ | |
2826 | i915_gem_object_unpin_pages(obj); | |
2827 | ||
88241785 | 2828 | return 0; |
54cf91dc CW |
2829 | } |
2830 | ||
b2da9fe5 | 2831 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 2832 | { |
3e31c6c0 | 2833 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2834 | struct intel_engine_cs *ring; |
1ec14ad3 | 2835 | int ret, i; |
4df2faf4 | 2836 | |
4df2faf4 | 2837 | /* Flush everything onto the inactive list. */ |
b4519513 | 2838 | for_each_ring(ring, dev_priv, i) { |
691e6415 | 2839 | ret = i915_switch_context(ring, ring->default_context); |
b6c7488d BW |
2840 | if (ret) |
2841 | return ret; | |
2842 | ||
3e960501 | 2843 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2844 | if (ret) |
2845 | return ret; | |
2846 | } | |
4df2faf4 | 2847 | |
8a1a49f9 | 2848 | return 0; |
4df2faf4 DV |
2849 | } |
2850 | ||
9ce079e4 CW |
2851 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2852 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2853 | { |
3e31c6c0 | 2854 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
2855 | int fence_reg; |
2856 | int fence_pitch_shift; | |
de151cf6 | 2857 | |
56c844e5 ID |
2858 | if (INTEL_INFO(dev)->gen >= 6) { |
2859 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2860 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2861 | } else { | |
2862 | fence_reg = FENCE_REG_965_0; | |
2863 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2864 | } | |
2865 | ||
d18b9619 CW |
2866 | fence_reg += reg * 8; |
2867 | ||
2868 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2869 | * we split the 64-bit update into two 32-bit writes. In order | |
2870 | * for a partial fence not to be evaluated between writes, we | |
2871 | * precede the update with write to turn off the fence register, | |
2872 | * and only enable the fence as the last step. | |
2873 | * | |
2874 | * For extra levels of paranoia, we make sure each step lands | |
2875 | * before applying the next step. | |
2876 | */ | |
2877 | I915_WRITE(fence_reg, 0); | |
2878 | POSTING_READ(fence_reg); | |
2879 | ||
9ce079e4 | 2880 | if (obj) { |
f343c5f6 | 2881 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2882 | uint64_t val; |
de151cf6 | 2883 | |
f343c5f6 | 2884 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2885 | 0xfffff000) << 32; |
f343c5f6 | 2886 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2887 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2888 | if (obj->tiling_mode == I915_TILING_Y) |
2889 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2890 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2891 | |
d18b9619 CW |
2892 | I915_WRITE(fence_reg + 4, val >> 32); |
2893 | POSTING_READ(fence_reg + 4); | |
2894 | ||
2895 | I915_WRITE(fence_reg + 0, val); | |
2896 | POSTING_READ(fence_reg); | |
2897 | } else { | |
2898 | I915_WRITE(fence_reg + 4, 0); | |
2899 | POSTING_READ(fence_reg + 4); | |
2900 | } | |
de151cf6 JB |
2901 | } |
2902 | ||
9ce079e4 CW |
2903 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2904 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2905 | { |
3e31c6c0 | 2906 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 2907 | u32 val; |
de151cf6 | 2908 | |
9ce079e4 | 2909 | if (obj) { |
f343c5f6 | 2910 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2911 | int pitch_val; |
2912 | int tile_width; | |
c6642782 | 2913 | |
f343c5f6 | 2914 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2915 | (size & -size) != size || |
f343c5f6 BW |
2916 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2917 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2918 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2919 | |
9ce079e4 CW |
2920 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2921 | tile_width = 128; | |
2922 | else | |
2923 | tile_width = 512; | |
2924 | ||
2925 | /* Note: pitch better be a power of two tile widths */ | |
2926 | pitch_val = obj->stride / tile_width; | |
2927 | pitch_val = ffs(pitch_val) - 1; | |
2928 | ||
f343c5f6 | 2929 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2930 | if (obj->tiling_mode == I915_TILING_Y) |
2931 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2932 | val |= I915_FENCE_SIZE_BITS(size); | |
2933 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2934 | val |= I830_FENCE_REG_VALID; | |
2935 | } else | |
2936 | val = 0; | |
2937 | ||
2938 | if (reg < 8) | |
2939 | reg = FENCE_REG_830_0 + reg * 4; | |
2940 | else | |
2941 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2942 | ||
2943 | I915_WRITE(reg, val); | |
2944 | POSTING_READ(reg); | |
de151cf6 JB |
2945 | } |
2946 | ||
9ce079e4 CW |
2947 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2948 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2949 | { |
3e31c6c0 | 2950 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 2951 | uint32_t val; |
de151cf6 | 2952 | |
9ce079e4 | 2953 | if (obj) { |
f343c5f6 | 2954 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2955 | uint32_t pitch_val; |
de151cf6 | 2956 | |
f343c5f6 | 2957 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2958 | (size & -size) != size || |
f343c5f6 BW |
2959 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2960 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2961 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2962 | |
9ce079e4 CW |
2963 | pitch_val = obj->stride / 128; |
2964 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2965 | |
f343c5f6 | 2966 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2967 | if (obj->tiling_mode == I915_TILING_Y) |
2968 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2969 | val |= I830_FENCE_SIZE_BITS(size); | |
2970 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2971 | val |= I830_FENCE_REG_VALID; | |
2972 | } else | |
2973 | val = 0; | |
c6642782 | 2974 | |
9ce079e4 CW |
2975 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2976 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2977 | } | |
2978 | ||
d0a57789 CW |
2979 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2980 | { | |
2981 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2982 | } | |
2983 | ||
9ce079e4 CW |
2984 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2985 | struct drm_i915_gem_object *obj) | |
2986 | { | |
d0a57789 CW |
2987 | struct drm_i915_private *dev_priv = dev->dev_private; |
2988 | ||
2989 | /* Ensure that all CPU reads are completed before installing a fence | |
2990 | * and all writes before removing the fence. | |
2991 | */ | |
2992 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2993 | mb(); | |
2994 | ||
94a335db DV |
2995 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2996 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2997 | obj->stride, obj->tiling_mode); | |
2998 | ||
9ce079e4 | 2999 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 3000 | case 8: |
9ce079e4 | 3001 | case 7: |
56c844e5 | 3002 | case 6: |
9ce079e4 CW |
3003 | case 5: |
3004 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
3005 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
3006 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 3007 | default: BUG(); |
9ce079e4 | 3008 | } |
d0a57789 CW |
3009 | |
3010 | /* And similarly be paranoid that no direct access to this region | |
3011 | * is reordered to before the fence is installed. | |
3012 | */ | |
3013 | if (i915_gem_object_needs_mb(obj)) | |
3014 | mb(); | |
de151cf6 JB |
3015 | } |
3016 | ||
61050808 CW |
3017 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3018 | struct drm_i915_fence_reg *fence) | |
3019 | { | |
3020 | return fence - dev_priv->fence_regs; | |
3021 | } | |
3022 | ||
3023 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3024 | struct drm_i915_fence_reg *fence, | |
3025 | bool enable) | |
3026 | { | |
2dc8aae0 | 3027 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3028 | int reg = fence_number(dev_priv, fence); |
3029 | ||
3030 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3031 | |
3032 | if (enable) { | |
46a0b638 | 3033 | obj->fence_reg = reg; |
61050808 CW |
3034 | fence->obj = obj; |
3035 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3036 | } else { | |
3037 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3038 | fence->obj = NULL; | |
3039 | list_del_init(&fence->lru_list); | |
3040 | } | |
94a335db | 3041 | obj->fence_dirty = false; |
61050808 CW |
3042 | } |
3043 | ||
d9e86c0e | 3044 | static int |
d0a57789 | 3045 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3046 | { |
1c293ea3 | 3047 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3048 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3049 | if (ret) |
3050 | return ret; | |
d9e86c0e CW |
3051 | |
3052 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3053 | } |
3054 | ||
86d5bc37 | 3055 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3056 | return 0; |
3057 | } | |
3058 | ||
3059 | int | |
3060 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3061 | { | |
61050808 | 3062 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3063 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3064 | int ret; |
3065 | ||
d0a57789 | 3066 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3067 | if (ret) |
3068 | return ret; | |
3069 | ||
61050808 CW |
3070 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3071 | return 0; | |
d9e86c0e | 3072 | |
f9c513e9 CW |
3073 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3074 | ||
aff10b30 DV |
3075 | if (WARN_ON(fence->pin_count)) |
3076 | return -EBUSY; | |
3077 | ||
61050808 | 3078 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3079 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3080 | |
3081 | return 0; | |
3082 | } | |
3083 | ||
3084 | static struct drm_i915_fence_reg * | |
a360bb1a | 3085 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3086 | { |
ae3db24a | 3087 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3088 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3089 | int i; |
ae3db24a DV |
3090 | |
3091 | /* First try to find a free reg */ | |
d9e86c0e | 3092 | avail = NULL; |
ae3db24a DV |
3093 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3094 | reg = &dev_priv->fence_regs[i]; | |
3095 | if (!reg->obj) | |
d9e86c0e | 3096 | return reg; |
ae3db24a | 3097 | |
1690e1eb | 3098 | if (!reg->pin_count) |
d9e86c0e | 3099 | avail = reg; |
ae3db24a DV |
3100 | } |
3101 | ||
d9e86c0e | 3102 | if (avail == NULL) |
5dce5b93 | 3103 | goto deadlock; |
ae3db24a DV |
3104 | |
3105 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3106 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3107 | if (reg->pin_count) |
ae3db24a DV |
3108 | continue; |
3109 | ||
8fe301ad | 3110 | return reg; |
ae3db24a DV |
3111 | } |
3112 | ||
5dce5b93 CW |
3113 | deadlock: |
3114 | /* Wait for completion of pending flips which consume fences */ | |
3115 | if (intel_has_pending_fb_unpin(dev)) | |
3116 | return ERR_PTR(-EAGAIN); | |
3117 | ||
3118 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3119 | } |
3120 | ||
de151cf6 | 3121 | /** |
9a5a53b3 | 3122 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3123 | * @obj: object to map through a fence reg |
3124 | * | |
3125 | * When mapping objects through the GTT, userspace wants to be able to write | |
3126 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3127 | * This function walks the fence regs looking for a free one for @obj, |
3128 | * stealing one if it can't find any. | |
3129 | * | |
3130 | * It then sets up the reg based on the object's properties: address, pitch | |
3131 | * and tiling format. | |
9a5a53b3 CW |
3132 | * |
3133 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3134 | */ |
8c4b8c3f | 3135 | int |
06d98131 | 3136 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3137 | { |
05394f39 | 3138 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3139 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3140 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3141 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3142 | int ret; |
de151cf6 | 3143 | |
14415745 CW |
3144 | /* Have we updated the tiling parameters upon the object and so |
3145 | * will need to serialise the write to the associated fence register? | |
3146 | */ | |
5d82e3e6 | 3147 | if (obj->fence_dirty) { |
d0a57789 | 3148 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3149 | if (ret) |
3150 | return ret; | |
3151 | } | |
9a5a53b3 | 3152 | |
d9e86c0e | 3153 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3154 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3155 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3156 | if (!obj->fence_dirty) { |
14415745 CW |
3157 | list_move_tail(®->lru_list, |
3158 | &dev_priv->mm.fence_list); | |
3159 | return 0; | |
3160 | } | |
3161 | } else if (enable) { | |
3162 | reg = i915_find_fence_reg(dev); | |
5dce5b93 CW |
3163 | if (IS_ERR(reg)) |
3164 | return PTR_ERR(reg); | |
d9e86c0e | 3165 | |
14415745 CW |
3166 | if (reg->obj) { |
3167 | struct drm_i915_gem_object *old = reg->obj; | |
3168 | ||
d0a57789 | 3169 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3170 | if (ret) |
3171 | return ret; | |
3172 | ||
14415745 | 3173 | i915_gem_object_fence_lost(old); |
29c5a587 | 3174 | } |
14415745 | 3175 | } else |
a09ba7fa | 3176 | return 0; |
a09ba7fa | 3177 | |
14415745 | 3178 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3179 | |
9ce079e4 | 3180 | return 0; |
de151cf6 JB |
3181 | } |
3182 | ||
42d6ab48 CW |
3183 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3184 | struct drm_mm_node *gtt_space, | |
3185 | unsigned long cache_level) | |
3186 | { | |
3187 | struct drm_mm_node *other; | |
3188 | ||
3189 | /* On non-LLC machines we have to be careful when putting differing | |
3190 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3191 | * crossing memory domains and dying. |
42d6ab48 CW |
3192 | */ |
3193 | if (HAS_LLC(dev)) | |
3194 | return true; | |
3195 | ||
c6cfb325 | 3196 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3197 | return true; |
3198 | ||
3199 | if (list_empty(>t_space->node_list)) | |
3200 | return true; | |
3201 | ||
3202 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3203 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3204 | return false; | |
3205 | ||
3206 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3207 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3208 | return false; | |
3209 | ||
3210 | return true; | |
3211 | } | |
3212 | ||
3213 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3214 | { | |
3215 | #if WATCH_GTT | |
3216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3217 | struct drm_i915_gem_object *obj; | |
3218 | int err = 0; | |
3219 | ||
35c20a60 | 3220 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3221 | if (obj->gtt_space == NULL) { |
3222 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3223 | err++; | |
3224 | continue; | |
3225 | } | |
3226 | ||
3227 | if (obj->cache_level != obj->gtt_space->color) { | |
3228 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3229 | i915_gem_obj_ggtt_offset(obj), |
3230 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3231 | obj->cache_level, |
3232 | obj->gtt_space->color); | |
3233 | err++; | |
3234 | continue; | |
3235 | } | |
3236 | ||
3237 | if (!i915_gem_valid_gtt_space(dev, | |
3238 | obj->gtt_space, | |
3239 | obj->cache_level)) { | |
3240 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3241 | i915_gem_obj_ggtt_offset(obj), |
3242 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3243 | obj->cache_level); |
3244 | err++; | |
3245 | continue; | |
3246 | } | |
3247 | } | |
3248 | ||
3249 | WARN_ON(err); | |
3250 | #endif | |
3251 | } | |
3252 | ||
673a394b EA |
3253 | /** |
3254 | * Finds free space in the GTT aperture and binds the object there. | |
3255 | */ | |
262de145 | 3256 | static struct i915_vma * |
07fe0b12 BW |
3257 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3258 | struct i915_address_space *vm, | |
3259 | unsigned alignment, | |
1ec9e26d | 3260 | unsigned flags) |
673a394b | 3261 | { |
05394f39 | 3262 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3263 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3264 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 | 3265 | size_t gtt_max = |
1ec9e26d | 3266 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3267 | struct i915_vma *vma; |
07f73f69 | 3268 | int ret; |
673a394b | 3269 | |
e28f8711 CW |
3270 | fence_size = i915_gem_get_gtt_size(dev, |
3271 | obj->base.size, | |
3272 | obj->tiling_mode); | |
3273 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3274 | obj->base.size, | |
d865110c | 3275 | obj->tiling_mode, true); |
e28f8711 | 3276 | unfenced_alignment = |
d865110c | 3277 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3278 | obj->base.size, |
3279 | obj->tiling_mode, false); | |
a00b10c3 | 3280 | |
673a394b | 3281 | if (alignment == 0) |
1ec9e26d | 3282 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3283 | unfenced_alignment; |
1ec9e26d | 3284 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3285 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3286 | return ERR_PTR(-EINVAL); |
673a394b EA |
3287 | } |
3288 | ||
1ec9e26d | 3289 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3290 | |
654fc607 CW |
3291 | /* If the object is bigger than the entire aperture, reject it early |
3292 | * before evicting everything in a vain attempt to find space. | |
3293 | */ | |
0a9ae0d7 | 3294 | if (obj->base.size > gtt_max) { |
bd9b6a4e | 3295 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb | 3296 | obj->base.size, |
1ec9e26d | 3297 | flags & PIN_MAPPABLE ? "mappable" : "total", |
0a9ae0d7 | 3298 | gtt_max); |
262de145 | 3299 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3300 | } |
3301 | ||
37e680a1 | 3302 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3303 | if (ret) |
262de145 | 3304 | return ERR_PTR(ret); |
6c085a72 | 3305 | |
fbdda6fb CW |
3306 | i915_gem_object_pin_pages(obj); |
3307 | ||
accfef2e | 3308 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3309 | if (IS_ERR(vma)) |
bc6bc15b | 3310 | goto err_unpin; |
2f633156 | 3311 | |
0a9ae0d7 | 3312 | search_free: |
07fe0b12 | 3313 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3314 | size, alignment, |
31e5d7c6 | 3315 | obj->cache_level, 0, gtt_max, |
62347f9e LK |
3316 | DRM_MM_SEARCH_DEFAULT, |
3317 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3318 | if (ret) { |
f6cd1f15 | 3319 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
1ec9e26d | 3320 | obj->cache_level, flags); |
dc9dd7a2 CW |
3321 | if (ret == 0) |
3322 | goto search_free; | |
9731129c | 3323 | |
bc6bc15b | 3324 | goto err_free_vma; |
673a394b | 3325 | } |
2f633156 | 3326 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3327 | obj->cache_level))) { |
2f633156 | 3328 | ret = -EINVAL; |
bc6bc15b | 3329 | goto err_remove_node; |
673a394b EA |
3330 | } |
3331 | ||
74163907 | 3332 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3333 | if (ret) |
bc6bc15b | 3334 | goto err_remove_node; |
673a394b | 3335 | |
35c20a60 | 3336 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3337 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3338 | |
4bd561b3 BW |
3339 | if (i915_is_ggtt(vm)) { |
3340 | bool mappable, fenceable; | |
a00b10c3 | 3341 | |
49987099 DV |
3342 | fenceable = (vma->node.size == fence_size && |
3343 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3344 | |
49987099 DV |
3345 | mappable = (vma->node.start + obj->base.size <= |
3346 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3347 | |
5cacaac7 | 3348 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3349 | } |
75e9e915 | 3350 | |
1ec9e26d | 3351 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
75e9e915 | 3352 | |
1ec9e26d | 3353 | trace_i915_vma_bind(vma, flags); |
8ea99c92 DV |
3354 | vma->bind_vma(vma, obj->cache_level, |
3355 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); | |
3356 | ||
42d6ab48 | 3357 | i915_gem_verify_gtt(dev); |
262de145 | 3358 | return vma; |
2f633156 | 3359 | |
bc6bc15b | 3360 | err_remove_node: |
6286ef9b | 3361 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3362 | err_free_vma: |
2f633156 | 3363 | i915_gem_vma_destroy(vma); |
262de145 | 3364 | vma = ERR_PTR(ret); |
bc6bc15b | 3365 | err_unpin: |
2f633156 | 3366 | i915_gem_object_unpin_pages(obj); |
262de145 | 3367 | return vma; |
673a394b EA |
3368 | } |
3369 | ||
000433b6 | 3370 | bool |
2c22569b CW |
3371 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3372 | bool force) | |
673a394b | 3373 | { |
673a394b EA |
3374 | /* If we don't have a page list set up, then we're not pinned |
3375 | * to GPU, and we can ignore the cache flush because it'll happen | |
3376 | * again at bind time. | |
3377 | */ | |
05394f39 | 3378 | if (obj->pages == NULL) |
000433b6 | 3379 | return false; |
673a394b | 3380 | |
769ce464 ID |
3381 | /* |
3382 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3383 | * marked as wc by the system, or the system is cache-coherent. | |
3384 | */ | |
3385 | if (obj->stolen) | |
000433b6 | 3386 | return false; |
769ce464 | 3387 | |
9c23f7fc CW |
3388 | /* If the GPU is snooping the contents of the CPU cache, |
3389 | * we do not need to manually clear the CPU cache lines. However, | |
3390 | * the caches are only snooped when the render cache is | |
3391 | * flushed/invalidated. As we always have to emit invalidations | |
3392 | * and flushes when moving into and out of the RENDER domain, correct | |
3393 | * snooping behaviour occurs naturally as the result of our domain | |
3394 | * tracking. | |
3395 | */ | |
2c22569b | 3396 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3397 | return false; |
9c23f7fc | 3398 | |
1c5d22f7 | 3399 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3400 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3401 | |
3402 | return true; | |
e47c68e9 EA |
3403 | } |
3404 | ||
3405 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3406 | static void | |
05394f39 | 3407 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3408 | { |
1c5d22f7 CW |
3409 | uint32_t old_write_domain; |
3410 | ||
05394f39 | 3411 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3412 | return; |
3413 | ||
63256ec5 | 3414 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3415 | * to it immediately go to main memory as far as we know, so there's |
3416 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3417 | * |
3418 | * However, we do have to enforce the order so that all writes through | |
3419 | * the GTT land before any writes to the device, such as updates to | |
3420 | * the GATT itself. | |
e47c68e9 | 3421 | */ |
63256ec5 CW |
3422 | wmb(); |
3423 | ||
05394f39 CW |
3424 | old_write_domain = obj->base.write_domain; |
3425 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3426 | |
3427 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3428 | obj->base.read_domains, |
1c5d22f7 | 3429 | old_write_domain); |
e47c68e9 EA |
3430 | } |
3431 | ||
3432 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3433 | static void | |
2c22569b CW |
3434 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3435 | bool force) | |
e47c68e9 | 3436 | { |
1c5d22f7 | 3437 | uint32_t old_write_domain; |
e47c68e9 | 3438 | |
05394f39 | 3439 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3440 | return; |
3441 | ||
000433b6 CW |
3442 | if (i915_gem_clflush_object(obj, force)) |
3443 | i915_gem_chipset_flush(obj->base.dev); | |
3444 | ||
05394f39 CW |
3445 | old_write_domain = obj->base.write_domain; |
3446 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3447 | |
3448 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3449 | obj->base.read_domains, |
1c5d22f7 | 3450 | old_write_domain); |
e47c68e9 EA |
3451 | } |
3452 | ||
2ef7eeaa EA |
3453 | /** |
3454 | * Moves a single object to the GTT read, and possibly write domain. | |
3455 | * | |
3456 | * This function returns when the move is complete, including waiting on | |
3457 | * flushes to occur. | |
3458 | */ | |
79e53945 | 3459 | int |
2021746e | 3460 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3461 | { |
3e31c6c0 | 3462 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3463 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3464 | int ret; |
2ef7eeaa | 3465 | |
02354392 | 3466 | /* Not valid to be called on unbound objects. */ |
9843877d | 3467 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3468 | return -EINVAL; |
3469 | ||
8d7e3de1 CW |
3470 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3471 | return 0; | |
3472 | ||
0201f1ec | 3473 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3474 | if (ret) |
3475 | return ret; | |
3476 | ||
c8725f3d | 3477 | i915_gem_object_retire(obj); |
2c22569b | 3478 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3479 | |
d0a57789 CW |
3480 | /* Serialise direct access to this object with the barriers for |
3481 | * coherent writes from the GPU, by effectively invalidating the | |
3482 | * GTT domain upon first access. | |
3483 | */ | |
3484 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3485 | mb(); | |
3486 | ||
05394f39 CW |
3487 | old_write_domain = obj->base.write_domain; |
3488 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3489 | |
e47c68e9 EA |
3490 | /* It should now be out of any other write domains, and we can update |
3491 | * the domain values for our changes. | |
3492 | */ | |
05394f39 CW |
3493 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3494 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3495 | if (write) { |
05394f39 CW |
3496 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3497 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3498 | obj->dirty = 1; | |
2ef7eeaa EA |
3499 | } |
3500 | ||
1c5d22f7 CW |
3501 | trace_i915_gem_object_change_domain(obj, |
3502 | old_read_domains, | |
3503 | old_write_domain); | |
3504 | ||
8325a09d | 3505 | /* And bump the LRU for this access */ |
ca191b13 | 3506 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3507 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3508 | if (vma) |
3509 | list_move_tail(&vma->mm_list, | |
3510 | &dev_priv->gtt.base.inactive_list); | |
3511 | ||
3512 | } | |
8325a09d | 3513 | |
e47c68e9 EA |
3514 | return 0; |
3515 | } | |
3516 | ||
e4ffd173 CW |
3517 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3518 | enum i915_cache_level cache_level) | |
3519 | { | |
7bddb01f | 3520 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3521 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3522 | int ret; |
3523 | ||
3524 | if (obj->cache_level == cache_level) | |
3525 | return 0; | |
3526 | ||
d7f46fc4 | 3527 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3528 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3529 | return -EBUSY; | |
3530 | } | |
3531 | ||
df6f783a | 3532 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
3089c6f2 | 3533 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
07fe0b12 | 3534 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3535 | if (ret) |
3536 | return ret; | |
3089c6f2 | 3537 | } |
42d6ab48 CW |
3538 | } |
3539 | ||
3089c6f2 | 3540 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3541 | ret = i915_gem_object_finish_gpu(obj); |
3542 | if (ret) | |
3543 | return ret; | |
3544 | ||
3545 | i915_gem_object_finish_gtt(obj); | |
3546 | ||
3547 | /* Before SandyBridge, you could not use tiling or fence | |
3548 | * registers with snooped memory, so relinquish any fences | |
3549 | * currently pointing to our region in the aperture. | |
3550 | */ | |
42d6ab48 | 3551 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3552 | ret = i915_gem_object_put_fence(obj); |
3553 | if (ret) | |
3554 | return ret; | |
3555 | } | |
3556 | ||
6f65e29a | 3557 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3558 | if (drm_mm_node_allocated(&vma->node)) |
3559 | vma->bind_vma(vma, cache_level, | |
3560 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); | |
e4ffd173 CW |
3561 | } |
3562 | ||
2c22569b CW |
3563 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3564 | vma->node.color = cache_level; | |
3565 | obj->cache_level = cache_level; | |
3566 | ||
3567 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3568 | u32 old_read_domains, old_write_domain; |
3569 | ||
3570 | /* If we're coming from LLC cached, then we haven't | |
3571 | * actually been tracking whether the data is in the | |
3572 | * CPU cache or not, since we only allow one bit set | |
3573 | * in obj->write_domain and have been skipping the clflushes. | |
3574 | * Just set it to the CPU cache for now. | |
3575 | */ | |
c8725f3d | 3576 | i915_gem_object_retire(obj); |
e4ffd173 | 3577 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e4ffd173 CW |
3578 | |
3579 | old_read_domains = obj->base.read_domains; | |
3580 | old_write_domain = obj->base.write_domain; | |
3581 | ||
3582 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3583 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3584 | ||
3585 | trace_i915_gem_object_change_domain(obj, | |
3586 | old_read_domains, | |
3587 | old_write_domain); | |
3588 | } | |
3589 | ||
42d6ab48 | 3590 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3591 | return 0; |
3592 | } | |
3593 | ||
199adf40 BW |
3594 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3595 | struct drm_file *file) | |
e6994aee | 3596 | { |
199adf40 | 3597 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3598 | struct drm_i915_gem_object *obj; |
3599 | int ret; | |
3600 | ||
3601 | ret = i915_mutex_lock_interruptible(dev); | |
3602 | if (ret) | |
3603 | return ret; | |
3604 | ||
3605 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3606 | if (&obj->base == NULL) { | |
3607 | ret = -ENOENT; | |
3608 | goto unlock; | |
3609 | } | |
3610 | ||
651d794f CW |
3611 | switch (obj->cache_level) { |
3612 | case I915_CACHE_LLC: | |
3613 | case I915_CACHE_L3_LLC: | |
3614 | args->caching = I915_CACHING_CACHED; | |
3615 | break; | |
3616 | ||
4257d3ba CW |
3617 | case I915_CACHE_WT: |
3618 | args->caching = I915_CACHING_DISPLAY; | |
3619 | break; | |
3620 | ||
651d794f CW |
3621 | default: |
3622 | args->caching = I915_CACHING_NONE; | |
3623 | break; | |
3624 | } | |
e6994aee CW |
3625 | |
3626 | drm_gem_object_unreference(&obj->base); | |
3627 | unlock: | |
3628 | mutex_unlock(&dev->struct_mutex); | |
3629 | return ret; | |
3630 | } | |
3631 | ||
199adf40 BW |
3632 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3633 | struct drm_file *file) | |
e6994aee | 3634 | { |
199adf40 | 3635 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3636 | struct drm_i915_gem_object *obj; |
3637 | enum i915_cache_level level; | |
3638 | int ret; | |
3639 | ||
199adf40 BW |
3640 | switch (args->caching) { |
3641 | case I915_CACHING_NONE: | |
e6994aee CW |
3642 | level = I915_CACHE_NONE; |
3643 | break; | |
199adf40 | 3644 | case I915_CACHING_CACHED: |
e6994aee CW |
3645 | level = I915_CACHE_LLC; |
3646 | break; | |
4257d3ba CW |
3647 | case I915_CACHING_DISPLAY: |
3648 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3649 | break; | |
e6994aee CW |
3650 | default: |
3651 | return -EINVAL; | |
3652 | } | |
3653 | ||
3bc2913e BW |
3654 | ret = i915_mutex_lock_interruptible(dev); |
3655 | if (ret) | |
3656 | return ret; | |
3657 | ||
e6994aee CW |
3658 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3659 | if (&obj->base == NULL) { | |
3660 | ret = -ENOENT; | |
3661 | goto unlock; | |
3662 | } | |
3663 | ||
3664 | ret = i915_gem_object_set_cache_level(obj, level); | |
3665 | ||
3666 | drm_gem_object_unreference(&obj->base); | |
3667 | unlock: | |
3668 | mutex_unlock(&dev->struct_mutex); | |
3669 | return ret; | |
3670 | } | |
3671 | ||
cc98b413 CW |
3672 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3673 | { | |
19656430 OM |
3674 | struct i915_vma *vma; |
3675 | ||
3676 | if (list_empty(&obj->vma_list)) | |
3677 | return false; | |
3678 | ||
3679 | vma = i915_gem_obj_to_ggtt(obj); | |
3680 | if (!vma) | |
3681 | return false; | |
3682 | ||
cc98b413 CW |
3683 | /* There are 3 sources that pin objects: |
3684 | * 1. The display engine (scanouts, sprites, cursors); | |
3685 | * 2. Reservations for execbuffer; | |
3686 | * 3. The user. | |
3687 | * | |
3688 | * We can ignore reservations as we hold the struct_mutex and | |
3689 | * are only called outside of the reservation path. The user | |
3690 | * can only increment pin_count once, and so if after | |
3691 | * subtracting the potential reference by the user, any pin_count | |
3692 | * remains, it must be due to another use by the display engine. | |
3693 | */ | |
19656430 | 3694 | return vma->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3695 | } |
3696 | ||
b9241ea3 | 3697 | /* |
2da3b9b9 CW |
3698 | * Prepare buffer for display plane (scanout, cursors, etc). |
3699 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3700 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3701 | */ |
3702 | int | |
2da3b9b9 CW |
3703 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3704 | u32 alignment, | |
a4872ba6 | 3705 | struct intel_engine_cs *pipelined) |
b9241ea3 | 3706 | { |
2da3b9b9 | 3707 | u32 old_read_domains, old_write_domain; |
19656430 | 3708 | bool was_pin_display; |
b9241ea3 ZW |
3709 | int ret; |
3710 | ||
0be73284 | 3711 | if (pipelined != obj->ring) { |
2911a35b BW |
3712 | ret = i915_gem_object_sync(obj, pipelined); |
3713 | if (ret) | |
b9241ea3 ZW |
3714 | return ret; |
3715 | } | |
3716 | ||
cc98b413 CW |
3717 | /* Mark the pin_display early so that we account for the |
3718 | * display coherency whilst setting up the cache domains. | |
3719 | */ | |
19656430 | 3720 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3721 | obj->pin_display = true; |
3722 | ||
a7ef0640 EA |
3723 | /* The display engine is not coherent with the LLC cache on gen6. As |
3724 | * a result, we make sure that the pinning that is about to occur is | |
3725 | * done with uncached PTEs. This is lowest common denominator for all | |
3726 | * chipsets. | |
3727 | * | |
3728 | * However for gen6+, we could do better by using the GFDT bit instead | |
3729 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3730 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3731 | */ | |
651d794f CW |
3732 | ret = i915_gem_object_set_cache_level(obj, |
3733 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3734 | if (ret) |
cc98b413 | 3735 | goto err_unpin_display; |
a7ef0640 | 3736 | |
2da3b9b9 CW |
3737 | /* As the user may map the buffer once pinned in the display plane |
3738 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3739 | * always use map_and_fenceable for all scanout buffers. | |
3740 | */ | |
1ec9e26d | 3741 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3742 | if (ret) |
cc98b413 | 3743 | goto err_unpin_display; |
2da3b9b9 | 3744 | |
2c22569b | 3745 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3746 | |
2da3b9b9 | 3747 | old_write_domain = obj->base.write_domain; |
05394f39 | 3748 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3749 | |
3750 | /* It should now be out of any other write domains, and we can update | |
3751 | * the domain values for our changes. | |
3752 | */ | |
e5f1d962 | 3753 | obj->base.write_domain = 0; |
05394f39 | 3754 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3755 | |
3756 | trace_i915_gem_object_change_domain(obj, | |
3757 | old_read_domains, | |
2da3b9b9 | 3758 | old_write_domain); |
b9241ea3 ZW |
3759 | |
3760 | return 0; | |
cc98b413 CW |
3761 | |
3762 | err_unpin_display: | |
19656430 OM |
3763 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3764 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
3765 | return ret; |
3766 | } | |
3767 | ||
3768 | void | |
3769 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3770 | { | |
d7f46fc4 | 3771 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3772 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3773 | } |
3774 | ||
85345517 | 3775 | int |
a8198eea | 3776 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3777 | { |
88241785 CW |
3778 | int ret; |
3779 | ||
a8198eea | 3780 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3781 | return 0; |
3782 | ||
0201f1ec | 3783 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3784 | if (ret) |
3785 | return ret; | |
3786 | ||
a8198eea CW |
3787 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3788 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3789 | return 0; |
85345517 CW |
3790 | } |
3791 | ||
e47c68e9 EA |
3792 | /** |
3793 | * Moves a single object to the CPU read, and possibly write domain. | |
3794 | * | |
3795 | * This function returns when the move is complete, including waiting on | |
3796 | * flushes to occur. | |
3797 | */ | |
dabdfe02 | 3798 | int |
919926ae | 3799 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3800 | { |
1c5d22f7 | 3801 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3802 | int ret; |
3803 | ||
8d7e3de1 CW |
3804 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3805 | return 0; | |
3806 | ||
0201f1ec | 3807 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3808 | if (ret) |
3809 | return ret; | |
3810 | ||
c8725f3d | 3811 | i915_gem_object_retire(obj); |
e47c68e9 | 3812 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3813 | |
05394f39 CW |
3814 | old_write_domain = obj->base.write_domain; |
3815 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3816 | |
e47c68e9 | 3817 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3818 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3819 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3820 | |
05394f39 | 3821 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3822 | } |
3823 | ||
3824 | /* It should now be out of any other write domains, and we can update | |
3825 | * the domain values for our changes. | |
3826 | */ | |
05394f39 | 3827 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3828 | |
3829 | /* If we're writing through the CPU, then the GPU read domains will | |
3830 | * need to be invalidated at next use. | |
3831 | */ | |
3832 | if (write) { | |
05394f39 CW |
3833 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3834 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3835 | } |
2ef7eeaa | 3836 | |
1c5d22f7 CW |
3837 | trace_i915_gem_object_change_domain(obj, |
3838 | old_read_domains, | |
3839 | old_write_domain); | |
3840 | ||
2ef7eeaa EA |
3841 | return 0; |
3842 | } | |
3843 | ||
673a394b EA |
3844 | /* Throttle our rendering by waiting until the ring has completed our requests |
3845 | * emitted over 20 msec ago. | |
3846 | * | |
b962442e EA |
3847 | * Note that if we were to use the current jiffies each time around the loop, |
3848 | * we wouldn't escape the function with any frames outstanding if the time to | |
3849 | * render a frame was over 20ms. | |
3850 | * | |
673a394b EA |
3851 | * This should get us reasonable parallelism between CPU and GPU but also |
3852 | * relatively low latency when blocking on a particular request to finish. | |
3853 | */ | |
40a5f0de | 3854 | static int |
f787a5f5 | 3855 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3856 | { |
f787a5f5 CW |
3857 | struct drm_i915_private *dev_priv = dev->dev_private; |
3858 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3859 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 | 3860 | struct drm_i915_gem_request *request; |
a4872ba6 | 3861 | struct intel_engine_cs *ring = NULL; |
f69061be | 3862 | unsigned reset_counter; |
f787a5f5 CW |
3863 | u32 seqno = 0; |
3864 | int ret; | |
93533c29 | 3865 | |
308887aa DV |
3866 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3867 | if (ret) | |
3868 | return ret; | |
3869 | ||
3870 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3871 | if (ret) | |
3872 | return ret; | |
e110e8d6 | 3873 | |
1c25595f | 3874 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3875 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3876 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3877 | break; | |
40a5f0de | 3878 | |
f787a5f5 CW |
3879 | ring = request->ring; |
3880 | seqno = request->seqno; | |
b962442e | 3881 | } |
f69061be | 3882 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3883 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3884 | |
f787a5f5 CW |
3885 | if (seqno == 0) |
3886 | return 0; | |
2bc43b5c | 3887 | |
b29c19b6 | 3888 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
3889 | if (ret == 0) |
3890 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3891 | |
3892 | return ret; | |
3893 | } | |
3894 | ||
673a394b | 3895 | int |
05394f39 | 3896 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3897 | struct i915_address_space *vm, |
05394f39 | 3898 | uint32_t alignment, |
1ec9e26d | 3899 | unsigned flags) |
673a394b | 3900 | { |
6e7186af | 3901 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 3902 | struct i915_vma *vma; |
673a394b EA |
3903 | int ret; |
3904 | ||
6e7186af BW |
3905 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
3906 | return -ENODEV; | |
3907 | ||
bf3d149b | 3908 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 3909 | return -EINVAL; |
07fe0b12 BW |
3910 | |
3911 | vma = i915_gem_obj_to_vma(obj, vm); | |
07fe0b12 | 3912 | if (vma) { |
d7f46fc4 BW |
3913 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3914 | return -EBUSY; | |
3915 | ||
07fe0b12 BW |
3916 | if ((alignment && |
3917 | vma->node.start & (alignment - 1)) || | |
1ec9e26d | 3918 | (flags & PIN_MAPPABLE && !obj->map_and_fenceable)) { |
d7f46fc4 | 3919 | WARN(vma->pin_count, |
ae7d49d8 | 3920 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3921 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3922 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3923 | i915_gem_obj_offset(obj, vm), alignment, |
1ec9e26d | 3924 | flags & PIN_MAPPABLE, |
05394f39 | 3925 | obj->map_and_fenceable); |
07fe0b12 | 3926 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3927 | if (ret) |
3928 | return ret; | |
8ea99c92 DV |
3929 | |
3930 | vma = NULL; | |
ac0c6b5a CW |
3931 | } |
3932 | } | |
3933 | ||
8ea99c92 | 3934 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
3935 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
3936 | if (IS_ERR(vma)) | |
3937 | return PTR_ERR(vma); | |
22c344e9 | 3938 | } |
76446cac | 3939 | |
8ea99c92 DV |
3940 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
3941 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
74898d7e | 3942 | |
8ea99c92 | 3943 | vma->pin_count++; |
1ec9e26d DV |
3944 | if (flags & PIN_MAPPABLE) |
3945 | obj->pin_mappable |= true; | |
673a394b EA |
3946 | |
3947 | return 0; | |
3948 | } | |
3949 | ||
3950 | void | |
d7f46fc4 | 3951 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3952 | { |
d7f46fc4 | 3953 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 3954 | |
d7f46fc4 BW |
3955 | BUG_ON(!vma); |
3956 | BUG_ON(vma->pin_count == 0); | |
3957 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
3958 | ||
3959 | if (--vma->pin_count == 0) | |
6299f992 | 3960 | obj->pin_mappable = false; |
673a394b EA |
3961 | } |
3962 | ||
d8ffa60b DV |
3963 | bool |
3964 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
3965 | { | |
3966 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
3967 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
3968 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
3969 | ||
3970 | WARN_ON(!ggtt_vma || | |
3971 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
3972 | ggtt_vma->pin_count); | |
3973 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
3974 | return true; | |
3975 | } else | |
3976 | return false; | |
3977 | } | |
3978 | ||
3979 | void | |
3980 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
3981 | { | |
3982 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
3983 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
3984 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
3985 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
3986 | } | |
3987 | } | |
3988 | ||
673a394b EA |
3989 | int |
3990 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3991 | struct drm_file *file) |
673a394b EA |
3992 | { |
3993 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3994 | struct drm_i915_gem_object *obj; |
673a394b EA |
3995 | int ret; |
3996 | ||
02f6bccc DV |
3997 | if (INTEL_INFO(dev)->gen >= 6) |
3998 | return -ENODEV; | |
3999 | ||
1d7cfea1 CW |
4000 | ret = i915_mutex_lock_interruptible(dev); |
4001 | if (ret) | |
4002 | return ret; | |
673a394b | 4003 | |
05394f39 | 4004 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4005 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4006 | ret = -ENOENT; |
4007 | goto unlock; | |
673a394b | 4008 | } |
673a394b | 4009 | |
05394f39 | 4010 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 4011 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
8c99e57d | 4012 | ret = -EFAULT; |
1d7cfea1 | 4013 | goto out; |
3ef94daa CW |
4014 | } |
4015 | ||
05394f39 | 4016 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
bd9b6a4e | 4017 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4018 | args->handle); |
1d7cfea1 CW |
4019 | ret = -EINVAL; |
4020 | goto out; | |
79e53945 JB |
4021 | } |
4022 | ||
aa5f8021 DV |
4023 | if (obj->user_pin_count == ULONG_MAX) { |
4024 | ret = -EBUSY; | |
4025 | goto out; | |
4026 | } | |
4027 | ||
93be8788 | 4028 | if (obj->user_pin_count == 0) { |
1ec9e26d | 4029 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
1d7cfea1 CW |
4030 | if (ret) |
4031 | goto out; | |
673a394b EA |
4032 | } |
4033 | ||
93be8788 CW |
4034 | obj->user_pin_count++; |
4035 | obj->pin_filp = file; | |
4036 | ||
f343c5f6 | 4037 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 4038 | out: |
05394f39 | 4039 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4040 | unlock: |
673a394b | 4041 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4042 | return ret; |
673a394b EA |
4043 | } |
4044 | ||
4045 | int | |
4046 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4047 | struct drm_file *file) |
673a394b EA |
4048 | { |
4049 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4050 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4051 | int ret; |
673a394b | 4052 | |
1d7cfea1 CW |
4053 | ret = i915_mutex_lock_interruptible(dev); |
4054 | if (ret) | |
4055 | return ret; | |
673a394b | 4056 | |
05394f39 | 4057 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4058 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4059 | ret = -ENOENT; |
4060 | goto unlock; | |
673a394b | 4061 | } |
76c1dec1 | 4062 | |
05394f39 | 4063 | if (obj->pin_filp != file) { |
bd9b6a4e | 4064 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4065 | args->handle); |
1d7cfea1 CW |
4066 | ret = -EINVAL; |
4067 | goto out; | |
79e53945 | 4068 | } |
05394f39 CW |
4069 | obj->user_pin_count--; |
4070 | if (obj->user_pin_count == 0) { | |
4071 | obj->pin_filp = NULL; | |
d7f46fc4 | 4072 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 4073 | } |
673a394b | 4074 | |
1d7cfea1 | 4075 | out: |
05394f39 | 4076 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4077 | unlock: |
673a394b | 4078 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4079 | return ret; |
673a394b EA |
4080 | } |
4081 | ||
4082 | int | |
4083 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4084 | struct drm_file *file) |
673a394b EA |
4085 | { |
4086 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4087 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4088 | int ret; |
4089 | ||
76c1dec1 | 4090 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4091 | if (ret) |
76c1dec1 | 4092 | return ret; |
673a394b | 4093 | |
05394f39 | 4094 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4095 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4096 | ret = -ENOENT; |
4097 | goto unlock; | |
673a394b | 4098 | } |
d1b851fc | 4099 | |
0be555b6 CW |
4100 | /* Count all active objects as busy, even if they are currently not used |
4101 | * by the gpu. Users of this interface expect objects to eventually | |
4102 | * become non-busy without any further actions, therefore emit any | |
4103 | * necessary flushes here. | |
c4de0a5d | 4104 | */ |
30dfebf3 | 4105 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4106 | |
30dfebf3 | 4107 | args->busy = obj->active; |
e9808edd CW |
4108 | if (obj->ring) { |
4109 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4110 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4111 | } | |
673a394b | 4112 | |
05394f39 | 4113 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4114 | unlock: |
673a394b | 4115 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4116 | return ret; |
673a394b EA |
4117 | } |
4118 | ||
4119 | int | |
4120 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4121 | struct drm_file *file_priv) | |
4122 | { | |
0206e353 | 4123 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4124 | } |
4125 | ||
3ef94daa CW |
4126 | int |
4127 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4128 | struct drm_file *file_priv) | |
4129 | { | |
4130 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4131 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4132 | int ret; |
3ef94daa CW |
4133 | |
4134 | switch (args->madv) { | |
4135 | case I915_MADV_DONTNEED: | |
4136 | case I915_MADV_WILLNEED: | |
4137 | break; | |
4138 | default: | |
4139 | return -EINVAL; | |
4140 | } | |
4141 | ||
1d7cfea1 CW |
4142 | ret = i915_mutex_lock_interruptible(dev); |
4143 | if (ret) | |
4144 | return ret; | |
4145 | ||
05394f39 | 4146 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4147 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4148 | ret = -ENOENT; |
4149 | goto unlock; | |
3ef94daa | 4150 | } |
3ef94daa | 4151 | |
d7f46fc4 | 4152 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4153 | ret = -EINVAL; |
4154 | goto out; | |
3ef94daa CW |
4155 | } |
4156 | ||
05394f39 CW |
4157 | if (obj->madv != __I915_MADV_PURGED) |
4158 | obj->madv = args->madv; | |
3ef94daa | 4159 | |
6c085a72 CW |
4160 | /* if the object is no longer attached, discard its backing storage */ |
4161 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4162 | i915_gem_object_truncate(obj); |
4163 | ||
05394f39 | 4164 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4165 | |
1d7cfea1 | 4166 | out: |
05394f39 | 4167 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4168 | unlock: |
3ef94daa | 4169 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4170 | return ret; |
3ef94daa CW |
4171 | } |
4172 | ||
37e680a1 CW |
4173 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4174 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4175 | { |
35c20a60 | 4176 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4177 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4178 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4179 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4180 | |
37e680a1 CW |
4181 | obj->ops = ops; |
4182 | ||
0327d6ba CW |
4183 | obj->fence_reg = I915_FENCE_REG_NONE; |
4184 | obj->madv = I915_MADV_WILLNEED; | |
4185 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4186 | obj->map_and_fenceable = true; | |
4187 | ||
4188 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4189 | } | |
4190 | ||
37e680a1 CW |
4191 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4192 | .get_pages = i915_gem_object_get_pages_gtt, | |
4193 | .put_pages = i915_gem_object_put_pages_gtt, | |
4194 | }; | |
4195 | ||
05394f39 CW |
4196 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4197 | size_t size) | |
ac52bc56 | 4198 | { |
c397b908 | 4199 | struct drm_i915_gem_object *obj; |
5949eac4 | 4200 | struct address_space *mapping; |
1a240d4d | 4201 | gfp_t mask; |
ac52bc56 | 4202 | |
42dcedd4 | 4203 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4204 | if (obj == NULL) |
4205 | return NULL; | |
673a394b | 4206 | |
c397b908 | 4207 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4208 | i915_gem_object_free(obj); |
c397b908 DV |
4209 | return NULL; |
4210 | } | |
673a394b | 4211 | |
bed1ea95 CW |
4212 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4213 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4214 | /* 965gm cannot relocate objects above 4GiB. */ | |
4215 | mask &= ~__GFP_HIGHMEM; | |
4216 | mask |= __GFP_DMA32; | |
4217 | } | |
4218 | ||
496ad9aa | 4219 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4220 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4221 | |
37e680a1 | 4222 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4223 | |
c397b908 DV |
4224 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4225 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4226 | |
3d29b842 ED |
4227 | if (HAS_LLC(dev)) { |
4228 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4229 | * cache) for about a 10% performance improvement |
4230 | * compared to uncached. Graphics requests other than | |
4231 | * display scanout are coherent with the CPU in | |
4232 | * accessing this cache. This means in this mode we | |
4233 | * don't need to clflush on the CPU side, and on the | |
4234 | * GPU side we only need to flush internal caches to | |
4235 | * get data visible to the CPU. | |
4236 | * | |
4237 | * However, we maintain the display planes as UC, and so | |
4238 | * need to rebind when first used as such. | |
4239 | */ | |
4240 | obj->cache_level = I915_CACHE_LLC; | |
4241 | } else | |
4242 | obj->cache_level = I915_CACHE_NONE; | |
4243 | ||
d861e338 DV |
4244 | trace_i915_gem_object_create(obj); |
4245 | ||
05394f39 | 4246 | return obj; |
c397b908 DV |
4247 | } |
4248 | ||
340fbd8c CW |
4249 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4250 | { | |
4251 | /* If we are the last user of the backing storage (be it shmemfs | |
4252 | * pages or stolen etc), we know that the pages are going to be | |
4253 | * immediately released. In this case, we can then skip copying | |
4254 | * back the contents from the GPU. | |
4255 | */ | |
4256 | ||
4257 | if (obj->madv != I915_MADV_WILLNEED) | |
4258 | return false; | |
4259 | ||
4260 | if (obj->base.filp == NULL) | |
4261 | return true; | |
4262 | ||
4263 | /* At first glance, this looks racy, but then again so would be | |
4264 | * userspace racing mmap against close. However, the first external | |
4265 | * reference to the filp can only be obtained through the | |
4266 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4267 | * acquiring such a reference whilst we are in the middle of | |
4268 | * freeing the object. | |
4269 | */ | |
4270 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4271 | } | |
4272 | ||
1488fc08 | 4273 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4274 | { |
1488fc08 | 4275 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4276 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4277 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4278 | struct i915_vma *vma, *next; |
673a394b | 4279 | |
f65c9168 PZ |
4280 | intel_runtime_pm_get(dev_priv); |
4281 | ||
26e12f89 CW |
4282 | trace_i915_gem_object_destroy(obj); |
4283 | ||
1488fc08 CW |
4284 | if (obj->phys_obj) |
4285 | i915_gem_detach_phys_object(dev, obj); | |
4286 | ||
07fe0b12 | 4287 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4288 | int ret; |
4289 | ||
4290 | vma->pin_count = 0; | |
4291 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4292 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4293 | bool was_interruptible; | |
1488fc08 | 4294 | |
07fe0b12 BW |
4295 | was_interruptible = dev_priv->mm.interruptible; |
4296 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4297 | |
07fe0b12 | 4298 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4299 | |
07fe0b12 BW |
4300 | dev_priv->mm.interruptible = was_interruptible; |
4301 | } | |
1488fc08 CW |
4302 | } |
4303 | ||
1d64ae71 BW |
4304 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4305 | * before progressing. */ | |
4306 | if (obj->stolen) | |
4307 | i915_gem_object_unpin_pages(obj); | |
4308 | ||
401c29f6 BW |
4309 | if (WARN_ON(obj->pages_pin_count)) |
4310 | obj->pages_pin_count = 0; | |
340fbd8c | 4311 | if (discard_backing_storage(obj)) |
5537252b | 4312 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4313 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4314 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4315 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4316 | |
9da3da66 CW |
4317 | BUG_ON(obj->pages); |
4318 | ||
2f745ad3 CW |
4319 | if (obj->base.import_attach) |
4320 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4321 | |
5cc9ed4b CW |
4322 | if (obj->ops->release) |
4323 | obj->ops->release(obj); | |
4324 | ||
05394f39 CW |
4325 | drm_gem_object_release(&obj->base); |
4326 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4327 | |
05394f39 | 4328 | kfree(obj->bit_17); |
42dcedd4 | 4329 | i915_gem_object_free(obj); |
f65c9168 PZ |
4330 | |
4331 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4332 | } |
4333 | ||
e656a6cb | 4334 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4335 | struct i915_address_space *vm) |
e656a6cb DV |
4336 | { |
4337 | struct i915_vma *vma; | |
4338 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4339 | if (vma->vm == vm) | |
4340 | return vma; | |
4341 | ||
4342 | return NULL; | |
4343 | } | |
4344 | ||
2f633156 BW |
4345 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4346 | { | |
4347 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4348 | |
4349 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4350 | if (!list_empty(&vma->exec_list)) | |
4351 | return; | |
4352 | ||
8b9c2b94 | 4353 | list_del(&vma->vma_link); |
b93dab6e | 4354 | |
2f633156 BW |
4355 | kfree(vma); |
4356 | } | |
4357 | ||
e3efda49 CW |
4358 | static void |
4359 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4360 | { | |
4361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4362 | struct intel_engine_cs *ring; |
e3efda49 CW |
4363 | int i; |
4364 | ||
4365 | for_each_ring(ring, dev_priv, i) | |
4366 | intel_stop_ring_buffer(ring); | |
4367 | } | |
4368 | ||
29105ccc | 4369 | int |
45c5f202 | 4370 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4371 | { |
3e31c6c0 | 4372 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4373 | int ret = 0; |
28dfe52a | 4374 | |
45c5f202 | 4375 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4376 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4377 | goto err; |
28dfe52a | 4378 | |
b2da9fe5 | 4379 | ret = i915_gpu_idle(dev); |
f7403347 | 4380 | if (ret) |
45c5f202 | 4381 | goto err; |
f7403347 | 4382 | |
b2da9fe5 | 4383 | i915_gem_retire_requests(dev); |
673a394b | 4384 | |
29105ccc | 4385 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4386 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4387 | i915_gem_evict_everything(dev); |
29105ccc | 4388 | |
29105ccc | 4389 | i915_kernel_lost_context(dev); |
e3efda49 | 4390 | i915_gem_stop_ringbuffers(dev); |
29105ccc | 4391 | |
45c5f202 CW |
4392 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4393 | * We need to replace this with a semaphore, or something. | |
4394 | * And not confound ums.mm_suspended! | |
4395 | */ | |
4396 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4397 | DRIVER_MODESET); | |
4398 | mutex_unlock(&dev->struct_mutex); | |
4399 | ||
4400 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4401 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
b29c19b6 | 4402 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4403 | |
673a394b | 4404 | return 0; |
45c5f202 CW |
4405 | |
4406 | err: | |
4407 | mutex_unlock(&dev->struct_mutex); | |
4408 | return ret; | |
673a394b EA |
4409 | } |
4410 | ||
a4872ba6 | 4411 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4412 | { |
c3787e2e | 4413 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4414 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4415 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4416 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4417 | int i, ret; |
b9524a1e | 4418 | |
040d2baa | 4419 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4420 | return 0; |
b9524a1e | 4421 | |
c3787e2e BW |
4422 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4423 | if (ret) | |
4424 | return ret; | |
b9524a1e | 4425 | |
c3787e2e BW |
4426 | /* |
4427 | * Note: We do not worry about the concurrent register cacheline hang | |
4428 | * here because no other code should access these registers other than | |
4429 | * at initialization time. | |
4430 | */ | |
b9524a1e | 4431 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4432 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4433 | intel_ring_emit(ring, reg_base + i); | |
4434 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4435 | } |
4436 | ||
c3787e2e | 4437 | intel_ring_advance(ring); |
b9524a1e | 4438 | |
c3787e2e | 4439 | return ret; |
b9524a1e BW |
4440 | } |
4441 | ||
f691e2f4 DV |
4442 | void i915_gem_init_swizzling(struct drm_device *dev) |
4443 | { | |
3e31c6c0 | 4444 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4445 | |
11782b02 | 4446 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4447 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4448 | return; | |
4449 | ||
4450 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4451 | DISP_TILE_SURFACE_SWIZZLING); | |
4452 | ||
11782b02 DV |
4453 | if (IS_GEN5(dev)) |
4454 | return; | |
4455 | ||
f691e2f4 DV |
4456 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4457 | if (IS_GEN6(dev)) | |
6b26c86d | 4458 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4459 | else if (IS_GEN7(dev)) |
6b26c86d | 4460 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4461 | else if (IS_GEN8(dev)) |
4462 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4463 | else |
4464 | BUG(); | |
f691e2f4 | 4465 | } |
e21af88d | 4466 | |
67b1b571 CW |
4467 | static bool |
4468 | intel_enable_blt(struct drm_device *dev) | |
4469 | { | |
4470 | if (!HAS_BLT(dev)) | |
4471 | return false; | |
4472 | ||
4473 | /* The blitter was dysfunctional on early prototypes */ | |
4474 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4475 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4476 | " graphics performance will be degraded.\n"); | |
4477 | return false; | |
4478 | } | |
4479 | ||
4480 | return true; | |
4481 | } | |
4482 | ||
4fc7c971 | 4483 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4484 | { |
4fc7c971 | 4485 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4486 | int ret; |
68f95ba9 | 4487 | |
5c1143bb | 4488 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4489 | if (ret) |
b6913e4b | 4490 | return ret; |
68f95ba9 CW |
4491 | |
4492 | if (HAS_BSD(dev)) { | |
5c1143bb | 4493 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4494 | if (ret) |
4495 | goto cleanup_render_ring; | |
d1b851fc | 4496 | } |
68f95ba9 | 4497 | |
67b1b571 | 4498 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4499 | ret = intel_init_blt_ring_buffer(dev); |
4500 | if (ret) | |
4501 | goto cleanup_bsd_ring; | |
4502 | } | |
4503 | ||
9a8a2213 BW |
4504 | if (HAS_VEBOX(dev)) { |
4505 | ret = intel_init_vebox_ring_buffer(dev); | |
4506 | if (ret) | |
4507 | goto cleanup_blt_ring; | |
4508 | } | |
4509 | ||
845f74a7 ZY |
4510 | if (HAS_BSD2(dev)) { |
4511 | ret = intel_init_bsd2_ring_buffer(dev); | |
4512 | if (ret) | |
4513 | goto cleanup_vebox_ring; | |
4514 | } | |
9a8a2213 | 4515 | |
99433931 | 4516 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4517 | if (ret) |
845f74a7 | 4518 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4519 | |
4520 | return 0; | |
4521 | ||
845f74a7 ZY |
4522 | cleanup_bsd2_ring: |
4523 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4524 | cleanup_vebox_ring: |
4525 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4526 | cleanup_blt_ring: |
4527 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4528 | cleanup_bsd_ring: | |
4529 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4530 | cleanup_render_ring: | |
4531 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4532 | ||
4533 | return ret; | |
4534 | } | |
4535 | ||
4536 | int | |
4537 | i915_gem_init_hw(struct drm_device *dev) | |
4538 | { | |
3e31c6c0 | 4539 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4540 | int ret, i; |
4fc7c971 BW |
4541 | |
4542 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4543 | return -EIO; | |
4544 | ||
59124506 | 4545 | if (dev_priv->ellc_size) |
05e21cc4 | 4546 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4547 | |
0bf21347 VS |
4548 | if (IS_HASWELL(dev)) |
4549 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4550 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4551 | |
88a2b2a3 | 4552 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4553 | if (IS_IVYBRIDGE(dev)) { |
4554 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4555 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4556 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4557 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4558 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4559 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4560 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4561 | } | |
88a2b2a3 BW |
4562 | } |
4563 | ||
4fc7c971 BW |
4564 | i915_gem_init_swizzling(dev); |
4565 | ||
4566 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4567 | if (ret) |
4568 | return ret; | |
4569 | ||
c3787e2e BW |
4570 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4571 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4572 | ||
254f965c | 4573 | /* |
2fa48d8d BW |
4574 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4575 | * default context switch however is something we'd like to do after | |
4576 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4577 | * goes with our code better). Context switching requires rings (for | |
4578 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4579 | */ |
2fa48d8d | 4580 | ret = i915_gem_context_enable(dev_priv); |
60990320 | 4581 | if (ret && ret != -EIO) { |
2fa48d8d | 4582 | DRM_ERROR("Context enable failed %d\n", ret); |
60990320 | 4583 | i915_gem_cleanup_ringbuffer(dev); |
b7c36d25 | 4584 | } |
e21af88d | 4585 | |
2fa48d8d | 4586 | return ret; |
8187a2b7 ZN |
4587 | } |
4588 | ||
1070a42b CW |
4589 | int i915_gem_init(struct drm_device *dev) |
4590 | { | |
4591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4592 | int ret; |
4593 | ||
1070a42b | 4594 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4595 | |
4596 | if (IS_VALLEYVIEW(dev)) { | |
4597 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4598 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4599 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4600 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4601 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4602 | } | |
4603 | ||
5cc9ed4b | 4604 | i915_gem_init_userptr(dev); |
d7e5008f | 4605 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4606 | |
2fa48d8d | 4607 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4608 | if (ret) { |
4609 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4610 | return ret; |
e3848694 | 4611 | } |
2fa48d8d | 4612 | |
1070a42b | 4613 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4614 | if (ret == -EIO) { |
4615 | /* Allow ring initialisation to fail by marking the GPU as | |
4616 | * wedged. But we only want to do this where the GPU is angry, | |
4617 | * for all other failure, such as an allocation failure, bail. | |
4618 | */ | |
4619 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4620 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4621 | ret = 0; | |
1070a42b | 4622 | } |
60990320 | 4623 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4624 | |
53ca26ca DV |
4625 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4626 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4627 | dev_priv->dri1.allow_batchbuffer = 1; | |
60990320 | 4628 | return ret; |
1070a42b CW |
4629 | } |
4630 | ||
8187a2b7 ZN |
4631 | void |
4632 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4633 | { | |
3e31c6c0 | 4634 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4635 | struct intel_engine_cs *ring; |
1ec14ad3 | 4636 | int i; |
8187a2b7 | 4637 | |
b4519513 CW |
4638 | for_each_ring(ring, dev_priv, i) |
4639 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4640 | } |
4641 | ||
673a394b EA |
4642 | int |
4643 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4644 | struct drm_file *file_priv) | |
4645 | { | |
db1b76ca | 4646 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4647 | int ret; |
673a394b | 4648 | |
79e53945 JB |
4649 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4650 | return 0; | |
4651 | ||
1f83fee0 | 4652 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4653 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4654 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4655 | } |
4656 | ||
673a394b | 4657 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4658 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4659 | |
f691e2f4 | 4660 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4661 | if (ret != 0) { |
4662 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4663 | return ret; |
d816f6ac | 4664 | } |
9bb2d6f9 | 4665 | |
5cef07e1 | 4666 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
dbb19d30 | 4667 | |
bb0f1b5c | 4668 | ret = drm_irq_install(dev, dev->pdev->irq); |
5f35308b CW |
4669 | if (ret) |
4670 | goto cleanup_ringbuffer; | |
e090c53b | 4671 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4672 | |
673a394b | 4673 | return 0; |
5f35308b CW |
4674 | |
4675 | cleanup_ringbuffer: | |
5f35308b | 4676 | i915_gem_cleanup_ringbuffer(dev); |
db1b76ca | 4677 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4678 | mutex_unlock(&dev->struct_mutex); |
4679 | ||
4680 | return ret; | |
673a394b EA |
4681 | } |
4682 | ||
4683 | int | |
4684 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4685 | struct drm_file *file_priv) | |
4686 | { | |
79e53945 JB |
4687 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4688 | return 0; | |
4689 | ||
e090c53b | 4690 | mutex_lock(&dev->struct_mutex); |
dbb19d30 | 4691 | drm_irq_uninstall(dev); |
e090c53b | 4692 | mutex_unlock(&dev->struct_mutex); |
db1b76ca | 4693 | |
45c5f202 | 4694 | return i915_gem_suspend(dev); |
673a394b EA |
4695 | } |
4696 | ||
4697 | void | |
4698 | i915_gem_lastclose(struct drm_device *dev) | |
4699 | { | |
4700 | int ret; | |
673a394b | 4701 | |
e806b495 EA |
4702 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4703 | return; | |
4704 | ||
45c5f202 | 4705 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4706 | if (ret) |
4707 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4708 | } |
4709 | ||
64193406 | 4710 | static void |
a4872ba6 | 4711 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4712 | { |
4713 | INIT_LIST_HEAD(&ring->active_list); | |
4714 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4715 | } |
4716 | ||
7e0d96bc BW |
4717 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4718 | struct i915_address_space *vm) | |
fc8c067e | 4719 | { |
7e0d96bc BW |
4720 | if (!i915_is_ggtt(vm)) |
4721 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4722 | vm->dev = dev_priv->dev; |
4723 | INIT_LIST_HEAD(&vm->active_list); | |
4724 | INIT_LIST_HEAD(&vm->inactive_list); | |
4725 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4726 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4727 | } |
4728 | ||
673a394b EA |
4729 | void |
4730 | i915_gem_load(struct drm_device *dev) | |
4731 | { | |
3e31c6c0 | 4732 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4733 | int i; |
4734 | ||
4735 | dev_priv->slab = | |
4736 | kmem_cache_create("i915_gem_object", | |
4737 | sizeof(struct drm_i915_gem_object), 0, | |
4738 | SLAB_HWCACHE_ALIGN, | |
4739 | NULL); | |
673a394b | 4740 | |
fc8c067e BW |
4741 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4742 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4743 | ||
a33afea5 | 4744 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4745 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4746 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4747 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4748 | for (i = 0; i < I915_NUM_RINGS; i++) |
4749 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4750 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4751 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4752 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4753 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4754 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4755 | i915_gem_idle_work_handler); | |
1f83fee0 | 4756 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4757 | |
94400120 DA |
4758 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4759 | if (IS_GEN3(dev)) { | |
50743298 DV |
4760 | I915_WRITE(MI_ARB_STATE, |
4761 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4762 | } |
4763 | ||
72bfa19c CW |
4764 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4765 | ||
de151cf6 | 4766 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4767 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4768 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4769 | |
42b5aeab VS |
4770 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4771 | dev_priv->num_fence_regs = 32; | |
4772 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4773 | dev_priv->num_fence_regs = 16; |
4774 | else | |
4775 | dev_priv->num_fence_regs = 8; | |
4776 | ||
b5aa8a0f | 4777 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4778 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4779 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4780 | |
673a394b | 4781 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4782 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4783 | |
ce453d81 CW |
4784 | dev_priv->mm.interruptible = true; |
4785 | ||
ceabbba5 CW |
4786 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
4787 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
4788 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
4789 | register_shrinker(&dev_priv->mm.shrinker); | |
2cfcd32a CW |
4790 | |
4791 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; | |
4792 | register_oom_notifier(&dev_priv->mm.oom_notifier); | |
673a394b | 4793 | } |
71acb5eb DA |
4794 | |
4795 | /* | |
4796 | * Create a physically contiguous memory object for this object | |
4797 | * e.g. for cursor + overlay regs | |
4798 | */ | |
995b6762 CW |
4799 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4800 | int id, int size, int align) | |
71acb5eb | 4801 | { |
3e31c6c0 | 4802 | struct drm_i915_private *dev_priv = dev->dev_private; |
71acb5eb DA |
4803 | struct drm_i915_gem_phys_object *phys_obj; |
4804 | int ret; | |
4805 | ||
4806 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4807 | return 0; | |
4808 | ||
b14c5679 | 4809 | phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL); |
71acb5eb DA |
4810 | if (!phys_obj) |
4811 | return -ENOMEM; | |
4812 | ||
4813 | phys_obj->id = id; | |
4814 | ||
6eeefaf3 | 4815 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4816 | if (!phys_obj->handle) { |
4817 | ret = -ENOMEM; | |
4818 | goto kfree_obj; | |
4819 | } | |
4820 | #ifdef CONFIG_X86 | |
4821 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4822 | #endif | |
4823 | ||
4824 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4825 | ||
4826 | return 0; | |
4827 | kfree_obj: | |
9a298b2a | 4828 | kfree(phys_obj); |
71acb5eb DA |
4829 | return ret; |
4830 | } | |
4831 | ||
995b6762 | 4832 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb | 4833 | { |
3e31c6c0 | 4834 | struct drm_i915_private *dev_priv = dev->dev_private; |
71acb5eb DA |
4835 | struct drm_i915_gem_phys_object *phys_obj; |
4836 | ||
4837 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4838 | return; | |
4839 | ||
4840 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4841 | if (phys_obj->cur_obj) { | |
4842 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4843 | } | |
4844 | ||
4845 | #ifdef CONFIG_X86 | |
4846 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4847 | #endif | |
4848 | drm_pci_free(dev, phys_obj->handle); | |
4849 | kfree(phys_obj); | |
4850 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4851 | } | |
4852 | ||
4853 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4854 | { | |
4855 | int i; | |
4856 | ||
260883c8 | 4857 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4858 | i915_gem_free_phys_object(dev, i); |
4859 | } | |
4860 | ||
4861 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4862 | struct drm_i915_gem_object *obj) |
71acb5eb | 4863 | { |
496ad9aa | 4864 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4865 | char *vaddr; |
71acb5eb | 4866 | int i; |
71acb5eb DA |
4867 | int page_count; |
4868 | ||
05394f39 | 4869 | if (!obj->phys_obj) |
71acb5eb | 4870 | return; |
05394f39 | 4871 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4872 | |
05394f39 | 4873 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4874 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4875 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4876 | if (!IS_ERR(page)) { |
4877 | char *dst = kmap_atomic(page); | |
4878 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4879 | kunmap_atomic(dst); | |
4880 | ||
4881 | drm_clflush_pages(&page, 1); | |
4882 | ||
4883 | set_page_dirty(page); | |
4884 | mark_page_accessed(page); | |
4885 | page_cache_release(page); | |
4886 | } | |
71acb5eb | 4887 | } |
e76e9aeb | 4888 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4889 | |
05394f39 CW |
4890 | obj->phys_obj->cur_obj = NULL; |
4891 | obj->phys_obj = NULL; | |
71acb5eb DA |
4892 | } |
4893 | ||
4894 | int | |
4895 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4896 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4897 | int id, |
4898 | int align) | |
71acb5eb | 4899 | { |
496ad9aa | 4900 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
3e31c6c0 | 4901 | struct drm_i915_private *dev_priv = dev->dev_private; |
71acb5eb DA |
4902 | int ret = 0; |
4903 | int page_count; | |
4904 | int i; | |
4905 | ||
4906 | if (id > I915_MAX_PHYS_OBJECT) | |
4907 | return -EINVAL; | |
4908 | ||
05394f39 CW |
4909 | if (obj->phys_obj) { |
4910 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4911 | return 0; |
4912 | i915_gem_detach_phys_object(dev, obj); | |
4913 | } | |
4914 | ||
71acb5eb DA |
4915 | /* create a new object */ |
4916 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4917 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4918 | obj->base.size, align); |
71acb5eb | 4919 | if (ret) { |
05394f39 CW |
4920 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4921 | id, obj->base.size); | |
e5281ccd | 4922 | return ret; |
71acb5eb DA |
4923 | } |
4924 | } | |
4925 | ||
4926 | /* bind to the object */ | |
05394f39 CW |
4927 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4928 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4929 | |
05394f39 | 4930 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4931 | |
4932 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4933 | struct page *page; |
4934 | char *dst, *src; | |
4935 | ||
5949eac4 | 4936 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4937 | if (IS_ERR(page)) |
4938 | return PTR_ERR(page); | |
71acb5eb | 4939 | |
ff75b9bc | 4940 | src = kmap_atomic(page); |
05394f39 | 4941 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4942 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4943 | kunmap_atomic(src); |
71acb5eb | 4944 | |
e5281ccd CW |
4945 | mark_page_accessed(page); |
4946 | page_cache_release(page); | |
4947 | } | |
d78b47b9 | 4948 | |
71acb5eb | 4949 | return 0; |
71acb5eb DA |
4950 | } |
4951 | ||
4952 | static int | |
05394f39 CW |
4953 | i915_gem_phys_pwrite(struct drm_device *dev, |
4954 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4955 | struct drm_i915_gem_pwrite *args, |
4956 | struct drm_file *file_priv) | |
4957 | { | |
05394f39 | 4958 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4959 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4960 | |
b47b30cc CW |
4961 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4962 | unsigned long unwritten; | |
4963 | ||
4964 | /* The physical object once assigned is fixed for the lifetime | |
4965 | * of the obj, so we can safely drop the lock and continue | |
4966 | * to access vaddr. | |
4967 | */ | |
4968 | mutex_unlock(&dev->struct_mutex); | |
4969 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4970 | mutex_lock(&dev->struct_mutex); | |
4971 | if (unwritten) | |
4972 | return -EFAULT; | |
4973 | } | |
71acb5eb | 4974 | |
e76e9aeb | 4975 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4976 | return 0; |
4977 | } | |
b962442e | 4978 | |
f787a5f5 | 4979 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4980 | { |
f787a5f5 | 4981 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4982 | |
b29c19b6 CW |
4983 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4984 | ||
b962442e EA |
4985 | /* Clean up our request list when the client is going away, so that |
4986 | * later retire_requests won't dereference our soon-to-be-gone | |
4987 | * file_priv. | |
4988 | */ | |
1c25595f | 4989 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4990 | while (!list_empty(&file_priv->mm.request_list)) { |
4991 | struct drm_i915_gem_request *request; | |
4992 | ||
4993 | request = list_first_entry(&file_priv->mm.request_list, | |
4994 | struct drm_i915_gem_request, | |
4995 | client_list); | |
4996 | list_del(&request->client_list); | |
4997 | request->file_priv = NULL; | |
4998 | } | |
1c25595f | 4999 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5000 | } |
31169714 | 5001 | |
b29c19b6 CW |
5002 | static void |
5003 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
5004 | { | |
5005 | struct drm_i915_file_private *file_priv = | |
5006 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
5007 | ||
5008 | atomic_set(&file_priv->rps_wait_boost, false); | |
5009 | } | |
5010 | ||
5011 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5012 | { | |
5013 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5014 | int ret; |
b29c19b6 CW |
5015 | |
5016 | DRM_DEBUG_DRIVER("\n"); | |
5017 | ||
5018 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5019 | if (!file_priv) | |
5020 | return -ENOMEM; | |
5021 | ||
5022 | file->driver_priv = file_priv; | |
5023 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5024 | file_priv->file = file; |
b29c19b6 CW |
5025 | |
5026 | spin_lock_init(&file_priv->mm.lock); | |
5027 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
5028 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
5029 | i915_gem_file_idle_work_handler); | |
5030 | ||
e422b888 BW |
5031 | ret = i915_gem_context_open(dev, file); |
5032 | if (ret) | |
5033 | kfree(file_priv); | |
b29c19b6 | 5034 | |
e422b888 | 5035 | return ret; |
b29c19b6 CW |
5036 | } |
5037 | ||
5774506f CW |
5038 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
5039 | { | |
5040 | if (!mutex_is_locked(mutex)) | |
5041 | return false; | |
5042 | ||
5043 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
5044 | return mutex->owner == task; | |
5045 | #else | |
5046 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5047 | return false; | |
5048 | #endif | |
5049 | } | |
5050 | ||
b453c4db CW |
5051 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
5052 | { | |
5053 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5054 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
5055 | return false; | |
5056 | ||
5057 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) | |
5058 | return false; | |
5059 | ||
5060 | *unlock = false; | |
5061 | } else | |
5062 | *unlock = true; | |
5063 | ||
5064 | return true; | |
5065 | } | |
5066 | ||
ceabbba5 CW |
5067 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5068 | { | |
5069 | struct i915_vma *vma; | |
5070 | int count = 0; | |
5071 | ||
5072 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5073 | if (drm_mm_node_allocated(&vma->node)) | |
5074 | count++; | |
5075 | ||
5076 | return count; | |
5077 | } | |
5078 | ||
7dc19d5a | 5079 | static unsigned long |
ceabbba5 | 5080 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5081 | { |
17250b71 | 5082 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5083 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5084 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5085 | struct drm_i915_gem_object *obj; |
7dc19d5a | 5086 | unsigned long count; |
b453c4db | 5087 | bool unlock; |
17250b71 | 5088 | |
b453c4db CW |
5089 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5090 | return 0; | |
31169714 | 5091 | |
7dc19d5a | 5092 | count = 0; |
35c20a60 | 5093 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5094 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5095 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5096 | |
5097 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5098 | if (!i915_gem_obj_is_pinned(obj) && |
5099 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5100 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5101 | } |
17250b71 | 5102 | |
5774506f CW |
5103 | if (unlock) |
5104 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5105 | |
7dc19d5a | 5106 | return count; |
31169714 | 5107 | } |
a70a3148 BW |
5108 | |
5109 | /* All the new VM stuff */ | |
5110 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5111 | struct i915_address_space *vm) | |
5112 | { | |
5113 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5114 | struct i915_vma *vma; | |
5115 | ||
6f425321 BW |
5116 | if (!dev_priv->mm.aliasing_ppgtt || |
5117 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5118 | vm = &dev_priv->gtt.base; |
5119 | ||
5120 | BUG_ON(list_empty(&o->vma_list)); | |
5121 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
5122 | if (vma->vm == vm) | |
5123 | return vma->node.start; | |
5124 | ||
5125 | } | |
5126 | return -1; | |
5127 | } | |
5128 | ||
5129 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5130 | struct i915_address_space *vm) | |
5131 | { | |
5132 | struct i915_vma *vma; | |
5133 | ||
5134 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5135 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5136 | return true; |
5137 | ||
5138 | return false; | |
5139 | } | |
5140 | ||
5141 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5142 | { | |
5a1d5eb0 | 5143 | struct i915_vma *vma; |
a70a3148 | 5144 | |
5a1d5eb0 CW |
5145 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5146 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5147 | return true; |
5148 | ||
5149 | return false; | |
5150 | } | |
5151 | ||
5152 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5153 | struct i915_address_space *vm) | |
5154 | { | |
5155 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5156 | struct i915_vma *vma; | |
5157 | ||
6f425321 BW |
5158 | if (!dev_priv->mm.aliasing_ppgtt || |
5159 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5160 | vm = &dev_priv->gtt.base; |
5161 | ||
5162 | BUG_ON(list_empty(&o->vma_list)); | |
5163 | ||
5164 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5165 | if (vma->vm == vm) | |
5166 | return vma->node.size; | |
5167 | ||
5168 | return 0; | |
5169 | } | |
5170 | ||
7dc19d5a | 5171 | static unsigned long |
ceabbba5 | 5172 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5173 | { |
5174 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5175 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5176 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a | 5177 | unsigned long freed; |
b453c4db | 5178 | bool unlock; |
7dc19d5a | 5179 | |
b453c4db CW |
5180 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5181 | return SHRINK_STOP; | |
7dc19d5a | 5182 | |
d9973b43 CW |
5183 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
5184 | if (freed < sc->nr_to_scan) | |
5185 | freed += __i915_gem_shrink(dev_priv, | |
5186 | sc->nr_to_scan - freed, | |
5187 | false); | |
7dc19d5a DC |
5188 | if (unlock) |
5189 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5190 | |
7dc19d5a DC |
5191 | return freed; |
5192 | } | |
5c2abbea | 5193 | |
2cfcd32a CW |
5194 | static int |
5195 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) | |
5196 | { | |
5197 | struct drm_i915_private *dev_priv = | |
5198 | container_of(nb, struct drm_i915_private, mm.oom_notifier); | |
5199 | struct drm_device *dev = dev_priv->dev; | |
5200 | struct drm_i915_gem_object *obj; | |
5201 | unsigned long timeout = msecs_to_jiffies(5000) + 1; | |
5202 | unsigned long pinned, bound, unbound, freed; | |
5203 | bool was_interruptible; | |
5204 | bool unlock; | |
5205 | ||
5206 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) | |
5207 | schedule_timeout_killable(1); | |
5208 | if (timeout == 0) { | |
5209 | pr_err("Unable to purge GPU memory due lock contention.\n"); | |
5210 | return NOTIFY_DONE; | |
5211 | } | |
5212 | ||
5213 | was_interruptible = dev_priv->mm.interruptible; | |
5214 | dev_priv->mm.interruptible = false; | |
5215 | ||
5216 | freed = i915_gem_shrink_all(dev_priv); | |
5217 | ||
5218 | dev_priv->mm.interruptible = was_interruptible; | |
5219 | ||
5220 | /* Because we may be allocating inside our own driver, we cannot | |
5221 | * assert that there are no objects with pinned pages that are not | |
5222 | * being pointed to by hardware. | |
5223 | */ | |
5224 | unbound = bound = pinned = 0; | |
5225 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5226 | if (!obj->base.filp) /* not backed by a freeable object */ | |
5227 | continue; | |
5228 | ||
5229 | if (obj->pages_pin_count) | |
5230 | pinned += obj->base.size; | |
5231 | else | |
5232 | unbound += obj->base.size; | |
5233 | } | |
5234 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5235 | if (!obj->base.filp) | |
5236 | continue; | |
5237 | ||
5238 | if (obj->pages_pin_count) | |
5239 | pinned += obj->base.size; | |
5240 | else | |
5241 | bound += obj->base.size; | |
5242 | } | |
5243 | ||
5244 | if (unlock) | |
5245 | mutex_unlock(&dev->struct_mutex); | |
5246 | ||
5247 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", | |
5248 | freed, pinned); | |
5249 | if (unbound || bound) | |
5250 | pr_err("%lu and %lu bytes still available in the " | |
5251 | "bound and unbound GPU page lists.\n", | |
5252 | bound, unbound); | |
5253 | ||
5254 | *(unsigned long *)ptr += freed; | |
5255 | return NOTIFY_DONE; | |
5256 | } | |
5257 | ||
5c2abbea BW |
5258 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
5259 | { | |
5260 | struct i915_vma *vma; | |
5261 | ||
19656430 OM |
5262 | /* This WARN has probably outlived its usefulness (callers already |
5263 | * WARN if they don't find the GGTT vma they expect). When removing, | |
5264 | * remember to remove the pre-check in is_pin_display() as well */ | |
5c2abbea BW |
5265 | if (WARN_ON(list_empty(&obj->vma_list))) |
5266 | return NULL; | |
5267 | ||
5268 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
6e164c33 | 5269 | if (vma->vm != obj_to_ggtt(obj)) |
5c2abbea BW |
5270 | return NULL; |
5271 | ||
5272 | return vma; | |
5273 | } |