Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
2cfcd32a | 34 | #include <linux/oom.h> |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
43 | bool force); | |
07fe0b12 | 44 | static __must_check int |
23f54483 BW |
45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
46 | bool readonly); | |
c8725f3d CW |
47 | static void |
48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
49 | ||
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
ceabbba5 | 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 57 | struct shrink_control *sc); |
ceabbba5 | 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 59 | struct shrink_control *sc); |
2cfcd32a CW |
60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
61 | unsigned long event, | |
62 | void *ptr); | |
d9973b43 | 63 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
31169714 | 64 | |
c76ce038 CW |
65 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
66 | enum i915_cache_level level) | |
67 | { | |
68 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
69 | } | |
70 | ||
2c22569b CW |
71 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
72 | { | |
73 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
74 | return true; | |
75 | ||
76 | return obj->pin_display; | |
77 | } | |
78 | ||
61050808 CW |
79 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
80 | { | |
81 | if (obj->tiling_mode) | |
82 | i915_gem_release_mmap(obj); | |
83 | ||
84 | /* As we do not have an associated fence register, we will force | |
85 | * a tiling change if we ever need to acquire one. | |
86 | */ | |
5d82e3e6 | 87 | obj->fence_dirty = false; |
61050808 CW |
88 | obj->fence_reg = I915_FENCE_REG_NONE; |
89 | } | |
90 | ||
73aa808f CW |
91 | /* some bookkeeping */ |
92 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
93 | size_t size) | |
94 | { | |
c20e8355 | 95 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
96 | dev_priv->mm.object_count++; |
97 | dev_priv->mm.object_memory += size; | |
c20e8355 | 98 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | } |
100 | ||
101 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
102 | size_t size) | |
103 | { | |
c20e8355 | 104 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | dev_priv->mm.object_count--; |
106 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 107 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
108 | } |
109 | ||
21dd3734 | 110 | static int |
33196ded | 111 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 112 | { |
30dbf0c0 CW |
113 | int ret; |
114 | ||
7abb690a DV |
115 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
116 | i915_terminally_wedged(error)) | |
1f83fee0 | 117 | if (EXIT_COND) |
30dbf0c0 CW |
118 | return 0; |
119 | ||
0a6759c6 DV |
120 | /* |
121 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
122 | * userspace. If it takes that long something really bad is going on and | |
123 | * we should simply try to bail out and fail as gracefully as possible. | |
124 | */ | |
1f83fee0 DV |
125 | ret = wait_event_interruptible_timeout(error->reset_queue, |
126 | EXIT_COND, | |
127 | 10*HZ); | |
0a6759c6 DV |
128 | if (ret == 0) { |
129 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
130 | return -EIO; | |
131 | } else if (ret < 0) { | |
30dbf0c0 | 132 | return ret; |
0a6759c6 | 133 | } |
1f83fee0 | 134 | #undef EXIT_COND |
30dbf0c0 | 135 | |
21dd3734 | 136 | return 0; |
30dbf0c0 CW |
137 | } |
138 | ||
54cf91dc | 139 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 140 | { |
33196ded | 141 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
142 | int ret; |
143 | ||
33196ded | 144 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
145 | if (ret) |
146 | return ret; | |
147 | ||
148 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
149 | if (ret) | |
150 | return ret; | |
151 | ||
23bc5982 | 152 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
153 | return 0; |
154 | } | |
30dbf0c0 | 155 | |
7d1c4804 | 156 | static inline bool |
05394f39 | 157 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 158 | { |
9843877d | 159 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
160 | } |
161 | ||
79e53945 JB |
162 | int |
163 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 164 | struct drm_file *file) |
79e53945 | 165 | { |
93d18799 | 166 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 167 | struct drm_i915_gem_init *args = data; |
2021746e | 168 | |
7bb6fb8d DV |
169 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
170 | return -ENODEV; | |
171 | ||
2021746e CW |
172 | if (args->gtt_start >= args->gtt_end || |
173 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
174 | return -EINVAL; | |
79e53945 | 175 | |
f534bc0b DV |
176 | /* GEM with user mode setting was never supported on ilk and later. */ |
177 | if (INTEL_INFO(dev)->gen >= 5) | |
178 | return -ENODEV; | |
179 | ||
79e53945 | 180 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
181 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
182 | args->gtt_end); | |
93d18799 | 183 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
184 | mutex_unlock(&dev->struct_mutex); |
185 | ||
2021746e | 186 | return 0; |
673a394b EA |
187 | } |
188 | ||
5a125c3c EA |
189 | int |
190 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 191 | struct drm_file *file) |
5a125c3c | 192 | { |
73aa808f | 193 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 194 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
195 | struct drm_i915_gem_object *obj; |
196 | size_t pinned; | |
5a125c3c | 197 | |
6299f992 | 198 | pinned = 0; |
73aa808f | 199 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 200 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 201 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 202 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 203 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 204 | |
853ba5d2 | 205 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 206 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 207 | |
5a125c3c EA |
208 | return 0; |
209 | } | |
210 | ||
6a2c4232 CW |
211 | static int |
212 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 213 | { |
6a2c4232 CW |
214 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
215 | char *vaddr = obj->phys_handle->vaddr; | |
216 | struct sg_table *st; | |
217 | struct scatterlist *sg; | |
218 | int i; | |
00731155 | 219 | |
6a2c4232 CW |
220 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
221 | return -EINVAL; | |
222 | ||
223 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
224 | struct page *page; | |
225 | char *src; | |
226 | ||
227 | page = shmem_read_mapping_page(mapping, i); | |
228 | if (IS_ERR(page)) | |
229 | return PTR_ERR(page); | |
230 | ||
231 | src = kmap_atomic(page); | |
232 | memcpy(vaddr, src, PAGE_SIZE); | |
233 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
234 | kunmap_atomic(src); | |
235 | ||
236 | page_cache_release(page); | |
237 | vaddr += PAGE_SIZE; | |
238 | } | |
239 | ||
240 | i915_gem_chipset_flush(obj->base.dev); | |
241 | ||
242 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
243 | if (st == NULL) | |
244 | return -ENOMEM; | |
245 | ||
246 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
247 | kfree(st); | |
248 | return -ENOMEM; | |
249 | } | |
250 | ||
251 | sg = st->sgl; | |
252 | sg->offset = 0; | |
253 | sg->length = obj->base.size; | |
00731155 | 254 | |
6a2c4232 CW |
255 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
256 | sg_dma_len(sg) = obj->base.size; | |
257 | ||
258 | obj->pages = st; | |
259 | obj->has_dma_mapping = true; | |
260 | return 0; | |
261 | } | |
262 | ||
263 | static void | |
264 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
265 | { | |
266 | int ret; | |
267 | ||
268 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
269 | ||
270 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
271 | if (ret) { | |
272 | /* In the event of a disaster, abandon all caches and | |
273 | * hope for the best. | |
274 | */ | |
275 | WARN_ON(ret != -EIO); | |
276 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
277 | } | |
278 | ||
279 | if (obj->madv == I915_MADV_DONTNEED) | |
280 | obj->dirty = 0; | |
281 | ||
282 | if (obj->dirty) { | |
00731155 | 283 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 284 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
285 | int i; |
286 | ||
287 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
288 | struct page *page; |
289 | char *dst; | |
290 | ||
291 | page = shmem_read_mapping_page(mapping, i); | |
292 | if (IS_ERR(page)) | |
293 | continue; | |
294 | ||
295 | dst = kmap_atomic(page); | |
296 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
297 | memcpy(dst, vaddr, PAGE_SIZE); | |
298 | kunmap_atomic(dst); | |
299 | ||
300 | set_page_dirty(page); | |
301 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 302 | mark_page_accessed(page); |
6a2c4232 | 303 | page_cache_release(page); |
00731155 CW |
304 | vaddr += PAGE_SIZE; |
305 | } | |
6a2c4232 | 306 | obj->dirty = 0; |
00731155 CW |
307 | } |
308 | ||
6a2c4232 CW |
309 | sg_free_table(obj->pages); |
310 | kfree(obj->pages); | |
311 | ||
312 | obj->has_dma_mapping = false; | |
313 | } | |
314 | ||
315 | static void | |
316 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
317 | { | |
318 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
319 | } | |
320 | ||
321 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
322 | .get_pages = i915_gem_object_get_pages_phys, | |
323 | .put_pages = i915_gem_object_put_pages_phys, | |
324 | .release = i915_gem_object_release_phys, | |
325 | }; | |
326 | ||
327 | static int | |
328 | drop_pages(struct drm_i915_gem_object *obj) | |
329 | { | |
330 | struct i915_vma *vma, *next; | |
331 | int ret; | |
332 | ||
333 | drm_gem_object_reference(&obj->base); | |
334 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) | |
335 | if (i915_vma_unbind(vma)) | |
336 | break; | |
337 | ||
338 | ret = i915_gem_object_put_pages(obj); | |
339 | drm_gem_object_unreference(&obj->base); | |
340 | ||
341 | return ret; | |
00731155 CW |
342 | } |
343 | ||
344 | int | |
345 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
346 | int align) | |
347 | { | |
348 | drm_dma_handle_t *phys; | |
6a2c4232 | 349 | int ret; |
00731155 CW |
350 | |
351 | if (obj->phys_handle) { | |
352 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
353 | return -EBUSY; | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | if (obj->madv != I915_MADV_WILLNEED) | |
359 | return -EFAULT; | |
360 | ||
361 | if (obj->base.filp == NULL) | |
362 | return -EINVAL; | |
363 | ||
6a2c4232 CW |
364 | ret = drop_pages(obj); |
365 | if (ret) | |
366 | return ret; | |
367 | ||
00731155 CW |
368 | /* create a new object */ |
369 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
370 | if (!phys) | |
371 | return -ENOMEM; | |
372 | ||
00731155 | 373 | obj->phys_handle = phys; |
6a2c4232 CW |
374 | obj->ops = &i915_gem_phys_ops; |
375 | ||
376 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
377 | } |
378 | ||
379 | static int | |
380 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
381 | struct drm_i915_gem_pwrite *args, | |
382 | struct drm_file *file_priv) | |
383 | { | |
384 | struct drm_device *dev = obj->base.dev; | |
385 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
386 | char __user *user_data = to_user_ptr(args->data_ptr); | |
6a2c4232 CW |
387 | int ret; |
388 | ||
389 | /* We manually control the domain here and pretend that it | |
390 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
391 | */ | |
392 | ret = i915_gem_object_wait_rendering(obj, false); | |
393 | if (ret) | |
394 | return ret; | |
00731155 CW |
395 | |
396 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
397 | unsigned long unwritten; | |
398 | ||
399 | /* The physical object once assigned is fixed for the lifetime | |
400 | * of the obj, so we can safely drop the lock and continue | |
401 | * to access vaddr. | |
402 | */ | |
403 | mutex_unlock(&dev->struct_mutex); | |
404 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
405 | mutex_lock(&dev->struct_mutex); | |
406 | if (unwritten) | |
407 | return -EFAULT; | |
408 | } | |
409 | ||
6a2c4232 | 410 | drm_clflush_virt_range(vaddr, args->size); |
00731155 CW |
411 | i915_gem_chipset_flush(dev); |
412 | return 0; | |
413 | } | |
414 | ||
42dcedd4 CW |
415 | void *i915_gem_object_alloc(struct drm_device *dev) |
416 | { | |
417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 418 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
419 | } |
420 | ||
421 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
422 | { | |
423 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
424 | kmem_cache_free(dev_priv->slab, obj); | |
425 | } | |
426 | ||
ff72145b DA |
427 | static int |
428 | i915_gem_create(struct drm_file *file, | |
429 | struct drm_device *dev, | |
430 | uint64_t size, | |
431 | uint32_t *handle_p) | |
673a394b | 432 | { |
05394f39 | 433 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
434 | int ret; |
435 | u32 handle; | |
673a394b | 436 | |
ff72145b | 437 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
438 | if (size == 0) |
439 | return -EINVAL; | |
673a394b EA |
440 | |
441 | /* Allocate the new object */ | |
ff72145b | 442 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
443 | if (obj == NULL) |
444 | return -ENOMEM; | |
445 | ||
05394f39 | 446 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 447 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
448 | drm_gem_object_unreference_unlocked(&obj->base); |
449 | if (ret) | |
450 | return ret; | |
202f2fef | 451 | |
ff72145b | 452 | *handle_p = handle; |
673a394b EA |
453 | return 0; |
454 | } | |
455 | ||
ff72145b DA |
456 | int |
457 | i915_gem_dumb_create(struct drm_file *file, | |
458 | struct drm_device *dev, | |
459 | struct drm_mode_create_dumb *args) | |
460 | { | |
461 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 462 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
463 | args->size = args->pitch * args->height; |
464 | return i915_gem_create(file, dev, | |
465 | args->size, &args->handle); | |
466 | } | |
467 | ||
ff72145b DA |
468 | /** |
469 | * Creates a new mm object and returns a handle to it. | |
470 | */ | |
471 | int | |
472 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
473 | struct drm_file *file) | |
474 | { | |
475 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 476 | |
ff72145b DA |
477 | return i915_gem_create(file, dev, |
478 | args->size, &args->handle); | |
479 | } | |
480 | ||
8461d226 DV |
481 | static inline int |
482 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
483 | const char *gpu_vaddr, int gpu_offset, | |
484 | int length) | |
485 | { | |
486 | int ret, cpu_offset = 0; | |
487 | ||
488 | while (length > 0) { | |
489 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
490 | int this_length = min(cacheline_end - gpu_offset, length); | |
491 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
492 | ||
493 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
494 | gpu_vaddr + swizzled_gpu_offset, | |
495 | this_length); | |
496 | if (ret) | |
497 | return ret + length; | |
498 | ||
499 | cpu_offset += this_length; | |
500 | gpu_offset += this_length; | |
501 | length -= this_length; | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
8c59967c | 507 | static inline int |
4f0c7cfb BW |
508 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
509 | const char __user *cpu_vaddr, | |
8c59967c DV |
510 | int length) |
511 | { | |
512 | int ret, cpu_offset = 0; | |
513 | ||
514 | while (length > 0) { | |
515 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
516 | int this_length = min(cacheline_end - gpu_offset, length); | |
517 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
518 | ||
519 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
520 | cpu_vaddr + cpu_offset, | |
521 | this_length); | |
522 | if (ret) | |
523 | return ret + length; | |
524 | ||
525 | cpu_offset += this_length; | |
526 | gpu_offset += this_length; | |
527 | length -= this_length; | |
528 | } | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
4c914c0c BV |
533 | /* |
534 | * Pins the specified object's pages and synchronizes the object with | |
535 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
536 | * flush the object from the CPU cache. | |
537 | */ | |
538 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
539 | int *needs_clflush) | |
540 | { | |
541 | int ret; | |
542 | ||
543 | *needs_clflush = 0; | |
544 | ||
545 | if (!obj->base.filp) | |
546 | return -EINVAL; | |
547 | ||
548 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
549 | /* If we're not in the cpu read domain, set ourself into the gtt | |
550 | * read domain and manually flush cachelines (if required). This | |
551 | * optimizes for the case when the gpu will dirty the data | |
552 | * anyway again before the next pread happens. */ | |
553 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
554 | obj->cache_level); | |
555 | ret = i915_gem_object_wait_rendering(obj, true); | |
556 | if (ret) | |
557 | return ret; | |
c8725f3d CW |
558 | |
559 | i915_gem_object_retire(obj); | |
4c914c0c BV |
560 | } |
561 | ||
562 | ret = i915_gem_object_get_pages(obj); | |
563 | if (ret) | |
564 | return ret; | |
565 | ||
566 | i915_gem_object_pin_pages(obj); | |
567 | ||
568 | return ret; | |
569 | } | |
570 | ||
d174bd64 DV |
571 | /* Per-page copy function for the shmem pread fastpath. |
572 | * Flushes invalid cachelines before reading the target if | |
573 | * needs_clflush is set. */ | |
eb01459f | 574 | static int |
d174bd64 DV |
575 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
576 | char __user *user_data, | |
577 | bool page_do_bit17_swizzling, bool needs_clflush) | |
578 | { | |
579 | char *vaddr; | |
580 | int ret; | |
581 | ||
e7e58eb5 | 582 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
583 | return -EINVAL; |
584 | ||
585 | vaddr = kmap_atomic(page); | |
586 | if (needs_clflush) | |
587 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
588 | page_length); | |
589 | ret = __copy_to_user_inatomic(user_data, | |
590 | vaddr + shmem_page_offset, | |
591 | page_length); | |
592 | kunmap_atomic(vaddr); | |
593 | ||
f60d7f0c | 594 | return ret ? -EFAULT : 0; |
d174bd64 DV |
595 | } |
596 | ||
23c18c71 DV |
597 | static void |
598 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
599 | bool swizzled) | |
600 | { | |
e7e58eb5 | 601 | if (unlikely(swizzled)) { |
23c18c71 DV |
602 | unsigned long start = (unsigned long) addr; |
603 | unsigned long end = (unsigned long) addr + length; | |
604 | ||
605 | /* For swizzling simply ensure that we always flush both | |
606 | * channels. Lame, but simple and it works. Swizzled | |
607 | * pwrite/pread is far from a hotpath - current userspace | |
608 | * doesn't use it at all. */ | |
609 | start = round_down(start, 128); | |
610 | end = round_up(end, 128); | |
611 | ||
612 | drm_clflush_virt_range((void *)start, end - start); | |
613 | } else { | |
614 | drm_clflush_virt_range(addr, length); | |
615 | } | |
616 | ||
617 | } | |
618 | ||
d174bd64 DV |
619 | /* Only difference to the fast-path function is that this can handle bit17 |
620 | * and uses non-atomic copy and kmap functions. */ | |
621 | static int | |
622 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
623 | char __user *user_data, | |
624 | bool page_do_bit17_swizzling, bool needs_clflush) | |
625 | { | |
626 | char *vaddr; | |
627 | int ret; | |
628 | ||
629 | vaddr = kmap(page); | |
630 | if (needs_clflush) | |
23c18c71 DV |
631 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
632 | page_length, | |
633 | page_do_bit17_swizzling); | |
d174bd64 DV |
634 | |
635 | if (page_do_bit17_swizzling) | |
636 | ret = __copy_to_user_swizzled(user_data, | |
637 | vaddr, shmem_page_offset, | |
638 | page_length); | |
639 | else | |
640 | ret = __copy_to_user(user_data, | |
641 | vaddr + shmem_page_offset, | |
642 | page_length); | |
643 | kunmap(page); | |
644 | ||
f60d7f0c | 645 | return ret ? - EFAULT : 0; |
d174bd64 DV |
646 | } |
647 | ||
eb01459f | 648 | static int |
dbf7bff0 DV |
649 | i915_gem_shmem_pread(struct drm_device *dev, |
650 | struct drm_i915_gem_object *obj, | |
651 | struct drm_i915_gem_pread *args, | |
652 | struct drm_file *file) | |
eb01459f | 653 | { |
8461d226 | 654 | char __user *user_data; |
eb01459f | 655 | ssize_t remain; |
8461d226 | 656 | loff_t offset; |
eb2c0c81 | 657 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 658 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 659 | int prefaulted = 0; |
8489731c | 660 | int needs_clflush = 0; |
67d5a50c | 661 | struct sg_page_iter sg_iter; |
eb01459f | 662 | |
2bb4629a | 663 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
664 | remain = args->size; |
665 | ||
8461d226 | 666 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 667 | |
4c914c0c | 668 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
669 | if (ret) |
670 | return ret; | |
671 | ||
8461d226 | 672 | offset = args->offset; |
eb01459f | 673 | |
67d5a50c ID |
674 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
675 | offset >> PAGE_SHIFT) { | |
2db76d7c | 676 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
677 | |
678 | if (remain <= 0) | |
679 | break; | |
680 | ||
eb01459f EA |
681 | /* Operation in this page |
682 | * | |
eb01459f | 683 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
684 | * page_length = bytes to copy for this page |
685 | */ | |
c8cbbb8b | 686 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
687 | page_length = remain; |
688 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
689 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 690 | |
8461d226 DV |
691 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
692 | (page_to_phys(page) & (1 << 17)) != 0; | |
693 | ||
d174bd64 DV |
694 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
695 | user_data, page_do_bit17_swizzling, | |
696 | needs_clflush); | |
697 | if (ret == 0) | |
698 | goto next_page; | |
dbf7bff0 | 699 | |
dbf7bff0 DV |
700 | mutex_unlock(&dev->struct_mutex); |
701 | ||
d330a953 | 702 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 703 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
704 | /* Userspace is tricking us, but we've already clobbered |
705 | * its pages with the prefault and promised to write the | |
706 | * data up to the first fault. Hence ignore any errors | |
707 | * and just continue. */ | |
708 | (void)ret; | |
709 | prefaulted = 1; | |
710 | } | |
eb01459f | 711 | |
d174bd64 DV |
712 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
713 | user_data, page_do_bit17_swizzling, | |
714 | needs_clflush); | |
eb01459f | 715 | |
dbf7bff0 | 716 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 717 | |
f60d7f0c | 718 | if (ret) |
8461d226 | 719 | goto out; |
8461d226 | 720 | |
17793c9a | 721 | next_page: |
eb01459f | 722 | remain -= page_length; |
8461d226 | 723 | user_data += page_length; |
eb01459f EA |
724 | offset += page_length; |
725 | } | |
726 | ||
4f27b75d | 727 | out: |
f60d7f0c CW |
728 | i915_gem_object_unpin_pages(obj); |
729 | ||
eb01459f EA |
730 | return ret; |
731 | } | |
732 | ||
673a394b EA |
733 | /** |
734 | * Reads data from the object referenced by handle. | |
735 | * | |
736 | * On error, the contents of *data are undefined. | |
737 | */ | |
738 | int | |
739 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 740 | struct drm_file *file) |
673a394b EA |
741 | { |
742 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 743 | struct drm_i915_gem_object *obj; |
35b62a89 | 744 | int ret = 0; |
673a394b | 745 | |
51311d0a CW |
746 | if (args->size == 0) |
747 | return 0; | |
748 | ||
749 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 750 | to_user_ptr(args->data_ptr), |
51311d0a CW |
751 | args->size)) |
752 | return -EFAULT; | |
753 | ||
4f27b75d | 754 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 755 | if (ret) |
4f27b75d | 756 | return ret; |
673a394b | 757 | |
05394f39 | 758 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 759 | if (&obj->base == NULL) { |
1d7cfea1 CW |
760 | ret = -ENOENT; |
761 | goto unlock; | |
4f27b75d | 762 | } |
673a394b | 763 | |
7dcd2499 | 764 | /* Bounds check source. */ |
05394f39 CW |
765 | if (args->offset > obj->base.size || |
766 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 767 | ret = -EINVAL; |
35b62a89 | 768 | goto out; |
ce9d419d CW |
769 | } |
770 | ||
1286ff73 DV |
771 | /* prime objects have no backing filp to GEM pread/pwrite |
772 | * pages from. | |
773 | */ | |
774 | if (!obj->base.filp) { | |
775 | ret = -EINVAL; | |
776 | goto out; | |
777 | } | |
778 | ||
db53a302 CW |
779 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
780 | ||
dbf7bff0 | 781 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 782 | |
35b62a89 | 783 | out: |
05394f39 | 784 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 785 | unlock: |
4f27b75d | 786 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 787 | return ret; |
673a394b EA |
788 | } |
789 | ||
0839ccb8 KP |
790 | /* This is the fast write path which cannot handle |
791 | * page faults in the source data | |
9b7530cc | 792 | */ |
0839ccb8 KP |
793 | |
794 | static inline int | |
795 | fast_user_write(struct io_mapping *mapping, | |
796 | loff_t page_base, int page_offset, | |
797 | char __user *user_data, | |
798 | int length) | |
9b7530cc | 799 | { |
4f0c7cfb BW |
800 | void __iomem *vaddr_atomic; |
801 | void *vaddr; | |
0839ccb8 | 802 | unsigned long unwritten; |
9b7530cc | 803 | |
3e4d3af5 | 804 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
805 | /* We can use the cpu mem copy function because this is X86. */ |
806 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
807 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 808 | user_data, length); |
3e4d3af5 | 809 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 810 | return unwritten; |
0839ccb8 KP |
811 | } |
812 | ||
3de09aa3 EA |
813 | /** |
814 | * This is the fast pwrite path, where we copy the data directly from the | |
815 | * user into the GTT, uncached. | |
816 | */ | |
673a394b | 817 | static int |
05394f39 CW |
818 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
819 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 820 | struct drm_i915_gem_pwrite *args, |
05394f39 | 821 | struct drm_file *file) |
673a394b | 822 | { |
3e31c6c0 | 823 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 824 | ssize_t remain; |
0839ccb8 | 825 | loff_t offset, page_base; |
673a394b | 826 | char __user *user_data; |
935aaa69 DV |
827 | int page_offset, page_length, ret; |
828 | ||
1ec9e26d | 829 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
830 | if (ret) |
831 | goto out; | |
832 | ||
833 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
834 | if (ret) | |
835 | goto out_unpin; | |
836 | ||
837 | ret = i915_gem_object_put_fence(obj); | |
838 | if (ret) | |
839 | goto out_unpin; | |
673a394b | 840 | |
2bb4629a | 841 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 842 | remain = args->size; |
673a394b | 843 | |
f343c5f6 | 844 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
845 | |
846 | while (remain > 0) { | |
847 | /* Operation in this page | |
848 | * | |
0839ccb8 KP |
849 | * page_base = page offset within aperture |
850 | * page_offset = offset within page | |
851 | * page_length = bytes to copy for this page | |
673a394b | 852 | */ |
c8cbbb8b CW |
853 | page_base = offset & PAGE_MASK; |
854 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
855 | page_length = remain; |
856 | if ((page_offset + remain) > PAGE_SIZE) | |
857 | page_length = PAGE_SIZE - page_offset; | |
858 | ||
0839ccb8 | 859 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
860 | * source page isn't available. Return the error and we'll |
861 | * retry in the slow path. | |
0839ccb8 | 862 | */ |
5d4545ae | 863 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
864 | page_offset, user_data, page_length)) { |
865 | ret = -EFAULT; | |
866 | goto out_unpin; | |
867 | } | |
673a394b | 868 | |
0839ccb8 KP |
869 | remain -= page_length; |
870 | user_data += page_length; | |
871 | offset += page_length; | |
673a394b | 872 | } |
673a394b | 873 | |
935aaa69 | 874 | out_unpin: |
d7f46fc4 | 875 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 876 | out: |
3de09aa3 | 877 | return ret; |
673a394b EA |
878 | } |
879 | ||
d174bd64 DV |
880 | /* Per-page copy function for the shmem pwrite fastpath. |
881 | * Flushes invalid cachelines before writing to the target if | |
882 | * needs_clflush_before is set and flushes out any written cachelines after | |
883 | * writing if needs_clflush is set. */ | |
3043c60c | 884 | static int |
d174bd64 DV |
885 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
886 | char __user *user_data, | |
887 | bool page_do_bit17_swizzling, | |
888 | bool needs_clflush_before, | |
889 | bool needs_clflush_after) | |
673a394b | 890 | { |
d174bd64 | 891 | char *vaddr; |
673a394b | 892 | int ret; |
3de09aa3 | 893 | |
e7e58eb5 | 894 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 895 | return -EINVAL; |
3de09aa3 | 896 | |
d174bd64 DV |
897 | vaddr = kmap_atomic(page); |
898 | if (needs_clflush_before) | |
899 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
900 | page_length); | |
c2831a94 CW |
901 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
902 | user_data, page_length); | |
d174bd64 DV |
903 | if (needs_clflush_after) |
904 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
905 | page_length); | |
906 | kunmap_atomic(vaddr); | |
3de09aa3 | 907 | |
755d2218 | 908 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
909 | } |
910 | ||
d174bd64 DV |
911 | /* Only difference to the fast-path function is that this can handle bit17 |
912 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 913 | static int |
d174bd64 DV |
914 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
915 | char __user *user_data, | |
916 | bool page_do_bit17_swizzling, | |
917 | bool needs_clflush_before, | |
918 | bool needs_clflush_after) | |
673a394b | 919 | { |
d174bd64 DV |
920 | char *vaddr; |
921 | int ret; | |
e5281ccd | 922 | |
d174bd64 | 923 | vaddr = kmap(page); |
e7e58eb5 | 924 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
925 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
926 | page_length, | |
927 | page_do_bit17_swizzling); | |
d174bd64 DV |
928 | if (page_do_bit17_swizzling) |
929 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
930 | user_data, |
931 | page_length); | |
d174bd64 DV |
932 | else |
933 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
934 | user_data, | |
935 | page_length); | |
936 | if (needs_clflush_after) | |
23c18c71 DV |
937 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
938 | page_length, | |
939 | page_do_bit17_swizzling); | |
d174bd64 | 940 | kunmap(page); |
40123c1f | 941 | |
755d2218 | 942 | return ret ? -EFAULT : 0; |
40123c1f EA |
943 | } |
944 | ||
40123c1f | 945 | static int |
e244a443 DV |
946 | i915_gem_shmem_pwrite(struct drm_device *dev, |
947 | struct drm_i915_gem_object *obj, | |
948 | struct drm_i915_gem_pwrite *args, | |
949 | struct drm_file *file) | |
40123c1f | 950 | { |
40123c1f | 951 | ssize_t remain; |
8c59967c DV |
952 | loff_t offset; |
953 | char __user *user_data; | |
eb2c0c81 | 954 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 955 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 956 | int hit_slowpath = 0; |
58642885 DV |
957 | int needs_clflush_after = 0; |
958 | int needs_clflush_before = 0; | |
67d5a50c | 959 | struct sg_page_iter sg_iter; |
40123c1f | 960 | |
2bb4629a | 961 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
962 | remain = args->size; |
963 | ||
8c59967c | 964 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 965 | |
58642885 DV |
966 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
967 | /* If we're not in the cpu write domain, set ourself into the gtt | |
968 | * write domain and manually flush cachelines (if required). This | |
969 | * optimizes for the case when the gpu will use the data | |
970 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 971 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
972 | ret = i915_gem_object_wait_rendering(obj, false); |
973 | if (ret) | |
974 | return ret; | |
c8725f3d CW |
975 | |
976 | i915_gem_object_retire(obj); | |
58642885 | 977 | } |
c76ce038 CW |
978 | /* Same trick applies to invalidate partially written cachelines read |
979 | * before writing. */ | |
980 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
981 | needs_clflush_before = | |
982 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 983 | |
755d2218 CW |
984 | ret = i915_gem_object_get_pages(obj); |
985 | if (ret) | |
986 | return ret; | |
987 | ||
988 | i915_gem_object_pin_pages(obj); | |
989 | ||
673a394b | 990 | offset = args->offset; |
05394f39 | 991 | obj->dirty = 1; |
673a394b | 992 | |
67d5a50c ID |
993 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
994 | offset >> PAGE_SHIFT) { | |
2db76d7c | 995 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 996 | int partial_cacheline_write; |
e5281ccd | 997 | |
9da3da66 CW |
998 | if (remain <= 0) |
999 | break; | |
1000 | ||
40123c1f EA |
1001 | /* Operation in this page |
1002 | * | |
40123c1f | 1003 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
1004 | * page_length = bytes to copy for this page |
1005 | */ | |
c8cbbb8b | 1006 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
1007 | |
1008 | page_length = remain; | |
1009 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1010 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 1011 | |
58642885 DV |
1012 | /* If we don't overwrite a cacheline completely we need to be |
1013 | * careful to have up-to-date data by first clflushing. Don't | |
1014 | * overcomplicate things and flush the entire patch. */ | |
1015 | partial_cacheline_write = needs_clflush_before && | |
1016 | ((shmem_page_offset | page_length) | |
1017 | & (boot_cpu_data.x86_clflush_size - 1)); | |
1018 | ||
8c59967c DV |
1019 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
1020 | (page_to_phys(page) & (1 << 17)) != 0; | |
1021 | ||
d174bd64 DV |
1022 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
1023 | user_data, page_do_bit17_swizzling, | |
1024 | partial_cacheline_write, | |
1025 | needs_clflush_after); | |
1026 | if (ret == 0) | |
1027 | goto next_page; | |
e244a443 DV |
1028 | |
1029 | hit_slowpath = 1; | |
e244a443 | 1030 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1031 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1032 | user_data, page_do_bit17_swizzling, | |
1033 | partial_cacheline_write, | |
1034 | needs_clflush_after); | |
40123c1f | 1035 | |
e244a443 | 1036 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1037 | |
755d2218 | 1038 | if (ret) |
8c59967c | 1039 | goto out; |
8c59967c | 1040 | |
17793c9a | 1041 | next_page: |
40123c1f | 1042 | remain -= page_length; |
8c59967c | 1043 | user_data += page_length; |
40123c1f | 1044 | offset += page_length; |
673a394b EA |
1045 | } |
1046 | ||
fbd5a26d | 1047 | out: |
755d2218 CW |
1048 | i915_gem_object_unpin_pages(obj); |
1049 | ||
e244a443 | 1050 | if (hit_slowpath) { |
8dcf015e DV |
1051 | /* |
1052 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1053 | * cachelines in-line while writing and the object moved | |
1054 | * out of the cpu write domain while we've dropped the lock. | |
1055 | */ | |
1056 | if (!needs_clflush_after && | |
1057 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
1058 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
1059 | i915_gem_chipset_flush(dev); | |
e244a443 | 1060 | } |
8c59967c | 1061 | } |
673a394b | 1062 | |
58642885 | 1063 | if (needs_clflush_after) |
e76e9aeb | 1064 | i915_gem_chipset_flush(dev); |
58642885 | 1065 | |
40123c1f | 1066 | return ret; |
673a394b EA |
1067 | } |
1068 | ||
1069 | /** | |
1070 | * Writes data to the object referenced by handle. | |
1071 | * | |
1072 | * On error, the contents of the buffer that were to be modified are undefined. | |
1073 | */ | |
1074 | int | |
1075 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1076 | struct drm_file *file) |
673a394b EA |
1077 | { |
1078 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1079 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1080 | int ret; |
1081 | ||
1082 | if (args->size == 0) | |
1083 | return 0; | |
1084 | ||
1085 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1086 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1087 | args->size)) |
1088 | return -EFAULT; | |
1089 | ||
d330a953 | 1090 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1091 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1092 | args->size); | |
1093 | if (ret) | |
1094 | return -EFAULT; | |
1095 | } | |
673a394b | 1096 | |
fbd5a26d | 1097 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1098 | if (ret) |
fbd5a26d | 1099 | return ret; |
1d7cfea1 | 1100 | |
05394f39 | 1101 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1102 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1103 | ret = -ENOENT; |
1104 | goto unlock; | |
fbd5a26d | 1105 | } |
673a394b | 1106 | |
7dcd2499 | 1107 | /* Bounds check destination. */ |
05394f39 CW |
1108 | if (args->offset > obj->base.size || |
1109 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1110 | ret = -EINVAL; |
35b62a89 | 1111 | goto out; |
ce9d419d CW |
1112 | } |
1113 | ||
1286ff73 DV |
1114 | /* prime objects have no backing filp to GEM pread/pwrite |
1115 | * pages from. | |
1116 | */ | |
1117 | if (!obj->base.filp) { | |
1118 | ret = -EINVAL; | |
1119 | goto out; | |
1120 | } | |
1121 | ||
db53a302 CW |
1122 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1123 | ||
935aaa69 | 1124 | ret = -EFAULT; |
673a394b EA |
1125 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1126 | * it would end up going through the fenced access, and we'll get | |
1127 | * different detiling behavior between reading and writing. | |
1128 | * pread/pwrite currently are reading and writing from the CPU | |
1129 | * perspective, requiring manual detiling by the client. | |
1130 | */ | |
2c22569b CW |
1131 | if (obj->tiling_mode == I915_TILING_NONE && |
1132 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1133 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1134 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1135 | /* Note that the gtt paths might fail with non-page-backed user |
1136 | * pointers (e.g. gtt mappings when moving data between | |
1137 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1138 | } |
673a394b | 1139 | |
6a2c4232 CW |
1140 | if (ret == -EFAULT || ret == -ENOSPC) { |
1141 | if (obj->phys_handle) | |
1142 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1143 | else | |
1144 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1145 | } | |
5c0480f2 | 1146 | |
35b62a89 | 1147 | out: |
05394f39 | 1148 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1149 | unlock: |
fbd5a26d | 1150 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1151 | return ret; |
1152 | } | |
1153 | ||
b361237b | 1154 | int |
33196ded | 1155 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1156 | bool interruptible) |
1157 | { | |
1f83fee0 | 1158 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1159 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1160 | * -EIO unconditionally for these. */ | |
1161 | if (!interruptible) | |
1162 | return -EIO; | |
1163 | ||
1f83fee0 DV |
1164 | /* Recovery complete, but the reset failed ... */ |
1165 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1166 | return -EIO; |
1167 | ||
6689c167 MA |
1168 | /* |
1169 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1170 | * to work properly to reinit the hw state while the gpu is | |
1171 | * still marked as reset-in-progress. Handle this with a flag. | |
1172 | */ | |
1173 | if (!error->reload_in_reset) | |
1174 | return -EAGAIN; | |
b361237b CW |
1175 | } |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
1180 | /* | |
1181 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
1182 | * equal. | |
1183 | */ | |
84c33a64 | 1184 | int |
a4872ba6 | 1185 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
b361237b CW |
1186 | { |
1187 | int ret; | |
1188 | ||
1189 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
1190 | ||
1191 | ret = 0; | |
1823521d | 1192 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 1193 | ret = i915_add_request(ring, NULL); |
b361237b CW |
1194 | |
1195 | return ret; | |
1196 | } | |
1197 | ||
094f9a54 CW |
1198 | static void fake_irq(unsigned long data) |
1199 | { | |
1200 | wake_up_process((struct task_struct *)data); | |
1201 | } | |
1202 | ||
1203 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1204 | struct intel_engine_cs *ring) |
094f9a54 CW |
1205 | { |
1206 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1207 | } | |
1208 | ||
b29c19b6 CW |
1209 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1210 | { | |
1211 | if (file_priv == NULL) | |
1212 | return true; | |
1213 | ||
1214 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1215 | } | |
1216 | ||
b361237b | 1217 | /** |
16e9a21f | 1218 | * __i915_wait_seqno - wait until execution of seqno has finished |
b361237b CW |
1219 | * @ring: the ring expected to report seqno |
1220 | * @seqno: duh! | |
f69061be | 1221 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
1222 | * @interruptible: do an interruptible wait (normally yes) |
1223 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1224 | * | |
f69061be DV |
1225 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1226 | * values have been read by the caller in an smp safe manner. Where read-side | |
1227 | * locks are involved, it is sufficient to read the reset_counter before | |
1228 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1229 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1230 | * inserted. | |
1231 | * | |
b361237b CW |
1232 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1233 | * errno with remaining time filled in timeout argument. | |
1234 | */ | |
16e9a21f | 1235 | int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
f69061be | 1236 | unsigned reset_counter, |
b29c19b6 | 1237 | bool interruptible, |
5ed0bdf2 | 1238 | s64 *timeout, |
b29c19b6 | 1239 | struct drm_i915_file_private *file_priv) |
b361237b | 1240 | { |
3d13ef2e | 1241 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1242 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1243 | const bool irq_test_in_progress = |
1244 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 | 1245 | DEFINE_WAIT(wait); |
47e9766d | 1246 | unsigned long timeout_expire; |
5ed0bdf2 | 1247 | s64 before, now; |
b361237b CW |
1248 | int ret; |
1249 | ||
9df7575f | 1250 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1251 | |
b361237b CW |
1252 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1253 | return 0; | |
1254 | ||
5ed0bdf2 | 1255 | timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0; |
b361237b | 1256 | |
ec5cc0f9 | 1257 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1258 | gen6_rps_boost(dev_priv); |
1259 | if (file_priv) | |
1260 | mod_delayed_work(dev_priv->wq, | |
1261 | &file_priv->mm.idle_work, | |
1262 | msecs_to_jiffies(100)); | |
1263 | } | |
1264 | ||
168c3f21 | 1265 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1266 | return -ENODEV; |
1267 | ||
094f9a54 CW |
1268 | /* Record current time in case interrupted by signal, or wedged */ |
1269 | trace_i915_gem_request_wait_begin(ring, seqno); | |
5ed0bdf2 | 1270 | before = ktime_get_raw_ns(); |
094f9a54 CW |
1271 | for (;;) { |
1272 | struct timer_list timer; | |
b361237b | 1273 | |
094f9a54 CW |
1274 | prepare_to_wait(&ring->irq_queue, &wait, |
1275 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1276 | |
f69061be DV |
1277 | /* We need to check whether any gpu reset happened in between |
1278 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1279 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1280 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1281 | * is truely gone. */ | |
1282 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1283 | if (ret == 0) | |
1284 | ret = -EAGAIN; | |
1285 | break; | |
1286 | } | |
f69061be | 1287 | |
094f9a54 CW |
1288 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1289 | ret = 0; | |
1290 | break; | |
1291 | } | |
b361237b | 1292 | |
094f9a54 CW |
1293 | if (interruptible && signal_pending(current)) { |
1294 | ret = -ERESTARTSYS; | |
1295 | break; | |
1296 | } | |
1297 | ||
47e9766d | 1298 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1299 | ret = -ETIME; |
1300 | break; | |
1301 | } | |
1302 | ||
1303 | timer.function = NULL; | |
1304 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1305 | unsigned long expire; |
1306 | ||
094f9a54 | 1307 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1308 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1309 | mod_timer(&timer, expire); |
1310 | } | |
1311 | ||
5035c275 | 1312 | io_schedule(); |
094f9a54 | 1313 | |
094f9a54 CW |
1314 | if (timer.function) { |
1315 | del_singleshot_timer_sync(&timer); | |
1316 | destroy_timer_on_stack(&timer); | |
1317 | } | |
1318 | } | |
5ed0bdf2 | 1319 | now = ktime_get_raw_ns(); |
094f9a54 | 1320 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1321 | |
168c3f21 MK |
1322 | if (!irq_test_in_progress) |
1323 | ring->irq_put(ring); | |
094f9a54 CW |
1324 | |
1325 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1326 | |
1327 | if (timeout) { | |
5ed0bdf2 TG |
1328 | s64 tres = *timeout - (now - before); |
1329 | ||
1330 | *timeout = tres < 0 ? 0 : tres; | |
b361237b CW |
1331 | } |
1332 | ||
094f9a54 | 1333 | return ret; |
b361237b CW |
1334 | } |
1335 | ||
1336 | /** | |
1337 | * Waits for a sequence number to be signaled, and cleans up the | |
1338 | * request and object lists appropriately for that event. | |
1339 | */ | |
1340 | int | |
a4872ba6 | 1341 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
b361237b CW |
1342 | { |
1343 | struct drm_device *dev = ring->dev; | |
1344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1345 | bool interruptible = dev_priv->mm.interruptible; | |
16e9a21f | 1346 | unsigned reset_counter; |
b361237b CW |
1347 | int ret; |
1348 | ||
1349 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1350 | BUG_ON(seqno == 0); | |
1351 | ||
33196ded | 1352 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1353 | if (ret) |
1354 | return ret; | |
1355 | ||
1356 | ret = i915_gem_check_olr(ring, seqno); | |
1357 | if (ret) | |
1358 | return ret; | |
1359 | ||
16e9a21f ACO |
1360 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1361 | return __i915_wait_seqno(ring, seqno, reset_counter, interruptible, | |
1362 | NULL, NULL); | |
b361237b CW |
1363 | } |
1364 | ||
d26e3af8 | 1365 | static int |
8e639549 | 1366 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) |
d26e3af8 | 1367 | { |
c8725f3d CW |
1368 | if (!obj->active) |
1369 | return 0; | |
d26e3af8 CW |
1370 | |
1371 | /* Manually manage the write flush as we may have not yet | |
1372 | * retired the buffer. | |
1373 | * | |
1374 | * Note that the last_write_seqno is always the earlier of | |
1375 | * the two (read/write) seqno, so if we haved successfully waited, | |
1376 | * we know we have passed the last write. | |
1377 | */ | |
1378 | obj->last_write_seqno = 0; | |
d26e3af8 CW |
1379 | |
1380 | return 0; | |
1381 | } | |
1382 | ||
b361237b CW |
1383 | /** |
1384 | * Ensures that all rendering to the object has completed and the object is | |
1385 | * safe to unbind from the GTT or access from the CPU. | |
1386 | */ | |
1387 | static __must_check int | |
1388 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1389 | bool readonly) | |
1390 | { | |
a4872ba6 | 1391 | struct intel_engine_cs *ring = obj->ring; |
b361237b CW |
1392 | u32 seqno; |
1393 | int ret; | |
1394 | ||
1395 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1396 | if (seqno == 0) | |
1397 | return 0; | |
1398 | ||
1399 | ret = i915_wait_seqno(ring, seqno); | |
1400 | if (ret) | |
1401 | return ret; | |
1402 | ||
8e639549 | 1403 | return i915_gem_object_wait_rendering__tail(obj); |
b361237b CW |
1404 | } |
1405 | ||
3236f57a CW |
1406 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1407 | * as the object state may change during this call. | |
1408 | */ | |
1409 | static __must_check int | |
1410 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1411 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1412 | bool readonly) |
1413 | { | |
1414 | struct drm_device *dev = obj->base.dev; | |
1415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1416 | struct intel_engine_cs *ring = obj->ring; |
f69061be | 1417 | unsigned reset_counter; |
3236f57a CW |
1418 | u32 seqno; |
1419 | int ret; | |
1420 | ||
1421 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1422 | BUG_ON(!dev_priv->mm.interruptible); | |
1423 | ||
1424 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1425 | if (seqno == 0) | |
1426 | return 0; | |
1427 | ||
33196ded | 1428 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1429 | if (ret) |
1430 | return ret; | |
1431 | ||
1432 | ret = i915_gem_check_olr(ring, seqno); | |
1433 | if (ret) | |
1434 | return ret; | |
1435 | ||
f69061be | 1436 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1437 | mutex_unlock(&dev->struct_mutex); |
16e9a21f ACO |
1438 | ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, |
1439 | file_priv); | |
3236f57a | 1440 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1441 | if (ret) |
1442 | return ret; | |
3236f57a | 1443 | |
8e639549 | 1444 | return i915_gem_object_wait_rendering__tail(obj); |
3236f57a CW |
1445 | } |
1446 | ||
673a394b | 1447 | /** |
2ef7eeaa EA |
1448 | * Called when user space prepares to use an object with the CPU, either |
1449 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1450 | */ |
1451 | int | |
1452 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1453 | struct drm_file *file) |
673a394b EA |
1454 | { |
1455 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1456 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1457 | uint32_t read_domains = args->read_domains; |
1458 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1459 | int ret; |
1460 | ||
2ef7eeaa | 1461 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1462 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1463 | return -EINVAL; |
1464 | ||
21d509e3 | 1465 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1466 | return -EINVAL; |
1467 | ||
1468 | /* Having something in the write domain implies it's in the read | |
1469 | * domain, and only that read domain. Enforce that in the request. | |
1470 | */ | |
1471 | if (write_domain != 0 && read_domains != write_domain) | |
1472 | return -EINVAL; | |
1473 | ||
76c1dec1 | 1474 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1475 | if (ret) |
76c1dec1 | 1476 | return ret; |
1d7cfea1 | 1477 | |
05394f39 | 1478 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1479 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1480 | ret = -ENOENT; |
1481 | goto unlock; | |
76c1dec1 | 1482 | } |
673a394b | 1483 | |
3236f57a CW |
1484 | /* Try to flush the object off the GPU without holding the lock. |
1485 | * We will repeat the flush holding the lock in the normal manner | |
1486 | * to catch cases where we are gazumped. | |
1487 | */ | |
6e4930f6 CW |
1488 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1489 | file->driver_priv, | |
1490 | !write_domain); | |
3236f57a CW |
1491 | if (ret) |
1492 | goto unref; | |
1493 | ||
2ef7eeaa EA |
1494 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1495 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1496 | |
1497 | /* Silently promote "you're not bound, there was nothing to do" | |
1498 | * to success, since the client was just asking us to | |
1499 | * make sure everything was done. | |
1500 | */ | |
1501 | if (ret == -EINVAL) | |
1502 | ret = 0; | |
2ef7eeaa | 1503 | } else { |
e47c68e9 | 1504 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1505 | } |
1506 | ||
3236f57a | 1507 | unref: |
05394f39 | 1508 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1509 | unlock: |
673a394b EA |
1510 | mutex_unlock(&dev->struct_mutex); |
1511 | return ret; | |
1512 | } | |
1513 | ||
1514 | /** | |
1515 | * Called when user space has done writes to this buffer | |
1516 | */ | |
1517 | int | |
1518 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1519 | struct drm_file *file) |
673a394b EA |
1520 | { |
1521 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1522 | struct drm_i915_gem_object *obj; |
673a394b EA |
1523 | int ret = 0; |
1524 | ||
76c1dec1 | 1525 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1526 | if (ret) |
76c1dec1 | 1527 | return ret; |
1d7cfea1 | 1528 | |
05394f39 | 1529 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1530 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1531 | ret = -ENOENT; |
1532 | goto unlock; | |
673a394b EA |
1533 | } |
1534 | ||
673a394b | 1535 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1536 | if (obj->pin_display) |
1537 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1538 | |
05394f39 | 1539 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1540 | unlock: |
673a394b EA |
1541 | mutex_unlock(&dev->struct_mutex); |
1542 | return ret; | |
1543 | } | |
1544 | ||
1545 | /** | |
1546 | * Maps the contents of an object, returning the address it is mapped | |
1547 | * into. | |
1548 | * | |
1549 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1550 | * imply a ref on the object itself. | |
34367381 DV |
1551 | * |
1552 | * IMPORTANT: | |
1553 | * | |
1554 | * DRM driver writers who look a this function as an example for how to do GEM | |
1555 | * mmap support, please don't implement mmap support like here. The modern way | |
1556 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1557 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1558 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1559 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1560 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1561 | */ |
1562 | int | |
1563 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1564 | struct drm_file *file) |
673a394b EA |
1565 | { |
1566 | struct drm_i915_gem_mmap *args = data; | |
1567 | struct drm_gem_object *obj; | |
673a394b EA |
1568 | unsigned long addr; |
1569 | ||
05394f39 | 1570 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1571 | if (obj == NULL) |
bf79cb91 | 1572 | return -ENOENT; |
673a394b | 1573 | |
1286ff73 DV |
1574 | /* prime objects have no backing filp to GEM mmap |
1575 | * pages from. | |
1576 | */ | |
1577 | if (!obj->filp) { | |
1578 | drm_gem_object_unreference_unlocked(obj); | |
1579 | return -EINVAL; | |
1580 | } | |
1581 | ||
6be5ceb0 | 1582 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1583 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1584 | args->offset); | |
bc9025bd | 1585 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1586 | if (IS_ERR((void *)addr)) |
1587 | return addr; | |
1588 | ||
1589 | args->addr_ptr = (uint64_t) addr; | |
1590 | ||
1591 | return 0; | |
1592 | } | |
1593 | ||
de151cf6 JB |
1594 | /** |
1595 | * i915_gem_fault - fault a page into the GTT | |
1596 | * vma: VMA in question | |
1597 | * vmf: fault info | |
1598 | * | |
1599 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1600 | * from userspace. The fault handler takes care of binding the object to | |
1601 | * the GTT (if needed), allocating and programming a fence register (again, | |
1602 | * only if needed based on whether the old reg is still valid or the object | |
1603 | * is tiled) and inserting a new PTE into the faulting process. | |
1604 | * | |
1605 | * Note that the faulting process may involve evicting existing objects | |
1606 | * from the GTT and/or fence registers to make room. So performance may | |
1607 | * suffer if the GTT working set is large or there are few fence registers | |
1608 | * left. | |
1609 | */ | |
1610 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1611 | { | |
05394f39 CW |
1612 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1613 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1614 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1615 | pgoff_t page_offset; |
1616 | unsigned long pfn; | |
1617 | int ret = 0; | |
0f973f27 | 1618 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1619 | |
f65c9168 PZ |
1620 | intel_runtime_pm_get(dev_priv); |
1621 | ||
de151cf6 JB |
1622 | /* We don't use vmf->pgoff since that has the fake offset */ |
1623 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1624 | PAGE_SHIFT; | |
1625 | ||
d9bc7e9f CW |
1626 | ret = i915_mutex_lock_interruptible(dev); |
1627 | if (ret) | |
1628 | goto out; | |
a00b10c3 | 1629 | |
db53a302 CW |
1630 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1631 | ||
6e4930f6 CW |
1632 | /* Try to flush the object off the GPU first without holding the lock. |
1633 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1634 | * repeat the flush holding the lock in the normal manner to catch cases | |
1635 | * where we are gazumped. | |
1636 | */ | |
1637 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1638 | if (ret) | |
1639 | goto unlock; | |
1640 | ||
eb119bd6 CW |
1641 | /* Access to snoopable pages through the GTT is incoherent. */ |
1642 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1643 | ret = -EFAULT; |
eb119bd6 CW |
1644 | goto unlock; |
1645 | } | |
1646 | ||
d9bc7e9f | 1647 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1648 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1649 | if (ret) |
1650 | goto unlock; | |
4a684a41 | 1651 | |
c9839303 CW |
1652 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1653 | if (ret) | |
1654 | goto unpin; | |
74898d7e | 1655 | |
06d98131 | 1656 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1657 | if (ret) |
c9839303 | 1658 | goto unpin; |
7d1c4804 | 1659 | |
b90b91d8 | 1660 | /* Finally, remap it using the new GTT offset */ |
f343c5f6 BW |
1661 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1662 | pfn >>= PAGE_SHIFT; | |
de151cf6 | 1663 | |
b90b91d8 | 1664 | if (!obj->fault_mappable) { |
beff0d0f VS |
1665 | unsigned long size = min_t(unsigned long, |
1666 | vma->vm_end - vma->vm_start, | |
1667 | obj->base.size); | |
b90b91d8 CW |
1668 | int i; |
1669 | ||
beff0d0f | 1670 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
b90b91d8 CW |
1671 | ret = vm_insert_pfn(vma, |
1672 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1673 | pfn + i); | |
1674 | if (ret) | |
1675 | break; | |
1676 | } | |
1677 | ||
1678 | obj->fault_mappable = true; | |
1679 | } else | |
1680 | ret = vm_insert_pfn(vma, | |
1681 | (unsigned long)vmf->virtual_address, | |
1682 | pfn + page_offset); | |
c9839303 | 1683 | unpin: |
d7f46fc4 | 1684 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1685 | unlock: |
de151cf6 | 1686 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1687 | out: |
de151cf6 | 1688 | switch (ret) { |
d9bc7e9f | 1689 | case -EIO: |
2232f031 DV |
1690 | /* |
1691 | * We eat errors when the gpu is terminally wedged to avoid | |
1692 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1693 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1694 | * and so needs to be reported. | |
1695 | */ | |
1696 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1697 | ret = VM_FAULT_SIGBUS; |
1698 | break; | |
1699 | } | |
045e769a | 1700 | case -EAGAIN: |
571c608d DV |
1701 | /* |
1702 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1703 | * handler to reset everything when re-faulting in | |
1704 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1705 | */ |
c715089f CW |
1706 | case 0: |
1707 | case -ERESTARTSYS: | |
bed636ab | 1708 | case -EINTR: |
e79e0fe3 DR |
1709 | case -EBUSY: |
1710 | /* | |
1711 | * EBUSY is ok: this just means that another thread | |
1712 | * already did the job. | |
1713 | */ | |
f65c9168 PZ |
1714 | ret = VM_FAULT_NOPAGE; |
1715 | break; | |
de151cf6 | 1716 | case -ENOMEM: |
f65c9168 PZ |
1717 | ret = VM_FAULT_OOM; |
1718 | break; | |
a7c2e1aa | 1719 | case -ENOSPC: |
45d67817 | 1720 | case -EFAULT: |
f65c9168 PZ |
1721 | ret = VM_FAULT_SIGBUS; |
1722 | break; | |
de151cf6 | 1723 | default: |
a7c2e1aa | 1724 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1725 | ret = VM_FAULT_SIGBUS; |
1726 | break; | |
de151cf6 | 1727 | } |
f65c9168 PZ |
1728 | |
1729 | intel_runtime_pm_put(dev_priv); | |
1730 | return ret; | |
de151cf6 JB |
1731 | } |
1732 | ||
901782b2 CW |
1733 | /** |
1734 | * i915_gem_release_mmap - remove physical page mappings | |
1735 | * @obj: obj in question | |
1736 | * | |
af901ca1 | 1737 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1738 | * relinquish ownership of the pages back to the system. |
1739 | * | |
1740 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1741 | * object through the GTT and then lose the fence register due to | |
1742 | * resource pressure. Similarly if the object has been moved out of the | |
1743 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1744 | * mapping will then trigger a page fault on the next user access, allowing | |
1745 | * fixup by i915_gem_fault(). | |
1746 | */ | |
d05ca301 | 1747 | void |
05394f39 | 1748 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1749 | { |
6299f992 CW |
1750 | if (!obj->fault_mappable) |
1751 | return; | |
901782b2 | 1752 | |
6796cb16 DH |
1753 | drm_vma_node_unmap(&obj->base.vma_node, |
1754 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1755 | obj->fault_mappable = false; |
901782b2 CW |
1756 | } |
1757 | ||
eedd10f4 CW |
1758 | void |
1759 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1760 | { | |
1761 | struct drm_i915_gem_object *obj; | |
1762 | ||
1763 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1764 | i915_gem_release_mmap(obj); | |
1765 | } | |
1766 | ||
0fa87796 | 1767 | uint32_t |
e28f8711 | 1768 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1769 | { |
e28f8711 | 1770 | uint32_t gtt_size; |
92b88aeb CW |
1771 | |
1772 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1773 | tiling_mode == I915_TILING_NONE) |
1774 | return size; | |
92b88aeb CW |
1775 | |
1776 | /* Previous chips need a power-of-two fence region when tiling */ | |
1777 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1778 | gtt_size = 1024*1024; |
92b88aeb | 1779 | else |
e28f8711 | 1780 | gtt_size = 512*1024; |
92b88aeb | 1781 | |
e28f8711 CW |
1782 | while (gtt_size < size) |
1783 | gtt_size <<= 1; | |
92b88aeb | 1784 | |
e28f8711 | 1785 | return gtt_size; |
92b88aeb CW |
1786 | } |
1787 | ||
de151cf6 JB |
1788 | /** |
1789 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1790 | * @obj: object to check | |
1791 | * | |
1792 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1793 | * potential fence register mapping. |
de151cf6 | 1794 | */ |
d865110c ID |
1795 | uint32_t |
1796 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1797 | int tiling_mode, bool fenced) | |
de151cf6 | 1798 | { |
de151cf6 JB |
1799 | /* |
1800 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1801 | * if a fence register is needed for the object. | |
1802 | */ | |
d865110c | 1803 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1804 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1805 | return 4096; |
1806 | ||
a00b10c3 CW |
1807 | /* |
1808 | * Previous chips need to be aligned to the size of the smallest | |
1809 | * fence register that can contain the object. | |
1810 | */ | |
e28f8711 | 1811 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1812 | } |
1813 | ||
d8cb5086 CW |
1814 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1815 | { | |
1816 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1817 | int ret; | |
1818 | ||
0de23977 | 1819 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1820 | return 0; |
1821 | ||
da494d7c DV |
1822 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1823 | ||
d8cb5086 CW |
1824 | ret = drm_gem_create_mmap_offset(&obj->base); |
1825 | if (ret != -ENOSPC) | |
da494d7c | 1826 | goto out; |
d8cb5086 CW |
1827 | |
1828 | /* Badly fragmented mmap space? The only way we can recover | |
1829 | * space is by destroying unwanted objects. We can't randomly release | |
1830 | * mmap_offsets as userspace expects them to be persistent for the | |
1831 | * lifetime of the objects. The closest we can is to release the | |
1832 | * offsets on purgeable objects by truncating it and marking it purged, | |
1833 | * which prevents userspace from ever using that object again. | |
1834 | */ | |
21ab4e74 CW |
1835 | i915_gem_shrink(dev_priv, |
1836 | obj->base.size >> PAGE_SHIFT, | |
1837 | I915_SHRINK_BOUND | | |
1838 | I915_SHRINK_UNBOUND | | |
1839 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1840 | ret = drm_gem_create_mmap_offset(&obj->base); |
1841 | if (ret != -ENOSPC) | |
da494d7c | 1842 | goto out; |
d8cb5086 CW |
1843 | |
1844 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1845 | ret = drm_gem_create_mmap_offset(&obj->base); |
1846 | out: | |
1847 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1848 | ||
1849 | return ret; | |
d8cb5086 CW |
1850 | } |
1851 | ||
1852 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1853 | { | |
d8cb5086 CW |
1854 | drm_gem_free_mmap_offset(&obj->base); |
1855 | } | |
1856 | ||
de151cf6 | 1857 | int |
ff72145b DA |
1858 | i915_gem_mmap_gtt(struct drm_file *file, |
1859 | struct drm_device *dev, | |
1860 | uint32_t handle, | |
1861 | uint64_t *offset) | |
de151cf6 | 1862 | { |
da761a6e | 1863 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1864 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1865 | int ret; |
1866 | ||
76c1dec1 | 1867 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1868 | if (ret) |
76c1dec1 | 1869 | return ret; |
de151cf6 | 1870 | |
ff72145b | 1871 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1872 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1873 | ret = -ENOENT; |
1874 | goto unlock; | |
1875 | } | |
de151cf6 | 1876 | |
5d4545ae | 1877 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1878 | ret = -E2BIG; |
ff56b0bc | 1879 | goto out; |
da761a6e CW |
1880 | } |
1881 | ||
05394f39 | 1882 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1883 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1884 | ret = -EFAULT; |
1d7cfea1 | 1885 | goto out; |
ab18282d CW |
1886 | } |
1887 | ||
d8cb5086 CW |
1888 | ret = i915_gem_object_create_mmap_offset(obj); |
1889 | if (ret) | |
1890 | goto out; | |
de151cf6 | 1891 | |
0de23977 | 1892 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1893 | |
1d7cfea1 | 1894 | out: |
05394f39 | 1895 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1896 | unlock: |
de151cf6 | 1897 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1898 | return ret; |
de151cf6 JB |
1899 | } |
1900 | ||
ff72145b DA |
1901 | /** |
1902 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1903 | * @dev: DRM device | |
1904 | * @data: GTT mapping ioctl data | |
1905 | * @file: GEM object info | |
1906 | * | |
1907 | * Simply returns the fake offset to userspace so it can mmap it. | |
1908 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1909 | * up so we can get faults in the handler above. | |
1910 | * | |
1911 | * The fault handler will take care of binding the object into the GTT | |
1912 | * (since it may have been evicted to make room for something), allocating | |
1913 | * a fence register, and mapping the appropriate aperture address into | |
1914 | * userspace. | |
1915 | */ | |
1916 | int | |
1917 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1918 | struct drm_file *file) | |
1919 | { | |
1920 | struct drm_i915_gem_mmap_gtt *args = data; | |
1921 | ||
ff72145b DA |
1922 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1923 | } | |
1924 | ||
5537252b CW |
1925 | static inline int |
1926 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1927 | { | |
1928 | return obj->madv == I915_MADV_DONTNEED; | |
1929 | } | |
1930 | ||
225067ee DV |
1931 | /* Immediately discard the backing storage */ |
1932 | static void | |
1933 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1934 | { |
4d6294bf | 1935 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1936 | |
4d6294bf CW |
1937 | if (obj->base.filp == NULL) |
1938 | return; | |
e5281ccd | 1939 | |
225067ee DV |
1940 | /* Our goal here is to return as much of the memory as |
1941 | * is possible back to the system as we are called from OOM. | |
1942 | * To do this we must instruct the shmfs to drop all of its | |
1943 | * backing pages, *now*. | |
1944 | */ | |
5537252b | 1945 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1946 | obj->madv = __I915_MADV_PURGED; |
1947 | } | |
e5281ccd | 1948 | |
5537252b CW |
1949 | /* Try to discard unwanted pages */ |
1950 | static void | |
1951 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1952 | { |
5537252b CW |
1953 | struct address_space *mapping; |
1954 | ||
1955 | switch (obj->madv) { | |
1956 | case I915_MADV_DONTNEED: | |
1957 | i915_gem_object_truncate(obj); | |
1958 | case __I915_MADV_PURGED: | |
1959 | return; | |
1960 | } | |
1961 | ||
1962 | if (obj->base.filp == NULL) | |
1963 | return; | |
1964 | ||
1965 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1966 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1967 | } |
1968 | ||
5cdf5881 | 1969 | static void |
05394f39 | 1970 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1971 | { |
90797e6d ID |
1972 | struct sg_page_iter sg_iter; |
1973 | int ret; | |
1286ff73 | 1974 | |
05394f39 | 1975 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1976 | |
6c085a72 CW |
1977 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1978 | if (ret) { | |
1979 | /* In the event of a disaster, abandon all caches and | |
1980 | * hope for the best. | |
1981 | */ | |
1982 | WARN_ON(ret != -EIO); | |
2c22569b | 1983 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1984 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1985 | } | |
1986 | ||
6dacfd2f | 1987 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1988 | i915_gem_object_save_bit_17_swizzle(obj); |
1989 | ||
05394f39 CW |
1990 | if (obj->madv == I915_MADV_DONTNEED) |
1991 | obj->dirty = 0; | |
3ef94daa | 1992 | |
90797e6d | 1993 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1994 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1995 | |
05394f39 | 1996 | if (obj->dirty) |
9da3da66 | 1997 | set_page_dirty(page); |
3ef94daa | 1998 | |
05394f39 | 1999 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2000 | mark_page_accessed(page); |
3ef94daa | 2001 | |
9da3da66 | 2002 | page_cache_release(page); |
3ef94daa | 2003 | } |
05394f39 | 2004 | obj->dirty = 0; |
673a394b | 2005 | |
9da3da66 CW |
2006 | sg_free_table(obj->pages); |
2007 | kfree(obj->pages); | |
37e680a1 | 2008 | } |
6c085a72 | 2009 | |
dd624afd | 2010 | int |
37e680a1 CW |
2011 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2012 | { | |
2013 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2014 | ||
2f745ad3 | 2015 | if (obj->pages == NULL) |
37e680a1 CW |
2016 | return 0; |
2017 | ||
a5570178 CW |
2018 | if (obj->pages_pin_count) |
2019 | return -EBUSY; | |
2020 | ||
9843877d | 2021 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2022 | |
a2165e31 CW |
2023 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2024 | * array, hence protect them from being reaped by removing them from gtt | |
2025 | * lists early. */ | |
35c20a60 | 2026 | list_del(&obj->global_list); |
a2165e31 | 2027 | |
37e680a1 | 2028 | ops->put_pages(obj); |
05394f39 | 2029 | obj->pages = NULL; |
37e680a1 | 2030 | |
5537252b | 2031 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2032 | |
2033 | return 0; | |
2034 | } | |
2035 | ||
21ab4e74 CW |
2036 | unsigned long |
2037 | i915_gem_shrink(struct drm_i915_private *dev_priv, | |
2038 | long target, unsigned flags) | |
6c085a72 | 2039 | { |
60a53727 CW |
2040 | const struct { |
2041 | struct list_head *list; | |
2042 | unsigned int bit; | |
2043 | } phases[] = { | |
2044 | { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND }, | |
2045 | { &dev_priv->mm.bound_list, I915_SHRINK_BOUND }, | |
2046 | { NULL, 0 }, | |
2047 | }, *phase; | |
d9973b43 | 2048 | unsigned long count = 0; |
6c085a72 | 2049 | |
57094f82 | 2050 | /* |
c8725f3d | 2051 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
2052 | * (due to retiring requests) we have to strictly process only |
2053 | * one element of the list at the time, and recheck the list | |
2054 | * on every iteration. | |
c8725f3d CW |
2055 | * |
2056 | * In particular, we must hold a reference whilst removing the | |
2057 | * object as we may end up waiting for and/or retiring the objects. | |
2058 | * This might release the final reference (held by the active list) | |
2059 | * and result in the object being freed from under us. This is | |
2060 | * similar to the precautions the eviction code must take whilst | |
2061 | * removing objects. | |
2062 | * | |
2063 | * Also note that although these lists do not hold a reference to | |
2064 | * the object we can safely grab one here: The final object | |
2065 | * unreferencing and the bound_list are both protected by the | |
2066 | * dev->struct_mutex and so we won't ever be able to observe an | |
2067 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 2068 | */ |
60a53727 | 2069 | for (phase = phases; phase->list; phase++) { |
21ab4e74 | 2070 | struct list_head still_in_list; |
c8725f3d | 2071 | |
60a53727 CW |
2072 | if ((flags & phase->bit) == 0) |
2073 | continue; | |
80dcfdbd | 2074 | |
21ab4e74 | 2075 | INIT_LIST_HEAD(&still_in_list); |
60a53727 | 2076 | while (count < target && !list_empty(phase->list)) { |
21ab4e74 CW |
2077 | struct drm_i915_gem_object *obj; |
2078 | struct i915_vma *vma, *v; | |
57094f82 | 2079 | |
60a53727 | 2080 | obj = list_first_entry(phase->list, |
21ab4e74 CW |
2081 | typeof(*obj), global_list); |
2082 | list_move_tail(&obj->global_list, &still_in_list); | |
80dcfdbd | 2083 | |
60a53727 CW |
2084 | if (flags & I915_SHRINK_PURGEABLE && |
2085 | !i915_gem_object_is_purgeable(obj)) | |
21ab4e74 | 2086 | continue; |
57094f82 | 2087 | |
21ab4e74 | 2088 | drm_gem_object_reference(&obj->base); |
80dcfdbd | 2089 | |
60a53727 CW |
2090 | /* For the unbound phase, this should be a no-op! */ |
2091 | list_for_each_entry_safe(vma, v, | |
2092 | &obj->vma_list, vma_link) | |
21ab4e74 CW |
2093 | if (i915_vma_unbind(vma)) |
2094 | break; | |
57094f82 | 2095 | |
21ab4e74 CW |
2096 | if (i915_gem_object_put_pages(obj) == 0) |
2097 | count += obj->base.size >> PAGE_SHIFT; | |
2098 | ||
2099 | drm_gem_object_unreference(&obj->base); | |
2100 | } | |
60a53727 | 2101 | list_splice(&still_in_list, phase->list); |
6c085a72 CW |
2102 | } |
2103 | ||
2104 | return count; | |
2105 | } | |
2106 | ||
d9973b43 | 2107 | static unsigned long |
6c085a72 CW |
2108 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
2109 | { | |
6c085a72 | 2110 | i915_gem_evict_everything(dev_priv->dev); |
21ab4e74 CW |
2111 | return i915_gem_shrink(dev_priv, LONG_MAX, |
2112 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); | |
225067ee DV |
2113 | } |
2114 | ||
37e680a1 | 2115 | static int |
6c085a72 | 2116 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2117 | { |
6c085a72 | 2118 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2119 | int page_count, i; |
2120 | struct address_space *mapping; | |
9da3da66 CW |
2121 | struct sg_table *st; |
2122 | struct scatterlist *sg; | |
90797e6d | 2123 | struct sg_page_iter sg_iter; |
e5281ccd | 2124 | struct page *page; |
90797e6d | 2125 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2126 | gfp_t gfp; |
e5281ccd | 2127 | |
6c085a72 CW |
2128 | /* Assert that the object is not currently in any GPU domain. As it |
2129 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2130 | * a GPU cache | |
2131 | */ | |
2132 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2133 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2134 | ||
9da3da66 CW |
2135 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2136 | if (st == NULL) | |
2137 | return -ENOMEM; | |
2138 | ||
05394f39 | 2139 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2140 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2141 | kfree(st); |
e5281ccd | 2142 | return -ENOMEM; |
9da3da66 | 2143 | } |
e5281ccd | 2144 | |
9da3da66 CW |
2145 | /* Get the list of pages out of our struct file. They'll be pinned |
2146 | * at this point until we release them. | |
2147 | * | |
2148 | * Fail silently without starting the shrinker | |
2149 | */ | |
496ad9aa | 2150 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2151 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2152 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2153 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2154 | sg = st->sgl; |
2155 | st->nents = 0; | |
2156 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2157 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2158 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2159 | i915_gem_shrink(dev_priv, |
2160 | page_count, | |
2161 | I915_SHRINK_BOUND | | |
2162 | I915_SHRINK_UNBOUND | | |
2163 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2164 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2165 | } | |
2166 | if (IS_ERR(page)) { | |
2167 | /* We've tried hard to allocate the memory by reaping | |
2168 | * our own buffer, now let the real VM do its job and | |
2169 | * go down in flames if truly OOM. | |
2170 | */ | |
6c085a72 | 2171 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2172 | page = shmem_read_mapping_page(mapping, i); |
6c085a72 CW |
2173 | if (IS_ERR(page)) |
2174 | goto err_pages; | |
6c085a72 | 2175 | } |
426729dc KRW |
2176 | #ifdef CONFIG_SWIOTLB |
2177 | if (swiotlb_nr_tbl()) { | |
2178 | st->nents++; | |
2179 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2180 | sg = sg_next(sg); | |
2181 | continue; | |
2182 | } | |
2183 | #endif | |
90797e6d ID |
2184 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2185 | if (i) | |
2186 | sg = sg_next(sg); | |
2187 | st->nents++; | |
2188 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2189 | } else { | |
2190 | sg->length += PAGE_SIZE; | |
2191 | } | |
2192 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2193 | |
2194 | /* Check that the i965g/gm workaround works. */ | |
2195 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2196 | } |
426729dc KRW |
2197 | #ifdef CONFIG_SWIOTLB |
2198 | if (!swiotlb_nr_tbl()) | |
2199 | #endif | |
2200 | sg_mark_end(sg); | |
74ce6b6c CW |
2201 | obj->pages = st; |
2202 | ||
6dacfd2f | 2203 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2204 | i915_gem_object_do_bit_17_swizzle(obj); |
2205 | ||
2206 | return 0; | |
2207 | ||
2208 | err_pages: | |
90797e6d ID |
2209 | sg_mark_end(sg); |
2210 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2211 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2212 | sg_free_table(st); |
2213 | kfree(st); | |
0820baf3 CW |
2214 | |
2215 | /* shmemfs first checks if there is enough memory to allocate the page | |
2216 | * and reports ENOSPC should there be insufficient, along with the usual | |
2217 | * ENOMEM for a genuine allocation failure. | |
2218 | * | |
2219 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2220 | * space and so want to translate the error from shmemfs back to our | |
2221 | * usual understanding of ENOMEM. | |
2222 | */ | |
2223 | if (PTR_ERR(page) == -ENOSPC) | |
2224 | return -ENOMEM; | |
2225 | else | |
2226 | return PTR_ERR(page); | |
673a394b EA |
2227 | } |
2228 | ||
37e680a1 CW |
2229 | /* Ensure that the associated pages are gathered from the backing storage |
2230 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2231 | * multiple times before they are released by a single call to | |
2232 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2233 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2234 | * or as the object is itself released. | |
2235 | */ | |
2236 | int | |
2237 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2238 | { | |
2239 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2240 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2241 | int ret; | |
2242 | ||
2f745ad3 | 2243 | if (obj->pages) |
37e680a1 CW |
2244 | return 0; |
2245 | ||
43e28f09 | 2246 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2247 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2248 | return -EFAULT; |
43e28f09 CW |
2249 | } |
2250 | ||
a5570178 CW |
2251 | BUG_ON(obj->pages_pin_count); |
2252 | ||
37e680a1 CW |
2253 | ret = ops->get_pages(obj); |
2254 | if (ret) | |
2255 | return ret; | |
2256 | ||
35c20a60 | 2257 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2258 | return 0; |
673a394b EA |
2259 | } |
2260 | ||
e2d05a8b | 2261 | static void |
05394f39 | 2262 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2263 | struct intel_engine_cs *ring) |
673a394b | 2264 | { |
9d773091 | 2265 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 2266 | |
852835f3 | 2267 | BUG_ON(ring == NULL); |
02978ff5 CW |
2268 | if (obj->ring != ring && obj->last_write_seqno) { |
2269 | /* Keep the seqno relative to the current ring */ | |
2270 | obj->last_write_seqno = seqno; | |
2271 | } | |
05394f39 | 2272 | obj->ring = ring; |
673a394b EA |
2273 | |
2274 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2275 | if (!obj->active) { |
2276 | drm_gem_object_reference(&obj->base); | |
2277 | obj->active = 1; | |
673a394b | 2278 | } |
e35a41de | 2279 | |
05394f39 | 2280 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2281 | |
0201f1ec | 2282 | obj->last_read_seqno = seqno; |
caea7476 CW |
2283 | } |
2284 | ||
e2d05a8b | 2285 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2286 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2287 | { |
2288 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2289 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2290 | } | |
2291 | ||
caea7476 | 2292 | static void |
caea7476 | 2293 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2294 | { |
ca191b13 | 2295 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2296 | struct i915_address_space *vm; |
2297 | struct i915_vma *vma; | |
ce44b0ea | 2298 | |
65ce3027 | 2299 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2300 | BUG_ON(!obj->active); |
caea7476 | 2301 | |
feb822cf BW |
2302 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2303 | vma = i915_gem_obj_to_vma(obj, vm); | |
2304 | if (vma && !list_empty(&vma->mm_list)) | |
2305 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2306 | } | |
caea7476 | 2307 | |
f99d7069 DV |
2308 | intel_fb_obj_flush(obj, true); |
2309 | ||
65ce3027 | 2310 | list_del_init(&obj->ring_list); |
caea7476 CW |
2311 | obj->ring = NULL; |
2312 | ||
65ce3027 CW |
2313 | obj->last_read_seqno = 0; |
2314 | obj->last_write_seqno = 0; | |
2315 | obj->base.write_domain = 0; | |
2316 | ||
2317 | obj->last_fenced_seqno = 0; | |
caea7476 CW |
2318 | |
2319 | obj->active = 0; | |
2320 | drm_gem_object_unreference(&obj->base); | |
2321 | ||
2322 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2323 | } |
673a394b | 2324 | |
c8725f3d CW |
2325 | static void |
2326 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2327 | { | |
a4872ba6 | 2328 | struct intel_engine_cs *ring = obj->ring; |
c8725f3d CW |
2329 | |
2330 | if (ring == NULL) | |
2331 | return; | |
2332 | ||
2333 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
2334 | obj->last_read_seqno)) | |
2335 | i915_gem_object_move_to_inactive(obj); | |
2336 | } | |
2337 | ||
9d773091 | 2338 | static int |
fca26bb4 | 2339 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2340 | { |
9d773091 | 2341 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2342 | struct intel_engine_cs *ring; |
9d773091 | 2343 | int ret, i, j; |
53d227f2 | 2344 | |
107f27a5 | 2345 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2346 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2347 | ret = intel_ring_idle(ring); |
2348 | if (ret) | |
2349 | return ret; | |
9d773091 | 2350 | } |
9d773091 | 2351 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2352 | |
2353 | /* Finally reset hw state */ | |
9d773091 | 2354 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2355 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2356 | |
ebc348b2 BW |
2357 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2358 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2359 | } |
53d227f2 | 2360 | |
9d773091 | 2361 | return 0; |
53d227f2 DV |
2362 | } |
2363 | ||
fca26bb4 MK |
2364 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2365 | { | |
2366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2367 | int ret; | |
2368 | ||
2369 | if (seqno == 0) | |
2370 | return -EINVAL; | |
2371 | ||
2372 | /* HWS page needs to be set less than what we | |
2373 | * will inject to ring | |
2374 | */ | |
2375 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2376 | if (ret) | |
2377 | return ret; | |
2378 | ||
2379 | /* Carefully set the last_seqno value so that wrap | |
2380 | * detection still works | |
2381 | */ | |
2382 | dev_priv->next_seqno = seqno; | |
2383 | dev_priv->last_seqno = seqno - 1; | |
2384 | if (dev_priv->last_seqno == 0) | |
2385 | dev_priv->last_seqno--; | |
2386 | ||
2387 | return 0; | |
2388 | } | |
2389 | ||
9d773091 CW |
2390 | int |
2391 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2392 | { |
9d773091 CW |
2393 | struct drm_i915_private *dev_priv = dev->dev_private; |
2394 | ||
2395 | /* reserve 0 for non-seqno */ | |
2396 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2397 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2398 | if (ret) |
2399 | return ret; | |
53d227f2 | 2400 | |
9d773091 CW |
2401 | dev_priv->next_seqno = 1; |
2402 | } | |
53d227f2 | 2403 | |
f72b3435 | 2404 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2405 | return 0; |
53d227f2 DV |
2406 | } |
2407 | ||
a4872ba6 | 2408 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2409 | struct drm_file *file, |
7d736f4f | 2410 | struct drm_i915_gem_object *obj, |
0025c077 | 2411 | u32 *out_seqno) |
673a394b | 2412 | { |
3e31c6c0 | 2413 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2414 | struct drm_i915_gem_request *request; |
48e29f55 | 2415 | struct intel_ringbuffer *ringbuf; |
7d736f4f | 2416 | u32 request_ring_position, request_start; |
3cce469c CW |
2417 | int ret; |
2418 | ||
48e29f55 OM |
2419 | request = ring->preallocated_lazy_request; |
2420 | if (WARN_ON(request == NULL)) | |
2421 | return -ENOMEM; | |
2422 | ||
2423 | if (i915.enable_execlists) { | |
2424 | struct intel_context *ctx = request->ctx; | |
2425 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2426 | } else | |
2427 | ringbuf = ring->buffer; | |
2428 | ||
2429 | request_start = intel_ring_get_tail(ringbuf); | |
cc889e0f DV |
2430 | /* |
2431 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2432 | * after having emitted the batchbuffer command. Hence we need to fix | |
2433 | * things up similar to emitting the lazy request. The difference here | |
2434 | * is that the flush _must_ happen before the next request, no matter | |
2435 | * what. | |
2436 | */ | |
48e29f55 OM |
2437 | if (i915.enable_execlists) { |
2438 | ret = logical_ring_flush_all_caches(ringbuf); | |
2439 | if (ret) | |
2440 | return ret; | |
2441 | } else { | |
2442 | ret = intel_ring_flush_all_caches(ring); | |
2443 | if (ret) | |
2444 | return ret; | |
2445 | } | |
cc889e0f | 2446 | |
a71d8d94 CW |
2447 | /* Record the position of the start of the request so that |
2448 | * should we detect the updated seqno part-way through the | |
2449 | * GPU processing the request, we never over-estimate the | |
2450 | * position of the head. | |
2451 | */ | |
48e29f55 | 2452 | request_ring_position = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2453 | |
48e29f55 OM |
2454 | if (i915.enable_execlists) { |
2455 | ret = ring->emit_request(ringbuf); | |
2456 | if (ret) | |
2457 | return ret; | |
2458 | } else { | |
2459 | ret = ring->add_request(ring); | |
2460 | if (ret) | |
2461 | return ret; | |
2462 | } | |
673a394b | 2463 | |
9d773091 | 2464 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2465 | request->ring = ring; |
7d736f4f | 2466 | request->head = request_start; |
a71d8d94 | 2467 | request->tail = request_ring_position; |
7d736f4f MK |
2468 | |
2469 | /* Whilst this request exists, batch_obj will be on the | |
2470 | * active_list, and so will hold the active reference. Only when this | |
2471 | * request is retired will the the batch_obj be moved onto the | |
2472 | * inactive_list and lose its active reference. Hence we do not need | |
2473 | * to explicitly hold another reference here. | |
2474 | */ | |
9a7e0c2a | 2475 | request->batch_obj = obj; |
0e50e96b | 2476 | |
48e29f55 OM |
2477 | if (!i915.enable_execlists) { |
2478 | /* Hold a reference to the current context so that we can inspect | |
2479 | * it later in case a hangcheck error event fires. | |
2480 | */ | |
2481 | request->ctx = ring->last_context; | |
2482 | if (request->ctx) | |
2483 | i915_gem_context_reference(request->ctx); | |
2484 | } | |
0e50e96b | 2485 | |
673a394b | 2486 | request->emitted_jiffies = jiffies; |
852835f3 | 2487 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2488 | request->file_priv = NULL; |
852835f3 | 2489 | |
db53a302 CW |
2490 | if (file) { |
2491 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2492 | ||
1c25595f | 2493 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2494 | request->file_priv = file_priv; |
b962442e | 2495 | list_add_tail(&request->client_list, |
f787a5f5 | 2496 | &file_priv->mm.request_list); |
1c25595f | 2497 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2498 | } |
673a394b | 2499 | |
9d773091 | 2500 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2501 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2502 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2503 | |
db1b76ca | 2504 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2505 | i915_queue_hangcheck(ring->dev); |
2506 | ||
f62a0076 CW |
2507 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2508 | queue_delayed_work(dev_priv->wq, | |
2509 | &dev_priv->mm.retire_work, | |
2510 | round_jiffies_up_relative(HZ)); | |
2511 | intel_mark_busy(dev_priv->dev); | |
f65d9421 | 2512 | } |
cc889e0f | 2513 | |
acb868d3 | 2514 | if (out_seqno) |
9d773091 | 2515 | *out_seqno = request->seqno; |
3cce469c | 2516 | return 0; |
673a394b EA |
2517 | } |
2518 | ||
f787a5f5 CW |
2519 | static inline void |
2520 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2521 | { |
1c25595f | 2522 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2523 | |
1c25595f CW |
2524 | if (!file_priv) |
2525 | return; | |
1c5d22f7 | 2526 | |
1c25595f | 2527 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2528 | list_del(&request->client_list); |
2529 | request->file_priv = NULL; | |
1c25595f | 2530 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2531 | } |
673a394b | 2532 | |
939fd762 | 2533 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2534 | const struct intel_context *ctx) |
be62acb4 | 2535 | { |
44e2c070 | 2536 | unsigned long elapsed; |
be62acb4 | 2537 | |
44e2c070 MK |
2538 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2539 | ||
2540 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2541 | return true; |
2542 | ||
2543 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2544 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2545 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2546 | return true; |
88b4aa87 MK |
2547 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2548 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2549 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2550 | return true; |
3fac8978 | 2551 | } |
be62acb4 MK |
2552 | } |
2553 | ||
2554 | return false; | |
2555 | } | |
2556 | ||
939fd762 | 2557 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2558 | struct intel_context *ctx, |
b6b0fac0 | 2559 | const bool guilty) |
aa60c664 | 2560 | { |
44e2c070 MK |
2561 | struct i915_ctx_hang_stats *hs; |
2562 | ||
2563 | if (WARN_ON(!ctx)) | |
2564 | return; | |
aa60c664 | 2565 | |
44e2c070 MK |
2566 | hs = &ctx->hang_stats; |
2567 | ||
2568 | if (guilty) { | |
939fd762 | 2569 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2570 | hs->batch_active++; |
2571 | hs->guilty_ts = get_seconds(); | |
2572 | } else { | |
2573 | hs->batch_pending++; | |
aa60c664 MK |
2574 | } |
2575 | } | |
2576 | ||
0e50e96b MK |
2577 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2578 | { | |
dcb4c12a OM |
2579 | struct intel_context *ctx = request->ctx; |
2580 | ||
0e50e96b MK |
2581 | list_del(&request->list); |
2582 | i915_gem_request_remove_from_client(request); | |
2583 | ||
dcb4c12a OM |
2584 | if (i915.enable_execlists && ctx) { |
2585 | struct intel_engine_cs *ring = request->ring; | |
0e50e96b | 2586 | |
dcb4c12a OM |
2587 | if (ctx != ring->default_context) |
2588 | intel_lr_context_unpin(ring, ctx); | |
2589 | i915_gem_context_unreference(ctx); | |
2590 | } | |
0e50e96b MK |
2591 | kfree(request); |
2592 | } | |
2593 | ||
8d9fc7fd | 2594 | struct drm_i915_gem_request * |
a4872ba6 | 2595 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2596 | { |
4db080f9 | 2597 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2598 | u32 completed_seqno; |
2599 | ||
2600 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2601 | |
2602 | list_for_each_entry(request, &ring->request_list, list) { | |
2603 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2604 | continue; | |
aa60c664 | 2605 | |
b6b0fac0 | 2606 | return request; |
4db080f9 | 2607 | } |
b6b0fac0 MK |
2608 | |
2609 | return NULL; | |
2610 | } | |
2611 | ||
2612 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2613 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2614 | { |
2615 | struct drm_i915_gem_request *request; | |
2616 | bool ring_hung; | |
2617 | ||
8d9fc7fd | 2618 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2619 | |
2620 | if (request == NULL) | |
2621 | return; | |
2622 | ||
2623 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2624 | ||
939fd762 | 2625 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2626 | |
2627 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2628 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2629 | } |
aa60c664 | 2630 | |
4db080f9 | 2631 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2632 | struct intel_engine_cs *ring) |
4db080f9 | 2633 | { |
dfaae392 | 2634 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2635 | struct drm_i915_gem_object *obj; |
9375e446 | 2636 | |
05394f39 CW |
2637 | obj = list_first_entry(&ring->active_list, |
2638 | struct drm_i915_gem_object, | |
2639 | ring_list); | |
9375e446 | 2640 | |
05394f39 | 2641 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2642 | } |
1d62beea | 2643 | |
dcb4c12a OM |
2644 | /* |
2645 | * Clear the execlists queue up before freeing the requests, as those | |
2646 | * are the ones that keep the context and ringbuffer backing objects | |
2647 | * pinned in place. | |
2648 | */ | |
2649 | while (!list_empty(&ring->execlist_queue)) { | |
2650 | struct intel_ctx_submit_request *submit_req; | |
2651 | ||
2652 | submit_req = list_first_entry(&ring->execlist_queue, | |
2653 | struct intel_ctx_submit_request, | |
2654 | execlist_link); | |
2655 | list_del(&submit_req->execlist_link); | |
2656 | intel_runtime_pm_put(dev_priv); | |
2657 | i915_gem_context_unreference(submit_req->ctx); | |
2658 | kfree(submit_req); | |
2659 | } | |
2660 | ||
1d62beea BW |
2661 | /* |
2662 | * We must free the requests after all the corresponding objects have | |
2663 | * been moved off active lists. Which is the same order as the normal | |
2664 | * retire_requests function does. This is important if object hold | |
2665 | * implicit references on things like e.g. ppgtt address spaces through | |
2666 | * the request. | |
2667 | */ | |
2668 | while (!list_empty(&ring->request_list)) { | |
2669 | struct drm_i915_gem_request *request; | |
2670 | ||
2671 | request = list_first_entry(&ring->request_list, | |
2672 | struct drm_i915_gem_request, | |
2673 | list); | |
2674 | ||
2675 | i915_gem_free_request(request); | |
2676 | } | |
e3efda49 CW |
2677 | |
2678 | /* These may not have been flush before the reset, do so now */ | |
2679 | kfree(ring->preallocated_lazy_request); | |
2680 | ring->preallocated_lazy_request = NULL; | |
2681 | ring->outstanding_lazy_seqno = 0; | |
673a394b EA |
2682 | } |
2683 | ||
19b2dbde | 2684 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2685 | { |
2686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2687 | int i; | |
2688 | ||
4b9de737 | 2689 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2690 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2691 | |
94a335db DV |
2692 | /* |
2693 | * Commit delayed tiling changes if we have an object still | |
2694 | * attached to the fence, otherwise just clear the fence. | |
2695 | */ | |
2696 | if (reg->obj) { | |
2697 | i915_gem_object_update_fence(reg->obj, reg, | |
2698 | reg->obj->tiling_mode); | |
2699 | } else { | |
2700 | i915_gem_write_fence(dev, i, NULL); | |
2701 | } | |
312817a3 CW |
2702 | } |
2703 | } | |
2704 | ||
069efc1d | 2705 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2706 | { |
77f01230 | 2707 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2708 | struct intel_engine_cs *ring; |
1ec14ad3 | 2709 | int i; |
673a394b | 2710 | |
4db080f9 CW |
2711 | /* |
2712 | * Before we free the objects from the requests, we need to inspect | |
2713 | * them for finding the guilty party. As the requests only borrow | |
2714 | * their reference to the objects, the inspection must be done first. | |
2715 | */ | |
2716 | for_each_ring(ring, dev_priv, i) | |
2717 | i915_gem_reset_ring_status(dev_priv, ring); | |
2718 | ||
b4519513 | 2719 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2720 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2721 | |
acce9ffa BW |
2722 | i915_gem_context_reset(dev); |
2723 | ||
19b2dbde | 2724 | i915_gem_restore_fences(dev); |
673a394b EA |
2725 | } |
2726 | ||
2727 | /** | |
2728 | * This function clears the request list as sequence numbers are passed. | |
2729 | */ | |
1cf0ba14 | 2730 | void |
a4872ba6 | 2731 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2732 | { |
673a394b EA |
2733 | uint32_t seqno; |
2734 | ||
db53a302 | 2735 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2736 | return; |
2737 | ||
db53a302 | 2738 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2739 | |
b2eadbc8 | 2740 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2741 | |
e9103038 CW |
2742 | /* Move any buffers on the active list that are no longer referenced |
2743 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2744 | * before we free the context associated with the requests. | |
2745 | */ | |
2746 | while (!list_empty(&ring->active_list)) { | |
2747 | struct drm_i915_gem_object *obj; | |
2748 | ||
2749 | obj = list_first_entry(&ring->active_list, | |
2750 | struct drm_i915_gem_object, | |
2751 | ring_list); | |
2752 | ||
2753 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) | |
2754 | break; | |
2755 | ||
2756 | i915_gem_object_move_to_inactive(obj); | |
2757 | } | |
2758 | ||
2759 | ||
852835f3 | 2760 | while (!list_empty(&ring->request_list)) { |
673a394b | 2761 | struct drm_i915_gem_request *request; |
48e29f55 | 2762 | struct intel_ringbuffer *ringbuf; |
673a394b | 2763 | |
852835f3 | 2764 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2765 | struct drm_i915_gem_request, |
2766 | list); | |
673a394b | 2767 | |
dfaae392 | 2768 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2769 | break; |
2770 | ||
db53a302 | 2771 | trace_i915_gem_request_retire(ring, request->seqno); |
48e29f55 OM |
2772 | |
2773 | /* This is one of the few common intersection points | |
2774 | * between legacy ringbuffer submission and execlists: | |
2775 | * we need to tell them apart in order to find the correct | |
2776 | * ringbuffer to which the request belongs to. | |
2777 | */ | |
2778 | if (i915.enable_execlists) { | |
2779 | struct intel_context *ctx = request->ctx; | |
2780 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2781 | } else | |
2782 | ringbuf = ring->buffer; | |
2783 | ||
a71d8d94 CW |
2784 | /* We know the GPU must have read the request to have |
2785 | * sent us the seqno + interrupt, so use the position | |
2786 | * of tail of the request to update the last known position | |
2787 | * of the GPU head. | |
2788 | */ | |
48e29f55 | 2789 | ringbuf->last_retired_head = request->tail; |
b84d5f0c | 2790 | |
0e50e96b | 2791 | i915_gem_free_request(request); |
b84d5f0c | 2792 | } |
673a394b | 2793 | |
db53a302 CW |
2794 | if (unlikely(ring->trace_irq_seqno && |
2795 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2796 | ring->irq_put(ring); |
db53a302 | 2797 | ring->trace_irq_seqno = 0; |
9d34e5db | 2798 | } |
23bc5982 | 2799 | |
db53a302 | 2800 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2801 | } |
2802 | ||
b29c19b6 | 2803 | bool |
b09a1fec CW |
2804 | i915_gem_retire_requests(struct drm_device *dev) |
2805 | { | |
3e31c6c0 | 2806 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2807 | struct intel_engine_cs *ring; |
b29c19b6 | 2808 | bool idle = true; |
1ec14ad3 | 2809 | int i; |
b09a1fec | 2810 | |
b29c19b6 | 2811 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2812 | i915_gem_retire_requests_ring(ring); |
b29c19b6 | 2813 | idle &= list_empty(&ring->request_list); |
c86ee3a9 TD |
2814 | if (i915.enable_execlists) { |
2815 | unsigned long flags; | |
2816 | ||
2817 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2818 | idle &= list_empty(&ring->execlist_queue); | |
2819 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
2820 | ||
2821 | intel_execlists_retire_requests(ring); | |
2822 | } | |
b29c19b6 CW |
2823 | } |
2824 | ||
2825 | if (idle) | |
2826 | mod_delayed_work(dev_priv->wq, | |
2827 | &dev_priv->mm.idle_work, | |
2828 | msecs_to_jiffies(100)); | |
2829 | ||
2830 | return idle; | |
b09a1fec CW |
2831 | } |
2832 | ||
75ef9da2 | 2833 | static void |
673a394b EA |
2834 | i915_gem_retire_work_handler(struct work_struct *work) |
2835 | { | |
b29c19b6 CW |
2836 | struct drm_i915_private *dev_priv = |
2837 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2838 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2839 | bool idle; |
673a394b | 2840 | |
891b48cf | 2841 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2842 | idle = false; |
2843 | if (mutex_trylock(&dev->struct_mutex)) { | |
2844 | idle = i915_gem_retire_requests(dev); | |
2845 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2846 | } |
b29c19b6 | 2847 | if (!idle) |
bcb45086 CW |
2848 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2849 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2850 | } |
0a58705b | 2851 | |
b29c19b6 CW |
2852 | static void |
2853 | i915_gem_idle_work_handler(struct work_struct *work) | |
2854 | { | |
2855 | struct drm_i915_private *dev_priv = | |
2856 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2857 | ||
2858 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2859 | } |
2860 | ||
30dfebf3 DV |
2861 | /** |
2862 | * Ensures that an object will eventually get non-busy by flushing any required | |
2863 | * write domains, emitting any outstanding lazy request and retiring and | |
2864 | * completed requests. | |
2865 | */ | |
2866 | static int | |
2867 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2868 | { | |
2869 | int ret; | |
2870 | ||
2871 | if (obj->active) { | |
0201f1ec | 2872 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2873 | if (ret) |
2874 | return ret; | |
2875 | ||
30dfebf3 DV |
2876 | i915_gem_retire_requests_ring(obj->ring); |
2877 | } | |
2878 | ||
2879 | return 0; | |
2880 | } | |
2881 | ||
23ba4fd0 BW |
2882 | /** |
2883 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2884 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2885 | * | |
2886 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2887 | * the timeout parameter. | |
2888 | * -ETIME: object is still busy after timeout | |
2889 | * -ERESTARTSYS: signal interrupted the wait | |
2890 | * -ENONENT: object doesn't exist | |
2891 | * Also possible, but rare: | |
2892 | * -EAGAIN: GPU wedged | |
2893 | * -ENOMEM: damn | |
2894 | * -ENODEV: Internal IRQ fail | |
2895 | * -E?: The add request failed | |
2896 | * | |
2897 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2898 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2899 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2900 | * without holding struct_mutex the object may become re-busied before this | |
2901 | * function completes. A similar but shorter * race condition exists in the busy | |
2902 | * ioctl | |
2903 | */ | |
2904 | int | |
2905 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2906 | { | |
3e31c6c0 | 2907 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2908 | struct drm_i915_gem_wait *args = data; |
2909 | struct drm_i915_gem_object *obj; | |
a4872ba6 | 2910 | struct intel_engine_cs *ring = NULL; |
f69061be | 2911 | unsigned reset_counter; |
23ba4fd0 BW |
2912 | u32 seqno = 0; |
2913 | int ret = 0; | |
2914 | ||
11b5d511 DV |
2915 | if (args->flags != 0) |
2916 | return -EINVAL; | |
2917 | ||
23ba4fd0 BW |
2918 | ret = i915_mutex_lock_interruptible(dev); |
2919 | if (ret) | |
2920 | return ret; | |
2921 | ||
2922 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2923 | if (&obj->base == NULL) { | |
2924 | mutex_unlock(&dev->struct_mutex); | |
2925 | return -ENOENT; | |
2926 | } | |
2927 | ||
30dfebf3 DV |
2928 | /* Need to make sure the object gets inactive eventually. */ |
2929 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2930 | if (ret) |
2931 | goto out; | |
2932 | ||
2933 | if (obj->active) { | |
0201f1ec | 2934 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2935 | ring = obj->ring; |
2936 | } | |
2937 | ||
2938 | if (seqno == 0) | |
2939 | goto out; | |
2940 | ||
23ba4fd0 | 2941 | /* Do this after OLR check to make sure we make forward progress polling |
5ed0bdf2 | 2942 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
23ba4fd0 | 2943 | */ |
5ed0bdf2 | 2944 | if (args->timeout_ns <= 0) { |
23ba4fd0 BW |
2945 | ret = -ETIME; |
2946 | goto out; | |
2947 | } | |
2948 | ||
2949 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2950 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2951 | mutex_unlock(&dev->struct_mutex); |
2952 | ||
16e9a21f ACO |
2953 | return __i915_wait_seqno(ring, seqno, reset_counter, true, |
2954 | &args->timeout_ns, file->driver_priv); | |
23ba4fd0 BW |
2955 | |
2956 | out: | |
2957 | drm_gem_object_unreference(&obj->base); | |
2958 | mutex_unlock(&dev->struct_mutex); | |
2959 | return ret; | |
2960 | } | |
2961 | ||
5816d648 BW |
2962 | /** |
2963 | * i915_gem_object_sync - sync an object to a ring. | |
2964 | * | |
2965 | * @obj: object which may be in use on another ring. | |
2966 | * @to: ring we wish to use the object on. May be NULL. | |
2967 | * | |
2968 | * This code is meant to abstract object synchronization with the GPU. | |
2969 | * Calling with NULL implies synchronizing the object with the CPU | |
2970 | * rather than a particular GPU ring. | |
2971 | * | |
2972 | * Returns 0 if successful, else propagates up the lower layer error. | |
2973 | */ | |
2911a35b BW |
2974 | int |
2975 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2976 | struct intel_engine_cs *to) |
2911a35b | 2977 | { |
a4872ba6 | 2978 | struct intel_engine_cs *from = obj->ring; |
2911a35b BW |
2979 | u32 seqno; |
2980 | int ret, idx; | |
2981 | ||
2982 | if (from == NULL || to == from) | |
2983 | return 0; | |
2984 | ||
5816d648 | 2985 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2986 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2987 | |
2988 | idx = intel_ring_sync_index(from, to); | |
2989 | ||
0201f1ec | 2990 | seqno = obj->last_read_seqno; |
ddd4dbc6 RV |
2991 | /* Optimization: Avoid semaphore sync when we are sure we already |
2992 | * waited for an object with higher seqno */ | |
ebc348b2 | 2993 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2994 | return 0; |
2995 | ||
b4aca010 BW |
2996 | ret = i915_gem_check_olr(obj->ring, seqno); |
2997 | if (ret) | |
2998 | return ret; | |
2911a35b | 2999 | |
b52b89da | 3000 | trace_i915_gem_ring_sync_to(from, to, seqno); |
ebc348b2 | 3001 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 3002 | if (!ret) |
7b01e260 MK |
3003 | /* We use last_read_seqno because sync_to() |
3004 | * might have just caused seqno wrap under | |
3005 | * the radar. | |
3006 | */ | |
ebc348b2 | 3007 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
2911a35b | 3008 | |
e3a5a225 | 3009 | return ret; |
2911a35b BW |
3010 | } |
3011 | ||
b5ffc9bc CW |
3012 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3013 | { | |
3014 | u32 old_write_domain, old_read_domains; | |
3015 | ||
b5ffc9bc CW |
3016 | /* Force a pagefault for domain tracking on next user access */ |
3017 | i915_gem_release_mmap(obj); | |
3018 | ||
b97c3d9c KP |
3019 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3020 | return; | |
3021 | ||
97c809fd CW |
3022 | /* Wait for any direct GTT access to complete */ |
3023 | mb(); | |
3024 | ||
b5ffc9bc CW |
3025 | old_read_domains = obj->base.read_domains; |
3026 | old_write_domain = obj->base.write_domain; | |
3027 | ||
3028 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3029 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3030 | ||
3031 | trace_i915_gem_object_change_domain(obj, | |
3032 | old_read_domains, | |
3033 | old_write_domain); | |
3034 | } | |
3035 | ||
07fe0b12 | 3036 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 3037 | { |
07fe0b12 | 3038 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3039 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3040 | int ret; |
673a394b | 3041 | |
07fe0b12 | 3042 | if (list_empty(&vma->vma_link)) |
673a394b EA |
3043 | return 0; |
3044 | ||
0ff501cb DV |
3045 | if (!drm_mm_node_allocated(&vma->node)) { |
3046 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3047 | return 0; |
3048 | } | |
433544bd | 3049 | |
d7f46fc4 | 3050 | if (vma->pin_count) |
31d8d651 | 3051 | return -EBUSY; |
673a394b | 3052 | |
c4670ad0 CW |
3053 | BUG_ON(obj->pages == NULL); |
3054 | ||
a8198eea | 3055 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 3056 | if (ret) |
a8198eea CW |
3057 | return ret; |
3058 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
3059 | * should be safe and we need to cleanup or else we might | |
3060 | * cause memory corruption through use-after-free. | |
3061 | */ | |
3062 | ||
1d1ef21d CW |
3063 | /* Throw away the active reference before moving to the unbound list */ |
3064 | i915_gem_object_retire(obj); | |
3065 | ||
8b1bc9b4 DV |
3066 | if (i915_is_ggtt(vma->vm)) { |
3067 | i915_gem_object_finish_gtt(obj); | |
5323fd04 | 3068 | |
8b1bc9b4 DV |
3069 | /* release the fence reg _after_ flushing */ |
3070 | ret = i915_gem_object_put_fence(obj); | |
3071 | if (ret) | |
3072 | return ret; | |
3073 | } | |
96b47b65 | 3074 | |
07fe0b12 | 3075 | trace_i915_vma_unbind(vma); |
db53a302 | 3076 | |
6f65e29a BW |
3077 | vma->unbind_vma(vma); |
3078 | ||
64bf9303 | 3079 | list_del_init(&vma->mm_list); |
5cacaac7 | 3080 | if (i915_is_ggtt(vma->vm)) |
e6a84468 | 3081 | obj->map_and_fenceable = false; |
673a394b | 3082 | |
2f633156 BW |
3083 | drm_mm_remove_node(&vma->node); |
3084 | i915_gem_vma_destroy(vma); | |
3085 | ||
3086 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3087 | * no more VMAs exist. */ |
9490edb5 AR |
3088 | if (list_empty(&obj->vma_list)) { |
3089 | i915_gem_gtt_finish_object(obj); | |
2f633156 | 3090 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
9490edb5 | 3091 | } |
673a394b | 3092 | |
70903c3b CW |
3093 | /* And finally now the object is completely decoupled from this vma, |
3094 | * we can drop its hold on the backing storage and allow it to be | |
3095 | * reaped by the shrinker. | |
3096 | */ | |
3097 | i915_gem_object_unpin_pages(obj); | |
3098 | ||
88241785 | 3099 | return 0; |
54cf91dc CW |
3100 | } |
3101 | ||
b2da9fe5 | 3102 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3103 | { |
3e31c6c0 | 3104 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3105 | struct intel_engine_cs *ring; |
1ec14ad3 | 3106 | int ret, i; |
4df2faf4 | 3107 | |
4df2faf4 | 3108 | /* Flush everything onto the inactive list. */ |
b4519513 | 3109 | for_each_ring(ring, dev_priv, i) { |
ecdb5fd8 TD |
3110 | if (!i915.enable_execlists) { |
3111 | ret = i915_switch_context(ring, ring->default_context); | |
3112 | if (ret) | |
3113 | return ret; | |
3114 | } | |
b6c7488d | 3115 | |
3e960501 | 3116 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
3117 | if (ret) |
3118 | return ret; | |
3119 | } | |
4df2faf4 | 3120 | |
8a1a49f9 | 3121 | return 0; |
4df2faf4 DV |
3122 | } |
3123 | ||
9ce079e4 CW |
3124 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
3125 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3126 | { |
3e31c6c0 | 3127 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
3128 | int fence_reg; |
3129 | int fence_pitch_shift; | |
de151cf6 | 3130 | |
56c844e5 ID |
3131 | if (INTEL_INFO(dev)->gen >= 6) { |
3132 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
3133 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
3134 | } else { | |
3135 | fence_reg = FENCE_REG_965_0; | |
3136 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
3137 | } | |
3138 | ||
d18b9619 CW |
3139 | fence_reg += reg * 8; |
3140 | ||
3141 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
3142 | * we split the 64-bit update into two 32-bit writes. In order | |
3143 | * for a partial fence not to be evaluated between writes, we | |
3144 | * precede the update with write to turn off the fence register, | |
3145 | * and only enable the fence as the last step. | |
3146 | * | |
3147 | * For extra levels of paranoia, we make sure each step lands | |
3148 | * before applying the next step. | |
3149 | */ | |
3150 | I915_WRITE(fence_reg, 0); | |
3151 | POSTING_READ(fence_reg); | |
3152 | ||
9ce079e4 | 3153 | if (obj) { |
f343c5f6 | 3154 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 3155 | uint64_t val; |
de151cf6 | 3156 | |
f343c5f6 | 3157 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3158 | 0xfffff000) << 32; |
f343c5f6 | 3159 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3160 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3161 | if (obj->tiling_mode == I915_TILING_Y) |
3162 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3163 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3164 | |
d18b9619 CW |
3165 | I915_WRITE(fence_reg + 4, val >> 32); |
3166 | POSTING_READ(fence_reg + 4); | |
3167 | ||
3168 | I915_WRITE(fence_reg + 0, val); | |
3169 | POSTING_READ(fence_reg); | |
3170 | } else { | |
3171 | I915_WRITE(fence_reg + 4, 0); | |
3172 | POSTING_READ(fence_reg + 4); | |
3173 | } | |
de151cf6 JB |
3174 | } |
3175 | ||
9ce079e4 CW |
3176 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3177 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3178 | { |
3e31c6c0 | 3179 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3180 | u32 val; |
de151cf6 | 3181 | |
9ce079e4 | 3182 | if (obj) { |
f343c5f6 | 3183 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3184 | int pitch_val; |
3185 | int tile_width; | |
c6642782 | 3186 | |
f343c5f6 | 3187 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3188 | (size & -size) != size || |
f343c5f6 BW |
3189 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3190 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3191 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3192 | |
9ce079e4 CW |
3193 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3194 | tile_width = 128; | |
3195 | else | |
3196 | tile_width = 512; | |
3197 | ||
3198 | /* Note: pitch better be a power of two tile widths */ | |
3199 | pitch_val = obj->stride / tile_width; | |
3200 | pitch_val = ffs(pitch_val) - 1; | |
3201 | ||
f343c5f6 | 3202 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3203 | if (obj->tiling_mode == I915_TILING_Y) |
3204 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3205 | val |= I915_FENCE_SIZE_BITS(size); | |
3206 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3207 | val |= I830_FENCE_REG_VALID; | |
3208 | } else | |
3209 | val = 0; | |
3210 | ||
3211 | if (reg < 8) | |
3212 | reg = FENCE_REG_830_0 + reg * 4; | |
3213 | else | |
3214 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3215 | ||
3216 | I915_WRITE(reg, val); | |
3217 | POSTING_READ(reg); | |
de151cf6 JB |
3218 | } |
3219 | ||
9ce079e4 CW |
3220 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3221 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3222 | { |
3e31c6c0 | 3223 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3224 | uint32_t val; |
de151cf6 | 3225 | |
9ce079e4 | 3226 | if (obj) { |
f343c5f6 | 3227 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3228 | uint32_t pitch_val; |
de151cf6 | 3229 | |
f343c5f6 | 3230 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3231 | (size & -size) != size || |
f343c5f6 BW |
3232 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3233 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3234 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3235 | |
9ce079e4 CW |
3236 | pitch_val = obj->stride / 128; |
3237 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3238 | |
f343c5f6 | 3239 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3240 | if (obj->tiling_mode == I915_TILING_Y) |
3241 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3242 | val |= I830_FENCE_SIZE_BITS(size); | |
3243 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3244 | val |= I830_FENCE_REG_VALID; | |
3245 | } else | |
3246 | val = 0; | |
c6642782 | 3247 | |
9ce079e4 CW |
3248 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3249 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3250 | } | |
3251 | ||
d0a57789 CW |
3252 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3253 | { | |
3254 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3255 | } | |
3256 | ||
9ce079e4 CW |
3257 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3258 | struct drm_i915_gem_object *obj) | |
3259 | { | |
d0a57789 CW |
3260 | struct drm_i915_private *dev_priv = dev->dev_private; |
3261 | ||
3262 | /* Ensure that all CPU reads are completed before installing a fence | |
3263 | * and all writes before removing the fence. | |
3264 | */ | |
3265 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3266 | mb(); | |
3267 | ||
94a335db DV |
3268 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3269 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3270 | obj->stride, obj->tiling_mode); | |
3271 | ||
9ce079e4 | 3272 | switch (INTEL_INFO(dev)->gen) { |
01209dd5 | 3273 | case 9: |
5ab31333 | 3274 | case 8: |
9ce079e4 | 3275 | case 7: |
56c844e5 | 3276 | case 6: |
9ce079e4 CW |
3277 | case 5: |
3278 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
3279 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
3280 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 3281 | default: BUG(); |
9ce079e4 | 3282 | } |
d0a57789 CW |
3283 | |
3284 | /* And similarly be paranoid that no direct access to this region | |
3285 | * is reordered to before the fence is installed. | |
3286 | */ | |
3287 | if (i915_gem_object_needs_mb(obj)) | |
3288 | mb(); | |
de151cf6 JB |
3289 | } |
3290 | ||
61050808 CW |
3291 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3292 | struct drm_i915_fence_reg *fence) | |
3293 | { | |
3294 | return fence - dev_priv->fence_regs; | |
3295 | } | |
3296 | ||
3297 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3298 | struct drm_i915_fence_reg *fence, | |
3299 | bool enable) | |
3300 | { | |
2dc8aae0 | 3301 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3302 | int reg = fence_number(dev_priv, fence); |
3303 | ||
3304 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3305 | |
3306 | if (enable) { | |
46a0b638 | 3307 | obj->fence_reg = reg; |
61050808 CW |
3308 | fence->obj = obj; |
3309 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3310 | } else { | |
3311 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3312 | fence->obj = NULL; | |
3313 | list_del_init(&fence->lru_list); | |
3314 | } | |
94a335db | 3315 | obj->fence_dirty = false; |
61050808 CW |
3316 | } |
3317 | ||
d9e86c0e | 3318 | static int |
d0a57789 | 3319 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3320 | { |
1c293ea3 | 3321 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3322 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3323 | if (ret) |
3324 | return ret; | |
d9e86c0e CW |
3325 | |
3326 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3327 | } |
3328 | ||
3329 | return 0; | |
3330 | } | |
3331 | ||
3332 | int | |
3333 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3334 | { | |
61050808 | 3335 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3336 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3337 | int ret; |
3338 | ||
d0a57789 | 3339 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3340 | if (ret) |
3341 | return ret; | |
3342 | ||
61050808 CW |
3343 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3344 | return 0; | |
d9e86c0e | 3345 | |
f9c513e9 CW |
3346 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3347 | ||
aff10b30 DV |
3348 | if (WARN_ON(fence->pin_count)) |
3349 | return -EBUSY; | |
3350 | ||
61050808 | 3351 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3352 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3353 | |
3354 | return 0; | |
3355 | } | |
3356 | ||
3357 | static struct drm_i915_fence_reg * | |
a360bb1a | 3358 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3359 | { |
ae3db24a | 3360 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3361 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3362 | int i; |
ae3db24a DV |
3363 | |
3364 | /* First try to find a free reg */ | |
d9e86c0e | 3365 | avail = NULL; |
ae3db24a DV |
3366 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3367 | reg = &dev_priv->fence_regs[i]; | |
3368 | if (!reg->obj) | |
d9e86c0e | 3369 | return reg; |
ae3db24a | 3370 | |
1690e1eb | 3371 | if (!reg->pin_count) |
d9e86c0e | 3372 | avail = reg; |
ae3db24a DV |
3373 | } |
3374 | ||
d9e86c0e | 3375 | if (avail == NULL) |
5dce5b93 | 3376 | goto deadlock; |
ae3db24a DV |
3377 | |
3378 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3379 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3380 | if (reg->pin_count) |
ae3db24a DV |
3381 | continue; |
3382 | ||
8fe301ad | 3383 | return reg; |
ae3db24a DV |
3384 | } |
3385 | ||
5dce5b93 CW |
3386 | deadlock: |
3387 | /* Wait for completion of pending flips which consume fences */ | |
3388 | if (intel_has_pending_fb_unpin(dev)) | |
3389 | return ERR_PTR(-EAGAIN); | |
3390 | ||
3391 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3392 | } |
3393 | ||
de151cf6 | 3394 | /** |
9a5a53b3 | 3395 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3396 | * @obj: object to map through a fence reg |
3397 | * | |
3398 | * When mapping objects through the GTT, userspace wants to be able to write | |
3399 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3400 | * This function walks the fence regs looking for a free one for @obj, |
3401 | * stealing one if it can't find any. | |
3402 | * | |
3403 | * It then sets up the reg based on the object's properties: address, pitch | |
3404 | * and tiling format. | |
9a5a53b3 CW |
3405 | * |
3406 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3407 | */ |
8c4b8c3f | 3408 | int |
06d98131 | 3409 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3410 | { |
05394f39 | 3411 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3412 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3413 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3414 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3415 | int ret; |
de151cf6 | 3416 | |
14415745 CW |
3417 | /* Have we updated the tiling parameters upon the object and so |
3418 | * will need to serialise the write to the associated fence register? | |
3419 | */ | |
5d82e3e6 | 3420 | if (obj->fence_dirty) { |
d0a57789 | 3421 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3422 | if (ret) |
3423 | return ret; | |
3424 | } | |
9a5a53b3 | 3425 | |
d9e86c0e | 3426 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3427 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3428 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3429 | if (!obj->fence_dirty) { |
14415745 CW |
3430 | list_move_tail(®->lru_list, |
3431 | &dev_priv->mm.fence_list); | |
3432 | return 0; | |
3433 | } | |
3434 | } else if (enable) { | |
e6a84468 CW |
3435 | if (WARN_ON(!obj->map_and_fenceable)) |
3436 | return -EINVAL; | |
3437 | ||
14415745 | 3438 | reg = i915_find_fence_reg(dev); |
5dce5b93 CW |
3439 | if (IS_ERR(reg)) |
3440 | return PTR_ERR(reg); | |
d9e86c0e | 3441 | |
14415745 CW |
3442 | if (reg->obj) { |
3443 | struct drm_i915_gem_object *old = reg->obj; | |
3444 | ||
d0a57789 | 3445 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3446 | if (ret) |
3447 | return ret; | |
3448 | ||
14415745 | 3449 | i915_gem_object_fence_lost(old); |
29c5a587 | 3450 | } |
14415745 | 3451 | } else |
a09ba7fa | 3452 | return 0; |
a09ba7fa | 3453 | |
14415745 | 3454 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3455 | |
9ce079e4 | 3456 | return 0; |
de151cf6 JB |
3457 | } |
3458 | ||
4144f9b5 | 3459 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3460 | unsigned long cache_level) |
3461 | { | |
4144f9b5 | 3462 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3463 | struct drm_mm_node *other; |
3464 | ||
4144f9b5 CW |
3465 | /* |
3466 | * On some machines we have to be careful when putting differing types | |
3467 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3468 | * domains and dying. During vm initialisation, we decide whether or not | |
3469 | * these constraints apply and set the drm_mm.color_adjust | |
3470 | * appropriately. | |
42d6ab48 | 3471 | */ |
4144f9b5 | 3472 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3473 | return true; |
3474 | ||
c6cfb325 | 3475 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3476 | return true; |
3477 | ||
3478 | if (list_empty(>t_space->node_list)) | |
3479 | return true; | |
3480 | ||
3481 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3482 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3483 | return false; | |
3484 | ||
3485 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3486 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3487 | return false; | |
3488 | ||
3489 | return true; | |
3490 | } | |
3491 | ||
673a394b EA |
3492 | /** |
3493 | * Finds free space in the GTT aperture and binds the object there. | |
3494 | */ | |
262de145 | 3495 | static struct i915_vma * |
07fe0b12 BW |
3496 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3497 | struct i915_address_space *vm, | |
3498 | unsigned alignment, | |
d23db88c | 3499 | uint64_t flags) |
673a394b | 3500 | { |
05394f39 | 3501 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3502 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3503 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3504 | unsigned long start = |
3505 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3506 | unsigned long end = | |
1ec9e26d | 3507 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3508 | struct i915_vma *vma; |
07f73f69 | 3509 | int ret; |
673a394b | 3510 | |
e28f8711 CW |
3511 | fence_size = i915_gem_get_gtt_size(dev, |
3512 | obj->base.size, | |
3513 | obj->tiling_mode); | |
3514 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3515 | obj->base.size, | |
d865110c | 3516 | obj->tiling_mode, true); |
e28f8711 | 3517 | unfenced_alignment = |
d865110c | 3518 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3519 | obj->base.size, |
3520 | obj->tiling_mode, false); | |
a00b10c3 | 3521 | |
673a394b | 3522 | if (alignment == 0) |
1ec9e26d | 3523 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3524 | unfenced_alignment; |
1ec9e26d | 3525 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3526 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3527 | return ERR_PTR(-EINVAL); |
673a394b EA |
3528 | } |
3529 | ||
1ec9e26d | 3530 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3531 | |
654fc607 CW |
3532 | /* If the object is bigger than the entire aperture, reject it early |
3533 | * before evicting everything in a vain attempt to find space. | |
3534 | */ | |
d23db88c CW |
3535 | if (obj->base.size > end) { |
3536 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", | |
a36689cb | 3537 | obj->base.size, |
1ec9e26d | 3538 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3539 | end); |
262de145 | 3540 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3541 | } |
3542 | ||
37e680a1 | 3543 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3544 | if (ret) |
262de145 | 3545 | return ERR_PTR(ret); |
6c085a72 | 3546 | |
fbdda6fb CW |
3547 | i915_gem_object_pin_pages(obj); |
3548 | ||
accfef2e | 3549 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3550 | if (IS_ERR(vma)) |
bc6bc15b | 3551 | goto err_unpin; |
2f633156 | 3552 | |
0a9ae0d7 | 3553 | search_free: |
07fe0b12 | 3554 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3555 | size, alignment, |
d23db88c CW |
3556 | obj->cache_level, |
3557 | start, end, | |
62347f9e LK |
3558 | DRM_MM_SEARCH_DEFAULT, |
3559 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3560 | if (ret) { |
f6cd1f15 | 3561 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3562 | obj->cache_level, |
3563 | start, end, | |
3564 | flags); | |
dc9dd7a2 CW |
3565 | if (ret == 0) |
3566 | goto search_free; | |
9731129c | 3567 | |
bc6bc15b | 3568 | goto err_free_vma; |
673a394b | 3569 | } |
4144f9b5 | 3570 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3571 | ret = -EINVAL; |
bc6bc15b | 3572 | goto err_remove_node; |
673a394b EA |
3573 | } |
3574 | ||
74163907 | 3575 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3576 | if (ret) |
bc6bc15b | 3577 | goto err_remove_node; |
673a394b | 3578 | |
35c20a60 | 3579 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3580 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3581 | |
1ec9e26d | 3582 | trace_i915_vma_bind(vma, flags); |
8ea99c92 | 3583 | vma->bind_vma(vma, obj->cache_level, |
c826c449 | 3584 | flags & PIN_GLOBAL ? GLOBAL_BIND : 0); |
8ea99c92 | 3585 | |
262de145 | 3586 | return vma; |
2f633156 | 3587 | |
bc6bc15b | 3588 | err_remove_node: |
6286ef9b | 3589 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3590 | err_free_vma: |
2f633156 | 3591 | i915_gem_vma_destroy(vma); |
262de145 | 3592 | vma = ERR_PTR(ret); |
bc6bc15b | 3593 | err_unpin: |
2f633156 | 3594 | i915_gem_object_unpin_pages(obj); |
262de145 | 3595 | return vma; |
673a394b EA |
3596 | } |
3597 | ||
000433b6 | 3598 | bool |
2c22569b CW |
3599 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3600 | bool force) | |
673a394b | 3601 | { |
673a394b EA |
3602 | /* If we don't have a page list set up, then we're not pinned |
3603 | * to GPU, and we can ignore the cache flush because it'll happen | |
3604 | * again at bind time. | |
3605 | */ | |
05394f39 | 3606 | if (obj->pages == NULL) |
000433b6 | 3607 | return false; |
673a394b | 3608 | |
769ce464 ID |
3609 | /* |
3610 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3611 | * marked as wc by the system, or the system is cache-coherent. | |
3612 | */ | |
6a2c4232 | 3613 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3614 | return false; |
769ce464 | 3615 | |
9c23f7fc CW |
3616 | /* If the GPU is snooping the contents of the CPU cache, |
3617 | * we do not need to manually clear the CPU cache lines. However, | |
3618 | * the caches are only snooped when the render cache is | |
3619 | * flushed/invalidated. As we always have to emit invalidations | |
3620 | * and flushes when moving into and out of the RENDER domain, correct | |
3621 | * snooping behaviour occurs naturally as the result of our domain | |
3622 | * tracking. | |
3623 | */ | |
2c22569b | 3624 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3625 | return false; |
9c23f7fc | 3626 | |
1c5d22f7 | 3627 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3628 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3629 | |
3630 | return true; | |
e47c68e9 EA |
3631 | } |
3632 | ||
3633 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3634 | static void | |
05394f39 | 3635 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3636 | { |
1c5d22f7 CW |
3637 | uint32_t old_write_domain; |
3638 | ||
05394f39 | 3639 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3640 | return; |
3641 | ||
63256ec5 | 3642 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3643 | * to it immediately go to main memory as far as we know, so there's |
3644 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3645 | * |
3646 | * However, we do have to enforce the order so that all writes through | |
3647 | * the GTT land before any writes to the device, such as updates to | |
3648 | * the GATT itself. | |
e47c68e9 | 3649 | */ |
63256ec5 CW |
3650 | wmb(); |
3651 | ||
05394f39 CW |
3652 | old_write_domain = obj->base.write_domain; |
3653 | obj->base.write_domain = 0; | |
1c5d22f7 | 3654 | |
f99d7069 DV |
3655 | intel_fb_obj_flush(obj, false); |
3656 | ||
1c5d22f7 | 3657 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3658 | obj->base.read_domains, |
1c5d22f7 | 3659 | old_write_domain); |
e47c68e9 EA |
3660 | } |
3661 | ||
3662 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3663 | static void | |
2c22569b CW |
3664 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3665 | bool force) | |
e47c68e9 | 3666 | { |
1c5d22f7 | 3667 | uint32_t old_write_domain; |
e47c68e9 | 3668 | |
05394f39 | 3669 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3670 | return; |
3671 | ||
000433b6 CW |
3672 | if (i915_gem_clflush_object(obj, force)) |
3673 | i915_gem_chipset_flush(obj->base.dev); | |
3674 | ||
05394f39 CW |
3675 | old_write_domain = obj->base.write_domain; |
3676 | obj->base.write_domain = 0; | |
1c5d22f7 | 3677 | |
f99d7069 DV |
3678 | intel_fb_obj_flush(obj, false); |
3679 | ||
1c5d22f7 | 3680 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3681 | obj->base.read_domains, |
1c5d22f7 | 3682 | old_write_domain); |
e47c68e9 EA |
3683 | } |
3684 | ||
2ef7eeaa EA |
3685 | /** |
3686 | * Moves a single object to the GTT read, and possibly write domain. | |
3687 | * | |
3688 | * This function returns when the move is complete, including waiting on | |
3689 | * flushes to occur. | |
3690 | */ | |
79e53945 | 3691 | int |
2021746e | 3692 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3693 | { |
3e31c6c0 | 3694 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
dc8cd1e7 | 3695 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
1c5d22f7 | 3696 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3697 | int ret; |
2ef7eeaa | 3698 | |
02354392 | 3699 | /* Not valid to be called on unbound objects. */ |
dc8cd1e7 | 3700 | if (vma == NULL) |
02354392 EA |
3701 | return -EINVAL; |
3702 | ||
8d7e3de1 CW |
3703 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3704 | return 0; | |
3705 | ||
0201f1ec | 3706 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3707 | if (ret) |
3708 | return ret; | |
3709 | ||
c8725f3d | 3710 | i915_gem_object_retire(obj); |
2c22569b | 3711 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3712 | |
d0a57789 CW |
3713 | /* Serialise direct access to this object with the barriers for |
3714 | * coherent writes from the GPU, by effectively invalidating the | |
3715 | * GTT domain upon first access. | |
3716 | */ | |
3717 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3718 | mb(); | |
3719 | ||
05394f39 CW |
3720 | old_write_domain = obj->base.write_domain; |
3721 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3722 | |
e47c68e9 EA |
3723 | /* It should now be out of any other write domains, and we can update |
3724 | * the domain values for our changes. | |
3725 | */ | |
05394f39 CW |
3726 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3727 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3728 | if (write) { |
05394f39 CW |
3729 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3730 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3731 | obj->dirty = 1; | |
2ef7eeaa EA |
3732 | } |
3733 | ||
f99d7069 DV |
3734 | if (write) |
3735 | intel_fb_obj_invalidate(obj, NULL); | |
3736 | ||
1c5d22f7 CW |
3737 | trace_i915_gem_object_change_domain(obj, |
3738 | old_read_domains, | |
3739 | old_write_domain); | |
3740 | ||
8325a09d | 3741 | /* And bump the LRU for this access */ |
dc8cd1e7 CW |
3742 | if (i915_gem_object_is_inactive(obj)) |
3743 | list_move_tail(&vma->mm_list, | |
3744 | &dev_priv->gtt.base.inactive_list); | |
8325a09d | 3745 | |
e47c68e9 EA |
3746 | return 0; |
3747 | } | |
3748 | ||
e4ffd173 CW |
3749 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3750 | enum i915_cache_level cache_level) | |
3751 | { | |
7bddb01f | 3752 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3753 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3754 | int ret; |
3755 | ||
3756 | if (obj->cache_level == cache_level) | |
3757 | return 0; | |
3758 | ||
d7f46fc4 | 3759 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3760 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3761 | return -EBUSY; | |
3762 | } | |
3763 | ||
df6f783a | 3764 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4144f9b5 | 3765 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3766 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3767 | if (ret) |
3768 | return ret; | |
3089c6f2 | 3769 | } |
42d6ab48 CW |
3770 | } |
3771 | ||
3089c6f2 | 3772 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3773 | ret = i915_gem_object_finish_gpu(obj); |
3774 | if (ret) | |
3775 | return ret; | |
3776 | ||
3777 | i915_gem_object_finish_gtt(obj); | |
3778 | ||
3779 | /* Before SandyBridge, you could not use tiling or fence | |
3780 | * registers with snooped memory, so relinquish any fences | |
3781 | * currently pointing to our region in the aperture. | |
3782 | */ | |
42d6ab48 | 3783 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3784 | ret = i915_gem_object_put_fence(obj); |
3785 | if (ret) | |
3786 | return ret; | |
3787 | } | |
3788 | ||
6f65e29a | 3789 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3790 | if (drm_mm_node_allocated(&vma->node)) |
3791 | vma->bind_vma(vma, cache_level, | |
aff43766 | 3792 | vma->bound & GLOBAL_BIND); |
e4ffd173 CW |
3793 | } |
3794 | ||
2c22569b CW |
3795 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3796 | vma->node.color = cache_level; | |
3797 | obj->cache_level = cache_level; | |
3798 | ||
3799 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3800 | u32 old_read_domains, old_write_domain; |
3801 | ||
3802 | /* If we're coming from LLC cached, then we haven't | |
3803 | * actually been tracking whether the data is in the | |
3804 | * CPU cache or not, since we only allow one bit set | |
3805 | * in obj->write_domain and have been skipping the clflushes. | |
3806 | * Just set it to the CPU cache for now. | |
3807 | */ | |
c8725f3d | 3808 | i915_gem_object_retire(obj); |
e4ffd173 | 3809 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e4ffd173 CW |
3810 | |
3811 | old_read_domains = obj->base.read_domains; | |
3812 | old_write_domain = obj->base.write_domain; | |
3813 | ||
3814 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3815 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3816 | ||
3817 | trace_i915_gem_object_change_domain(obj, | |
3818 | old_read_domains, | |
3819 | old_write_domain); | |
3820 | } | |
3821 | ||
e4ffd173 CW |
3822 | return 0; |
3823 | } | |
3824 | ||
199adf40 BW |
3825 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3826 | struct drm_file *file) | |
e6994aee | 3827 | { |
199adf40 | 3828 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3829 | struct drm_i915_gem_object *obj; |
3830 | int ret; | |
3831 | ||
3832 | ret = i915_mutex_lock_interruptible(dev); | |
3833 | if (ret) | |
3834 | return ret; | |
3835 | ||
3836 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3837 | if (&obj->base == NULL) { | |
3838 | ret = -ENOENT; | |
3839 | goto unlock; | |
3840 | } | |
3841 | ||
651d794f CW |
3842 | switch (obj->cache_level) { |
3843 | case I915_CACHE_LLC: | |
3844 | case I915_CACHE_L3_LLC: | |
3845 | args->caching = I915_CACHING_CACHED; | |
3846 | break; | |
3847 | ||
4257d3ba CW |
3848 | case I915_CACHE_WT: |
3849 | args->caching = I915_CACHING_DISPLAY; | |
3850 | break; | |
3851 | ||
651d794f CW |
3852 | default: |
3853 | args->caching = I915_CACHING_NONE; | |
3854 | break; | |
3855 | } | |
e6994aee CW |
3856 | |
3857 | drm_gem_object_unreference(&obj->base); | |
3858 | unlock: | |
3859 | mutex_unlock(&dev->struct_mutex); | |
3860 | return ret; | |
3861 | } | |
3862 | ||
199adf40 BW |
3863 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3864 | struct drm_file *file) | |
e6994aee | 3865 | { |
199adf40 | 3866 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3867 | struct drm_i915_gem_object *obj; |
3868 | enum i915_cache_level level; | |
3869 | int ret; | |
3870 | ||
199adf40 BW |
3871 | switch (args->caching) { |
3872 | case I915_CACHING_NONE: | |
e6994aee CW |
3873 | level = I915_CACHE_NONE; |
3874 | break; | |
199adf40 | 3875 | case I915_CACHING_CACHED: |
e6994aee CW |
3876 | level = I915_CACHE_LLC; |
3877 | break; | |
4257d3ba CW |
3878 | case I915_CACHING_DISPLAY: |
3879 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3880 | break; | |
e6994aee CW |
3881 | default: |
3882 | return -EINVAL; | |
3883 | } | |
3884 | ||
3bc2913e BW |
3885 | ret = i915_mutex_lock_interruptible(dev); |
3886 | if (ret) | |
3887 | return ret; | |
3888 | ||
e6994aee CW |
3889 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3890 | if (&obj->base == NULL) { | |
3891 | ret = -ENOENT; | |
3892 | goto unlock; | |
3893 | } | |
3894 | ||
3895 | ret = i915_gem_object_set_cache_level(obj, level); | |
3896 | ||
3897 | drm_gem_object_unreference(&obj->base); | |
3898 | unlock: | |
3899 | mutex_unlock(&dev->struct_mutex); | |
3900 | return ret; | |
3901 | } | |
3902 | ||
cc98b413 CW |
3903 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3904 | { | |
19656430 OM |
3905 | struct i915_vma *vma; |
3906 | ||
19656430 OM |
3907 | vma = i915_gem_obj_to_ggtt(obj); |
3908 | if (!vma) | |
3909 | return false; | |
3910 | ||
cc98b413 CW |
3911 | /* There are 3 sources that pin objects: |
3912 | * 1. The display engine (scanouts, sprites, cursors); | |
3913 | * 2. Reservations for execbuffer; | |
3914 | * 3. The user. | |
3915 | * | |
3916 | * We can ignore reservations as we hold the struct_mutex and | |
3917 | * are only called outside of the reservation path. The user | |
3918 | * can only increment pin_count once, and so if after | |
3919 | * subtracting the potential reference by the user, any pin_count | |
3920 | * remains, it must be due to another use by the display engine. | |
3921 | */ | |
19656430 | 3922 | return vma->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3923 | } |
3924 | ||
b9241ea3 | 3925 | /* |
2da3b9b9 CW |
3926 | * Prepare buffer for display plane (scanout, cursors, etc). |
3927 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3928 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3929 | */ |
3930 | int | |
2da3b9b9 CW |
3931 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3932 | u32 alignment, | |
a4872ba6 | 3933 | struct intel_engine_cs *pipelined) |
b9241ea3 | 3934 | { |
2da3b9b9 | 3935 | u32 old_read_domains, old_write_domain; |
19656430 | 3936 | bool was_pin_display; |
b9241ea3 ZW |
3937 | int ret; |
3938 | ||
0be73284 | 3939 | if (pipelined != obj->ring) { |
2911a35b BW |
3940 | ret = i915_gem_object_sync(obj, pipelined); |
3941 | if (ret) | |
b9241ea3 ZW |
3942 | return ret; |
3943 | } | |
3944 | ||
cc98b413 CW |
3945 | /* Mark the pin_display early so that we account for the |
3946 | * display coherency whilst setting up the cache domains. | |
3947 | */ | |
19656430 | 3948 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3949 | obj->pin_display = true; |
3950 | ||
a7ef0640 EA |
3951 | /* The display engine is not coherent with the LLC cache on gen6. As |
3952 | * a result, we make sure that the pinning that is about to occur is | |
3953 | * done with uncached PTEs. This is lowest common denominator for all | |
3954 | * chipsets. | |
3955 | * | |
3956 | * However for gen6+, we could do better by using the GFDT bit instead | |
3957 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3958 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3959 | */ | |
651d794f CW |
3960 | ret = i915_gem_object_set_cache_level(obj, |
3961 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3962 | if (ret) |
cc98b413 | 3963 | goto err_unpin_display; |
a7ef0640 | 3964 | |
2da3b9b9 CW |
3965 | /* As the user may map the buffer once pinned in the display plane |
3966 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3967 | * always use map_and_fenceable for all scanout buffers. | |
3968 | */ | |
1ec9e26d | 3969 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3970 | if (ret) |
cc98b413 | 3971 | goto err_unpin_display; |
2da3b9b9 | 3972 | |
2c22569b | 3973 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3974 | |
2da3b9b9 | 3975 | old_write_domain = obj->base.write_domain; |
05394f39 | 3976 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3977 | |
3978 | /* It should now be out of any other write domains, and we can update | |
3979 | * the domain values for our changes. | |
3980 | */ | |
e5f1d962 | 3981 | obj->base.write_domain = 0; |
05394f39 | 3982 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3983 | |
3984 | trace_i915_gem_object_change_domain(obj, | |
3985 | old_read_domains, | |
2da3b9b9 | 3986 | old_write_domain); |
b9241ea3 ZW |
3987 | |
3988 | return 0; | |
cc98b413 CW |
3989 | |
3990 | err_unpin_display: | |
19656430 OM |
3991 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3992 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
3993 | return ret; |
3994 | } | |
3995 | ||
3996 | void | |
3997 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3998 | { | |
d7f46fc4 | 3999 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 4000 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
4001 | } |
4002 | ||
85345517 | 4003 | int |
a8198eea | 4004 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 4005 | { |
88241785 CW |
4006 | int ret; |
4007 | ||
a8198eea | 4008 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
4009 | return 0; |
4010 | ||
0201f1ec | 4011 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
4012 | if (ret) |
4013 | return ret; | |
4014 | ||
a8198eea CW |
4015 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
4016 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 4017 | return 0; |
85345517 CW |
4018 | } |
4019 | ||
e47c68e9 EA |
4020 | /** |
4021 | * Moves a single object to the CPU read, and possibly write domain. | |
4022 | * | |
4023 | * This function returns when the move is complete, including waiting on | |
4024 | * flushes to occur. | |
4025 | */ | |
dabdfe02 | 4026 | int |
919926ae | 4027 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4028 | { |
1c5d22f7 | 4029 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4030 | int ret; |
4031 | ||
8d7e3de1 CW |
4032 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4033 | return 0; | |
4034 | ||
0201f1ec | 4035 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4036 | if (ret) |
4037 | return ret; | |
4038 | ||
c8725f3d | 4039 | i915_gem_object_retire(obj); |
e47c68e9 | 4040 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4041 | |
05394f39 CW |
4042 | old_write_domain = obj->base.write_domain; |
4043 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4044 | |
e47c68e9 | 4045 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4046 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4047 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4048 | |
05394f39 | 4049 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4050 | } |
4051 | ||
4052 | /* It should now be out of any other write domains, and we can update | |
4053 | * the domain values for our changes. | |
4054 | */ | |
05394f39 | 4055 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4056 | |
4057 | /* If we're writing through the CPU, then the GPU read domains will | |
4058 | * need to be invalidated at next use. | |
4059 | */ | |
4060 | if (write) { | |
05394f39 CW |
4061 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4062 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4063 | } |
2ef7eeaa | 4064 | |
f99d7069 DV |
4065 | if (write) |
4066 | intel_fb_obj_invalidate(obj, NULL); | |
4067 | ||
1c5d22f7 CW |
4068 | trace_i915_gem_object_change_domain(obj, |
4069 | old_read_domains, | |
4070 | old_write_domain); | |
4071 | ||
2ef7eeaa EA |
4072 | return 0; |
4073 | } | |
4074 | ||
673a394b EA |
4075 | /* Throttle our rendering by waiting until the ring has completed our requests |
4076 | * emitted over 20 msec ago. | |
4077 | * | |
b962442e EA |
4078 | * Note that if we were to use the current jiffies each time around the loop, |
4079 | * we wouldn't escape the function with any frames outstanding if the time to | |
4080 | * render a frame was over 20ms. | |
4081 | * | |
673a394b EA |
4082 | * This should get us reasonable parallelism between CPU and GPU but also |
4083 | * relatively low latency when blocking on a particular request to finish. | |
4084 | */ | |
40a5f0de | 4085 | static int |
f787a5f5 | 4086 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4087 | { |
f787a5f5 CW |
4088 | struct drm_i915_private *dev_priv = dev->dev_private; |
4089 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 4090 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 | 4091 | struct drm_i915_gem_request *request; |
a4872ba6 | 4092 | struct intel_engine_cs *ring = NULL; |
f69061be | 4093 | unsigned reset_counter; |
f787a5f5 CW |
4094 | u32 seqno = 0; |
4095 | int ret; | |
93533c29 | 4096 | |
308887aa DV |
4097 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4098 | if (ret) | |
4099 | return ret; | |
4100 | ||
4101 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4102 | if (ret) | |
4103 | return ret; | |
e110e8d6 | 4104 | |
1c25595f | 4105 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4106 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4107 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4108 | break; | |
40a5f0de | 4109 | |
f787a5f5 CW |
4110 | ring = request->ring; |
4111 | seqno = request->seqno; | |
b962442e | 4112 | } |
f69061be | 4113 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 4114 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4115 | |
f787a5f5 CW |
4116 | if (seqno == 0) |
4117 | return 0; | |
2bc43b5c | 4118 | |
16e9a21f | 4119 | ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4120 | if (ret == 0) |
4121 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
4122 | |
4123 | return ret; | |
4124 | } | |
4125 | ||
d23db88c CW |
4126 | static bool |
4127 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4128 | { | |
4129 | struct drm_i915_gem_object *obj = vma->obj; | |
4130 | ||
4131 | if (alignment && | |
4132 | vma->node.start & (alignment - 1)) | |
4133 | return true; | |
4134 | ||
4135 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4136 | return true; | |
4137 | ||
4138 | if (flags & PIN_OFFSET_BIAS && | |
4139 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4140 | return true; | |
4141 | ||
4142 | return false; | |
4143 | } | |
4144 | ||
673a394b | 4145 | int |
05394f39 | 4146 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 4147 | struct i915_address_space *vm, |
05394f39 | 4148 | uint32_t alignment, |
d23db88c | 4149 | uint64_t flags) |
673a394b | 4150 | { |
6e7186af | 4151 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4152 | struct i915_vma *vma; |
ef79e17c | 4153 | unsigned bound; |
673a394b EA |
4154 | int ret; |
4155 | ||
6e7186af BW |
4156 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4157 | return -ENODEV; | |
4158 | ||
bf3d149b | 4159 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4160 | return -EINVAL; |
07fe0b12 | 4161 | |
c826c449 CW |
4162 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4163 | return -EINVAL; | |
4164 | ||
07fe0b12 | 4165 | vma = i915_gem_obj_to_vma(obj, vm); |
07fe0b12 | 4166 | if (vma) { |
d7f46fc4 BW |
4167 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4168 | return -EBUSY; | |
4169 | ||
d23db88c | 4170 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4171 | WARN(vma->pin_count, |
ae7d49d8 | 4172 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 4173 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4174 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 4175 | i915_gem_obj_offset(obj, vm), alignment, |
d23db88c | 4176 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4177 | obj->map_and_fenceable); |
07fe0b12 | 4178 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4179 | if (ret) |
4180 | return ret; | |
8ea99c92 DV |
4181 | |
4182 | vma = NULL; | |
ac0c6b5a CW |
4183 | } |
4184 | } | |
4185 | ||
ef79e17c | 4186 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4187 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
4188 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
4189 | if (IS_ERR(vma)) | |
4190 | return PTR_ERR(vma); | |
22c344e9 | 4191 | } |
76446cac | 4192 | |
aff43766 | 4193 | if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) |
8ea99c92 | 4194 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
74898d7e | 4195 | |
ef79e17c CW |
4196 | if ((bound ^ vma->bound) & GLOBAL_BIND) { |
4197 | bool mappable, fenceable; | |
4198 | u32 fence_size, fence_alignment; | |
4199 | ||
4200 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4201 | obj->base.size, | |
4202 | obj->tiling_mode); | |
4203 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4204 | obj->base.size, | |
4205 | obj->tiling_mode, | |
4206 | true); | |
4207 | ||
4208 | fenceable = (vma->node.size == fence_size && | |
4209 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4210 | ||
4211 | mappable = (vma->node.start + obj->base.size <= | |
4212 | dev_priv->gtt.mappable_end); | |
4213 | ||
4214 | obj->map_and_fenceable = mappable && fenceable; | |
4215 | } | |
4216 | ||
4217 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); | |
4218 | ||
8ea99c92 | 4219 | vma->pin_count++; |
1ec9e26d DV |
4220 | if (flags & PIN_MAPPABLE) |
4221 | obj->pin_mappable |= true; | |
673a394b EA |
4222 | |
4223 | return 0; | |
4224 | } | |
4225 | ||
4226 | void | |
d7f46fc4 | 4227 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4228 | { |
d7f46fc4 | 4229 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 4230 | |
d7f46fc4 BW |
4231 | BUG_ON(!vma); |
4232 | BUG_ON(vma->pin_count == 0); | |
4233 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
4234 | ||
4235 | if (--vma->pin_count == 0) | |
6299f992 | 4236 | obj->pin_mappable = false; |
673a394b EA |
4237 | } |
4238 | ||
d8ffa60b DV |
4239 | bool |
4240 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4241 | { | |
4242 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4243 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4244 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4245 | ||
4246 | WARN_ON(!ggtt_vma || | |
4247 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4248 | ggtt_vma->pin_count); | |
4249 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4250 | return true; | |
4251 | } else | |
4252 | return false; | |
4253 | } | |
4254 | ||
4255 | void | |
4256 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4257 | { | |
4258 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4259 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4260 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4261 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4262 | } | |
4263 | } | |
4264 | ||
673a394b EA |
4265 | int |
4266 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4267 | struct drm_file *file) |
673a394b EA |
4268 | { |
4269 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4270 | struct drm_i915_gem_object *obj; |
673a394b EA |
4271 | int ret; |
4272 | ||
02f6bccc DV |
4273 | if (INTEL_INFO(dev)->gen >= 6) |
4274 | return -ENODEV; | |
4275 | ||
1d7cfea1 CW |
4276 | ret = i915_mutex_lock_interruptible(dev); |
4277 | if (ret) | |
4278 | return ret; | |
673a394b | 4279 | |
05394f39 | 4280 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4281 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4282 | ret = -ENOENT; |
4283 | goto unlock; | |
673a394b | 4284 | } |
673a394b | 4285 | |
05394f39 | 4286 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 4287 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
8c99e57d | 4288 | ret = -EFAULT; |
1d7cfea1 | 4289 | goto out; |
3ef94daa CW |
4290 | } |
4291 | ||
05394f39 | 4292 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
bd9b6a4e | 4293 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4294 | args->handle); |
1d7cfea1 CW |
4295 | ret = -EINVAL; |
4296 | goto out; | |
79e53945 JB |
4297 | } |
4298 | ||
aa5f8021 DV |
4299 | if (obj->user_pin_count == ULONG_MAX) { |
4300 | ret = -EBUSY; | |
4301 | goto out; | |
4302 | } | |
4303 | ||
93be8788 | 4304 | if (obj->user_pin_count == 0) { |
1ec9e26d | 4305 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
1d7cfea1 CW |
4306 | if (ret) |
4307 | goto out; | |
673a394b EA |
4308 | } |
4309 | ||
93be8788 CW |
4310 | obj->user_pin_count++; |
4311 | obj->pin_filp = file; | |
4312 | ||
f343c5f6 | 4313 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 4314 | out: |
05394f39 | 4315 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4316 | unlock: |
673a394b | 4317 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4318 | return ret; |
673a394b EA |
4319 | } |
4320 | ||
4321 | int | |
4322 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4323 | struct drm_file *file) |
673a394b EA |
4324 | { |
4325 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4326 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4327 | int ret; |
673a394b | 4328 | |
1d7cfea1 CW |
4329 | ret = i915_mutex_lock_interruptible(dev); |
4330 | if (ret) | |
4331 | return ret; | |
673a394b | 4332 | |
05394f39 | 4333 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4334 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4335 | ret = -ENOENT; |
4336 | goto unlock; | |
673a394b | 4337 | } |
76c1dec1 | 4338 | |
05394f39 | 4339 | if (obj->pin_filp != file) { |
bd9b6a4e | 4340 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4341 | args->handle); |
1d7cfea1 CW |
4342 | ret = -EINVAL; |
4343 | goto out; | |
79e53945 | 4344 | } |
05394f39 CW |
4345 | obj->user_pin_count--; |
4346 | if (obj->user_pin_count == 0) { | |
4347 | obj->pin_filp = NULL; | |
d7f46fc4 | 4348 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 4349 | } |
673a394b | 4350 | |
1d7cfea1 | 4351 | out: |
05394f39 | 4352 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4353 | unlock: |
673a394b | 4354 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4355 | return ret; |
673a394b EA |
4356 | } |
4357 | ||
4358 | int | |
4359 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4360 | struct drm_file *file) |
673a394b EA |
4361 | { |
4362 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4363 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4364 | int ret; |
4365 | ||
76c1dec1 | 4366 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4367 | if (ret) |
76c1dec1 | 4368 | return ret; |
673a394b | 4369 | |
05394f39 | 4370 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4371 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4372 | ret = -ENOENT; |
4373 | goto unlock; | |
673a394b | 4374 | } |
d1b851fc | 4375 | |
0be555b6 CW |
4376 | /* Count all active objects as busy, even if they are currently not used |
4377 | * by the gpu. Users of this interface expect objects to eventually | |
4378 | * become non-busy without any further actions, therefore emit any | |
4379 | * necessary flushes here. | |
c4de0a5d | 4380 | */ |
30dfebf3 | 4381 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4382 | |
30dfebf3 | 4383 | args->busy = obj->active; |
e9808edd CW |
4384 | if (obj->ring) { |
4385 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4386 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4387 | } | |
673a394b | 4388 | |
05394f39 | 4389 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4390 | unlock: |
673a394b | 4391 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4392 | return ret; |
673a394b EA |
4393 | } |
4394 | ||
4395 | int | |
4396 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4397 | struct drm_file *file_priv) | |
4398 | { | |
0206e353 | 4399 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4400 | } |
4401 | ||
3ef94daa CW |
4402 | int |
4403 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4404 | struct drm_file *file_priv) | |
4405 | { | |
4406 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4407 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4408 | int ret; |
3ef94daa CW |
4409 | |
4410 | switch (args->madv) { | |
4411 | case I915_MADV_DONTNEED: | |
4412 | case I915_MADV_WILLNEED: | |
4413 | break; | |
4414 | default: | |
4415 | return -EINVAL; | |
4416 | } | |
4417 | ||
1d7cfea1 CW |
4418 | ret = i915_mutex_lock_interruptible(dev); |
4419 | if (ret) | |
4420 | return ret; | |
4421 | ||
05394f39 | 4422 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4423 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4424 | ret = -ENOENT; |
4425 | goto unlock; | |
3ef94daa | 4426 | } |
3ef94daa | 4427 | |
d7f46fc4 | 4428 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4429 | ret = -EINVAL; |
4430 | goto out; | |
3ef94daa CW |
4431 | } |
4432 | ||
05394f39 CW |
4433 | if (obj->madv != __I915_MADV_PURGED) |
4434 | obj->madv = args->madv; | |
3ef94daa | 4435 | |
6c085a72 CW |
4436 | /* if the object is no longer attached, discard its backing storage */ |
4437 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4438 | i915_gem_object_truncate(obj); |
4439 | ||
05394f39 | 4440 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4441 | |
1d7cfea1 | 4442 | out: |
05394f39 | 4443 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4444 | unlock: |
3ef94daa | 4445 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4446 | return ret; |
3ef94daa CW |
4447 | } |
4448 | ||
37e680a1 CW |
4449 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4450 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4451 | { |
35c20a60 | 4452 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4453 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4454 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4455 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4456 | |
37e680a1 CW |
4457 | obj->ops = ops; |
4458 | ||
0327d6ba CW |
4459 | obj->fence_reg = I915_FENCE_REG_NONE; |
4460 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4461 | |
4462 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4463 | } | |
4464 | ||
37e680a1 CW |
4465 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4466 | .get_pages = i915_gem_object_get_pages_gtt, | |
4467 | .put_pages = i915_gem_object_put_pages_gtt, | |
4468 | }; | |
4469 | ||
05394f39 CW |
4470 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4471 | size_t size) | |
ac52bc56 | 4472 | { |
c397b908 | 4473 | struct drm_i915_gem_object *obj; |
5949eac4 | 4474 | struct address_space *mapping; |
1a240d4d | 4475 | gfp_t mask; |
ac52bc56 | 4476 | |
42dcedd4 | 4477 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4478 | if (obj == NULL) |
4479 | return NULL; | |
673a394b | 4480 | |
c397b908 | 4481 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4482 | i915_gem_object_free(obj); |
c397b908 DV |
4483 | return NULL; |
4484 | } | |
673a394b | 4485 | |
bed1ea95 CW |
4486 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4487 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4488 | /* 965gm cannot relocate objects above 4GiB. */ | |
4489 | mask &= ~__GFP_HIGHMEM; | |
4490 | mask |= __GFP_DMA32; | |
4491 | } | |
4492 | ||
496ad9aa | 4493 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4494 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4495 | |
37e680a1 | 4496 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4497 | |
c397b908 DV |
4498 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4499 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4500 | |
3d29b842 ED |
4501 | if (HAS_LLC(dev)) { |
4502 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4503 | * cache) for about a 10% performance improvement |
4504 | * compared to uncached. Graphics requests other than | |
4505 | * display scanout are coherent with the CPU in | |
4506 | * accessing this cache. This means in this mode we | |
4507 | * don't need to clflush on the CPU side, and on the | |
4508 | * GPU side we only need to flush internal caches to | |
4509 | * get data visible to the CPU. | |
4510 | * | |
4511 | * However, we maintain the display planes as UC, and so | |
4512 | * need to rebind when first used as such. | |
4513 | */ | |
4514 | obj->cache_level = I915_CACHE_LLC; | |
4515 | } else | |
4516 | obj->cache_level = I915_CACHE_NONE; | |
4517 | ||
d861e338 DV |
4518 | trace_i915_gem_object_create(obj); |
4519 | ||
05394f39 | 4520 | return obj; |
c397b908 DV |
4521 | } |
4522 | ||
340fbd8c CW |
4523 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4524 | { | |
4525 | /* If we are the last user of the backing storage (be it shmemfs | |
4526 | * pages or stolen etc), we know that the pages are going to be | |
4527 | * immediately released. In this case, we can then skip copying | |
4528 | * back the contents from the GPU. | |
4529 | */ | |
4530 | ||
4531 | if (obj->madv != I915_MADV_WILLNEED) | |
4532 | return false; | |
4533 | ||
4534 | if (obj->base.filp == NULL) | |
4535 | return true; | |
4536 | ||
4537 | /* At first glance, this looks racy, but then again so would be | |
4538 | * userspace racing mmap against close. However, the first external | |
4539 | * reference to the filp can only be obtained through the | |
4540 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4541 | * acquiring such a reference whilst we are in the middle of | |
4542 | * freeing the object. | |
4543 | */ | |
4544 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4545 | } | |
4546 | ||
1488fc08 | 4547 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4548 | { |
1488fc08 | 4549 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4550 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4551 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4552 | struct i915_vma *vma, *next; |
673a394b | 4553 | |
f65c9168 PZ |
4554 | intel_runtime_pm_get(dev_priv); |
4555 | ||
26e12f89 CW |
4556 | trace_i915_gem_object_destroy(obj); |
4557 | ||
07fe0b12 | 4558 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4559 | int ret; |
4560 | ||
4561 | vma->pin_count = 0; | |
4562 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4563 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4564 | bool was_interruptible; | |
1488fc08 | 4565 | |
07fe0b12 BW |
4566 | was_interruptible = dev_priv->mm.interruptible; |
4567 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4568 | |
07fe0b12 | 4569 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4570 | |
07fe0b12 BW |
4571 | dev_priv->mm.interruptible = was_interruptible; |
4572 | } | |
1488fc08 CW |
4573 | } |
4574 | ||
1d64ae71 BW |
4575 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4576 | * before progressing. */ | |
4577 | if (obj->stolen) | |
4578 | i915_gem_object_unpin_pages(obj); | |
4579 | ||
a071fa00 DV |
4580 | WARN_ON(obj->frontbuffer_bits); |
4581 | ||
401c29f6 BW |
4582 | if (WARN_ON(obj->pages_pin_count)) |
4583 | obj->pages_pin_count = 0; | |
340fbd8c | 4584 | if (discard_backing_storage(obj)) |
5537252b | 4585 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4586 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4587 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4588 | |
9da3da66 CW |
4589 | BUG_ON(obj->pages); |
4590 | ||
2f745ad3 CW |
4591 | if (obj->base.import_attach) |
4592 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4593 | |
5cc9ed4b CW |
4594 | if (obj->ops->release) |
4595 | obj->ops->release(obj); | |
4596 | ||
05394f39 CW |
4597 | drm_gem_object_release(&obj->base); |
4598 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4599 | |
05394f39 | 4600 | kfree(obj->bit_17); |
42dcedd4 | 4601 | i915_gem_object_free(obj); |
f65c9168 PZ |
4602 | |
4603 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4604 | } |
4605 | ||
e656a6cb | 4606 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4607 | struct i915_address_space *vm) |
e656a6cb DV |
4608 | { |
4609 | struct i915_vma *vma; | |
4610 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4611 | if (vma->vm == vm) | |
4612 | return vma; | |
4613 | ||
4614 | return NULL; | |
4615 | } | |
4616 | ||
2f633156 BW |
4617 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4618 | { | |
b9d06dd9 | 4619 | struct i915_address_space *vm = NULL; |
2f633156 | 4620 | WARN_ON(vma->node.allocated); |
aaa05667 CW |
4621 | |
4622 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4623 | if (!list_empty(&vma->exec_list)) | |
4624 | return; | |
4625 | ||
b9d06dd9 | 4626 | vm = vma->vm; |
b9d06dd9 | 4627 | |
841cd773 DV |
4628 | if (!i915_is_ggtt(vm)) |
4629 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 4630 | |
8b9c2b94 | 4631 | list_del(&vma->vma_link); |
b93dab6e | 4632 | |
2f633156 BW |
4633 | kfree(vma); |
4634 | } | |
4635 | ||
e3efda49 CW |
4636 | static void |
4637 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4638 | { | |
4639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4640 | struct intel_engine_cs *ring; |
e3efda49 CW |
4641 | int i; |
4642 | ||
4643 | for_each_ring(ring, dev_priv, i) | |
a83014d3 | 4644 | dev_priv->gt.stop_ring(ring); |
e3efda49 CW |
4645 | } |
4646 | ||
29105ccc | 4647 | int |
45c5f202 | 4648 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4649 | { |
3e31c6c0 | 4650 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4651 | int ret = 0; |
28dfe52a | 4652 | |
45c5f202 | 4653 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4654 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4655 | goto err; |
28dfe52a | 4656 | |
b2da9fe5 | 4657 | ret = i915_gpu_idle(dev); |
f7403347 | 4658 | if (ret) |
45c5f202 | 4659 | goto err; |
f7403347 | 4660 | |
b2da9fe5 | 4661 | i915_gem_retire_requests(dev); |
673a394b | 4662 | |
29105ccc | 4663 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4664 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4665 | i915_gem_evict_everything(dev); |
29105ccc | 4666 | |
e3efda49 | 4667 | i915_gem_stop_ringbuffers(dev); |
29105ccc | 4668 | |
45c5f202 CW |
4669 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4670 | * We need to replace this with a semaphore, or something. | |
4671 | * And not confound ums.mm_suspended! | |
4672 | */ | |
4673 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4674 | DRIVER_MODESET); | |
4675 | mutex_unlock(&dev->struct_mutex); | |
4676 | ||
4677 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4678 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4679 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4680 | |
673a394b | 4681 | return 0; |
45c5f202 CW |
4682 | |
4683 | err: | |
4684 | mutex_unlock(&dev->struct_mutex); | |
4685 | return ret; | |
673a394b EA |
4686 | } |
4687 | ||
a4872ba6 | 4688 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4689 | { |
c3787e2e | 4690 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4691 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4692 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4693 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4694 | int i, ret; |
b9524a1e | 4695 | |
040d2baa | 4696 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4697 | return 0; |
b9524a1e | 4698 | |
c3787e2e BW |
4699 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4700 | if (ret) | |
4701 | return ret; | |
b9524a1e | 4702 | |
c3787e2e BW |
4703 | /* |
4704 | * Note: We do not worry about the concurrent register cacheline hang | |
4705 | * here because no other code should access these registers other than | |
4706 | * at initialization time. | |
4707 | */ | |
b9524a1e | 4708 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4709 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4710 | intel_ring_emit(ring, reg_base + i); | |
4711 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4712 | } |
4713 | ||
c3787e2e | 4714 | intel_ring_advance(ring); |
b9524a1e | 4715 | |
c3787e2e | 4716 | return ret; |
b9524a1e BW |
4717 | } |
4718 | ||
f691e2f4 DV |
4719 | void i915_gem_init_swizzling(struct drm_device *dev) |
4720 | { | |
3e31c6c0 | 4721 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4722 | |
11782b02 | 4723 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4724 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4725 | return; | |
4726 | ||
4727 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4728 | DISP_TILE_SURFACE_SWIZZLING); | |
4729 | ||
11782b02 DV |
4730 | if (IS_GEN5(dev)) |
4731 | return; | |
4732 | ||
f691e2f4 DV |
4733 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4734 | if (IS_GEN6(dev)) | |
6b26c86d | 4735 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4736 | else if (IS_GEN7(dev)) |
6b26c86d | 4737 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4738 | else if (IS_GEN8(dev)) |
4739 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4740 | else |
4741 | BUG(); | |
f691e2f4 | 4742 | } |
e21af88d | 4743 | |
67b1b571 CW |
4744 | static bool |
4745 | intel_enable_blt(struct drm_device *dev) | |
4746 | { | |
4747 | if (!HAS_BLT(dev)) | |
4748 | return false; | |
4749 | ||
4750 | /* The blitter was dysfunctional on early prototypes */ | |
4751 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4752 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4753 | " graphics performance will be degraded.\n"); | |
4754 | return false; | |
4755 | } | |
4756 | ||
4757 | return true; | |
4758 | } | |
4759 | ||
81e7f200 VS |
4760 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4761 | { | |
4762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4763 | ||
4764 | I915_WRITE(RING_CTL(base), 0); | |
4765 | I915_WRITE(RING_HEAD(base), 0); | |
4766 | I915_WRITE(RING_TAIL(base), 0); | |
4767 | I915_WRITE(RING_START(base), 0); | |
4768 | } | |
4769 | ||
4770 | static void init_unused_rings(struct drm_device *dev) | |
4771 | { | |
4772 | if (IS_I830(dev)) { | |
4773 | init_unused_ring(dev, PRB1_BASE); | |
4774 | init_unused_ring(dev, SRB0_BASE); | |
4775 | init_unused_ring(dev, SRB1_BASE); | |
4776 | init_unused_ring(dev, SRB2_BASE); | |
4777 | init_unused_ring(dev, SRB3_BASE); | |
4778 | } else if (IS_GEN2(dev)) { | |
4779 | init_unused_ring(dev, SRB0_BASE); | |
4780 | init_unused_ring(dev, SRB1_BASE); | |
4781 | } else if (IS_GEN3(dev)) { | |
4782 | init_unused_ring(dev, PRB1_BASE); | |
4783 | init_unused_ring(dev, PRB2_BASE); | |
4784 | } | |
4785 | } | |
4786 | ||
a83014d3 | 4787 | int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4788 | { |
4fc7c971 | 4789 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4790 | int ret; |
68f95ba9 | 4791 | |
81e7f200 VS |
4792 | /* |
4793 | * At least 830 can leave some of the unused rings | |
4794 | * "active" (ie. head != tail) after resume which | |
4795 | * will prevent c3 entry. Makes sure all unused rings | |
4796 | * are totally idle. | |
4797 | */ | |
4798 | init_unused_rings(dev); | |
4799 | ||
5c1143bb | 4800 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4801 | if (ret) |
b6913e4b | 4802 | return ret; |
68f95ba9 CW |
4803 | |
4804 | if (HAS_BSD(dev)) { | |
5c1143bb | 4805 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4806 | if (ret) |
4807 | goto cleanup_render_ring; | |
d1b851fc | 4808 | } |
68f95ba9 | 4809 | |
67b1b571 | 4810 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4811 | ret = intel_init_blt_ring_buffer(dev); |
4812 | if (ret) | |
4813 | goto cleanup_bsd_ring; | |
4814 | } | |
4815 | ||
9a8a2213 BW |
4816 | if (HAS_VEBOX(dev)) { |
4817 | ret = intel_init_vebox_ring_buffer(dev); | |
4818 | if (ret) | |
4819 | goto cleanup_blt_ring; | |
4820 | } | |
4821 | ||
845f74a7 ZY |
4822 | if (HAS_BSD2(dev)) { |
4823 | ret = intel_init_bsd2_ring_buffer(dev); | |
4824 | if (ret) | |
4825 | goto cleanup_vebox_ring; | |
4826 | } | |
9a8a2213 | 4827 | |
99433931 | 4828 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4829 | if (ret) |
845f74a7 | 4830 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4831 | |
4832 | return 0; | |
4833 | ||
845f74a7 ZY |
4834 | cleanup_bsd2_ring: |
4835 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4836 | cleanup_vebox_ring: |
4837 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4838 | cleanup_blt_ring: |
4839 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4840 | cleanup_bsd_ring: | |
4841 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4842 | cleanup_render_ring: | |
4843 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4844 | ||
4845 | return ret; | |
4846 | } | |
4847 | ||
4848 | int | |
4849 | i915_gem_init_hw(struct drm_device *dev) | |
4850 | { | |
3e31c6c0 | 4851 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4852 | int ret, i; |
4fc7c971 BW |
4853 | |
4854 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4855 | return -EIO; | |
4856 | ||
59124506 | 4857 | if (dev_priv->ellc_size) |
05e21cc4 | 4858 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4859 | |
0bf21347 VS |
4860 | if (IS_HASWELL(dev)) |
4861 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4862 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4863 | |
88a2b2a3 | 4864 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4865 | if (IS_IVYBRIDGE(dev)) { |
4866 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4867 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4868 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4869 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4870 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4871 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4872 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4873 | } | |
88a2b2a3 BW |
4874 | } |
4875 | ||
4fc7c971 BW |
4876 | i915_gem_init_swizzling(dev); |
4877 | ||
a83014d3 | 4878 | ret = dev_priv->gt.init_rings(dev); |
99433931 MK |
4879 | if (ret) |
4880 | return ret; | |
4881 | ||
c3787e2e BW |
4882 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4883 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4884 | ||
254f965c | 4885 | /* |
2fa48d8d BW |
4886 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4887 | * default context switch however is something we'd like to do after | |
4888 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4889 | * goes with our code better). Context switching requires rings (for | |
4890 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4891 | */ |
2fa48d8d | 4892 | ret = i915_gem_context_enable(dev_priv); |
60990320 | 4893 | if (ret && ret != -EIO) { |
2fa48d8d | 4894 | DRM_ERROR("Context enable failed %d\n", ret); |
60990320 | 4895 | i915_gem_cleanup_ringbuffer(dev); |
82460d97 DV |
4896 | |
4897 | return ret; | |
4898 | } | |
4899 | ||
4900 | ret = i915_ppgtt_init_hw(dev); | |
4901 | if (ret && ret != -EIO) { | |
4902 | DRM_ERROR("PPGTT enable failed %d\n", ret); | |
4903 | i915_gem_cleanup_ringbuffer(dev); | |
b7c36d25 | 4904 | } |
e21af88d | 4905 | |
2fa48d8d | 4906 | return ret; |
8187a2b7 ZN |
4907 | } |
4908 | ||
1070a42b CW |
4909 | int i915_gem_init(struct drm_device *dev) |
4910 | { | |
4911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4912 | int ret; |
4913 | ||
127f1003 OM |
4914 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4915 | i915.enable_execlists); | |
4916 | ||
1070a42b | 4917 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4918 | |
4919 | if (IS_VALLEYVIEW(dev)) { | |
4920 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4921 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4922 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4923 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4924 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4925 | } | |
4926 | ||
a83014d3 OM |
4927 | if (!i915.enable_execlists) { |
4928 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; | |
4929 | dev_priv->gt.init_rings = i915_gem_init_rings; | |
4930 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
4931 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
454afebd OM |
4932 | } else { |
4933 | dev_priv->gt.do_execbuf = intel_execlists_submission; | |
4934 | dev_priv->gt.init_rings = intel_logical_rings_init; | |
4935 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
4936 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
a83014d3 OM |
4937 | } |
4938 | ||
6c5566a8 DV |
4939 | ret = i915_gem_init_userptr(dev); |
4940 | if (ret) { | |
4941 | mutex_unlock(&dev->struct_mutex); | |
4942 | return ret; | |
4943 | } | |
4944 | ||
d7e5008f | 4945 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4946 | |
2fa48d8d | 4947 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4948 | if (ret) { |
4949 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4950 | return ret; |
e3848694 | 4951 | } |
2fa48d8d | 4952 | |
1070a42b | 4953 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4954 | if (ret == -EIO) { |
4955 | /* Allow ring initialisation to fail by marking the GPU as | |
4956 | * wedged. But we only want to do this where the GPU is angry, | |
4957 | * for all other failure, such as an allocation failure, bail. | |
4958 | */ | |
4959 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4960 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4961 | ret = 0; | |
1070a42b | 4962 | } |
60990320 | 4963 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4964 | |
60990320 | 4965 | return ret; |
1070a42b CW |
4966 | } |
4967 | ||
8187a2b7 ZN |
4968 | void |
4969 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4970 | { | |
3e31c6c0 | 4971 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4972 | struct intel_engine_cs *ring; |
1ec14ad3 | 4973 | int i; |
8187a2b7 | 4974 | |
b4519513 | 4975 | for_each_ring(ring, dev_priv, i) |
a83014d3 | 4976 | dev_priv->gt.cleanup_ring(ring); |
8187a2b7 ZN |
4977 | } |
4978 | ||
673a394b EA |
4979 | int |
4980 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4981 | struct drm_file *file_priv) | |
4982 | { | |
db1b76ca | 4983 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4984 | int ret; |
673a394b | 4985 | |
79e53945 JB |
4986 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4987 | return 0; | |
4988 | ||
1f83fee0 | 4989 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4990 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4991 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4992 | } |
4993 | ||
673a394b | 4994 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4995 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4996 | |
f691e2f4 | 4997 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4998 | if (ret != 0) { |
4999 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 5000 | return ret; |
d816f6ac | 5001 | } |
9bb2d6f9 | 5002 | |
5cef07e1 | 5003 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
dbb19d30 | 5004 | |
bb0f1b5c | 5005 | ret = drm_irq_install(dev, dev->pdev->irq); |
5f35308b CW |
5006 | if (ret) |
5007 | goto cleanup_ringbuffer; | |
e090c53b | 5008 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 5009 | |
673a394b | 5010 | return 0; |
5f35308b CW |
5011 | |
5012 | cleanup_ringbuffer: | |
5f35308b | 5013 | i915_gem_cleanup_ringbuffer(dev); |
db1b76ca | 5014 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
5015 | mutex_unlock(&dev->struct_mutex); |
5016 | ||
5017 | return ret; | |
673a394b EA |
5018 | } |
5019 | ||
5020 | int | |
5021 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
5022 | struct drm_file *file_priv) | |
5023 | { | |
79e53945 JB |
5024 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
5025 | return 0; | |
5026 | ||
e090c53b | 5027 | mutex_lock(&dev->struct_mutex); |
dbb19d30 | 5028 | drm_irq_uninstall(dev); |
e090c53b | 5029 | mutex_unlock(&dev->struct_mutex); |
db1b76ca | 5030 | |
45c5f202 | 5031 | return i915_gem_suspend(dev); |
673a394b EA |
5032 | } |
5033 | ||
5034 | void | |
5035 | i915_gem_lastclose(struct drm_device *dev) | |
5036 | { | |
5037 | int ret; | |
673a394b | 5038 | |
e806b495 EA |
5039 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
5040 | return; | |
5041 | ||
45c5f202 | 5042 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
5043 | if (ret) |
5044 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
5045 | } |
5046 | ||
64193406 | 5047 | static void |
a4872ba6 | 5048 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
5049 | { |
5050 | INIT_LIST_HEAD(&ring->active_list); | |
5051 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
5052 | } |
5053 | ||
7e0d96bc BW |
5054 | void i915_init_vm(struct drm_i915_private *dev_priv, |
5055 | struct i915_address_space *vm) | |
fc8c067e | 5056 | { |
7e0d96bc BW |
5057 | if (!i915_is_ggtt(vm)) |
5058 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
5059 | vm->dev = dev_priv->dev; |
5060 | INIT_LIST_HEAD(&vm->active_list); | |
5061 | INIT_LIST_HEAD(&vm->inactive_list); | |
5062 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 5063 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
5064 | } |
5065 | ||
673a394b EA |
5066 | void |
5067 | i915_gem_load(struct drm_device *dev) | |
5068 | { | |
3e31c6c0 | 5069 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
5070 | int i; |
5071 | ||
5072 | dev_priv->slab = | |
5073 | kmem_cache_create("i915_gem_object", | |
5074 | sizeof(struct drm_i915_gem_object), 0, | |
5075 | SLAB_HWCACHE_ALIGN, | |
5076 | NULL); | |
673a394b | 5077 | |
fc8c067e BW |
5078 | INIT_LIST_HEAD(&dev_priv->vm_list); |
5079 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
5080 | ||
a33afea5 | 5081 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
5082 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
5083 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 5084 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
5085 | for (i = 0; i < I915_NUM_RINGS; i++) |
5086 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 5087 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 5088 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
5089 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
5090 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
5091 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
5092 | i915_gem_idle_work_handler); | |
1f83fee0 | 5093 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 5094 | |
94400120 | 5095 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
dbb42748 | 5096 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
50743298 DV |
5097 | I915_WRITE(MI_ARB_STATE, |
5098 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
5099 | } |
5100 | ||
72bfa19c CW |
5101 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
5102 | ||
de151cf6 | 5103 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
5104 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
5105 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 5106 | |
42b5aeab VS |
5107 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
5108 | dev_priv->num_fence_regs = 32; | |
5109 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
5110 | dev_priv->num_fence_regs = 16; |
5111 | else | |
5112 | dev_priv->num_fence_regs = 8; | |
5113 | ||
b5aa8a0f | 5114 | /* Initialize fence registers to zero */ |
19b2dbde CW |
5115 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
5116 | i915_gem_restore_fences(dev); | |
10ed13e4 | 5117 | |
673a394b | 5118 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 5119 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 5120 | |
ce453d81 CW |
5121 | dev_priv->mm.interruptible = true; |
5122 | ||
ceabbba5 CW |
5123 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
5124 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
5125 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
5126 | register_shrinker(&dev_priv->mm.shrinker); | |
2cfcd32a CW |
5127 | |
5128 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; | |
5129 | register_oom_notifier(&dev_priv->mm.oom_notifier); | |
f99d7069 DV |
5130 | |
5131 | mutex_init(&dev_priv->fb_tracking.lock); | |
673a394b | 5132 | } |
71acb5eb | 5133 | |
f787a5f5 | 5134 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5135 | { |
f787a5f5 | 5136 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 5137 | |
b29c19b6 CW |
5138 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
5139 | ||
b962442e EA |
5140 | /* Clean up our request list when the client is going away, so that |
5141 | * later retire_requests won't dereference our soon-to-be-gone | |
5142 | * file_priv. | |
5143 | */ | |
1c25595f | 5144 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5145 | while (!list_empty(&file_priv->mm.request_list)) { |
5146 | struct drm_i915_gem_request *request; | |
5147 | ||
5148 | request = list_first_entry(&file_priv->mm.request_list, | |
5149 | struct drm_i915_gem_request, | |
5150 | client_list); | |
5151 | list_del(&request->client_list); | |
5152 | request->file_priv = NULL; | |
5153 | } | |
1c25595f | 5154 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5155 | } |
31169714 | 5156 | |
b29c19b6 CW |
5157 | static void |
5158 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
5159 | { | |
5160 | struct drm_i915_file_private *file_priv = | |
5161 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
5162 | ||
5163 | atomic_set(&file_priv->rps_wait_boost, false); | |
5164 | } | |
5165 | ||
5166 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5167 | { | |
5168 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5169 | int ret; |
b29c19b6 CW |
5170 | |
5171 | DRM_DEBUG_DRIVER("\n"); | |
5172 | ||
5173 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5174 | if (!file_priv) | |
5175 | return -ENOMEM; | |
5176 | ||
5177 | file->driver_priv = file_priv; | |
5178 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5179 | file_priv->file = file; |
b29c19b6 CW |
5180 | |
5181 | spin_lock_init(&file_priv->mm.lock); | |
5182 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
5183 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
5184 | i915_gem_file_idle_work_handler); | |
5185 | ||
e422b888 BW |
5186 | ret = i915_gem_context_open(dev, file); |
5187 | if (ret) | |
5188 | kfree(file_priv); | |
b29c19b6 | 5189 | |
e422b888 | 5190 | return ret; |
b29c19b6 CW |
5191 | } |
5192 | ||
b680c37a DV |
5193 | /** |
5194 | * i915_gem_track_fb - update frontbuffer tracking | |
5195 | * old: current GEM buffer for the frontbuffer slots | |
5196 | * new: new GEM buffer for the frontbuffer slots | |
5197 | * frontbuffer_bits: bitmask of frontbuffer slots | |
5198 | * | |
5199 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5200 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5201 | */ | |
a071fa00 DV |
5202 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5203 | struct drm_i915_gem_object *new, | |
5204 | unsigned frontbuffer_bits) | |
5205 | { | |
5206 | if (old) { | |
5207 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5208 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5209 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5210 | } | |
5211 | ||
5212 | if (new) { | |
5213 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5214 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5215 | new->frontbuffer_bits |= frontbuffer_bits; | |
5216 | } | |
5217 | } | |
5218 | ||
5774506f CW |
5219 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
5220 | { | |
5221 | if (!mutex_is_locked(mutex)) | |
5222 | return false; | |
5223 | ||
5224 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
5225 | return mutex->owner == task; | |
5226 | #else | |
5227 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5228 | return false; | |
5229 | #endif | |
5230 | } | |
5231 | ||
b453c4db CW |
5232 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
5233 | { | |
5234 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5235 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
5236 | return false; | |
5237 | ||
5238 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) | |
5239 | return false; | |
5240 | ||
5241 | *unlock = false; | |
5242 | } else | |
5243 | *unlock = true; | |
5244 | ||
5245 | return true; | |
5246 | } | |
5247 | ||
ceabbba5 CW |
5248 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5249 | { | |
5250 | struct i915_vma *vma; | |
5251 | int count = 0; | |
5252 | ||
5253 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5254 | if (drm_mm_node_allocated(&vma->node)) | |
5255 | count++; | |
5256 | ||
5257 | return count; | |
5258 | } | |
5259 | ||
7dc19d5a | 5260 | static unsigned long |
ceabbba5 | 5261 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5262 | { |
17250b71 | 5263 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5264 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5265 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5266 | struct drm_i915_gem_object *obj; |
7dc19d5a | 5267 | unsigned long count; |
b453c4db | 5268 | bool unlock; |
17250b71 | 5269 | |
b453c4db CW |
5270 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5271 | return 0; | |
31169714 | 5272 | |
7dc19d5a | 5273 | count = 0; |
35c20a60 | 5274 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5275 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5276 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5277 | |
5278 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5279 | if (!i915_gem_obj_is_pinned(obj) && |
5280 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5281 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5282 | } |
17250b71 | 5283 | |
5774506f CW |
5284 | if (unlock) |
5285 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5286 | |
7dc19d5a | 5287 | return count; |
31169714 | 5288 | } |
a70a3148 BW |
5289 | |
5290 | /* All the new VM stuff */ | |
5291 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5292 | struct i915_address_space *vm) | |
5293 | { | |
5294 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5295 | struct i915_vma *vma; | |
5296 | ||
896ab1a5 | 5297 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5298 | |
a70a3148 BW |
5299 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
5300 | if (vma->vm == vm) | |
5301 | return vma->node.start; | |
5302 | ||
5303 | } | |
f25748ea DV |
5304 | WARN(1, "%s vma for this object not found.\n", |
5305 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5306 | return -1; |
5307 | } | |
5308 | ||
5309 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5310 | struct i915_address_space *vm) | |
5311 | { | |
5312 | struct i915_vma *vma; | |
5313 | ||
5314 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5315 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5316 | return true; |
5317 | ||
5318 | return false; | |
5319 | } | |
5320 | ||
5321 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5322 | { | |
5a1d5eb0 | 5323 | struct i915_vma *vma; |
a70a3148 | 5324 | |
5a1d5eb0 CW |
5325 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5326 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5327 | return true; |
5328 | ||
5329 | return false; | |
5330 | } | |
5331 | ||
5332 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5333 | struct i915_address_space *vm) | |
5334 | { | |
5335 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5336 | struct i915_vma *vma; | |
5337 | ||
896ab1a5 | 5338 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5339 | |
5340 | BUG_ON(list_empty(&o->vma_list)); | |
5341 | ||
5342 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5343 | if (vma->vm == vm) | |
5344 | return vma->node.size; | |
5345 | ||
5346 | return 0; | |
5347 | } | |
5348 | ||
7dc19d5a | 5349 | static unsigned long |
ceabbba5 | 5350 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5351 | { |
5352 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5353 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5354 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a | 5355 | unsigned long freed; |
b453c4db | 5356 | bool unlock; |
7dc19d5a | 5357 | |
b453c4db CW |
5358 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5359 | return SHRINK_STOP; | |
7dc19d5a | 5360 | |
21ab4e74 CW |
5361 | freed = i915_gem_shrink(dev_priv, |
5362 | sc->nr_to_scan, | |
5363 | I915_SHRINK_BOUND | | |
5364 | I915_SHRINK_UNBOUND | | |
5365 | I915_SHRINK_PURGEABLE); | |
d9973b43 | 5366 | if (freed < sc->nr_to_scan) |
21ab4e74 CW |
5367 | freed += i915_gem_shrink(dev_priv, |
5368 | sc->nr_to_scan - freed, | |
5369 | I915_SHRINK_BOUND | | |
5370 | I915_SHRINK_UNBOUND); | |
7dc19d5a DC |
5371 | if (unlock) |
5372 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5373 | |
7dc19d5a DC |
5374 | return freed; |
5375 | } | |
5c2abbea | 5376 | |
2cfcd32a CW |
5377 | static int |
5378 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) | |
5379 | { | |
5380 | struct drm_i915_private *dev_priv = | |
5381 | container_of(nb, struct drm_i915_private, mm.oom_notifier); | |
5382 | struct drm_device *dev = dev_priv->dev; | |
5383 | struct drm_i915_gem_object *obj; | |
5384 | unsigned long timeout = msecs_to_jiffies(5000) + 1; | |
005445c5 | 5385 | unsigned long pinned, bound, unbound, freed_pages; |
2cfcd32a CW |
5386 | bool was_interruptible; |
5387 | bool unlock; | |
5388 | ||
a1db2fa7 | 5389 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) { |
2cfcd32a | 5390 | schedule_timeout_killable(1); |
a1db2fa7 CW |
5391 | if (fatal_signal_pending(current)) |
5392 | return NOTIFY_DONE; | |
5393 | } | |
2cfcd32a CW |
5394 | if (timeout == 0) { |
5395 | pr_err("Unable to purge GPU memory due lock contention.\n"); | |
5396 | return NOTIFY_DONE; | |
5397 | } | |
5398 | ||
5399 | was_interruptible = dev_priv->mm.interruptible; | |
5400 | dev_priv->mm.interruptible = false; | |
5401 | ||
005445c5 | 5402 | freed_pages = i915_gem_shrink_all(dev_priv); |
2cfcd32a CW |
5403 | |
5404 | dev_priv->mm.interruptible = was_interruptible; | |
5405 | ||
5406 | /* Because we may be allocating inside our own driver, we cannot | |
5407 | * assert that there are no objects with pinned pages that are not | |
5408 | * being pointed to by hardware. | |
5409 | */ | |
5410 | unbound = bound = pinned = 0; | |
5411 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5412 | if (!obj->base.filp) /* not backed by a freeable object */ | |
5413 | continue; | |
5414 | ||
5415 | if (obj->pages_pin_count) | |
5416 | pinned += obj->base.size; | |
5417 | else | |
5418 | unbound += obj->base.size; | |
5419 | } | |
5420 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5421 | if (!obj->base.filp) | |
5422 | continue; | |
5423 | ||
5424 | if (obj->pages_pin_count) | |
5425 | pinned += obj->base.size; | |
5426 | else | |
5427 | bound += obj->base.size; | |
5428 | } | |
5429 | ||
5430 | if (unlock) | |
5431 | mutex_unlock(&dev->struct_mutex); | |
5432 | ||
bb9059d3 CW |
5433 | if (freed_pages || unbound || bound) |
5434 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", | |
5435 | freed_pages << PAGE_SHIFT, pinned); | |
2cfcd32a CW |
5436 | if (unbound || bound) |
5437 | pr_err("%lu and %lu bytes still available in the " | |
5438 | "bound and unbound GPU page lists.\n", | |
5439 | bound, unbound); | |
5440 | ||
005445c5 | 5441 | *(unsigned long *)ptr += freed_pages; |
2cfcd32a CW |
5442 | return NOTIFY_DONE; |
5443 | } | |
5444 | ||
5c2abbea BW |
5445 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
5446 | { | |
5447 | struct i915_vma *vma; | |
5448 | ||
5c2abbea | 5449 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
5dc383b0 | 5450 | if (vma->vm != i915_obj_to_ggtt(obj)) |
5c2abbea BW |
5451 | return NULL; |
5452 | ||
5453 | return vma; | |
5454 | } |