Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
0ccdacf6 | 35 | #include "intel_mocs.h" |
5949eac4 | 36 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
673a394b | 38 | #include <linux/swap.h> |
79e53945 | 39 | #include <linux/pci.h> |
1286ff73 | 40 | #include <linux/dma-buf.h> |
673a394b | 41 | |
05394f39 | 42 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 43 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
c8725f3d | 44 | static void |
b4716185 CW |
45 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
46 | static void | |
47 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); | |
61050808 | 48 | |
c76ce038 CW |
49 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
50 | enum i915_cache_level level) | |
51 | { | |
52 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
53 | } | |
54 | ||
2c22569b CW |
55 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
56 | { | |
57 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
58 | return true; | |
59 | ||
60 | return obj->pin_display; | |
61 | } | |
62 | ||
73aa808f CW |
63 | /* some bookkeeping */ |
64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
65 | size_t size) | |
66 | { | |
c20e8355 | 67 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
68 | dev_priv->mm.object_count++; |
69 | dev_priv->mm.object_memory += size; | |
c20e8355 | 70 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
71 | } |
72 | ||
73 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
74 | size_t size) | |
75 | { | |
c20e8355 | 76 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
77 | dev_priv->mm.object_count--; |
78 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 79 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
80 | } |
81 | ||
21dd3734 | 82 | static int |
33196ded | 83 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 84 | { |
30dbf0c0 CW |
85 | int ret; |
86 | ||
d98c52cf | 87 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
88 | return 0; |
89 | ||
0a6759c6 DV |
90 | /* |
91 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
92 | * userspace. If it takes that long something really bad is going on and | |
93 | * we should simply try to bail out and fail as gracefully as possible. | |
94 | */ | |
1f83fee0 | 95 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 96 | !i915_reset_in_progress(error), |
1f83fee0 | 97 | 10*HZ); |
0a6759c6 DV |
98 | if (ret == 0) { |
99 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
100 | return -EIO; | |
101 | } else if (ret < 0) { | |
30dbf0c0 | 102 | return ret; |
d98c52cf CW |
103 | } else { |
104 | return 0; | |
0a6759c6 | 105 | } |
30dbf0c0 CW |
106 | } |
107 | ||
54cf91dc | 108 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 109 | { |
33196ded | 110 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
111 | int ret; |
112 | ||
33196ded | 113 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
114 | if (ret) |
115 | return ret; | |
116 | ||
117 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
118 | if (ret) | |
119 | return ret; | |
120 | ||
23bc5982 | 121 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
122 | return 0; |
123 | } | |
30dbf0c0 | 124 | |
5a125c3c EA |
125 | int |
126 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 127 | struct drm_file *file) |
5a125c3c | 128 | { |
72e96d64 | 129 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 130 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 131 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 132 | struct i915_vma *vma; |
6299f992 | 133 | size_t pinned; |
5a125c3c | 134 | |
6299f992 | 135 | pinned = 0; |
73aa808f | 136 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 137 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
ca1543be TU |
138 | if (vma->pin_count) |
139 | pinned += vma->node.size; | |
1c7f4bca | 140 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
ca1543be TU |
141 | if (vma->pin_count) |
142 | pinned += vma->node.size; | |
73aa808f | 143 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 144 | |
72e96d64 | 145 | args->aper_size = ggtt->base.total; |
0206e353 | 146 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 147 | |
5a125c3c EA |
148 | return 0; |
149 | } | |
150 | ||
6a2c4232 CW |
151 | static int |
152 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 153 | { |
6a2c4232 CW |
154 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
155 | char *vaddr = obj->phys_handle->vaddr; | |
156 | struct sg_table *st; | |
157 | struct scatterlist *sg; | |
158 | int i; | |
00731155 | 159 | |
6a2c4232 CW |
160 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
161 | return -EINVAL; | |
162 | ||
163 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
164 | struct page *page; | |
165 | char *src; | |
166 | ||
167 | page = shmem_read_mapping_page(mapping, i); | |
168 | if (IS_ERR(page)) | |
169 | return PTR_ERR(page); | |
170 | ||
171 | src = kmap_atomic(page); | |
172 | memcpy(vaddr, src, PAGE_SIZE); | |
173 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
174 | kunmap_atomic(src); | |
175 | ||
09cbfeaf | 176 | put_page(page); |
6a2c4232 CW |
177 | vaddr += PAGE_SIZE; |
178 | } | |
179 | ||
c033666a | 180 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
181 | |
182 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
183 | if (st == NULL) | |
184 | return -ENOMEM; | |
185 | ||
186 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
187 | kfree(st); | |
188 | return -ENOMEM; | |
189 | } | |
190 | ||
191 | sg = st->sgl; | |
192 | sg->offset = 0; | |
193 | sg->length = obj->base.size; | |
00731155 | 194 | |
6a2c4232 CW |
195 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
196 | sg_dma_len(sg) = obj->base.size; | |
197 | ||
198 | obj->pages = st; | |
6a2c4232 CW |
199 | return 0; |
200 | } | |
201 | ||
202 | static void | |
203 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
204 | { | |
205 | int ret; | |
206 | ||
207 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 208 | |
6a2c4232 | 209 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 210 | if (WARN_ON(ret)) { |
6a2c4232 CW |
211 | /* In the event of a disaster, abandon all caches and |
212 | * hope for the best. | |
213 | */ | |
6a2c4232 CW |
214 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
215 | } | |
216 | ||
217 | if (obj->madv == I915_MADV_DONTNEED) | |
218 | obj->dirty = 0; | |
219 | ||
220 | if (obj->dirty) { | |
00731155 | 221 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 222 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
223 | int i; |
224 | ||
225 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
226 | struct page *page; |
227 | char *dst; | |
228 | ||
229 | page = shmem_read_mapping_page(mapping, i); | |
230 | if (IS_ERR(page)) | |
231 | continue; | |
232 | ||
233 | dst = kmap_atomic(page); | |
234 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
235 | memcpy(dst, vaddr, PAGE_SIZE); | |
236 | kunmap_atomic(dst); | |
237 | ||
238 | set_page_dirty(page); | |
239 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 240 | mark_page_accessed(page); |
09cbfeaf | 241 | put_page(page); |
00731155 CW |
242 | vaddr += PAGE_SIZE; |
243 | } | |
6a2c4232 | 244 | obj->dirty = 0; |
00731155 CW |
245 | } |
246 | ||
6a2c4232 CW |
247 | sg_free_table(obj->pages); |
248 | kfree(obj->pages); | |
6a2c4232 CW |
249 | } |
250 | ||
251 | static void | |
252 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
253 | { | |
254 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
255 | } | |
256 | ||
257 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
258 | .get_pages = i915_gem_object_get_pages_phys, | |
259 | .put_pages = i915_gem_object_put_pages_phys, | |
260 | .release = i915_gem_object_release_phys, | |
261 | }; | |
262 | ||
263 | static int | |
264 | drop_pages(struct drm_i915_gem_object *obj) | |
265 | { | |
266 | struct i915_vma *vma, *next; | |
267 | int ret; | |
268 | ||
269 | drm_gem_object_reference(&obj->base); | |
1c7f4bca | 270 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) |
6a2c4232 CW |
271 | if (i915_vma_unbind(vma)) |
272 | break; | |
273 | ||
274 | ret = i915_gem_object_put_pages(obj); | |
275 | drm_gem_object_unreference(&obj->base); | |
276 | ||
277 | return ret; | |
00731155 CW |
278 | } |
279 | ||
280 | int | |
281 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
282 | int align) | |
283 | { | |
284 | drm_dma_handle_t *phys; | |
6a2c4232 | 285 | int ret; |
00731155 CW |
286 | |
287 | if (obj->phys_handle) { | |
288 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
289 | return -EBUSY; | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | if (obj->madv != I915_MADV_WILLNEED) | |
295 | return -EFAULT; | |
296 | ||
297 | if (obj->base.filp == NULL) | |
298 | return -EINVAL; | |
299 | ||
6a2c4232 CW |
300 | ret = drop_pages(obj); |
301 | if (ret) | |
302 | return ret; | |
303 | ||
00731155 CW |
304 | /* create a new object */ |
305 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
306 | if (!phys) | |
307 | return -ENOMEM; | |
308 | ||
00731155 | 309 | obj->phys_handle = phys; |
6a2c4232 CW |
310 | obj->ops = &i915_gem_phys_ops; |
311 | ||
312 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
313 | } |
314 | ||
315 | static int | |
316 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
317 | struct drm_i915_gem_pwrite *args, | |
318 | struct drm_file *file_priv) | |
319 | { | |
320 | struct drm_device *dev = obj->base.dev; | |
321 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 322 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
063e4e6b | 323 | int ret = 0; |
6a2c4232 CW |
324 | |
325 | /* We manually control the domain here and pretend that it | |
326 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
327 | */ | |
328 | ret = i915_gem_object_wait_rendering(obj, false); | |
329 | if (ret) | |
330 | return ret; | |
00731155 | 331 | |
77a0d1ca | 332 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
333 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
334 | unsigned long unwritten; | |
335 | ||
336 | /* The physical object once assigned is fixed for the lifetime | |
337 | * of the obj, so we can safely drop the lock and continue | |
338 | * to access vaddr. | |
339 | */ | |
340 | mutex_unlock(&dev->struct_mutex); | |
341 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
342 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
343 | if (unwritten) { |
344 | ret = -EFAULT; | |
345 | goto out; | |
346 | } | |
00731155 CW |
347 | } |
348 | ||
6a2c4232 | 349 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 350 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
351 | |
352 | out: | |
de152b62 | 353 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 354 | return ret; |
00731155 CW |
355 | } |
356 | ||
42dcedd4 CW |
357 | void *i915_gem_object_alloc(struct drm_device *dev) |
358 | { | |
359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
efab6d8d | 360 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
361 | } |
362 | ||
363 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
364 | { | |
365 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
efab6d8d | 366 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
367 | } |
368 | ||
ff72145b DA |
369 | static int |
370 | i915_gem_create(struct drm_file *file, | |
371 | struct drm_device *dev, | |
372 | uint64_t size, | |
373 | uint32_t *handle_p) | |
673a394b | 374 | { |
05394f39 | 375 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
376 | int ret; |
377 | u32 handle; | |
673a394b | 378 | |
ff72145b | 379 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
380 | if (size == 0) |
381 | return -EINVAL; | |
673a394b EA |
382 | |
383 | /* Allocate the new object */ | |
d37cd8a8 | 384 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
385 | if (IS_ERR(obj)) |
386 | return PTR_ERR(obj); | |
673a394b | 387 | |
05394f39 | 388 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 389 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
390 | drm_gem_object_unreference_unlocked(&obj->base); |
391 | if (ret) | |
392 | return ret; | |
202f2fef | 393 | |
ff72145b | 394 | *handle_p = handle; |
673a394b EA |
395 | return 0; |
396 | } | |
397 | ||
ff72145b DA |
398 | int |
399 | i915_gem_dumb_create(struct drm_file *file, | |
400 | struct drm_device *dev, | |
401 | struct drm_mode_create_dumb *args) | |
402 | { | |
403 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 404 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
405 | args->size = args->pitch * args->height; |
406 | return i915_gem_create(file, dev, | |
da6b51d0 | 407 | args->size, &args->handle); |
ff72145b DA |
408 | } |
409 | ||
ff72145b DA |
410 | /** |
411 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
412 | * @dev: drm device pointer |
413 | * @data: ioctl data blob | |
414 | * @file: drm file pointer | |
ff72145b DA |
415 | */ |
416 | int | |
417 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
418 | struct drm_file *file) | |
419 | { | |
420 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 421 | |
ff72145b | 422 | return i915_gem_create(file, dev, |
da6b51d0 | 423 | args->size, &args->handle); |
ff72145b DA |
424 | } |
425 | ||
8461d226 DV |
426 | static inline int |
427 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
428 | const char *gpu_vaddr, int gpu_offset, | |
429 | int length) | |
430 | { | |
431 | int ret, cpu_offset = 0; | |
432 | ||
433 | while (length > 0) { | |
434 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
435 | int this_length = min(cacheline_end - gpu_offset, length); | |
436 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
437 | ||
438 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
439 | gpu_vaddr + swizzled_gpu_offset, | |
440 | this_length); | |
441 | if (ret) | |
442 | return ret + length; | |
443 | ||
444 | cpu_offset += this_length; | |
445 | gpu_offset += this_length; | |
446 | length -= this_length; | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
8c59967c | 452 | static inline int |
4f0c7cfb BW |
453 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
454 | const char __user *cpu_vaddr, | |
8c59967c DV |
455 | int length) |
456 | { | |
457 | int ret, cpu_offset = 0; | |
458 | ||
459 | while (length > 0) { | |
460 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
461 | int this_length = min(cacheline_end - gpu_offset, length); | |
462 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
463 | ||
464 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
465 | cpu_vaddr + cpu_offset, | |
466 | this_length); | |
467 | if (ret) | |
468 | return ret + length; | |
469 | ||
470 | cpu_offset += this_length; | |
471 | gpu_offset += this_length; | |
472 | length -= this_length; | |
473 | } | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
4c914c0c BV |
478 | /* |
479 | * Pins the specified object's pages and synchronizes the object with | |
480 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
481 | * flush the object from the CPU cache. | |
482 | */ | |
483 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
484 | int *needs_clflush) | |
485 | { | |
486 | int ret; | |
487 | ||
488 | *needs_clflush = 0; | |
489 | ||
1db6e2e7 | 490 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
4c914c0c BV |
491 | return -EINVAL; |
492 | ||
493 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
494 | /* If we're not in the cpu read domain, set ourself into the gtt | |
495 | * read domain and manually flush cachelines (if required). This | |
496 | * optimizes for the case when the gpu will dirty the data | |
497 | * anyway again before the next pread happens. */ | |
498 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
499 | obj->cache_level); | |
500 | ret = i915_gem_object_wait_rendering(obj, true); | |
501 | if (ret) | |
502 | return ret; | |
503 | } | |
504 | ||
505 | ret = i915_gem_object_get_pages(obj); | |
506 | if (ret) | |
507 | return ret; | |
508 | ||
509 | i915_gem_object_pin_pages(obj); | |
510 | ||
511 | return ret; | |
512 | } | |
513 | ||
d174bd64 DV |
514 | /* Per-page copy function for the shmem pread fastpath. |
515 | * Flushes invalid cachelines before reading the target if | |
516 | * needs_clflush is set. */ | |
eb01459f | 517 | static int |
d174bd64 DV |
518 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
519 | char __user *user_data, | |
520 | bool page_do_bit17_swizzling, bool needs_clflush) | |
521 | { | |
522 | char *vaddr; | |
523 | int ret; | |
524 | ||
e7e58eb5 | 525 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
526 | return -EINVAL; |
527 | ||
528 | vaddr = kmap_atomic(page); | |
529 | if (needs_clflush) | |
530 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
531 | page_length); | |
532 | ret = __copy_to_user_inatomic(user_data, | |
533 | vaddr + shmem_page_offset, | |
534 | page_length); | |
535 | kunmap_atomic(vaddr); | |
536 | ||
f60d7f0c | 537 | return ret ? -EFAULT : 0; |
d174bd64 DV |
538 | } |
539 | ||
23c18c71 DV |
540 | static void |
541 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
542 | bool swizzled) | |
543 | { | |
e7e58eb5 | 544 | if (unlikely(swizzled)) { |
23c18c71 DV |
545 | unsigned long start = (unsigned long) addr; |
546 | unsigned long end = (unsigned long) addr + length; | |
547 | ||
548 | /* For swizzling simply ensure that we always flush both | |
549 | * channels. Lame, but simple and it works. Swizzled | |
550 | * pwrite/pread is far from a hotpath - current userspace | |
551 | * doesn't use it at all. */ | |
552 | start = round_down(start, 128); | |
553 | end = round_up(end, 128); | |
554 | ||
555 | drm_clflush_virt_range((void *)start, end - start); | |
556 | } else { | |
557 | drm_clflush_virt_range(addr, length); | |
558 | } | |
559 | ||
560 | } | |
561 | ||
d174bd64 DV |
562 | /* Only difference to the fast-path function is that this can handle bit17 |
563 | * and uses non-atomic copy and kmap functions. */ | |
564 | static int | |
565 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
566 | char __user *user_data, | |
567 | bool page_do_bit17_swizzling, bool needs_clflush) | |
568 | { | |
569 | char *vaddr; | |
570 | int ret; | |
571 | ||
572 | vaddr = kmap(page); | |
573 | if (needs_clflush) | |
23c18c71 DV |
574 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
575 | page_length, | |
576 | page_do_bit17_swizzling); | |
d174bd64 DV |
577 | |
578 | if (page_do_bit17_swizzling) | |
579 | ret = __copy_to_user_swizzled(user_data, | |
580 | vaddr, shmem_page_offset, | |
581 | page_length); | |
582 | else | |
583 | ret = __copy_to_user(user_data, | |
584 | vaddr + shmem_page_offset, | |
585 | page_length); | |
586 | kunmap(page); | |
587 | ||
f60d7f0c | 588 | return ret ? - EFAULT : 0; |
d174bd64 DV |
589 | } |
590 | ||
eb01459f | 591 | static int |
dbf7bff0 DV |
592 | i915_gem_shmem_pread(struct drm_device *dev, |
593 | struct drm_i915_gem_object *obj, | |
594 | struct drm_i915_gem_pread *args, | |
595 | struct drm_file *file) | |
eb01459f | 596 | { |
8461d226 | 597 | char __user *user_data; |
eb01459f | 598 | ssize_t remain; |
8461d226 | 599 | loff_t offset; |
eb2c0c81 | 600 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 601 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 602 | int prefaulted = 0; |
8489731c | 603 | int needs_clflush = 0; |
67d5a50c | 604 | struct sg_page_iter sg_iter; |
eb01459f | 605 | |
3ed605bc | 606 | user_data = u64_to_user_ptr(args->data_ptr); |
eb01459f EA |
607 | remain = args->size; |
608 | ||
8461d226 | 609 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 610 | |
4c914c0c | 611 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
612 | if (ret) |
613 | return ret; | |
614 | ||
8461d226 | 615 | offset = args->offset; |
eb01459f | 616 | |
67d5a50c ID |
617 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
618 | offset >> PAGE_SHIFT) { | |
2db76d7c | 619 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
620 | |
621 | if (remain <= 0) | |
622 | break; | |
623 | ||
eb01459f EA |
624 | /* Operation in this page |
625 | * | |
eb01459f | 626 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
627 | * page_length = bytes to copy for this page |
628 | */ | |
c8cbbb8b | 629 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
630 | page_length = remain; |
631 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
632 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 633 | |
8461d226 DV |
634 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
635 | (page_to_phys(page) & (1 << 17)) != 0; | |
636 | ||
d174bd64 DV |
637 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
638 | user_data, page_do_bit17_swizzling, | |
639 | needs_clflush); | |
640 | if (ret == 0) | |
641 | goto next_page; | |
dbf7bff0 | 642 | |
dbf7bff0 DV |
643 | mutex_unlock(&dev->struct_mutex); |
644 | ||
d330a953 | 645 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 646 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
647 | /* Userspace is tricking us, but we've already clobbered |
648 | * its pages with the prefault and promised to write the | |
649 | * data up to the first fault. Hence ignore any errors | |
650 | * and just continue. */ | |
651 | (void)ret; | |
652 | prefaulted = 1; | |
653 | } | |
eb01459f | 654 | |
d174bd64 DV |
655 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
656 | user_data, page_do_bit17_swizzling, | |
657 | needs_clflush); | |
eb01459f | 658 | |
dbf7bff0 | 659 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 660 | |
f60d7f0c | 661 | if (ret) |
8461d226 | 662 | goto out; |
8461d226 | 663 | |
17793c9a | 664 | next_page: |
eb01459f | 665 | remain -= page_length; |
8461d226 | 666 | user_data += page_length; |
eb01459f EA |
667 | offset += page_length; |
668 | } | |
669 | ||
4f27b75d | 670 | out: |
f60d7f0c CW |
671 | i915_gem_object_unpin_pages(obj); |
672 | ||
eb01459f EA |
673 | return ret; |
674 | } | |
675 | ||
673a394b EA |
676 | /** |
677 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
678 | * @dev: drm device pointer |
679 | * @data: ioctl data blob | |
680 | * @file: drm file pointer | |
673a394b EA |
681 | * |
682 | * On error, the contents of *data are undefined. | |
683 | */ | |
684 | int | |
685 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 686 | struct drm_file *file) |
673a394b EA |
687 | { |
688 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 689 | struct drm_i915_gem_object *obj; |
35b62a89 | 690 | int ret = 0; |
673a394b | 691 | |
51311d0a CW |
692 | if (args->size == 0) |
693 | return 0; | |
694 | ||
695 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 696 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
697 | args->size)) |
698 | return -EFAULT; | |
699 | ||
4f27b75d | 700 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 701 | if (ret) |
4f27b75d | 702 | return ret; |
673a394b | 703 | |
a8ad0bd8 | 704 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 705 | if (&obj->base == NULL) { |
1d7cfea1 CW |
706 | ret = -ENOENT; |
707 | goto unlock; | |
4f27b75d | 708 | } |
673a394b | 709 | |
7dcd2499 | 710 | /* Bounds check source. */ |
05394f39 CW |
711 | if (args->offset > obj->base.size || |
712 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 713 | ret = -EINVAL; |
35b62a89 | 714 | goto out; |
ce9d419d CW |
715 | } |
716 | ||
1286ff73 DV |
717 | /* prime objects have no backing filp to GEM pread/pwrite |
718 | * pages from. | |
719 | */ | |
720 | if (!obj->base.filp) { | |
721 | ret = -EINVAL; | |
722 | goto out; | |
723 | } | |
724 | ||
db53a302 CW |
725 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
726 | ||
dbf7bff0 | 727 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 728 | |
35b62a89 | 729 | out: |
05394f39 | 730 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 731 | unlock: |
4f27b75d | 732 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 733 | return ret; |
673a394b EA |
734 | } |
735 | ||
0839ccb8 KP |
736 | /* This is the fast write path which cannot handle |
737 | * page faults in the source data | |
9b7530cc | 738 | */ |
0839ccb8 KP |
739 | |
740 | static inline int | |
741 | fast_user_write(struct io_mapping *mapping, | |
742 | loff_t page_base, int page_offset, | |
743 | char __user *user_data, | |
744 | int length) | |
9b7530cc | 745 | { |
4f0c7cfb BW |
746 | void __iomem *vaddr_atomic; |
747 | void *vaddr; | |
0839ccb8 | 748 | unsigned long unwritten; |
9b7530cc | 749 | |
3e4d3af5 | 750 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
751 | /* We can use the cpu mem copy function because this is X86. */ |
752 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
753 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 754 | user_data, length); |
3e4d3af5 | 755 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 756 | return unwritten; |
0839ccb8 KP |
757 | } |
758 | ||
3de09aa3 EA |
759 | /** |
760 | * This is the fast pwrite path, where we copy the data directly from the | |
761 | * user into the GTT, uncached. | |
14bb2c11 TU |
762 | * @dev: drm device pointer |
763 | * @obj: i915 gem object | |
764 | * @args: pwrite arguments structure | |
765 | * @file: drm file pointer | |
3de09aa3 | 766 | */ |
673a394b | 767 | static int |
05394f39 CW |
768 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
769 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 770 | struct drm_i915_gem_pwrite *args, |
05394f39 | 771 | struct drm_file *file) |
673a394b | 772 | { |
72e96d64 JL |
773 | struct drm_i915_private *dev_priv = to_i915(dev); |
774 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
673a394b | 775 | ssize_t remain; |
0839ccb8 | 776 | loff_t offset, page_base; |
673a394b | 777 | char __user *user_data; |
935aaa69 DV |
778 | int page_offset, page_length, ret; |
779 | ||
1ec9e26d | 780 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
781 | if (ret) |
782 | goto out; | |
783 | ||
784 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
785 | if (ret) | |
786 | goto out_unpin; | |
787 | ||
788 | ret = i915_gem_object_put_fence(obj); | |
789 | if (ret) | |
790 | goto out_unpin; | |
673a394b | 791 | |
3ed605bc | 792 | user_data = u64_to_user_ptr(args->data_ptr); |
673a394b | 793 | remain = args->size; |
673a394b | 794 | |
f343c5f6 | 795 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b | 796 | |
77a0d1ca | 797 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
063e4e6b | 798 | |
673a394b EA |
799 | while (remain > 0) { |
800 | /* Operation in this page | |
801 | * | |
0839ccb8 KP |
802 | * page_base = page offset within aperture |
803 | * page_offset = offset within page | |
804 | * page_length = bytes to copy for this page | |
673a394b | 805 | */ |
c8cbbb8b CW |
806 | page_base = offset & PAGE_MASK; |
807 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
808 | page_length = remain; |
809 | if ((page_offset + remain) > PAGE_SIZE) | |
810 | page_length = PAGE_SIZE - page_offset; | |
811 | ||
0839ccb8 | 812 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
813 | * source page isn't available. Return the error and we'll |
814 | * retry in the slow path. | |
0839ccb8 | 815 | */ |
72e96d64 | 816 | if (fast_user_write(ggtt->mappable, page_base, |
935aaa69 DV |
817 | page_offset, user_data, page_length)) { |
818 | ret = -EFAULT; | |
063e4e6b | 819 | goto out_flush; |
935aaa69 | 820 | } |
673a394b | 821 | |
0839ccb8 KP |
822 | remain -= page_length; |
823 | user_data += page_length; | |
824 | offset += page_length; | |
673a394b | 825 | } |
673a394b | 826 | |
063e4e6b | 827 | out_flush: |
de152b62 | 828 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 829 | out_unpin: |
d7f46fc4 | 830 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 831 | out: |
3de09aa3 | 832 | return ret; |
673a394b EA |
833 | } |
834 | ||
d174bd64 DV |
835 | /* Per-page copy function for the shmem pwrite fastpath. |
836 | * Flushes invalid cachelines before writing to the target if | |
837 | * needs_clflush_before is set and flushes out any written cachelines after | |
838 | * writing if needs_clflush is set. */ | |
3043c60c | 839 | static int |
d174bd64 DV |
840 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
841 | char __user *user_data, | |
842 | bool page_do_bit17_swizzling, | |
843 | bool needs_clflush_before, | |
844 | bool needs_clflush_after) | |
673a394b | 845 | { |
d174bd64 | 846 | char *vaddr; |
673a394b | 847 | int ret; |
3de09aa3 | 848 | |
e7e58eb5 | 849 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 850 | return -EINVAL; |
3de09aa3 | 851 | |
d174bd64 DV |
852 | vaddr = kmap_atomic(page); |
853 | if (needs_clflush_before) | |
854 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
855 | page_length); | |
c2831a94 CW |
856 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
857 | user_data, page_length); | |
d174bd64 DV |
858 | if (needs_clflush_after) |
859 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
860 | page_length); | |
861 | kunmap_atomic(vaddr); | |
3de09aa3 | 862 | |
755d2218 | 863 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
864 | } |
865 | ||
d174bd64 DV |
866 | /* Only difference to the fast-path function is that this can handle bit17 |
867 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 868 | static int |
d174bd64 DV |
869 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
870 | char __user *user_data, | |
871 | bool page_do_bit17_swizzling, | |
872 | bool needs_clflush_before, | |
873 | bool needs_clflush_after) | |
673a394b | 874 | { |
d174bd64 DV |
875 | char *vaddr; |
876 | int ret; | |
e5281ccd | 877 | |
d174bd64 | 878 | vaddr = kmap(page); |
e7e58eb5 | 879 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
880 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
881 | page_length, | |
882 | page_do_bit17_swizzling); | |
d174bd64 DV |
883 | if (page_do_bit17_swizzling) |
884 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
885 | user_data, |
886 | page_length); | |
d174bd64 DV |
887 | else |
888 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
889 | user_data, | |
890 | page_length); | |
891 | if (needs_clflush_after) | |
23c18c71 DV |
892 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
893 | page_length, | |
894 | page_do_bit17_swizzling); | |
d174bd64 | 895 | kunmap(page); |
40123c1f | 896 | |
755d2218 | 897 | return ret ? -EFAULT : 0; |
40123c1f EA |
898 | } |
899 | ||
40123c1f | 900 | static int |
e244a443 DV |
901 | i915_gem_shmem_pwrite(struct drm_device *dev, |
902 | struct drm_i915_gem_object *obj, | |
903 | struct drm_i915_gem_pwrite *args, | |
904 | struct drm_file *file) | |
40123c1f | 905 | { |
40123c1f | 906 | ssize_t remain; |
8c59967c DV |
907 | loff_t offset; |
908 | char __user *user_data; | |
eb2c0c81 | 909 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 910 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 911 | int hit_slowpath = 0; |
58642885 DV |
912 | int needs_clflush_after = 0; |
913 | int needs_clflush_before = 0; | |
67d5a50c | 914 | struct sg_page_iter sg_iter; |
40123c1f | 915 | |
3ed605bc | 916 | user_data = u64_to_user_ptr(args->data_ptr); |
40123c1f EA |
917 | remain = args->size; |
918 | ||
8c59967c | 919 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 920 | |
58642885 DV |
921 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
922 | /* If we're not in the cpu write domain, set ourself into the gtt | |
923 | * write domain and manually flush cachelines (if required). This | |
924 | * optimizes for the case when the gpu will use the data | |
925 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 926 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
927 | ret = i915_gem_object_wait_rendering(obj, false); |
928 | if (ret) | |
929 | return ret; | |
58642885 | 930 | } |
c76ce038 CW |
931 | /* Same trick applies to invalidate partially written cachelines read |
932 | * before writing. */ | |
933 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
934 | needs_clflush_before = | |
935 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 936 | |
755d2218 CW |
937 | ret = i915_gem_object_get_pages(obj); |
938 | if (ret) | |
939 | return ret; | |
940 | ||
77a0d1ca | 941 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 942 | |
755d2218 CW |
943 | i915_gem_object_pin_pages(obj); |
944 | ||
673a394b | 945 | offset = args->offset; |
05394f39 | 946 | obj->dirty = 1; |
673a394b | 947 | |
67d5a50c ID |
948 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
949 | offset >> PAGE_SHIFT) { | |
2db76d7c | 950 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 951 | int partial_cacheline_write; |
e5281ccd | 952 | |
9da3da66 CW |
953 | if (remain <= 0) |
954 | break; | |
955 | ||
40123c1f EA |
956 | /* Operation in this page |
957 | * | |
40123c1f | 958 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
959 | * page_length = bytes to copy for this page |
960 | */ | |
c8cbbb8b | 961 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
962 | |
963 | page_length = remain; | |
964 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
965 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 966 | |
58642885 DV |
967 | /* If we don't overwrite a cacheline completely we need to be |
968 | * careful to have up-to-date data by first clflushing. Don't | |
969 | * overcomplicate things and flush the entire patch. */ | |
970 | partial_cacheline_write = needs_clflush_before && | |
971 | ((shmem_page_offset | page_length) | |
972 | & (boot_cpu_data.x86_clflush_size - 1)); | |
973 | ||
8c59967c DV |
974 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
975 | (page_to_phys(page) & (1 << 17)) != 0; | |
976 | ||
d174bd64 DV |
977 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
978 | user_data, page_do_bit17_swizzling, | |
979 | partial_cacheline_write, | |
980 | needs_clflush_after); | |
981 | if (ret == 0) | |
982 | goto next_page; | |
e244a443 DV |
983 | |
984 | hit_slowpath = 1; | |
e244a443 | 985 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
986 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
987 | user_data, page_do_bit17_swizzling, | |
988 | partial_cacheline_write, | |
989 | needs_clflush_after); | |
40123c1f | 990 | |
e244a443 | 991 | mutex_lock(&dev->struct_mutex); |
755d2218 | 992 | |
755d2218 | 993 | if (ret) |
8c59967c | 994 | goto out; |
8c59967c | 995 | |
17793c9a | 996 | next_page: |
40123c1f | 997 | remain -= page_length; |
8c59967c | 998 | user_data += page_length; |
40123c1f | 999 | offset += page_length; |
673a394b EA |
1000 | } |
1001 | ||
fbd5a26d | 1002 | out: |
755d2218 CW |
1003 | i915_gem_object_unpin_pages(obj); |
1004 | ||
e244a443 | 1005 | if (hit_slowpath) { |
8dcf015e DV |
1006 | /* |
1007 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1008 | * cachelines in-line while writing and the object moved | |
1009 | * out of the cpu write domain while we've dropped the lock. | |
1010 | */ | |
1011 | if (!needs_clflush_after && | |
1012 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1013 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1014 | needs_clflush_after = true; |
e244a443 | 1015 | } |
8c59967c | 1016 | } |
673a394b | 1017 | |
58642885 | 1018 | if (needs_clflush_after) |
c033666a | 1019 | i915_gem_chipset_flush(to_i915(dev)); |
ed75a55b VS |
1020 | else |
1021 | obj->cache_dirty = true; | |
58642885 | 1022 | |
de152b62 | 1023 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1024 | return ret; |
673a394b EA |
1025 | } |
1026 | ||
1027 | /** | |
1028 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1029 | * @dev: drm device |
1030 | * @data: ioctl data blob | |
1031 | * @file: drm file | |
673a394b EA |
1032 | * |
1033 | * On error, the contents of the buffer that were to be modified are undefined. | |
1034 | */ | |
1035 | int | |
1036 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1037 | struct drm_file *file) |
673a394b | 1038 | { |
5d77d9c5 | 1039 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1040 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1041 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1042 | int ret; |
1043 | ||
1044 | if (args->size == 0) | |
1045 | return 0; | |
1046 | ||
1047 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1048 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1049 | args->size)) |
1050 | return -EFAULT; | |
1051 | ||
d330a953 | 1052 | if (likely(!i915.prefault_disable)) { |
3ed605bc | 1053 | ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr), |
0b74b508 XZ |
1054 | args->size); |
1055 | if (ret) | |
1056 | return -EFAULT; | |
1057 | } | |
673a394b | 1058 | |
5d77d9c5 ID |
1059 | intel_runtime_pm_get(dev_priv); |
1060 | ||
fbd5a26d | 1061 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1062 | if (ret) |
5d77d9c5 | 1063 | goto put_rpm; |
1d7cfea1 | 1064 | |
a8ad0bd8 | 1065 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 1066 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1067 | ret = -ENOENT; |
1068 | goto unlock; | |
fbd5a26d | 1069 | } |
673a394b | 1070 | |
7dcd2499 | 1071 | /* Bounds check destination. */ |
05394f39 CW |
1072 | if (args->offset > obj->base.size || |
1073 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1074 | ret = -EINVAL; |
35b62a89 | 1075 | goto out; |
ce9d419d CW |
1076 | } |
1077 | ||
1286ff73 DV |
1078 | /* prime objects have no backing filp to GEM pread/pwrite |
1079 | * pages from. | |
1080 | */ | |
1081 | if (!obj->base.filp) { | |
1082 | ret = -EINVAL; | |
1083 | goto out; | |
1084 | } | |
1085 | ||
db53a302 CW |
1086 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1087 | ||
935aaa69 | 1088 | ret = -EFAULT; |
673a394b EA |
1089 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1090 | * it would end up going through the fenced access, and we'll get | |
1091 | * different detiling behavior between reading and writing. | |
1092 | * pread/pwrite currently are reading and writing from the CPU | |
1093 | * perspective, requiring manual detiling by the client. | |
1094 | */ | |
2c22569b CW |
1095 | if (obj->tiling_mode == I915_TILING_NONE && |
1096 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1097 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1098 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1099 | /* Note that the gtt paths might fail with non-page-backed user |
1100 | * pointers (e.g. gtt mappings when moving data between | |
1101 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1102 | } |
673a394b | 1103 | |
6a2c4232 CW |
1104 | if (ret == -EFAULT || ret == -ENOSPC) { |
1105 | if (obj->phys_handle) | |
1106 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1107 | else | |
1108 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1109 | } | |
5c0480f2 | 1110 | |
35b62a89 | 1111 | out: |
05394f39 | 1112 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1113 | unlock: |
fbd5a26d | 1114 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1115 | put_rpm: |
1116 | intel_runtime_pm_put(dev_priv); | |
1117 | ||
673a394b EA |
1118 | return ret; |
1119 | } | |
1120 | ||
f4457ae7 CW |
1121 | static int |
1122 | i915_gem_check_wedge(unsigned reset_counter, bool interruptible) | |
b361237b | 1123 | { |
f4457ae7 CW |
1124 | if (__i915_terminally_wedged(reset_counter)) |
1125 | return -EIO; | |
d98c52cf | 1126 | |
f4457ae7 | 1127 | if (__i915_reset_in_progress(reset_counter)) { |
b361237b CW |
1128 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1129 | * -EIO unconditionally for these. */ | |
1130 | if (!interruptible) | |
1131 | return -EIO; | |
1132 | ||
d98c52cf | 1133 | return -EAGAIN; |
b361237b CW |
1134 | } |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
094f9a54 CW |
1139 | static void fake_irq(unsigned long data) |
1140 | { | |
1141 | wake_up_process((struct task_struct *)data); | |
1142 | } | |
1143 | ||
1144 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
0bc40be8 | 1145 | struct intel_engine_cs *engine) |
094f9a54 | 1146 | { |
0bc40be8 | 1147 | return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings); |
094f9a54 CW |
1148 | } |
1149 | ||
ca5b721e CW |
1150 | static unsigned long local_clock_us(unsigned *cpu) |
1151 | { | |
1152 | unsigned long t; | |
1153 | ||
1154 | /* Cheaply and approximately convert from nanoseconds to microseconds. | |
1155 | * The result and subsequent calculations are also defined in the same | |
1156 | * approximate microseconds units. The principal source of timing | |
1157 | * error here is from the simple truncation. | |
1158 | * | |
1159 | * Note that local_clock() is only defined wrt to the current CPU; | |
1160 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1161 | * blocking preemption for the entire busywait, we can detect the CPU | |
1162 | * switch and use that as indicator of system load and a reason to | |
1163 | * stop busywaiting, see busywait_stop(). | |
1164 | */ | |
1165 | *cpu = get_cpu(); | |
1166 | t = local_clock() >> 10; | |
1167 | put_cpu(); | |
1168 | ||
1169 | return t; | |
1170 | } | |
1171 | ||
1172 | static bool busywait_stop(unsigned long timeout, unsigned cpu) | |
1173 | { | |
1174 | unsigned this_cpu; | |
1175 | ||
1176 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1177 | return true; | |
1178 | ||
1179 | return this_cpu != cpu; | |
1180 | } | |
1181 | ||
91b0c352 | 1182 | static int __i915_spin_request(struct drm_i915_gem_request *req, int state) |
b29c19b6 | 1183 | { |
2def4ad9 | 1184 | unsigned long timeout; |
ca5b721e CW |
1185 | unsigned cpu; |
1186 | ||
1187 | /* When waiting for high frequency requests, e.g. during synchronous | |
1188 | * rendering split between the CPU and GPU, the finite amount of time | |
1189 | * required to set up the irq and wait upon it limits the response | |
1190 | * rate. By busywaiting on the request completion for a short while we | |
1191 | * can service the high frequency waits as quick as possible. However, | |
1192 | * if it is a slow request, we want to sleep as quickly as possible. | |
1193 | * The tradeoff between waiting and sleeping is roughly the time it | |
1194 | * takes to sleep on a request, on the order of a microsecond. | |
1195 | */ | |
2def4ad9 | 1196 | |
4a570db5 | 1197 | if (req->engine->irq_refcount) |
2def4ad9 CW |
1198 | return -EBUSY; |
1199 | ||
821485dc CW |
1200 | /* Only spin if we know the GPU is processing this request */ |
1201 | if (!i915_gem_request_started(req, true)) | |
1202 | return -EAGAIN; | |
1203 | ||
ca5b721e | 1204 | timeout = local_clock_us(&cpu) + 5; |
2def4ad9 | 1205 | while (!need_resched()) { |
eed29a5b | 1206 | if (i915_gem_request_completed(req, true)) |
2def4ad9 CW |
1207 | return 0; |
1208 | ||
91b0c352 CW |
1209 | if (signal_pending_state(state, current)) |
1210 | break; | |
1211 | ||
ca5b721e | 1212 | if (busywait_stop(timeout, cpu)) |
2def4ad9 | 1213 | break; |
b29c19b6 | 1214 | |
2def4ad9 CW |
1215 | cpu_relax_lowlatency(); |
1216 | } | |
821485dc | 1217 | |
eed29a5b | 1218 | if (i915_gem_request_completed(req, false)) |
2def4ad9 CW |
1219 | return 0; |
1220 | ||
1221 | return -EAGAIN; | |
b29c19b6 CW |
1222 | } |
1223 | ||
b361237b | 1224 | /** |
9c654818 JH |
1225 | * __i915_wait_request - wait until execution of request has finished |
1226 | * @req: duh! | |
b361237b CW |
1227 | * @interruptible: do an interruptible wait (normally yes) |
1228 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
14bb2c11 | 1229 | * @rps: RPS client |
b361237b | 1230 | * |
f69061be DV |
1231 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1232 | * values have been read by the caller in an smp safe manner. Where read-side | |
1233 | * locks are involved, it is sufficient to read the reset_counter before | |
1234 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1235 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1236 | * inserted. | |
1237 | * | |
9c654818 | 1238 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1239 | * errno with remaining time filled in timeout argument. |
1240 | */ | |
9c654818 | 1241 | int __i915_wait_request(struct drm_i915_gem_request *req, |
b29c19b6 | 1242 | bool interruptible, |
5ed0bdf2 | 1243 | s64 *timeout, |
2e1b8730 | 1244 | struct intel_rps_client *rps) |
b361237b | 1245 | { |
666796da | 1246 | struct intel_engine_cs *engine = i915_gem_request_get_engine(req); |
c033666a | 1247 | struct drm_i915_private *dev_priv = req->i915; |
168c3f21 | 1248 | const bool irq_test_in_progress = |
666796da | 1249 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine); |
91b0c352 | 1250 | int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; |
094f9a54 | 1251 | DEFINE_WAIT(wait); |
47e9766d | 1252 | unsigned long timeout_expire; |
e0313db0 | 1253 | s64 before = 0; /* Only to silence a compiler warning. */ |
b361237b CW |
1254 | int ret; |
1255 | ||
9df7575f | 1256 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1257 | |
b4716185 CW |
1258 | if (list_empty(&req->list)) |
1259 | return 0; | |
1260 | ||
1b5a433a | 1261 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1262 | return 0; |
1263 | ||
bb6d1984 CW |
1264 | timeout_expire = 0; |
1265 | if (timeout) { | |
1266 | if (WARN_ON(*timeout < 0)) | |
1267 | return -EINVAL; | |
1268 | ||
1269 | if (*timeout == 0) | |
1270 | return -ETIME; | |
1271 | ||
1272 | timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout); | |
e0313db0 TU |
1273 | |
1274 | /* | |
1275 | * Record current time in case interrupted by signal, or wedged. | |
1276 | */ | |
1277 | before = ktime_get_raw_ns(); | |
bb6d1984 | 1278 | } |
b361237b | 1279 | |
2e1b8730 | 1280 | if (INTEL_INFO(dev_priv)->gen >= 6) |
e61b9958 | 1281 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
b361237b | 1282 | |
74328ee5 | 1283 | trace_i915_gem_request_wait_begin(req); |
2def4ad9 CW |
1284 | |
1285 | /* Optimistic spin for the next jiffie before touching IRQs */ | |
91b0c352 | 1286 | ret = __i915_spin_request(req, state); |
2def4ad9 CW |
1287 | if (ret == 0) |
1288 | goto out; | |
1289 | ||
e2f80391 | 1290 | if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) { |
2def4ad9 CW |
1291 | ret = -ENODEV; |
1292 | goto out; | |
1293 | } | |
1294 | ||
094f9a54 CW |
1295 | for (;;) { |
1296 | struct timer_list timer; | |
b361237b | 1297 | |
e2f80391 | 1298 | prepare_to_wait(&engine->irq_queue, &wait, state); |
b361237b | 1299 | |
f69061be | 1300 | /* We need to check whether any gpu reset happened in between |
f4457ae7 CW |
1301 | * the request being submitted and now. If a reset has occurred, |
1302 | * the request is effectively complete (we either are in the | |
1303 | * process of or have discarded the rendering and completely | |
1304 | * reset the GPU. The results of the request are lost and we | |
1305 | * are free to continue on with the original operation. | |
1306 | */ | |
299259a3 | 1307 | if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) { |
f4457ae7 | 1308 | ret = 0; |
094f9a54 CW |
1309 | break; |
1310 | } | |
f69061be | 1311 | |
1b5a433a | 1312 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1313 | ret = 0; |
1314 | break; | |
1315 | } | |
b361237b | 1316 | |
91b0c352 | 1317 | if (signal_pending_state(state, current)) { |
094f9a54 CW |
1318 | ret = -ERESTARTSYS; |
1319 | break; | |
1320 | } | |
1321 | ||
47e9766d | 1322 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1323 | ret = -ETIME; |
1324 | break; | |
1325 | } | |
1326 | ||
1327 | timer.function = NULL; | |
e2f80391 | 1328 | if (timeout || missed_irq(dev_priv, engine)) { |
47e9766d MK |
1329 | unsigned long expire; |
1330 | ||
094f9a54 | 1331 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
e2f80391 | 1332 | expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1333 | mod_timer(&timer, expire); |
1334 | } | |
1335 | ||
5035c275 | 1336 | io_schedule(); |
094f9a54 | 1337 | |
094f9a54 CW |
1338 | if (timer.function) { |
1339 | del_singleshot_timer_sync(&timer); | |
1340 | destroy_timer_on_stack(&timer); | |
1341 | } | |
1342 | } | |
168c3f21 | 1343 | if (!irq_test_in_progress) |
e2f80391 | 1344 | engine->irq_put(engine); |
094f9a54 | 1345 | |
e2f80391 | 1346 | finish_wait(&engine->irq_queue, &wait); |
b361237b | 1347 | |
2def4ad9 | 1348 | out: |
2def4ad9 CW |
1349 | trace_i915_gem_request_wait_end(req); |
1350 | ||
b361237b | 1351 | if (timeout) { |
e0313db0 | 1352 | s64 tres = *timeout - (ktime_get_raw_ns() - before); |
5ed0bdf2 TG |
1353 | |
1354 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1355 | |
1356 | /* | |
1357 | * Apparently ktime isn't accurate enough and occasionally has a | |
1358 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1359 | * things up to make the test happy. We allow up to 1 jiffy. | |
1360 | * | |
1361 | * This is a regrssion from the timespec->ktime conversion. | |
1362 | */ | |
1363 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1364 | *timeout = 0; | |
b361237b CW |
1365 | } |
1366 | ||
094f9a54 | 1367 | return ret; |
b361237b CW |
1368 | } |
1369 | ||
fcfa423c JH |
1370 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
1371 | struct drm_file *file) | |
1372 | { | |
fcfa423c JH |
1373 | struct drm_i915_file_private *file_priv; |
1374 | ||
1375 | WARN_ON(!req || !file || req->file_priv); | |
1376 | ||
1377 | if (!req || !file) | |
1378 | return -EINVAL; | |
1379 | ||
1380 | if (req->file_priv) | |
1381 | return -EINVAL; | |
1382 | ||
fcfa423c JH |
1383 | file_priv = file->driver_priv; |
1384 | ||
1385 | spin_lock(&file_priv->mm.lock); | |
1386 | req->file_priv = file_priv; | |
1387 | list_add_tail(&req->client_list, &file_priv->mm.request_list); | |
1388 | spin_unlock(&file_priv->mm.lock); | |
1389 | ||
1390 | req->pid = get_pid(task_pid(current)); | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
b4716185 CW |
1395 | static inline void |
1396 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
1397 | { | |
1398 | struct drm_i915_file_private *file_priv = request->file_priv; | |
1399 | ||
1400 | if (!file_priv) | |
1401 | return; | |
1402 | ||
1403 | spin_lock(&file_priv->mm.lock); | |
1404 | list_del(&request->client_list); | |
1405 | request->file_priv = NULL; | |
1406 | spin_unlock(&file_priv->mm.lock); | |
fcfa423c JH |
1407 | |
1408 | put_pid(request->pid); | |
1409 | request->pid = NULL; | |
b4716185 CW |
1410 | } |
1411 | ||
1412 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) | |
1413 | { | |
1414 | trace_i915_gem_request_retire(request); | |
1415 | ||
1416 | /* We know the GPU must have read the request to have | |
1417 | * sent us the seqno + interrupt, so use the position | |
1418 | * of tail of the request to update the last known position | |
1419 | * of the GPU head. | |
1420 | * | |
1421 | * Note this requires that we are always called in request | |
1422 | * completion order. | |
1423 | */ | |
1424 | request->ringbuf->last_retired_head = request->postfix; | |
1425 | ||
1426 | list_del_init(&request->list); | |
1427 | i915_gem_request_remove_from_client(request); | |
1428 | ||
a16a4052 | 1429 | if (request->previous_context) { |
73db04cf | 1430 | if (i915.enable_execlists) |
a16a4052 CW |
1431 | intel_lr_context_unpin(request->previous_context, |
1432 | request->engine); | |
73db04cf CW |
1433 | } |
1434 | ||
a16a4052 | 1435 | i915_gem_context_unreference(request->ctx); |
b4716185 CW |
1436 | i915_gem_request_unreference(request); |
1437 | } | |
1438 | ||
1439 | static void | |
1440 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) | |
1441 | { | |
4a570db5 | 1442 | struct intel_engine_cs *engine = req->engine; |
b4716185 CW |
1443 | struct drm_i915_gem_request *tmp; |
1444 | ||
c033666a | 1445 | lockdep_assert_held(&engine->i915->dev->struct_mutex); |
b4716185 CW |
1446 | |
1447 | if (list_empty(&req->list)) | |
1448 | return; | |
1449 | ||
1450 | do { | |
1451 | tmp = list_first_entry(&engine->request_list, | |
1452 | typeof(*tmp), list); | |
1453 | ||
1454 | i915_gem_request_retire(tmp); | |
1455 | } while (tmp != req); | |
1456 | ||
1457 | WARN_ON(i915_verify_lists(engine->dev)); | |
1458 | } | |
1459 | ||
b361237b | 1460 | /** |
a4b3a571 | 1461 | * Waits for a request to be signaled, and cleans up the |
b361237b | 1462 | * request and object lists appropriately for that event. |
14bb2c11 | 1463 | * @req: request to wait on |
b361237b CW |
1464 | */ |
1465 | int | |
a4b3a571 | 1466 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1467 | { |
791bee12 | 1468 | struct drm_i915_private *dev_priv = req->i915; |
a4b3a571 | 1469 | bool interruptible; |
b361237b CW |
1470 | int ret; |
1471 | ||
a4b3a571 DV |
1472 | interruptible = dev_priv->mm.interruptible; |
1473 | ||
791bee12 | 1474 | BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
b361237b | 1475 | |
299259a3 | 1476 | ret = __i915_wait_request(req, interruptible, NULL, NULL); |
b4716185 CW |
1477 | if (ret) |
1478 | return ret; | |
d26e3af8 | 1479 | |
e075a32f CW |
1480 | /* If the GPU hung, we want to keep the requests to find the guilty. */ |
1481 | if (req->reset_counter == i915_reset_counter(&dev_priv->gpu_error)) | |
1482 | __i915_gem_request_retire__upto(req); | |
1483 | ||
d26e3af8 CW |
1484 | return 0; |
1485 | } | |
1486 | ||
b361237b CW |
1487 | /** |
1488 | * Ensures that all rendering to the object has completed and the object is | |
1489 | * safe to unbind from the GTT or access from the CPU. | |
14bb2c11 TU |
1490 | * @obj: i915 gem object |
1491 | * @readonly: waiting for read access or write | |
b361237b | 1492 | */ |
2e2f351d | 1493 | int |
b361237b CW |
1494 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1495 | bool readonly) | |
1496 | { | |
b4716185 | 1497 | int ret, i; |
b361237b | 1498 | |
b4716185 | 1499 | if (!obj->active) |
b361237b CW |
1500 | return 0; |
1501 | ||
b4716185 CW |
1502 | if (readonly) { |
1503 | if (obj->last_write_req != NULL) { | |
1504 | ret = i915_wait_request(obj->last_write_req); | |
1505 | if (ret) | |
1506 | return ret; | |
b361237b | 1507 | |
4a570db5 | 1508 | i = obj->last_write_req->engine->id; |
b4716185 CW |
1509 | if (obj->last_read_req[i] == obj->last_write_req) |
1510 | i915_gem_object_retire__read(obj, i); | |
1511 | else | |
1512 | i915_gem_object_retire__write(obj); | |
1513 | } | |
1514 | } else { | |
666796da | 1515 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1516 | if (obj->last_read_req[i] == NULL) |
1517 | continue; | |
1518 | ||
1519 | ret = i915_wait_request(obj->last_read_req[i]); | |
1520 | if (ret) | |
1521 | return ret; | |
1522 | ||
1523 | i915_gem_object_retire__read(obj, i); | |
1524 | } | |
d501b1d2 | 1525 | GEM_BUG_ON(obj->active); |
b4716185 CW |
1526 | } |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | static void | |
1532 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, | |
1533 | struct drm_i915_gem_request *req) | |
1534 | { | |
4a570db5 | 1535 | int ring = req->engine->id; |
b4716185 CW |
1536 | |
1537 | if (obj->last_read_req[ring] == req) | |
1538 | i915_gem_object_retire__read(obj, ring); | |
1539 | else if (obj->last_write_req == req) | |
1540 | i915_gem_object_retire__write(obj); | |
1541 | ||
e075a32f CW |
1542 | if (req->reset_counter == i915_reset_counter(&req->i915->gpu_error)) |
1543 | __i915_gem_request_retire__upto(req); | |
b361237b CW |
1544 | } |
1545 | ||
3236f57a CW |
1546 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1547 | * as the object state may change during this call. | |
1548 | */ | |
1549 | static __must_check int | |
1550 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
2e1b8730 | 1551 | struct intel_rps_client *rps, |
3236f57a CW |
1552 | bool readonly) |
1553 | { | |
1554 | struct drm_device *dev = obj->base.dev; | |
1555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
666796da | 1556 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
b4716185 | 1557 | int ret, i, n = 0; |
3236f57a CW |
1558 | |
1559 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1560 | BUG_ON(!dev_priv->mm.interruptible); | |
1561 | ||
b4716185 | 1562 | if (!obj->active) |
3236f57a CW |
1563 | return 0; |
1564 | ||
b4716185 CW |
1565 | if (readonly) { |
1566 | struct drm_i915_gem_request *req; | |
1567 | ||
1568 | req = obj->last_write_req; | |
1569 | if (req == NULL) | |
1570 | return 0; | |
1571 | ||
b4716185 CW |
1572 | requests[n++] = i915_gem_request_reference(req); |
1573 | } else { | |
666796da | 1574 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1575 | struct drm_i915_gem_request *req; |
1576 | ||
1577 | req = obj->last_read_req[i]; | |
1578 | if (req == NULL) | |
1579 | continue; | |
1580 | ||
b4716185 CW |
1581 | requests[n++] = i915_gem_request_reference(req); |
1582 | } | |
1583 | } | |
1584 | ||
3236f57a | 1585 | mutex_unlock(&dev->struct_mutex); |
299259a3 | 1586 | ret = 0; |
b4716185 | 1587 | for (i = 0; ret == 0 && i < n; i++) |
299259a3 | 1588 | ret = __i915_wait_request(requests[i], true, NULL, rps); |
3236f57a CW |
1589 | mutex_lock(&dev->struct_mutex); |
1590 | ||
b4716185 CW |
1591 | for (i = 0; i < n; i++) { |
1592 | if (ret == 0) | |
1593 | i915_gem_object_retire_request(obj, requests[i]); | |
1594 | i915_gem_request_unreference(requests[i]); | |
1595 | } | |
1596 | ||
1597 | return ret; | |
3236f57a CW |
1598 | } |
1599 | ||
2e1b8730 CW |
1600 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
1601 | { | |
1602 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1603 | return &fpriv->rps; | |
1604 | } | |
1605 | ||
673a394b | 1606 | /** |
2ef7eeaa EA |
1607 | * Called when user space prepares to use an object with the CPU, either |
1608 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1609 | * @dev: drm device |
1610 | * @data: ioctl data blob | |
1611 | * @file: drm file | |
673a394b EA |
1612 | */ |
1613 | int | |
1614 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1615 | struct drm_file *file) |
673a394b EA |
1616 | { |
1617 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1618 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1619 | uint32_t read_domains = args->read_domains; |
1620 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1621 | int ret; |
1622 | ||
2ef7eeaa | 1623 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1624 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1625 | return -EINVAL; |
1626 | ||
21d509e3 | 1627 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1628 | return -EINVAL; |
1629 | ||
1630 | /* Having something in the write domain implies it's in the read | |
1631 | * domain, and only that read domain. Enforce that in the request. | |
1632 | */ | |
1633 | if (write_domain != 0 && read_domains != write_domain) | |
1634 | return -EINVAL; | |
1635 | ||
76c1dec1 | 1636 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1637 | if (ret) |
76c1dec1 | 1638 | return ret; |
1d7cfea1 | 1639 | |
a8ad0bd8 | 1640 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 1641 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1642 | ret = -ENOENT; |
1643 | goto unlock; | |
76c1dec1 | 1644 | } |
673a394b | 1645 | |
3236f57a CW |
1646 | /* Try to flush the object off the GPU without holding the lock. |
1647 | * We will repeat the flush holding the lock in the normal manner | |
1648 | * to catch cases where we are gazumped. | |
1649 | */ | |
6e4930f6 | 1650 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
2e1b8730 | 1651 | to_rps_client(file), |
6e4930f6 | 1652 | !write_domain); |
3236f57a CW |
1653 | if (ret) |
1654 | goto unref; | |
1655 | ||
43566ded | 1656 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1657 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1658 | else |
e47c68e9 | 1659 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1660 | |
031b698a DV |
1661 | if (write_domain != 0) |
1662 | intel_fb_obj_invalidate(obj, | |
1663 | write_domain == I915_GEM_DOMAIN_GTT ? | |
1664 | ORIGIN_GTT : ORIGIN_CPU); | |
1665 | ||
3236f57a | 1666 | unref: |
05394f39 | 1667 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1668 | unlock: |
673a394b EA |
1669 | mutex_unlock(&dev->struct_mutex); |
1670 | return ret; | |
1671 | } | |
1672 | ||
1673 | /** | |
1674 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1675 | * @dev: drm device |
1676 | * @data: ioctl data blob | |
1677 | * @file: drm file | |
673a394b EA |
1678 | */ |
1679 | int | |
1680 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1681 | struct drm_file *file) |
673a394b EA |
1682 | { |
1683 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1684 | struct drm_i915_gem_object *obj; |
673a394b EA |
1685 | int ret = 0; |
1686 | ||
76c1dec1 | 1687 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1688 | if (ret) |
76c1dec1 | 1689 | return ret; |
1d7cfea1 | 1690 | |
a8ad0bd8 | 1691 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 1692 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1693 | ret = -ENOENT; |
1694 | goto unlock; | |
673a394b EA |
1695 | } |
1696 | ||
673a394b | 1697 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1698 | if (obj->pin_display) |
e62b59e4 | 1699 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1700 | |
05394f39 | 1701 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1702 | unlock: |
673a394b EA |
1703 | mutex_unlock(&dev->struct_mutex); |
1704 | return ret; | |
1705 | } | |
1706 | ||
1707 | /** | |
14bb2c11 TU |
1708 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1709 | * it is mapped to. | |
1710 | * @dev: drm device | |
1711 | * @data: ioctl data blob | |
1712 | * @file: drm file | |
673a394b EA |
1713 | * |
1714 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1715 | * imply a ref on the object itself. | |
34367381 DV |
1716 | * |
1717 | * IMPORTANT: | |
1718 | * | |
1719 | * DRM driver writers who look a this function as an example for how to do GEM | |
1720 | * mmap support, please don't implement mmap support like here. The modern way | |
1721 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1722 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1723 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1724 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1725 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1726 | */ |
1727 | int | |
1728 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1729 | struct drm_file *file) |
673a394b EA |
1730 | { |
1731 | struct drm_i915_gem_mmap *args = data; | |
1732 | struct drm_gem_object *obj; | |
673a394b EA |
1733 | unsigned long addr; |
1734 | ||
1816f923 AG |
1735 | if (args->flags & ~(I915_MMAP_WC)) |
1736 | return -EINVAL; | |
1737 | ||
568a58e5 | 1738 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1739 | return -ENODEV; |
1740 | ||
a8ad0bd8 | 1741 | obj = drm_gem_object_lookup(file, args->handle); |
673a394b | 1742 | if (obj == NULL) |
bf79cb91 | 1743 | return -ENOENT; |
673a394b | 1744 | |
1286ff73 DV |
1745 | /* prime objects have no backing filp to GEM mmap |
1746 | * pages from. | |
1747 | */ | |
1748 | if (!obj->filp) { | |
1749 | drm_gem_object_unreference_unlocked(obj); | |
1750 | return -EINVAL; | |
1751 | } | |
1752 | ||
6be5ceb0 | 1753 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1754 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1755 | args->offset); | |
1816f923 AG |
1756 | if (args->flags & I915_MMAP_WC) { |
1757 | struct mm_struct *mm = current->mm; | |
1758 | struct vm_area_struct *vma; | |
1759 | ||
80a89a5e MH |
1760 | if (down_write_killable(&mm->mmap_sem)) { |
1761 | drm_gem_object_unreference_unlocked(obj); | |
1762 | return -EINTR; | |
1763 | } | |
1816f923 AG |
1764 | vma = find_vma(mm, addr); |
1765 | if (vma) | |
1766 | vma->vm_page_prot = | |
1767 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1768 | else | |
1769 | addr = -ENOMEM; | |
1770 | up_write(&mm->mmap_sem); | |
1771 | } | |
bc9025bd | 1772 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1773 | if (IS_ERR((void *)addr)) |
1774 | return addr; | |
1775 | ||
1776 | args->addr_ptr = (uint64_t) addr; | |
1777 | ||
1778 | return 0; | |
1779 | } | |
1780 | ||
de151cf6 JB |
1781 | /** |
1782 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
1783 | * @vma: VMA in question |
1784 | * @vmf: fault info | |
de151cf6 JB |
1785 | * |
1786 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1787 | * from userspace. The fault handler takes care of binding the object to | |
1788 | * the GTT (if needed), allocating and programming a fence register (again, | |
1789 | * only if needed based on whether the old reg is still valid or the object | |
1790 | * is tiled) and inserting a new PTE into the faulting process. | |
1791 | * | |
1792 | * Note that the faulting process may involve evicting existing objects | |
1793 | * from the GTT and/or fence registers to make room. So performance may | |
1794 | * suffer if the GTT working set is large or there are few fence registers | |
1795 | * left. | |
1796 | */ | |
1797 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1798 | { | |
05394f39 CW |
1799 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1800 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
1801 | struct drm_i915_private *dev_priv = to_i915(dev); |
1802 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
c5ad54cf | 1803 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
de151cf6 JB |
1804 | pgoff_t page_offset; |
1805 | unsigned long pfn; | |
1806 | int ret = 0; | |
0f973f27 | 1807 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1808 | |
f65c9168 PZ |
1809 | intel_runtime_pm_get(dev_priv); |
1810 | ||
de151cf6 JB |
1811 | /* We don't use vmf->pgoff since that has the fake offset */ |
1812 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1813 | PAGE_SHIFT; | |
1814 | ||
d9bc7e9f CW |
1815 | ret = i915_mutex_lock_interruptible(dev); |
1816 | if (ret) | |
1817 | goto out; | |
a00b10c3 | 1818 | |
db53a302 CW |
1819 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1820 | ||
6e4930f6 CW |
1821 | /* Try to flush the object off the GPU first without holding the lock. |
1822 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1823 | * repeat the flush holding the lock in the normal manner to catch cases | |
1824 | * where we are gazumped. | |
1825 | */ | |
1826 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1827 | if (ret) | |
1828 | goto unlock; | |
1829 | ||
eb119bd6 CW |
1830 | /* Access to snoopable pages through the GTT is incoherent. */ |
1831 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1832 | ret = -EFAULT; |
eb119bd6 CW |
1833 | goto unlock; |
1834 | } | |
1835 | ||
c5ad54cf | 1836 | /* Use a partial view if the object is bigger than the aperture. */ |
72e96d64 | 1837 | if (obj->base.size >= ggtt->mappable_end && |
e7ded2d7 | 1838 | obj->tiling_mode == I915_TILING_NONE) { |
c5ad54cf | 1839 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1840 | |
c5ad54cf JL |
1841 | memset(&view, 0, sizeof(view)); |
1842 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1843 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1844 | view.params.partial.size = | |
1845 | min_t(unsigned int, | |
1846 | chunk_size, | |
1847 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1848 | view.params.partial.offset); | |
1849 | } | |
1850 | ||
1851 | /* Now pin it into the GTT if needed */ | |
1852 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); | |
c9839303 CW |
1853 | if (ret) |
1854 | goto unlock; | |
4a684a41 | 1855 | |
c9839303 CW |
1856 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1857 | if (ret) | |
1858 | goto unpin; | |
74898d7e | 1859 | |
06d98131 | 1860 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1861 | if (ret) |
c9839303 | 1862 | goto unpin; |
7d1c4804 | 1863 | |
b90b91d8 | 1864 | /* Finally, remap it using the new GTT offset */ |
72e96d64 | 1865 | pfn = ggtt->mappable_base + |
c5ad54cf | 1866 | i915_gem_obj_ggtt_offset_view(obj, &view); |
f343c5f6 | 1867 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1868 | |
c5ad54cf JL |
1869 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1870 | /* Overriding existing pages in partial view does not cause | |
1871 | * us any trouble as TLBs are still valid because the fault | |
1872 | * is due to userspace losing part of the mapping or never | |
1873 | * having accessed it before (at this partials' range). | |
1874 | */ | |
1875 | unsigned long base = vma->vm_start + | |
1876 | (view.params.partial.offset << PAGE_SHIFT); | |
1877 | unsigned int i; | |
b90b91d8 | 1878 | |
c5ad54cf JL |
1879 | for (i = 0; i < view.params.partial.size; i++) { |
1880 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1881 | if (ret) |
1882 | break; | |
1883 | } | |
1884 | ||
1885 | obj->fault_mappable = true; | |
c5ad54cf JL |
1886 | } else { |
1887 | if (!obj->fault_mappable) { | |
1888 | unsigned long size = min_t(unsigned long, | |
1889 | vma->vm_end - vma->vm_start, | |
1890 | obj->base.size); | |
1891 | int i; | |
1892 | ||
1893 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1894 | ret = vm_insert_pfn(vma, | |
1895 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1896 | pfn + i); | |
1897 | if (ret) | |
1898 | break; | |
1899 | } | |
1900 | ||
1901 | obj->fault_mappable = true; | |
1902 | } else | |
1903 | ret = vm_insert_pfn(vma, | |
1904 | (unsigned long)vmf->virtual_address, | |
1905 | pfn + page_offset); | |
1906 | } | |
c9839303 | 1907 | unpin: |
c5ad54cf | 1908 | i915_gem_object_ggtt_unpin_view(obj, &view); |
c715089f | 1909 | unlock: |
de151cf6 | 1910 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1911 | out: |
de151cf6 | 1912 | switch (ret) { |
d9bc7e9f | 1913 | case -EIO: |
2232f031 DV |
1914 | /* |
1915 | * We eat errors when the gpu is terminally wedged to avoid | |
1916 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1917 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1918 | * and so needs to be reported. | |
1919 | */ | |
1920 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1921 | ret = VM_FAULT_SIGBUS; |
1922 | break; | |
1923 | } | |
045e769a | 1924 | case -EAGAIN: |
571c608d DV |
1925 | /* |
1926 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1927 | * handler to reset everything when re-faulting in | |
1928 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1929 | */ |
c715089f CW |
1930 | case 0: |
1931 | case -ERESTARTSYS: | |
bed636ab | 1932 | case -EINTR: |
e79e0fe3 DR |
1933 | case -EBUSY: |
1934 | /* | |
1935 | * EBUSY is ok: this just means that another thread | |
1936 | * already did the job. | |
1937 | */ | |
f65c9168 PZ |
1938 | ret = VM_FAULT_NOPAGE; |
1939 | break; | |
de151cf6 | 1940 | case -ENOMEM: |
f65c9168 PZ |
1941 | ret = VM_FAULT_OOM; |
1942 | break; | |
a7c2e1aa | 1943 | case -ENOSPC: |
45d67817 | 1944 | case -EFAULT: |
f65c9168 PZ |
1945 | ret = VM_FAULT_SIGBUS; |
1946 | break; | |
de151cf6 | 1947 | default: |
a7c2e1aa | 1948 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1949 | ret = VM_FAULT_SIGBUS; |
1950 | break; | |
de151cf6 | 1951 | } |
f65c9168 PZ |
1952 | |
1953 | intel_runtime_pm_put(dev_priv); | |
1954 | return ret; | |
de151cf6 JB |
1955 | } |
1956 | ||
901782b2 CW |
1957 | /** |
1958 | * i915_gem_release_mmap - remove physical page mappings | |
1959 | * @obj: obj in question | |
1960 | * | |
af901ca1 | 1961 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1962 | * relinquish ownership of the pages back to the system. |
1963 | * | |
1964 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1965 | * object through the GTT and then lose the fence register due to | |
1966 | * resource pressure. Similarly if the object has been moved out of the | |
1967 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1968 | * mapping will then trigger a page fault on the next user access, allowing | |
1969 | * fixup by i915_gem_fault(). | |
1970 | */ | |
d05ca301 | 1971 | void |
05394f39 | 1972 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1973 | { |
349f2ccf CW |
1974 | /* Serialisation between user GTT access and our code depends upon |
1975 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1976 | * pagefault then has to wait until we release the mutex. | |
1977 | */ | |
1978 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
1979 | ||
6299f992 CW |
1980 | if (!obj->fault_mappable) |
1981 | return; | |
901782b2 | 1982 | |
6796cb16 DH |
1983 | drm_vma_node_unmap(&obj->base.vma_node, |
1984 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1985 | |
1986 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1987 | * memory transactions from userspace before we return. The TLB | |
1988 | * flushing implied above by changing the PTE above *should* be | |
1989 | * sufficient, an extra barrier here just provides us with a bit | |
1990 | * of paranoid documentation about our requirement to serialise | |
1991 | * memory writes before touching registers / GSM. | |
1992 | */ | |
1993 | wmb(); | |
1994 | ||
6299f992 | 1995 | obj->fault_mappable = false; |
901782b2 CW |
1996 | } |
1997 | ||
eedd10f4 CW |
1998 | void |
1999 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
2000 | { | |
2001 | struct drm_i915_gem_object *obj; | |
2002 | ||
2003 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
2004 | i915_gem_release_mmap(obj); | |
2005 | } | |
2006 | ||
0fa87796 | 2007 | uint32_t |
e28f8711 | 2008 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 2009 | { |
e28f8711 | 2010 | uint32_t gtt_size; |
92b88aeb CW |
2011 | |
2012 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
2013 | tiling_mode == I915_TILING_NONE) |
2014 | return size; | |
92b88aeb CW |
2015 | |
2016 | /* Previous chips need a power-of-two fence region when tiling */ | |
7e22dbbb | 2017 | if (IS_GEN3(dev)) |
e28f8711 | 2018 | gtt_size = 1024*1024; |
92b88aeb | 2019 | else |
e28f8711 | 2020 | gtt_size = 512*1024; |
92b88aeb | 2021 | |
e28f8711 CW |
2022 | while (gtt_size < size) |
2023 | gtt_size <<= 1; | |
92b88aeb | 2024 | |
e28f8711 | 2025 | return gtt_size; |
92b88aeb CW |
2026 | } |
2027 | ||
de151cf6 JB |
2028 | /** |
2029 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
14bb2c11 TU |
2030 | * @dev: drm device |
2031 | * @size: object size | |
2032 | * @tiling_mode: tiling mode | |
2033 | * @fenced: is fenced alignemned required or not | |
de151cf6 JB |
2034 | * |
2035 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 2036 | * potential fence register mapping. |
de151cf6 | 2037 | */ |
d865110c ID |
2038 | uint32_t |
2039 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
2040 | int tiling_mode, bool fenced) | |
de151cf6 | 2041 | { |
de151cf6 JB |
2042 | /* |
2043 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2044 | * if a fence register is needed for the object. | |
2045 | */ | |
d865110c | 2046 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 2047 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2048 | return 4096; |
2049 | ||
a00b10c3 CW |
2050 | /* |
2051 | * Previous chips need to be aligned to the size of the smallest | |
2052 | * fence register that can contain the object. | |
2053 | */ | |
e28f8711 | 2054 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
2055 | } |
2056 | ||
d8cb5086 CW |
2057 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2058 | { | |
2059 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2060 | int ret; | |
2061 | ||
da494d7c DV |
2062 | dev_priv->mm.shrinker_no_lock_stealing = true; |
2063 | ||
d8cb5086 CW |
2064 | ret = drm_gem_create_mmap_offset(&obj->base); |
2065 | if (ret != -ENOSPC) | |
da494d7c | 2066 | goto out; |
d8cb5086 CW |
2067 | |
2068 | /* Badly fragmented mmap space? The only way we can recover | |
2069 | * space is by destroying unwanted objects. We can't randomly release | |
2070 | * mmap_offsets as userspace expects them to be persistent for the | |
2071 | * lifetime of the objects. The closest we can is to release the | |
2072 | * offsets on purgeable objects by truncating it and marking it purged, | |
2073 | * which prevents userspace from ever using that object again. | |
2074 | */ | |
21ab4e74 CW |
2075 | i915_gem_shrink(dev_priv, |
2076 | obj->base.size >> PAGE_SHIFT, | |
2077 | I915_SHRINK_BOUND | | |
2078 | I915_SHRINK_UNBOUND | | |
2079 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
2080 | ret = drm_gem_create_mmap_offset(&obj->base); |
2081 | if (ret != -ENOSPC) | |
da494d7c | 2082 | goto out; |
d8cb5086 CW |
2083 | |
2084 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
2085 | ret = drm_gem_create_mmap_offset(&obj->base); |
2086 | out: | |
2087 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
2088 | ||
2089 | return ret; | |
d8cb5086 CW |
2090 | } |
2091 | ||
2092 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2093 | { | |
d8cb5086 CW |
2094 | drm_gem_free_mmap_offset(&obj->base); |
2095 | } | |
2096 | ||
da6b51d0 | 2097 | int |
ff72145b DA |
2098 | i915_gem_mmap_gtt(struct drm_file *file, |
2099 | struct drm_device *dev, | |
da6b51d0 | 2100 | uint32_t handle, |
ff72145b | 2101 | uint64_t *offset) |
de151cf6 | 2102 | { |
05394f39 | 2103 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2104 | int ret; |
2105 | ||
76c1dec1 | 2106 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 2107 | if (ret) |
76c1dec1 | 2108 | return ret; |
de151cf6 | 2109 | |
a8ad0bd8 | 2110 | obj = to_intel_bo(drm_gem_object_lookup(file, handle)); |
c8725226 | 2111 | if (&obj->base == NULL) { |
1d7cfea1 CW |
2112 | ret = -ENOENT; |
2113 | goto unlock; | |
2114 | } | |
de151cf6 | 2115 | |
05394f39 | 2116 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2117 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 2118 | ret = -EFAULT; |
1d7cfea1 | 2119 | goto out; |
ab18282d CW |
2120 | } |
2121 | ||
d8cb5086 CW |
2122 | ret = i915_gem_object_create_mmap_offset(obj); |
2123 | if (ret) | |
2124 | goto out; | |
de151cf6 | 2125 | |
0de23977 | 2126 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 2127 | |
1d7cfea1 | 2128 | out: |
05394f39 | 2129 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 2130 | unlock: |
de151cf6 | 2131 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 2132 | return ret; |
de151cf6 JB |
2133 | } |
2134 | ||
ff72145b DA |
2135 | /** |
2136 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2137 | * @dev: DRM device | |
2138 | * @data: GTT mapping ioctl data | |
2139 | * @file: GEM object info | |
2140 | * | |
2141 | * Simply returns the fake offset to userspace so it can mmap it. | |
2142 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2143 | * up so we can get faults in the handler above. | |
2144 | * | |
2145 | * The fault handler will take care of binding the object into the GTT | |
2146 | * (since it may have been evicted to make room for something), allocating | |
2147 | * a fence register, and mapping the appropriate aperture address into | |
2148 | * userspace. | |
2149 | */ | |
2150 | int | |
2151 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2152 | struct drm_file *file) | |
2153 | { | |
2154 | struct drm_i915_gem_mmap_gtt *args = data; | |
2155 | ||
da6b51d0 | 2156 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2157 | } |
2158 | ||
225067ee DV |
2159 | /* Immediately discard the backing storage */ |
2160 | static void | |
2161 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2162 | { |
4d6294bf | 2163 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2164 | |
4d6294bf CW |
2165 | if (obj->base.filp == NULL) |
2166 | return; | |
e5281ccd | 2167 | |
225067ee DV |
2168 | /* Our goal here is to return as much of the memory as |
2169 | * is possible back to the system as we are called from OOM. | |
2170 | * To do this we must instruct the shmfs to drop all of its | |
2171 | * backing pages, *now*. | |
2172 | */ | |
5537252b | 2173 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2174 | obj->madv = __I915_MADV_PURGED; |
2175 | } | |
e5281ccd | 2176 | |
5537252b CW |
2177 | /* Try to discard unwanted pages */ |
2178 | static void | |
2179 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2180 | { |
5537252b CW |
2181 | struct address_space *mapping; |
2182 | ||
2183 | switch (obj->madv) { | |
2184 | case I915_MADV_DONTNEED: | |
2185 | i915_gem_object_truncate(obj); | |
2186 | case __I915_MADV_PURGED: | |
2187 | return; | |
2188 | } | |
2189 | ||
2190 | if (obj->base.filp == NULL) | |
2191 | return; | |
2192 | ||
2193 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2194 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2195 | } |
2196 | ||
5cdf5881 | 2197 | static void |
05394f39 | 2198 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2199 | { |
85d1225e DG |
2200 | struct sgt_iter sgt_iter; |
2201 | struct page *page; | |
90797e6d | 2202 | int ret; |
1286ff73 | 2203 | |
05394f39 | 2204 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2205 | |
6c085a72 | 2206 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2207 | if (WARN_ON(ret)) { |
6c085a72 CW |
2208 | /* In the event of a disaster, abandon all caches and |
2209 | * hope for the best. | |
2210 | */ | |
2c22569b | 2211 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2212 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2213 | } | |
2214 | ||
e2273302 ID |
2215 | i915_gem_gtt_finish_object(obj); |
2216 | ||
6dacfd2f | 2217 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2218 | i915_gem_object_save_bit_17_swizzle(obj); |
2219 | ||
05394f39 CW |
2220 | if (obj->madv == I915_MADV_DONTNEED) |
2221 | obj->dirty = 0; | |
3ef94daa | 2222 | |
85d1225e | 2223 | for_each_sgt_page(page, sgt_iter, obj->pages) { |
05394f39 | 2224 | if (obj->dirty) |
9da3da66 | 2225 | set_page_dirty(page); |
3ef94daa | 2226 | |
05394f39 | 2227 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2228 | mark_page_accessed(page); |
3ef94daa | 2229 | |
09cbfeaf | 2230 | put_page(page); |
3ef94daa | 2231 | } |
05394f39 | 2232 | obj->dirty = 0; |
673a394b | 2233 | |
9da3da66 CW |
2234 | sg_free_table(obj->pages); |
2235 | kfree(obj->pages); | |
37e680a1 | 2236 | } |
6c085a72 | 2237 | |
dd624afd | 2238 | int |
37e680a1 CW |
2239 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2240 | { | |
2241 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2242 | ||
2f745ad3 | 2243 | if (obj->pages == NULL) |
37e680a1 CW |
2244 | return 0; |
2245 | ||
a5570178 CW |
2246 | if (obj->pages_pin_count) |
2247 | return -EBUSY; | |
2248 | ||
9843877d | 2249 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2250 | |
a2165e31 CW |
2251 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2252 | * array, hence protect them from being reaped by removing them from gtt | |
2253 | * lists early. */ | |
35c20a60 | 2254 | list_del(&obj->global_list); |
a2165e31 | 2255 | |
0a798eb9 | 2256 | if (obj->mapping) { |
fb8621d3 CW |
2257 | if (is_vmalloc_addr(obj->mapping)) |
2258 | vunmap(obj->mapping); | |
2259 | else | |
2260 | kunmap(kmap_to_page(obj->mapping)); | |
0a798eb9 CW |
2261 | obj->mapping = NULL; |
2262 | } | |
2263 | ||
37e680a1 | 2264 | ops->put_pages(obj); |
05394f39 | 2265 | obj->pages = NULL; |
37e680a1 | 2266 | |
5537252b | 2267 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2268 | |
2269 | return 0; | |
2270 | } | |
2271 | ||
37e680a1 | 2272 | static int |
6c085a72 | 2273 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2274 | { |
6c085a72 | 2275 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2276 | int page_count, i; |
2277 | struct address_space *mapping; | |
9da3da66 CW |
2278 | struct sg_table *st; |
2279 | struct scatterlist *sg; | |
85d1225e | 2280 | struct sgt_iter sgt_iter; |
e5281ccd | 2281 | struct page *page; |
90797e6d | 2282 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2283 | int ret; |
6c085a72 | 2284 | gfp_t gfp; |
e5281ccd | 2285 | |
6c085a72 CW |
2286 | /* Assert that the object is not currently in any GPU domain. As it |
2287 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2288 | * a GPU cache | |
2289 | */ | |
2290 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2291 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2292 | ||
9da3da66 CW |
2293 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2294 | if (st == NULL) | |
2295 | return -ENOMEM; | |
2296 | ||
05394f39 | 2297 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2298 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2299 | kfree(st); |
e5281ccd | 2300 | return -ENOMEM; |
9da3da66 | 2301 | } |
e5281ccd | 2302 | |
9da3da66 CW |
2303 | /* Get the list of pages out of our struct file. They'll be pinned |
2304 | * at this point until we release them. | |
2305 | * | |
2306 | * Fail silently without starting the shrinker | |
2307 | */ | |
496ad9aa | 2308 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2309 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2310 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2311 | sg = st->sgl; |
2312 | st->nents = 0; | |
2313 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2314 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2315 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2316 | i915_gem_shrink(dev_priv, |
2317 | page_count, | |
2318 | I915_SHRINK_BOUND | | |
2319 | I915_SHRINK_UNBOUND | | |
2320 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2321 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2322 | } | |
2323 | if (IS_ERR(page)) { | |
2324 | /* We've tried hard to allocate the memory by reaping | |
2325 | * our own buffer, now let the real VM do its job and | |
2326 | * go down in flames if truly OOM. | |
2327 | */ | |
6c085a72 | 2328 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2329 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2330 | if (IS_ERR(page)) { |
2331 | ret = PTR_ERR(page); | |
6c085a72 | 2332 | goto err_pages; |
e2273302 | 2333 | } |
6c085a72 | 2334 | } |
426729dc KRW |
2335 | #ifdef CONFIG_SWIOTLB |
2336 | if (swiotlb_nr_tbl()) { | |
2337 | st->nents++; | |
2338 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2339 | sg = sg_next(sg); | |
2340 | continue; | |
2341 | } | |
2342 | #endif | |
90797e6d ID |
2343 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2344 | if (i) | |
2345 | sg = sg_next(sg); | |
2346 | st->nents++; | |
2347 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2348 | } else { | |
2349 | sg->length += PAGE_SIZE; | |
2350 | } | |
2351 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2352 | |
2353 | /* Check that the i965g/gm workaround works. */ | |
2354 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2355 | } |
426729dc KRW |
2356 | #ifdef CONFIG_SWIOTLB |
2357 | if (!swiotlb_nr_tbl()) | |
2358 | #endif | |
2359 | sg_mark_end(sg); | |
74ce6b6c CW |
2360 | obj->pages = st; |
2361 | ||
e2273302 ID |
2362 | ret = i915_gem_gtt_prepare_object(obj); |
2363 | if (ret) | |
2364 | goto err_pages; | |
2365 | ||
6dacfd2f | 2366 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2367 | i915_gem_object_do_bit_17_swizzle(obj); |
2368 | ||
656bfa3a DV |
2369 | if (obj->tiling_mode != I915_TILING_NONE && |
2370 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2371 | i915_gem_object_pin_pages(obj); | |
2372 | ||
e5281ccd CW |
2373 | return 0; |
2374 | ||
2375 | err_pages: | |
90797e6d | 2376 | sg_mark_end(sg); |
85d1225e DG |
2377 | for_each_sgt_page(page, sgt_iter, st) |
2378 | put_page(page); | |
9da3da66 CW |
2379 | sg_free_table(st); |
2380 | kfree(st); | |
0820baf3 CW |
2381 | |
2382 | /* shmemfs first checks if there is enough memory to allocate the page | |
2383 | * and reports ENOSPC should there be insufficient, along with the usual | |
2384 | * ENOMEM for a genuine allocation failure. | |
2385 | * | |
2386 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2387 | * space and so want to translate the error from shmemfs back to our | |
2388 | * usual understanding of ENOMEM. | |
2389 | */ | |
e2273302 ID |
2390 | if (ret == -ENOSPC) |
2391 | ret = -ENOMEM; | |
2392 | ||
2393 | return ret; | |
673a394b EA |
2394 | } |
2395 | ||
37e680a1 CW |
2396 | /* Ensure that the associated pages are gathered from the backing storage |
2397 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2398 | * multiple times before they are released by a single call to | |
2399 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2400 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2401 | * or as the object is itself released. | |
2402 | */ | |
2403 | int | |
2404 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2405 | { | |
2406 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2407 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2408 | int ret; | |
2409 | ||
2f745ad3 | 2410 | if (obj->pages) |
37e680a1 CW |
2411 | return 0; |
2412 | ||
43e28f09 | 2413 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2414 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2415 | return -EFAULT; |
43e28f09 CW |
2416 | } |
2417 | ||
a5570178 CW |
2418 | BUG_ON(obj->pages_pin_count); |
2419 | ||
37e680a1 CW |
2420 | ret = ops->get_pages(obj); |
2421 | if (ret) | |
2422 | return ret; | |
2423 | ||
35c20a60 | 2424 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2425 | |
2426 | obj->get_page.sg = obj->pages->sgl; | |
2427 | obj->get_page.last = 0; | |
2428 | ||
37e680a1 | 2429 | return 0; |
673a394b EA |
2430 | } |
2431 | ||
dd6034c6 DG |
2432 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
2433 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj) | |
2434 | { | |
2435 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
2436 | struct sg_table *sgt = obj->pages; | |
85d1225e DG |
2437 | struct sgt_iter sgt_iter; |
2438 | struct page *page; | |
b338fa47 DG |
2439 | struct page *stack_pages[32]; |
2440 | struct page **pages = stack_pages; | |
dd6034c6 DG |
2441 | unsigned long i = 0; |
2442 | void *addr; | |
2443 | ||
2444 | /* A single page can always be kmapped */ | |
2445 | if (n_pages == 1) | |
2446 | return kmap(sg_page(sgt->sgl)); | |
2447 | ||
b338fa47 DG |
2448 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2449 | /* Too big for stack -- allocate temporary array instead */ | |
2450 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2451 | if (!pages) | |
2452 | return NULL; | |
2453 | } | |
dd6034c6 | 2454 | |
85d1225e DG |
2455 | for_each_sgt_page(page, sgt_iter, sgt) |
2456 | pages[i++] = page; | |
dd6034c6 DG |
2457 | |
2458 | /* Check that we have the expected number of pages */ | |
2459 | GEM_BUG_ON(i != n_pages); | |
2460 | ||
2461 | addr = vmap(pages, n_pages, 0, PAGE_KERNEL); | |
2462 | ||
b338fa47 DG |
2463 | if (pages != stack_pages) |
2464 | drm_free_large(pages); | |
dd6034c6 DG |
2465 | |
2466 | return addr; | |
2467 | } | |
2468 | ||
2469 | /* get, pin, and map the pages of the object into kernel space */ | |
0a798eb9 CW |
2470 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
2471 | { | |
2472 | int ret; | |
2473 | ||
2474 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
2475 | ||
2476 | ret = i915_gem_object_get_pages(obj); | |
2477 | if (ret) | |
2478 | return ERR_PTR(ret); | |
2479 | ||
2480 | i915_gem_object_pin_pages(obj); | |
2481 | ||
dd6034c6 DG |
2482 | if (!obj->mapping) { |
2483 | obj->mapping = i915_gem_object_map(obj); | |
2484 | if (!obj->mapping) { | |
0a798eb9 CW |
2485 | i915_gem_object_unpin_pages(obj); |
2486 | return ERR_PTR(-ENOMEM); | |
2487 | } | |
2488 | } | |
2489 | ||
2490 | return obj->mapping; | |
2491 | } | |
2492 | ||
b4716185 | 2493 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2494 | struct drm_i915_gem_request *req) |
673a394b | 2495 | { |
b4716185 | 2496 | struct drm_i915_gem_object *obj = vma->obj; |
e2f80391 | 2497 | struct intel_engine_cs *engine; |
b2af0376 | 2498 | |
666796da | 2499 | engine = i915_gem_request_get_engine(req); |
673a394b EA |
2500 | |
2501 | /* Add a reference if we're newly entering the active list. */ | |
b4716185 | 2502 | if (obj->active == 0) |
05394f39 | 2503 | drm_gem_object_reference(&obj->base); |
666796da | 2504 | obj->active |= intel_engine_flag(engine); |
e35a41de | 2505 | |
117897f4 | 2506 | list_move_tail(&obj->engine_list[engine->id], &engine->active_list); |
e2f80391 | 2507 | i915_gem_request_assign(&obj->last_read_req[engine->id], req); |
caea7476 | 2508 | |
1c7f4bca | 2509 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
caea7476 CW |
2510 | } |
2511 | ||
b4716185 CW |
2512 | static void |
2513 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) | |
e2d05a8b | 2514 | { |
d501b1d2 CW |
2515 | GEM_BUG_ON(obj->last_write_req == NULL); |
2516 | GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine))); | |
b4716185 CW |
2517 | |
2518 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
de152b62 | 2519 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2520 | } |
2521 | ||
caea7476 | 2522 | static void |
b4716185 | 2523 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
ce44b0ea | 2524 | { |
feb822cf | 2525 | struct i915_vma *vma; |
ce44b0ea | 2526 | |
d501b1d2 CW |
2527 | GEM_BUG_ON(obj->last_read_req[ring] == NULL); |
2528 | GEM_BUG_ON(!(obj->active & (1 << ring))); | |
b4716185 | 2529 | |
117897f4 | 2530 | list_del_init(&obj->engine_list[ring]); |
b4716185 CW |
2531 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
2532 | ||
4a570db5 | 2533 | if (obj->last_write_req && obj->last_write_req->engine->id == ring) |
b4716185 CW |
2534 | i915_gem_object_retire__write(obj); |
2535 | ||
2536 | obj->active &= ~(1 << ring); | |
2537 | if (obj->active) | |
2538 | return; | |
caea7476 | 2539 | |
6c246959 CW |
2540 | /* Bump our place on the bound list to keep it roughly in LRU order |
2541 | * so that we don't steal from recently used but inactive objects | |
2542 | * (unless we are forced to ofc!) | |
2543 | */ | |
2544 | list_move_tail(&obj->global_list, | |
2545 | &to_i915(obj->base.dev)->mm.bound_list); | |
2546 | ||
1c7f4bca CW |
2547 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
2548 | if (!list_empty(&vma->vm_link)) | |
2549 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
feb822cf | 2550 | } |
caea7476 | 2551 | |
97b2a6a1 | 2552 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 | 2553 | drm_gem_object_unreference(&obj->base); |
c8725f3d CW |
2554 | } |
2555 | ||
9d773091 | 2556 | static int |
c033666a | 2557 | i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno) |
53d227f2 | 2558 | { |
e2f80391 | 2559 | struct intel_engine_cs *engine; |
29dcb570 | 2560 | int ret; |
53d227f2 | 2561 | |
107f27a5 | 2562 | /* Carefully retire all requests without writing to the rings */ |
b4ac5afc | 2563 | for_each_engine(engine, dev_priv) { |
666796da | 2564 | ret = intel_engine_idle(engine); |
107f27a5 CW |
2565 | if (ret) |
2566 | return ret; | |
9d773091 | 2567 | } |
c033666a | 2568 | i915_gem_retire_requests(dev_priv); |
107f27a5 CW |
2569 | |
2570 | /* Finally reset hw state */ | |
29dcb570 | 2571 | for_each_engine(engine, dev_priv) |
e2f80391 | 2572 | intel_ring_init_seqno(engine, seqno); |
498d2ac1 | 2573 | |
9d773091 | 2574 | return 0; |
53d227f2 DV |
2575 | } |
2576 | ||
fca26bb4 MK |
2577 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2578 | { | |
2579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2580 | int ret; | |
2581 | ||
2582 | if (seqno == 0) | |
2583 | return -EINVAL; | |
2584 | ||
2585 | /* HWS page needs to be set less than what we | |
2586 | * will inject to ring | |
2587 | */ | |
c033666a | 2588 | ret = i915_gem_init_seqno(dev_priv, seqno - 1); |
fca26bb4 MK |
2589 | if (ret) |
2590 | return ret; | |
2591 | ||
2592 | /* Carefully set the last_seqno value so that wrap | |
2593 | * detection still works | |
2594 | */ | |
2595 | dev_priv->next_seqno = seqno; | |
2596 | dev_priv->last_seqno = seqno - 1; | |
2597 | if (dev_priv->last_seqno == 0) | |
2598 | dev_priv->last_seqno--; | |
2599 | ||
2600 | return 0; | |
2601 | } | |
2602 | ||
9d773091 | 2603 | int |
c033666a | 2604 | i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno) |
53d227f2 | 2605 | { |
9d773091 CW |
2606 | /* reserve 0 for non-seqno */ |
2607 | if (dev_priv->next_seqno == 0) { | |
c033666a | 2608 | int ret = i915_gem_init_seqno(dev_priv, 0); |
9d773091 CW |
2609 | if (ret) |
2610 | return ret; | |
53d227f2 | 2611 | |
9d773091 CW |
2612 | dev_priv->next_seqno = 1; |
2613 | } | |
53d227f2 | 2614 | |
f72b3435 | 2615 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2616 | return 0; |
53d227f2 DV |
2617 | } |
2618 | ||
bf7dc5b7 JH |
2619 | /* |
2620 | * NB: This function is not allowed to fail. Doing so would mean the the | |
2621 | * request is not being tracked for completion but the work itself is | |
2622 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
2623 | */ | |
75289874 | 2624 | void __i915_add_request(struct drm_i915_gem_request *request, |
5b4a60c2 JH |
2625 | struct drm_i915_gem_object *obj, |
2626 | bool flush_caches) | |
673a394b | 2627 | { |
e2f80391 | 2628 | struct intel_engine_cs *engine; |
75289874 | 2629 | struct drm_i915_private *dev_priv; |
48e29f55 | 2630 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2631 | u32 request_start; |
0251a963 | 2632 | u32 reserved_tail; |
3cce469c CW |
2633 | int ret; |
2634 | ||
48e29f55 | 2635 | if (WARN_ON(request == NULL)) |
bf7dc5b7 | 2636 | return; |
48e29f55 | 2637 | |
4a570db5 | 2638 | engine = request->engine; |
39dabecd | 2639 | dev_priv = request->i915; |
75289874 JH |
2640 | ringbuf = request->ringbuf; |
2641 | ||
29b1b415 JH |
2642 | /* |
2643 | * To ensure that this call will not fail, space for its emissions | |
2644 | * should already have been reserved in the ring buffer. Let the ring | |
2645 | * know that it is time to use that space up. | |
2646 | */ | |
48e29f55 | 2647 | request_start = intel_ring_get_tail(ringbuf); |
0251a963 CW |
2648 | reserved_tail = request->reserved_space; |
2649 | request->reserved_space = 0; | |
2650 | ||
cc889e0f DV |
2651 | /* |
2652 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2653 | * after having emitted the batchbuffer command. Hence we need to fix | |
2654 | * things up similar to emitting the lazy request. The difference here | |
2655 | * is that the flush _must_ happen before the next request, no matter | |
2656 | * what. | |
2657 | */ | |
5b4a60c2 JH |
2658 | if (flush_caches) { |
2659 | if (i915.enable_execlists) | |
4866d729 | 2660 | ret = logical_ring_flush_all_caches(request); |
5b4a60c2 | 2661 | else |
4866d729 | 2662 | ret = intel_ring_flush_all_caches(request); |
5b4a60c2 JH |
2663 | /* Not allowed to fail! */ |
2664 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); | |
2665 | } | |
cc889e0f | 2666 | |
7c90b7de CW |
2667 | trace_i915_gem_request_add(request); |
2668 | ||
2669 | request->head = request_start; | |
2670 | ||
2671 | /* Whilst this request exists, batch_obj will be on the | |
2672 | * active_list, and so will hold the active reference. Only when this | |
2673 | * request is retired will the the batch_obj be moved onto the | |
2674 | * inactive_list and lose its active reference. Hence we do not need | |
2675 | * to explicitly hold another reference here. | |
2676 | */ | |
2677 | request->batch_obj = obj; | |
2678 | ||
2679 | /* Seal the request and mark it as pending execution. Note that | |
2680 | * we may inspect this state, without holding any locks, during | |
2681 | * hangcheck. Hence we apply the barrier to ensure that we do not | |
2682 | * see a more recent value in the hws than we are tracking. | |
2683 | */ | |
2684 | request->emitted_jiffies = jiffies; | |
2685 | request->previous_seqno = engine->last_submitted_seqno; | |
2686 | smp_store_mb(engine->last_submitted_seqno, request->seqno); | |
2687 | list_add_tail(&request->list, &engine->request_list); | |
2688 | ||
a71d8d94 CW |
2689 | /* Record the position of the start of the request so that |
2690 | * should we detect the updated seqno part-way through the | |
2691 | * GPU processing the request, we never over-estimate the | |
2692 | * position of the head. | |
2693 | */ | |
6d3d8274 | 2694 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2695 | |
bf7dc5b7 | 2696 | if (i915.enable_execlists) |
e2f80391 | 2697 | ret = engine->emit_request(request); |
bf7dc5b7 | 2698 | else { |
e2f80391 | 2699 | ret = engine->add_request(request); |
53292cdb MT |
2700 | |
2701 | request->tail = intel_ring_get_tail(ringbuf); | |
48e29f55 | 2702 | } |
bf7dc5b7 JH |
2703 | /* Not allowed to fail! */ |
2704 | WARN(ret, "emit|add_request failed: %d!\n", ret); | |
673a394b | 2705 | |
c033666a | 2706 | i915_queue_hangcheck(engine->i915); |
10cd45b6 | 2707 | |
87255483 DV |
2708 | queue_delayed_work(dev_priv->wq, |
2709 | &dev_priv->mm.retire_work, | |
2710 | round_jiffies_up_relative(HZ)); | |
7d993739 | 2711 | intel_mark_busy(dev_priv); |
cc889e0f | 2712 | |
29b1b415 | 2713 | /* Sanity check that the reserved size was large enough. */ |
0251a963 CW |
2714 | ret = intel_ring_get_tail(ringbuf) - request_start; |
2715 | if (ret < 0) | |
2716 | ret += ringbuf->size; | |
2717 | WARN_ONCE(ret > reserved_tail, | |
2718 | "Not enough space reserved (%d bytes) " | |
2719 | "for adding the request (%d bytes)\n", | |
2720 | reserved_tail, ret); | |
673a394b EA |
2721 | } |
2722 | ||
939fd762 | 2723 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
e2efd130 | 2724 | const struct i915_gem_context *ctx) |
be62acb4 | 2725 | { |
44e2c070 | 2726 | unsigned long elapsed; |
be62acb4 | 2727 | |
44e2c070 MK |
2728 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2729 | ||
2730 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2731 | return true; |
2732 | ||
676fa572 CW |
2733 | if (ctx->hang_stats.ban_period_seconds && |
2734 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
ccc7bed0 | 2735 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2736 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2737 | return true; |
88b4aa87 MK |
2738 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2739 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2740 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2741 | return true; |
3fac8978 | 2742 | } |
be62acb4 MK |
2743 | } |
2744 | ||
2745 | return false; | |
2746 | } | |
2747 | ||
939fd762 | 2748 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
e2efd130 | 2749 | struct i915_gem_context *ctx, |
b6b0fac0 | 2750 | const bool guilty) |
aa60c664 | 2751 | { |
44e2c070 MK |
2752 | struct i915_ctx_hang_stats *hs; |
2753 | ||
2754 | if (WARN_ON(!ctx)) | |
2755 | return; | |
aa60c664 | 2756 | |
44e2c070 MK |
2757 | hs = &ctx->hang_stats; |
2758 | ||
2759 | if (guilty) { | |
939fd762 | 2760 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2761 | hs->batch_active++; |
2762 | hs->guilty_ts = get_seconds(); | |
2763 | } else { | |
2764 | hs->batch_pending++; | |
aa60c664 MK |
2765 | } |
2766 | } | |
2767 | ||
abfe262a JH |
2768 | void i915_gem_request_free(struct kref *req_ref) |
2769 | { | |
2770 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2771 | typeof(*req), ref); | |
efab6d8d | 2772 | kmem_cache_free(req->i915->requests, req); |
0e50e96b MK |
2773 | } |
2774 | ||
26827088 | 2775 | static inline int |
0bc40be8 | 2776 | __i915_gem_request_alloc(struct intel_engine_cs *engine, |
e2efd130 | 2777 | struct i915_gem_context *ctx, |
26827088 | 2778 | struct drm_i915_gem_request **req_out) |
6689cb2b | 2779 | { |
c033666a | 2780 | struct drm_i915_private *dev_priv = engine->i915; |
299259a3 | 2781 | unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
eed29a5b | 2782 | struct drm_i915_gem_request *req; |
6689cb2b | 2783 | int ret; |
6689cb2b | 2784 | |
217e46b5 JH |
2785 | if (!req_out) |
2786 | return -EINVAL; | |
2787 | ||
bccca494 | 2788 | *req_out = NULL; |
6689cb2b | 2789 | |
f4457ae7 CW |
2790 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
2791 | * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex | |
2792 | * and restart. | |
2793 | */ | |
2794 | ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible); | |
299259a3 CW |
2795 | if (ret) |
2796 | return ret; | |
2797 | ||
eed29a5b DV |
2798 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
2799 | if (req == NULL) | |
6689cb2b JH |
2800 | return -ENOMEM; |
2801 | ||
c033666a | 2802 | ret = i915_gem_get_seqno(engine->i915, &req->seqno); |
9a0c1e27 CW |
2803 | if (ret) |
2804 | goto err; | |
6689cb2b | 2805 | |
40e895ce JH |
2806 | kref_init(&req->ref); |
2807 | req->i915 = dev_priv; | |
4a570db5 | 2808 | req->engine = engine; |
299259a3 | 2809 | req->reset_counter = reset_counter; |
40e895ce JH |
2810 | req->ctx = ctx; |
2811 | i915_gem_context_reference(req->ctx); | |
6689cb2b | 2812 | |
29b1b415 JH |
2813 | /* |
2814 | * Reserve space in the ring buffer for all the commands required to | |
2815 | * eventually emit this request. This is to guarantee that the | |
2816 | * i915_add_request() call can't fail. Note that the reserve may need | |
2817 | * to be redone if the request is not actually submitted straight | |
2818 | * away, e.g. because a GPU scheduler has deferred it. | |
29b1b415 | 2819 | */ |
0251a963 | 2820 | req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; |
bfa01200 CW |
2821 | |
2822 | if (i915.enable_execlists) | |
2823 | ret = intel_logical_ring_alloc_request_extras(req); | |
2824 | else | |
2825 | ret = intel_ring_alloc_request_extras(req); | |
2826 | if (ret) | |
2827 | goto err_ctx; | |
29b1b415 | 2828 | |
bccca494 | 2829 | *req_out = req; |
6689cb2b | 2830 | return 0; |
9a0c1e27 | 2831 | |
bfa01200 CW |
2832 | err_ctx: |
2833 | i915_gem_context_unreference(ctx); | |
9a0c1e27 CW |
2834 | err: |
2835 | kmem_cache_free(dev_priv->requests, req); | |
2836 | return ret; | |
0e50e96b MK |
2837 | } |
2838 | ||
26827088 DG |
2839 | /** |
2840 | * i915_gem_request_alloc - allocate a request structure | |
2841 | * | |
2842 | * @engine: engine that we wish to issue the request on. | |
2843 | * @ctx: context that the request will be associated with. | |
2844 | * This can be NULL if the request is not directly related to | |
2845 | * any specific user context, in which case this function will | |
2846 | * choose an appropriate context to use. | |
2847 | * | |
2848 | * Returns a pointer to the allocated request if successful, | |
2849 | * or an error code if not. | |
2850 | */ | |
2851 | struct drm_i915_gem_request * | |
2852 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
e2efd130 | 2853 | struct i915_gem_context *ctx) |
26827088 DG |
2854 | { |
2855 | struct drm_i915_gem_request *req; | |
2856 | int err; | |
2857 | ||
2858 | if (ctx == NULL) | |
c033666a | 2859 | ctx = engine->i915->kernel_context; |
26827088 DG |
2860 | err = __i915_gem_request_alloc(engine, ctx, &req); |
2861 | return err ? ERR_PTR(err) : req; | |
2862 | } | |
2863 | ||
8d9fc7fd | 2864 | struct drm_i915_gem_request * |
0bc40be8 | 2865 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2866 | { |
4db080f9 CW |
2867 | struct drm_i915_gem_request *request; |
2868 | ||
0bc40be8 | 2869 | list_for_each_entry(request, &engine->request_list, list) { |
1b5a433a | 2870 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2871 | continue; |
aa60c664 | 2872 | |
b6b0fac0 | 2873 | return request; |
4db080f9 | 2874 | } |
b6b0fac0 MK |
2875 | |
2876 | return NULL; | |
2877 | } | |
2878 | ||
666796da | 2879 | static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv, |
0bc40be8 | 2880 | struct intel_engine_cs *engine) |
b6b0fac0 MK |
2881 | { |
2882 | struct drm_i915_gem_request *request; | |
2883 | bool ring_hung; | |
2884 | ||
0bc40be8 | 2885 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
2886 | |
2887 | if (request == NULL) | |
2888 | return; | |
2889 | ||
0bc40be8 | 2890 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 2891 | |
939fd762 | 2892 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 | 2893 | |
0bc40be8 | 2894 | list_for_each_entry_continue(request, &engine->request_list, list) |
939fd762 | 2895 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2896 | } |
aa60c664 | 2897 | |
666796da | 2898 | static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv, |
0bc40be8 | 2899 | struct intel_engine_cs *engine) |
4db080f9 | 2900 | { |
608c1a52 CW |
2901 | struct intel_ringbuffer *buffer; |
2902 | ||
0bc40be8 | 2903 | while (!list_empty(&engine->active_list)) { |
05394f39 | 2904 | struct drm_i915_gem_object *obj; |
9375e446 | 2905 | |
0bc40be8 | 2906 | obj = list_first_entry(&engine->active_list, |
05394f39 | 2907 | struct drm_i915_gem_object, |
117897f4 | 2908 | engine_list[engine->id]); |
9375e446 | 2909 | |
0bc40be8 | 2910 | i915_gem_object_retire__read(obj, engine->id); |
673a394b | 2911 | } |
1d62beea | 2912 | |
dcb4c12a OM |
2913 | /* |
2914 | * Clear the execlists queue up before freeing the requests, as those | |
2915 | * are the ones that keep the context and ringbuffer backing objects | |
2916 | * pinned in place. | |
2917 | */ | |
dcb4c12a | 2918 | |
7de1691a | 2919 | if (i915.enable_execlists) { |
27af5eea TU |
2920 | /* Ensure irq handler finishes or is cancelled. */ |
2921 | tasklet_kill(&engine->irq_tasklet); | |
1197b4f2 | 2922 | |
e39d42fa | 2923 | intel_execlists_cancel_requests(engine); |
dcb4c12a OM |
2924 | } |
2925 | ||
1d62beea BW |
2926 | /* |
2927 | * We must free the requests after all the corresponding objects have | |
2928 | * been moved off active lists. Which is the same order as the normal | |
2929 | * retire_requests function does. This is important if object hold | |
2930 | * implicit references on things like e.g. ppgtt address spaces through | |
2931 | * the request. | |
2932 | */ | |
0bc40be8 | 2933 | while (!list_empty(&engine->request_list)) { |
1d62beea BW |
2934 | struct drm_i915_gem_request *request; |
2935 | ||
0bc40be8 | 2936 | request = list_first_entry(&engine->request_list, |
1d62beea BW |
2937 | struct drm_i915_gem_request, |
2938 | list); | |
2939 | ||
b4716185 | 2940 | i915_gem_request_retire(request); |
1d62beea | 2941 | } |
608c1a52 CW |
2942 | |
2943 | /* Having flushed all requests from all queues, we know that all | |
2944 | * ringbuffers must now be empty. However, since we do not reclaim | |
2945 | * all space when retiring the request (to prevent HEADs colliding | |
2946 | * with rapid ringbuffer wraparound) the amount of available space | |
2947 | * upon reset is less than when we start. Do one more pass over | |
2948 | * all the ringbuffers to reset last_retired_head. | |
2949 | */ | |
0bc40be8 | 2950 | list_for_each_entry(buffer, &engine->buffers, link) { |
608c1a52 CW |
2951 | buffer->last_retired_head = buffer->tail; |
2952 | intel_ring_update_space(buffer); | |
2953 | } | |
2ed53a94 CW |
2954 | |
2955 | intel_ring_init_seqno(engine, engine->last_submitted_seqno); | |
673a394b EA |
2956 | } |
2957 | ||
069efc1d | 2958 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2959 | { |
77f01230 | 2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2961 | struct intel_engine_cs *engine; |
673a394b | 2962 | |
4db080f9 CW |
2963 | /* |
2964 | * Before we free the objects from the requests, we need to inspect | |
2965 | * them for finding the guilty party. As the requests only borrow | |
2966 | * their reference to the objects, the inspection must be done first. | |
2967 | */ | |
b4ac5afc | 2968 | for_each_engine(engine, dev_priv) |
666796da | 2969 | i915_gem_reset_engine_status(dev_priv, engine); |
4db080f9 | 2970 | |
b4ac5afc | 2971 | for_each_engine(engine, dev_priv) |
666796da | 2972 | i915_gem_reset_engine_cleanup(dev_priv, engine); |
dfaae392 | 2973 | |
acce9ffa BW |
2974 | i915_gem_context_reset(dev); |
2975 | ||
19b2dbde | 2976 | i915_gem_restore_fences(dev); |
b4716185 CW |
2977 | |
2978 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2979 | } |
2980 | ||
2981 | /** | |
2982 | * This function clears the request list as sequence numbers are passed. | |
14bb2c11 | 2983 | * @engine: engine to retire requests on |
673a394b | 2984 | */ |
1cf0ba14 | 2985 | void |
0bc40be8 | 2986 | i915_gem_retire_requests_ring(struct intel_engine_cs *engine) |
673a394b | 2987 | { |
0bc40be8 | 2988 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b | 2989 | |
832a3aad CW |
2990 | /* Retire requests first as we use it above for the early return. |
2991 | * If we retire requests last, we may use a later seqno and so clear | |
2992 | * the requests lists without clearing the active list, leading to | |
2993 | * confusion. | |
e9103038 | 2994 | */ |
0bc40be8 | 2995 | while (!list_empty(&engine->request_list)) { |
673a394b | 2996 | struct drm_i915_gem_request *request; |
673a394b | 2997 | |
0bc40be8 | 2998 | request = list_first_entry(&engine->request_list, |
673a394b EA |
2999 | struct drm_i915_gem_request, |
3000 | list); | |
673a394b | 3001 | |
1b5a433a | 3002 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
3003 | break; |
3004 | ||
b4716185 | 3005 | i915_gem_request_retire(request); |
b84d5f0c | 3006 | } |
673a394b | 3007 | |
832a3aad CW |
3008 | /* Move any buffers on the active list that are no longer referenced |
3009 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
3010 | * before we free the context associated with the requests. | |
3011 | */ | |
0bc40be8 | 3012 | while (!list_empty(&engine->active_list)) { |
832a3aad CW |
3013 | struct drm_i915_gem_object *obj; |
3014 | ||
0bc40be8 TU |
3015 | obj = list_first_entry(&engine->active_list, |
3016 | struct drm_i915_gem_object, | |
117897f4 | 3017 | engine_list[engine->id]); |
832a3aad | 3018 | |
0bc40be8 | 3019 | if (!list_empty(&obj->last_read_req[engine->id]->list)) |
832a3aad CW |
3020 | break; |
3021 | ||
0bc40be8 | 3022 | i915_gem_object_retire__read(obj, engine->id); |
832a3aad CW |
3023 | } |
3024 | ||
0bc40be8 TU |
3025 | if (unlikely(engine->trace_irq_req && |
3026 | i915_gem_request_completed(engine->trace_irq_req, true))) { | |
3027 | engine->irq_put(engine); | |
3028 | i915_gem_request_assign(&engine->trace_irq_req, NULL); | |
9d34e5db | 3029 | } |
23bc5982 | 3030 | |
0bc40be8 | 3031 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b EA |
3032 | } |
3033 | ||
b29c19b6 | 3034 | bool |
c033666a | 3035 | i915_gem_retire_requests(struct drm_i915_private *dev_priv) |
b09a1fec | 3036 | { |
e2f80391 | 3037 | struct intel_engine_cs *engine; |
b29c19b6 | 3038 | bool idle = true; |
b09a1fec | 3039 | |
b4ac5afc | 3040 | for_each_engine(engine, dev_priv) { |
e2f80391 TU |
3041 | i915_gem_retire_requests_ring(engine); |
3042 | idle &= list_empty(&engine->request_list); | |
c86ee3a9 | 3043 | if (i915.enable_execlists) { |
27af5eea | 3044 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 3045 | idle &= list_empty(&engine->execlist_queue); |
27af5eea | 3046 | spin_unlock_bh(&engine->execlist_lock); |
c86ee3a9 | 3047 | } |
b29c19b6 CW |
3048 | } |
3049 | ||
3050 | if (idle) | |
3051 | mod_delayed_work(dev_priv->wq, | |
3052 | &dev_priv->mm.idle_work, | |
3053 | msecs_to_jiffies(100)); | |
3054 | ||
3055 | return idle; | |
b09a1fec CW |
3056 | } |
3057 | ||
75ef9da2 | 3058 | static void |
673a394b EA |
3059 | i915_gem_retire_work_handler(struct work_struct *work) |
3060 | { | |
b29c19b6 CW |
3061 | struct drm_i915_private *dev_priv = |
3062 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
3063 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 3064 | bool idle; |
673a394b | 3065 | |
891b48cf | 3066 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
3067 | idle = false; |
3068 | if (mutex_trylock(&dev->struct_mutex)) { | |
c033666a | 3069 | idle = i915_gem_retire_requests(dev_priv); |
b29c19b6 | 3070 | mutex_unlock(&dev->struct_mutex); |
673a394b | 3071 | } |
b29c19b6 | 3072 | if (!idle) |
bcb45086 CW |
3073 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
3074 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 3075 | } |
0a58705b | 3076 | |
b29c19b6 CW |
3077 | static void |
3078 | i915_gem_idle_work_handler(struct work_struct *work) | |
3079 | { | |
3080 | struct drm_i915_private *dev_priv = | |
3081 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
35c94185 | 3082 | struct drm_device *dev = dev_priv->dev; |
b4ac5afc | 3083 | struct intel_engine_cs *engine; |
b29c19b6 | 3084 | |
b4ac5afc DG |
3085 | for_each_engine(engine, dev_priv) |
3086 | if (!list_empty(&engine->request_list)) | |
423795cb | 3087 | return; |
35c94185 | 3088 | |
30ecad77 | 3089 | /* we probably should sync with hangcheck here, using cancel_work_sync. |
b4ac5afc | 3090 | * Also locking seems to be fubar here, engine->request_list is protected |
30ecad77 DV |
3091 | * by dev->struct_mutex. */ |
3092 | ||
7d993739 | 3093 | intel_mark_idle(dev_priv); |
35c94185 CW |
3094 | |
3095 | if (mutex_trylock(&dev->struct_mutex)) { | |
b4ac5afc | 3096 | for_each_engine(engine, dev_priv) |
e2f80391 | 3097 | i915_gem_batch_pool_fini(&engine->batch_pool); |
b29c19b6 | 3098 | |
35c94185 CW |
3099 | mutex_unlock(&dev->struct_mutex); |
3100 | } | |
673a394b EA |
3101 | } |
3102 | ||
30dfebf3 DV |
3103 | /** |
3104 | * Ensures that an object will eventually get non-busy by flushing any required | |
3105 | * write domains, emitting any outstanding lazy request and retiring and | |
3106 | * completed requests. | |
14bb2c11 | 3107 | * @obj: object to flush |
30dfebf3 DV |
3108 | */ |
3109 | static int | |
3110 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
3111 | { | |
a5ac0f90 | 3112 | int i; |
b4716185 CW |
3113 | |
3114 | if (!obj->active) | |
3115 | return 0; | |
30dfebf3 | 3116 | |
666796da | 3117 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 | 3118 | struct drm_i915_gem_request *req; |
41c52415 | 3119 | |
b4716185 CW |
3120 | req = obj->last_read_req[i]; |
3121 | if (req == NULL) | |
3122 | continue; | |
3123 | ||
e6db7469 | 3124 | if (i915_gem_request_completed(req, true)) |
b4716185 | 3125 | i915_gem_object_retire__read(obj, i); |
30dfebf3 DV |
3126 | } |
3127 | ||
3128 | return 0; | |
3129 | } | |
3130 | ||
23ba4fd0 BW |
3131 | /** |
3132 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
3133 | * @dev: drm device pointer |
3134 | * @data: ioctl data blob | |
3135 | * @file: drm file pointer | |
23ba4fd0 BW |
3136 | * |
3137 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3138 | * the timeout parameter. | |
3139 | * -ETIME: object is still busy after timeout | |
3140 | * -ERESTARTSYS: signal interrupted the wait | |
3141 | * -ENONENT: object doesn't exist | |
3142 | * Also possible, but rare: | |
3143 | * -EAGAIN: GPU wedged | |
3144 | * -ENOMEM: damn | |
3145 | * -ENODEV: Internal IRQ fail | |
3146 | * -E?: The add request failed | |
3147 | * | |
3148 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3149 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3150 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3151 | * without holding struct_mutex the object may become re-busied before this | |
3152 | * function completes. A similar but shorter * race condition exists in the busy | |
3153 | * ioctl | |
3154 | */ | |
3155 | int | |
3156 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3157 | { | |
3158 | struct drm_i915_gem_wait *args = data; | |
3159 | struct drm_i915_gem_object *obj; | |
666796da | 3160 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 CW |
3161 | int i, n = 0; |
3162 | int ret; | |
23ba4fd0 | 3163 | |
11b5d511 DV |
3164 | if (args->flags != 0) |
3165 | return -EINVAL; | |
3166 | ||
23ba4fd0 BW |
3167 | ret = i915_mutex_lock_interruptible(dev); |
3168 | if (ret) | |
3169 | return ret; | |
3170 | ||
a8ad0bd8 | 3171 | obj = to_intel_bo(drm_gem_object_lookup(file, args->bo_handle)); |
23ba4fd0 BW |
3172 | if (&obj->base == NULL) { |
3173 | mutex_unlock(&dev->struct_mutex); | |
3174 | return -ENOENT; | |
3175 | } | |
3176 | ||
30dfebf3 DV |
3177 | /* Need to make sure the object gets inactive eventually. */ |
3178 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
3179 | if (ret) |
3180 | goto out; | |
3181 | ||
b4716185 | 3182 | if (!obj->active) |
97b2a6a1 | 3183 | goto out; |
23ba4fd0 | 3184 | |
23ba4fd0 | 3185 | /* Do this after OLR check to make sure we make forward progress polling |
762e4583 | 3186 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
23ba4fd0 | 3187 | */ |
762e4583 | 3188 | if (args->timeout_ns == 0) { |
23ba4fd0 BW |
3189 | ret = -ETIME; |
3190 | goto out; | |
3191 | } | |
3192 | ||
3193 | drm_gem_object_unreference(&obj->base); | |
b4716185 | 3194 | |
666796da | 3195 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
3196 | if (obj->last_read_req[i] == NULL) |
3197 | continue; | |
3198 | ||
3199 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); | |
3200 | } | |
3201 | ||
23ba4fd0 BW |
3202 | mutex_unlock(&dev->struct_mutex); |
3203 | ||
b4716185 CW |
3204 | for (i = 0; i < n; i++) { |
3205 | if (ret == 0) | |
299259a3 | 3206 | ret = __i915_wait_request(req[i], true, |
b4716185 | 3207 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
b6aa0873 | 3208 | to_rps_client(file)); |
73db04cf | 3209 | i915_gem_request_unreference(req[i]); |
b4716185 | 3210 | } |
ff865885 | 3211 | return ret; |
23ba4fd0 BW |
3212 | |
3213 | out: | |
3214 | drm_gem_object_unreference(&obj->base); | |
3215 | mutex_unlock(&dev->struct_mutex); | |
3216 | return ret; | |
3217 | } | |
3218 | ||
b4716185 CW |
3219 | static int |
3220 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3221 | struct intel_engine_cs *to, | |
91af127f JH |
3222 | struct drm_i915_gem_request *from_req, |
3223 | struct drm_i915_gem_request **to_req) | |
b4716185 CW |
3224 | { |
3225 | struct intel_engine_cs *from; | |
3226 | int ret; | |
3227 | ||
666796da | 3228 | from = i915_gem_request_get_engine(from_req); |
b4716185 CW |
3229 | if (to == from) |
3230 | return 0; | |
3231 | ||
91af127f | 3232 | if (i915_gem_request_completed(from_req, true)) |
b4716185 CW |
3233 | return 0; |
3234 | ||
c033666a | 3235 | if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) { |
a6f766f3 | 3236 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
91af127f | 3237 | ret = __i915_wait_request(from_req, |
a6f766f3 CW |
3238 | i915->mm.interruptible, |
3239 | NULL, | |
3240 | &i915->rps.semaphores); | |
b4716185 CW |
3241 | if (ret) |
3242 | return ret; | |
3243 | ||
91af127f | 3244 | i915_gem_object_retire_request(obj, from_req); |
b4716185 CW |
3245 | } else { |
3246 | int idx = intel_ring_sync_index(from, to); | |
91af127f JH |
3247 | u32 seqno = i915_gem_request_get_seqno(from_req); |
3248 | ||
3249 | WARN_ON(!to_req); | |
b4716185 CW |
3250 | |
3251 | if (seqno <= from->semaphore.sync_seqno[idx]) | |
3252 | return 0; | |
3253 | ||
91af127f | 3254 | if (*to_req == NULL) { |
26827088 DG |
3255 | struct drm_i915_gem_request *req; |
3256 | ||
3257 | req = i915_gem_request_alloc(to, NULL); | |
3258 | if (IS_ERR(req)) | |
3259 | return PTR_ERR(req); | |
3260 | ||
3261 | *to_req = req; | |
91af127f JH |
3262 | } |
3263 | ||
599d924c JH |
3264 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
3265 | ret = to->semaphore.sync_to(*to_req, from, seqno); | |
b4716185 CW |
3266 | if (ret) |
3267 | return ret; | |
3268 | ||
3269 | /* We use last_read_req because sync_to() | |
3270 | * might have just caused seqno wrap under | |
3271 | * the radar. | |
3272 | */ | |
3273 | from->semaphore.sync_seqno[idx] = | |
3274 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); | |
3275 | } | |
3276 | ||
3277 | return 0; | |
3278 | } | |
3279 | ||
5816d648 BW |
3280 | /** |
3281 | * i915_gem_object_sync - sync an object to a ring. | |
3282 | * | |
3283 | * @obj: object which may be in use on another ring. | |
3284 | * @to: ring we wish to use the object on. May be NULL. | |
91af127f JH |
3285 | * @to_req: request we wish to use the object for. See below. |
3286 | * This will be allocated and returned if a request is | |
3287 | * required but not passed in. | |
5816d648 BW |
3288 | * |
3289 | * This code is meant to abstract object synchronization with the GPU. | |
3290 | * Calling with NULL implies synchronizing the object with the CPU | |
b4716185 | 3291 | * rather than a particular GPU ring. Conceptually we serialise writes |
91af127f | 3292 | * between engines inside the GPU. We only allow one engine to write |
b4716185 CW |
3293 | * into a buffer at any time, but multiple readers. To ensure each has |
3294 | * a coherent view of memory, we must: | |
3295 | * | |
3296 | * - If there is an outstanding write request to the object, the new | |
3297 | * request must wait for it to complete (either CPU or in hw, requests | |
3298 | * on the same ring will be naturally ordered). | |
3299 | * | |
3300 | * - If we are a write request (pending_write_domain is set), the new | |
3301 | * request must wait for outstanding read requests to complete. | |
5816d648 | 3302 | * |
91af127f JH |
3303 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
3304 | * rings to_req must be non-NULL. However, a request does not have to be | |
3305 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a | |
3306 | * request will be allocated automatically and returned through *to_req. Note | |
3307 | * that it is not guaranteed that commands will be emitted (because the system | |
3308 | * might already be idle). Hence there is no need to create a request that | |
3309 | * might never have any work submitted. Note further that if a request is | |
3310 | * returned in *to_req, it is the responsibility of the caller to submit | |
3311 | * that request (after potentially adding more work to it). | |
3312 | * | |
5816d648 BW |
3313 | * Returns 0 if successful, else propagates up the lower layer error. |
3314 | */ | |
2911a35b BW |
3315 | int |
3316 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
91af127f JH |
3317 | struct intel_engine_cs *to, |
3318 | struct drm_i915_gem_request **to_req) | |
2911a35b | 3319 | { |
b4716185 | 3320 | const bool readonly = obj->base.pending_write_domain == 0; |
666796da | 3321 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 | 3322 | int ret, i, n; |
41c52415 | 3323 | |
b4716185 | 3324 | if (!obj->active) |
2911a35b BW |
3325 | return 0; |
3326 | ||
b4716185 CW |
3327 | if (to == NULL) |
3328 | return i915_gem_object_wait_rendering(obj, readonly); | |
2911a35b | 3329 | |
b4716185 CW |
3330 | n = 0; |
3331 | if (readonly) { | |
3332 | if (obj->last_write_req) | |
3333 | req[n++] = obj->last_write_req; | |
3334 | } else { | |
666796da | 3335 | for (i = 0; i < I915_NUM_ENGINES; i++) |
b4716185 CW |
3336 | if (obj->last_read_req[i]) |
3337 | req[n++] = obj->last_read_req[i]; | |
3338 | } | |
3339 | for (i = 0; i < n; i++) { | |
91af127f | 3340 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
b4716185 CW |
3341 | if (ret) |
3342 | return ret; | |
3343 | } | |
2911a35b | 3344 | |
b4716185 | 3345 | return 0; |
2911a35b BW |
3346 | } |
3347 | ||
b5ffc9bc CW |
3348 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3349 | { | |
3350 | u32 old_write_domain, old_read_domains; | |
3351 | ||
b5ffc9bc CW |
3352 | /* Force a pagefault for domain tracking on next user access */ |
3353 | i915_gem_release_mmap(obj); | |
3354 | ||
b97c3d9c KP |
3355 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3356 | return; | |
3357 | ||
b5ffc9bc CW |
3358 | old_read_domains = obj->base.read_domains; |
3359 | old_write_domain = obj->base.write_domain; | |
3360 | ||
3361 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3362 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3363 | ||
3364 | trace_i915_gem_object_change_domain(obj, | |
3365 | old_read_domains, | |
3366 | old_write_domain); | |
3367 | } | |
3368 | ||
8ef8561f CW |
3369 | static void __i915_vma_iounmap(struct i915_vma *vma) |
3370 | { | |
3371 | GEM_BUG_ON(vma->pin_count); | |
3372 | ||
3373 | if (vma->iomap == NULL) | |
3374 | return; | |
3375 | ||
3376 | io_mapping_unmap(vma->iomap); | |
3377 | vma->iomap = NULL; | |
3378 | } | |
3379 | ||
e9f24d5f | 3380 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
673a394b | 3381 | { |
07fe0b12 | 3382 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3383 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3384 | int ret; |
673a394b | 3385 | |
1c7f4bca | 3386 | if (list_empty(&vma->obj_link)) |
673a394b EA |
3387 | return 0; |
3388 | ||
0ff501cb DV |
3389 | if (!drm_mm_node_allocated(&vma->node)) { |
3390 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3391 | return 0; |
3392 | } | |
433544bd | 3393 | |
d7f46fc4 | 3394 | if (vma->pin_count) |
31d8d651 | 3395 | return -EBUSY; |
673a394b | 3396 | |
c4670ad0 CW |
3397 | BUG_ON(obj->pages == NULL); |
3398 | ||
e9f24d5f TU |
3399 | if (wait) { |
3400 | ret = i915_gem_object_wait_rendering(obj, false); | |
3401 | if (ret) | |
3402 | return ret; | |
3403 | } | |
a8198eea | 3404 | |
596c5923 | 3405 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
8b1bc9b4 | 3406 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3407 | |
8b1bc9b4 DV |
3408 | /* release the fence reg _after_ flushing */ |
3409 | ret = i915_gem_object_put_fence(obj); | |
3410 | if (ret) | |
3411 | return ret; | |
8ef8561f CW |
3412 | |
3413 | __i915_vma_iounmap(vma); | |
8b1bc9b4 | 3414 | } |
96b47b65 | 3415 | |
07fe0b12 | 3416 | trace_i915_vma_unbind(vma); |
db53a302 | 3417 | |
777dc5bb | 3418 | vma->vm->unbind_vma(vma); |
5e562f1d | 3419 | vma->bound = 0; |
6f65e29a | 3420 | |
1c7f4bca | 3421 | list_del_init(&vma->vm_link); |
596c5923 | 3422 | if (vma->is_ggtt) { |
fe14d5f4 TU |
3423 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
3424 | obj->map_and_fenceable = false; | |
3425 | } else if (vma->ggtt_view.pages) { | |
3426 | sg_free_table(vma->ggtt_view.pages); | |
3427 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 3428 | } |
016a65a3 | 3429 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 3430 | } |
673a394b | 3431 | |
2f633156 BW |
3432 | drm_mm_remove_node(&vma->node); |
3433 | i915_gem_vma_destroy(vma); | |
3434 | ||
3435 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3436 | * no more VMAs exist. */ |
e2273302 | 3437 | if (list_empty(&obj->vma_list)) |
2f633156 | 3438 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
673a394b | 3439 | |
70903c3b CW |
3440 | /* And finally now the object is completely decoupled from this vma, |
3441 | * we can drop its hold on the backing storage and allow it to be | |
3442 | * reaped by the shrinker. | |
3443 | */ | |
3444 | i915_gem_object_unpin_pages(obj); | |
3445 | ||
88241785 | 3446 | return 0; |
54cf91dc CW |
3447 | } |
3448 | ||
e9f24d5f TU |
3449 | int i915_vma_unbind(struct i915_vma *vma) |
3450 | { | |
3451 | return __i915_vma_unbind(vma, true); | |
3452 | } | |
3453 | ||
3454 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) | |
3455 | { | |
3456 | return __i915_vma_unbind(vma, false); | |
3457 | } | |
3458 | ||
b2da9fe5 | 3459 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3460 | { |
3e31c6c0 | 3461 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 3462 | struct intel_engine_cs *engine; |
b4ac5afc | 3463 | int ret; |
4df2faf4 | 3464 | |
4df2faf4 | 3465 | /* Flush everything onto the inactive list. */ |
b4ac5afc | 3466 | for_each_engine(engine, dev_priv) { |
ecdb5fd8 | 3467 | if (!i915.enable_execlists) { |
73cfa865 JH |
3468 | struct drm_i915_gem_request *req; |
3469 | ||
e2f80391 | 3470 | req = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
3471 | if (IS_ERR(req)) |
3472 | return PTR_ERR(req); | |
73cfa865 | 3473 | |
ba01cc93 | 3474 | ret = i915_switch_context(req); |
75289874 | 3475 | i915_add_request_no_flush(req); |
aa9b7810 CW |
3476 | if (ret) |
3477 | return ret; | |
ecdb5fd8 | 3478 | } |
b6c7488d | 3479 | |
666796da | 3480 | ret = intel_engine_idle(engine); |
1ec14ad3 CW |
3481 | if (ret) |
3482 | return ret; | |
3483 | } | |
4df2faf4 | 3484 | |
b4716185 | 3485 | WARN_ON(i915_verify_lists(dev)); |
8a1a49f9 | 3486 | return 0; |
4df2faf4 DV |
3487 | } |
3488 | ||
4144f9b5 | 3489 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3490 | unsigned long cache_level) |
3491 | { | |
4144f9b5 | 3492 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3493 | struct drm_mm_node *other; |
3494 | ||
4144f9b5 CW |
3495 | /* |
3496 | * On some machines we have to be careful when putting differing types | |
3497 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3498 | * domains and dying. During vm initialisation, we decide whether or not | |
3499 | * these constraints apply and set the drm_mm.color_adjust | |
3500 | * appropriately. | |
42d6ab48 | 3501 | */ |
4144f9b5 | 3502 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3503 | return true; |
3504 | ||
c6cfb325 | 3505 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3506 | return true; |
3507 | ||
3508 | if (list_empty(>t_space->node_list)) | |
3509 | return true; | |
3510 | ||
3511 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3512 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3513 | return false; | |
3514 | ||
3515 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3516 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3517 | return false; | |
3518 | ||
3519 | return true; | |
3520 | } | |
3521 | ||
673a394b | 3522 | /** |
91e6711e JL |
3523 | * Finds free space in the GTT aperture and binds the object or a view of it |
3524 | * there. | |
14bb2c11 TU |
3525 | * @obj: object to bind |
3526 | * @vm: address space to bind into | |
3527 | * @ggtt_view: global gtt view if applicable | |
3528 | * @alignment: requested alignment | |
3529 | * @flags: mask of PIN_* flags to use | |
673a394b | 3530 | */ |
262de145 | 3531 | static struct i915_vma * |
07fe0b12 BW |
3532 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3533 | struct i915_address_space *vm, | |
ec7adb6e | 3534 | const struct i915_ggtt_view *ggtt_view, |
07fe0b12 | 3535 | unsigned alignment, |
ec7adb6e | 3536 | uint64_t flags) |
673a394b | 3537 | { |
05394f39 | 3538 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
3539 | struct drm_i915_private *dev_priv = to_i915(dev); |
3540 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
65bd342f | 3541 | u32 fence_alignment, unfenced_alignment; |
101b506a MT |
3542 | u32 search_flag, alloc_flag; |
3543 | u64 start, end; | |
65bd342f | 3544 | u64 size, fence_size; |
2f633156 | 3545 | struct i915_vma *vma; |
07f73f69 | 3546 | int ret; |
673a394b | 3547 | |
91e6711e JL |
3548 | if (i915_is_ggtt(vm)) { |
3549 | u32 view_size; | |
3550 | ||
3551 | if (WARN_ON(!ggtt_view)) | |
3552 | return ERR_PTR(-EINVAL); | |
ec7adb6e | 3553 | |
91e6711e JL |
3554 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
3555 | ||
3556 | fence_size = i915_gem_get_gtt_size(dev, | |
3557 | view_size, | |
3558 | obj->tiling_mode); | |
3559 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3560 | view_size, | |
3561 | obj->tiling_mode, | |
3562 | true); | |
3563 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, | |
3564 | view_size, | |
3565 | obj->tiling_mode, | |
3566 | false); | |
3567 | size = flags & PIN_MAPPABLE ? fence_size : view_size; | |
3568 | } else { | |
3569 | fence_size = i915_gem_get_gtt_size(dev, | |
3570 | obj->base.size, | |
3571 | obj->tiling_mode); | |
3572 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3573 | obj->base.size, | |
3574 | obj->tiling_mode, | |
3575 | true); | |
3576 | unfenced_alignment = | |
3577 | i915_gem_get_gtt_alignment(dev, | |
3578 | obj->base.size, | |
3579 | obj->tiling_mode, | |
3580 | false); | |
3581 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; | |
3582 | } | |
a00b10c3 | 3583 | |
101b506a MT |
3584 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
3585 | end = vm->total; | |
3586 | if (flags & PIN_MAPPABLE) | |
72e96d64 | 3587 | end = min_t(u64, end, ggtt->mappable_end); |
101b506a | 3588 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3589 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3590 | |
673a394b | 3591 | if (alignment == 0) |
1ec9e26d | 3592 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3593 | unfenced_alignment; |
1ec9e26d | 3594 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
91e6711e JL |
3595 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
3596 | ggtt_view ? ggtt_view->type : 0, | |
3597 | alignment); | |
262de145 | 3598 | return ERR_PTR(-EINVAL); |
673a394b EA |
3599 | } |
3600 | ||
91e6711e JL |
3601 | /* If binding the object/GGTT view requires more space than the entire |
3602 | * aperture has, reject it early before evicting everything in a vain | |
3603 | * attempt to find space. | |
654fc607 | 3604 | */ |
91e6711e | 3605 | if (size > end) { |
65bd342f | 3606 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
91e6711e JL |
3607 | ggtt_view ? ggtt_view->type : 0, |
3608 | size, | |
1ec9e26d | 3609 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3610 | end); |
262de145 | 3611 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3612 | } |
3613 | ||
37e680a1 | 3614 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3615 | if (ret) |
262de145 | 3616 | return ERR_PTR(ret); |
6c085a72 | 3617 | |
fbdda6fb CW |
3618 | i915_gem_object_pin_pages(obj); |
3619 | ||
ec7adb6e JL |
3620 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
3621 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3622 | ||
262de145 | 3623 | if (IS_ERR(vma)) |
bc6bc15b | 3624 | goto err_unpin; |
2f633156 | 3625 | |
506a8e87 CW |
3626 | if (flags & PIN_OFFSET_FIXED) { |
3627 | uint64_t offset = flags & PIN_OFFSET_MASK; | |
3628 | ||
3629 | if (offset & (alignment - 1) || offset + size > end) { | |
3630 | ret = -EINVAL; | |
3631 | goto err_free_vma; | |
3632 | } | |
3633 | vma->node.start = offset; | |
3634 | vma->node.size = size; | |
3635 | vma->node.color = obj->cache_level; | |
3636 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3637 | if (ret) { | |
3638 | ret = i915_gem_evict_for_vma(vma); | |
3639 | if (ret == 0) | |
3640 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3641 | } | |
3642 | if (ret) | |
3643 | goto err_free_vma; | |
101b506a | 3644 | } else { |
506a8e87 CW |
3645 | if (flags & PIN_HIGH) { |
3646 | search_flag = DRM_MM_SEARCH_BELOW; | |
3647 | alloc_flag = DRM_MM_CREATE_TOP; | |
3648 | } else { | |
3649 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3650 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3651 | } | |
101b506a | 3652 | |
0a9ae0d7 | 3653 | search_free: |
506a8e87 CW |
3654 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3655 | size, alignment, | |
3656 | obj->cache_level, | |
3657 | start, end, | |
3658 | search_flag, | |
3659 | alloc_flag); | |
3660 | if (ret) { | |
3661 | ret = i915_gem_evict_something(dev, vm, size, alignment, | |
3662 | obj->cache_level, | |
3663 | start, end, | |
3664 | flags); | |
3665 | if (ret == 0) | |
3666 | goto search_free; | |
9731129c | 3667 | |
506a8e87 CW |
3668 | goto err_free_vma; |
3669 | } | |
673a394b | 3670 | } |
4144f9b5 | 3671 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3672 | ret = -EINVAL; |
bc6bc15b | 3673 | goto err_remove_node; |
673a394b EA |
3674 | } |
3675 | ||
fe14d5f4 | 3676 | trace_i915_vma_bind(vma, flags); |
0875546c | 3677 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
fe14d5f4 | 3678 | if (ret) |
e2273302 | 3679 | goto err_remove_node; |
fe14d5f4 | 3680 | |
35c20a60 | 3681 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
1c7f4bca | 3682 | list_add_tail(&vma->vm_link, &vm->inactive_list); |
bf1a1092 | 3683 | |
262de145 | 3684 | return vma; |
2f633156 | 3685 | |
bc6bc15b | 3686 | err_remove_node: |
6286ef9b | 3687 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3688 | err_free_vma: |
2f633156 | 3689 | i915_gem_vma_destroy(vma); |
262de145 | 3690 | vma = ERR_PTR(ret); |
bc6bc15b | 3691 | err_unpin: |
2f633156 | 3692 | i915_gem_object_unpin_pages(obj); |
262de145 | 3693 | return vma; |
673a394b EA |
3694 | } |
3695 | ||
000433b6 | 3696 | bool |
2c22569b CW |
3697 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3698 | bool force) | |
673a394b | 3699 | { |
673a394b EA |
3700 | /* If we don't have a page list set up, then we're not pinned |
3701 | * to GPU, and we can ignore the cache flush because it'll happen | |
3702 | * again at bind time. | |
3703 | */ | |
05394f39 | 3704 | if (obj->pages == NULL) |
000433b6 | 3705 | return false; |
673a394b | 3706 | |
769ce464 ID |
3707 | /* |
3708 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3709 | * marked as wc by the system, or the system is cache-coherent. | |
3710 | */ | |
6a2c4232 | 3711 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3712 | return false; |
769ce464 | 3713 | |
9c23f7fc CW |
3714 | /* If the GPU is snooping the contents of the CPU cache, |
3715 | * we do not need to manually clear the CPU cache lines. However, | |
3716 | * the caches are only snooped when the render cache is | |
3717 | * flushed/invalidated. As we always have to emit invalidations | |
3718 | * and flushes when moving into and out of the RENDER domain, correct | |
3719 | * snooping behaviour occurs naturally as the result of our domain | |
3720 | * tracking. | |
3721 | */ | |
0f71979a CW |
3722 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3723 | obj->cache_dirty = true; | |
000433b6 | 3724 | return false; |
0f71979a | 3725 | } |
9c23f7fc | 3726 | |
1c5d22f7 | 3727 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3728 | drm_clflush_sg(obj->pages); |
0f71979a | 3729 | obj->cache_dirty = false; |
000433b6 CW |
3730 | |
3731 | return true; | |
e47c68e9 EA |
3732 | } |
3733 | ||
3734 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3735 | static void | |
05394f39 | 3736 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3737 | { |
1c5d22f7 CW |
3738 | uint32_t old_write_domain; |
3739 | ||
05394f39 | 3740 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3741 | return; |
3742 | ||
63256ec5 | 3743 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3744 | * to it immediately go to main memory as far as we know, so there's |
3745 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3746 | * |
3747 | * However, we do have to enforce the order so that all writes through | |
3748 | * the GTT land before any writes to the device, such as updates to | |
3749 | * the GATT itself. | |
e47c68e9 | 3750 | */ |
63256ec5 CW |
3751 | wmb(); |
3752 | ||
05394f39 CW |
3753 | old_write_domain = obj->base.write_domain; |
3754 | obj->base.write_domain = 0; | |
1c5d22f7 | 3755 | |
de152b62 | 3756 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3757 | |
1c5d22f7 | 3758 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3759 | obj->base.read_domains, |
1c5d22f7 | 3760 | old_write_domain); |
e47c68e9 EA |
3761 | } |
3762 | ||
3763 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3764 | static void | |
e62b59e4 | 3765 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3766 | { |
1c5d22f7 | 3767 | uint32_t old_write_domain; |
e47c68e9 | 3768 | |
05394f39 | 3769 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3770 | return; |
3771 | ||
e62b59e4 | 3772 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 3773 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 3774 | |
05394f39 CW |
3775 | old_write_domain = obj->base.write_domain; |
3776 | obj->base.write_domain = 0; | |
1c5d22f7 | 3777 | |
de152b62 | 3778 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3779 | |
1c5d22f7 | 3780 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3781 | obj->base.read_domains, |
1c5d22f7 | 3782 | old_write_domain); |
e47c68e9 EA |
3783 | } |
3784 | ||
2ef7eeaa EA |
3785 | /** |
3786 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3787 | * @obj: object to act on |
3788 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3789 | * |
3790 | * This function returns when the move is complete, including waiting on | |
3791 | * flushes to occur. | |
3792 | */ | |
79e53945 | 3793 | int |
2021746e | 3794 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3795 | { |
72e96d64 JL |
3796 | struct drm_device *dev = obj->base.dev; |
3797 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3798 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1c5d22f7 | 3799 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3800 | struct i915_vma *vma; |
e47c68e9 | 3801 | int ret; |
2ef7eeaa | 3802 | |
8d7e3de1 CW |
3803 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3804 | return 0; | |
3805 | ||
0201f1ec | 3806 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3807 | if (ret) |
3808 | return ret; | |
3809 | ||
43566ded CW |
3810 | /* Flush and acquire obj->pages so that we are coherent through |
3811 | * direct access in memory with previous cached writes through | |
3812 | * shmemfs and that our cache domain tracking remains valid. | |
3813 | * For example, if the obj->filp was moved to swap without us | |
3814 | * being notified and releasing the pages, we would mistakenly | |
3815 | * continue to assume that the obj remained out of the CPU cached | |
3816 | * domain. | |
3817 | */ | |
3818 | ret = i915_gem_object_get_pages(obj); | |
3819 | if (ret) | |
3820 | return ret; | |
3821 | ||
e62b59e4 | 3822 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3823 | |
d0a57789 CW |
3824 | /* Serialise direct access to this object with the barriers for |
3825 | * coherent writes from the GPU, by effectively invalidating the | |
3826 | * GTT domain upon first access. | |
3827 | */ | |
3828 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3829 | mb(); | |
3830 | ||
05394f39 CW |
3831 | old_write_domain = obj->base.write_domain; |
3832 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3833 | |
e47c68e9 EA |
3834 | /* It should now be out of any other write domains, and we can update |
3835 | * the domain values for our changes. | |
3836 | */ | |
05394f39 CW |
3837 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3838 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3839 | if (write) { |
05394f39 CW |
3840 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3841 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3842 | obj->dirty = 1; | |
2ef7eeaa EA |
3843 | } |
3844 | ||
1c5d22f7 CW |
3845 | trace_i915_gem_object_change_domain(obj, |
3846 | old_read_domains, | |
3847 | old_write_domain); | |
3848 | ||
8325a09d | 3849 | /* And bump the LRU for this access */ |
43566ded CW |
3850 | vma = i915_gem_obj_to_ggtt(obj); |
3851 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
1c7f4bca | 3852 | list_move_tail(&vma->vm_link, |
72e96d64 | 3853 | &ggtt->base.inactive_list); |
8325a09d | 3854 | |
e47c68e9 EA |
3855 | return 0; |
3856 | } | |
3857 | ||
ef55f92a CW |
3858 | /** |
3859 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3860 | * @obj: object to act on |
3861 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3862 | * |
3863 | * After this function returns, the object will be in the new cache-level | |
3864 | * across all GTT and the contents of the backing storage will be coherent, | |
3865 | * with respect to the new cache-level. In order to keep the backing storage | |
3866 | * coherent for all users, we only allow a single cache level to be set | |
3867 | * globally on the object and prevent it from being changed whilst the | |
3868 | * hardware is reading from the object. That is if the object is currently | |
3869 | * on the scanout it will be set to uncached (or equivalent display | |
3870 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3871 | * that all direct access to the scanout remains coherent. | |
3872 | */ | |
e4ffd173 CW |
3873 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3874 | enum i915_cache_level cache_level) | |
3875 | { | |
7bddb01f | 3876 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3877 | struct i915_vma *vma, *next; |
ef55f92a | 3878 | bool bound = false; |
ed75a55b | 3879 | int ret = 0; |
e4ffd173 CW |
3880 | |
3881 | if (obj->cache_level == cache_level) | |
ed75a55b | 3882 | goto out; |
e4ffd173 | 3883 | |
ef55f92a CW |
3884 | /* Inspect the list of currently bound VMA and unbind any that would |
3885 | * be invalid given the new cache-level. This is principally to | |
3886 | * catch the issue of the CS prefetch crossing page boundaries and | |
3887 | * reading an invalid PTE on older architectures. | |
3888 | */ | |
1c7f4bca | 3889 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
ef55f92a CW |
3890 | if (!drm_mm_node_allocated(&vma->node)) |
3891 | continue; | |
3892 | ||
3893 | if (vma->pin_count) { | |
3894 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3895 | return -EBUSY; | |
3896 | } | |
3897 | ||
4144f9b5 | 3898 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3899 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3900 | if (ret) |
3901 | return ret; | |
ef55f92a CW |
3902 | } else |
3903 | bound = true; | |
42d6ab48 CW |
3904 | } |
3905 | ||
ef55f92a CW |
3906 | /* We can reuse the existing drm_mm nodes but need to change the |
3907 | * cache-level on the PTE. We could simply unbind them all and | |
3908 | * rebind with the correct cache-level on next use. However since | |
3909 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3910 | * rewrite the PTE in the belief that doing so tramples upon less | |
3911 | * state and so involves less work. | |
3912 | */ | |
3913 | if (bound) { | |
3914 | /* Before we change the PTE, the GPU must not be accessing it. | |
3915 | * If we wait upon the object, we know that all the bound | |
3916 | * VMA are no longer active. | |
3917 | */ | |
2e2f351d | 3918 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3919 | if (ret) |
3920 | return ret; | |
3921 | ||
ef55f92a CW |
3922 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
3923 | /* Access to snoopable pages through the GTT is | |
3924 | * incoherent and on some machines causes a hard | |
3925 | * lockup. Relinquish the CPU mmaping to force | |
3926 | * userspace to refault in the pages and we can | |
3927 | * then double check if the GTT mapping is still | |
3928 | * valid for that pointer access. | |
3929 | */ | |
3930 | i915_gem_release_mmap(obj); | |
3931 | ||
3932 | /* As we no longer need a fence for GTT access, | |
3933 | * we can relinquish it now (and so prevent having | |
3934 | * to steal a fence from someone else on the next | |
3935 | * fence request). Note GPU activity would have | |
3936 | * dropped the fence as all snoopable access is | |
3937 | * supposed to be linear. | |
3938 | */ | |
e4ffd173 CW |
3939 | ret = i915_gem_object_put_fence(obj); |
3940 | if (ret) | |
3941 | return ret; | |
ef55f92a CW |
3942 | } else { |
3943 | /* We either have incoherent backing store and | |
3944 | * so no GTT access or the architecture is fully | |
3945 | * coherent. In such cases, existing GTT mmaps | |
3946 | * ignore the cache bit in the PTE and we can | |
3947 | * rewrite it without confusing the GPU or having | |
3948 | * to force userspace to fault back in its mmaps. | |
3949 | */ | |
e4ffd173 CW |
3950 | } |
3951 | ||
1c7f4bca | 3952 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3953 | if (!drm_mm_node_allocated(&vma->node)) |
3954 | continue; | |
3955 | ||
3956 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3957 | if (ret) | |
3958 | return ret; | |
3959 | } | |
e4ffd173 CW |
3960 | } |
3961 | ||
1c7f4bca | 3962 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3963 | vma->node.color = cache_level; |
3964 | obj->cache_level = cache_level; | |
3965 | ||
ed75a55b | 3966 | out: |
ef55f92a CW |
3967 | /* Flush the dirty CPU caches to the backing storage so that the |
3968 | * object is now coherent at its new cache level (with respect | |
3969 | * to the access domain). | |
3970 | */ | |
0f71979a CW |
3971 | if (obj->cache_dirty && |
3972 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
3973 | cpu_write_needs_clflush(obj)) { | |
3974 | if (i915_gem_clflush_object(obj, true)) | |
c033666a | 3975 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
3976 | } |
3977 | ||
e4ffd173 CW |
3978 | return 0; |
3979 | } | |
3980 | ||
199adf40 BW |
3981 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3982 | struct drm_file *file) | |
e6994aee | 3983 | { |
199adf40 | 3984 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3985 | struct drm_i915_gem_object *obj; |
e6994aee | 3986 | |
a8ad0bd8 | 3987 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
432be69d CW |
3988 | if (&obj->base == NULL) |
3989 | return -ENOENT; | |
e6994aee | 3990 | |
651d794f CW |
3991 | switch (obj->cache_level) { |
3992 | case I915_CACHE_LLC: | |
3993 | case I915_CACHE_L3_LLC: | |
3994 | args->caching = I915_CACHING_CACHED; | |
3995 | break; | |
3996 | ||
4257d3ba CW |
3997 | case I915_CACHE_WT: |
3998 | args->caching = I915_CACHING_DISPLAY; | |
3999 | break; | |
4000 | ||
651d794f CW |
4001 | default: |
4002 | args->caching = I915_CACHING_NONE; | |
4003 | break; | |
4004 | } | |
e6994aee | 4005 | |
432be69d CW |
4006 | drm_gem_object_unreference_unlocked(&obj->base); |
4007 | return 0; | |
e6994aee CW |
4008 | } |
4009 | ||
199adf40 BW |
4010 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
4011 | struct drm_file *file) | |
e6994aee | 4012 | { |
fd0fe6ac | 4013 | struct drm_i915_private *dev_priv = dev->dev_private; |
199adf40 | 4014 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
4015 | struct drm_i915_gem_object *obj; |
4016 | enum i915_cache_level level; | |
4017 | int ret; | |
4018 | ||
199adf40 BW |
4019 | switch (args->caching) { |
4020 | case I915_CACHING_NONE: | |
e6994aee CW |
4021 | level = I915_CACHE_NONE; |
4022 | break; | |
199adf40 | 4023 | case I915_CACHING_CACHED: |
e5756c10 ID |
4024 | /* |
4025 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
4026 | * snooped mapping may leave stale data in a corresponding CPU | |
4027 | * cacheline, whereas normally such cachelines would get | |
4028 | * invalidated. | |
4029 | */ | |
ca377809 | 4030 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
4031 | return -ENODEV; |
4032 | ||
e6994aee CW |
4033 | level = I915_CACHE_LLC; |
4034 | break; | |
4257d3ba CW |
4035 | case I915_CACHING_DISPLAY: |
4036 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
4037 | break; | |
e6994aee CW |
4038 | default: |
4039 | return -EINVAL; | |
4040 | } | |
4041 | ||
fd0fe6ac ID |
4042 | intel_runtime_pm_get(dev_priv); |
4043 | ||
3bc2913e BW |
4044 | ret = i915_mutex_lock_interruptible(dev); |
4045 | if (ret) | |
fd0fe6ac | 4046 | goto rpm_put; |
3bc2913e | 4047 | |
a8ad0bd8 | 4048 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
e6994aee CW |
4049 | if (&obj->base == NULL) { |
4050 | ret = -ENOENT; | |
4051 | goto unlock; | |
4052 | } | |
4053 | ||
4054 | ret = i915_gem_object_set_cache_level(obj, level); | |
4055 | ||
4056 | drm_gem_object_unreference(&obj->base); | |
4057 | unlock: | |
4058 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
4059 | rpm_put: |
4060 | intel_runtime_pm_put(dev_priv); | |
4061 | ||
e6994aee CW |
4062 | return ret; |
4063 | } | |
4064 | ||
b9241ea3 | 4065 | /* |
2da3b9b9 CW |
4066 | * Prepare buffer for display plane (scanout, cursors, etc). |
4067 | * Can be called from an uninterruptible phase (modesetting) and allows | |
4068 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
4069 | */ |
4070 | int | |
2da3b9b9 CW |
4071 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
4072 | u32 alignment, | |
e6617330 | 4073 | const struct i915_ggtt_view *view) |
b9241ea3 | 4074 | { |
2da3b9b9 | 4075 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
4076 | int ret; |
4077 | ||
cc98b413 CW |
4078 | /* Mark the pin_display early so that we account for the |
4079 | * display coherency whilst setting up the cache domains. | |
4080 | */ | |
8a0c39b1 | 4081 | obj->pin_display++; |
cc98b413 | 4082 | |
a7ef0640 EA |
4083 | /* The display engine is not coherent with the LLC cache on gen6. As |
4084 | * a result, we make sure that the pinning that is about to occur is | |
4085 | * done with uncached PTEs. This is lowest common denominator for all | |
4086 | * chipsets. | |
4087 | * | |
4088 | * However for gen6+, we could do better by using the GFDT bit instead | |
4089 | * of uncaching, which would allow us to flush all the LLC-cached data | |
4090 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
4091 | */ | |
651d794f CW |
4092 | ret = i915_gem_object_set_cache_level(obj, |
4093 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 4094 | if (ret) |
cc98b413 | 4095 | goto err_unpin_display; |
a7ef0640 | 4096 | |
2da3b9b9 CW |
4097 | /* As the user may map the buffer once pinned in the display plane |
4098 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
4099 | * always use map_and_fenceable for all scanout buffers. | |
4100 | */ | |
50470bb0 TU |
4101 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
4102 | view->type == I915_GGTT_VIEW_NORMAL ? | |
4103 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 4104 | if (ret) |
cc98b413 | 4105 | goto err_unpin_display; |
2da3b9b9 | 4106 | |
e62b59e4 | 4107 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 4108 | |
2da3b9b9 | 4109 | old_write_domain = obj->base.write_domain; |
05394f39 | 4110 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
4111 | |
4112 | /* It should now be out of any other write domains, and we can update | |
4113 | * the domain values for our changes. | |
4114 | */ | |
e5f1d962 | 4115 | obj->base.write_domain = 0; |
05394f39 | 4116 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
4117 | |
4118 | trace_i915_gem_object_change_domain(obj, | |
4119 | old_read_domains, | |
2da3b9b9 | 4120 | old_write_domain); |
b9241ea3 ZW |
4121 | |
4122 | return 0; | |
cc98b413 CW |
4123 | |
4124 | err_unpin_display: | |
8a0c39b1 | 4125 | obj->pin_display--; |
cc98b413 CW |
4126 | return ret; |
4127 | } | |
4128 | ||
4129 | void | |
e6617330 TU |
4130 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
4131 | const struct i915_ggtt_view *view) | |
cc98b413 | 4132 | { |
8a0c39b1 TU |
4133 | if (WARN_ON(obj->pin_display == 0)) |
4134 | return; | |
4135 | ||
e6617330 TU |
4136 | i915_gem_object_ggtt_unpin_view(obj, view); |
4137 | ||
8a0c39b1 | 4138 | obj->pin_display--; |
b9241ea3 ZW |
4139 | } |
4140 | ||
e47c68e9 EA |
4141 | /** |
4142 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
4143 | * @obj: object to act on |
4144 | * @write: requesting write or read-only access | |
e47c68e9 EA |
4145 | * |
4146 | * This function returns when the move is complete, including waiting on | |
4147 | * flushes to occur. | |
4148 | */ | |
dabdfe02 | 4149 | int |
919926ae | 4150 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4151 | { |
1c5d22f7 | 4152 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4153 | int ret; |
4154 | ||
8d7e3de1 CW |
4155 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4156 | return 0; | |
4157 | ||
0201f1ec | 4158 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4159 | if (ret) |
4160 | return ret; | |
4161 | ||
e47c68e9 | 4162 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4163 | |
05394f39 CW |
4164 | old_write_domain = obj->base.write_domain; |
4165 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4166 | |
e47c68e9 | 4167 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4168 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4169 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4170 | |
05394f39 | 4171 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4172 | } |
4173 | ||
4174 | /* It should now be out of any other write domains, and we can update | |
4175 | * the domain values for our changes. | |
4176 | */ | |
05394f39 | 4177 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4178 | |
4179 | /* If we're writing through the CPU, then the GPU read domains will | |
4180 | * need to be invalidated at next use. | |
4181 | */ | |
4182 | if (write) { | |
05394f39 CW |
4183 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4184 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4185 | } |
2ef7eeaa | 4186 | |
1c5d22f7 CW |
4187 | trace_i915_gem_object_change_domain(obj, |
4188 | old_read_domains, | |
4189 | old_write_domain); | |
4190 | ||
2ef7eeaa EA |
4191 | return 0; |
4192 | } | |
4193 | ||
673a394b EA |
4194 | /* Throttle our rendering by waiting until the ring has completed our requests |
4195 | * emitted over 20 msec ago. | |
4196 | * | |
b962442e EA |
4197 | * Note that if we were to use the current jiffies each time around the loop, |
4198 | * we wouldn't escape the function with any frames outstanding if the time to | |
4199 | * render a frame was over 20ms. | |
4200 | * | |
673a394b EA |
4201 | * This should get us reasonable parallelism between CPU and GPU but also |
4202 | * relatively low latency when blocking on a particular request to finish. | |
4203 | */ | |
40a5f0de | 4204 | static int |
f787a5f5 | 4205 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4206 | { |
f787a5f5 CW |
4207 | struct drm_i915_private *dev_priv = dev->dev_private; |
4208 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
d0bc54f2 | 4209 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 4210 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 4211 | int ret; |
93533c29 | 4212 | |
308887aa DV |
4213 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4214 | if (ret) | |
4215 | return ret; | |
4216 | ||
f4457ae7 CW |
4217 | /* ABI: return -EIO if already wedged */ |
4218 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
4219 | return -EIO; | |
e110e8d6 | 4220 | |
1c25595f | 4221 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4222 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4223 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4224 | break; | |
40a5f0de | 4225 | |
fcfa423c JH |
4226 | /* |
4227 | * Note that the request might not have been submitted yet. | |
4228 | * In which case emitted_jiffies will be zero. | |
4229 | */ | |
4230 | if (!request->emitted_jiffies) | |
4231 | continue; | |
4232 | ||
54fb2411 | 4233 | target = request; |
b962442e | 4234 | } |
ff865885 JH |
4235 | if (target) |
4236 | i915_gem_request_reference(target); | |
1c25595f | 4237 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4238 | |
54fb2411 | 4239 | if (target == NULL) |
f787a5f5 | 4240 | return 0; |
2bc43b5c | 4241 | |
299259a3 | 4242 | ret = __i915_wait_request(target, true, NULL, NULL); |
f787a5f5 CW |
4243 | if (ret == 0) |
4244 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4245 | |
73db04cf | 4246 | i915_gem_request_unreference(target); |
ff865885 | 4247 | |
40a5f0de EA |
4248 | return ret; |
4249 | } | |
4250 | ||
d23db88c CW |
4251 | static bool |
4252 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4253 | { | |
4254 | struct drm_i915_gem_object *obj = vma->obj; | |
4255 | ||
4256 | if (alignment && | |
4257 | vma->node.start & (alignment - 1)) | |
4258 | return true; | |
4259 | ||
4260 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4261 | return true; | |
4262 | ||
4263 | if (flags & PIN_OFFSET_BIAS && | |
4264 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4265 | return true; | |
4266 | ||
506a8e87 CW |
4267 | if (flags & PIN_OFFSET_FIXED && |
4268 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
4269 | return true; | |
4270 | ||
d23db88c CW |
4271 | return false; |
4272 | } | |
4273 | ||
d0710abb CW |
4274 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
4275 | { | |
4276 | struct drm_i915_gem_object *obj = vma->obj; | |
4277 | bool mappable, fenceable; | |
4278 | u32 fence_size, fence_alignment; | |
4279 | ||
4280 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4281 | obj->base.size, | |
4282 | obj->tiling_mode); | |
4283 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4284 | obj->base.size, | |
4285 | obj->tiling_mode, | |
4286 | true); | |
4287 | ||
4288 | fenceable = (vma->node.size == fence_size && | |
4289 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4290 | ||
4291 | mappable = (vma->node.start + fence_size <= | |
62106b4f | 4292 | to_i915(obj->base.dev)->ggtt.mappable_end); |
d0710abb CW |
4293 | |
4294 | obj->map_and_fenceable = mappable && fenceable; | |
4295 | } | |
4296 | ||
ec7adb6e JL |
4297 | static int |
4298 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
4299 | struct i915_address_space *vm, | |
4300 | const struct i915_ggtt_view *ggtt_view, | |
4301 | uint32_t alignment, | |
4302 | uint64_t flags) | |
673a394b | 4303 | { |
6e7186af | 4304 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4305 | struct i915_vma *vma; |
ef79e17c | 4306 | unsigned bound; |
673a394b EA |
4307 | int ret; |
4308 | ||
6e7186af BW |
4309 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4310 | return -ENODEV; | |
4311 | ||
bf3d149b | 4312 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4313 | return -EINVAL; |
07fe0b12 | 4314 | |
c826c449 CW |
4315 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4316 | return -EINVAL; | |
4317 | ||
ec7adb6e JL |
4318 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
4319 | return -EINVAL; | |
4320 | ||
4321 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
4322 | i915_gem_obj_to_vma(obj, vm); | |
4323 | ||
07fe0b12 | 4324 | if (vma) { |
d7f46fc4 BW |
4325 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4326 | return -EBUSY; | |
4327 | ||
d23db88c | 4328 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4329 | WARN(vma->pin_count, |
ec7adb6e | 4330 | "bo is already pinned in %s with incorrect alignment:" |
088e0df4 | 4331 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4332 | " obj->map_and_fenceable=%d\n", |
ec7adb6e | 4333 | ggtt_view ? "ggtt" : "ppgtt", |
088e0df4 MT |
4334 | upper_32_bits(vma->node.start), |
4335 | lower_32_bits(vma->node.start), | |
fe14d5f4 | 4336 | alignment, |
d23db88c | 4337 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4338 | obj->map_and_fenceable); |
07fe0b12 | 4339 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4340 | if (ret) |
4341 | return ret; | |
8ea99c92 DV |
4342 | |
4343 | vma = NULL; | |
ac0c6b5a CW |
4344 | } |
4345 | } | |
4346 | ||
ef79e17c | 4347 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4348 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
ec7adb6e JL |
4349 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
4350 | flags); | |
262de145 DV |
4351 | if (IS_ERR(vma)) |
4352 | return PTR_ERR(vma); | |
0875546c DV |
4353 | } else { |
4354 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
fe14d5f4 TU |
4355 | if (ret) |
4356 | return ret; | |
4357 | } | |
74898d7e | 4358 | |
91e6711e JL |
4359 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
4360 | (bound ^ vma->bound) & GLOBAL_BIND) { | |
d0710abb | 4361 | __i915_vma_set_map_and_fenceable(vma); |
91e6711e JL |
4362 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
4363 | } | |
ef79e17c | 4364 | |
8ea99c92 | 4365 | vma->pin_count++; |
673a394b EA |
4366 | return 0; |
4367 | } | |
4368 | ||
ec7adb6e JL |
4369 | int |
4370 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
4371 | struct i915_address_space *vm, | |
4372 | uint32_t alignment, | |
4373 | uint64_t flags) | |
4374 | { | |
4375 | return i915_gem_object_do_pin(obj, vm, | |
4376 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
4377 | alignment, flags); | |
4378 | } | |
4379 | ||
4380 | int | |
4381 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
4382 | const struct i915_ggtt_view *view, | |
4383 | uint32_t alignment, | |
4384 | uint64_t flags) | |
4385 | { | |
72e96d64 JL |
4386 | struct drm_device *dev = obj->base.dev; |
4387 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4388 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
4389 | ||
ade7daa1 | 4390 | BUG_ON(!view); |
ec7adb6e | 4391 | |
72e96d64 | 4392 | return i915_gem_object_do_pin(obj, &ggtt->base, view, |
6fafab76 | 4393 | alignment, flags | PIN_GLOBAL); |
ec7adb6e JL |
4394 | } |
4395 | ||
673a394b | 4396 | void |
e6617330 TU |
4397 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
4398 | const struct i915_ggtt_view *view) | |
673a394b | 4399 | { |
e6617330 | 4400 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 4401 | |
e6617330 | 4402 | WARN_ON(vma->pin_count == 0); |
9abc4648 | 4403 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 4404 | |
30154650 | 4405 | --vma->pin_count; |
673a394b EA |
4406 | } |
4407 | ||
673a394b EA |
4408 | int |
4409 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4410 | struct drm_file *file) |
673a394b EA |
4411 | { |
4412 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4413 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4414 | int ret; |
4415 | ||
76c1dec1 | 4416 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4417 | if (ret) |
76c1dec1 | 4418 | return ret; |
673a394b | 4419 | |
a8ad0bd8 | 4420 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 4421 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4422 | ret = -ENOENT; |
4423 | goto unlock; | |
673a394b | 4424 | } |
d1b851fc | 4425 | |
0be555b6 CW |
4426 | /* Count all active objects as busy, even if they are currently not used |
4427 | * by the gpu. Users of this interface expect objects to eventually | |
4428 | * become non-busy without any further actions, therefore emit any | |
4429 | * necessary flushes here. | |
c4de0a5d | 4430 | */ |
30dfebf3 | 4431 | ret = i915_gem_object_flush_active(obj); |
b4716185 CW |
4432 | if (ret) |
4433 | goto unref; | |
0be555b6 | 4434 | |
426960be CW |
4435 | args->busy = 0; |
4436 | if (obj->active) { | |
4437 | int i; | |
4438 | ||
666796da | 4439 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
426960be CW |
4440 | struct drm_i915_gem_request *req; |
4441 | ||
4442 | req = obj->last_read_req[i]; | |
4443 | if (req) | |
4a570db5 | 4444 | args->busy |= 1 << (16 + req->engine->exec_id); |
426960be CW |
4445 | } |
4446 | if (obj->last_write_req) | |
4a570db5 | 4447 | args->busy |= obj->last_write_req->engine->exec_id; |
426960be | 4448 | } |
673a394b | 4449 | |
b4716185 | 4450 | unref: |
05394f39 | 4451 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4452 | unlock: |
673a394b | 4453 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4454 | return ret; |
673a394b EA |
4455 | } |
4456 | ||
4457 | int | |
4458 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4459 | struct drm_file *file_priv) | |
4460 | { | |
0206e353 | 4461 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4462 | } |
4463 | ||
3ef94daa CW |
4464 | int |
4465 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4466 | struct drm_file *file_priv) | |
4467 | { | |
656bfa3a | 4468 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4469 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4470 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4471 | int ret; |
3ef94daa CW |
4472 | |
4473 | switch (args->madv) { | |
4474 | case I915_MADV_DONTNEED: | |
4475 | case I915_MADV_WILLNEED: | |
4476 | break; | |
4477 | default: | |
4478 | return -EINVAL; | |
4479 | } | |
4480 | ||
1d7cfea1 CW |
4481 | ret = i915_mutex_lock_interruptible(dev); |
4482 | if (ret) | |
4483 | return ret; | |
4484 | ||
a8ad0bd8 | 4485 | obj = to_intel_bo(drm_gem_object_lookup(file_priv, args->handle)); |
c8725226 | 4486 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4487 | ret = -ENOENT; |
4488 | goto unlock; | |
3ef94daa | 4489 | } |
3ef94daa | 4490 | |
d7f46fc4 | 4491 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4492 | ret = -EINVAL; |
4493 | goto out; | |
3ef94daa CW |
4494 | } |
4495 | ||
656bfa3a DV |
4496 | if (obj->pages && |
4497 | obj->tiling_mode != I915_TILING_NONE && | |
4498 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4499 | if (obj->madv == I915_MADV_WILLNEED) | |
4500 | i915_gem_object_unpin_pages(obj); | |
4501 | if (args->madv == I915_MADV_WILLNEED) | |
4502 | i915_gem_object_pin_pages(obj); | |
4503 | } | |
4504 | ||
05394f39 CW |
4505 | if (obj->madv != __I915_MADV_PURGED) |
4506 | obj->madv = args->madv; | |
3ef94daa | 4507 | |
6c085a72 | 4508 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4509 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4510 | i915_gem_object_truncate(obj); |
4511 | ||
05394f39 | 4512 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4513 | |
1d7cfea1 | 4514 | out: |
05394f39 | 4515 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4516 | unlock: |
3ef94daa | 4517 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4518 | return ret; |
3ef94daa CW |
4519 | } |
4520 | ||
37e680a1 CW |
4521 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4522 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4523 | { |
b4716185 CW |
4524 | int i; |
4525 | ||
35c20a60 | 4526 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 4527 | for (i = 0; i < I915_NUM_ENGINES; i++) |
117897f4 | 4528 | INIT_LIST_HEAD(&obj->engine_list[i]); |
b25cb2f8 | 4529 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4530 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4531 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4532 | |
37e680a1 CW |
4533 | obj->ops = ops; |
4534 | ||
0327d6ba CW |
4535 | obj->fence_reg = I915_FENCE_REG_NONE; |
4536 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4537 | |
4538 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4539 | } | |
4540 | ||
37e680a1 | 4541 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 4542 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
4543 | .get_pages = i915_gem_object_get_pages_gtt, |
4544 | .put_pages = i915_gem_object_put_pages_gtt, | |
4545 | }; | |
4546 | ||
d37cd8a8 | 4547 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 4548 | size_t size) |
ac52bc56 | 4549 | { |
c397b908 | 4550 | struct drm_i915_gem_object *obj; |
5949eac4 | 4551 | struct address_space *mapping; |
1a240d4d | 4552 | gfp_t mask; |
fe3db79b | 4553 | int ret; |
ac52bc56 | 4554 | |
42dcedd4 | 4555 | obj = i915_gem_object_alloc(dev); |
c397b908 | 4556 | if (obj == NULL) |
fe3db79b | 4557 | return ERR_PTR(-ENOMEM); |
673a394b | 4558 | |
fe3db79b CW |
4559 | ret = drm_gem_object_init(dev, &obj->base, size); |
4560 | if (ret) | |
4561 | goto fail; | |
673a394b | 4562 | |
bed1ea95 CW |
4563 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4564 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4565 | /* 965gm cannot relocate objects above 4GiB. */ | |
4566 | mask &= ~__GFP_HIGHMEM; | |
4567 | mask |= __GFP_DMA32; | |
4568 | } | |
4569 | ||
496ad9aa | 4570 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4571 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4572 | |
37e680a1 | 4573 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4574 | |
c397b908 DV |
4575 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4576 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4577 | |
3d29b842 ED |
4578 | if (HAS_LLC(dev)) { |
4579 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4580 | * cache) for about a 10% performance improvement |
4581 | * compared to uncached. Graphics requests other than | |
4582 | * display scanout are coherent with the CPU in | |
4583 | * accessing this cache. This means in this mode we | |
4584 | * don't need to clflush on the CPU side, and on the | |
4585 | * GPU side we only need to flush internal caches to | |
4586 | * get data visible to the CPU. | |
4587 | * | |
4588 | * However, we maintain the display planes as UC, and so | |
4589 | * need to rebind when first used as such. | |
4590 | */ | |
4591 | obj->cache_level = I915_CACHE_LLC; | |
4592 | } else | |
4593 | obj->cache_level = I915_CACHE_NONE; | |
4594 | ||
d861e338 DV |
4595 | trace_i915_gem_object_create(obj); |
4596 | ||
05394f39 | 4597 | return obj; |
fe3db79b CW |
4598 | |
4599 | fail: | |
4600 | i915_gem_object_free(obj); | |
4601 | ||
4602 | return ERR_PTR(ret); | |
c397b908 DV |
4603 | } |
4604 | ||
340fbd8c CW |
4605 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4606 | { | |
4607 | /* If we are the last user of the backing storage (be it shmemfs | |
4608 | * pages or stolen etc), we know that the pages are going to be | |
4609 | * immediately released. In this case, we can then skip copying | |
4610 | * back the contents from the GPU. | |
4611 | */ | |
4612 | ||
4613 | if (obj->madv != I915_MADV_WILLNEED) | |
4614 | return false; | |
4615 | ||
4616 | if (obj->base.filp == NULL) | |
4617 | return true; | |
4618 | ||
4619 | /* At first glance, this looks racy, but then again so would be | |
4620 | * userspace racing mmap against close. However, the first external | |
4621 | * reference to the filp can only be obtained through the | |
4622 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4623 | * acquiring such a reference whilst we are in the middle of | |
4624 | * freeing the object. | |
4625 | */ | |
4626 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4627 | } | |
4628 | ||
1488fc08 | 4629 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4630 | { |
1488fc08 | 4631 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4632 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4633 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4634 | struct i915_vma *vma, *next; |
673a394b | 4635 | |
f65c9168 PZ |
4636 | intel_runtime_pm_get(dev_priv); |
4637 | ||
26e12f89 CW |
4638 | trace_i915_gem_object_destroy(obj); |
4639 | ||
1c7f4bca | 4640 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
4641 | int ret; |
4642 | ||
4643 | vma->pin_count = 0; | |
4644 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4645 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4646 | bool was_interruptible; | |
1488fc08 | 4647 | |
07fe0b12 BW |
4648 | was_interruptible = dev_priv->mm.interruptible; |
4649 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4650 | |
07fe0b12 | 4651 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4652 | |
07fe0b12 BW |
4653 | dev_priv->mm.interruptible = was_interruptible; |
4654 | } | |
1488fc08 CW |
4655 | } |
4656 | ||
1d64ae71 BW |
4657 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4658 | * before progressing. */ | |
4659 | if (obj->stolen) | |
4660 | i915_gem_object_unpin_pages(obj); | |
4661 | ||
a071fa00 DV |
4662 | WARN_ON(obj->frontbuffer_bits); |
4663 | ||
656bfa3a DV |
4664 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4665 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4666 | obj->tiling_mode != I915_TILING_NONE) | |
4667 | i915_gem_object_unpin_pages(obj); | |
4668 | ||
401c29f6 BW |
4669 | if (WARN_ON(obj->pages_pin_count)) |
4670 | obj->pages_pin_count = 0; | |
340fbd8c | 4671 | if (discard_backing_storage(obj)) |
5537252b | 4672 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4673 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4674 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4675 | |
9da3da66 CW |
4676 | BUG_ON(obj->pages); |
4677 | ||
2f745ad3 CW |
4678 | if (obj->base.import_attach) |
4679 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4680 | |
5cc9ed4b CW |
4681 | if (obj->ops->release) |
4682 | obj->ops->release(obj); | |
4683 | ||
05394f39 CW |
4684 | drm_gem_object_release(&obj->base); |
4685 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4686 | |
05394f39 | 4687 | kfree(obj->bit_17); |
42dcedd4 | 4688 | i915_gem_object_free(obj); |
f65c9168 PZ |
4689 | |
4690 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4691 | } |
4692 | ||
ec7adb6e JL |
4693 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4694 | struct i915_address_space *vm) | |
e656a6cb DV |
4695 | { |
4696 | struct i915_vma *vma; | |
1c7f4bca | 4697 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
1b683729 TU |
4698 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4699 | vma->vm == vm) | |
e656a6cb | 4700 | return vma; |
ec7adb6e JL |
4701 | } |
4702 | return NULL; | |
4703 | } | |
4704 | ||
4705 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4706 | const struct i915_ggtt_view *view) | |
4707 | { | |
ec7adb6e | 4708 | struct i915_vma *vma; |
e656a6cb | 4709 | |
598b9ec8 | 4710 | GEM_BUG_ON(!view); |
ec7adb6e | 4711 | |
1c7f4bca | 4712 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
598b9ec8 | 4713 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e | 4714 | return vma; |
e656a6cb DV |
4715 | return NULL; |
4716 | } | |
4717 | ||
2f633156 BW |
4718 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4719 | { | |
4720 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4721 | |
4722 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4723 | if (!list_empty(&vma->exec_list)) | |
4724 | return; | |
4725 | ||
596c5923 CW |
4726 | if (!vma->is_ggtt) |
4727 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); | |
b9d06dd9 | 4728 | |
1c7f4bca | 4729 | list_del(&vma->obj_link); |
b93dab6e | 4730 | |
e20d2ab7 | 4731 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
2f633156 BW |
4732 | } |
4733 | ||
e3efda49 | 4734 | static void |
117897f4 | 4735 | i915_gem_stop_engines(struct drm_device *dev) |
e3efda49 CW |
4736 | { |
4737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 4738 | struct intel_engine_cs *engine; |
e3efda49 | 4739 | |
b4ac5afc | 4740 | for_each_engine(engine, dev_priv) |
117897f4 | 4741 | dev_priv->gt.stop_engine(engine); |
e3efda49 CW |
4742 | } |
4743 | ||
29105ccc | 4744 | int |
45c5f202 | 4745 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4746 | { |
3e31c6c0 | 4747 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4748 | int ret = 0; |
28dfe52a | 4749 | |
45c5f202 | 4750 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4751 | ret = i915_gpu_idle(dev); |
f7403347 | 4752 | if (ret) |
45c5f202 | 4753 | goto err; |
f7403347 | 4754 | |
c033666a | 4755 | i915_gem_retire_requests(dev_priv); |
673a394b | 4756 | |
117897f4 | 4757 | i915_gem_stop_engines(dev); |
b2e862d0 | 4758 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4759 | mutex_unlock(&dev->struct_mutex); |
4760 | ||
737b1506 | 4761 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
29105ccc | 4762 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4763 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4764 | |
bdcf120b CW |
4765 | /* Assert that we sucessfully flushed all the work and |
4766 | * reset the GPU back to its idle, low power state. | |
4767 | */ | |
4768 | WARN_ON(dev_priv->mm.busy); | |
4769 | ||
673a394b | 4770 | return 0; |
45c5f202 CW |
4771 | |
4772 | err: | |
4773 | mutex_unlock(&dev->struct_mutex); | |
4774 | return ret; | |
673a394b EA |
4775 | } |
4776 | ||
f691e2f4 DV |
4777 | void i915_gem_init_swizzling(struct drm_device *dev) |
4778 | { | |
3e31c6c0 | 4779 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4780 | |
11782b02 | 4781 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4782 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4783 | return; | |
4784 | ||
4785 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4786 | DISP_TILE_SURFACE_SWIZZLING); | |
4787 | ||
11782b02 DV |
4788 | if (IS_GEN5(dev)) |
4789 | return; | |
4790 | ||
f691e2f4 DV |
4791 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4792 | if (IS_GEN6(dev)) | |
6b26c86d | 4793 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4794 | else if (IS_GEN7(dev)) |
6b26c86d | 4795 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4796 | else if (IS_GEN8(dev)) |
4797 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4798 | else |
4799 | BUG(); | |
f691e2f4 | 4800 | } |
e21af88d | 4801 | |
81e7f200 VS |
4802 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4803 | { | |
4804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4805 | ||
4806 | I915_WRITE(RING_CTL(base), 0); | |
4807 | I915_WRITE(RING_HEAD(base), 0); | |
4808 | I915_WRITE(RING_TAIL(base), 0); | |
4809 | I915_WRITE(RING_START(base), 0); | |
4810 | } | |
4811 | ||
4812 | static void init_unused_rings(struct drm_device *dev) | |
4813 | { | |
4814 | if (IS_I830(dev)) { | |
4815 | init_unused_ring(dev, PRB1_BASE); | |
4816 | init_unused_ring(dev, SRB0_BASE); | |
4817 | init_unused_ring(dev, SRB1_BASE); | |
4818 | init_unused_ring(dev, SRB2_BASE); | |
4819 | init_unused_ring(dev, SRB3_BASE); | |
4820 | } else if (IS_GEN2(dev)) { | |
4821 | init_unused_ring(dev, SRB0_BASE); | |
4822 | init_unused_ring(dev, SRB1_BASE); | |
4823 | } else if (IS_GEN3(dev)) { | |
4824 | init_unused_ring(dev, PRB1_BASE); | |
4825 | init_unused_ring(dev, PRB2_BASE); | |
4826 | } | |
4827 | } | |
4828 | ||
117897f4 | 4829 | int i915_gem_init_engines(struct drm_device *dev) |
8187a2b7 | 4830 | { |
4fc7c971 | 4831 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4832 | int ret; |
68f95ba9 | 4833 | |
5c1143bb | 4834 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4835 | if (ret) |
b6913e4b | 4836 | return ret; |
68f95ba9 CW |
4837 | |
4838 | if (HAS_BSD(dev)) { | |
5c1143bb | 4839 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4840 | if (ret) |
4841 | goto cleanup_render_ring; | |
d1b851fc | 4842 | } |
68f95ba9 | 4843 | |
d39398f5 | 4844 | if (HAS_BLT(dev)) { |
549f7365 CW |
4845 | ret = intel_init_blt_ring_buffer(dev); |
4846 | if (ret) | |
4847 | goto cleanup_bsd_ring; | |
4848 | } | |
4849 | ||
9a8a2213 BW |
4850 | if (HAS_VEBOX(dev)) { |
4851 | ret = intel_init_vebox_ring_buffer(dev); | |
4852 | if (ret) | |
4853 | goto cleanup_blt_ring; | |
4854 | } | |
4855 | ||
845f74a7 ZY |
4856 | if (HAS_BSD2(dev)) { |
4857 | ret = intel_init_bsd2_ring_buffer(dev); | |
4858 | if (ret) | |
4859 | goto cleanup_vebox_ring; | |
4860 | } | |
9a8a2213 | 4861 | |
4fc7c971 BW |
4862 | return 0; |
4863 | ||
9a8a2213 | 4864 | cleanup_vebox_ring: |
117897f4 | 4865 | intel_cleanup_engine(&dev_priv->engine[VECS]); |
4fc7c971 | 4866 | cleanup_blt_ring: |
117897f4 | 4867 | intel_cleanup_engine(&dev_priv->engine[BCS]); |
4fc7c971 | 4868 | cleanup_bsd_ring: |
117897f4 | 4869 | intel_cleanup_engine(&dev_priv->engine[VCS]); |
4fc7c971 | 4870 | cleanup_render_ring: |
117897f4 | 4871 | intel_cleanup_engine(&dev_priv->engine[RCS]); |
4fc7c971 BW |
4872 | |
4873 | return ret; | |
4874 | } | |
4875 | ||
4876 | int | |
4877 | i915_gem_init_hw(struct drm_device *dev) | |
4878 | { | |
3e31c6c0 | 4879 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 4880 | struct intel_engine_cs *engine; |
d200cda6 | 4881 | int ret; |
4fc7c971 | 4882 | |
5e4f5189 CW |
4883 | /* Double layer security blanket, see i915_gem_init() */ |
4884 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4885 | ||
3accaf7e | 4886 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4887 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4888 | |
0bf21347 VS |
4889 | if (IS_HASWELL(dev)) |
4890 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4891 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4892 | |
88a2b2a3 | 4893 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4894 | if (IS_IVYBRIDGE(dev)) { |
4895 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4896 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4897 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4898 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4899 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4900 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4901 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4902 | } | |
88a2b2a3 BW |
4903 | } |
4904 | ||
4fc7c971 BW |
4905 | i915_gem_init_swizzling(dev); |
4906 | ||
d5abdfda DV |
4907 | /* |
4908 | * At least 830 can leave some of the unused rings | |
4909 | * "active" (ie. head != tail) after resume which | |
4910 | * will prevent c3 entry. Makes sure all unused rings | |
4911 | * are totally idle. | |
4912 | */ | |
4913 | init_unused_rings(dev); | |
4914 | ||
ed54c1a1 | 4915 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4916 | |
4ad2fd88 JH |
4917 | ret = i915_ppgtt_init_hw(dev); |
4918 | if (ret) { | |
4919 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4920 | goto out; | |
4921 | } | |
4922 | ||
4923 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4924 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4925 | ret = engine->init_hw(engine); |
35a57ffb | 4926 | if (ret) |
5e4f5189 | 4927 | goto out; |
35a57ffb | 4928 | } |
99433931 | 4929 | |
0ccdacf6 PA |
4930 | intel_mocs_init_l3cc_table(dev); |
4931 | ||
33a732f4 | 4932 | /* We can't enable contexts until all firmware is loaded */ |
1a3d1898 | 4933 | if (HAS_GUC(dev)) { |
f09d675f | 4934 | ret = intel_guc_setup(dev); |
fce91f22 | 4935 | if (ret) |
9f9e539f | 4936 | goto out; |
33a732f4 AD |
4937 | } |
4938 | ||
e84fe803 NH |
4939 | /* |
4940 | * Increment the next seqno by 0x100 so we have a visible break | |
4941 | * on re-initialisation | |
4942 | */ | |
4943 | ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100); | |
e21af88d | 4944 | |
5e4f5189 CW |
4945 | out: |
4946 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4947 | return ret; |
8187a2b7 ZN |
4948 | } |
4949 | ||
1070a42b CW |
4950 | int i915_gem_init(struct drm_device *dev) |
4951 | { | |
4952 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4953 | int ret; |
4954 | ||
1070a42b | 4955 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4956 | |
a83014d3 | 4957 | if (!i915.enable_execlists) { |
f3dc74c0 | 4958 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
117897f4 TU |
4959 | dev_priv->gt.init_engines = i915_gem_init_engines; |
4960 | dev_priv->gt.cleanup_engine = intel_cleanup_engine; | |
4961 | dev_priv->gt.stop_engine = intel_stop_engine; | |
454afebd | 4962 | } else { |
f3dc74c0 | 4963 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
117897f4 TU |
4964 | dev_priv->gt.init_engines = intel_logical_rings_init; |
4965 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; | |
4966 | dev_priv->gt.stop_engine = intel_logical_ring_stop; | |
a83014d3 OM |
4967 | } |
4968 | ||
5e4f5189 CW |
4969 | /* This is just a security blanket to placate dragons. |
4970 | * On some systems, we very sporadically observe that the first TLBs | |
4971 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4972 | * we hold the forcewake during initialisation these problems | |
4973 | * just magically go away. | |
4974 | */ | |
4975 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4976 | ||
72778cb2 | 4977 | i915_gem_init_userptr(dev_priv); |
d85489d3 | 4978 | i915_gem_init_ggtt(dev); |
d62b4892 | 4979 | |
2fa48d8d | 4980 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4981 | if (ret) |
4982 | goto out_unlock; | |
2fa48d8d | 4983 | |
117897f4 | 4984 | ret = dev_priv->gt.init_engines(dev); |
35a57ffb | 4985 | if (ret) |
7bcc3777 | 4986 | goto out_unlock; |
2fa48d8d | 4987 | |
1070a42b | 4988 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4989 | if (ret == -EIO) { |
4990 | /* Allow ring initialisation to fail by marking the GPU as | |
4991 | * wedged. But we only want to do this where the GPU is angry, | |
4992 | * for all other failure, such as an allocation failure, bail. | |
4993 | */ | |
4994 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 4995 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 4996 | ret = 0; |
1070a42b | 4997 | } |
7bcc3777 JN |
4998 | |
4999 | out_unlock: | |
5e4f5189 | 5000 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 5001 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 5002 | |
60990320 | 5003 | return ret; |
1070a42b CW |
5004 | } |
5005 | ||
8187a2b7 | 5006 | void |
117897f4 | 5007 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 5008 | { |
3e31c6c0 | 5009 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 5010 | struct intel_engine_cs *engine; |
8187a2b7 | 5011 | |
b4ac5afc | 5012 | for_each_engine(engine, dev_priv) |
117897f4 | 5013 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
5014 | } |
5015 | ||
64193406 | 5016 | static void |
666796da | 5017 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 5018 | { |
0bc40be8 TU |
5019 | INIT_LIST_HEAD(&engine->active_list); |
5020 | INIT_LIST_HEAD(&engine->request_list); | |
64193406 CW |
5021 | } |
5022 | ||
40ae4e16 ID |
5023 | void |
5024 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
5025 | { | |
5026 | struct drm_device *dev = dev_priv->dev; | |
5027 | ||
5028 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
5029 | !IS_CHERRYVIEW(dev_priv)) | |
5030 | dev_priv->num_fence_regs = 32; | |
5031 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
5032 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
5033 | dev_priv->num_fence_regs = 16; | |
5034 | else | |
5035 | dev_priv->num_fence_regs = 8; | |
5036 | ||
c033666a | 5037 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
5038 | dev_priv->num_fence_regs = |
5039 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
5040 | ||
5041 | /* Initialize fence registers to zero */ | |
5042 | i915_gem_restore_fences(dev); | |
5043 | ||
5044 | i915_gem_detect_bit_6_swizzle(dev); | |
5045 | } | |
5046 | ||
673a394b | 5047 | void |
d64aa096 | 5048 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 5049 | { |
3e31c6c0 | 5050 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
5051 | int i; |
5052 | ||
efab6d8d | 5053 | dev_priv->objects = |
42dcedd4 CW |
5054 | kmem_cache_create("i915_gem_object", |
5055 | sizeof(struct drm_i915_gem_object), 0, | |
5056 | SLAB_HWCACHE_ALIGN, | |
5057 | NULL); | |
e20d2ab7 CW |
5058 | dev_priv->vmas = |
5059 | kmem_cache_create("i915_gem_vma", | |
5060 | sizeof(struct i915_vma), 0, | |
5061 | SLAB_HWCACHE_ALIGN, | |
5062 | NULL); | |
efab6d8d CW |
5063 | dev_priv->requests = |
5064 | kmem_cache_create("i915_gem_request", | |
5065 | sizeof(struct drm_i915_gem_request), 0, | |
5066 | SLAB_HWCACHE_ALIGN, | |
5067 | NULL); | |
673a394b | 5068 | |
fc8c067e | 5069 | INIT_LIST_HEAD(&dev_priv->vm_list); |
a33afea5 | 5070 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
5071 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
5072 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 5073 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
5074 | for (i = 0; i < I915_NUM_ENGINES; i++) |
5075 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 5076 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 5077 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
5078 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
5079 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
5080 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
5081 | i915_gem_idle_work_handler); | |
1f83fee0 | 5082 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 5083 | |
72bfa19c CW |
5084 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
5085 | ||
e84fe803 NH |
5086 | /* |
5087 | * Set initial sequence number for requests. | |
5088 | * Using this number allows the wraparound to happen early, | |
5089 | * catching any obvious problems. | |
5090 | */ | |
5091 | dev_priv->next_seqno = ((u32)~0 - 0x1100); | |
5092 | dev_priv->last_seqno = ((u32)~0 - 0x1101); | |
5093 | ||
19b2dbde | 5094 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 5095 | |
6b95a207 | 5096 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 5097 | |
ce453d81 CW |
5098 | dev_priv->mm.interruptible = true; |
5099 | ||
f99d7069 | 5100 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 5101 | } |
71acb5eb | 5102 | |
d64aa096 ID |
5103 | void i915_gem_load_cleanup(struct drm_device *dev) |
5104 | { | |
5105 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5106 | ||
5107 | kmem_cache_destroy(dev_priv->requests); | |
5108 | kmem_cache_destroy(dev_priv->vmas); | |
5109 | kmem_cache_destroy(dev_priv->objects); | |
5110 | } | |
5111 | ||
461fb99c CW |
5112 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
5113 | { | |
5114 | struct drm_i915_gem_object *obj; | |
5115 | ||
5116 | /* Called just before we write the hibernation image. | |
5117 | * | |
5118 | * We need to update the domain tracking to reflect that the CPU | |
5119 | * will be accessing all the pages to create and restore from the | |
5120 | * hibernation, and so upon restoration those pages will be in the | |
5121 | * CPU domain. | |
5122 | * | |
5123 | * To make sure the hibernation image contains the latest state, | |
5124 | * we update that state just before writing out the image. | |
5125 | */ | |
5126 | ||
5127 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5128 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
5129 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
5130 | } | |
5131 | ||
5132 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5133 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
5134 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
5135 | } | |
5136 | ||
5137 | return 0; | |
5138 | } | |
5139 | ||
f787a5f5 | 5140 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5141 | { |
f787a5f5 | 5142 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
5143 | |
5144 | /* Clean up our request list when the client is going away, so that | |
5145 | * later retire_requests won't dereference our soon-to-be-gone | |
5146 | * file_priv. | |
5147 | */ | |
1c25595f | 5148 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5149 | while (!list_empty(&file_priv->mm.request_list)) { |
5150 | struct drm_i915_gem_request *request; | |
5151 | ||
5152 | request = list_first_entry(&file_priv->mm.request_list, | |
5153 | struct drm_i915_gem_request, | |
5154 | client_list); | |
5155 | list_del(&request->client_list); | |
5156 | request->file_priv = NULL; | |
5157 | } | |
1c25595f | 5158 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 5159 | |
2e1b8730 | 5160 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 5161 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 5162 | list_del(&file_priv->rps.link); |
8d3afd7d | 5163 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 5164 | } |
b29c19b6 CW |
5165 | } |
5166 | ||
5167 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5168 | { | |
5169 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5170 | int ret; |
b29c19b6 CW |
5171 | |
5172 | DRM_DEBUG_DRIVER("\n"); | |
5173 | ||
5174 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5175 | if (!file_priv) | |
5176 | return -ENOMEM; | |
5177 | ||
5178 | file->driver_priv = file_priv; | |
5179 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5180 | file_priv->file = file; |
2e1b8730 | 5181 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
5182 | |
5183 | spin_lock_init(&file_priv->mm.lock); | |
5184 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5185 | |
de1add36 TU |
5186 | file_priv->bsd_ring = -1; |
5187 | ||
e422b888 BW |
5188 | ret = i915_gem_context_open(dev, file); |
5189 | if (ret) | |
5190 | kfree(file_priv); | |
b29c19b6 | 5191 | |
e422b888 | 5192 | return ret; |
b29c19b6 CW |
5193 | } |
5194 | ||
b680c37a DV |
5195 | /** |
5196 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5197 | * @old: current GEM buffer for the frontbuffer slots |
5198 | * @new: new GEM buffer for the frontbuffer slots | |
5199 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5200 | * |
5201 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5202 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5203 | */ | |
a071fa00 DV |
5204 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5205 | struct drm_i915_gem_object *new, | |
5206 | unsigned frontbuffer_bits) | |
5207 | { | |
5208 | if (old) { | |
5209 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5210 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5211 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5212 | } | |
5213 | ||
5214 | if (new) { | |
5215 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5216 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5217 | new->frontbuffer_bits |= frontbuffer_bits; | |
5218 | } | |
5219 | } | |
5220 | ||
a70a3148 | 5221 | /* All the new VM stuff */ |
088e0df4 MT |
5222 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
5223 | struct i915_address_space *vm) | |
a70a3148 BW |
5224 | { |
5225 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5226 | struct i915_vma *vma; | |
5227 | ||
896ab1a5 | 5228 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5229 | |
1c7f4bca | 5230 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5231 | if (vma->is_ggtt && |
ec7adb6e JL |
5232 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5233 | continue; | |
5234 | if (vma->vm == vm) | |
a70a3148 | 5235 | return vma->node.start; |
a70a3148 | 5236 | } |
ec7adb6e | 5237 | |
f25748ea DV |
5238 | WARN(1, "%s vma for this object not found.\n", |
5239 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5240 | return -1; |
5241 | } | |
5242 | ||
088e0df4 MT |
5243 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
5244 | const struct i915_ggtt_view *view) | |
a70a3148 BW |
5245 | { |
5246 | struct i915_vma *vma; | |
5247 | ||
1c7f4bca | 5248 | list_for_each_entry(vma, &o->vma_list, obj_link) |
8aac2220 | 5249 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e JL |
5250 | return vma->node.start; |
5251 | ||
5678ad73 | 5252 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
5253 | return -1; |
5254 | } | |
5255 | ||
5256 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5257 | struct i915_address_space *vm) | |
5258 | { | |
5259 | struct i915_vma *vma; | |
5260 | ||
1c7f4bca | 5261 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5262 | if (vma->is_ggtt && |
ec7adb6e JL |
5263 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5264 | continue; | |
5265 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
5266 | return true; | |
5267 | } | |
5268 | ||
5269 | return false; | |
5270 | } | |
5271 | ||
5272 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5273 | const struct i915_ggtt_view *view) |
ec7adb6e | 5274 | { |
ec7adb6e JL |
5275 | struct i915_vma *vma; |
5276 | ||
1c7f4bca | 5277 | list_for_each_entry(vma, &o->vma_list, obj_link) |
ff5ec22d | 5278 | if (vma->is_ggtt && |
9abc4648 | 5279 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 5280 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5281 | return true; |
5282 | ||
5283 | return false; | |
5284 | } | |
5285 | ||
5286 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5287 | { | |
5a1d5eb0 | 5288 | struct i915_vma *vma; |
a70a3148 | 5289 | |
1c7f4bca | 5290 | list_for_each_entry(vma, &o->vma_list, obj_link) |
5a1d5eb0 | 5291 | if (drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5292 | return true; |
5293 | ||
5294 | return false; | |
5295 | } | |
5296 | ||
8da32727 | 5297 | unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o) |
a70a3148 | 5298 | { |
a70a3148 BW |
5299 | struct i915_vma *vma; |
5300 | ||
8da32727 | 5301 | GEM_BUG_ON(list_empty(&o->vma_list)); |
a70a3148 | 5302 | |
1c7f4bca | 5303 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5304 | if (vma->is_ggtt && |
8da32727 | 5305 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
a70a3148 | 5306 | return vma->node.size; |
ec7adb6e | 5307 | } |
8da32727 | 5308 | |
a70a3148 BW |
5309 | return 0; |
5310 | } | |
5311 | ||
ec7adb6e | 5312 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
5313 | { |
5314 | struct i915_vma *vma; | |
1c7f4bca | 5315 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
ec7adb6e JL |
5316 | if (vma->pin_count > 0) |
5317 | return true; | |
a6631ae1 | 5318 | |
ec7adb6e | 5319 | return false; |
5c2abbea | 5320 | } |
ea70299d | 5321 | |
033908ae DG |
5322 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
5323 | struct page * | |
5324 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
5325 | { | |
5326 | struct page *page; | |
5327 | ||
5328 | /* Only default objects have per-page dirty tracking */ | |
de472664 | 5329 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
033908ae DG |
5330 | return NULL; |
5331 | ||
5332 | page = i915_gem_object_get_page(obj, n); | |
5333 | set_page_dirty(page); | |
5334 | return page; | |
5335 | } | |
5336 | ||
ea70299d DG |
5337 | /* Allocate a new GEM object and fill it with the supplied data */ |
5338 | struct drm_i915_gem_object * | |
5339 | i915_gem_object_create_from_data(struct drm_device *dev, | |
5340 | const void *data, size_t size) | |
5341 | { | |
5342 | struct drm_i915_gem_object *obj; | |
5343 | struct sg_table *sg; | |
5344 | size_t bytes; | |
5345 | int ret; | |
5346 | ||
d37cd8a8 | 5347 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 5348 | if (IS_ERR(obj)) |
ea70299d DG |
5349 | return obj; |
5350 | ||
5351 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
5352 | if (ret) | |
5353 | goto fail; | |
5354 | ||
5355 | ret = i915_gem_object_get_pages(obj); | |
5356 | if (ret) | |
5357 | goto fail; | |
5358 | ||
5359 | i915_gem_object_pin_pages(obj); | |
5360 | sg = obj->pages; | |
5361 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 5362 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
5363 | i915_gem_object_unpin_pages(obj); |
5364 | ||
5365 | if (WARN_ON(bytes != size)) { | |
5366 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
5367 | ret = -EFAULT; | |
5368 | goto fail; | |
5369 | } | |
5370 | ||
5371 | return obj; | |
5372 | ||
5373 | fail: | |
5374 | drm_gem_object_unreference(&obj->base); | |
5375 | return ERR_PTR(ret); | |
5376 | } |