Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
2cfcd32a | 34 | #include <linux/oom.h> |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
43 | bool force); | |
07fe0b12 | 44 | static __must_check int |
23f54483 BW |
45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
46 | bool readonly); | |
c8725f3d CW |
47 | static void |
48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
49 | ||
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
ceabbba5 | 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 57 | struct shrink_control *sc); |
ceabbba5 | 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 59 | struct shrink_control *sc); |
2cfcd32a CW |
60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
61 | unsigned long event, | |
62 | void *ptr); | |
d9973b43 | 63 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
31169714 | 64 | |
c76ce038 CW |
65 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
66 | enum i915_cache_level level) | |
67 | { | |
68 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
69 | } | |
70 | ||
2c22569b CW |
71 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
72 | { | |
73 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
74 | return true; | |
75 | ||
76 | return obj->pin_display; | |
77 | } | |
78 | ||
61050808 CW |
79 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
80 | { | |
81 | if (obj->tiling_mode) | |
82 | i915_gem_release_mmap(obj); | |
83 | ||
84 | /* As we do not have an associated fence register, we will force | |
85 | * a tiling change if we ever need to acquire one. | |
86 | */ | |
5d82e3e6 | 87 | obj->fence_dirty = false; |
61050808 CW |
88 | obj->fence_reg = I915_FENCE_REG_NONE; |
89 | } | |
90 | ||
73aa808f CW |
91 | /* some bookkeeping */ |
92 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
93 | size_t size) | |
94 | { | |
c20e8355 | 95 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
96 | dev_priv->mm.object_count++; |
97 | dev_priv->mm.object_memory += size; | |
c20e8355 | 98 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | } |
100 | ||
101 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
102 | size_t size) | |
103 | { | |
c20e8355 | 104 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | dev_priv->mm.object_count--; |
106 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 107 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
108 | } |
109 | ||
21dd3734 | 110 | static int |
33196ded | 111 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 112 | { |
30dbf0c0 CW |
113 | int ret; |
114 | ||
7abb690a DV |
115 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
116 | i915_terminally_wedged(error)) | |
1f83fee0 | 117 | if (EXIT_COND) |
30dbf0c0 CW |
118 | return 0; |
119 | ||
0a6759c6 DV |
120 | /* |
121 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
122 | * userspace. If it takes that long something really bad is going on and | |
123 | * we should simply try to bail out and fail as gracefully as possible. | |
124 | */ | |
1f83fee0 DV |
125 | ret = wait_event_interruptible_timeout(error->reset_queue, |
126 | EXIT_COND, | |
127 | 10*HZ); | |
0a6759c6 DV |
128 | if (ret == 0) { |
129 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
130 | return -EIO; | |
131 | } else if (ret < 0) { | |
30dbf0c0 | 132 | return ret; |
0a6759c6 | 133 | } |
1f83fee0 | 134 | #undef EXIT_COND |
30dbf0c0 | 135 | |
21dd3734 | 136 | return 0; |
30dbf0c0 CW |
137 | } |
138 | ||
54cf91dc | 139 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 140 | { |
33196ded | 141 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
142 | int ret; |
143 | ||
33196ded | 144 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
145 | if (ret) |
146 | return ret; | |
147 | ||
148 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
149 | if (ret) | |
150 | return ret; | |
151 | ||
23bc5982 | 152 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
153 | return 0; |
154 | } | |
30dbf0c0 | 155 | |
5a125c3c EA |
156 | int |
157 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 158 | struct drm_file *file) |
5a125c3c | 159 | { |
73aa808f | 160 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 161 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
162 | struct drm_i915_gem_object *obj; |
163 | size_t pinned; | |
5a125c3c | 164 | |
6299f992 | 165 | pinned = 0; |
73aa808f | 166 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 167 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 168 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 169 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 170 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 171 | |
853ba5d2 | 172 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 173 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 174 | |
5a125c3c EA |
175 | return 0; |
176 | } | |
177 | ||
6a2c4232 CW |
178 | static int |
179 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 180 | { |
6a2c4232 CW |
181 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
182 | char *vaddr = obj->phys_handle->vaddr; | |
183 | struct sg_table *st; | |
184 | struct scatterlist *sg; | |
185 | int i; | |
00731155 | 186 | |
6a2c4232 CW |
187 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
188 | return -EINVAL; | |
189 | ||
190 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
191 | struct page *page; | |
192 | char *src; | |
193 | ||
194 | page = shmem_read_mapping_page(mapping, i); | |
195 | if (IS_ERR(page)) | |
196 | return PTR_ERR(page); | |
197 | ||
198 | src = kmap_atomic(page); | |
199 | memcpy(vaddr, src, PAGE_SIZE); | |
200 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
201 | kunmap_atomic(src); | |
202 | ||
203 | page_cache_release(page); | |
204 | vaddr += PAGE_SIZE; | |
205 | } | |
206 | ||
207 | i915_gem_chipset_flush(obj->base.dev); | |
208 | ||
209 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
210 | if (st == NULL) | |
211 | return -ENOMEM; | |
212 | ||
213 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
214 | kfree(st); | |
215 | return -ENOMEM; | |
216 | } | |
217 | ||
218 | sg = st->sgl; | |
219 | sg->offset = 0; | |
220 | sg->length = obj->base.size; | |
00731155 | 221 | |
6a2c4232 CW |
222 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
223 | sg_dma_len(sg) = obj->base.size; | |
224 | ||
225 | obj->pages = st; | |
226 | obj->has_dma_mapping = true; | |
227 | return 0; | |
228 | } | |
229 | ||
230 | static void | |
231 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
232 | { | |
233 | int ret; | |
234 | ||
235 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 236 | |
6a2c4232 CW |
237 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
238 | if (ret) { | |
239 | /* In the event of a disaster, abandon all caches and | |
240 | * hope for the best. | |
241 | */ | |
242 | WARN_ON(ret != -EIO); | |
243 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
244 | } | |
245 | ||
246 | if (obj->madv == I915_MADV_DONTNEED) | |
247 | obj->dirty = 0; | |
248 | ||
249 | if (obj->dirty) { | |
00731155 | 250 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 251 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
252 | int i; |
253 | ||
254 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
255 | struct page *page; |
256 | char *dst; | |
257 | ||
258 | page = shmem_read_mapping_page(mapping, i); | |
259 | if (IS_ERR(page)) | |
260 | continue; | |
261 | ||
262 | dst = kmap_atomic(page); | |
263 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
264 | memcpy(dst, vaddr, PAGE_SIZE); | |
265 | kunmap_atomic(dst); | |
266 | ||
267 | set_page_dirty(page); | |
268 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 269 | mark_page_accessed(page); |
6a2c4232 | 270 | page_cache_release(page); |
00731155 CW |
271 | vaddr += PAGE_SIZE; |
272 | } | |
6a2c4232 | 273 | obj->dirty = 0; |
00731155 CW |
274 | } |
275 | ||
6a2c4232 CW |
276 | sg_free_table(obj->pages); |
277 | kfree(obj->pages); | |
278 | ||
279 | obj->has_dma_mapping = false; | |
280 | } | |
281 | ||
282 | static void | |
283 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
284 | { | |
285 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
286 | } | |
287 | ||
288 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
289 | .get_pages = i915_gem_object_get_pages_phys, | |
290 | .put_pages = i915_gem_object_put_pages_phys, | |
291 | .release = i915_gem_object_release_phys, | |
292 | }; | |
293 | ||
294 | static int | |
295 | drop_pages(struct drm_i915_gem_object *obj) | |
296 | { | |
297 | struct i915_vma *vma, *next; | |
298 | int ret; | |
299 | ||
300 | drm_gem_object_reference(&obj->base); | |
301 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) | |
302 | if (i915_vma_unbind(vma)) | |
303 | break; | |
304 | ||
305 | ret = i915_gem_object_put_pages(obj); | |
306 | drm_gem_object_unreference(&obj->base); | |
307 | ||
308 | return ret; | |
00731155 CW |
309 | } |
310 | ||
311 | int | |
312 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
313 | int align) | |
314 | { | |
315 | drm_dma_handle_t *phys; | |
6a2c4232 | 316 | int ret; |
00731155 CW |
317 | |
318 | if (obj->phys_handle) { | |
319 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
320 | return -EBUSY; | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | if (obj->madv != I915_MADV_WILLNEED) | |
326 | return -EFAULT; | |
327 | ||
328 | if (obj->base.filp == NULL) | |
329 | return -EINVAL; | |
330 | ||
6a2c4232 CW |
331 | ret = drop_pages(obj); |
332 | if (ret) | |
333 | return ret; | |
334 | ||
00731155 CW |
335 | /* create a new object */ |
336 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
337 | if (!phys) | |
338 | return -ENOMEM; | |
339 | ||
00731155 | 340 | obj->phys_handle = phys; |
6a2c4232 CW |
341 | obj->ops = &i915_gem_phys_ops; |
342 | ||
343 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
344 | } |
345 | ||
346 | static int | |
347 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
348 | struct drm_i915_gem_pwrite *args, | |
349 | struct drm_file *file_priv) | |
350 | { | |
351 | struct drm_device *dev = obj->base.dev; | |
352 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
353 | char __user *user_data = to_user_ptr(args->data_ptr); | |
6a2c4232 CW |
354 | int ret; |
355 | ||
356 | /* We manually control the domain here and pretend that it | |
357 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
358 | */ | |
359 | ret = i915_gem_object_wait_rendering(obj, false); | |
360 | if (ret) | |
361 | return ret; | |
00731155 CW |
362 | |
363 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
364 | unsigned long unwritten; | |
365 | ||
366 | /* The physical object once assigned is fixed for the lifetime | |
367 | * of the obj, so we can safely drop the lock and continue | |
368 | * to access vaddr. | |
369 | */ | |
370 | mutex_unlock(&dev->struct_mutex); | |
371 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
372 | mutex_lock(&dev->struct_mutex); | |
373 | if (unwritten) | |
374 | return -EFAULT; | |
375 | } | |
376 | ||
6a2c4232 | 377 | drm_clflush_virt_range(vaddr, args->size); |
00731155 CW |
378 | i915_gem_chipset_flush(dev); |
379 | return 0; | |
380 | } | |
381 | ||
42dcedd4 CW |
382 | void *i915_gem_object_alloc(struct drm_device *dev) |
383 | { | |
384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 385 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
386 | } |
387 | ||
388 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
389 | { | |
390 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
391 | kmem_cache_free(dev_priv->slab, obj); | |
392 | } | |
393 | ||
ff72145b DA |
394 | static int |
395 | i915_gem_create(struct drm_file *file, | |
396 | struct drm_device *dev, | |
397 | uint64_t size, | |
398 | uint32_t *handle_p) | |
673a394b | 399 | { |
05394f39 | 400 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
401 | int ret; |
402 | u32 handle; | |
673a394b | 403 | |
ff72145b | 404 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
405 | if (size == 0) |
406 | return -EINVAL; | |
673a394b EA |
407 | |
408 | /* Allocate the new object */ | |
ff72145b | 409 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
410 | if (obj == NULL) |
411 | return -ENOMEM; | |
412 | ||
05394f39 | 413 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 414 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
415 | drm_gem_object_unreference_unlocked(&obj->base); |
416 | if (ret) | |
417 | return ret; | |
202f2fef | 418 | |
ff72145b | 419 | *handle_p = handle; |
673a394b EA |
420 | return 0; |
421 | } | |
422 | ||
ff72145b DA |
423 | int |
424 | i915_gem_dumb_create(struct drm_file *file, | |
425 | struct drm_device *dev, | |
426 | struct drm_mode_create_dumb *args) | |
427 | { | |
428 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 429 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
430 | args->size = args->pitch * args->height; |
431 | return i915_gem_create(file, dev, | |
da6b51d0 | 432 | args->size, &args->handle); |
ff72145b DA |
433 | } |
434 | ||
ff72145b DA |
435 | /** |
436 | * Creates a new mm object and returns a handle to it. | |
437 | */ | |
438 | int | |
439 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
440 | struct drm_file *file) | |
441 | { | |
442 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 443 | |
ff72145b | 444 | return i915_gem_create(file, dev, |
da6b51d0 | 445 | args->size, &args->handle); |
ff72145b DA |
446 | } |
447 | ||
8461d226 DV |
448 | static inline int |
449 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
450 | const char *gpu_vaddr, int gpu_offset, | |
451 | int length) | |
452 | { | |
453 | int ret, cpu_offset = 0; | |
454 | ||
455 | while (length > 0) { | |
456 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
457 | int this_length = min(cacheline_end - gpu_offset, length); | |
458 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
459 | ||
460 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
461 | gpu_vaddr + swizzled_gpu_offset, | |
462 | this_length); | |
463 | if (ret) | |
464 | return ret + length; | |
465 | ||
466 | cpu_offset += this_length; | |
467 | gpu_offset += this_length; | |
468 | length -= this_length; | |
469 | } | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
8c59967c | 474 | static inline int |
4f0c7cfb BW |
475 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
476 | const char __user *cpu_vaddr, | |
8c59967c DV |
477 | int length) |
478 | { | |
479 | int ret, cpu_offset = 0; | |
480 | ||
481 | while (length > 0) { | |
482 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
483 | int this_length = min(cacheline_end - gpu_offset, length); | |
484 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
485 | ||
486 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
487 | cpu_vaddr + cpu_offset, | |
488 | this_length); | |
489 | if (ret) | |
490 | return ret + length; | |
491 | ||
492 | cpu_offset += this_length; | |
493 | gpu_offset += this_length; | |
494 | length -= this_length; | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
4c914c0c BV |
500 | /* |
501 | * Pins the specified object's pages and synchronizes the object with | |
502 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
503 | * flush the object from the CPU cache. | |
504 | */ | |
505 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
506 | int *needs_clflush) | |
507 | { | |
508 | int ret; | |
509 | ||
510 | *needs_clflush = 0; | |
511 | ||
512 | if (!obj->base.filp) | |
513 | return -EINVAL; | |
514 | ||
515 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
516 | /* If we're not in the cpu read domain, set ourself into the gtt | |
517 | * read domain and manually flush cachelines (if required). This | |
518 | * optimizes for the case when the gpu will dirty the data | |
519 | * anyway again before the next pread happens. */ | |
520 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
521 | obj->cache_level); | |
522 | ret = i915_gem_object_wait_rendering(obj, true); | |
523 | if (ret) | |
524 | return ret; | |
c8725f3d CW |
525 | |
526 | i915_gem_object_retire(obj); | |
4c914c0c BV |
527 | } |
528 | ||
529 | ret = i915_gem_object_get_pages(obj); | |
530 | if (ret) | |
531 | return ret; | |
532 | ||
533 | i915_gem_object_pin_pages(obj); | |
534 | ||
535 | return ret; | |
536 | } | |
537 | ||
d174bd64 DV |
538 | /* Per-page copy function for the shmem pread fastpath. |
539 | * Flushes invalid cachelines before reading the target if | |
540 | * needs_clflush is set. */ | |
eb01459f | 541 | static int |
d174bd64 DV |
542 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
543 | char __user *user_data, | |
544 | bool page_do_bit17_swizzling, bool needs_clflush) | |
545 | { | |
546 | char *vaddr; | |
547 | int ret; | |
548 | ||
e7e58eb5 | 549 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
550 | return -EINVAL; |
551 | ||
552 | vaddr = kmap_atomic(page); | |
553 | if (needs_clflush) | |
554 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
555 | page_length); | |
556 | ret = __copy_to_user_inatomic(user_data, | |
557 | vaddr + shmem_page_offset, | |
558 | page_length); | |
559 | kunmap_atomic(vaddr); | |
560 | ||
f60d7f0c | 561 | return ret ? -EFAULT : 0; |
d174bd64 DV |
562 | } |
563 | ||
23c18c71 DV |
564 | static void |
565 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
566 | bool swizzled) | |
567 | { | |
e7e58eb5 | 568 | if (unlikely(swizzled)) { |
23c18c71 DV |
569 | unsigned long start = (unsigned long) addr; |
570 | unsigned long end = (unsigned long) addr + length; | |
571 | ||
572 | /* For swizzling simply ensure that we always flush both | |
573 | * channels. Lame, but simple and it works. Swizzled | |
574 | * pwrite/pread is far from a hotpath - current userspace | |
575 | * doesn't use it at all. */ | |
576 | start = round_down(start, 128); | |
577 | end = round_up(end, 128); | |
578 | ||
579 | drm_clflush_virt_range((void *)start, end - start); | |
580 | } else { | |
581 | drm_clflush_virt_range(addr, length); | |
582 | } | |
583 | ||
584 | } | |
585 | ||
d174bd64 DV |
586 | /* Only difference to the fast-path function is that this can handle bit17 |
587 | * and uses non-atomic copy and kmap functions. */ | |
588 | static int | |
589 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
590 | char __user *user_data, | |
591 | bool page_do_bit17_swizzling, bool needs_clflush) | |
592 | { | |
593 | char *vaddr; | |
594 | int ret; | |
595 | ||
596 | vaddr = kmap(page); | |
597 | if (needs_clflush) | |
23c18c71 DV |
598 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
599 | page_length, | |
600 | page_do_bit17_swizzling); | |
d174bd64 DV |
601 | |
602 | if (page_do_bit17_swizzling) | |
603 | ret = __copy_to_user_swizzled(user_data, | |
604 | vaddr, shmem_page_offset, | |
605 | page_length); | |
606 | else | |
607 | ret = __copy_to_user(user_data, | |
608 | vaddr + shmem_page_offset, | |
609 | page_length); | |
610 | kunmap(page); | |
611 | ||
f60d7f0c | 612 | return ret ? - EFAULT : 0; |
d174bd64 DV |
613 | } |
614 | ||
eb01459f | 615 | static int |
dbf7bff0 DV |
616 | i915_gem_shmem_pread(struct drm_device *dev, |
617 | struct drm_i915_gem_object *obj, | |
618 | struct drm_i915_gem_pread *args, | |
619 | struct drm_file *file) | |
eb01459f | 620 | { |
8461d226 | 621 | char __user *user_data; |
eb01459f | 622 | ssize_t remain; |
8461d226 | 623 | loff_t offset; |
eb2c0c81 | 624 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 625 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 626 | int prefaulted = 0; |
8489731c | 627 | int needs_clflush = 0; |
67d5a50c | 628 | struct sg_page_iter sg_iter; |
eb01459f | 629 | |
2bb4629a | 630 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
631 | remain = args->size; |
632 | ||
8461d226 | 633 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 634 | |
4c914c0c | 635 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
636 | if (ret) |
637 | return ret; | |
638 | ||
8461d226 | 639 | offset = args->offset; |
eb01459f | 640 | |
67d5a50c ID |
641 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
642 | offset >> PAGE_SHIFT) { | |
2db76d7c | 643 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
644 | |
645 | if (remain <= 0) | |
646 | break; | |
647 | ||
eb01459f EA |
648 | /* Operation in this page |
649 | * | |
eb01459f | 650 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
651 | * page_length = bytes to copy for this page |
652 | */ | |
c8cbbb8b | 653 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
654 | page_length = remain; |
655 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
656 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 657 | |
8461d226 DV |
658 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
659 | (page_to_phys(page) & (1 << 17)) != 0; | |
660 | ||
d174bd64 DV |
661 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
662 | user_data, page_do_bit17_swizzling, | |
663 | needs_clflush); | |
664 | if (ret == 0) | |
665 | goto next_page; | |
dbf7bff0 | 666 | |
dbf7bff0 DV |
667 | mutex_unlock(&dev->struct_mutex); |
668 | ||
d330a953 | 669 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 670 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
671 | /* Userspace is tricking us, but we've already clobbered |
672 | * its pages with the prefault and promised to write the | |
673 | * data up to the first fault. Hence ignore any errors | |
674 | * and just continue. */ | |
675 | (void)ret; | |
676 | prefaulted = 1; | |
677 | } | |
eb01459f | 678 | |
d174bd64 DV |
679 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
680 | user_data, page_do_bit17_swizzling, | |
681 | needs_clflush); | |
eb01459f | 682 | |
dbf7bff0 | 683 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 684 | |
f60d7f0c | 685 | if (ret) |
8461d226 | 686 | goto out; |
8461d226 | 687 | |
17793c9a | 688 | next_page: |
eb01459f | 689 | remain -= page_length; |
8461d226 | 690 | user_data += page_length; |
eb01459f EA |
691 | offset += page_length; |
692 | } | |
693 | ||
4f27b75d | 694 | out: |
f60d7f0c CW |
695 | i915_gem_object_unpin_pages(obj); |
696 | ||
eb01459f EA |
697 | return ret; |
698 | } | |
699 | ||
673a394b EA |
700 | /** |
701 | * Reads data from the object referenced by handle. | |
702 | * | |
703 | * On error, the contents of *data are undefined. | |
704 | */ | |
705 | int | |
706 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 707 | struct drm_file *file) |
673a394b EA |
708 | { |
709 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 710 | struct drm_i915_gem_object *obj; |
35b62a89 | 711 | int ret = 0; |
673a394b | 712 | |
51311d0a CW |
713 | if (args->size == 0) |
714 | return 0; | |
715 | ||
716 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 717 | to_user_ptr(args->data_ptr), |
51311d0a CW |
718 | args->size)) |
719 | return -EFAULT; | |
720 | ||
4f27b75d | 721 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 722 | if (ret) |
4f27b75d | 723 | return ret; |
673a394b | 724 | |
05394f39 | 725 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 726 | if (&obj->base == NULL) { |
1d7cfea1 CW |
727 | ret = -ENOENT; |
728 | goto unlock; | |
4f27b75d | 729 | } |
673a394b | 730 | |
7dcd2499 | 731 | /* Bounds check source. */ |
05394f39 CW |
732 | if (args->offset > obj->base.size || |
733 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 734 | ret = -EINVAL; |
35b62a89 | 735 | goto out; |
ce9d419d CW |
736 | } |
737 | ||
1286ff73 DV |
738 | /* prime objects have no backing filp to GEM pread/pwrite |
739 | * pages from. | |
740 | */ | |
741 | if (!obj->base.filp) { | |
742 | ret = -EINVAL; | |
743 | goto out; | |
744 | } | |
745 | ||
db53a302 CW |
746 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
747 | ||
dbf7bff0 | 748 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 749 | |
35b62a89 | 750 | out: |
05394f39 | 751 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 752 | unlock: |
4f27b75d | 753 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 754 | return ret; |
673a394b EA |
755 | } |
756 | ||
0839ccb8 KP |
757 | /* This is the fast write path which cannot handle |
758 | * page faults in the source data | |
9b7530cc | 759 | */ |
0839ccb8 KP |
760 | |
761 | static inline int | |
762 | fast_user_write(struct io_mapping *mapping, | |
763 | loff_t page_base, int page_offset, | |
764 | char __user *user_data, | |
765 | int length) | |
9b7530cc | 766 | { |
4f0c7cfb BW |
767 | void __iomem *vaddr_atomic; |
768 | void *vaddr; | |
0839ccb8 | 769 | unsigned long unwritten; |
9b7530cc | 770 | |
3e4d3af5 | 771 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
772 | /* We can use the cpu mem copy function because this is X86. */ |
773 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
774 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 775 | user_data, length); |
3e4d3af5 | 776 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 777 | return unwritten; |
0839ccb8 KP |
778 | } |
779 | ||
3de09aa3 EA |
780 | /** |
781 | * This is the fast pwrite path, where we copy the data directly from the | |
782 | * user into the GTT, uncached. | |
783 | */ | |
673a394b | 784 | static int |
05394f39 CW |
785 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
786 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 787 | struct drm_i915_gem_pwrite *args, |
05394f39 | 788 | struct drm_file *file) |
673a394b | 789 | { |
3e31c6c0 | 790 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 791 | ssize_t remain; |
0839ccb8 | 792 | loff_t offset, page_base; |
673a394b | 793 | char __user *user_data; |
935aaa69 DV |
794 | int page_offset, page_length, ret; |
795 | ||
1ec9e26d | 796 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
797 | if (ret) |
798 | goto out; | |
799 | ||
800 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
801 | if (ret) | |
802 | goto out_unpin; | |
803 | ||
804 | ret = i915_gem_object_put_fence(obj); | |
805 | if (ret) | |
806 | goto out_unpin; | |
673a394b | 807 | |
2bb4629a | 808 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 809 | remain = args->size; |
673a394b | 810 | |
f343c5f6 | 811 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
812 | |
813 | while (remain > 0) { | |
814 | /* Operation in this page | |
815 | * | |
0839ccb8 KP |
816 | * page_base = page offset within aperture |
817 | * page_offset = offset within page | |
818 | * page_length = bytes to copy for this page | |
673a394b | 819 | */ |
c8cbbb8b CW |
820 | page_base = offset & PAGE_MASK; |
821 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
822 | page_length = remain; |
823 | if ((page_offset + remain) > PAGE_SIZE) | |
824 | page_length = PAGE_SIZE - page_offset; | |
825 | ||
0839ccb8 | 826 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
827 | * source page isn't available. Return the error and we'll |
828 | * retry in the slow path. | |
0839ccb8 | 829 | */ |
5d4545ae | 830 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
831 | page_offset, user_data, page_length)) { |
832 | ret = -EFAULT; | |
833 | goto out_unpin; | |
834 | } | |
673a394b | 835 | |
0839ccb8 KP |
836 | remain -= page_length; |
837 | user_data += page_length; | |
838 | offset += page_length; | |
673a394b | 839 | } |
673a394b | 840 | |
935aaa69 | 841 | out_unpin: |
d7f46fc4 | 842 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 843 | out: |
3de09aa3 | 844 | return ret; |
673a394b EA |
845 | } |
846 | ||
d174bd64 DV |
847 | /* Per-page copy function for the shmem pwrite fastpath. |
848 | * Flushes invalid cachelines before writing to the target if | |
849 | * needs_clflush_before is set and flushes out any written cachelines after | |
850 | * writing if needs_clflush is set. */ | |
3043c60c | 851 | static int |
d174bd64 DV |
852 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
853 | char __user *user_data, | |
854 | bool page_do_bit17_swizzling, | |
855 | bool needs_clflush_before, | |
856 | bool needs_clflush_after) | |
673a394b | 857 | { |
d174bd64 | 858 | char *vaddr; |
673a394b | 859 | int ret; |
3de09aa3 | 860 | |
e7e58eb5 | 861 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 862 | return -EINVAL; |
3de09aa3 | 863 | |
d174bd64 DV |
864 | vaddr = kmap_atomic(page); |
865 | if (needs_clflush_before) | |
866 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
867 | page_length); | |
c2831a94 CW |
868 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
869 | user_data, page_length); | |
d174bd64 DV |
870 | if (needs_clflush_after) |
871 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
872 | page_length); | |
873 | kunmap_atomic(vaddr); | |
3de09aa3 | 874 | |
755d2218 | 875 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
876 | } |
877 | ||
d174bd64 DV |
878 | /* Only difference to the fast-path function is that this can handle bit17 |
879 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 880 | static int |
d174bd64 DV |
881 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
882 | char __user *user_data, | |
883 | bool page_do_bit17_swizzling, | |
884 | bool needs_clflush_before, | |
885 | bool needs_clflush_after) | |
673a394b | 886 | { |
d174bd64 DV |
887 | char *vaddr; |
888 | int ret; | |
e5281ccd | 889 | |
d174bd64 | 890 | vaddr = kmap(page); |
e7e58eb5 | 891 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
892 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
893 | page_length, | |
894 | page_do_bit17_swizzling); | |
d174bd64 DV |
895 | if (page_do_bit17_swizzling) |
896 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
897 | user_data, |
898 | page_length); | |
d174bd64 DV |
899 | else |
900 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
901 | user_data, | |
902 | page_length); | |
903 | if (needs_clflush_after) | |
23c18c71 DV |
904 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
905 | page_length, | |
906 | page_do_bit17_swizzling); | |
d174bd64 | 907 | kunmap(page); |
40123c1f | 908 | |
755d2218 | 909 | return ret ? -EFAULT : 0; |
40123c1f EA |
910 | } |
911 | ||
40123c1f | 912 | static int |
e244a443 DV |
913 | i915_gem_shmem_pwrite(struct drm_device *dev, |
914 | struct drm_i915_gem_object *obj, | |
915 | struct drm_i915_gem_pwrite *args, | |
916 | struct drm_file *file) | |
40123c1f | 917 | { |
40123c1f | 918 | ssize_t remain; |
8c59967c DV |
919 | loff_t offset; |
920 | char __user *user_data; | |
eb2c0c81 | 921 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 922 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 923 | int hit_slowpath = 0; |
58642885 DV |
924 | int needs_clflush_after = 0; |
925 | int needs_clflush_before = 0; | |
67d5a50c | 926 | struct sg_page_iter sg_iter; |
40123c1f | 927 | |
2bb4629a | 928 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
929 | remain = args->size; |
930 | ||
8c59967c | 931 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 932 | |
58642885 DV |
933 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
934 | /* If we're not in the cpu write domain, set ourself into the gtt | |
935 | * write domain and manually flush cachelines (if required). This | |
936 | * optimizes for the case when the gpu will use the data | |
937 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 938 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
939 | ret = i915_gem_object_wait_rendering(obj, false); |
940 | if (ret) | |
941 | return ret; | |
c8725f3d CW |
942 | |
943 | i915_gem_object_retire(obj); | |
58642885 | 944 | } |
c76ce038 CW |
945 | /* Same trick applies to invalidate partially written cachelines read |
946 | * before writing. */ | |
947 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
948 | needs_clflush_before = | |
949 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 950 | |
755d2218 CW |
951 | ret = i915_gem_object_get_pages(obj); |
952 | if (ret) | |
953 | return ret; | |
954 | ||
955 | i915_gem_object_pin_pages(obj); | |
956 | ||
673a394b | 957 | offset = args->offset; |
05394f39 | 958 | obj->dirty = 1; |
673a394b | 959 | |
67d5a50c ID |
960 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
961 | offset >> PAGE_SHIFT) { | |
2db76d7c | 962 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 963 | int partial_cacheline_write; |
e5281ccd | 964 | |
9da3da66 CW |
965 | if (remain <= 0) |
966 | break; | |
967 | ||
40123c1f EA |
968 | /* Operation in this page |
969 | * | |
40123c1f | 970 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
971 | * page_length = bytes to copy for this page |
972 | */ | |
c8cbbb8b | 973 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
974 | |
975 | page_length = remain; | |
976 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
977 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 978 | |
58642885 DV |
979 | /* If we don't overwrite a cacheline completely we need to be |
980 | * careful to have up-to-date data by first clflushing. Don't | |
981 | * overcomplicate things and flush the entire patch. */ | |
982 | partial_cacheline_write = needs_clflush_before && | |
983 | ((shmem_page_offset | page_length) | |
984 | & (boot_cpu_data.x86_clflush_size - 1)); | |
985 | ||
8c59967c DV |
986 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
987 | (page_to_phys(page) & (1 << 17)) != 0; | |
988 | ||
d174bd64 DV |
989 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
990 | user_data, page_do_bit17_swizzling, | |
991 | partial_cacheline_write, | |
992 | needs_clflush_after); | |
993 | if (ret == 0) | |
994 | goto next_page; | |
e244a443 DV |
995 | |
996 | hit_slowpath = 1; | |
e244a443 | 997 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
998 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
999 | user_data, page_do_bit17_swizzling, | |
1000 | partial_cacheline_write, | |
1001 | needs_clflush_after); | |
40123c1f | 1002 | |
e244a443 | 1003 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1004 | |
755d2218 | 1005 | if (ret) |
8c59967c | 1006 | goto out; |
8c59967c | 1007 | |
17793c9a | 1008 | next_page: |
40123c1f | 1009 | remain -= page_length; |
8c59967c | 1010 | user_data += page_length; |
40123c1f | 1011 | offset += page_length; |
673a394b EA |
1012 | } |
1013 | ||
fbd5a26d | 1014 | out: |
755d2218 CW |
1015 | i915_gem_object_unpin_pages(obj); |
1016 | ||
e244a443 | 1017 | if (hit_slowpath) { |
8dcf015e DV |
1018 | /* |
1019 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1020 | * cachelines in-line while writing and the object moved | |
1021 | * out of the cpu write domain while we've dropped the lock. | |
1022 | */ | |
1023 | if (!needs_clflush_after && | |
1024 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
1025 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
1026 | i915_gem_chipset_flush(dev); | |
e244a443 | 1027 | } |
8c59967c | 1028 | } |
673a394b | 1029 | |
58642885 | 1030 | if (needs_clflush_after) |
e76e9aeb | 1031 | i915_gem_chipset_flush(dev); |
58642885 | 1032 | |
40123c1f | 1033 | return ret; |
673a394b EA |
1034 | } |
1035 | ||
1036 | /** | |
1037 | * Writes data to the object referenced by handle. | |
1038 | * | |
1039 | * On error, the contents of the buffer that were to be modified are undefined. | |
1040 | */ | |
1041 | int | |
1042 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1043 | struct drm_file *file) |
673a394b | 1044 | { |
5d77d9c5 | 1045 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1046 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1047 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1048 | int ret; |
1049 | ||
1050 | if (args->size == 0) | |
1051 | return 0; | |
1052 | ||
1053 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1054 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1055 | args->size)) |
1056 | return -EFAULT; | |
1057 | ||
d330a953 | 1058 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1059 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1060 | args->size); | |
1061 | if (ret) | |
1062 | return -EFAULT; | |
1063 | } | |
673a394b | 1064 | |
5d77d9c5 ID |
1065 | intel_runtime_pm_get(dev_priv); |
1066 | ||
fbd5a26d | 1067 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1068 | if (ret) |
5d77d9c5 | 1069 | goto put_rpm; |
1d7cfea1 | 1070 | |
05394f39 | 1071 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1072 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1073 | ret = -ENOENT; |
1074 | goto unlock; | |
fbd5a26d | 1075 | } |
673a394b | 1076 | |
7dcd2499 | 1077 | /* Bounds check destination. */ |
05394f39 CW |
1078 | if (args->offset > obj->base.size || |
1079 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1080 | ret = -EINVAL; |
35b62a89 | 1081 | goto out; |
ce9d419d CW |
1082 | } |
1083 | ||
1286ff73 DV |
1084 | /* prime objects have no backing filp to GEM pread/pwrite |
1085 | * pages from. | |
1086 | */ | |
1087 | if (!obj->base.filp) { | |
1088 | ret = -EINVAL; | |
1089 | goto out; | |
1090 | } | |
1091 | ||
db53a302 CW |
1092 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1093 | ||
935aaa69 | 1094 | ret = -EFAULT; |
673a394b EA |
1095 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1096 | * it would end up going through the fenced access, and we'll get | |
1097 | * different detiling behavior between reading and writing. | |
1098 | * pread/pwrite currently are reading and writing from the CPU | |
1099 | * perspective, requiring manual detiling by the client. | |
1100 | */ | |
2c22569b CW |
1101 | if (obj->tiling_mode == I915_TILING_NONE && |
1102 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1103 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1104 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1105 | /* Note that the gtt paths might fail with non-page-backed user |
1106 | * pointers (e.g. gtt mappings when moving data between | |
1107 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1108 | } |
673a394b | 1109 | |
6a2c4232 CW |
1110 | if (ret == -EFAULT || ret == -ENOSPC) { |
1111 | if (obj->phys_handle) | |
1112 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1113 | else | |
1114 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1115 | } | |
5c0480f2 | 1116 | |
35b62a89 | 1117 | out: |
05394f39 | 1118 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1119 | unlock: |
fbd5a26d | 1120 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1121 | put_rpm: |
1122 | intel_runtime_pm_put(dev_priv); | |
1123 | ||
673a394b EA |
1124 | return ret; |
1125 | } | |
1126 | ||
b361237b | 1127 | int |
33196ded | 1128 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1129 | bool interruptible) |
1130 | { | |
1f83fee0 | 1131 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1132 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1133 | * -EIO unconditionally for these. */ | |
1134 | if (!interruptible) | |
1135 | return -EIO; | |
1136 | ||
1f83fee0 DV |
1137 | /* Recovery complete, but the reset failed ... */ |
1138 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1139 | return -EIO; |
1140 | ||
6689c167 MA |
1141 | /* |
1142 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1143 | * to work properly to reinit the hw state while the gpu is | |
1144 | * still marked as reset-in-progress. Handle this with a flag. | |
1145 | */ | |
1146 | if (!error->reload_in_reset) | |
1147 | return -EAGAIN; | |
b361237b CW |
1148 | } |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | /* | |
b6660d59 | 1154 | * Compare arbitrary request against outstanding lazy request. Emit on match. |
b361237b | 1155 | */ |
84c33a64 | 1156 | int |
b6660d59 | 1157 | i915_gem_check_olr(struct drm_i915_gem_request *req) |
b361237b CW |
1158 | { |
1159 | int ret; | |
1160 | ||
b6660d59 | 1161 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
b361237b CW |
1162 | |
1163 | ret = 0; | |
b6660d59 | 1164 | if (req == req->ring->outstanding_lazy_request) |
9400ae5c | 1165 | ret = i915_add_request(req->ring); |
b361237b CW |
1166 | |
1167 | return ret; | |
1168 | } | |
1169 | ||
094f9a54 CW |
1170 | static void fake_irq(unsigned long data) |
1171 | { | |
1172 | wake_up_process((struct task_struct *)data); | |
1173 | } | |
1174 | ||
1175 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1176 | struct intel_engine_cs *ring) |
094f9a54 CW |
1177 | { |
1178 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1179 | } | |
1180 | ||
b29c19b6 CW |
1181 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1182 | { | |
1183 | if (file_priv == NULL) | |
1184 | return true; | |
1185 | ||
1186 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1187 | } | |
1188 | ||
b361237b | 1189 | /** |
9c654818 JH |
1190 | * __i915_wait_request - wait until execution of request has finished |
1191 | * @req: duh! | |
1192 | * @reset_counter: reset sequence associated with the given request | |
b361237b CW |
1193 | * @interruptible: do an interruptible wait (normally yes) |
1194 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1195 | * | |
f69061be DV |
1196 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1197 | * values have been read by the caller in an smp safe manner. Where read-side | |
1198 | * locks are involved, it is sufficient to read the reset_counter before | |
1199 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1200 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1201 | * inserted. | |
1202 | * | |
9c654818 | 1203 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1204 | * errno with remaining time filled in timeout argument. |
1205 | */ | |
9c654818 | 1206 | int __i915_wait_request(struct drm_i915_gem_request *req, |
f69061be | 1207 | unsigned reset_counter, |
b29c19b6 | 1208 | bool interruptible, |
5ed0bdf2 | 1209 | s64 *timeout, |
b29c19b6 | 1210 | struct drm_i915_file_private *file_priv) |
b361237b | 1211 | { |
9c654818 | 1212 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
3d13ef2e | 1213 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1214 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1215 | const bool irq_test_in_progress = |
1216 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 | 1217 | DEFINE_WAIT(wait); |
47e9766d | 1218 | unsigned long timeout_expire; |
5ed0bdf2 | 1219 | s64 before, now; |
b361237b CW |
1220 | int ret; |
1221 | ||
9df7575f | 1222 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1223 | |
1b5a433a | 1224 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1225 | return 0; |
1226 | ||
7bd0e226 DV |
1227 | timeout_expire = timeout ? |
1228 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; | |
b361237b | 1229 | |
ec5cc0f9 | 1230 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1231 | gen6_rps_boost(dev_priv); |
1232 | if (file_priv) | |
1233 | mod_delayed_work(dev_priv->wq, | |
1234 | &file_priv->mm.idle_work, | |
1235 | msecs_to_jiffies(100)); | |
1236 | } | |
1237 | ||
168c3f21 | 1238 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1239 | return -ENODEV; |
1240 | ||
094f9a54 | 1241 | /* Record current time in case interrupted by signal, or wedged */ |
74328ee5 | 1242 | trace_i915_gem_request_wait_begin(req); |
5ed0bdf2 | 1243 | before = ktime_get_raw_ns(); |
094f9a54 CW |
1244 | for (;;) { |
1245 | struct timer_list timer; | |
b361237b | 1246 | |
094f9a54 CW |
1247 | prepare_to_wait(&ring->irq_queue, &wait, |
1248 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1249 | |
f69061be DV |
1250 | /* We need to check whether any gpu reset happened in between |
1251 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1252 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1253 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1254 | * is truely gone. */ | |
1255 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1256 | if (ret == 0) | |
1257 | ret = -EAGAIN; | |
1258 | break; | |
1259 | } | |
f69061be | 1260 | |
1b5a433a | 1261 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1262 | ret = 0; |
1263 | break; | |
1264 | } | |
b361237b | 1265 | |
094f9a54 CW |
1266 | if (interruptible && signal_pending(current)) { |
1267 | ret = -ERESTARTSYS; | |
1268 | break; | |
1269 | } | |
1270 | ||
47e9766d | 1271 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1272 | ret = -ETIME; |
1273 | break; | |
1274 | } | |
1275 | ||
1276 | timer.function = NULL; | |
1277 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1278 | unsigned long expire; |
1279 | ||
094f9a54 | 1280 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1281 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1282 | mod_timer(&timer, expire); |
1283 | } | |
1284 | ||
5035c275 | 1285 | io_schedule(); |
094f9a54 | 1286 | |
094f9a54 CW |
1287 | if (timer.function) { |
1288 | del_singleshot_timer_sync(&timer); | |
1289 | destroy_timer_on_stack(&timer); | |
1290 | } | |
1291 | } | |
5ed0bdf2 | 1292 | now = ktime_get_raw_ns(); |
74328ee5 | 1293 | trace_i915_gem_request_wait_end(req); |
b361237b | 1294 | |
168c3f21 MK |
1295 | if (!irq_test_in_progress) |
1296 | ring->irq_put(ring); | |
094f9a54 CW |
1297 | |
1298 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1299 | |
1300 | if (timeout) { | |
5ed0bdf2 TG |
1301 | s64 tres = *timeout - (now - before); |
1302 | ||
1303 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1304 | |
1305 | /* | |
1306 | * Apparently ktime isn't accurate enough and occasionally has a | |
1307 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1308 | * things up to make the test happy. We allow up to 1 jiffy. | |
1309 | * | |
1310 | * This is a regrssion from the timespec->ktime conversion. | |
1311 | */ | |
1312 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1313 | *timeout = 0; | |
b361237b CW |
1314 | } |
1315 | ||
094f9a54 | 1316 | return ret; |
b361237b CW |
1317 | } |
1318 | ||
1319 | /** | |
a4b3a571 | 1320 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1321 | * request and object lists appropriately for that event. |
1322 | */ | |
1323 | int | |
a4b3a571 | 1324 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1325 | { |
a4b3a571 DV |
1326 | struct drm_device *dev; |
1327 | struct drm_i915_private *dev_priv; | |
1328 | bool interruptible; | |
16e9a21f | 1329 | unsigned reset_counter; |
b361237b CW |
1330 | int ret; |
1331 | ||
a4b3a571 DV |
1332 | BUG_ON(req == NULL); |
1333 | ||
1334 | dev = req->ring->dev; | |
1335 | dev_priv = dev->dev_private; | |
1336 | interruptible = dev_priv->mm.interruptible; | |
1337 | ||
b361237b | 1338 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1339 | |
33196ded | 1340 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1341 | if (ret) |
1342 | return ret; | |
1343 | ||
a4b3a571 | 1344 | ret = i915_gem_check_olr(req); |
b361237b CW |
1345 | if (ret) |
1346 | return ret; | |
1347 | ||
16e9a21f | 1348 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
a4b3a571 | 1349 | i915_gem_request_reference(req); |
9c654818 JH |
1350 | ret = __i915_wait_request(req, reset_counter, |
1351 | interruptible, NULL, NULL); | |
a4b3a571 DV |
1352 | i915_gem_request_unreference(req); |
1353 | return ret; | |
b361237b CW |
1354 | } |
1355 | ||
d26e3af8 | 1356 | static int |
8e639549 | 1357 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) |
d26e3af8 | 1358 | { |
c8725f3d CW |
1359 | if (!obj->active) |
1360 | return 0; | |
d26e3af8 CW |
1361 | |
1362 | /* Manually manage the write flush as we may have not yet | |
1363 | * retired the buffer. | |
1364 | * | |
97b2a6a1 JH |
1365 | * Note that the last_write_req is always the earlier of |
1366 | * the two (read/write) requests, so if we haved successfully waited, | |
d26e3af8 CW |
1367 | * we know we have passed the last write. |
1368 | */ | |
97b2a6a1 | 1369 | i915_gem_request_assign(&obj->last_write_req, NULL); |
d26e3af8 CW |
1370 | |
1371 | return 0; | |
1372 | } | |
1373 | ||
b361237b CW |
1374 | /** |
1375 | * Ensures that all rendering to the object has completed and the object is | |
1376 | * safe to unbind from the GTT or access from the CPU. | |
1377 | */ | |
1378 | static __must_check int | |
1379 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1380 | bool readonly) | |
1381 | { | |
97b2a6a1 | 1382 | struct drm_i915_gem_request *req; |
b361237b CW |
1383 | int ret; |
1384 | ||
97b2a6a1 JH |
1385 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1386 | if (!req) | |
b361237b CW |
1387 | return 0; |
1388 | ||
a4b3a571 | 1389 | ret = i915_wait_request(req); |
b361237b CW |
1390 | if (ret) |
1391 | return ret; | |
1392 | ||
8e639549 | 1393 | return i915_gem_object_wait_rendering__tail(obj); |
b361237b CW |
1394 | } |
1395 | ||
3236f57a CW |
1396 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1397 | * as the object state may change during this call. | |
1398 | */ | |
1399 | static __must_check int | |
1400 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1401 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1402 | bool readonly) |
1403 | { | |
97b2a6a1 | 1404 | struct drm_i915_gem_request *req; |
3236f57a CW |
1405 | struct drm_device *dev = obj->base.dev; |
1406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f69061be | 1407 | unsigned reset_counter; |
3236f57a CW |
1408 | int ret; |
1409 | ||
1410 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1411 | BUG_ON(!dev_priv->mm.interruptible); | |
1412 | ||
97b2a6a1 JH |
1413 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1414 | if (!req) | |
3236f57a CW |
1415 | return 0; |
1416 | ||
33196ded | 1417 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1418 | if (ret) |
1419 | return ret; | |
1420 | ||
b6660d59 | 1421 | ret = i915_gem_check_olr(req); |
3236f57a CW |
1422 | if (ret) |
1423 | return ret; | |
1424 | ||
f69061be | 1425 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 1426 | i915_gem_request_reference(req); |
3236f57a | 1427 | mutex_unlock(&dev->struct_mutex); |
9c654818 | 1428 | ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv); |
3236f57a | 1429 | mutex_lock(&dev->struct_mutex); |
ff865885 | 1430 | i915_gem_request_unreference(req); |
d26e3af8 CW |
1431 | if (ret) |
1432 | return ret; | |
3236f57a | 1433 | |
8e639549 | 1434 | return i915_gem_object_wait_rendering__tail(obj); |
3236f57a CW |
1435 | } |
1436 | ||
673a394b | 1437 | /** |
2ef7eeaa EA |
1438 | * Called when user space prepares to use an object with the CPU, either |
1439 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1440 | */ |
1441 | int | |
1442 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1443 | struct drm_file *file) |
673a394b EA |
1444 | { |
1445 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1446 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1447 | uint32_t read_domains = args->read_domains; |
1448 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1449 | int ret; |
1450 | ||
2ef7eeaa | 1451 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1452 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1453 | return -EINVAL; |
1454 | ||
21d509e3 | 1455 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1456 | return -EINVAL; |
1457 | ||
1458 | /* Having something in the write domain implies it's in the read | |
1459 | * domain, and only that read domain. Enforce that in the request. | |
1460 | */ | |
1461 | if (write_domain != 0 && read_domains != write_domain) | |
1462 | return -EINVAL; | |
1463 | ||
76c1dec1 | 1464 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1465 | if (ret) |
76c1dec1 | 1466 | return ret; |
1d7cfea1 | 1467 | |
05394f39 | 1468 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1469 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1470 | ret = -ENOENT; |
1471 | goto unlock; | |
76c1dec1 | 1472 | } |
673a394b | 1473 | |
3236f57a CW |
1474 | /* Try to flush the object off the GPU without holding the lock. |
1475 | * We will repeat the flush holding the lock in the normal manner | |
1476 | * to catch cases where we are gazumped. | |
1477 | */ | |
6e4930f6 CW |
1478 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1479 | file->driver_priv, | |
1480 | !write_domain); | |
3236f57a CW |
1481 | if (ret) |
1482 | goto unref; | |
1483 | ||
43566ded | 1484 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1485 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1486 | else |
e47c68e9 | 1487 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1488 | |
3236f57a | 1489 | unref: |
05394f39 | 1490 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1491 | unlock: |
673a394b EA |
1492 | mutex_unlock(&dev->struct_mutex); |
1493 | return ret; | |
1494 | } | |
1495 | ||
1496 | /** | |
1497 | * Called when user space has done writes to this buffer | |
1498 | */ | |
1499 | int | |
1500 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1501 | struct drm_file *file) |
673a394b EA |
1502 | { |
1503 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1504 | struct drm_i915_gem_object *obj; |
673a394b EA |
1505 | int ret = 0; |
1506 | ||
76c1dec1 | 1507 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1508 | if (ret) |
76c1dec1 | 1509 | return ret; |
1d7cfea1 | 1510 | |
05394f39 | 1511 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1512 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1513 | ret = -ENOENT; |
1514 | goto unlock; | |
673a394b EA |
1515 | } |
1516 | ||
673a394b | 1517 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1518 | if (obj->pin_display) |
1519 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1520 | |
05394f39 | 1521 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1522 | unlock: |
673a394b EA |
1523 | mutex_unlock(&dev->struct_mutex); |
1524 | return ret; | |
1525 | } | |
1526 | ||
1527 | /** | |
1528 | * Maps the contents of an object, returning the address it is mapped | |
1529 | * into. | |
1530 | * | |
1531 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1532 | * imply a ref on the object itself. | |
34367381 DV |
1533 | * |
1534 | * IMPORTANT: | |
1535 | * | |
1536 | * DRM driver writers who look a this function as an example for how to do GEM | |
1537 | * mmap support, please don't implement mmap support like here. The modern way | |
1538 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1539 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1540 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1541 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1542 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1543 | */ |
1544 | int | |
1545 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1546 | struct drm_file *file) |
673a394b EA |
1547 | { |
1548 | struct drm_i915_gem_mmap *args = data; | |
1549 | struct drm_gem_object *obj; | |
673a394b EA |
1550 | unsigned long addr; |
1551 | ||
1816f923 AG |
1552 | if (args->flags & ~(I915_MMAP_WC)) |
1553 | return -EINVAL; | |
1554 | ||
1555 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) | |
1556 | return -ENODEV; | |
1557 | ||
05394f39 | 1558 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1559 | if (obj == NULL) |
bf79cb91 | 1560 | return -ENOENT; |
673a394b | 1561 | |
1286ff73 DV |
1562 | /* prime objects have no backing filp to GEM mmap |
1563 | * pages from. | |
1564 | */ | |
1565 | if (!obj->filp) { | |
1566 | drm_gem_object_unreference_unlocked(obj); | |
1567 | return -EINVAL; | |
1568 | } | |
1569 | ||
6be5ceb0 | 1570 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1571 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1572 | args->offset); | |
1816f923 AG |
1573 | if (args->flags & I915_MMAP_WC) { |
1574 | struct mm_struct *mm = current->mm; | |
1575 | struct vm_area_struct *vma; | |
1576 | ||
1577 | down_write(&mm->mmap_sem); | |
1578 | vma = find_vma(mm, addr); | |
1579 | if (vma) | |
1580 | vma->vm_page_prot = | |
1581 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1582 | else | |
1583 | addr = -ENOMEM; | |
1584 | up_write(&mm->mmap_sem); | |
1585 | } | |
bc9025bd | 1586 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1587 | if (IS_ERR((void *)addr)) |
1588 | return addr; | |
1589 | ||
1590 | args->addr_ptr = (uint64_t) addr; | |
1591 | ||
1592 | return 0; | |
1593 | } | |
1594 | ||
de151cf6 JB |
1595 | /** |
1596 | * i915_gem_fault - fault a page into the GTT | |
1597 | * vma: VMA in question | |
1598 | * vmf: fault info | |
1599 | * | |
1600 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1601 | * from userspace. The fault handler takes care of binding the object to | |
1602 | * the GTT (if needed), allocating and programming a fence register (again, | |
1603 | * only if needed based on whether the old reg is still valid or the object | |
1604 | * is tiled) and inserting a new PTE into the faulting process. | |
1605 | * | |
1606 | * Note that the faulting process may involve evicting existing objects | |
1607 | * from the GTT and/or fence registers to make room. So performance may | |
1608 | * suffer if the GTT working set is large or there are few fence registers | |
1609 | * left. | |
1610 | */ | |
1611 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1612 | { | |
05394f39 CW |
1613 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1614 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1615 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1616 | pgoff_t page_offset; |
1617 | unsigned long pfn; | |
1618 | int ret = 0; | |
0f973f27 | 1619 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1620 | |
f65c9168 PZ |
1621 | intel_runtime_pm_get(dev_priv); |
1622 | ||
de151cf6 JB |
1623 | /* We don't use vmf->pgoff since that has the fake offset */ |
1624 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1625 | PAGE_SHIFT; | |
1626 | ||
d9bc7e9f CW |
1627 | ret = i915_mutex_lock_interruptible(dev); |
1628 | if (ret) | |
1629 | goto out; | |
a00b10c3 | 1630 | |
db53a302 CW |
1631 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1632 | ||
6e4930f6 CW |
1633 | /* Try to flush the object off the GPU first without holding the lock. |
1634 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1635 | * repeat the flush holding the lock in the normal manner to catch cases | |
1636 | * where we are gazumped. | |
1637 | */ | |
1638 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1639 | if (ret) | |
1640 | goto unlock; | |
1641 | ||
eb119bd6 CW |
1642 | /* Access to snoopable pages through the GTT is incoherent. */ |
1643 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1644 | ret = -EFAULT; |
eb119bd6 CW |
1645 | goto unlock; |
1646 | } | |
1647 | ||
d9bc7e9f | 1648 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1649 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1650 | if (ret) |
1651 | goto unlock; | |
4a684a41 | 1652 | |
c9839303 CW |
1653 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1654 | if (ret) | |
1655 | goto unpin; | |
74898d7e | 1656 | |
06d98131 | 1657 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1658 | if (ret) |
c9839303 | 1659 | goto unpin; |
7d1c4804 | 1660 | |
b90b91d8 | 1661 | /* Finally, remap it using the new GTT offset */ |
f343c5f6 BW |
1662 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1663 | pfn >>= PAGE_SHIFT; | |
de151cf6 | 1664 | |
b90b91d8 | 1665 | if (!obj->fault_mappable) { |
beff0d0f VS |
1666 | unsigned long size = min_t(unsigned long, |
1667 | vma->vm_end - vma->vm_start, | |
1668 | obj->base.size); | |
b90b91d8 CW |
1669 | int i; |
1670 | ||
beff0d0f | 1671 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
b90b91d8 CW |
1672 | ret = vm_insert_pfn(vma, |
1673 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1674 | pfn + i); | |
1675 | if (ret) | |
1676 | break; | |
1677 | } | |
1678 | ||
1679 | obj->fault_mappable = true; | |
1680 | } else | |
1681 | ret = vm_insert_pfn(vma, | |
1682 | (unsigned long)vmf->virtual_address, | |
1683 | pfn + page_offset); | |
c9839303 | 1684 | unpin: |
d7f46fc4 | 1685 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1686 | unlock: |
de151cf6 | 1687 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1688 | out: |
de151cf6 | 1689 | switch (ret) { |
d9bc7e9f | 1690 | case -EIO: |
2232f031 DV |
1691 | /* |
1692 | * We eat errors when the gpu is terminally wedged to avoid | |
1693 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1694 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1695 | * and so needs to be reported. | |
1696 | */ | |
1697 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1698 | ret = VM_FAULT_SIGBUS; |
1699 | break; | |
1700 | } | |
045e769a | 1701 | case -EAGAIN: |
571c608d DV |
1702 | /* |
1703 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1704 | * handler to reset everything when re-faulting in | |
1705 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1706 | */ |
c715089f CW |
1707 | case 0: |
1708 | case -ERESTARTSYS: | |
bed636ab | 1709 | case -EINTR: |
e79e0fe3 DR |
1710 | case -EBUSY: |
1711 | /* | |
1712 | * EBUSY is ok: this just means that another thread | |
1713 | * already did the job. | |
1714 | */ | |
f65c9168 PZ |
1715 | ret = VM_FAULT_NOPAGE; |
1716 | break; | |
de151cf6 | 1717 | case -ENOMEM: |
f65c9168 PZ |
1718 | ret = VM_FAULT_OOM; |
1719 | break; | |
a7c2e1aa | 1720 | case -ENOSPC: |
45d67817 | 1721 | case -EFAULT: |
f65c9168 PZ |
1722 | ret = VM_FAULT_SIGBUS; |
1723 | break; | |
de151cf6 | 1724 | default: |
a7c2e1aa | 1725 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1726 | ret = VM_FAULT_SIGBUS; |
1727 | break; | |
de151cf6 | 1728 | } |
f65c9168 PZ |
1729 | |
1730 | intel_runtime_pm_put(dev_priv); | |
1731 | return ret; | |
de151cf6 JB |
1732 | } |
1733 | ||
901782b2 CW |
1734 | /** |
1735 | * i915_gem_release_mmap - remove physical page mappings | |
1736 | * @obj: obj in question | |
1737 | * | |
af901ca1 | 1738 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1739 | * relinquish ownership of the pages back to the system. |
1740 | * | |
1741 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1742 | * object through the GTT and then lose the fence register due to | |
1743 | * resource pressure. Similarly if the object has been moved out of the | |
1744 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1745 | * mapping will then trigger a page fault on the next user access, allowing | |
1746 | * fixup by i915_gem_fault(). | |
1747 | */ | |
d05ca301 | 1748 | void |
05394f39 | 1749 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1750 | { |
6299f992 CW |
1751 | if (!obj->fault_mappable) |
1752 | return; | |
901782b2 | 1753 | |
6796cb16 DH |
1754 | drm_vma_node_unmap(&obj->base.vma_node, |
1755 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1756 | obj->fault_mappable = false; |
901782b2 CW |
1757 | } |
1758 | ||
eedd10f4 CW |
1759 | void |
1760 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1761 | { | |
1762 | struct drm_i915_gem_object *obj; | |
1763 | ||
1764 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1765 | i915_gem_release_mmap(obj); | |
1766 | } | |
1767 | ||
0fa87796 | 1768 | uint32_t |
e28f8711 | 1769 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1770 | { |
e28f8711 | 1771 | uint32_t gtt_size; |
92b88aeb CW |
1772 | |
1773 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1774 | tiling_mode == I915_TILING_NONE) |
1775 | return size; | |
92b88aeb CW |
1776 | |
1777 | /* Previous chips need a power-of-two fence region when tiling */ | |
1778 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1779 | gtt_size = 1024*1024; |
92b88aeb | 1780 | else |
e28f8711 | 1781 | gtt_size = 512*1024; |
92b88aeb | 1782 | |
e28f8711 CW |
1783 | while (gtt_size < size) |
1784 | gtt_size <<= 1; | |
92b88aeb | 1785 | |
e28f8711 | 1786 | return gtt_size; |
92b88aeb CW |
1787 | } |
1788 | ||
de151cf6 JB |
1789 | /** |
1790 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1791 | * @obj: object to check | |
1792 | * | |
1793 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1794 | * potential fence register mapping. |
de151cf6 | 1795 | */ |
d865110c ID |
1796 | uint32_t |
1797 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1798 | int tiling_mode, bool fenced) | |
de151cf6 | 1799 | { |
de151cf6 JB |
1800 | /* |
1801 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1802 | * if a fence register is needed for the object. | |
1803 | */ | |
d865110c | 1804 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1805 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1806 | return 4096; |
1807 | ||
a00b10c3 CW |
1808 | /* |
1809 | * Previous chips need to be aligned to the size of the smallest | |
1810 | * fence register that can contain the object. | |
1811 | */ | |
e28f8711 | 1812 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1813 | } |
1814 | ||
d8cb5086 CW |
1815 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1816 | { | |
1817 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1818 | int ret; | |
1819 | ||
0de23977 | 1820 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1821 | return 0; |
1822 | ||
da494d7c DV |
1823 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1824 | ||
d8cb5086 CW |
1825 | ret = drm_gem_create_mmap_offset(&obj->base); |
1826 | if (ret != -ENOSPC) | |
da494d7c | 1827 | goto out; |
d8cb5086 CW |
1828 | |
1829 | /* Badly fragmented mmap space? The only way we can recover | |
1830 | * space is by destroying unwanted objects. We can't randomly release | |
1831 | * mmap_offsets as userspace expects them to be persistent for the | |
1832 | * lifetime of the objects. The closest we can is to release the | |
1833 | * offsets on purgeable objects by truncating it and marking it purged, | |
1834 | * which prevents userspace from ever using that object again. | |
1835 | */ | |
21ab4e74 CW |
1836 | i915_gem_shrink(dev_priv, |
1837 | obj->base.size >> PAGE_SHIFT, | |
1838 | I915_SHRINK_BOUND | | |
1839 | I915_SHRINK_UNBOUND | | |
1840 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1841 | ret = drm_gem_create_mmap_offset(&obj->base); |
1842 | if (ret != -ENOSPC) | |
da494d7c | 1843 | goto out; |
d8cb5086 CW |
1844 | |
1845 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1846 | ret = drm_gem_create_mmap_offset(&obj->base); |
1847 | out: | |
1848 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1849 | ||
1850 | return ret; | |
d8cb5086 CW |
1851 | } |
1852 | ||
1853 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1854 | { | |
d8cb5086 CW |
1855 | drm_gem_free_mmap_offset(&obj->base); |
1856 | } | |
1857 | ||
da6b51d0 | 1858 | int |
ff72145b DA |
1859 | i915_gem_mmap_gtt(struct drm_file *file, |
1860 | struct drm_device *dev, | |
da6b51d0 | 1861 | uint32_t handle, |
ff72145b | 1862 | uint64_t *offset) |
de151cf6 | 1863 | { |
da761a6e | 1864 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1865 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1866 | int ret; |
1867 | ||
76c1dec1 | 1868 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1869 | if (ret) |
76c1dec1 | 1870 | return ret; |
de151cf6 | 1871 | |
ff72145b | 1872 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1873 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1874 | ret = -ENOENT; |
1875 | goto unlock; | |
1876 | } | |
de151cf6 | 1877 | |
5d4545ae | 1878 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1879 | ret = -E2BIG; |
ff56b0bc | 1880 | goto out; |
da761a6e CW |
1881 | } |
1882 | ||
05394f39 | 1883 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1884 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1885 | ret = -EFAULT; |
1d7cfea1 | 1886 | goto out; |
ab18282d CW |
1887 | } |
1888 | ||
d8cb5086 CW |
1889 | ret = i915_gem_object_create_mmap_offset(obj); |
1890 | if (ret) | |
1891 | goto out; | |
de151cf6 | 1892 | |
0de23977 | 1893 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1894 | |
1d7cfea1 | 1895 | out: |
05394f39 | 1896 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1897 | unlock: |
de151cf6 | 1898 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1899 | return ret; |
de151cf6 JB |
1900 | } |
1901 | ||
ff72145b DA |
1902 | /** |
1903 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1904 | * @dev: DRM device | |
1905 | * @data: GTT mapping ioctl data | |
1906 | * @file: GEM object info | |
1907 | * | |
1908 | * Simply returns the fake offset to userspace so it can mmap it. | |
1909 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1910 | * up so we can get faults in the handler above. | |
1911 | * | |
1912 | * The fault handler will take care of binding the object into the GTT | |
1913 | * (since it may have been evicted to make room for something), allocating | |
1914 | * a fence register, and mapping the appropriate aperture address into | |
1915 | * userspace. | |
1916 | */ | |
1917 | int | |
1918 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1919 | struct drm_file *file) | |
1920 | { | |
1921 | struct drm_i915_gem_mmap_gtt *args = data; | |
1922 | ||
da6b51d0 | 1923 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
1924 | } |
1925 | ||
5537252b CW |
1926 | static inline int |
1927 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1928 | { | |
1929 | return obj->madv == I915_MADV_DONTNEED; | |
1930 | } | |
1931 | ||
225067ee DV |
1932 | /* Immediately discard the backing storage */ |
1933 | static void | |
1934 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1935 | { |
4d6294bf | 1936 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1937 | |
4d6294bf CW |
1938 | if (obj->base.filp == NULL) |
1939 | return; | |
e5281ccd | 1940 | |
225067ee DV |
1941 | /* Our goal here is to return as much of the memory as |
1942 | * is possible back to the system as we are called from OOM. | |
1943 | * To do this we must instruct the shmfs to drop all of its | |
1944 | * backing pages, *now*. | |
1945 | */ | |
5537252b | 1946 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1947 | obj->madv = __I915_MADV_PURGED; |
1948 | } | |
e5281ccd | 1949 | |
5537252b CW |
1950 | /* Try to discard unwanted pages */ |
1951 | static void | |
1952 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1953 | { |
5537252b CW |
1954 | struct address_space *mapping; |
1955 | ||
1956 | switch (obj->madv) { | |
1957 | case I915_MADV_DONTNEED: | |
1958 | i915_gem_object_truncate(obj); | |
1959 | case __I915_MADV_PURGED: | |
1960 | return; | |
1961 | } | |
1962 | ||
1963 | if (obj->base.filp == NULL) | |
1964 | return; | |
1965 | ||
1966 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1967 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1968 | } |
1969 | ||
5cdf5881 | 1970 | static void |
05394f39 | 1971 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1972 | { |
90797e6d ID |
1973 | struct sg_page_iter sg_iter; |
1974 | int ret; | |
1286ff73 | 1975 | |
05394f39 | 1976 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1977 | |
6c085a72 CW |
1978 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1979 | if (ret) { | |
1980 | /* In the event of a disaster, abandon all caches and | |
1981 | * hope for the best. | |
1982 | */ | |
1983 | WARN_ON(ret != -EIO); | |
2c22569b | 1984 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1985 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1986 | } | |
1987 | ||
6dacfd2f | 1988 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1989 | i915_gem_object_save_bit_17_swizzle(obj); |
1990 | ||
05394f39 CW |
1991 | if (obj->madv == I915_MADV_DONTNEED) |
1992 | obj->dirty = 0; | |
3ef94daa | 1993 | |
90797e6d | 1994 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1995 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1996 | |
05394f39 | 1997 | if (obj->dirty) |
9da3da66 | 1998 | set_page_dirty(page); |
3ef94daa | 1999 | |
05394f39 | 2000 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2001 | mark_page_accessed(page); |
3ef94daa | 2002 | |
9da3da66 | 2003 | page_cache_release(page); |
3ef94daa | 2004 | } |
05394f39 | 2005 | obj->dirty = 0; |
673a394b | 2006 | |
9da3da66 CW |
2007 | sg_free_table(obj->pages); |
2008 | kfree(obj->pages); | |
37e680a1 | 2009 | } |
6c085a72 | 2010 | |
dd624afd | 2011 | int |
37e680a1 CW |
2012 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2013 | { | |
2014 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2015 | ||
2f745ad3 | 2016 | if (obj->pages == NULL) |
37e680a1 CW |
2017 | return 0; |
2018 | ||
a5570178 CW |
2019 | if (obj->pages_pin_count) |
2020 | return -EBUSY; | |
2021 | ||
9843877d | 2022 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2023 | |
a2165e31 CW |
2024 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2025 | * array, hence protect them from being reaped by removing them from gtt | |
2026 | * lists early. */ | |
35c20a60 | 2027 | list_del(&obj->global_list); |
a2165e31 | 2028 | |
37e680a1 | 2029 | ops->put_pages(obj); |
05394f39 | 2030 | obj->pages = NULL; |
37e680a1 | 2031 | |
5537252b | 2032 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2033 | |
2034 | return 0; | |
2035 | } | |
2036 | ||
21ab4e74 CW |
2037 | unsigned long |
2038 | i915_gem_shrink(struct drm_i915_private *dev_priv, | |
2039 | long target, unsigned flags) | |
6c085a72 | 2040 | { |
60a53727 CW |
2041 | const struct { |
2042 | struct list_head *list; | |
2043 | unsigned int bit; | |
2044 | } phases[] = { | |
2045 | { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND }, | |
2046 | { &dev_priv->mm.bound_list, I915_SHRINK_BOUND }, | |
2047 | { NULL, 0 }, | |
2048 | }, *phase; | |
d9973b43 | 2049 | unsigned long count = 0; |
6c085a72 | 2050 | |
57094f82 | 2051 | /* |
c8725f3d | 2052 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
2053 | * (due to retiring requests) we have to strictly process only |
2054 | * one element of the list at the time, and recheck the list | |
2055 | * on every iteration. | |
c8725f3d CW |
2056 | * |
2057 | * In particular, we must hold a reference whilst removing the | |
2058 | * object as we may end up waiting for and/or retiring the objects. | |
2059 | * This might release the final reference (held by the active list) | |
2060 | * and result in the object being freed from under us. This is | |
2061 | * similar to the precautions the eviction code must take whilst | |
2062 | * removing objects. | |
2063 | * | |
2064 | * Also note that although these lists do not hold a reference to | |
2065 | * the object we can safely grab one here: The final object | |
2066 | * unreferencing and the bound_list are both protected by the | |
2067 | * dev->struct_mutex and so we won't ever be able to observe an | |
2068 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 2069 | */ |
60a53727 | 2070 | for (phase = phases; phase->list; phase++) { |
21ab4e74 | 2071 | struct list_head still_in_list; |
c8725f3d | 2072 | |
60a53727 CW |
2073 | if ((flags & phase->bit) == 0) |
2074 | continue; | |
80dcfdbd | 2075 | |
21ab4e74 | 2076 | INIT_LIST_HEAD(&still_in_list); |
60a53727 | 2077 | while (count < target && !list_empty(phase->list)) { |
21ab4e74 CW |
2078 | struct drm_i915_gem_object *obj; |
2079 | struct i915_vma *vma, *v; | |
57094f82 | 2080 | |
60a53727 | 2081 | obj = list_first_entry(phase->list, |
21ab4e74 CW |
2082 | typeof(*obj), global_list); |
2083 | list_move_tail(&obj->global_list, &still_in_list); | |
80dcfdbd | 2084 | |
60a53727 CW |
2085 | if (flags & I915_SHRINK_PURGEABLE && |
2086 | !i915_gem_object_is_purgeable(obj)) | |
21ab4e74 | 2087 | continue; |
57094f82 | 2088 | |
21ab4e74 | 2089 | drm_gem_object_reference(&obj->base); |
80dcfdbd | 2090 | |
60a53727 CW |
2091 | /* For the unbound phase, this should be a no-op! */ |
2092 | list_for_each_entry_safe(vma, v, | |
2093 | &obj->vma_list, vma_link) | |
21ab4e74 CW |
2094 | if (i915_vma_unbind(vma)) |
2095 | break; | |
57094f82 | 2096 | |
21ab4e74 CW |
2097 | if (i915_gem_object_put_pages(obj) == 0) |
2098 | count += obj->base.size >> PAGE_SHIFT; | |
2099 | ||
2100 | drm_gem_object_unreference(&obj->base); | |
2101 | } | |
60a53727 | 2102 | list_splice(&still_in_list, phase->list); |
6c085a72 CW |
2103 | } |
2104 | ||
2105 | return count; | |
2106 | } | |
2107 | ||
d9973b43 | 2108 | static unsigned long |
6c085a72 CW |
2109 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
2110 | { | |
6c085a72 | 2111 | i915_gem_evict_everything(dev_priv->dev); |
21ab4e74 CW |
2112 | return i915_gem_shrink(dev_priv, LONG_MAX, |
2113 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); | |
225067ee DV |
2114 | } |
2115 | ||
37e680a1 | 2116 | static int |
6c085a72 | 2117 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2118 | { |
6c085a72 | 2119 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2120 | int page_count, i; |
2121 | struct address_space *mapping; | |
9da3da66 CW |
2122 | struct sg_table *st; |
2123 | struct scatterlist *sg; | |
90797e6d | 2124 | struct sg_page_iter sg_iter; |
e5281ccd | 2125 | struct page *page; |
90797e6d | 2126 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2127 | gfp_t gfp; |
e5281ccd | 2128 | |
6c085a72 CW |
2129 | /* Assert that the object is not currently in any GPU domain. As it |
2130 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2131 | * a GPU cache | |
2132 | */ | |
2133 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2134 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2135 | ||
9da3da66 CW |
2136 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2137 | if (st == NULL) | |
2138 | return -ENOMEM; | |
2139 | ||
05394f39 | 2140 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2141 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2142 | kfree(st); |
e5281ccd | 2143 | return -ENOMEM; |
9da3da66 | 2144 | } |
e5281ccd | 2145 | |
9da3da66 CW |
2146 | /* Get the list of pages out of our struct file. They'll be pinned |
2147 | * at this point until we release them. | |
2148 | * | |
2149 | * Fail silently without starting the shrinker | |
2150 | */ | |
496ad9aa | 2151 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2152 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2153 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2154 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2155 | sg = st->sgl; |
2156 | st->nents = 0; | |
2157 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2158 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2159 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2160 | i915_gem_shrink(dev_priv, |
2161 | page_count, | |
2162 | I915_SHRINK_BOUND | | |
2163 | I915_SHRINK_UNBOUND | | |
2164 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2165 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2166 | } | |
2167 | if (IS_ERR(page)) { | |
2168 | /* We've tried hard to allocate the memory by reaping | |
2169 | * our own buffer, now let the real VM do its job and | |
2170 | * go down in flames if truly OOM. | |
2171 | */ | |
6c085a72 | 2172 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2173 | page = shmem_read_mapping_page(mapping, i); |
6c085a72 CW |
2174 | if (IS_ERR(page)) |
2175 | goto err_pages; | |
6c085a72 | 2176 | } |
426729dc KRW |
2177 | #ifdef CONFIG_SWIOTLB |
2178 | if (swiotlb_nr_tbl()) { | |
2179 | st->nents++; | |
2180 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2181 | sg = sg_next(sg); | |
2182 | continue; | |
2183 | } | |
2184 | #endif | |
90797e6d ID |
2185 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2186 | if (i) | |
2187 | sg = sg_next(sg); | |
2188 | st->nents++; | |
2189 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2190 | } else { | |
2191 | sg->length += PAGE_SIZE; | |
2192 | } | |
2193 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2194 | |
2195 | /* Check that the i965g/gm workaround works. */ | |
2196 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2197 | } |
426729dc KRW |
2198 | #ifdef CONFIG_SWIOTLB |
2199 | if (!swiotlb_nr_tbl()) | |
2200 | #endif | |
2201 | sg_mark_end(sg); | |
74ce6b6c CW |
2202 | obj->pages = st; |
2203 | ||
6dacfd2f | 2204 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2205 | i915_gem_object_do_bit_17_swizzle(obj); |
2206 | ||
656bfa3a DV |
2207 | if (obj->tiling_mode != I915_TILING_NONE && |
2208 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2209 | i915_gem_object_pin_pages(obj); | |
2210 | ||
e5281ccd CW |
2211 | return 0; |
2212 | ||
2213 | err_pages: | |
90797e6d ID |
2214 | sg_mark_end(sg); |
2215 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2216 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2217 | sg_free_table(st); |
2218 | kfree(st); | |
0820baf3 CW |
2219 | |
2220 | /* shmemfs first checks if there is enough memory to allocate the page | |
2221 | * and reports ENOSPC should there be insufficient, along with the usual | |
2222 | * ENOMEM for a genuine allocation failure. | |
2223 | * | |
2224 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2225 | * space and so want to translate the error from shmemfs back to our | |
2226 | * usual understanding of ENOMEM. | |
2227 | */ | |
2228 | if (PTR_ERR(page) == -ENOSPC) | |
2229 | return -ENOMEM; | |
2230 | else | |
2231 | return PTR_ERR(page); | |
673a394b EA |
2232 | } |
2233 | ||
37e680a1 CW |
2234 | /* Ensure that the associated pages are gathered from the backing storage |
2235 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2236 | * multiple times before they are released by a single call to | |
2237 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2238 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2239 | * or as the object is itself released. | |
2240 | */ | |
2241 | int | |
2242 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2243 | { | |
2244 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2245 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2246 | int ret; | |
2247 | ||
2f745ad3 | 2248 | if (obj->pages) |
37e680a1 CW |
2249 | return 0; |
2250 | ||
43e28f09 | 2251 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2252 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2253 | return -EFAULT; |
43e28f09 CW |
2254 | } |
2255 | ||
a5570178 CW |
2256 | BUG_ON(obj->pages_pin_count); |
2257 | ||
37e680a1 CW |
2258 | ret = ops->get_pages(obj); |
2259 | if (ret) | |
2260 | return ret; | |
2261 | ||
35c20a60 | 2262 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2263 | return 0; |
673a394b EA |
2264 | } |
2265 | ||
e2d05a8b | 2266 | static void |
05394f39 | 2267 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2268 | struct intel_engine_cs *ring) |
673a394b | 2269 | { |
41c52415 JH |
2270 | struct drm_i915_gem_request *req; |
2271 | struct intel_engine_cs *old_ring; | |
617dbe27 | 2272 | |
852835f3 | 2273 | BUG_ON(ring == NULL); |
41c52415 JH |
2274 | |
2275 | req = intel_ring_get_request(ring); | |
2276 | old_ring = i915_gem_request_get_ring(obj->last_read_req); | |
2277 | ||
2278 | if (old_ring != ring && obj->last_write_req) { | |
97b2a6a1 JH |
2279 | /* Keep the request relative to the current ring */ |
2280 | i915_gem_request_assign(&obj->last_write_req, req); | |
02978ff5 | 2281 | } |
673a394b EA |
2282 | |
2283 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2284 | if (!obj->active) { |
2285 | drm_gem_object_reference(&obj->base); | |
2286 | obj->active = 1; | |
673a394b | 2287 | } |
e35a41de | 2288 | |
05394f39 | 2289 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2290 | |
97b2a6a1 | 2291 | i915_gem_request_assign(&obj->last_read_req, req); |
caea7476 CW |
2292 | } |
2293 | ||
e2d05a8b | 2294 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2295 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2296 | { |
2297 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2298 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2299 | } | |
2300 | ||
caea7476 | 2301 | static void |
caea7476 | 2302 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2303 | { |
feb822cf | 2304 | struct i915_vma *vma; |
ce44b0ea | 2305 | |
65ce3027 | 2306 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2307 | BUG_ON(!obj->active); |
caea7476 | 2308 | |
fe14d5f4 TU |
2309 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
2310 | if (!list_empty(&vma->mm_list)) | |
2311 | list_move_tail(&vma->mm_list, &vma->vm->inactive_list); | |
feb822cf | 2312 | } |
caea7476 | 2313 | |
f99d7069 DV |
2314 | intel_fb_obj_flush(obj, true); |
2315 | ||
65ce3027 | 2316 | list_del_init(&obj->ring_list); |
caea7476 | 2317 | |
97b2a6a1 JH |
2318 | i915_gem_request_assign(&obj->last_read_req, NULL); |
2319 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
65ce3027 CW |
2320 | obj->base.write_domain = 0; |
2321 | ||
97b2a6a1 | 2322 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 CW |
2323 | |
2324 | obj->active = 0; | |
2325 | drm_gem_object_unreference(&obj->base); | |
2326 | ||
2327 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2328 | } |
673a394b | 2329 | |
c8725f3d CW |
2330 | static void |
2331 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2332 | { | |
41c52415 | 2333 | if (obj->last_read_req == NULL) |
c8725f3d CW |
2334 | return; |
2335 | ||
1b5a433a | 2336 | if (i915_gem_request_completed(obj->last_read_req, true)) |
c8725f3d CW |
2337 | i915_gem_object_move_to_inactive(obj); |
2338 | } | |
2339 | ||
9d773091 | 2340 | static int |
fca26bb4 | 2341 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2342 | { |
9d773091 | 2343 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2344 | struct intel_engine_cs *ring; |
9d773091 | 2345 | int ret, i, j; |
53d227f2 | 2346 | |
107f27a5 | 2347 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2348 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2349 | ret = intel_ring_idle(ring); |
2350 | if (ret) | |
2351 | return ret; | |
9d773091 | 2352 | } |
9d773091 | 2353 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2354 | |
2355 | /* Finally reset hw state */ | |
9d773091 | 2356 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2357 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2358 | |
ebc348b2 BW |
2359 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2360 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2361 | } |
53d227f2 | 2362 | |
9d773091 | 2363 | return 0; |
53d227f2 DV |
2364 | } |
2365 | ||
fca26bb4 MK |
2366 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2367 | { | |
2368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2369 | int ret; | |
2370 | ||
2371 | if (seqno == 0) | |
2372 | return -EINVAL; | |
2373 | ||
2374 | /* HWS page needs to be set less than what we | |
2375 | * will inject to ring | |
2376 | */ | |
2377 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2378 | if (ret) | |
2379 | return ret; | |
2380 | ||
2381 | /* Carefully set the last_seqno value so that wrap | |
2382 | * detection still works | |
2383 | */ | |
2384 | dev_priv->next_seqno = seqno; | |
2385 | dev_priv->last_seqno = seqno - 1; | |
2386 | if (dev_priv->last_seqno == 0) | |
2387 | dev_priv->last_seqno--; | |
2388 | ||
2389 | return 0; | |
2390 | } | |
2391 | ||
9d773091 CW |
2392 | int |
2393 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2394 | { |
9d773091 CW |
2395 | struct drm_i915_private *dev_priv = dev->dev_private; |
2396 | ||
2397 | /* reserve 0 for non-seqno */ | |
2398 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2399 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2400 | if (ret) |
2401 | return ret; | |
53d227f2 | 2402 | |
9d773091 CW |
2403 | dev_priv->next_seqno = 1; |
2404 | } | |
53d227f2 | 2405 | |
f72b3435 | 2406 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2407 | return 0; |
53d227f2 DV |
2408 | } |
2409 | ||
a4872ba6 | 2410 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2411 | struct drm_file *file, |
9400ae5c | 2412 | struct drm_i915_gem_object *obj) |
673a394b | 2413 | { |
3e31c6c0 | 2414 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2415 | struct drm_i915_gem_request *request; |
48e29f55 | 2416 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2417 | u32 request_start; |
3cce469c CW |
2418 | int ret; |
2419 | ||
6259cead | 2420 | request = ring->outstanding_lazy_request; |
48e29f55 OM |
2421 | if (WARN_ON(request == NULL)) |
2422 | return -ENOMEM; | |
2423 | ||
2424 | if (i915.enable_execlists) { | |
21076372 | 2425 | ringbuf = request->ctx->engine[ring->id].ringbuf; |
48e29f55 OM |
2426 | } else |
2427 | ringbuf = ring->buffer; | |
2428 | ||
2429 | request_start = intel_ring_get_tail(ringbuf); | |
cc889e0f DV |
2430 | /* |
2431 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2432 | * after having emitted the batchbuffer command. Hence we need to fix | |
2433 | * things up similar to emitting the lazy request. The difference here | |
2434 | * is that the flush _must_ happen before the next request, no matter | |
2435 | * what. | |
2436 | */ | |
48e29f55 | 2437 | if (i915.enable_execlists) { |
21076372 | 2438 | ret = logical_ring_flush_all_caches(ringbuf, request->ctx); |
48e29f55 OM |
2439 | if (ret) |
2440 | return ret; | |
2441 | } else { | |
2442 | ret = intel_ring_flush_all_caches(ring); | |
2443 | if (ret) | |
2444 | return ret; | |
2445 | } | |
cc889e0f | 2446 | |
a71d8d94 CW |
2447 | /* Record the position of the start of the request so that |
2448 | * should we detect the updated seqno part-way through the | |
2449 | * GPU processing the request, we never over-estimate the | |
2450 | * position of the head. | |
2451 | */ | |
6d3d8274 | 2452 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2453 | |
48e29f55 | 2454 | if (i915.enable_execlists) { |
72f95afa | 2455 | ret = ring->emit_request(ringbuf, request); |
48e29f55 OM |
2456 | if (ret) |
2457 | return ret; | |
2458 | } else { | |
2459 | ret = ring->add_request(ring); | |
2460 | if (ret) | |
2461 | return ret; | |
2462 | } | |
673a394b | 2463 | |
7d736f4f | 2464 | request->head = request_start; |
6d3d8274 | 2465 | request->tail = intel_ring_get_tail(ringbuf); |
7d736f4f MK |
2466 | |
2467 | /* Whilst this request exists, batch_obj will be on the | |
2468 | * active_list, and so will hold the active reference. Only when this | |
2469 | * request is retired will the the batch_obj be moved onto the | |
2470 | * inactive_list and lose its active reference. Hence we do not need | |
2471 | * to explicitly hold another reference here. | |
2472 | */ | |
9a7e0c2a | 2473 | request->batch_obj = obj; |
0e50e96b | 2474 | |
48e29f55 OM |
2475 | if (!i915.enable_execlists) { |
2476 | /* Hold a reference to the current context so that we can inspect | |
2477 | * it later in case a hangcheck error event fires. | |
2478 | */ | |
2479 | request->ctx = ring->last_context; | |
2480 | if (request->ctx) | |
2481 | i915_gem_context_reference(request->ctx); | |
2482 | } | |
0e50e96b | 2483 | |
673a394b | 2484 | request->emitted_jiffies = jiffies; |
852835f3 | 2485 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2486 | request->file_priv = NULL; |
852835f3 | 2487 | |
db53a302 CW |
2488 | if (file) { |
2489 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2490 | ||
1c25595f | 2491 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2492 | request->file_priv = file_priv; |
b962442e | 2493 | list_add_tail(&request->client_list, |
f787a5f5 | 2494 | &file_priv->mm.request_list); |
1c25595f | 2495 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2496 | } |
673a394b | 2497 | |
74328ee5 | 2498 | trace_i915_gem_request_add(request); |
6259cead | 2499 | ring->outstanding_lazy_request = NULL; |
db53a302 | 2500 | |
87255483 | 2501 | i915_queue_hangcheck(ring->dev); |
10cd45b6 | 2502 | |
87255483 DV |
2503 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2504 | queue_delayed_work(dev_priv->wq, | |
2505 | &dev_priv->mm.retire_work, | |
2506 | round_jiffies_up_relative(HZ)); | |
2507 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2508 | |
3cce469c | 2509 | return 0; |
673a394b EA |
2510 | } |
2511 | ||
f787a5f5 CW |
2512 | static inline void |
2513 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2514 | { |
1c25595f | 2515 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2516 | |
1c25595f CW |
2517 | if (!file_priv) |
2518 | return; | |
1c5d22f7 | 2519 | |
1c25595f | 2520 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2521 | list_del(&request->client_list); |
2522 | request->file_priv = NULL; | |
1c25595f | 2523 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2524 | } |
673a394b | 2525 | |
939fd762 | 2526 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2527 | const struct intel_context *ctx) |
be62acb4 | 2528 | { |
44e2c070 | 2529 | unsigned long elapsed; |
be62acb4 | 2530 | |
44e2c070 MK |
2531 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2532 | ||
2533 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2534 | return true; |
2535 | ||
676fa572 CW |
2536 | if (ctx->hang_stats.ban_period_seconds && |
2537 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
ccc7bed0 | 2538 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2539 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2540 | return true; |
88b4aa87 MK |
2541 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2542 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2543 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2544 | return true; |
3fac8978 | 2545 | } |
be62acb4 MK |
2546 | } |
2547 | ||
2548 | return false; | |
2549 | } | |
2550 | ||
939fd762 | 2551 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2552 | struct intel_context *ctx, |
b6b0fac0 | 2553 | const bool guilty) |
aa60c664 | 2554 | { |
44e2c070 MK |
2555 | struct i915_ctx_hang_stats *hs; |
2556 | ||
2557 | if (WARN_ON(!ctx)) | |
2558 | return; | |
aa60c664 | 2559 | |
44e2c070 MK |
2560 | hs = &ctx->hang_stats; |
2561 | ||
2562 | if (guilty) { | |
939fd762 | 2563 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2564 | hs->batch_active++; |
2565 | hs->guilty_ts = get_seconds(); | |
2566 | } else { | |
2567 | hs->batch_pending++; | |
aa60c664 MK |
2568 | } |
2569 | } | |
2570 | ||
0e50e96b MK |
2571 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2572 | { | |
2573 | list_del(&request->list); | |
2574 | i915_gem_request_remove_from_client(request); | |
2575 | ||
abfe262a JH |
2576 | i915_gem_request_unreference(request); |
2577 | } | |
2578 | ||
2579 | void i915_gem_request_free(struct kref *req_ref) | |
2580 | { | |
2581 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2582 | typeof(*req), ref); | |
2583 | struct intel_context *ctx = req->ctx; | |
2584 | ||
0794aed3 TD |
2585 | if (ctx) { |
2586 | if (i915.enable_execlists) { | |
abfe262a | 2587 | struct intel_engine_cs *ring = req->ring; |
0e50e96b | 2588 | |
0794aed3 TD |
2589 | if (ctx != ring->default_context) |
2590 | intel_lr_context_unpin(ring, ctx); | |
2591 | } | |
abfe262a | 2592 | |
dcb4c12a OM |
2593 | i915_gem_context_unreference(ctx); |
2594 | } | |
abfe262a JH |
2595 | |
2596 | kfree(req); | |
0e50e96b MK |
2597 | } |
2598 | ||
8d9fc7fd | 2599 | struct drm_i915_gem_request * |
a4872ba6 | 2600 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2601 | { |
4db080f9 CW |
2602 | struct drm_i915_gem_request *request; |
2603 | ||
2604 | list_for_each_entry(request, &ring->request_list, list) { | |
1b5a433a | 2605 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2606 | continue; |
aa60c664 | 2607 | |
b6b0fac0 | 2608 | return request; |
4db080f9 | 2609 | } |
b6b0fac0 MK |
2610 | |
2611 | return NULL; | |
2612 | } | |
2613 | ||
2614 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2615 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2616 | { |
2617 | struct drm_i915_gem_request *request; | |
2618 | bool ring_hung; | |
2619 | ||
8d9fc7fd | 2620 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2621 | |
2622 | if (request == NULL) | |
2623 | return; | |
2624 | ||
2625 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2626 | ||
939fd762 | 2627 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2628 | |
2629 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2630 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2631 | } |
aa60c664 | 2632 | |
4db080f9 | 2633 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2634 | struct intel_engine_cs *ring) |
4db080f9 | 2635 | { |
dfaae392 | 2636 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2637 | struct drm_i915_gem_object *obj; |
9375e446 | 2638 | |
05394f39 CW |
2639 | obj = list_first_entry(&ring->active_list, |
2640 | struct drm_i915_gem_object, | |
2641 | ring_list); | |
9375e446 | 2642 | |
05394f39 | 2643 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2644 | } |
1d62beea | 2645 | |
dcb4c12a OM |
2646 | /* |
2647 | * Clear the execlists queue up before freeing the requests, as those | |
2648 | * are the ones that keep the context and ringbuffer backing objects | |
2649 | * pinned in place. | |
2650 | */ | |
2651 | while (!list_empty(&ring->execlist_queue)) { | |
6d3d8274 | 2652 | struct drm_i915_gem_request *submit_req; |
dcb4c12a OM |
2653 | |
2654 | submit_req = list_first_entry(&ring->execlist_queue, | |
6d3d8274 | 2655 | struct drm_i915_gem_request, |
dcb4c12a OM |
2656 | execlist_link); |
2657 | list_del(&submit_req->execlist_link); | |
2658 | intel_runtime_pm_put(dev_priv); | |
6d3d8274 | 2659 | i915_gem_context_unreference(submit_req->ctx); |
dcb4c12a OM |
2660 | kfree(submit_req); |
2661 | } | |
2662 | ||
1d62beea BW |
2663 | /* |
2664 | * We must free the requests after all the corresponding objects have | |
2665 | * been moved off active lists. Which is the same order as the normal | |
2666 | * retire_requests function does. This is important if object hold | |
2667 | * implicit references on things like e.g. ppgtt address spaces through | |
2668 | * the request. | |
2669 | */ | |
2670 | while (!list_empty(&ring->request_list)) { | |
2671 | struct drm_i915_gem_request *request; | |
2672 | ||
2673 | request = list_first_entry(&ring->request_list, | |
2674 | struct drm_i915_gem_request, | |
2675 | list); | |
2676 | ||
2677 | i915_gem_free_request(request); | |
2678 | } | |
e3efda49 | 2679 | |
6259cead JH |
2680 | /* This may not have been flushed before the reset, so clean it now */ |
2681 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); | |
673a394b EA |
2682 | } |
2683 | ||
19b2dbde | 2684 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2685 | { |
2686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2687 | int i; | |
2688 | ||
4b9de737 | 2689 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2690 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2691 | |
94a335db DV |
2692 | /* |
2693 | * Commit delayed tiling changes if we have an object still | |
2694 | * attached to the fence, otherwise just clear the fence. | |
2695 | */ | |
2696 | if (reg->obj) { | |
2697 | i915_gem_object_update_fence(reg->obj, reg, | |
2698 | reg->obj->tiling_mode); | |
2699 | } else { | |
2700 | i915_gem_write_fence(dev, i, NULL); | |
2701 | } | |
312817a3 CW |
2702 | } |
2703 | } | |
2704 | ||
069efc1d | 2705 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2706 | { |
77f01230 | 2707 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2708 | struct intel_engine_cs *ring; |
1ec14ad3 | 2709 | int i; |
673a394b | 2710 | |
4db080f9 CW |
2711 | /* |
2712 | * Before we free the objects from the requests, we need to inspect | |
2713 | * them for finding the guilty party. As the requests only borrow | |
2714 | * their reference to the objects, the inspection must be done first. | |
2715 | */ | |
2716 | for_each_ring(ring, dev_priv, i) | |
2717 | i915_gem_reset_ring_status(dev_priv, ring); | |
2718 | ||
b4519513 | 2719 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2720 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2721 | |
acce9ffa BW |
2722 | i915_gem_context_reset(dev); |
2723 | ||
19b2dbde | 2724 | i915_gem_restore_fences(dev); |
673a394b EA |
2725 | } |
2726 | ||
2727 | /** | |
2728 | * This function clears the request list as sequence numbers are passed. | |
2729 | */ | |
1cf0ba14 | 2730 | void |
a4872ba6 | 2731 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2732 | { |
db53a302 | 2733 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2734 | return; |
2735 | ||
db53a302 | 2736 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2737 | |
e9103038 CW |
2738 | /* Move any buffers on the active list that are no longer referenced |
2739 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2740 | * before we free the context associated with the requests. | |
2741 | */ | |
2742 | while (!list_empty(&ring->active_list)) { | |
2743 | struct drm_i915_gem_object *obj; | |
2744 | ||
2745 | obj = list_first_entry(&ring->active_list, | |
2746 | struct drm_i915_gem_object, | |
2747 | ring_list); | |
2748 | ||
1b5a433a | 2749 | if (!i915_gem_request_completed(obj->last_read_req, true)) |
e9103038 CW |
2750 | break; |
2751 | ||
2752 | i915_gem_object_move_to_inactive(obj); | |
2753 | } | |
2754 | ||
2755 | ||
852835f3 | 2756 | while (!list_empty(&ring->request_list)) { |
673a394b | 2757 | struct drm_i915_gem_request *request; |
48e29f55 | 2758 | struct intel_ringbuffer *ringbuf; |
673a394b | 2759 | |
852835f3 | 2760 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2761 | struct drm_i915_gem_request, |
2762 | list); | |
673a394b | 2763 | |
1b5a433a | 2764 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
2765 | break; |
2766 | ||
74328ee5 | 2767 | trace_i915_gem_request_retire(request); |
48e29f55 OM |
2768 | |
2769 | /* This is one of the few common intersection points | |
2770 | * between legacy ringbuffer submission and execlists: | |
2771 | * we need to tell them apart in order to find the correct | |
2772 | * ringbuffer to which the request belongs to. | |
2773 | */ | |
2774 | if (i915.enable_execlists) { | |
2775 | struct intel_context *ctx = request->ctx; | |
2776 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2777 | } else | |
2778 | ringbuf = ring->buffer; | |
2779 | ||
a71d8d94 CW |
2780 | /* We know the GPU must have read the request to have |
2781 | * sent us the seqno + interrupt, so use the position | |
2782 | * of tail of the request to update the last known position | |
2783 | * of the GPU head. | |
2784 | */ | |
72f95afa | 2785 | ringbuf->last_retired_head = request->postfix; |
b84d5f0c | 2786 | |
0e50e96b | 2787 | i915_gem_free_request(request); |
b84d5f0c | 2788 | } |
673a394b | 2789 | |
581c26e8 JH |
2790 | if (unlikely(ring->trace_irq_req && |
2791 | i915_gem_request_completed(ring->trace_irq_req, true))) { | |
1ec14ad3 | 2792 | ring->irq_put(ring); |
581c26e8 | 2793 | i915_gem_request_assign(&ring->trace_irq_req, NULL); |
9d34e5db | 2794 | } |
23bc5982 | 2795 | |
db53a302 | 2796 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2797 | } |
2798 | ||
b29c19b6 | 2799 | bool |
b09a1fec CW |
2800 | i915_gem_retire_requests(struct drm_device *dev) |
2801 | { | |
3e31c6c0 | 2802 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2803 | struct intel_engine_cs *ring; |
b29c19b6 | 2804 | bool idle = true; |
1ec14ad3 | 2805 | int i; |
b09a1fec | 2806 | |
b29c19b6 | 2807 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2808 | i915_gem_retire_requests_ring(ring); |
b29c19b6 | 2809 | idle &= list_empty(&ring->request_list); |
c86ee3a9 TD |
2810 | if (i915.enable_execlists) { |
2811 | unsigned long flags; | |
2812 | ||
2813 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2814 | idle &= list_empty(&ring->execlist_queue); | |
2815 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
2816 | ||
2817 | intel_execlists_retire_requests(ring); | |
2818 | } | |
b29c19b6 CW |
2819 | } |
2820 | ||
2821 | if (idle) | |
2822 | mod_delayed_work(dev_priv->wq, | |
2823 | &dev_priv->mm.idle_work, | |
2824 | msecs_to_jiffies(100)); | |
2825 | ||
2826 | return idle; | |
b09a1fec CW |
2827 | } |
2828 | ||
75ef9da2 | 2829 | static void |
673a394b EA |
2830 | i915_gem_retire_work_handler(struct work_struct *work) |
2831 | { | |
b29c19b6 CW |
2832 | struct drm_i915_private *dev_priv = |
2833 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2834 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2835 | bool idle; |
673a394b | 2836 | |
891b48cf | 2837 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2838 | idle = false; |
2839 | if (mutex_trylock(&dev->struct_mutex)) { | |
2840 | idle = i915_gem_retire_requests(dev); | |
2841 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2842 | } |
b29c19b6 | 2843 | if (!idle) |
bcb45086 CW |
2844 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2845 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2846 | } |
0a58705b | 2847 | |
b29c19b6 CW |
2848 | static void |
2849 | i915_gem_idle_work_handler(struct work_struct *work) | |
2850 | { | |
2851 | struct drm_i915_private *dev_priv = | |
2852 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2853 | ||
2854 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2855 | } |
2856 | ||
30dfebf3 DV |
2857 | /** |
2858 | * Ensures that an object will eventually get non-busy by flushing any required | |
2859 | * write domains, emitting any outstanding lazy request and retiring and | |
2860 | * completed requests. | |
2861 | */ | |
2862 | static int | |
2863 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2864 | { | |
41c52415 | 2865 | struct intel_engine_cs *ring; |
30dfebf3 DV |
2866 | int ret; |
2867 | ||
2868 | if (obj->active) { | |
41c52415 JH |
2869 | ring = i915_gem_request_get_ring(obj->last_read_req); |
2870 | ||
b6660d59 | 2871 | ret = i915_gem_check_olr(obj->last_read_req); |
30dfebf3 DV |
2872 | if (ret) |
2873 | return ret; | |
2874 | ||
41c52415 | 2875 | i915_gem_retire_requests_ring(ring); |
30dfebf3 DV |
2876 | } |
2877 | ||
2878 | return 0; | |
2879 | } | |
2880 | ||
23ba4fd0 BW |
2881 | /** |
2882 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2883 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2884 | * | |
2885 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2886 | * the timeout parameter. | |
2887 | * -ETIME: object is still busy after timeout | |
2888 | * -ERESTARTSYS: signal interrupted the wait | |
2889 | * -ENONENT: object doesn't exist | |
2890 | * Also possible, but rare: | |
2891 | * -EAGAIN: GPU wedged | |
2892 | * -ENOMEM: damn | |
2893 | * -ENODEV: Internal IRQ fail | |
2894 | * -E?: The add request failed | |
2895 | * | |
2896 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2897 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2898 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2899 | * without holding struct_mutex the object may become re-busied before this | |
2900 | * function completes. A similar but shorter * race condition exists in the busy | |
2901 | * ioctl | |
2902 | */ | |
2903 | int | |
2904 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2905 | { | |
3e31c6c0 | 2906 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2907 | struct drm_i915_gem_wait *args = data; |
2908 | struct drm_i915_gem_object *obj; | |
ff865885 | 2909 | struct drm_i915_gem_request *req; |
f69061be | 2910 | unsigned reset_counter; |
23ba4fd0 BW |
2911 | int ret = 0; |
2912 | ||
11b5d511 DV |
2913 | if (args->flags != 0) |
2914 | return -EINVAL; | |
2915 | ||
23ba4fd0 BW |
2916 | ret = i915_mutex_lock_interruptible(dev); |
2917 | if (ret) | |
2918 | return ret; | |
2919 | ||
2920 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2921 | if (&obj->base == NULL) { | |
2922 | mutex_unlock(&dev->struct_mutex); | |
2923 | return -ENOENT; | |
2924 | } | |
2925 | ||
30dfebf3 DV |
2926 | /* Need to make sure the object gets inactive eventually. */ |
2927 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2928 | if (ret) |
2929 | goto out; | |
2930 | ||
97b2a6a1 JH |
2931 | if (!obj->active || !obj->last_read_req) |
2932 | goto out; | |
23ba4fd0 | 2933 | |
ff865885 | 2934 | req = obj->last_read_req; |
23ba4fd0 | 2935 | |
23ba4fd0 | 2936 | /* Do this after OLR check to make sure we make forward progress polling |
5ed0bdf2 | 2937 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
23ba4fd0 | 2938 | */ |
5ed0bdf2 | 2939 | if (args->timeout_ns <= 0) { |
23ba4fd0 BW |
2940 | ret = -ETIME; |
2941 | goto out; | |
2942 | } | |
2943 | ||
2944 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2945 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 2946 | i915_gem_request_reference(req); |
23ba4fd0 BW |
2947 | mutex_unlock(&dev->struct_mutex); |
2948 | ||
9c654818 JH |
2949 | ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns, |
2950 | file->driver_priv); | |
ff865885 JH |
2951 | mutex_lock(&dev->struct_mutex); |
2952 | i915_gem_request_unreference(req); | |
2953 | mutex_unlock(&dev->struct_mutex); | |
2954 | return ret; | |
23ba4fd0 BW |
2955 | |
2956 | out: | |
2957 | drm_gem_object_unreference(&obj->base); | |
2958 | mutex_unlock(&dev->struct_mutex); | |
2959 | return ret; | |
2960 | } | |
2961 | ||
5816d648 BW |
2962 | /** |
2963 | * i915_gem_object_sync - sync an object to a ring. | |
2964 | * | |
2965 | * @obj: object which may be in use on another ring. | |
2966 | * @to: ring we wish to use the object on. May be NULL. | |
2967 | * | |
2968 | * This code is meant to abstract object synchronization with the GPU. | |
2969 | * Calling with NULL implies synchronizing the object with the CPU | |
2970 | * rather than a particular GPU ring. | |
2971 | * | |
2972 | * Returns 0 if successful, else propagates up the lower layer error. | |
2973 | */ | |
2911a35b BW |
2974 | int |
2975 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2976 | struct intel_engine_cs *to) |
2911a35b | 2977 | { |
41c52415 | 2978 | struct intel_engine_cs *from; |
2911a35b BW |
2979 | u32 seqno; |
2980 | int ret, idx; | |
2981 | ||
41c52415 JH |
2982 | from = i915_gem_request_get_ring(obj->last_read_req); |
2983 | ||
2911a35b BW |
2984 | if (from == NULL || to == from) |
2985 | return 0; | |
2986 | ||
5816d648 | 2987 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2988 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2989 | |
2990 | idx = intel_ring_sync_index(from, to); | |
2991 | ||
97b2a6a1 | 2992 | seqno = i915_gem_request_get_seqno(obj->last_read_req); |
ddd4dbc6 RV |
2993 | /* Optimization: Avoid semaphore sync when we are sure we already |
2994 | * waited for an object with higher seqno */ | |
ebc348b2 | 2995 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2996 | return 0; |
2997 | ||
b6660d59 | 2998 | ret = i915_gem_check_olr(obj->last_read_req); |
b4aca010 BW |
2999 | if (ret) |
3000 | return ret; | |
2911a35b | 3001 | |
74328ee5 | 3002 | trace_i915_gem_ring_sync_to(from, to, obj->last_read_req); |
ebc348b2 | 3003 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 3004 | if (!ret) |
97b2a6a1 | 3005 | /* We use last_read_req because sync_to() |
7b01e260 MK |
3006 | * might have just caused seqno wrap under |
3007 | * the radar. | |
3008 | */ | |
97b2a6a1 JH |
3009 | from->semaphore.sync_seqno[idx] = |
3010 | i915_gem_request_get_seqno(obj->last_read_req); | |
2911a35b | 3011 | |
e3a5a225 | 3012 | return ret; |
2911a35b BW |
3013 | } |
3014 | ||
b5ffc9bc CW |
3015 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3016 | { | |
3017 | u32 old_write_domain, old_read_domains; | |
3018 | ||
b5ffc9bc CW |
3019 | /* Force a pagefault for domain tracking on next user access */ |
3020 | i915_gem_release_mmap(obj); | |
3021 | ||
b97c3d9c KP |
3022 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3023 | return; | |
3024 | ||
97c809fd CW |
3025 | /* Wait for any direct GTT access to complete */ |
3026 | mb(); | |
3027 | ||
b5ffc9bc CW |
3028 | old_read_domains = obj->base.read_domains; |
3029 | old_write_domain = obj->base.write_domain; | |
3030 | ||
3031 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3032 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3033 | ||
3034 | trace_i915_gem_object_change_domain(obj, | |
3035 | old_read_domains, | |
3036 | old_write_domain); | |
3037 | } | |
3038 | ||
07fe0b12 | 3039 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 3040 | { |
07fe0b12 | 3041 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3042 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3043 | int ret; |
673a394b | 3044 | |
07fe0b12 | 3045 | if (list_empty(&vma->vma_link)) |
673a394b EA |
3046 | return 0; |
3047 | ||
0ff501cb DV |
3048 | if (!drm_mm_node_allocated(&vma->node)) { |
3049 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3050 | return 0; |
3051 | } | |
433544bd | 3052 | |
d7f46fc4 | 3053 | if (vma->pin_count) |
31d8d651 | 3054 | return -EBUSY; |
673a394b | 3055 | |
c4670ad0 CW |
3056 | BUG_ON(obj->pages == NULL); |
3057 | ||
a8198eea | 3058 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 3059 | if (ret) |
a8198eea CW |
3060 | return ret; |
3061 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
3062 | * should be safe and we need to cleanup or else we might | |
3063 | * cause memory corruption through use-after-free. | |
3064 | */ | |
3065 | ||
fe14d5f4 TU |
3066 | if (i915_is_ggtt(vma->vm) && |
3067 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
8b1bc9b4 | 3068 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3069 | |
8b1bc9b4 DV |
3070 | /* release the fence reg _after_ flushing */ |
3071 | ret = i915_gem_object_put_fence(obj); | |
3072 | if (ret) | |
3073 | return ret; | |
3074 | } | |
96b47b65 | 3075 | |
07fe0b12 | 3076 | trace_i915_vma_unbind(vma); |
db53a302 | 3077 | |
6f65e29a BW |
3078 | vma->unbind_vma(vma); |
3079 | ||
64bf9303 | 3080 | list_del_init(&vma->mm_list); |
fe14d5f4 TU |
3081 | if (i915_is_ggtt(vma->vm)) { |
3082 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
3083 | obj->map_and_fenceable = false; | |
3084 | } else if (vma->ggtt_view.pages) { | |
3085 | sg_free_table(vma->ggtt_view.pages); | |
3086 | kfree(vma->ggtt_view.pages); | |
3087 | vma->ggtt_view.pages = NULL; | |
3088 | } | |
3089 | } | |
673a394b | 3090 | |
2f633156 BW |
3091 | drm_mm_remove_node(&vma->node); |
3092 | i915_gem_vma_destroy(vma); | |
3093 | ||
3094 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3095 | * no more VMAs exist. */ |
9490edb5 | 3096 | if (list_empty(&obj->vma_list)) { |
fe14d5f4 TU |
3097 | /* Throw away the active reference before |
3098 | * moving to the unbound list. */ | |
3099 | i915_gem_object_retire(obj); | |
3100 | ||
9490edb5 | 3101 | i915_gem_gtt_finish_object(obj); |
2f633156 | 3102 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
9490edb5 | 3103 | } |
673a394b | 3104 | |
70903c3b CW |
3105 | /* And finally now the object is completely decoupled from this vma, |
3106 | * we can drop its hold on the backing storage and allow it to be | |
3107 | * reaped by the shrinker. | |
3108 | */ | |
3109 | i915_gem_object_unpin_pages(obj); | |
3110 | ||
88241785 | 3111 | return 0; |
54cf91dc CW |
3112 | } |
3113 | ||
b2da9fe5 | 3114 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3115 | { |
3e31c6c0 | 3116 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3117 | struct intel_engine_cs *ring; |
1ec14ad3 | 3118 | int ret, i; |
4df2faf4 | 3119 | |
4df2faf4 | 3120 | /* Flush everything onto the inactive list. */ |
b4519513 | 3121 | for_each_ring(ring, dev_priv, i) { |
ecdb5fd8 TD |
3122 | if (!i915.enable_execlists) { |
3123 | ret = i915_switch_context(ring, ring->default_context); | |
3124 | if (ret) | |
3125 | return ret; | |
3126 | } | |
b6c7488d | 3127 | |
3e960501 | 3128 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
3129 | if (ret) |
3130 | return ret; | |
3131 | } | |
4df2faf4 | 3132 | |
8a1a49f9 | 3133 | return 0; |
4df2faf4 DV |
3134 | } |
3135 | ||
9ce079e4 CW |
3136 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
3137 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3138 | { |
3e31c6c0 | 3139 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
3140 | int fence_reg; |
3141 | int fence_pitch_shift; | |
de151cf6 | 3142 | |
56c844e5 ID |
3143 | if (INTEL_INFO(dev)->gen >= 6) { |
3144 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
3145 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
3146 | } else { | |
3147 | fence_reg = FENCE_REG_965_0; | |
3148 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
3149 | } | |
3150 | ||
d18b9619 CW |
3151 | fence_reg += reg * 8; |
3152 | ||
3153 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
3154 | * we split the 64-bit update into two 32-bit writes. In order | |
3155 | * for a partial fence not to be evaluated between writes, we | |
3156 | * precede the update with write to turn off the fence register, | |
3157 | * and only enable the fence as the last step. | |
3158 | * | |
3159 | * For extra levels of paranoia, we make sure each step lands | |
3160 | * before applying the next step. | |
3161 | */ | |
3162 | I915_WRITE(fence_reg, 0); | |
3163 | POSTING_READ(fence_reg); | |
3164 | ||
9ce079e4 | 3165 | if (obj) { |
f343c5f6 | 3166 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 3167 | uint64_t val; |
de151cf6 | 3168 | |
f343c5f6 | 3169 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3170 | 0xfffff000) << 32; |
f343c5f6 | 3171 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3172 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3173 | if (obj->tiling_mode == I915_TILING_Y) |
3174 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3175 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3176 | |
d18b9619 CW |
3177 | I915_WRITE(fence_reg + 4, val >> 32); |
3178 | POSTING_READ(fence_reg + 4); | |
3179 | ||
3180 | I915_WRITE(fence_reg + 0, val); | |
3181 | POSTING_READ(fence_reg); | |
3182 | } else { | |
3183 | I915_WRITE(fence_reg + 4, 0); | |
3184 | POSTING_READ(fence_reg + 4); | |
3185 | } | |
de151cf6 JB |
3186 | } |
3187 | ||
9ce079e4 CW |
3188 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3189 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3190 | { |
3e31c6c0 | 3191 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3192 | u32 val; |
de151cf6 | 3193 | |
9ce079e4 | 3194 | if (obj) { |
f343c5f6 | 3195 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3196 | int pitch_val; |
3197 | int tile_width; | |
c6642782 | 3198 | |
f343c5f6 | 3199 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3200 | (size & -size) != size || |
f343c5f6 BW |
3201 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3202 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3203 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3204 | |
9ce079e4 CW |
3205 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3206 | tile_width = 128; | |
3207 | else | |
3208 | tile_width = 512; | |
3209 | ||
3210 | /* Note: pitch better be a power of two tile widths */ | |
3211 | pitch_val = obj->stride / tile_width; | |
3212 | pitch_val = ffs(pitch_val) - 1; | |
3213 | ||
f343c5f6 | 3214 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3215 | if (obj->tiling_mode == I915_TILING_Y) |
3216 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3217 | val |= I915_FENCE_SIZE_BITS(size); | |
3218 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3219 | val |= I830_FENCE_REG_VALID; | |
3220 | } else | |
3221 | val = 0; | |
3222 | ||
3223 | if (reg < 8) | |
3224 | reg = FENCE_REG_830_0 + reg * 4; | |
3225 | else | |
3226 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3227 | ||
3228 | I915_WRITE(reg, val); | |
3229 | POSTING_READ(reg); | |
de151cf6 JB |
3230 | } |
3231 | ||
9ce079e4 CW |
3232 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3233 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3234 | { |
3e31c6c0 | 3235 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3236 | uint32_t val; |
de151cf6 | 3237 | |
9ce079e4 | 3238 | if (obj) { |
f343c5f6 | 3239 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3240 | uint32_t pitch_val; |
de151cf6 | 3241 | |
f343c5f6 | 3242 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3243 | (size & -size) != size || |
f343c5f6 BW |
3244 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3245 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3246 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3247 | |
9ce079e4 CW |
3248 | pitch_val = obj->stride / 128; |
3249 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3250 | |
f343c5f6 | 3251 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3252 | if (obj->tiling_mode == I915_TILING_Y) |
3253 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3254 | val |= I830_FENCE_SIZE_BITS(size); | |
3255 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3256 | val |= I830_FENCE_REG_VALID; | |
3257 | } else | |
3258 | val = 0; | |
c6642782 | 3259 | |
9ce079e4 CW |
3260 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3261 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3262 | } | |
3263 | ||
d0a57789 CW |
3264 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3265 | { | |
3266 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3267 | } | |
3268 | ||
9ce079e4 CW |
3269 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3270 | struct drm_i915_gem_object *obj) | |
3271 | { | |
d0a57789 CW |
3272 | struct drm_i915_private *dev_priv = dev->dev_private; |
3273 | ||
3274 | /* Ensure that all CPU reads are completed before installing a fence | |
3275 | * and all writes before removing the fence. | |
3276 | */ | |
3277 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3278 | mb(); | |
3279 | ||
94a335db DV |
3280 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3281 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3282 | obj->stride, obj->tiling_mode); | |
3283 | ||
ce38ab05 RV |
3284 | if (IS_GEN2(dev)) |
3285 | i830_write_fence_reg(dev, reg, obj); | |
3286 | else if (IS_GEN3(dev)) | |
3287 | i915_write_fence_reg(dev, reg, obj); | |
3288 | else if (INTEL_INFO(dev)->gen >= 4) | |
3289 | i965_write_fence_reg(dev, reg, obj); | |
d0a57789 CW |
3290 | |
3291 | /* And similarly be paranoid that no direct access to this region | |
3292 | * is reordered to before the fence is installed. | |
3293 | */ | |
3294 | if (i915_gem_object_needs_mb(obj)) | |
3295 | mb(); | |
de151cf6 JB |
3296 | } |
3297 | ||
61050808 CW |
3298 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3299 | struct drm_i915_fence_reg *fence) | |
3300 | { | |
3301 | return fence - dev_priv->fence_regs; | |
3302 | } | |
3303 | ||
3304 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3305 | struct drm_i915_fence_reg *fence, | |
3306 | bool enable) | |
3307 | { | |
2dc8aae0 | 3308 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3309 | int reg = fence_number(dev_priv, fence); |
3310 | ||
3311 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3312 | |
3313 | if (enable) { | |
46a0b638 | 3314 | obj->fence_reg = reg; |
61050808 CW |
3315 | fence->obj = obj; |
3316 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3317 | } else { | |
3318 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3319 | fence->obj = NULL; | |
3320 | list_del_init(&fence->lru_list); | |
3321 | } | |
94a335db | 3322 | obj->fence_dirty = false; |
61050808 CW |
3323 | } |
3324 | ||
d9e86c0e | 3325 | static int |
d0a57789 | 3326 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3327 | { |
97b2a6a1 | 3328 | if (obj->last_fenced_req) { |
a4b3a571 | 3329 | int ret = i915_wait_request(obj->last_fenced_req); |
18991845 CW |
3330 | if (ret) |
3331 | return ret; | |
d9e86c0e | 3332 | |
97b2a6a1 | 3333 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
d9e86c0e CW |
3334 | } |
3335 | ||
3336 | return 0; | |
3337 | } | |
3338 | ||
3339 | int | |
3340 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3341 | { | |
61050808 | 3342 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3343 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3344 | int ret; |
3345 | ||
d0a57789 | 3346 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3347 | if (ret) |
3348 | return ret; | |
3349 | ||
61050808 CW |
3350 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3351 | return 0; | |
d9e86c0e | 3352 | |
f9c513e9 CW |
3353 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3354 | ||
aff10b30 DV |
3355 | if (WARN_ON(fence->pin_count)) |
3356 | return -EBUSY; | |
3357 | ||
61050808 | 3358 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3359 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3360 | |
3361 | return 0; | |
3362 | } | |
3363 | ||
3364 | static struct drm_i915_fence_reg * | |
a360bb1a | 3365 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3366 | { |
ae3db24a | 3367 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3368 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3369 | int i; |
ae3db24a DV |
3370 | |
3371 | /* First try to find a free reg */ | |
d9e86c0e | 3372 | avail = NULL; |
ae3db24a DV |
3373 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3374 | reg = &dev_priv->fence_regs[i]; | |
3375 | if (!reg->obj) | |
d9e86c0e | 3376 | return reg; |
ae3db24a | 3377 | |
1690e1eb | 3378 | if (!reg->pin_count) |
d9e86c0e | 3379 | avail = reg; |
ae3db24a DV |
3380 | } |
3381 | ||
d9e86c0e | 3382 | if (avail == NULL) |
5dce5b93 | 3383 | goto deadlock; |
ae3db24a DV |
3384 | |
3385 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3386 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3387 | if (reg->pin_count) |
ae3db24a DV |
3388 | continue; |
3389 | ||
8fe301ad | 3390 | return reg; |
ae3db24a DV |
3391 | } |
3392 | ||
5dce5b93 CW |
3393 | deadlock: |
3394 | /* Wait for completion of pending flips which consume fences */ | |
3395 | if (intel_has_pending_fb_unpin(dev)) | |
3396 | return ERR_PTR(-EAGAIN); | |
3397 | ||
3398 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3399 | } |
3400 | ||
de151cf6 | 3401 | /** |
9a5a53b3 | 3402 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3403 | * @obj: object to map through a fence reg |
3404 | * | |
3405 | * When mapping objects through the GTT, userspace wants to be able to write | |
3406 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3407 | * This function walks the fence regs looking for a free one for @obj, |
3408 | * stealing one if it can't find any. | |
3409 | * | |
3410 | * It then sets up the reg based on the object's properties: address, pitch | |
3411 | * and tiling format. | |
9a5a53b3 CW |
3412 | * |
3413 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3414 | */ |
8c4b8c3f | 3415 | int |
06d98131 | 3416 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3417 | { |
05394f39 | 3418 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3419 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3420 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3421 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3422 | int ret; |
de151cf6 | 3423 | |
14415745 CW |
3424 | /* Have we updated the tiling parameters upon the object and so |
3425 | * will need to serialise the write to the associated fence register? | |
3426 | */ | |
5d82e3e6 | 3427 | if (obj->fence_dirty) { |
d0a57789 | 3428 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3429 | if (ret) |
3430 | return ret; | |
3431 | } | |
9a5a53b3 | 3432 | |
d9e86c0e | 3433 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3434 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3435 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3436 | if (!obj->fence_dirty) { |
14415745 CW |
3437 | list_move_tail(®->lru_list, |
3438 | &dev_priv->mm.fence_list); | |
3439 | return 0; | |
3440 | } | |
3441 | } else if (enable) { | |
e6a84468 CW |
3442 | if (WARN_ON(!obj->map_and_fenceable)) |
3443 | return -EINVAL; | |
3444 | ||
14415745 | 3445 | reg = i915_find_fence_reg(dev); |
5dce5b93 CW |
3446 | if (IS_ERR(reg)) |
3447 | return PTR_ERR(reg); | |
d9e86c0e | 3448 | |
14415745 CW |
3449 | if (reg->obj) { |
3450 | struct drm_i915_gem_object *old = reg->obj; | |
3451 | ||
d0a57789 | 3452 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3453 | if (ret) |
3454 | return ret; | |
3455 | ||
14415745 | 3456 | i915_gem_object_fence_lost(old); |
29c5a587 | 3457 | } |
14415745 | 3458 | } else |
a09ba7fa | 3459 | return 0; |
a09ba7fa | 3460 | |
14415745 | 3461 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3462 | |
9ce079e4 | 3463 | return 0; |
de151cf6 JB |
3464 | } |
3465 | ||
4144f9b5 | 3466 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3467 | unsigned long cache_level) |
3468 | { | |
4144f9b5 | 3469 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3470 | struct drm_mm_node *other; |
3471 | ||
4144f9b5 CW |
3472 | /* |
3473 | * On some machines we have to be careful when putting differing types | |
3474 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3475 | * domains and dying. During vm initialisation, we decide whether or not | |
3476 | * these constraints apply and set the drm_mm.color_adjust | |
3477 | * appropriately. | |
42d6ab48 | 3478 | */ |
4144f9b5 | 3479 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3480 | return true; |
3481 | ||
c6cfb325 | 3482 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3483 | return true; |
3484 | ||
3485 | if (list_empty(>t_space->node_list)) | |
3486 | return true; | |
3487 | ||
3488 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3489 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3490 | return false; | |
3491 | ||
3492 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3493 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3494 | return false; | |
3495 | ||
3496 | return true; | |
3497 | } | |
3498 | ||
673a394b EA |
3499 | /** |
3500 | * Finds free space in the GTT aperture and binds the object there. | |
3501 | */ | |
262de145 | 3502 | static struct i915_vma * |
07fe0b12 BW |
3503 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3504 | struct i915_address_space *vm, | |
3505 | unsigned alignment, | |
fe14d5f4 TU |
3506 | uint64_t flags, |
3507 | const struct i915_ggtt_view *view) | |
673a394b | 3508 | { |
05394f39 | 3509 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3510 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3511 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3512 | unsigned long start = |
3513 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3514 | unsigned long end = | |
1ec9e26d | 3515 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3516 | struct i915_vma *vma; |
07f73f69 | 3517 | int ret; |
673a394b | 3518 | |
e28f8711 CW |
3519 | fence_size = i915_gem_get_gtt_size(dev, |
3520 | obj->base.size, | |
3521 | obj->tiling_mode); | |
3522 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3523 | obj->base.size, | |
d865110c | 3524 | obj->tiling_mode, true); |
e28f8711 | 3525 | unfenced_alignment = |
d865110c | 3526 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3527 | obj->base.size, |
3528 | obj->tiling_mode, false); | |
a00b10c3 | 3529 | |
673a394b | 3530 | if (alignment == 0) |
1ec9e26d | 3531 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3532 | unfenced_alignment; |
1ec9e26d | 3533 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3534 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3535 | return ERR_PTR(-EINVAL); |
673a394b EA |
3536 | } |
3537 | ||
1ec9e26d | 3538 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3539 | |
654fc607 CW |
3540 | /* If the object is bigger than the entire aperture, reject it early |
3541 | * before evicting everything in a vain attempt to find space. | |
3542 | */ | |
d23db88c CW |
3543 | if (obj->base.size > end) { |
3544 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", | |
a36689cb | 3545 | obj->base.size, |
1ec9e26d | 3546 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3547 | end); |
262de145 | 3548 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3549 | } |
3550 | ||
37e680a1 | 3551 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3552 | if (ret) |
262de145 | 3553 | return ERR_PTR(ret); |
6c085a72 | 3554 | |
fbdda6fb CW |
3555 | i915_gem_object_pin_pages(obj); |
3556 | ||
fe14d5f4 | 3557 | vma = i915_gem_obj_lookup_or_create_vma_view(obj, vm, view); |
262de145 | 3558 | if (IS_ERR(vma)) |
bc6bc15b | 3559 | goto err_unpin; |
2f633156 | 3560 | |
0a9ae0d7 | 3561 | search_free: |
07fe0b12 | 3562 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3563 | size, alignment, |
d23db88c CW |
3564 | obj->cache_level, |
3565 | start, end, | |
62347f9e LK |
3566 | DRM_MM_SEARCH_DEFAULT, |
3567 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3568 | if (ret) { |
f6cd1f15 | 3569 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3570 | obj->cache_level, |
3571 | start, end, | |
3572 | flags); | |
dc9dd7a2 CW |
3573 | if (ret == 0) |
3574 | goto search_free; | |
9731129c | 3575 | |
bc6bc15b | 3576 | goto err_free_vma; |
673a394b | 3577 | } |
4144f9b5 | 3578 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3579 | ret = -EINVAL; |
bc6bc15b | 3580 | goto err_remove_node; |
673a394b EA |
3581 | } |
3582 | ||
74163907 | 3583 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3584 | if (ret) |
bc6bc15b | 3585 | goto err_remove_node; |
673a394b | 3586 | |
fe14d5f4 TU |
3587 | trace_i915_vma_bind(vma, flags); |
3588 | ret = i915_vma_bind(vma, obj->cache_level, | |
3589 | flags & PIN_GLOBAL ? GLOBAL_BIND : 0); | |
3590 | if (ret) | |
3591 | goto err_finish_gtt; | |
3592 | ||
35c20a60 | 3593 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3594 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3595 | |
262de145 | 3596 | return vma; |
2f633156 | 3597 | |
fe14d5f4 TU |
3598 | err_finish_gtt: |
3599 | i915_gem_gtt_finish_object(obj); | |
bc6bc15b | 3600 | err_remove_node: |
6286ef9b | 3601 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3602 | err_free_vma: |
2f633156 | 3603 | i915_gem_vma_destroy(vma); |
262de145 | 3604 | vma = ERR_PTR(ret); |
bc6bc15b | 3605 | err_unpin: |
2f633156 | 3606 | i915_gem_object_unpin_pages(obj); |
262de145 | 3607 | return vma; |
673a394b EA |
3608 | } |
3609 | ||
000433b6 | 3610 | bool |
2c22569b CW |
3611 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3612 | bool force) | |
673a394b | 3613 | { |
673a394b EA |
3614 | /* If we don't have a page list set up, then we're not pinned |
3615 | * to GPU, and we can ignore the cache flush because it'll happen | |
3616 | * again at bind time. | |
3617 | */ | |
05394f39 | 3618 | if (obj->pages == NULL) |
000433b6 | 3619 | return false; |
673a394b | 3620 | |
769ce464 ID |
3621 | /* |
3622 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3623 | * marked as wc by the system, or the system is cache-coherent. | |
3624 | */ | |
6a2c4232 | 3625 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3626 | return false; |
769ce464 | 3627 | |
9c23f7fc CW |
3628 | /* If the GPU is snooping the contents of the CPU cache, |
3629 | * we do not need to manually clear the CPU cache lines. However, | |
3630 | * the caches are only snooped when the render cache is | |
3631 | * flushed/invalidated. As we always have to emit invalidations | |
3632 | * and flushes when moving into and out of the RENDER domain, correct | |
3633 | * snooping behaviour occurs naturally as the result of our domain | |
3634 | * tracking. | |
3635 | */ | |
2c22569b | 3636 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3637 | return false; |
9c23f7fc | 3638 | |
1c5d22f7 | 3639 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3640 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3641 | |
3642 | return true; | |
e47c68e9 EA |
3643 | } |
3644 | ||
3645 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3646 | static void | |
05394f39 | 3647 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3648 | { |
1c5d22f7 CW |
3649 | uint32_t old_write_domain; |
3650 | ||
05394f39 | 3651 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3652 | return; |
3653 | ||
63256ec5 | 3654 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3655 | * to it immediately go to main memory as far as we know, so there's |
3656 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3657 | * |
3658 | * However, we do have to enforce the order so that all writes through | |
3659 | * the GTT land before any writes to the device, such as updates to | |
3660 | * the GATT itself. | |
e47c68e9 | 3661 | */ |
63256ec5 CW |
3662 | wmb(); |
3663 | ||
05394f39 CW |
3664 | old_write_domain = obj->base.write_domain; |
3665 | obj->base.write_domain = 0; | |
1c5d22f7 | 3666 | |
f99d7069 DV |
3667 | intel_fb_obj_flush(obj, false); |
3668 | ||
1c5d22f7 | 3669 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3670 | obj->base.read_domains, |
1c5d22f7 | 3671 | old_write_domain); |
e47c68e9 EA |
3672 | } |
3673 | ||
3674 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3675 | static void | |
2c22569b CW |
3676 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3677 | bool force) | |
e47c68e9 | 3678 | { |
1c5d22f7 | 3679 | uint32_t old_write_domain; |
e47c68e9 | 3680 | |
05394f39 | 3681 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3682 | return; |
3683 | ||
000433b6 CW |
3684 | if (i915_gem_clflush_object(obj, force)) |
3685 | i915_gem_chipset_flush(obj->base.dev); | |
3686 | ||
05394f39 CW |
3687 | old_write_domain = obj->base.write_domain; |
3688 | obj->base.write_domain = 0; | |
1c5d22f7 | 3689 | |
f99d7069 DV |
3690 | intel_fb_obj_flush(obj, false); |
3691 | ||
1c5d22f7 | 3692 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3693 | obj->base.read_domains, |
1c5d22f7 | 3694 | old_write_domain); |
e47c68e9 EA |
3695 | } |
3696 | ||
2ef7eeaa EA |
3697 | /** |
3698 | * Moves a single object to the GTT read, and possibly write domain. | |
3699 | * | |
3700 | * This function returns when the move is complete, including waiting on | |
3701 | * flushes to occur. | |
3702 | */ | |
79e53945 | 3703 | int |
2021746e | 3704 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3705 | { |
1c5d22f7 | 3706 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3707 | struct i915_vma *vma; |
e47c68e9 | 3708 | int ret; |
2ef7eeaa | 3709 | |
8d7e3de1 CW |
3710 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3711 | return 0; | |
3712 | ||
0201f1ec | 3713 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3714 | if (ret) |
3715 | return ret; | |
3716 | ||
c8725f3d | 3717 | i915_gem_object_retire(obj); |
43566ded CW |
3718 | |
3719 | /* Flush and acquire obj->pages so that we are coherent through | |
3720 | * direct access in memory with previous cached writes through | |
3721 | * shmemfs and that our cache domain tracking remains valid. | |
3722 | * For example, if the obj->filp was moved to swap without us | |
3723 | * being notified and releasing the pages, we would mistakenly | |
3724 | * continue to assume that the obj remained out of the CPU cached | |
3725 | * domain. | |
3726 | */ | |
3727 | ret = i915_gem_object_get_pages(obj); | |
3728 | if (ret) | |
3729 | return ret; | |
3730 | ||
2c22569b | 3731 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3732 | |
d0a57789 CW |
3733 | /* Serialise direct access to this object with the barriers for |
3734 | * coherent writes from the GPU, by effectively invalidating the | |
3735 | * GTT domain upon first access. | |
3736 | */ | |
3737 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3738 | mb(); | |
3739 | ||
05394f39 CW |
3740 | old_write_domain = obj->base.write_domain; |
3741 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3742 | |
e47c68e9 EA |
3743 | /* It should now be out of any other write domains, and we can update |
3744 | * the domain values for our changes. | |
3745 | */ | |
05394f39 CW |
3746 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3747 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3748 | if (write) { |
05394f39 CW |
3749 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3750 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3751 | obj->dirty = 1; | |
2ef7eeaa EA |
3752 | } |
3753 | ||
f99d7069 DV |
3754 | if (write) |
3755 | intel_fb_obj_invalidate(obj, NULL); | |
3756 | ||
1c5d22f7 CW |
3757 | trace_i915_gem_object_change_domain(obj, |
3758 | old_read_domains, | |
3759 | old_write_domain); | |
3760 | ||
8325a09d | 3761 | /* And bump the LRU for this access */ |
43566ded CW |
3762 | vma = i915_gem_obj_to_ggtt(obj); |
3763 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
dc8cd1e7 | 3764 | list_move_tail(&vma->mm_list, |
43566ded | 3765 | &to_i915(obj->base.dev)->gtt.base.inactive_list); |
8325a09d | 3766 | |
e47c68e9 EA |
3767 | return 0; |
3768 | } | |
3769 | ||
e4ffd173 CW |
3770 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3771 | enum i915_cache_level cache_level) | |
3772 | { | |
7bddb01f | 3773 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3774 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3775 | int ret; |
3776 | ||
3777 | if (obj->cache_level == cache_level) | |
3778 | return 0; | |
3779 | ||
d7f46fc4 | 3780 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3781 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3782 | return -EBUSY; | |
3783 | } | |
3784 | ||
df6f783a | 3785 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4144f9b5 | 3786 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3787 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3788 | if (ret) |
3789 | return ret; | |
3089c6f2 | 3790 | } |
42d6ab48 CW |
3791 | } |
3792 | ||
3089c6f2 | 3793 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3794 | ret = i915_gem_object_finish_gpu(obj); |
3795 | if (ret) | |
3796 | return ret; | |
3797 | ||
3798 | i915_gem_object_finish_gtt(obj); | |
3799 | ||
3800 | /* Before SandyBridge, you could not use tiling or fence | |
3801 | * registers with snooped memory, so relinquish any fences | |
3802 | * currently pointing to our region in the aperture. | |
3803 | */ | |
42d6ab48 | 3804 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3805 | ret = i915_gem_object_put_fence(obj); |
3806 | if (ret) | |
3807 | return ret; | |
3808 | } | |
3809 | ||
6f65e29a | 3810 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
fe14d5f4 TU |
3811 | if (drm_mm_node_allocated(&vma->node)) { |
3812 | ret = i915_vma_bind(vma, cache_level, | |
3813 | vma->bound & GLOBAL_BIND); | |
3814 | if (ret) | |
3815 | return ret; | |
3816 | } | |
e4ffd173 CW |
3817 | } |
3818 | ||
2c22569b CW |
3819 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3820 | vma->node.color = cache_level; | |
3821 | obj->cache_level = cache_level; | |
3822 | ||
3823 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3824 | u32 old_read_domains, old_write_domain; |
3825 | ||
3826 | /* If we're coming from LLC cached, then we haven't | |
3827 | * actually been tracking whether the data is in the | |
3828 | * CPU cache or not, since we only allow one bit set | |
3829 | * in obj->write_domain and have been skipping the clflushes. | |
3830 | * Just set it to the CPU cache for now. | |
3831 | */ | |
c8725f3d | 3832 | i915_gem_object_retire(obj); |
e4ffd173 | 3833 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e4ffd173 CW |
3834 | |
3835 | old_read_domains = obj->base.read_domains; | |
3836 | old_write_domain = obj->base.write_domain; | |
3837 | ||
3838 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3839 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3840 | ||
3841 | trace_i915_gem_object_change_domain(obj, | |
3842 | old_read_domains, | |
3843 | old_write_domain); | |
3844 | } | |
3845 | ||
e4ffd173 CW |
3846 | return 0; |
3847 | } | |
3848 | ||
199adf40 BW |
3849 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3850 | struct drm_file *file) | |
e6994aee | 3851 | { |
199adf40 | 3852 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3853 | struct drm_i915_gem_object *obj; |
3854 | int ret; | |
3855 | ||
3856 | ret = i915_mutex_lock_interruptible(dev); | |
3857 | if (ret) | |
3858 | return ret; | |
3859 | ||
3860 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3861 | if (&obj->base == NULL) { | |
3862 | ret = -ENOENT; | |
3863 | goto unlock; | |
3864 | } | |
3865 | ||
651d794f CW |
3866 | switch (obj->cache_level) { |
3867 | case I915_CACHE_LLC: | |
3868 | case I915_CACHE_L3_LLC: | |
3869 | args->caching = I915_CACHING_CACHED; | |
3870 | break; | |
3871 | ||
4257d3ba CW |
3872 | case I915_CACHE_WT: |
3873 | args->caching = I915_CACHING_DISPLAY; | |
3874 | break; | |
3875 | ||
651d794f CW |
3876 | default: |
3877 | args->caching = I915_CACHING_NONE; | |
3878 | break; | |
3879 | } | |
e6994aee CW |
3880 | |
3881 | drm_gem_object_unreference(&obj->base); | |
3882 | unlock: | |
3883 | mutex_unlock(&dev->struct_mutex); | |
3884 | return ret; | |
3885 | } | |
3886 | ||
199adf40 BW |
3887 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3888 | struct drm_file *file) | |
e6994aee | 3889 | { |
199adf40 | 3890 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3891 | struct drm_i915_gem_object *obj; |
3892 | enum i915_cache_level level; | |
3893 | int ret; | |
3894 | ||
199adf40 BW |
3895 | switch (args->caching) { |
3896 | case I915_CACHING_NONE: | |
e6994aee CW |
3897 | level = I915_CACHE_NONE; |
3898 | break; | |
199adf40 | 3899 | case I915_CACHING_CACHED: |
e6994aee CW |
3900 | level = I915_CACHE_LLC; |
3901 | break; | |
4257d3ba CW |
3902 | case I915_CACHING_DISPLAY: |
3903 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3904 | break; | |
e6994aee CW |
3905 | default: |
3906 | return -EINVAL; | |
3907 | } | |
3908 | ||
3bc2913e BW |
3909 | ret = i915_mutex_lock_interruptible(dev); |
3910 | if (ret) | |
3911 | return ret; | |
3912 | ||
e6994aee CW |
3913 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3914 | if (&obj->base == NULL) { | |
3915 | ret = -ENOENT; | |
3916 | goto unlock; | |
3917 | } | |
3918 | ||
3919 | ret = i915_gem_object_set_cache_level(obj, level); | |
3920 | ||
3921 | drm_gem_object_unreference(&obj->base); | |
3922 | unlock: | |
3923 | mutex_unlock(&dev->struct_mutex); | |
3924 | return ret; | |
3925 | } | |
3926 | ||
cc98b413 CW |
3927 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3928 | { | |
19656430 OM |
3929 | struct i915_vma *vma; |
3930 | ||
19656430 OM |
3931 | vma = i915_gem_obj_to_ggtt(obj); |
3932 | if (!vma) | |
3933 | return false; | |
3934 | ||
4feb7659 | 3935 | /* There are 2 sources that pin objects: |
cc98b413 CW |
3936 | * 1. The display engine (scanouts, sprites, cursors); |
3937 | * 2. Reservations for execbuffer; | |
cc98b413 CW |
3938 | * |
3939 | * We can ignore reservations as we hold the struct_mutex and | |
4feb7659 | 3940 | * are only called outside of the reservation path. |
cc98b413 | 3941 | */ |
4feb7659 | 3942 | return vma->pin_count; |
cc98b413 CW |
3943 | } |
3944 | ||
b9241ea3 | 3945 | /* |
2da3b9b9 CW |
3946 | * Prepare buffer for display plane (scanout, cursors, etc). |
3947 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3948 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3949 | */ |
3950 | int | |
2da3b9b9 CW |
3951 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3952 | u32 alignment, | |
a4872ba6 | 3953 | struct intel_engine_cs *pipelined) |
b9241ea3 | 3954 | { |
2da3b9b9 | 3955 | u32 old_read_domains, old_write_domain; |
19656430 | 3956 | bool was_pin_display; |
b9241ea3 ZW |
3957 | int ret; |
3958 | ||
41c52415 | 3959 | if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) { |
2911a35b BW |
3960 | ret = i915_gem_object_sync(obj, pipelined); |
3961 | if (ret) | |
b9241ea3 ZW |
3962 | return ret; |
3963 | } | |
3964 | ||
cc98b413 CW |
3965 | /* Mark the pin_display early so that we account for the |
3966 | * display coherency whilst setting up the cache domains. | |
3967 | */ | |
19656430 | 3968 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3969 | obj->pin_display = true; |
3970 | ||
a7ef0640 EA |
3971 | /* The display engine is not coherent with the LLC cache on gen6. As |
3972 | * a result, we make sure that the pinning that is about to occur is | |
3973 | * done with uncached PTEs. This is lowest common denominator for all | |
3974 | * chipsets. | |
3975 | * | |
3976 | * However for gen6+, we could do better by using the GFDT bit instead | |
3977 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3978 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3979 | */ | |
651d794f CW |
3980 | ret = i915_gem_object_set_cache_level(obj, |
3981 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3982 | if (ret) |
cc98b413 | 3983 | goto err_unpin_display; |
a7ef0640 | 3984 | |
2da3b9b9 CW |
3985 | /* As the user may map the buffer once pinned in the display plane |
3986 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3987 | * always use map_and_fenceable for all scanout buffers. | |
3988 | */ | |
1ec9e26d | 3989 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3990 | if (ret) |
cc98b413 | 3991 | goto err_unpin_display; |
2da3b9b9 | 3992 | |
2c22569b | 3993 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3994 | |
2da3b9b9 | 3995 | old_write_domain = obj->base.write_domain; |
05394f39 | 3996 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3997 | |
3998 | /* It should now be out of any other write domains, and we can update | |
3999 | * the domain values for our changes. | |
4000 | */ | |
e5f1d962 | 4001 | obj->base.write_domain = 0; |
05394f39 | 4002 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
4003 | |
4004 | trace_i915_gem_object_change_domain(obj, | |
4005 | old_read_domains, | |
2da3b9b9 | 4006 | old_write_domain); |
b9241ea3 ZW |
4007 | |
4008 | return 0; | |
cc98b413 CW |
4009 | |
4010 | err_unpin_display: | |
19656430 OM |
4011 | WARN_ON(was_pin_display != is_pin_display(obj)); |
4012 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
4013 | return ret; |
4014 | } | |
4015 | ||
4016 | void | |
4017 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
4018 | { | |
d7f46fc4 | 4019 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 4020 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
4021 | } |
4022 | ||
85345517 | 4023 | int |
a8198eea | 4024 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 4025 | { |
88241785 CW |
4026 | int ret; |
4027 | ||
a8198eea | 4028 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
4029 | return 0; |
4030 | ||
0201f1ec | 4031 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
4032 | if (ret) |
4033 | return ret; | |
4034 | ||
a8198eea CW |
4035 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
4036 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 4037 | return 0; |
85345517 CW |
4038 | } |
4039 | ||
e47c68e9 EA |
4040 | /** |
4041 | * Moves a single object to the CPU read, and possibly write domain. | |
4042 | * | |
4043 | * This function returns when the move is complete, including waiting on | |
4044 | * flushes to occur. | |
4045 | */ | |
dabdfe02 | 4046 | int |
919926ae | 4047 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4048 | { |
1c5d22f7 | 4049 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4050 | int ret; |
4051 | ||
8d7e3de1 CW |
4052 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4053 | return 0; | |
4054 | ||
0201f1ec | 4055 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4056 | if (ret) |
4057 | return ret; | |
4058 | ||
c8725f3d | 4059 | i915_gem_object_retire(obj); |
e47c68e9 | 4060 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4061 | |
05394f39 CW |
4062 | old_write_domain = obj->base.write_domain; |
4063 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4064 | |
e47c68e9 | 4065 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4066 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4067 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4068 | |
05394f39 | 4069 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4070 | } |
4071 | ||
4072 | /* It should now be out of any other write domains, and we can update | |
4073 | * the domain values for our changes. | |
4074 | */ | |
05394f39 | 4075 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4076 | |
4077 | /* If we're writing through the CPU, then the GPU read domains will | |
4078 | * need to be invalidated at next use. | |
4079 | */ | |
4080 | if (write) { | |
05394f39 CW |
4081 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4082 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4083 | } |
2ef7eeaa | 4084 | |
f99d7069 DV |
4085 | if (write) |
4086 | intel_fb_obj_invalidate(obj, NULL); | |
4087 | ||
1c5d22f7 CW |
4088 | trace_i915_gem_object_change_domain(obj, |
4089 | old_read_domains, | |
4090 | old_write_domain); | |
4091 | ||
2ef7eeaa EA |
4092 | return 0; |
4093 | } | |
4094 | ||
673a394b EA |
4095 | /* Throttle our rendering by waiting until the ring has completed our requests |
4096 | * emitted over 20 msec ago. | |
4097 | * | |
b962442e EA |
4098 | * Note that if we were to use the current jiffies each time around the loop, |
4099 | * we wouldn't escape the function with any frames outstanding if the time to | |
4100 | * render a frame was over 20ms. | |
4101 | * | |
673a394b EA |
4102 | * This should get us reasonable parallelism between CPU and GPU but also |
4103 | * relatively low latency when blocking on a particular request to finish. | |
4104 | */ | |
40a5f0de | 4105 | static int |
f787a5f5 | 4106 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4107 | { |
f787a5f5 CW |
4108 | struct drm_i915_private *dev_priv = dev->dev_private; |
4109 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 4110 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
54fb2411 | 4111 | struct drm_i915_gem_request *request, *target = NULL; |
f69061be | 4112 | unsigned reset_counter; |
f787a5f5 | 4113 | int ret; |
93533c29 | 4114 | |
308887aa DV |
4115 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4116 | if (ret) | |
4117 | return ret; | |
4118 | ||
4119 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4120 | if (ret) | |
4121 | return ret; | |
e110e8d6 | 4122 | |
1c25595f | 4123 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4124 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4125 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4126 | break; | |
40a5f0de | 4127 | |
54fb2411 | 4128 | target = request; |
b962442e | 4129 | } |
f69061be | 4130 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 JH |
4131 | if (target) |
4132 | i915_gem_request_reference(target); | |
1c25595f | 4133 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4134 | |
54fb2411 | 4135 | if (target == NULL) |
f787a5f5 | 4136 | return 0; |
2bc43b5c | 4137 | |
9c654818 | 4138 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4139 | if (ret == 0) |
4140 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4141 | |
ff865885 JH |
4142 | mutex_lock(&dev->struct_mutex); |
4143 | i915_gem_request_unreference(target); | |
4144 | mutex_unlock(&dev->struct_mutex); | |
4145 | ||
40a5f0de EA |
4146 | return ret; |
4147 | } | |
4148 | ||
d23db88c CW |
4149 | static bool |
4150 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4151 | { | |
4152 | struct drm_i915_gem_object *obj = vma->obj; | |
4153 | ||
4154 | if (alignment && | |
4155 | vma->node.start & (alignment - 1)) | |
4156 | return true; | |
4157 | ||
4158 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4159 | return true; | |
4160 | ||
4161 | if (flags & PIN_OFFSET_BIAS && | |
4162 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4163 | return true; | |
4164 | ||
4165 | return false; | |
4166 | } | |
4167 | ||
673a394b | 4168 | int |
fe14d5f4 TU |
4169 | i915_gem_object_pin_view(struct drm_i915_gem_object *obj, |
4170 | struct i915_address_space *vm, | |
4171 | uint32_t alignment, | |
4172 | uint64_t flags, | |
4173 | const struct i915_ggtt_view *view) | |
673a394b | 4174 | { |
6e7186af | 4175 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4176 | struct i915_vma *vma; |
ef79e17c | 4177 | unsigned bound; |
673a394b EA |
4178 | int ret; |
4179 | ||
6e7186af BW |
4180 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4181 | return -ENODEV; | |
4182 | ||
bf3d149b | 4183 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4184 | return -EINVAL; |
07fe0b12 | 4185 | |
c826c449 CW |
4186 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4187 | return -EINVAL; | |
4188 | ||
fe14d5f4 | 4189 | vma = i915_gem_obj_to_vma_view(obj, vm, view); |
07fe0b12 | 4190 | if (vma) { |
d7f46fc4 BW |
4191 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4192 | return -EBUSY; | |
4193 | ||
d23db88c | 4194 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4195 | WARN(vma->pin_count, |
ae7d49d8 | 4196 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 4197 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4198 | " obj->map_and_fenceable=%d\n", |
fe14d5f4 TU |
4199 | i915_gem_obj_offset_view(obj, vm, view->type), |
4200 | alignment, | |
d23db88c | 4201 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4202 | obj->map_and_fenceable); |
07fe0b12 | 4203 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4204 | if (ret) |
4205 | return ret; | |
8ea99c92 DV |
4206 | |
4207 | vma = NULL; | |
ac0c6b5a CW |
4208 | } |
4209 | } | |
4210 | ||
ef79e17c | 4211 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4212 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
fe14d5f4 TU |
4213 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, |
4214 | flags, view); | |
262de145 DV |
4215 | if (IS_ERR(vma)) |
4216 | return PTR_ERR(vma); | |
22c344e9 | 4217 | } |
76446cac | 4218 | |
fe14d5f4 TU |
4219 | if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) { |
4220 | ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND); | |
4221 | if (ret) | |
4222 | return ret; | |
4223 | } | |
74898d7e | 4224 | |
ef79e17c CW |
4225 | if ((bound ^ vma->bound) & GLOBAL_BIND) { |
4226 | bool mappable, fenceable; | |
4227 | u32 fence_size, fence_alignment; | |
4228 | ||
4229 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4230 | obj->base.size, | |
4231 | obj->tiling_mode); | |
4232 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4233 | obj->base.size, | |
4234 | obj->tiling_mode, | |
4235 | true); | |
4236 | ||
4237 | fenceable = (vma->node.size == fence_size && | |
4238 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4239 | ||
4240 | mappable = (vma->node.start + obj->base.size <= | |
4241 | dev_priv->gtt.mappable_end); | |
4242 | ||
4243 | obj->map_and_fenceable = mappable && fenceable; | |
4244 | } | |
4245 | ||
4246 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); | |
4247 | ||
8ea99c92 | 4248 | vma->pin_count++; |
1ec9e26d DV |
4249 | if (flags & PIN_MAPPABLE) |
4250 | obj->pin_mappable |= true; | |
673a394b EA |
4251 | |
4252 | return 0; | |
4253 | } | |
4254 | ||
4255 | void | |
d7f46fc4 | 4256 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4257 | { |
d7f46fc4 | 4258 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 4259 | |
d7f46fc4 BW |
4260 | BUG_ON(!vma); |
4261 | BUG_ON(vma->pin_count == 0); | |
4262 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
4263 | ||
4264 | if (--vma->pin_count == 0) | |
6299f992 | 4265 | obj->pin_mappable = false; |
673a394b EA |
4266 | } |
4267 | ||
d8ffa60b DV |
4268 | bool |
4269 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4270 | { | |
4271 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4272 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4273 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4274 | ||
4275 | WARN_ON(!ggtt_vma || | |
4276 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4277 | ggtt_vma->pin_count); | |
4278 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4279 | return true; | |
4280 | } else | |
4281 | return false; | |
4282 | } | |
4283 | ||
4284 | void | |
4285 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4286 | { | |
4287 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4288 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4289 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4290 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4291 | } | |
4292 | } | |
4293 | ||
673a394b EA |
4294 | int |
4295 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4296 | struct drm_file *file) |
673a394b EA |
4297 | { |
4298 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4299 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4300 | int ret; |
4301 | ||
76c1dec1 | 4302 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4303 | if (ret) |
76c1dec1 | 4304 | return ret; |
673a394b | 4305 | |
05394f39 | 4306 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4307 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4308 | ret = -ENOENT; |
4309 | goto unlock; | |
673a394b | 4310 | } |
d1b851fc | 4311 | |
0be555b6 CW |
4312 | /* Count all active objects as busy, even if they are currently not used |
4313 | * by the gpu. Users of this interface expect objects to eventually | |
4314 | * become non-busy without any further actions, therefore emit any | |
4315 | * necessary flushes here. | |
c4de0a5d | 4316 | */ |
30dfebf3 | 4317 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4318 | |
30dfebf3 | 4319 | args->busy = obj->active; |
41c52415 JH |
4320 | if (obj->last_read_req) { |
4321 | struct intel_engine_cs *ring; | |
e9808edd | 4322 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
41c52415 JH |
4323 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4324 | args->busy |= intel_ring_flag(ring) << 16; | |
e9808edd | 4325 | } |
673a394b | 4326 | |
05394f39 | 4327 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4328 | unlock: |
673a394b | 4329 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4330 | return ret; |
673a394b EA |
4331 | } |
4332 | ||
4333 | int | |
4334 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4335 | struct drm_file *file_priv) | |
4336 | { | |
0206e353 | 4337 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4338 | } |
4339 | ||
3ef94daa CW |
4340 | int |
4341 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4342 | struct drm_file *file_priv) | |
4343 | { | |
656bfa3a | 4344 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4345 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4346 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4347 | int ret; |
3ef94daa CW |
4348 | |
4349 | switch (args->madv) { | |
4350 | case I915_MADV_DONTNEED: | |
4351 | case I915_MADV_WILLNEED: | |
4352 | break; | |
4353 | default: | |
4354 | return -EINVAL; | |
4355 | } | |
4356 | ||
1d7cfea1 CW |
4357 | ret = i915_mutex_lock_interruptible(dev); |
4358 | if (ret) | |
4359 | return ret; | |
4360 | ||
05394f39 | 4361 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4362 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4363 | ret = -ENOENT; |
4364 | goto unlock; | |
3ef94daa | 4365 | } |
3ef94daa | 4366 | |
d7f46fc4 | 4367 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4368 | ret = -EINVAL; |
4369 | goto out; | |
3ef94daa CW |
4370 | } |
4371 | ||
656bfa3a DV |
4372 | if (obj->pages && |
4373 | obj->tiling_mode != I915_TILING_NONE && | |
4374 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4375 | if (obj->madv == I915_MADV_WILLNEED) | |
4376 | i915_gem_object_unpin_pages(obj); | |
4377 | if (args->madv == I915_MADV_WILLNEED) | |
4378 | i915_gem_object_pin_pages(obj); | |
4379 | } | |
4380 | ||
05394f39 CW |
4381 | if (obj->madv != __I915_MADV_PURGED) |
4382 | obj->madv = args->madv; | |
3ef94daa | 4383 | |
6c085a72 CW |
4384 | /* if the object is no longer attached, discard its backing storage */ |
4385 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4386 | i915_gem_object_truncate(obj); |
4387 | ||
05394f39 | 4388 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4389 | |
1d7cfea1 | 4390 | out: |
05394f39 | 4391 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4392 | unlock: |
3ef94daa | 4393 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4394 | return ret; |
3ef94daa CW |
4395 | } |
4396 | ||
37e680a1 CW |
4397 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4398 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4399 | { |
35c20a60 | 4400 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4401 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4402 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4403 | INIT_LIST_HEAD(&obj->vma_list); |
493018dc | 4404 | INIT_LIST_HEAD(&obj->batch_pool_list); |
0327d6ba | 4405 | |
37e680a1 CW |
4406 | obj->ops = ops; |
4407 | ||
0327d6ba CW |
4408 | obj->fence_reg = I915_FENCE_REG_NONE; |
4409 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4410 | |
4411 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4412 | } | |
4413 | ||
37e680a1 CW |
4414 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4415 | .get_pages = i915_gem_object_get_pages_gtt, | |
4416 | .put_pages = i915_gem_object_put_pages_gtt, | |
4417 | }; | |
4418 | ||
05394f39 CW |
4419 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4420 | size_t size) | |
ac52bc56 | 4421 | { |
c397b908 | 4422 | struct drm_i915_gem_object *obj; |
5949eac4 | 4423 | struct address_space *mapping; |
1a240d4d | 4424 | gfp_t mask; |
ac52bc56 | 4425 | |
42dcedd4 | 4426 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4427 | if (obj == NULL) |
4428 | return NULL; | |
673a394b | 4429 | |
c397b908 | 4430 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4431 | i915_gem_object_free(obj); |
c397b908 DV |
4432 | return NULL; |
4433 | } | |
673a394b | 4434 | |
bed1ea95 CW |
4435 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4436 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4437 | /* 965gm cannot relocate objects above 4GiB. */ | |
4438 | mask &= ~__GFP_HIGHMEM; | |
4439 | mask |= __GFP_DMA32; | |
4440 | } | |
4441 | ||
496ad9aa | 4442 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4443 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4444 | |
37e680a1 | 4445 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4446 | |
c397b908 DV |
4447 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4448 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4449 | |
3d29b842 ED |
4450 | if (HAS_LLC(dev)) { |
4451 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4452 | * cache) for about a 10% performance improvement |
4453 | * compared to uncached. Graphics requests other than | |
4454 | * display scanout are coherent with the CPU in | |
4455 | * accessing this cache. This means in this mode we | |
4456 | * don't need to clflush on the CPU side, and on the | |
4457 | * GPU side we only need to flush internal caches to | |
4458 | * get data visible to the CPU. | |
4459 | * | |
4460 | * However, we maintain the display planes as UC, and so | |
4461 | * need to rebind when first used as such. | |
4462 | */ | |
4463 | obj->cache_level = I915_CACHE_LLC; | |
4464 | } else | |
4465 | obj->cache_level = I915_CACHE_NONE; | |
4466 | ||
d861e338 DV |
4467 | trace_i915_gem_object_create(obj); |
4468 | ||
05394f39 | 4469 | return obj; |
c397b908 DV |
4470 | } |
4471 | ||
340fbd8c CW |
4472 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4473 | { | |
4474 | /* If we are the last user of the backing storage (be it shmemfs | |
4475 | * pages or stolen etc), we know that the pages are going to be | |
4476 | * immediately released. In this case, we can then skip copying | |
4477 | * back the contents from the GPU. | |
4478 | */ | |
4479 | ||
4480 | if (obj->madv != I915_MADV_WILLNEED) | |
4481 | return false; | |
4482 | ||
4483 | if (obj->base.filp == NULL) | |
4484 | return true; | |
4485 | ||
4486 | /* At first glance, this looks racy, but then again so would be | |
4487 | * userspace racing mmap against close. However, the first external | |
4488 | * reference to the filp can only be obtained through the | |
4489 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4490 | * acquiring such a reference whilst we are in the middle of | |
4491 | * freeing the object. | |
4492 | */ | |
4493 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4494 | } | |
4495 | ||
1488fc08 | 4496 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4497 | { |
1488fc08 | 4498 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4499 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4500 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4501 | struct i915_vma *vma, *next; |
673a394b | 4502 | |
f65c9168 PZ |
4503 | intel_runtime_pm_get(dev_priv); |
4504 | ||
26e12f89 CW |
4505 | trace_i915_gem_object_destroy(obj); |
4506 | ||
07fe0b12 | 4507 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4508 | int ret; |
4509 | ||
4510 | vma->pin_count = 0; | |
4511 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4512 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4513 | bool was_interruptible; | |
1488fc08 | 4514 | |
07fe0b12 BW |
4515 | was_interruptible = dev_priv->mm.interruptible; |
4516 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4517 | |
07fe0b12 | 4518 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4519 | |
07fe0b12 BW |
4520 | dev_priv->mm.interruptible = was_interruptible; |
4521 | } | |
1488fc08 CW |
4522 | } |
4523 | ||
1d64ae71 BW |
4524 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4525 | * before progressing. */ | |
4526 | if (obj->stolen) | |
4527 | i915_gem_object_unpin_pages(obj); | |
4528 | ||
a071fa00 DV |
4529 | WARN_ON(obj->frontbuffer_bits); |
4530 | ||
656bfa3a DV |
4531 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4532 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4533 | obj->tiling_mode != I915_TILING_NONE) | |
4534 | i915_gem_object_unpin_pages(obj); | |
4535 | ||
401c29f6 BW |
4536 | if (WARN_ON(obj->pages_pin_count)) |
4537 | obj->pages_pin_count = 0; | |
340fbd8c | 4538 | if (discard_backing_storage(obj)) |
5537252b | 4539 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4540 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4541 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4542 | |
9da3da66 CW |
4543 | BUG_ON(obj->pages); |
4544 | ||
2f745ad3 CW |
4545 | if (obj->base.import_attach) |
4546 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4547 | |
5cc9ed4b CW |
4548 | if (obj->ops->release) |
4549 | obj->ops->release(obj); | |
4550 | ||
05394f39 CW |
4551 | drm_gem_object_release(&obj->base); |
4552 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4553 | |
05394f39 | 4554 | kfree(obj->bit_17); |
42dcedd4 | 4555 | i915_gem_object_free(obj); |
f65c9168 PZ |
4556 | |
4557 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4558 | } |
4559 | ||
fe14d5f4 TU |
4560 | struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj, |
4561 | struct i915_address_space *vm, | |
4562 | const struct i915_ggtt_view *view) | |
e656a6cb DV |
4563 | { |
4564 | struct i915_vma *vma; | |
4565 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
fe14d5f4 | 4566 | if (vma->vm == vm && vma->ggtt_view.type == view->type) |
e656a6cb DV |
4567 | return vma; |
4568 | ||
4569 | return NULL; | |
4570 | } | |
4571 | ||
2f633156 BW |
4572 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4573 | { | |
b9d06dd9 | 4574 | struct i915_address_space *vm = NULL; |
2f633156 | 4575 | WARN_ON(vma->node.allocated); |
aaa05667 CW |
4576 | |
4577 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4578 | if (!list_empty(&vma->exec_list)) | |
4579 | return; | |
4580 | ||
b9d06dd9 | 4581 | vm = vma->vm; |
b9d06dd9 | 4582 | |
841cd773 DV |
4583 | if (!i915_is_ggtt(vm)) |
4584 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 4585 | |
8b9c2b94 | 4586 | list_del(&vma->vma_link); |
b93dab6e | 4587 | |
2f633156 BW |
4588 | kfree(vma); |
4589 | } | |
4590 | ||
e3efda49 CW |
4591 | static void |
4592 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4593 | { | |
4594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4595 | struct intel_engine_cs *ring; |
e3efda49 CW |
4596 | int i; |
4597 | ||
4598 | for_each_ring(ring, dev_priv, i) | |
a83014d3 | 4599 | dev_priv->gt.stop_ring(ring); |
e3efda49 CW |
4600 | } |
4601 | ||
29105ccc | 4602 | int |
45c5f202 | 4603 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4604 | { |
3e31c6c0 | 4605 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4606 | int ret = 0; |
28dfe52a | 4607 | |
45c5f202 | 4608 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4609 | ret = i915_gpu_idle(dev); |
f7403347 | 4610 | if (ret) |
45c5f202 | 4611 | goto err; |
f7403347 | 4612 | |
b2da9fe5 | 4613 | i915_gem_retire_requests(dev); |
673a394b | 4614 | |
29105ccc | 4615 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4616 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4617 | i915_gem_evict_everything(dev); |
29105ccc | 4618 | |
e3efda49 | 4619 | i915_gem_stop_ringbuffers(dev); |
45c5f202 CW |
4620 | mutex_unlock(&dev->struct_mutex); |
4621 | ||
4622 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4623 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4624 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4625 | |
bdcf120b CW |
4626 | /* Assert that we sucessfully flushed all the work and |
4627 | * reset the GPU back to its idle, low power state. | |
4628 | */ | |
4629 | WARN_ON(dev_priv->mm.busy); | |
4630 | ||
673a394b | 4631 | return 0; |
45c5f202 CW |
4632 | |
4633 | err: | |
4634 | mutex_unlock(&dev->struct_mutex); | |
4635 | return ret; | |
673a394b EA |
4636 | } |
4637 | ||
a4872ba6 | 4638 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4639 | { |
c3787e2e | 4640 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4641 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4642 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4643 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4644 | int i, ret; |
b9524a1e | 4645 | |
040d2baa | 4646 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4647 | return 0; |
b9524a1e | 4648 | |
c3787e2e BW |
4649 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4650 | if (ret) | |
4651 | return ret; | |
b9524a1e | 4652 | |
c3787e2e BW |
4653 | /* |
4654 | * Note: We do not worry about the concurrent register cacheline hang | |
4655 | * here because no other code should access these registers other than | |
4656 | * at initialization time. | |
4657 | */ | |
b9524a1e | 4658 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4659 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4660 | intel_ring_emit(ring, reg_base + i); | |
4661 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4662 | } |
4663 | ||
c3787e2e | 4664 | intel_ring_advance(ring); |
b9524a1e | 4665 | |
c3787e2e | 4666 | return ret; |
b9524a1e BW |
4667 | } |
4668 | ||
f691e2f4 DV |
4669 | void i915_gem_init_swizzling(struct drm_device *dev) |
4670 | { | |
3e31c6c0 | 4671 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4672 | |
11782b02 | 4673 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4674 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4675 | return; | |
4676 | ||
4677 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4678 | DISP_TILE_SURFACE_SWIZZLING); | |
4679 | ||
11782b02 DV |
4680 | if (IS_GEN5(dev)) |
4681 | return; | |
4682 | ||
f691e2f4 DV |
4683 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4684 | if (IS_GEN6(dev)) | |
6b26c86d | 4685 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4686 | else if (IS_GEN7(dev)) |
6b26c86d | 4687 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4688 | else if (IS_GEN8(dev)) |
4689 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4690 | else |
4691 | BUG(); | |
f691e2f4 | 4692 | } |
e21af88d | 4693 | |
67b1b571 CW |
4694 | static bool |
4695 | intel_enable_blt(struct drm_device *dev) | |
4696 | { | |
4697 | if (!HAS_BLT(dev)) | |
4698 | return false; | |
4699 | ||
4700 | /* The blitter was dysfunctional on early prototypes */ | |
4701 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4702 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4703 | " graphics performance will be degraded.\n"); | |
4704 | return false; | |
4705 | } | |
4706 | ||
4707 | return true; | |
4708 | } | |
4709 | ||
81e7f200 VS |
4710 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4711 | { | |
4712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4713 | ||
4714 | I915_WRITE(RING_CTL(base), 0); | |
4715 | I915_WRITE(RING_HEAD(base), 0); | |
4716 | I915_WRITE(RING_TAIL(base), 0); | |
4717 | I915_WRITE(RING_START(base), 0); | |
4718 | } | |
4719 | ||
4720 | static void init_unused_rings(struct drm_device *dev) | |
4721 | { | |
4722 | if (IS_I830(dev)) { | |
4723 | init_unused_ring(dev, PRB1_BASE); | |
4724 | init_unused_ring(dev, SRB0_BASE); | |
4725 | init_unused_ring(dev, SRB1_BASE); | |
4726 | init_unused_ring(dev, SRB2_BASE); | |
4727 | init_unused_ring(dev, SRB3_BASE); | |
4728 | } else if (IS_GEN2(dev)) { | |
4729 | init_unused_ring(dev, SRB0_BASE); | |
4730 | init_unused_ring(dev, SRB1_BASE); | |
4731 | } else if (IS_GEN3(dev)) { | |
4732 | init_unused_ring(dev, PRB1_BASE); | |
4733 | init_unused_ring(dev, PRB2_BASE); | |
4734 | } | |
4735 | } | |
4736 | ||
a83014d3 | 4737 | int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4738 | { |
4fc7c971 | 4739 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4740 | int ret; |
68f95ba9 | 4741 | |
5c1143bb | 4742 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4743 | if (ret) |
b6913e4b | 4744 | return ret; |
68f95ba9 CW |
4745 | |
4746 | if (HAS_BSD(dev)) { | |
5c1143bb | 4747 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4748 | if (ret) |
4749 | goto cleanup_render_ring; | |
d1b851fc | 4750 | } |
68f95ba9 | 4751 | |
67b1b571 | 4752 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4753 | ret = intel_init_blt_ring_buffer(dev); |
4754 | if (ret) | |
4755 | goto cleanup_bsd_ring; | |
4756 | } | |
4757 | ||
9a8a2213 BW |
4758 | if (HAS_VEBOX(dev)) { |
4759 | ret = intel_init_vebox_ring_buffer(dev); | |
4760 | if (ret) | |
4761 | goto cleanup_blt_ring; | |
4762 | } | |
4763 | ||
845f74a7 ZY |
4764 | if (HAS_BSD2(dev)) { |
4765 | ret = intel_init_bsd2_ring_buffer(dev); | |
4766 | if (ret) | |
4767 | goto cleanup_vebox_ring; | |
4768 | } | |
9a8a2213 | 4769 | |
99433931 | 4770 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4771 | if (ret) |
845f74a7 | 4772 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4773 | |
4774 | return 0; | |
4775 | ||
845f74a7 ZY |
4776 | cleanup_bsd2_ring: |
4777 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4778 | cleanup_vebox_ring: |
4779 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4780 | cleanup_blt_ring: |
4781 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4782 | cleanup_bsd_ring: | |
4783 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4784 | cleanup_render_ring: | |
4785 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4786 | ||
4787 | return ret; | |
4788 | } | |
4789 | ||
4790 | int | |
4791 | i915_gem_init_hw(struct drm_device *dev) | |
4792 | { | |
3e31c6c0 | 4793 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a57ffb | 4794 | struct intel_engine_cs *ring; |
35a85ac6 | 4795 | int ret, i; |
4fc7c971 BW |
4796 | |
4797 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4798 | return -EIO; | |
4799 | ||
59124506 | 4800 | if (dev_priv->ellc_size) |
05e21cc4 | 4801 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4802 | |
0bf21347 VS |
4803 | if (IS_HASWELL(dev)) |
4804 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4805 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4806 | |
88a2b2a3 | 4807 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4808 | if (IS_IVYBRIDGE(dev)) { |
4809 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4810 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4811 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4812 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4813 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4814 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4815 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4816 | } | |
88a2b2a3 BW |
4817 | } |
4818 | ||
4fc7c971 BW |
4819 | i915_gem_init_swizzling(dev); |
4820 | ||
d5abdfda DV |
4821 | /* |
4822 | * At least 830 can leave some of the unused rings | |
4823 | * "active" (ie. head != tail) after resume which | |
4824 | * will prevent c3 entry. Makes sure all unused rings | |
4825 | * are totally idle. | |
4826 | */ | |
4827 | init_unused_rings(dev); | |
4828 | ||
35a57ffb DV |
4829 | for_each_ring(ring, dev_priv, i) { |
4830 | ret = ring->init_hw(ring); | |
4831 | if (ret) | |
4832 | return ret; | |
4833 | } | |
99433931 | 4834 | |
c3787e2e BW |
4835 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4836 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4837 | ||
254f965c | 4838 | /* |
2fa48d8d BW |
4839 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4840 | * default context switch however is something we'd like to do after | |
4841 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4842 | * goes with our code better). Context switching requires rings (for | |
4843 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4844 | */ |
2fa48d8d | 4845 | ret = i915_gem_context_enable(dev_priv); |
60990320 | 4846 | if (ret && ret != -EIO) { |
2fa48d8d | 4847 | DRM_ERROR("Context enable failed %d\n", ret); |
60990320 | 4848 | i915_gem_cleanup_ringbuffer(dev); |
82460d97 DV |
4849 | |
4850 | return ret; | |
4851 | } | |
4852 | ||
4853 | ret = i915_ppgtt_init_hw(dev); | |
4854 | if (ret && ret != -EIO) { | |
4855 | DRM_ERROR("PPGTT enable failed %d\n", ret); | |
4856 | i915_gem_cleanup_ringbuffer(dev); | |
b7c36d25 | 4857 | } |
e21af88d | 4858 | |
2fa48d8d | 4859 | return ret; |
8187a2b7 ZN |
4860 | } |
4861 | ||
1070a42b CW |
4862 | int i915_gem_init(struct drm_device *dev) |
4863 | { | |
4864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4865 | int ret; |
4866 | ||
127f1003 OM |
4867 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4868 | i915.enable_execlists); | |
4869 | ||
1070a42b | 4870 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4871 | |
4872 | if (IS_VALLEYVIEW(dev)) { | |
4873 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4874 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4875 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4876 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4877 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4878 | } | |
4879 | ||
a83014d3 OM |
4880 | if (!i915.enable_execlists) { |
4881 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; | |
4882 | dev_priv->gt.init_rings = i915_gem_init_rings; | |
4883 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
4884 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
454afebd OM |
4885 | } else { |
4886 | dev_priv->gt.do_execbuf = intel_execlists_submission; | |
4887 | dev_priv->gt.init_rings = intel_logical_rings_init; | |
4888 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
4889 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
a83014d3 OM |
4890 | } |
4891 | ||
6c5566a8 | 4892 | ret = i915_gem_init_userptr(dev); |
7bcc3777 JN |
4893 | if (ret) |
4894 | goto out_unlock; | |
6c5566a8 | 4895 | |
d7e5008f | 4896 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4897 | |
2fa48d8d | 4898 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4899 | if (ret) |
4900 | goto out_unlock; | |
2fa48d8d | 4901 | |
35a57ffb DV |
4902 | ret = dev_priv->gt.init_rings(dev); |
4903 | if (ret) | |
7bcc3777 | 4904 | goto out_unlock; |
2fa48d8d | 4905 | |
1070a42b | 4906 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4907 | if (ret == -EIO) { |
4908 | /* Allow ring initialisation to fail by marking the GPU as | |
4909 | * wedged. But we only want to do this where the GPU is angry, | |
4910 | * for all other failure, such as an allocation failure, bail. | |
4911 | */ | |
4912 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4913 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4914 | ret = 0; | |
1070a42b | 4915 | } |
7bcc3777 JN |
4916 | |
4917 | out_unlock: | |
60990320 | 4918 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4919 | |
60990320 | 4920 | return ret; |
1070a42b CW |
4921 | } |
4922 | ||
8187a2b7 ZN |
4923 | void |
4924 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4925 | { | |
3e31c6c0 | 4926 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4927 | struct intel_engine_cs *ring; |
1ec14ad3 | 4928 | int i; |
8187a2b7 | 4929 | |
b4519513 | 4930 | for_each_ring(ring, dev_priv, i) |
a83014d3 | 4931 | dev_priv->gt.cleanup_ring(ring); |
8187a2b7 ZN |
4932 | } |
4933 | ||
64193406 | 4934 | static void |
a4872ba6 | 4935 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4936 | { |
4937 | INIT_LIST_HEAD(&ring->active_list); | |
4938 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4939 | } |
4940 | ||
7e0d96bc BW |
4941 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4942 | struct i915_address_space *vm) | |
fc8c067e | 4943 | { |
7e0d96bc BW |
4944 | if (!i915_is_ggtt(vm)) |
4945 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4946 | vm->dev = dev_priv->dev; |
4947 | INIT_LIST_HEAD(&vm->active_list); | |
4948 | INIT_LIST_HEAD(&vm->inactive_list); | |
4949 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4950 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4951 | } |
4952 | ||
673a394b EA |
4953 | void |
4954 | i915_gem_load(struct drm_device *dev) | |
4955 | { | |
3e31c6c0 | 4956 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4957 | int i; |
4958 | ||
4959 | dev_priv->slab = | |
4960 | kmem_cache_create("i915_gem_object", | |
4961 | sizeof(struct drm_i915_gem_object), 0, | |
4962 | SLAB_HWCACHE_ALIGN, | |
4963 | NULL); | |
673a394b | 4964 | |
fc8c067e BW |
4965 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4966 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4967 | ||
a33afea5 | 4968 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4969 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4970 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4971 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4972 | for (i = 0; i < I915_NUM_RINGS; i++) |
4973 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4974 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4975 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4976 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4977 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4978 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4979 | i915_gem_idle_work_handler); | |
1f83fee0 | 4980 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4981 | |
94400120 | 4982 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
dbb42748 | 4983 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
50743298 DV |
4984 | I915_WRITE(MI_ARB_STATE, |
4985 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4986 | } |
4987 | ||
72bfa19c CW |
4988 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4989 | ||
de151cf6 | 4990 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4991 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4992 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4993 | |
42b5aeab VS |
4994 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4995 | dev_priv->num_fence_regs = 32; | |
4996 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4997 | dev_priv->num_fence_regs = 16; |
4998 | else | |
4999 | dev_priv->num_fence_regs = 8; | |
5000 | ||
b5aa8a0f | 5001 | /* Initialize fence registers to zero */ |
19b2dbde CW |
5002 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
5003 | i915_gem_restore_fences(dev); | |
10ed13e4 | 5004 | |
673a394b | 5005 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 5006 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 5007 | |
ce453d81 CW |
5008 | dev_priv->mm.interruptible = true; |
5009 | ||
ceabbba5 CW |
5010 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
5011 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
5012 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
5013 | register_shrinker(&dev_priv->mm.shrinker); | |
2cfcd32a CW |
5014 | |
5015 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; | |
5016 | register_oom_notifier(&dev_priv->mm.oom_notifier); | |
f99d7069 | 5017 | |
78a42377 BV |
5018 | i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool); |
5019 | ||
f99d7069 | 5020 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 5021 | } |
71acb5eb | 5022 | |
f787a5f5 | 5023 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5024 | { |
f787a5f5 | 5025 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 5026 | |
b29c19b6 CW |
5027 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
5028 | ||
b962442e EA |
5029 | /* Clean up our request list when the client is going away, so that |
5030 | * later retire_requests won't dereference our soon-to-be-gone | |
5031 | * file_priv. | |
5032 | */ | |
1c25595f | 5033 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5034 | while (!list_empty(&file_priv->mm.request_list)) { |
5035 | struct drm_i915_gem_request *request; | |
5036 | ||
5037 | request = list_first_entry(&file_priv->mm.request_list, | |
5038 | struct drm_i915_gem_request, | |
5039 | client_list); | |
5040 | list_del(&request->client_list); | |
5041 | request->file_priv = NULL; | |
5042 | } | |
1c25595f | 5043 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5044 | } |
31169714 | 5045 | |
b29c19b6 CW |
5046 | static void |
5047 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
5048 | { | |
5049 | struct drm_i915_file_private *file_priv = | |
5050 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
5051 | ||
5052 | atomic_set(&file_priv->rps_wait_boost, false); | |
5053 | } | |
5054 | ||
5055 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5056 | { | |
5057 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5058 | int ret; |
b29c19b6 CW |
5059 | |
5060 | DRM_DEBUG_DRIVER("\n"); | |
5061 | ||
5062 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5063 | if (!file_priv) | |
5064 | return -ENOMEM; | |
5065 | ||
5066 | file->driver_priv = file_priv; | |
5067 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5068 | file_priv->file = file; |
b29c19b6 CW |
5069 | |
5070 | spin_lock_init(&file_priv->mm.lock); | |
5071 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
5072 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
5073 | i915_gem_file_idle_work_handler); | |
5074 | ||
e422b888 BW |
5075 | ret = i915_gem_context_open(dev, file); |
5076 | if (ret) | |
5077 | kfree(file_priv); | |
b29c19b6 | 5078 | |
e422b888 | 5079 | return ret; |
b29c19b6 CW |
5080 | } |
5081 | ||
b680c37a DV |
5082 | /** |
5083 | * i915_gem_track_fb - update frontbuffer tracking | |
5084 | * old: current GEM buffer for the frontbuffer slots | |
5085 | * new: new GEM buffer for the frontbuffer slots | |
5086 | * frontbuffer_bits: bitmask of frontbuffer slots | |
5087 | * | |
5088 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5089 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5090 | */ | |
a071fa00 DV |
5091 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5092 | struct drm_i915_gem_object *new, | |
5093 | unsigned frontbuffer_bits) | |
5094 | { | |
5095 | if (old) { | |
5096 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5097 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5098 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5099 | } | |
5100 | ||
5101 | if (new) { | |
5102 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5103 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5104 | new->frontbuffer_bits |= frontbuffer_bits; | |
5105 | } | |
5106 | } | |
5107 | ||
5774506f CW |
5108 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
5109 | { | |
5110 | if (!mutex_is_locked(mutex)) | |
5111 | return false; | |
5112 | ||
226e5ae9 | 5113 | #if defined(CONFIG_SMP) && !defined(CONFIG_DEBUG_MUTEXES) |
5774506f CW |
5114 | return mutex->owner == task; |
5115 | #else | |
5116 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5117 | return false; | |
5118 | #endif | |
5119 | } | |
5120 | ||
b453c4db CW |
5121 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
5122 | { | |
5123 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5124 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
5125 | return false; | |
5126 | ||
5127 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) | |
5128 | return false; | |
5129 | ||
5130 | *unlock = false; | |
5131 | } else | |
5132 | *unlock = true; | |
5133 | ||
5134 | return true; | |
5135 | } | |
5136 | ||
ceabbba5 CW |
5137 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5138 | { | |
5139 | struct i915_vma *vma; | |
5140 | int count = 0; | |
5141 | ||
5142 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5143 | if (drm_mm_node_allocated(&vma->node)) | |
5144 | count++; | |
5145 | ||
5146 | return count; | |
5147 | } | |
5148 | ||
7dc19d5a | 5149 | static unsigned long |
ceabbba5 | 5150 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5151 | { |
17250b71 | 5152 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5153 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5154 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5155 | struct drm_i915_gem_object *obj; |
7dc19d5a | 5156 | unsigned long count; |
b453c4db | 5157 | bool unlock; |
17250b71 | 5158 | |
b453c4db CW |
5159 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5160 | return 0; | |
31169714 | 5161 | |
7dc19d5a | 5162 | count = 0; |
35c20a60 | 5163 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5164 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5165 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5166 | |
5167 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5168 | if (!i915_gem_obj_is_pinned(obj) && |
5169 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5170 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5171 | } |
17250b71 | 5172 | |
5774506f CW |
5173 | if (unlock) |
5174 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5175 | |
7dc19d5a | 5176 | return count; |
31169714 | 5177 | } |
a70a3148 BW |
5178 | |
5179 | /* All the new VM stuff */ | |
fe14d5f4 TU |
5180 | unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o, |
5181 | struct i915_address_space *vm, | |
5182 | enum i915_ggtt_view_type view) | |
a70a3148 BW |
5183 | { |
5184 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5185 | struct i915_vma *vma; | |
5186 | ||
896ab1a5 | 5187 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5188 | |
a70a3148 | 5189 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
fe14d5f4 | 5190 | if (vma->vm == vm && vma->ggtt_view.type == view) |
a70a3148 BW |
5191 | return vma->node.start; |
5192 | ||
5193 | } | |
f25748ea DV |
5194 | WARN(1, "%s vma for this object not found.\n", |
5195 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5196 | return -1; |
5197 | } | |
5198 | ||
fe14d5f4 TU |
5199 | bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o, |
5200 | struct i915_address_space *vm, | |
5201 | enum i915_ggtt_view_type view) | |
a70a3148 BW |
5202 | { |
5203 | struct i915_vma *vma; | |
5204 | ||
5205 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
fe14d5f4 TU |
5206 | if (vma->vm == vm && |
5207 | vma->ggtt_view.type == view && | |
5208 | drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5209 | return true; |
5210 | ||
5211 | return false; | |
5212 | } | |
5213 | ||
5214 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5215 | { | |
5a1d5eb0 | 5216 | struct i915_vma *vma; |
a70a3148 | 5217 | |
5a1d5eb0 CW |
5218 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5219 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5220 | return true; |
5221 | ||
5222 | return false; | |
5223 | } | |
5224 | ||
5225 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5226 | struct i915_address_space *vm) | |
5227 | { | |
5228 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5229 | struct i915_vma *vma; | |
5230 | ||
896ab1a5 | 5231 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5232 | |
5233 | BUG_ON(list_empty(&o->vma_list)); | |
5234 | ||
5235 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5236 | if (vma->vm == vm) | |
5237 | return vma->node.size; | |
5238 | ||
5239 | return 0; | |
5240 | } | |
5241 | ||
7dc19d5a | 5242 | static unsigned long |
ceabbba5 | 5243 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5244 | { |
5245 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5246 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5247 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a | 5248 | unsigned long freed; |
b453c4db | 5249 | bool unlock; |
7dc19d5a | 5250 | |
b453c4db CW |
5251 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5252 | return SHRINK_STOP; | |
7dc19d5a | 5253 | |
21ab4e74 CW |
5254 | freed = i915_gem_shrink(dev_priv, |
5255 | sc->nr_to_scan, | |
5256 | I915_SHRINK_BOUND | | |
5257 | I915_SHRINK_UNBOUND | | |
5258 | I915_SHRINK_PURGEABLE); | |
d9973b43 | 5259 | if (freed < sc->nr_to_scan) |
21ab4e74 CW |
5260 | freed += i915_gem_shrink(dev_priv, |
5261 | sc->nr_to_scan - freed, | |
5262 | I915_SHRINK_BOUND | | |
5263 | I915_SHRINK_UNBOUND); | |
7dc19d5a DC |
5264 | if (unlock) |
5265 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5266 | |
7dc19d5a DC |
5267 | return freed; |
5268 | } | |
5c2abbea | 5269 | |
2cfcd32a CW |
5270 | static int |
5271 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) | |
5272 | { | |
5273 | struct drm_i915_private *dev_priv = | |
5274 | container_of(nb, struct drm_i915_private, mm.oom_notifier); | |
5275 | struct drm_device *dev = dev_priv->dev; | |
5276 | struct drm_i915_gem_object *obj; | |
5277 | unsigned long timeout = msecs_to_jiffies(5000) + 1; | |
005445c5 | 5278 | unsigned long pinned, bound, unbound, freed_pages; |
2cfcd32a CW |
5279 | bool was_interruptible; |
5280 | bool unlock; | |
5281 | ||
a1db2fa7 | 5282 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) { |
2cfcd32a | 5283 | schedule_timeout_killable(1); |
a1db2fa7 CW |
5284 | if (fatal_signal_pending(current)) |
5285 | return NOTIFY_DONE; | |
5286 | } | |
2cfcd32a CW |
5287 | if (timeout == 0) { |
5288 | pr_err("Unable to purge GPU memory due lock contention.\n"); | |
5289 | return NOTIFY_DONE; | |
5290 | } | |
5291 | ||
5292 | was_interruptible = dev_priv->mm.interruptible; | |
5293 | dev_priv->mm.interruptible = false; | |
5294 | ||
005445c5 | 5295 | freed_pages = i915_gem_shrink_all(dev_priv); |
2cfcd32a CW |
5296 | |
5297 | dev_priv->mm.interruptible = was_interruptible; | |
5298 | ||
5299 | /* Because we may be allocating inside our own driver, we cannot | |
5300 | * assert that there are no objects with pinned pages that are not | |
5301 | * being pointed to by hardware. | |
5302 | */ | |
5303 | unbound = bound = pinned = 0; | |
5304 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5305 | if (!obj->base.filp) /* not backed by a freeable object */ | |
5306 | continue; | |
5307 | ||
5308 | if (obj->pages_pin_count) | |
5309 | pinned += obj->base.size; | |
5310 | else | |
5311 | unbound += obj->base.size; | |
5312 | } | |
5313 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5314 | if (!obj->base.filp) | |
5315 | continue; | |
5316 | ||
5317 | if (obj->pages_pin_count) | |
5318 | pinned += obj->base.size; | |
5319 | else | |
5320 | bound += obj->base.size; | |
5321 | } | |
5322 | ||
5323 | if (unlock) | |
5324 | mutex_unlock(&dev->struct_mutex); | |
5325 | ||
bb9059d3 CW |
5326 | if (freed_pages || unbound || bound) |
5327 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", | |
5328 | freed_pages << PAGE_SHIFT, pinned); | |
2cfcd32a CW |
5329 | if (unbound || bound) |
5330 | pr_err("%lu and %lu bytes still available in the " | |
5331 | "bound and unbound GPU page lists.\n", | |
5332 | bound, unbound); | |
5333 | ||
005445c5 | 5334 | *(unsigned long *)ptr += freed_pages; |
2cfcd32a CW |
5335 | return NOTIFY_DONE; |
5336 | } | |
5337 | ||
5c2abbea BW |
5338 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
5339 | { | |
f7635669 | 5340 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
5c2abbea BW |
5341 | struct i915_vma *vma; |
5342 | ||
fe14d5f4 TU |
5343 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
5344 | if (vma->vm == ggtt && | |
5345 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
f7635669 | 5346 | return vma; |
5c2abbea | 5347 | |
f7635669 | 5348 | return NULL; |
5c2abbea | 5349 | } |