Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
86a1ee26 CW |
44 | bool map_and_fenceable, |
45 | bool nonblocking); | |
05394f39 CW |
46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
47 | struct drm_i915_gem_object *obj, | |
71acb5eb | 48 | struct drm_i915_gem_pwrite *args, |
05394f39 | 49 | struct drm_file *file); |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
6c085a72 CW |
59 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
60 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 61 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 62 | |
61050808 CW |
63 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
64 | { | |
65 | if (obj->tiling_mode) | |
66 | i915_gem_release_mmap(obj); | |
67 | ||
68 | /* As we do not have an associated fence register, we will force | |
69 | * a tiling change if we ever need to acquire one. | |
70 | */ | |
5d82e3e6 | 71 | obj->fence_dirty = false; |
61050808 CW |
72 | obj->fence_reg = I915_FENCE_REG_NONE; |
73 | } | |
74 | ||
73aa808f CW |
75 | /* some bookkeeping */ |
76 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
77 | size_t size) | |
78 | { | |
79 | dev_priv->mm.object_count++; | |
80 | dev_priv->mm.object_memory += size; | |
81 | } | |
82 | ||
83 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
84 | size_t size) | |
85 | { | |
86 | dev_priv->mm.object_count--; | |
87 | dev_priv->mm.object_memory -= size; | |
88 | } | |
89 | ||
21dd3734 CW |
90 | static int |
91 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
92 | { |
93 | struct drm_i915_private *dev_priv = dev->dev_private; | |
94 | struct completion *x = &dev_priv->error_completion; | |
95 | unsigned long flags; | |
96 | int ret; | |
97 | ||
98 | if (!atomic_read(&dev_priv->mm.wedged)) | |
99 | return 0; | |
100 | ||
0a6759c6 DV |
101 | /* |
102 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
103 | * userspace. If it takes that long something really bad is going on and | |
104 | * we should simply try to bail out and fail as gracefully as possible. | |
105 | */ | |
106 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
107 | if (ret == 0) { | |
108 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
109 | return -EIO; | |
110 | } else if (ret < 0) { | |
30dbf0c0 | 111 | return ret; |
0a6759c6 | 112 | } |
30dbf0c0 | 113 | |
21dd3734 CW |
114 | if (atomic_read(&dev_priv->mm.wedged)) { |
115 | /* GPU is hung, bump the completion count to account for | |
116 | * the token we just consumed so that we never hit zero and | |
117 | * end up waiting upon a subsequent completion event that | |
118 | * will never happen. | |
119 | */ | |
120 | spin_lock_irqsave(&x->wait.lock, flags); | |
121 | x->done++; | |
122 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
123 | } | |
124 | return 0; | |
30dbf0c0 CW |
125 | } |
126 | ||
54cf91dc | 127 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 128 | { |
76c1dec1 CW |
129 | int ret; |
130 | ||
21dd3734 | 131 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
132 | if (ret) |
133 | return ret; | |
134 | ||
135 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
136 | if (ret) | |
137 | return ret; | |
138 | ||
23bc5982 | 139 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
140 | return 0; |
141 | } | |
30dbf0c0 | 142 | |
7d1c4804 | 143 | static inline bool |
05394f39 | 144 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 145 | { |
6c085a72 | 146 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
147 | } |
148 | ||
79e53945 JB |
149 | int |
150 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 151 | struct drm_file *file) |
79e53945 JB |
152 | { |
153 | struct drm_i915_gem_init *args = data; | |
2021746e | 154 | |
7bb6fb8d DV |
155 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
156 | return -ENODEV; | |
157 | ||
2021746e CW |
158 | if (args->gtt_start >= args->gtt_end || |
159 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
160 | return -EINVAL; | |
79e53945 | 161 | |
f534bc0b DV |
162 | /* GEM with user mode setting was never supported on ilk and later. */ |
163 | if (INTEL_INFO(dev)->gen >= 5) | |
164 | return -ENODEV; | |
165 | ||
79e53945 | 166 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
167 | i915_gem_init_global_gtt(dev, args->gtt_start, |
168 | args->gtt_end, args->gtt_end); | |
673a394b EA |
169 | mutex_unlock(&dev->struct_mutex); |
170 | ||
2021746e | 171 | return 0; |
673a394b EA |
172 | } |
173 | ||
5a125c3c EA |
174 | int |
175 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 176 | struct drm_file *file) |
5a125c3c | 177 | { |
73aa808f | 178 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 179 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
180 | struct drm_i915_gem_object *obj; |
181 | size_t pinned; | |
5a125c3c | 182 | |
6299f992 | 183 | pinned = 0; |
73aa808f | 184 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 185 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
186 | if (obj->pin_count) |
187 | pinned += obj->gtt_space->size; | |
73aa808f | 188 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 189 | |
6299f992 | 190 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 191 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 192 | |
5a125c3c EA |
193 | return 0; |
194 | } | |
195 | ||
ff72145b DA |
196 | static int |
197 | i915_gem_create(struct drm_file *file, | |
198 | struct drm_device *dev, | |
199 | uint64_t size, | |
200 | uint32_t *handle_p) | |
673a394b | 201 | { |
05394f39 | 202 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
203 | int ret; |
204 | u32 handle; | |
673a394b | 205 | |
ff72145b | 206 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
207 | if (size == 0) |
208 | return -EINVAL; | |
673a394b EA |
209 | |
210 | /* Allocate the new object */ | |
ff72145b | 211 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
212 | if (obj == NULL) |
213 | return -ENOMEM; | |
214 | ||
05394f39 | 215 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 216 | if (ret) { |
05394f39 CW |
217 | drm_gem_object_release(&obj->base); |
218 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 219 | kfree(obj); |
673a394b | 220 | return ret; |
1dfd9754 | 221 | } |
673a394b | 222 | |
202f2fef | 223 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 224 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
225 | trace_i915_gem_object_create(obj); |
226 | ||
ff72145b | 227 | *handle_p = handle; |
673a394b EA |
228 | return 0; |
229 | } | |
230 | ||
ff72145b DA |
231 | int |
232 | i915_gem_dumb_create(struct drm_file *file, | |
233 | struct drm_device *dev, | |
234 | struct drm_mode_create_dumb *args) | |
235 | { | |
236 | /* have to work out size/pitch and return them */ | |
ed0291fd | 237 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
238 | args->size = args->pitch * args->height; |
239 | return i915_gem_create(file, dev, | |
240 | args->size, &args->handle); | |
241 | } | |
242 | ||
243 | int i915_gem_dumb_destroy(struct drm_file *file, | |
244 | struct drm_device *dev, | |
245 | uint32_t handle) | |
246 | { | |
247 | return drm_gem_handle_delete(file, handle); | |
248 | } | |
249 | ||
250 | /** | |
251 | * Creates a new mm object and returns a handle to it. | |
252 | */ | |
253 | int | |
254 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
255 | struct drm_file *file) | |
256 | { | |
257 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 258 | |
ff72145b DA |
259 | return i915_gem_create(file, dev, |
260 | args->size, &args->handle); | |
261 | } | |
262 | ||
05394f39 | 263 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 264 | { |
05394f39 | 265 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
266 | |
267 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 268 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
269 | } |
270 | ||
8461d226 DV |
271 | static inline int |
272 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
273 | const char *gpu_vaddr, int gpu_offset, | |
274 | int length) | |
275 | { | |
276 | int ret, cpu_offset = 0; | |
277 | ||
278 | while (length > 0) { | |
279 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
280 | int this_length = min(cacheline_end - gpu_offset, length); | |
281 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
282 | ||
283 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
284 | gpu_vaddr + swizzled_gpu_offset, | |
285 | this_length); | |
286 | if (ret) | |
287 | return ret + length; | |
288 | ||
289 | cpu_offset += this_length; | |
290 | gpu_offset += this_length; | |
291 | length -= this_length; | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
8c59967c | 297 | static inline int |
4f0c7cfb BW |
298 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
299 | const char __user *cpu_vaddr, | |
8c59967c DV |
300 | int length) |
301 | { | |
302 | int ret, cpu_offset = 0; | |
303 | ||
304 | while (length > 0) { | |
305 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
306 | int this_length = min(cacheline_end - gpu_offset, length); | |
307 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
308 | ||
309 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
310 | cpu_vaddr + cpu_offset, | |
311 | this_length); | |
312 | if (ret) | |
313 | return ret + length; | |
314 | ||
315 | cpu_offset += this_length; | |
316 | gpu_offset += this_length; | |
317 | length -= this_length; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
d174bd64 DV |
323 | /* Per-page copy function for the shmem pread fastpath. |
324 | * Flushes invalid cachelines before reading the target if | |
325 | * needs_clflush is set. */ | |
eb01459f | 326 | static int |
d174bd64 DV |
327 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
328 | char __user *user_data, | |
329 | bool page_do_bit17_swizzling, bool needs_clflush) | |
330 | { | |
331 | char *vaddr; | |
332 | int ret; | |
333 | ||
e7e58eb5 | 334 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
335 | return -EINVAL; |
336 | ||
337 | vaddr = kmap_atomic(page); | |
338 | if (needs_clflush) | |
339 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
340 | page_length); | |
341 | ret = __copy_to_user_inatomic(user_data, | |
342 | vaddr + shmem_page_offset, | |
343 | page_length); | |
344 | kunmap_atomic(vaddr); | |
345 | ||
f60d7f0c | 346 | return ret ? -EFAULT : 0; |
d174bd64 DV |
347 | } |
348 | ||
23c18c71 DV |
349 | static void |
350 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
351 | bool swizzled) | |
352 | { | |
e7e58eb5 | 353 | if (unlikely(swizzled)) { |
23c18c71 DV |
354 | unsigned long start = (unsigned long) addr; |
355 | unsigned long end = (unsigned long) addr + length; | |
356 | ||
357 | /* For swizzling simply ensure that we always flush both | |
358 | * channels. Lame, but simple and it works. Swizzled | |
359 | * pwrite/pread is far from a hotpath - current userspace | |
360 | * doesn't use it at all. */ | |
361 | start = round_down(start, 128); | |
362 | end = round_up(end, 128); | |
363 | ||
364 | drm_clflush_virt_range((void *)start, end - start); | |
365 | } else { | |
366 | drm_clflush_virt_range(addr, length); | |
367 | } | |
368 | ||
369 | } | |
370 | ||
d174bd64 DV |
371 | /* Only difference to the fast-path function is that this can handle bit17 |
372 | * and uses non-atomic copy and kmap functions. */ | |
373 | static int | |
374 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
375 | char __user *user_data, | |
376 | bool page_do_bit17_swizzling, bool needs_clflush) | |
377 | { | |
378 | char *vaddr; | |
379 | int ret; | |
380 | ||
381 | vaddr = kmap(page); | |
382 | if (needs_clflush) | |
23c18c71 DV |
383 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
384 | page_length, | |
385 | page_do_bit17_swizzling); | |
d174bd64 DV |
386 | |
387 | if (page_do_bit17_swizzling) | |
388 | ret = __copy_to_user_swizzled(user_data, | |
389 | vaddr, shmem_page_offset, | |
390 | page_length); | |
391 | else | |
392 | ret = __copy_to_user(user_data, | |
393 | vaddr + shmem_page_offset, | |
394 | page_length); | |
395 | kunmap(page); | |
396 | ||
f60d7f0c | 397 | return ret ? - EFAULT : 0; |
d174bd64 DV |
398 | } |
399 | ||
eb01459f | 400 | static int |
dbf7bff0 DV |
401 | i915_gem_shmem_pread(struct drm_device *dev, |
402 | struct drm_i915_gem_object *obj, | |
403 | struct drm_i915_gem_pread *args, | |
404 | struct drm_file *file) | |
eb01459f | 405 | { |
8461d226 | 406 | char __user *user_data; |
eb01459f | 407 | ssize_t remain; |
8461d226 | 408 | loff_t offset; |
eb2c0c81 | 409 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 410 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 411 | int hit_slowpath = 0; |
96d79b52 | 412 | int prefaulted = 0; |
8489731c | 413 | int needs_clflush = 0; |
9da3da66 CW |
414 | struct scatterlist *sg; |
415 | int i; | |
eb01459f | 416 | |
8461d226 | 417 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
418 | remain = args->size; |
419 | ||
8461d226 | 420 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 421 | |
8489731c DV |
422 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
423 | /* If we're not in the cpu read domain, set ourself into the gtt | |
424 | * read domain and manually flush cachelines (if required). This | |
425 | * optimizes for the case when the gpu will dirty the data | |
426 | * anyway again before the next pread happens. */ | |
427 | if (obj->cache_level == I915_CACHE_NONE) | |
428 | needs_clflush = 1; | |
6c085a72 CW |
429 | if (obj->gtt_space) { |
430 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
431 | if (ret) | |
432 | return ret; | |
433 | } | |
8489731c | 434 | } |
eb01459f | 435 | |
f60d7f0c CW |
436 | ret = i915_gem_object_get_pages(obj); |
437 | if (ret) | |
438 | return ret; | |
439 | ||
440 | i915_gem_object_pin_pages(obj); | |
441 | ||
8461d226 | 442 | offset = args->offset; |
eb01459f | 443 | |
9da3da66 | 444 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd CW |
445 | struct page *page; |
446 | ||
9da3da66 CW |
447 | if (i < offset >> PAGE_SHIFT) |
448 | continue; | |
449 | ||
450 | if (remain <= 0) | |
451 | break; | |
452 | ||
eb01459f EA |
453 | /* Operation in this page |
454 | * | |
eb01459f | 455 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
456 | * page_length = bytes to copy for this page |
457 | */ | |
c8cbbb8b | 458 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
459 | page_length = remain; |
460 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
461 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 462 | |
9da3da66 | 463 | page = sg_page(sg); |
8461d226 DV |
464 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
465 | (page_to_phys(page) & (1 << 17)) != 0; | |
466 | ||
d174bd64 DV |
467 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
468 | user_data, page_do_bit17_swizzling, | |
469 | needs_clflush); | |
470 | if (ret == 0) | |
471 | goto next_page; | |
dbf7bff0 DV |
472 | |
473 | hit_slowpath = 1; | |
dbf7bff0 DV |
474 | mutex_unlock(&dev->struct_mutex); |
475 | ||
96d79b52 | 476 | if (!prefaulted) { |
f56f821f | 477 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
478 | /* Userspace is tricking us, but we've already clobbered |
479 | * its pages with the prefault and promised to write the | |
480 | * data up to the first fault. Hence ignore any errors | |
481 | * and just continue. */ | |
482 | (void)ret; | |
483 | prefaulted = 1; | |
484 | } | |
eb01459f | 485 | |
d174bd64 DV |
486 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
487 | user_data, page_do_bit17_swizzling, | |
488 | needs_clflush); | |
eb01459f | 489 | |
dbf7bff0 | 490 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 491 | |
dbf7bff0 | 492 | next_page: |
e5281ccd | 493 | mark_page_accessed(page); |
e5281ccd | 494 | |
f60d7f0c | 495 | if (ret) |
8461d226 | 496 | goto out; |
8461d226 | 497 | |
eb01459f | 498 | remain -= page_length; |
8461d226 | 499 | user_data += page_length; |
eb01459f EA |
500 | offset += page_length; |
501 | } | |
502 | ||
4f27b75d | 503 | out: |
f60d7f0c CW |
504 | i915_gem_object_unpin_pages(obj); |
505 | ||
dbf7bff0 DV |
506 | if (hit_slowpath) { |
507 | /* Fixup: Kill any reinstated backing storage pages */ | |
508 | if (obj->madv == __I915_MADV_PURGED) | |
509 | i915_gem_object_truncate(obj); | |
510 | } | |
eb01459f EA |
511 | |
512 | return ret; | |
513 | } | |
514 | ||
673a394b EA |
515 | /** |
516 | * Reads data from the object referenced by handle. | |
517 | * | |
518 | * On error, the contents of *data are undefined. | |
519 | */ | |
520 | int | |
521 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 522 | struct drm_file *file) |
673a394b EA |
523 | { |
524 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 525 | struct drm_i915_gem_object *obj; |
35b62a89 | 526 | int ret = 0; |
673a394b | 527 | |
51311d0a CW |
528 | if (args->size == 0) |
529 | return 0; | |
530 | ||
531 | if (!access_ok(VERIFY_WRITE, | |
532 | (char __user *)(uintptr_t)args->data_ptr, | |
533 | args->size)) | |
534 | return -EFAULT; | |
535 | ||
4f27b75d | 536 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 537 | if (ret) |
4f27b75d | 538 | return ret; |
673a394b | 539 | |
05394f39 | 540 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 541 | if (&obj->base == NULL) { |
1d7cfea1 CW |
542 | ret = -ENOENT; |
543 | goto unlock; | |
4f27b75d | 544 | } |
673a394b | 545 | |
7dcd2499 | 546 | /* Bounds check source. */ |
05394f39 CW |
547 | if (args->offset > obj->base.size || |
548 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 549 | ret = -EINVAL; |
35b62a89 | 550 | goto out; |
ce9d419d CW |
551 | } |
552 | ||
1286ff73 DV |
553 | /* prime objects have no backing filp to GEM pread/pwrite |
554 | * pages from. | |
555 | */ | |
556 | if (!obj->base.filp) { | |
557 | ret = -EINVAL; | |
558 | goto out; | |
559 | } | |
560 | ||
db53a302 CW |
561 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
562 | ||
dbf7bff0 | 563 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 564 | |
35b62a89 | 565 | out: |
05394f39 | 566 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 567 | unlock: |
4f27b75d | 568 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 569 | return ret; |
673a394b EA |
570 | } |
571 | ||
0839ccb8 KP |
572 | /* This is the fast write path which cannot handle |
573 | * page faults in the source data | |
9b7530cc | 574 | */ |
0839ccb8 KP |
575 | |
576 | static inline int | |
577 | fast_user_write(struct io_mapping *mapping, | |
578 | loff_t page_base, int page_offset, | |
579 | char __user *user_data, | |
580 | int length) | |
9b7530cc | 581 | { |
4f0c7cfb BW |
582 | void __iomem *vaddr_atomic; |
583 | void *vaddr; | |
0839ccb8 | 584 | unsigned long unwritten; |
9b7530cc | 585 | |
3e4d3af5 | 586 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
587 | /* We can use the cpu mem copy function because this is X86. */ |
588 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
589 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 590 | user_data, length); |
3e4d3af5 | 591 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 592 | return unwritten; |
0839ccb8 KP |
593 | } |
594 | ||
3de09aa3 EA |
595 | /** |
596 | * This is the fast pwrite path, where we copy the data directly from the | |
597 | * user into the GTT, uncached. | |
598 | */ | |
673a394b | 599 | static int |
05394f39 CW |
600 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
601 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 602 | struct drm_i915_gem_pwrite *args, |
05394f39 | 603 | struct drm_file *file) |
673a394b | 604 | { |
0839ccb8 | 605 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 606 | ssize_t remain; |
0839ccb8 | 607 | loff_t offset, page_base; |
673a394b | 608 | char __user *user_data; |
935aaa69 DV |
609 | int page_offset, page_length, ret; |
610 | ||
86a1ee26 | 611 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
612 | if (ret) |
613 | goto out; | |
614 | ||
615 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
616 | if (ret) | |
617 | goto out_unpin; | |
618 | ||
619 | ret = i915_gem_object_put_fence(obj); | |
620 | if (ret) | |
621 | goto out_unpin; | |
673a394b EA |
622 | |
623 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
624 | remain = args->size; | |
673a394b | 625 | |
05394f39 | 626 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
627 | |
628 | while (remain > 0) { | |
629 | /* Operation in this page | |
630 | * | |
0839ccb8 KP |
631 | * page_base = page offset within aperture |
632 | * page_offset = offset within page | |
633 | * page_length = bytes to copy for this page | |
673a394b | 634 | */ |
c8cbbb8b CW |
635 | page_base = offset & PAGE_MASK; |
636 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
637 | page_length = remain; |
638 | if ((page_offset + remain) > PAGE_SIZE) | |
639 | page_length = PAGE_SIZE - page_offset; | |
640 | ||
0839ccb8 | 641 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
642 | * source page isn't available. Return the error and we'll |
643 | * retry in the slow path. | |
0839ccb8 | 644 | */ |
fbd5a26d | 645 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
646 | page_offset, user_data, page_length)) { |
647 | ret = -EFAULT; | |
648 | goto out_unpin; | |
649 | } | |
673a394b | 650 | |
0839ccb8 KP |
651 | remain -= page_length; |
652 | user_data += page_length; | |
653 | offset += page_length; | |
673a394b | 654 | } |
673a394b | 655 | |
935aaa69 DV |
656 | out_unpin: |
657 | i915_gem_object_unpin(obj); | |
658 | out: | |
3de09aa3 | 659 | return ret; |
673a394b EA |
660 | } |
661 | ||
d174bd64 DV |
662 | /* Per-page copy function for the shmem pwrite fastpath. |
663 | * Flushes invalid cachelines before writing to the target if | |
664 | * needs_clflush_before is set and flushes out any written cachelines after | |
665 | * writing if needs_clflush is set. */ | |
3043c60c | 666 | static int |
d174bd64 DV |
667 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
668 | char __user *user_data, | |
669 | bool page_do_bit17_swizzling, | |
670 | bool needs_clflush_before, | |
671 | bool needs_clflush_after) | |
673a394b | 672 | { |
d174bd64 | 673 | char *vaddr; |
673a394b | 674 | int ret; |
3de09aa3 | 675 | |
e7e58eb5 | 676 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 677 | return -EINVAL; |
3de09aa3 | 678 | |
d174bd64 DV |
679 | vaddr = kmap_atomic(page); |
680 | if (needs_clflush_before) | |
681 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
682 | page_length); | |
683 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
684 | user_data, | |
685 | page_length); | |
686 | if (needs_clflush_after) | |
687 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
688 | page_length); | |
689 | kunmap_atomic(vaddr); | |
3de09aa3 | 690 | |
755d2218 | 691 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
692 | } |
693 | ||
d174bd64 DV |
694 | /* Only difference to the fast-path function is that this can handle bit17 |
695 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 696 | static int |
d174bd64 DV |
697 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
698 | char __user *user_data, | |
699 | bool page_do_bit17_swizzling, | |
700 | bool needs_clflush_before, | |
701 | bool needs_clflush_after) | |
673a394b | 702 | { |
d174bd64 DV |
703 | char *vaddr; |
704 | int ret; | |
e5281ccd | 705 | |
d174bd64 | 706 | vaddr = kmap(page); |
e7e58eb5 | 707 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
708 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
709 | page_length, | |
710 | page_do_bit17_swizzling); | |
d174bd64 DV |
711 | if (page_do_bit17_swizzling) |
712 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
713 | user_data, |
714 | page_length); | |
d174bd64 DV |
715 | else |
716 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
717 | user_data, | |
718 | page_length); | |
719 | if (needs_clflush_after) | |
23c18c71 DV |
720 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
721 | page_length, | |
722 | page_do_bit17_swizzling); | |
d174bd64 | 723 | kunmap(page); |
40123c1f | 724 | |
755d2218 | 725 | return ret ? -EFAULT : 0; |
40123c1f EA |
726 | } |
727 | ||
40123c1f | 728 | static int |
e244a443 DV |
729 | i915_gem_shmem_pwrite(struct drm_device *dev, |
730 | struct drm_i915_gem_object *obj, | |
731 | struct drm_i915_gem_pwrite *args, | |
732 | struct drm_file *file) | |
40123c1f | 733 | { |
40123c1f | 734 | ssize_t remain; |
8c59967c DV |
735 | loff_t offset; |
736 | char __user *user_data; | |
eb2c0c81 | 737 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 738 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 739 | int hit_slowpath = 0; |
58642885 DV |
740 | int needs_clflush_after = 0; |
741 | int needs_clflush_before = 0; | |
9da3da66 CW |
742 | int i; |
743 | struct scatterlist *sg; | |
40123c1f | 744 | |
8c59967c | 745 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
746 | remain = args->size; |
747 | ||
8c59967c | 748 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 749 | |
58642885 DV |
750 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
751 | /* If we're not in the cpu write domain, set ourself into the gtt | |
752 | * write domain and manually flush cachelines (if required). This | |
753 | * optimizes for the case when the gpu will use the data | |
754 | * right away and we therefore have to clflush anyway. */ | |
755 | if (obj->cache_level == I915_CACHE_NONE) | |
756 | needs_clflush_after = 1; | |
6c085a72 CW |
757 | if (obj->gtt_space) { |
758 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
759 | if (ret) | |
760 | return ret; | |
761 | } | |
58642885 DV |
762 | } |
763 | /* Same trick applies for invalidate partially written cachelines before | |
764 | * writing. */ | |
765 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
766 | && obj->cache_level == I915_CACHE_NONE) | |
767 | needs_clflush_before = 1; | |
768 | ||
755d2218 CW |
769 | ret = i915_gem_object_get_pages(obj); |
770 | if (ret) | |
771 | return ret; | |
772 | ||
773 | i915_gem_object_pin_pages(obj); | |
774 | ||
673a394b | 775 | offset = args->offset; |
05394f39 | 776 | obj->dirty = 1; |
673a394b | 777 | |
9da3da66 | 778 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd | 779 | struct page *page; |
58642885 | 780 | int partial_cacheline_write; |
e5281ccd | 781 | |
9da3da66 CW |
782 | if (i < offset >> PAGE_SHIFT) |
783 | continue; | |
784 | ||
785 | if (remain <= 0) | |
786 | break; | |
787 | ||
40123c1f EA |
788 | /* Operation in this page |
789 | * | |
40123c1f | 790 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
791 | * page_length = bytes to copy for this page |
792 | */ | |
c8cbbb8b | 793 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
794 | |
795 | page_length = remain; | |
796 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
797 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 798 | |
58642885 DV |
799 | /* If we don't overwrite a cacheline completely we need to be |
800 | * careful to have up-to-date data by first clflushing. Don't | |
801 | * overcomplicate things and flush the entire patch. */ | |
802 | partial_cacheline_write = needs_clflush_before && | |
803 | ((shmem_page_offset | page_length) | |
804 | & (boot_cpu_data.x86_clflush_size - 1)); | |
805 | ||
9da3da66 | 806 | page = sg_page(sg); |
8c59967c DV |
807 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
808 | (page_to_phys(page) & (1 << 17)) != 0; | |
809 | ||
d174bd64 DV |
810 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
811 | user_data, page_do_bit17_swizzling, | |
812 | partial_cacheline_write, | |
813 | needs_clflush_after); | |
814 | if (ret == 0) | |
815 | goto next_page; | |
e244a443 DV |
816 | |
817 | hit_slowpath = 1; | |
e244a443 | 818 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
819 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
820 | user_data, page_do_bit17_swizzling, | |
821 | partial_cacheline_write, | |
822 | needs_clflush_after); | |
40123c1f | 823 | |
e244a443 | 824 | mutex_lock(&dev->struct_mutex); |
755d2218 | 825 | |
e244a443 | 826 | next_page: |
e5281ccd CW |
827 | set_page_dirty(page); |
828 | mark_page_accessed(page); | |
e5281ccd | 829 | |
755d2218 | 830 | if (ret) |
8c59967c | 831 | goto out; |
8c59967c | 832 | |
40123c1f | 833 | remain -= page_length; |
8c59967c | 834 | user_data += page_length; |
40123c1f | 835 | offset += page_length; |
673a394b EA |
836 | } |
837 | ||
fbd5a26d | 838 | out: |
755d2218 CW |
839 | i915_gem_object_unpin_pages(obj); |
840 | ||
e244a443 DV |
841 | if (hit_slowpath) { |
842 | /* Fixup: Kill any reinstated backing storage pages */ | |
843 | if (obj->madv == __I915_MADV_PURGED) | |
844 | i915_gem_object_truncate(obj); | |
845 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
846 | * domain anymore. */ | |
847 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
848 | i915_gem_clflush_object(obj); | |
849 | intel_gtt_chipset_flush(); | |
850 | } | |
8c59967c | 851 | } |
673a394b | 852 | |
58642885 DV |
853 | if (needs_clflush_after) |
854 | intel_gtt_chipset_flush(); | |
855 | ||
40123c1f | 856 | return ret; |
673a394b EA |
857 | } |
858 | ||
859 | /** | |
860 | * Writes data to the object referenced by handle. | |
861 | * | |
862 | * On error, the contents of the buffer that were to be modified are undefined. | |
863 | */ | |
864 | int | |
865 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 866 | struct drm_file *file) |
673a394b EA |
867 | { |
868 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 869 | struct drm_i915_gem_object *obj; |
51311d0a CW |
870 | int ret; |
871 | ||
872 | if (args->size == 0) | |
873 | return 0; | |
874 | ||
875 | if (!access_ok(VERIFY_READ, | |
876 | (char __user *)(uintptr_t)args->data_ptr, | |
877 | args->size)) | |
878 | return -EFAULT; | |
879 | ||
f56f821f DV |
880 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
881 | args->size); | |
51311d0a CW |
882 | if (ret) |
883 | return -EFAULT; | |
673a394b | 884 | |
fbd5a26d | 885 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 886 | if (ret) |
fbd5a26d | 887 | return ret; |
1d7cfea1 | 888 | |
05394f39 | 889 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 890 | if (&obj->base == NULL) { |
1d7cfea1 CW |
891 | ret = -ENOENT; |
892 | goto unlock; | |
fbd5a26d | 893 | } |
673a394b | 894 | |
7dcd2499 | 895 | /* Bounds check destination. */ |
05394f39 CW |
896 | if (args->offset > obj->base.size || |
897 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 898 | ret = -EINVAL; |
35b62a89 | 899 | goto out; |
ce9d419d CW |
900 | } |
901 | ||
1286ff73 DV |
902 | /* prime objects have no backing filp to GEM pread/pwrite |
903 | * pages from. | |
904 | */ | |
905 | if (!obj->base.filp) { | |
906 | ret = -EINVAL; | |
907 | goto out; | |
908 | } | |
909 | ||
db53a302 CW |
910 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
911 | ||
935aaa69 | 912 | ret = -EFAULT; |
673a394b EA |
913 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
914 | * it would end up going through the fenced access, and we'll get | |
915 | * different detiling behavior between reading and writing. | |
916 | * pread/pwrite currently are reading and writing from the CPU | |
917 | * perspective, requiring manual detiling by the client. | |
918 | */ | |
5c0480f2 | 919 | if (obj->phys_obj) { |
fbd5a26d | 920 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
921 | goto out; |
922 | } | |
923 | ||
86a1ee26 | 924 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 925 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 926 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 927 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
928 | /* Note that the gtt paths might fail with non-page-backed user |
929 | * pointers (e.g. gtt mappings when moving data between | |
930 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 931 | } |
673a394b | 932 | |
86a1ee26 | 933 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 934 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 935 | |
35b62a89 | 936 | out: |
05394f39 | 937 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 938 | unlock: |
fbd5a26d | 939 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
940 | return ret; |
941 | } | |
942 | ||
b361237b CW |
943 | int |
944 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
945 | bool interruptible) | |
946 | { | |
947 | if (atomic_read(&dev_priv->mm.wedged)) { | |
948 | struct completion *x = &dev_priv->error_completion; | |
949 | bool recovery_complete; | |
950 | unsigned long flags; | |
951 | ||
952 | /* Give the error handler a chance to run. */ | |
953 | spin_lock_irqsave(&x->wait.lock, flags); | |
954 | recovery_complete = x->done > 0; | |
955 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
956 | ||
957 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
958 | * -EIO unconditionally for these. */ | |
959 | if (!interruptible) | |
960 | return -EIO; | |
961 | ||
962 | /* Recovery complete, but still wedged means reset failure. */ | |
963 | if (recovery_complete) | |
964 | return -EIO; | |
965 | ||
966 | return -EAGAIN; | |
967 | } | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | /* | |
973 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
974 | * equal. | |
975 | */ | |
976 | static int | |
977 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
978 | { | |
979 | int ret; | |
980 | ||
981 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
982 | ||
983 | ret = 0; | |
984 | if (seqno == ring->outstanding_lazy_request) | |
985 | ret = i915_add_request(ring, NULL, NULL); | |
986 | ||
987 | return ret; | |
988 | } | |
989 | ||
990 | /** | |
991 | * __wait_seqno - wait until execution of seqno has finished | |
992 | * @ring: the ring expected to report seqno | |
993 | * @seqno: duh! | |
994 | * @interruptible: do an interruptible wait (normally yes) | |
995 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
996 | * | |
997 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
998 | * errno with remaining time filled in timeout argument. | |
999 | */ | |
1000 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
1001 | bool interruptible, struct timespec *timeout) | |
1002 | { | |
1003 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1004 | struct timespec before, now, wait_time={1,0}; | |
1005 | unsigned long timeout_jiffies; | |
1006 | long end; | |
1007 | bool wait_forever = true; | |
1008 | int ret; | |
1009 | ||
1010 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
1011 | return 0; | |
1012 | ||
1013 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1014 | ||
1015 | if (timeout != NULL) { | |
1016 | wait_time = *timeout; | |
1017 | wait_forever = false; | |
1018 | } | |
1019 | ||
1020 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1021 | ||
1022 | if (WARN_ON(!ring->irq_get(ring))) | |
1023 | return -ENODEV; | |
1024 | ||
1025 | /* Record current time in case interrupted by signal, or wedged * */ | |
1026 | getrawmonotonic(&before); | |
1027 | ||
1028 | #define EXIT_COND \ | |
1029 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
1030 | atomic_read(&dev_priv->mm.wedged)) | |
1031 | do { | |
1032 | if (interruptible) | |
1033 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1034 | EXIT_COND, | |
1035 | timeout_jiffies); | |
1036 | else | |
1037 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1038 | timeout_jiffies); | |
1039 | ||
1040 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1041 | if (ret) | |
1042 | end = ret; | |
1043 | } while (end == 0 && wait_forever); | |
1044 | ||
1045 | getrawmonotonic(&now); | |
1046 | ||
1047 | ring->irq_put(ring); | |
1048 | trace_i915_gem_request_wait_end(ring, seqno); | |
1049 | #undef EXIT_COND | |
1050 | ||
1051 | if (timeout) { | |
1052 | struct timespec sleep_time = timespec_sub(now, before); | |
1053 | *timeout = timespec_sub(*timeout, sleep_time); | |
1054 | } | |
1055 | ||
1056 | switch (end) { | |
1057 | case -EIO: | |
1058 | case -EAGAIN: /* Wedged */ | |
1059 | case -ERESTARTSYS: /* Signal */ | |
1060 | return (int)end; | |
1061 | case 0: /* Timeout */ | |
1062 | if (timeout) | |
1063 | set_normalized_timespec(timeout, 0, 0); | |
1064 | return -ETIME; | |
1065 | default: /* Completed */ | |
1066 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1067 | return 0; | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | /** | |
1072 | * Waits for a sequence number to be signaled, and cleans up the | |
1073 | * request and object lists appropriately for that event. | |
1074 | */ | |
1075 | int | |
1076 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1077 | { | |
1078 | struct drm_device *dev = ring->dev; | |
1079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1080 | bool interruptible = dev_priv->mm.interruptible; | |
1081 | int ret; | |
1082 | ||
1083 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1084 | BUG_ON(seqno == 0); | |
1085 | ||
1086 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1087 | if (ret) | |
1088 | return ret; | |
1089 | ||
1090 | ret = i915_gem_check_olr(ring, seqno); | |
1091 | if (ret) | |
1092 | return ret; | |
1093 | ||
1094 | return __wait_seqno(ring, seqno, interruptible, NULL); | |
1095 | } | |
1096 | ||
1097 | /** | |
1098 | * Ensures that all rendering to the object has completed and the object is | |
1099 | * safe to unbind from the GTT or access from the CPU. | |
1100 | */ | |
1101 | static __must_check int | |
1102 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1103 | bool readonly) | |
1104 | { | |
1105 | struct intel_ring_buffer *ring = obj->ring; | |
1106 | u32 seqno; | |
1107 | int ret; | |
1108 | ||
1109 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1110 | if (seqno == 0) | |
1111 | return 0; | |
1112 | ||
1113 | ret = i915_wait_seqno(ring, seqno); | |
1114 | if (ret) | |
1115 | return ret; | |
1116 | ||
1117 | i915_gem_retire_requests_ring(ring); | |
1118 | ||
1119 | /* Manually manage the write flush as we may have not yet | |
1120 | * retired the buffer. | |
1121 | */ | |
1122 | if (obj->last_write_seqno && | |
1123 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1124 | obj->last_write_seqno = 0; | |
1125 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1126 | } | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
3236f57a CW |
1131 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1132 | * as the object state may change during this call. | |
1133 | */ | |
1134 | static __must_check int | |
1135 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1136 | bool readonly) | |
1137 | { | |
1138 | struct drm_device *dev = obj->base.dev; | |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1140 | struct intel_ring_buffer *ring = obj->ring; | |
1141 | u32 seqno; | |
1142 | int ret; | |
1143 | ||
1144 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1145 | BUG_ON(!dev_priv->mm.interruptible); | |
1146 | ||
1147 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1148 | if (seqno == 0) | |
1149 | return 0; | |
1150 | ||
1151 | ret = i915_gem_check_wedge(dev_priv, true); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | ||
1155 | ret = i915_gem_check_olr(ring, seqno); | |
1156 | if (ret) | |
1157 | return ret; | |
1158 | ||
1159 | mutex_unlock(&dev->struct_mutex); | |
1160 | ret = __wait_seqno(ring, seqno, true, NULL); | |
1161 | mutex_lock(&dev->struct_mutex); | |
1162 | ||
1163 | i915_gem_retire_requests_ring(ring); | |
1164 | ||
1165 | /* Manually manage the write flush as we may have not yet | |
1166 | * retired the buffer. | |
1167 | */ | |
1168 | if (obj->last_write_seqno && | |
1169 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1170 | obj->last_write_seqno = 0; | |
1171 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1172 | } | |
1173 | ||
1174 | return ret; | |
1175 | } | |
1176 | ||
673a394b | 1177 | /** |
2ef7eeaa EA |
1178 | * Called when user space prepares to use an object with the CPU, either |
1179 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1180 | */ |
1181 | int | |
1182 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1183 | struct drm_file *file) |
673a394b EA |
1184 | { |
1185 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1186 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1187 | uint32_t read_domains = args->read_domains; |
1188 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1189 | int ret; |
1190 | ||
2ef7eeaa | 1191 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1192 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1193 | return -EINVAL; |
1194 | ||
21d509e3 | 1195 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1196 | return -EINVAL; |
1197 | ||
1198 | /* Having something in the write domain implies it's in the read | |
1199 | * domain, and only that read domain. Enforce that in the request. | |
1200 | */ | |
1201 | if (write_domain != 0 && read_domains != write_domain) | |
1202 | return -EINVAL; | |
1203 | ||
76c1dec1 | 1204 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1205 | if (ret) |
76c1dec1 | 1206 | return ret; |
1d7cfea1 | 1207 | |
05394f39 | 1208 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1209 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1210 | ret = -ENOENT; |
1211 | goto unlock; | |
76c1dec1 | 1212 | } |
673a394b | 1213 | |
3236f57a CW |
1214 | /* Try to flush the object off the GPU without holding the lock. |
1215 | * We will repeat the flush holding the lock in the normal manner | |
1216 | * to catch cases where we are gazumped. | |
1217 | */ | |
1218 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1219 | if (ret) | |
1220 | goto unref; | |
1221 | ||
2ef7eeaa EA |
1222 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1223 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1224 | |
1225 | /* Silently promote "you're not bound, there was nothing to do" | |
1226 | * to success, since the client was just asking us to | |
1227 | * make sure everything was done. | |
1228 | */ | |
1229 | if (ret == -EINVAL) | |
1230 | ret = 0; | |
2ef7eeaa | 1231 | } else { |
e47c68e9 | 1232 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1233 | } |
1234 | ||
3236f57a | 1235 | unref: |
05394f39 | 1236 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1237 | unlock: |
673a394b EA |
1238 | mutex_unlock(&dev->struct_mutex); |
1239 | return ret; | |
1240 | } | |
1241 | ||
1242 | /** | |
1243 | * Called when user space has done writes to this buffer | |
1244 | */ | |
1245 | int | |
1246 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1247 | struct drm_file *file) |
673a394b EA |
1248 | { |
1249 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1250 | struct drm_i915_gem_object *obj; |
673a394b EA |
1251 | int ret = 0; |
1252 | ||
76c1dec1 | 1253 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1254 | if (ret) |
76c1dec1 | 1255 | return ret; |
1d7cfea1 | 1256 | |
05394f39 | 1257 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1258 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1259 | ret = -ENOENT; |
1260 | goto unlock; | |
673a394b EA |
1261 | } |
1262 | ||
673a394b | 1263 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1264 | if (obj->pin_count) |
e47c68e9 EA |
1265 | i915_gem_object_flush_cpu_write_domain(obj); |
1266 | ||
05394f39 | 1267 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1268 | unlock: |
673a394b EA |
1269 | mutex_unlock(&dev->struct_mutex); |
1270 | return ret; | |
1271 | } | |
1272 | ||
1273 | /** | |
1274 | * Maps the contents of an object, returning the address it is mapped | |
1275 | * into. | |
1276 | * | |
1277 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1278 | * imply a ref on the object itself. | |
1279 | */ | |
1280 | int | |
1281 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1282 | struct drm_file *file) |
673a394b EA |
1283 | { |
1284 | struct drm_i915_gem_mmap *args = data; | |
1285 | struct drm_gem_object *obj; | |
673a394b EA |
1286 | unsigned long addr; |
1287 | ||
05394f39 | 1288 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1289 | if (obj == NULL) |
bf79cb91 | 1290 | return -ENOENT; |
673a394b | 1291 | |
1286ff73 DV |
1292 | /* prime objects have no backing filp to GEM mmap |
1293 | * pages from. | |
1294 | */ | |
1295 | if (!obj->filp) { | |
1296 | drm_gem_object_unreference_unlocked(obj); | |
1297 | return -EINVAL; | |
1298 | } | |
1299 | ||
6be5ceb0 | 1300 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1301 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1302 | args->offset); | |
bc9025bd | 1303 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1304 | if (IS_ERR((void *)addr)) |
1305 | return addr; | |
1306 | ||
1307 | args->addr_ptr = (uint64_t) addr; | |
1308 | ||
1309 | return 0; | |
1310 | } | |
1311 | ||
de151cf6 JB |
1312 | /** |
1313 | * i915_gem_fault - fault a page into the GTT | |
1314 | * vma: VMA in question | |
1315 | * vmf: fault info | |
1316 | * | |
1317 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1318 | * from userspace. The fault handler takes care of binding the object to | |
1319 | * the GTT (if needed), allocating and programming a fence register (again, | |
1320 | * only if needed based on whether the old reg is still valid or the object | |
1321 | * is tiled) and inserting a new PTE into the faulting process. | |
1322 | * | |
1323 | * Note that the faulting process may involve evicting existing objects | |
1324 | * from the GTT and/or fence registers to make room. So performance may | |
1325 | * suffer if the GTT working set is large or there are few fence registers | |
1326 | * left. | |
1327 | */ | |
1328 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1329 | { | |
05394f39 CW |
1330 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1331 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1332 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1333 | pgoff_t page_offset; |
1334 | unsigned long pfn; | |
1335 | int ret = 0; | |
0f973f27 | 1336 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1337 | |
1338 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1339 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1340 | PAGE_SHIFT; | |
1341 | ||
d9bc7e9f CW |
1342 | ret = i915_mutex_lock_interruptible(dev); |
1343 | if (ret) | |
1344 | goto out; | |
a00b10c3 | 1345 | |
db53a302 CW |
1346 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1347 | ||
d9bc7e9f | 1348 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1349 | if (!obj->map_and_fenceable) { |
1350 | ret = i915_gem_object_unbind(obj); | |
1351 | if (ret) | |
1352 | goto unlock; | |
a00b10c3 | 1353 | } |
05394f39 | 1354 | if (!obj->gtt_space) { |
86a1ee26 | 1355 | ret = i915_gem_object_bind_to_gtt(obj, 0, true, false); |
c715089f CW |
1356 | if (ret) |
1357 | goto unlock; | |
de151cf6 | 1358 | |
e92d03bf EA |
1359 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1360 | if (ret) | |
1361 | goto unlock; | |
1362 | } | |
4a684a41 | 1363 | |
74898d7e DV |
1364 | if (!obj->has_global_gtt_mapping) |
1365 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1366 | ||
06d98131 | 1367 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1368 | if (ret) |
1369 | goto unlock; | |
de151cf6 | 1370 | |
05394f39 CW |
1371 | if (i915_gem_object_is_inactive(obj)) |
1372 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1373 | |
6299f992 CW |
1374 | obj->fault_mappable = true; |
1375 | ||
dd2757f8 | 1376 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1377 | page_offset; |
1378 | ||
1379 | /* Finally, remap it using the new GTT offset */ | |
1380 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1381 | unlock: |
de151cf6 | 1382 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1383 | out: |
de151cf6 | 1384 | switch (ret) { |
d9bc7e9f | 1385 | case -EIO: |
a9340cca DV |
1386 | /* If this -EIO is due to a gpu hang, give the reset code a |
1387 | * chance to clean up the mess. Otherwise return the proper | |
1388 | * SIGBUS. */ | |
1389 | if (!atomic_read(&dev_priv->mm.wedged)) | |
1390 | return VM_FAULT_SIGBUS; | |
045e769a | 1391 | case -EAGAIN: |
d9bc7e9f CW |
1392 | /* Give the error handler a chance to run and move the |
1393 | * objects off the GPU active list. Next time we service the | |
1394 | * fault, we should be able to transition the page into the | |
1395 | * GTT without touching the GPU (and so avoid further | |
1396 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1397 | * with coherency, just lost writes. | |
1398 | */ | |
045e769a | 1399 | set_need_resched(); |
c715089f CW |
1400 | case 0: |
1401 | case -ERESTARTSYS: | |
bed636ab | 1402 | case -EINTR: |
e79e0fe3 DR |
1403 | case -EBUSY: |
1404 | /* | |
1405 | * EBUSY is ok: this just means that another thread | |
1406 | * already did the job. | |
1407 | */ | |
c715089f | 1408 | return VM_FAULT_NOPAGE; |
de151cf6 | 1409 | case -ENOMEM: |
de151cf6 | 1410 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1411 | case -ENOSPC: |
1412 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1413 | default: |
a7c2e1aa | 1414 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1415 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1416 | } |
1417 | } | |
1418 | ||
901782b2 CW |
1419 | /** |
1420 | * i915_gem_release_mmap - remove physical page mappings | |
1421 | * @obj: obj in question | |
1422 | * | |
af901ca1 | 1423 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1424 | * relinquish ownership of the pages back to the system. |
1425 | * | |
1426 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1427 | * object through the GTT and then lose the fence register due to | |
1428 | * resource pressure. Similarly if the object has been moved out of the | |
1429 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1430 | * mapping will then trigger a page fault on the next user access, allowing | |
1431 | * fixup by i915_gem_fault(). | |
1432 | */ | |
d05ca301 | 1433 | void |
05394f39 | 1434 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1435 | { |
6299f992 CW |
1436 | if (!obj->fault_mappable) |
1437 | return; | |
901782b2 | 1438 | |
f6e47884 CW |
1439 | if (obj->base.dev->dev_mapping) |
1440 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1441 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1442 | obj->base.size, 1); | |
fb7d516a | 1443 | |
6299f992 | 1444 | obj->fault_mappable = false; |
901782b2 CW |
1445 | } |
1446 | ||
92b88aeb | 1447 | static uint32_t |
e28f8711 | 1448 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1449 | { |
e28f8711 | 1450 | uint32_t gtt_size; |
92b88aeb CW |
1451 | |
1452 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1453 | tiling_mode == I915_TILING_NONE) |
1454 | return size; | |
92b88aeb CW |
1455 | |
1456 | /* Previous chips need a power-of-two fence region when tiling */ | |
1457 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1458 | gtt_size = 1024*1024; |
92b88aeb | 1459 | else |
e28f8711 | 1460 | gtt_size = 512*1024; |
92b88aeb | 1461 | |
e28f8711 CW |
1462 | while (gtt_size < size) |
1463 | gtt_size <<= 1; | |
92b88aeb | 1464 | |
e28f8711 | 1465 | return gtt_size; |
92b88aeb CW |
1466 | } |
1467 | ||
de151cf6 JB |
1468 | /** |
1469 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1470 | * @obj: object to check | |
1471 | * | |
1472 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1473 | * potential fence register mapping. |
de151cf6 JB |
1474 | */ |
1475 | static uint32_t | |
e28f8711 CW |
1476 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1477 | uint32_t size, | |
1478 | int tiling_mode) | |
de151cf6 | 1479 | { |
de151cf6 JB |
1480 | /* |
1481 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1482 | * if a fence register is needed for the object. | |
1483 | */ | |
a00b10c3 | 1484 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1485 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1486 | return 4096; |
1487 | ||
a00b10c3 CW |
1488 | /* |
1489 | * Previous chips need to be aligned to the size of the smallest | |
1490 | * fence register that can contain the object. | |
1491 | */ | |
e28f8711 | 1492 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1493 | } |
1494 | ||
5e783301 DV |
1495 | /** |
1496 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1497 | * unfenced object | |
e28f8711 CW |
1498 | * @dev: the device |
1499 | * @size: size of the object | |
1500 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1501 | * |
1502 | * Return the required GTT alignment for an object, only taking into account | |
1503 | * unfenced tiled surface requirements. | |
1504 | */ | |
467cffba | 1505 | uint32_t |
e28f8711 CW |
1506 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1507 | uint32_t size, | |
1508 | int tiling_mode) | |
5e783301 | 1509 | { |
5e783301 DV |
1510 | /* |
1511 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1512 | */ | |
1513 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1514 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1515 | return 4096; |
1516 | ||
e28f8711 CW |
1517 | /* Previous hardware however needs to be aligned to a power-of-two |
1518 | * tile height. The simplest method for determining this is to reuse | |
1519 | * the power-of-tile object size. | |
5e783301 | 1520 | */ |
e28f8711 | 1521 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1522 | } |
1523 | ||
d8cb5086 CW |
1524 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1525 | { | |
1526 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1527 | int ret; | |
1528 | ||
1529 | if (obj->base.map_list.map) | |
1530 | return 0; | |
1531 | ||
1532 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1533 | if (ret != -ENOSPC) | |
1534 | return ret; | |
1535 | ||
1536 | /* Badly fragmented mmap space? The only way we can recover | |
1537 | * space is by destroying unwanted objects. We can't randomly release | |
1538 | * mmap_offsets as userspace expects them to be persistent for the | |
1539 | * lifetime of the objects. The closest we can is to release the | |
1540 | * offsets on purgeable objects by truncating it and marking it purged, | |
1541 | * which prevents userspace from ever using that object again. | |
1542 | */ | |
1543 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1544 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1545 | if (ret != -ENOSPC) | |
1546 | return ret; | |
1547 | ||
1548 | i915_gem_shrink_all(dev_priv); | |
1549 | return drm_gem_create_mmap_offset(&obj->base); | |
1550 | } | |
1551 | ||
1552 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1553 | { | |
1554 | if (!obj->base.map_list.map) | |
1555 | return; | |
1556 | ||
1557 | drm_gem_free_mmap_offset(&obj->base); | |
1558 | } | |
1559 | ||
de151cf6 | 1560 | int |
ff72145b DA |
1561 | i915_gem_mmap_gtt(struct drm_file *file, |
1562 | struct drm_device *dev, | |
1563 | uint32_t handle, | |
1564 | uint64_t *offset) | |
de151cf6 | 1565 | { |
da761a6e | 1566 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1567 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1568 | int ret; |
1569 | ||
76c1dec1 | 1570 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1571 | if (ret) |
76c1dec1 | 1572 | return ret; |
de151cf6 | 1573 | |
ff72145b | 1574 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1575 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1576 | ret = -ENOENT; |
1577 | goto unlock; | |
1578 | } | |
de151cf6 | 1579 | |
05394f39 | 1580 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1581 | ret = -E2BIG; |
ff56b0bc | 1582 | goto out; |
da761a6e CW |
1583 | } |
1584 | ||
05394f39 | 1585 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1586 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1587 | ret = -EINVAL; |
1588 | goto out; | |
ab18282d CW |
1589 | } |
1590 | ||
d8cb5086 CW |
1591 | ret = i915_gem_object_create_mmap_offset(obj); |
1592 | if (ret) | |
1593 | goto out; | |
de151cf6 | 1594 | |
ff72145b | 1595 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1596 | |
1d7cfea1 | 1597 | out: |
05394f39 | 1598 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1599 | unlock: |
de151cf6 | 1600 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1601 | return ret; |
de151cf6 JB |
1602 | } |
1603 | ||
ff72145b DA |
1604 | /** |
1605 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1606 | * @dev: DRM device | |
1607 | * @data: GTT mapping ioctl data | |
1608 | * @file: GEM object info | |
1609 | * | |
1610 | * Simply returns the fake offset to userspace so it can mmap it. | |
1611 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1612 | * up so we can get faults in the handler above. | |
1613 | * | |
1614 | * The fault handler will take care of binding the object into the GTT | |
1615 | * (since it may have been evicted to make room for something), allocating | |
1616 | * a fence register, and mapping the appropriate aperture address into | |
1617 | * userspace. | |
1618 | */ | |
1619 | int | |
1620 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1621 | struct drm_file *file) | |
1622 | { | |
1623 | struct drm_i915_gem_mmap_gtt *args = data; | |
1624 | ||
ff72145b DA |
1625 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1626 | } | |
1627 | ||
225067ee DV |
1628 | /* Immediately discard the backing storage */ |
1629 | static void | |
1630 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1631 | { |
e5281ccd | 1632 | struct inode *inode; |
e5281ccd | 1633 | |
4d6294bf | 1634 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1635 | |
4d6294bf CW |
1636 | if (obj->base.filp == NULL) |
1637 | return; | |
e5281ccd | 1638 | |
225067ee DV |
1639 | /* Our goal here is to return as much of the memory as |
1640 | * is possible back to the system as we are called from OOM. | |
1641 | * To do this we must instruct the shmfs to drop all of its | |
1642 | * backing pages, *now*. | |
1643 | */ | |
05394f39 | 1644 | inode = obj->base.filp->f_path.dentry->d_inode; |
225067ee | 1645 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1646 | |
225067ee DV |
1647 | obj->madv = __I915_MADV_PURGED; |
1648 | } | |
e5281ccd | 1649 | |
225067ee DV |
1650 | static inline int |
1651 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1652 | { | |
1653 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1654 | } |
1655 | ||
37e680a1 | 1656 | static void |
05394f39 | 1657 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1658 | { |
05394f39 | 1659 | int page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1660 | struct scatterlist *sg; |
6c085a72 | 1661 | int ret, i; |
673a394b | 1662 | |
05394f39 | 1663 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1664 | |
6c085a72 CW |
1665 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1666 | if (ret) { | |
1667 | /* In the event of a disaster, abandon all caches and | |
1668 | * hope for the best. | |
1669 | */ | |
1670 | WARN_ON(ret != -EIO); | |
1671 | i915_gem_clflush_object(obj); | |
1672 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1673 | } | |
1674 | ||
6dacfd2f | 1675 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1676 | i915_gem_object_save_bit_17_swizzle(obj); |
1677 | ||
05394f39 CW |
1678 | if (obj->madv == I915_MADV_DONTNEED) |
1679 | obj->dirty = 0; | |
3ef94daa | 1680 | |
9da3da66 CW |
1681 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
1682 | struct page *page = sg_page(sg); | |
1683 | ||
05394f39 | 1684 | if (obj->dirty) |
9da3da66 | 1685 | set_page_dirty(page); |
3ef94daa | 1686 | |
05394f39 | 1687 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1688 | mark_page_accessed(page); |
3ef94daa | 1689 | |
9da3da66 | 1690 | page_cache_release(page); |
3ef94daa | 1691 | } |
05394f39 | 1692 | obj->dirty = 0; |
673a394b | 1693 | |
9da3da66 CW |
1694 | sg_free_table(obj->pages); |
1695 | kfree(obj->pages); | |
37e680a1 | 1696 | } |
6c085a72 | 1697 | |
37e680a1 CW |
1698 | static int |
1699 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) | |
1700 | { | |
1701 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1702 | ||
2f745ad3 | 1703 | if (obj->pages == NULL) |
37e680a1 CW |
1704 | return 0; |
1705 | ||
1706 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1707 | |
a5570178 CW |
1708 | if (obj->pages_pin_count) |
1709 | return -EBUSY; | |
1710 | ||
37e680a1 | 1711 | ops->put_pages(obj); |
9da3da66 | 1712 | obj->pages = NULL; |
37e680a1 CW |
1713 | |
1714 | list_del(&obj->gtt_list); | |
6c085a72 CW |
1715 | if (i915_gem_object_is_purgeable(obj)) |
1716 | i915_gem_object_truncate(obj); | |
1717 | ||
1718 | return 0; | |
1719 | } | |
1720 | ||
1721 | static long | |
1722 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1723 | { | |
1724 | struct drm_i915_gem_object *obj, *next; | |
1725 | long count = 0; | |
1726 | ||
1727 | list_for_each_entry_safe(obj, next, | |
1728 | &dev_priv->mm.unbound_list, | |
1729 | gtt_list) { | |
1730 | if (i915_gem_object_is_purgeable(obj) && | |
37e680a1 | 1731 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1732 | count += obj->base.size >> PAGE_SHIFT; |
1733 | if (count >= target) | |
1734 | return count; | |
1735 | } | |
1736 | } | |
1737 | ||
1738 | list_for_each_entry_safe(obj, next, | |
1739 | &dev_priv->mm.inactive_list, | |
1740 | mm_list) { | |
1741 | if (i915_gem_object_is_purgeable(obj) && | |
1742 | i915_gem_object_unbind(obj) == 0 && | |
37e680a1 | 1743 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1744 | count += obj->base.size >> PAGE_SHIFT; |
1745 | if (count >= target) | |
1746 | return count; | |
1747 | } | |
1748 | } | |
1749 | ||
1750 | return count; | |
1751 | } | |
1752 | ||
1753 | static void | |
1754 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1755 | { | |
1756 | struct drm_i915_gem_object *obj, *next; | |
1757 | ||
1758 | i915_gem_evict_everything(dev_priv->dev); | |
1759 | ||
1760 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1761 | i915_gem_object_put_pages(obj); |
225067ee DV |
1762 | } |
1763 | ||
37e680a1 | 1764 | static int |
6c085a72 | 1765 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1766 | { |
6c085a72 | 1767 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1768 | int page_count, i; |
1769 | struct address_space *mapping; | |
9da3da66 CW |
1770 | struct sg_table *st; |
1771 | struct scatterlist *sg; | |
e5281ccd | 1772 | struct page *page; |
6c085a72 | 1773 | gfp_t gfp; |
e5281ccd | 1774 | |
6c085a72 CW |
1775 | /* Assert that the object is not currently in any GPU domain. As it |
1776 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1777 | * a GPU cache | |
1778 | */ | |
1779 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1780 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1781 | ||
9da3da66 CW |
1782 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1783 | if (st == NULL) | |
1784 | return -ENOMEM; | |
1785 | ||
05394f39 | 1786 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1787 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1788 | sg_free_table(st); | |
1789 | kfree(st); | |
e5281ccd | 1790 | return -ENOMEM; |
9da3da66 | 1791 | } |
e5281ccd | 1792 | |
9da3da66 CW |
1793 | /* Get the list of pages out of our struct file. They'll be pinned |
1794 | * at this point until we release them. | |
1795 | * | |
1796 | * Fail silently without starting the shrinker | |
1797 | */ | |
6c085a72 CW |
1798 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
1799 | gfp = mapping_gfp_mask(mapping); | |
d7c3b937 | 1800 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 | 1801 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
9da3da66 | 1802 | for_each_sg(st->sgl, sg, page_count, i) { |
6c085a72 CW |
1803 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1804 | if (IS_ERR(page)) { | |
1805 | i915_gem_purge(dev_priv, page_count); | |
1806 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1807 | } | |
1808 | if (IS_ERR(page)) { | |
1809 | /* We've tried hard to allocate the memory by reaping | |
1810 | * our own buffer, now let the real VM do its job and | |
1811 | * go down in flames if truly OOM. | |
1812 | */ | |
d7c3b937 | 1813 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN); |
6c085a72 CW |
1814 | gfp |= __GFP_IO | __GFP_WAIT; |
1815 | ||
1816 | i915_gem_shrink_all(dev_priv); | |
1817 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1818 | if (IS_ERR(page)) | |
1819 | goto err_pages; | |
1820 | ||
d7c3b937 | 1821 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 CW |
1822 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1823 | } | |
e5281ccd | 1824 | |
9da3da66 | 1825 | sg_set_page(sg, page, PAGE_SIZE, 0); |
e5281ccd CW |
1826 | } |
1827 | ||
74ce6b6c CW |
1828 | obj->pages = st; |
1829 | ||
6dacfd2f | 1830 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1831 | i915_gem_object_do_bit_17_swizzle(obj); |
1832 | ||
1833 | return 0; | |
1834 | ||
1835 | err_pages: | |
9da3da66 CW |
1836 | for_each_sg(st->sgl, sg, i, page_count) |
1837 | page_cache_release(sg_page(sg)); | |
1838 | sg_free_table(st); | |
1839 | kfree(st); | |
e5281ccd | 1840 | return PTR_ERR(page); |
673a394b EA |
1841 | } |
1842 | ||
37e680a1 CW |
1843 | /* Ensure that the associated pages are gathered from the backing storage |
1844 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1845 | * multiple times before they are released by a single call to | |
1846 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1847 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1848 | * or as the object is itself released. | |
1849 | */ | |
1850 | int | |
1851 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1852 | { | |
1853 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1854 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1855 | int ret; | |
1856 | ||
2f745ad3 | 1857 | if (obj->pages) |
37e680a1 CW |
1858 | return 0; |
1859 | ||
a5570178 CW |
1860 | BUG_ON(obj->pages_pin_count); |
1861 | ||
37e680a1 CW |
1862 | ret = ops->get_pages(obj); |
1863 | if (ret) | |
1864 | return ret; | |
1865 | ||
1866 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1867 | return 0; | |
1868 | } | |
1869 | ||
54cf91dc | 1870 | void |
05394f39 | 1871 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1872 | struct intel_ring_buffer *ring, |
1873 | u32 seqno) | |
673a394b | 1874 | { |
05394f39 | 1875 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1877 | |
852835f3 | 1878 | BUG_ON(ring == NULL); |
05394f39 | 1879 | obj->ring = ring; |
673a394b EA |
1880 | |
1881 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1882 | if (!obj->active) { |
1883 | drm_gem_object_reference(&obj->base); | |
1884 | obj->active = 1; | |
673a394b | 1885 | } |
e35a41de | 1886 | |
673a394b | 1887 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1888 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1889 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1890 | |
0201f1ec | 1891 | obj->last_read_seqno = seqno; |
caea7476 | 1892 | |
7dd49065 | 1893 | if (obj->fenced_gpu_access) { |
caea7476 | 1894 | obj->last_fenced_seqno = seqno; |
caea7476 | 1895 | |
7dd49065 CW |
1896 | /* Bump MRU to take account of the delayed flush */ |
1897 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1898 | struct drm_i915_fence_reg *reg; | |
1899 | ||
1900 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1901 | list_move_tail(®->lru_list, | |
1902 | &dev_priv->mm.fence_list); | |
1903 | } | |
caea7476 CW |
1904 | } |
1905 | } | |
1906 | ||
caea7476 CW |
1907 | static void |
1908 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1909 | { | |
1910 | struct drm_device *dev = obj->base.dev; | |
1911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1912 | ||
65ce3027 | 1913 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
caea7476 | 1914 | BUG_ON(!obj->active); |
65ce3027 | 1915 | |
f047e395 CW |
1916 | if (obj->pin_count) /* are we a framebuffer? */ |
1917 | intel_mark_fb_idle(obj); | |
1918 | ||
1919 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1920 | ||
65ce3027 | 1921 | list_del_init(&obj->ring_list); |
caea7476 CW |
1922 | obj->ring = NULL; |
1923 | ||
65ce3027 CW |
1924 | obj->last_read_seqno = 0; |
1925 | obj->last_write_seqno = 0; | |
1926 | obj->base.write_domain = 0; | |
1927 | ||
1928 | obj->last_fenced_seqno = 0; | |
caea7476 | 1929 | obj->fenced_gpu_access = false; |
caea7476 CW |
1930 | |
1931 | obj->active = 0; | |
1932 | drm_gem_object_unreference(&obj->base); | |
1933 | ||
1934 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1935 | } |
673a394b | 1936 | |
53d227f2 DV |
1937 | static u32 |
1938 | i915_gem_get_seqno(struct drm_device *dev) | |
1939 | { | |
1940 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1941 | u32 seqno = dev_priv->next_seqno; | |
1942 | ||
1943 | /* reserve 0 for non-seqno */ | |
1944 | if (++dev_priv->next_seqno == 0) | |
1945 | dev_priv->next_seqno = 1; | |
1946 | ||
1947 | return seqno; | |
1948 | } | |
1949 | ||
1950 | u32 | |
1951 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1952 | { | |
1953 | if (ring->outstanding_lazy_request == 0) | |
1954 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1955 | ||
1956 | return ring->outstanding_lazy_request; | |
1957 | } | |
1958 | ||
3cce469c | 1959 | int |
db53a302 | 1960 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1961 | struct drm_file *file, |
acb868d3 | 1962 | u32 *out_seqno) |
673a394b | 1963 | { |
db53a302 | 1964 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 1965 | struct drm_i915_gem_request *request; |
a71d8d94 | 1966 | u32 request_ring_position; |
acb868d3 | 1967 | u32 seqno; |
673a394b | 1968 | int was_empty; |
3cce469c CW |
1969 | int ret; |
1970 | ||
cc889e0f DV |
1971 | /* |
1972 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1973 | * after having emitted the batchbuffer command. Hence we need to fix | |
1974 | * things up similar to emitting the lazy request. The difference here | |
1975 | * is that the flush _must_ happen before the next request, no matter | |
1976 | * what. | |
1977 | */ | |
a7b9761d CW |
1978 | ret = intel_ring_flush_all_caches(ring); |
1979 | if (ret) | |
1980 | return ret; | |
cc889e0f | 1981 | |
acb868d3 CW |
1982 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
1983 | if (request == NULL) | |
1984 | return -ENOMEM; | |
3bb73aba | 1985 | |
53d227f2 | 1986 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1987 | |
a71d8d94 CW |
1988 | /* Record the position of the start of the request so that |
1989 | * should we detect the updated seqno part-way through the | |
1990 | * GPU processing the request, we never over-estimate the | |
1991 | * position of the head. | |
1992 | */ | |
1993 | request_ring_position = intel_ring_get_tail(ring); | |
1994 | ||
3cce469c | 1995 | ret = ring->add_request(ring, &seqno); |
3bb73aba CW |
1996 | if (ret) { |
1997 | kfree(request); | |
1998 | return ret; | |
1999 | } | |
673a394b | 2000 | |
db53a302 | 2001 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
2002 | |
2003 | request->seqno = seqno; | |
852835f3 | 2004 | request->ring = ring; |
a71d8d94 | 2005 | request->tail = request_ring_position; |
673a394b | 2006 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2007 | was_empty = list_empty(&ring->request_list); |
2008 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2009 | request->file_priv = NULL; |
852835f3 | 2010 | |
db53a302 CW |
2011 | if (file) { |
2012 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2013 | ||
1c25595f | 2014 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2015 | request->file_priv = file_priv; |
b962442e | 2016 | list_add_tail(&request->client_list, |
f787a5f5 | 2017 | &file_priv->mm.request_list); |
1c25595f | 2018 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2019 | } |
673a394b | 2020 | |
5391d0cf | 2021 | ring->outstanding_lazy_request = 0; |
db53a302 | 2022 | |
f65d9421 | 2023 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
2024 | if (i915_enable_hangcheck) { |
2025 | mod_timer(&dev_priv->hangcheck_timer, | |
2026 | jiffies + | |
2027 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
2028 | } | |
f047e395 | 2029 | if (was_empty) { |
b3b079db CW |
2030 | queue_delayed_work(dev_priv->wq, |
2031 | &dev_priv->mm.retire_work, HZ); | |
f047e395 CW |
2032 | intel_mark_busy(dev_priv->dev); |
2033 | } | |
f65d9421 | 2034 | } |
cc889e0f | 2035 | |
acb868d3 CW |
2036 | if (out_seqno) |
2037 | *out_seqno = seqno; | |
3cce469c | 2038 | return 0; |
673a394b EA |
2039 | } |
2040 | ||
f787a5f5 CW |
2041 | static inline void |
2042 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2043 | { |
1c25595f | 2044 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2045 | |
1c25595f CW |
2046 | if (!file_priv) |
2047 | return; | |
1c5d22f7 | 2048 | |
1c25595f | 2049 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2050 | if (request->file_priv) { |
2051 | list_del(&request->client_list); | |
2052 | request->file_priv = NULL; | |
2053 | } | |
1c25595f | 2054 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2055 | } |
673a394b | 2056 | |
dfaae392 CW |
2057 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2058 | struct intel_ring_buffer *ring) | |
9375e446 | 2059 | { |
dfaae392 CW |
2060 | while (!list_empty(&ring->request_list)) { |
2061 | struct drm_i915_gem_request *request; | |
673a394b | 2062 | |
dfaae392 CW |
2063 | request = list_first_entry(&ring->request_list, |
2064 | struct drm_i915_gem_request, | |
2065 | list); | |
de151cf6 | 2066 | |
dfaae392 | 2067 | list_del(&request->list); |
f787a5f5 | 2068 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2069 | kfree(request); |
2070 | } | |
673a394b | 2071 | |
dfaae392 | 2072 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2073 | struct drm_i915_gem_object *obj; |
9375e446 | 2074 | |
05394f39 CW |
2075 | obj = list_first_entry(&ring->active_list, |
2076 | struct drm_i915_gem_object, | |
2077 | ring_list); | |
9375e446 | 2078 | |
05394f39 | 2079 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2080 | } |
2081 | } | |
2082 | ||
312817a3 CW |
2083 | static void i915_gem_reset_fences(struct drm_device *dev) |
2084 | { | |
2085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2086 | int i; | |
2087 | ||
4b9de737 | 2088 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2089 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2090 | |
ada726c7 | 2091 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 2092 | |
ada726c7 CW |
2093 | if (reg->obj) |
2094 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2095 | |
ada726c7 CW |
2096 | reg->pin_count = 0; |
2097 | reg->obj = NULL; | |
2098 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2099 | } |
ada726c7 CW |
2100 | |
2101 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2102 | } |
2103 | ||
069efc1d | 2104 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2105 | { |
77f01230 | 2106 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2107 | struct drm_i915_gem_object *obj; |
b4519513 | 2108 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2109 | int i; |
673a394b | 2110 | |
b4519513 CW |
2111 | for_each_ring(ring, dev_priv, i) |
2112 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2113 | |
dfaae392 CW |
2114 | /* Move everything out of the GPU domains to ensure we do any |
2115 | * necessary invalidation upon reuse. | |
2116 | */ | |
05394f39 | 2117 | list_for_each_entry(obj, |
77f01230 | 2118 | &dev_priv->mm.inactive_list, |
69dc4987 | 2119 | mm_list) |
77f01230 | 2120 | { |
05394f39 | 2121 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2122 | } |
069efc1d CW |
2123 | |
2124 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 2125 | i915_gem_reset_fences(dev); |
673a394b EA |
2126 | } |
2127 | ||
2128 | /** | |
2129 | * This function clears the request list as sequence numbers are passed. | |
2130 | */ | |
a71d8d94 | 2131 | void |
db53a302 | 2132 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2133 | { |
673a394b | 2134 | uint32_t seqno; |
1ec14ad3 | 2135 | int i; |
673a394b | 2136 | |
db53a302 | 2137 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2138 | return; |
2139 | ||
db53a302 | 2140 | WARN_ON(i915_verify_lists(ring->dev)); |
5c81fe85 | 2141 | |
b2eadbc8 | 2142 | seqno = ring->get_seqno(ring, true); |
604dd3ec | 2143 | |
076e2c0e | 2144 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
2145 | if (seqno >= ring->sync_seqno[i]) |
2146 | ring->sync_seqno[i] = 0; | |
5c81fe85 | 2147 | |
852835f3 | 2148 | while (!list_empty(&ring->request_list)) { |
673a394b | 2149 | struct drm_i915_gem_request *request; |
604dd3ec | 2150 | |
852835f3 | 2151 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2152 | struct drm_i915_gem_request, |
2153 | list); | |
5c81fe85 | 2154 | |
dfaae392 | 2155 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c | 2156 | break; |
604dd3ec | 2157 | |
db53a302 | 2158 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2159 | /* We know the GPU must have read the request to have |
2160 | * sent us the seqno + interrupt, so use the position | |
2161 | * of tail of the request to update the last known position | |
2162 | * of the GPU head. | |
2163 | */ | |
2164 | ring->last_retired_head = request->tail; | |
604dd3ec | 2165 | |
b84d5f0c | 2166 | list_del(&request->list); |
f787a5f5 | 2167 | i915_gem_request_remove_from_client(request); |
b84d5f0c | 2168 | kfree(request); |
5c81fe85 BW |
2169 | } |
2170 | ||
b84d5f0c CW |
2171 | /* Move any buffers on the active list that are no longer referenced |
2172 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2173 | */ | |
2174 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2175 | struct drm_i915_gem_object *obj; |
604dd3ec | 2176 | |
0206e353 | 2177 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2178 | struct drm_i915_gem_object, |
2179 | ring_list); | |
673a394b | 2180 | |
0201f1ec | 2181 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2182 | break; |
673a394b | 2183 | |
65ce3027 | 2184 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2185 | } |
3cce469c | 2186 | |
db53a302 CW |
2187 | if (unlikely(ring->trace_irq_seqno && |
2188 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2189 | ring->irq_put(ring); |
db53a302 | 2190 | ring->trace_irq_seqno = 0; |
9d34e5db | 2191 | } |
23bc5982 | 2192 | |
db53a302 | 2193 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2194 | } |
ffed1d09 | 2195 | |
b09a1fec CW |
2196 | void |
2197 | i915_gem_retire_requests(struct drm_device *dev) | |
2198 | { | |
2199 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2200 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2201 | int i; |
673a394b | 2202 | |
b4519513 CW |
2203 | for_each_ring(ring, dev_priv, i) |
2204 | i915_gem_retire_requests_ring(ring); | |
673a394b EA |
2205 | } |
2206 | ||
75ef9da2 | 2207 | static void |
673a394b | 2208 | i915_gem_retire_work_handler(struct work_struct *work) |
673a394b | 2209 | { |
673a394b EA |
2210 | drm_i915_private_t *dev_priv; |
2211 | struct drm_device *dev; | |
b4519513 | 2212 | struct intel_ring_buffer *ring; |
0a58705b CW |
2213 | bool idle; |
2214 | int i; | |
673a394b | 2215 | |
673a394b EA |
2216 | dev_priv = container_of(work, drm_i915_private_t, |
2217 | mm.retire_work.work); | |
2218 | dev = dev_priv->dev; | |
0201f1ec | 2219 | |
891b48cf CW |
2220 | /* Come back later if the device is busy... */ |
2221 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2222 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2223 | return; | |
2224 | } | |
2225 | ||
b09a1fec | 2226 | i915_gem_retire_requests(dev); |
0201f1ec | 2227 | |
0a58705b CW |
2228 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2229 | * objects indefinitely. | |
0201f1ec | 2230 | */ |
0a58705b | 2231 | idle = true; |
b4519513 | 2232 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2233 | if (ring->gpu_caches_dirty) |
2234 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2235 | |
2236 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2237 | } |
2238 | ||
0a58705b | 2239 | if (!dev_priv->mm.suspended && !idle) |
9c9fe1f8 | 2240 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
f047e395 CW |
2241 | if (idle) |
2242 | intel_mark_idle(dev); | |
0a58705b | 2243 | |
673a394b | 2244 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2245 | } |
2246 | ||
30dfebf3 DV |
2247 | /** |
2248 | * Ensures that an object will eventually get non-busy by flushing any required | |
2249 | * write domains, emitting any outstanding lazy request and retiring and | |
2250 | * completed requests. | |
2251 | */ | |
2252 | static int | |
2253 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2254 | { | |
2255 | int ret; | |
2256 | ||
2257 | if (obj->active) { | |
0201f1ec | 2258 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2259 | if (ret) |
2260 | return ret; | |
0201f1ec | 2261 | |
30dfebf3 DV |
2262 | i915_gem_retire_requests_ring(obj->ring); |
2263 | } | |
2264 | ||
2265 | return 0; | |
2266 | } | |
2267 | ||
23ba4fd0 BW |
2268 | /** |
2269 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2270 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2271 | * | |
2272 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2273 | * the timeout parameter. | |
2274 | * -ETIME: object is still busy after timeout | |
2275 | * -ERESTARTSYS: signal interrupted the wait | |
2276 | * -ENONENT: object doesn't exist | |
2277 | * Also possible, but rare: | |
2278 | * -EAGAIN: GPU wedged | |
2279 | * -ENOMEM: damn | |
2280 | * -ENODEV: Internal IRQ fail | |
2281 | * -E?: The add request failed | |
2282 | * | |
2283 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2284 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2285 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2286 | * without holding struct_mutex the object may become re-busied before this | |
2287 | * function completes. A similar but shorter * race condition exists in the busy | |
2288 | * ioctl | |
2289 | */ | |
2290 | int | |
2291 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2292 | { | |
2293 | struct drm_i915_gem_wait *args = data; | |
2294 | struct drm_i915_gem_object *obj; | |
2295 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2296 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2297 | u32 seqno = 0; |
2298 | int ret = 0; | |
2299 | ||
eac1f14f BW |
2300 | if (args->timeout_ns >= 0) { |
2301 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2302 | timeout = &timeout_stack; | |
2303 | } | |
23ba4fd0 BW |
2304 | |
2305 | ret = i915_mutex_lock_interruptible(dev); | |
2306 | if (ret) | |
2307 | return ret; | |
2308 | ||
2309 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2310 | if (&obj->base == NULL) { | |
2311 | mutex_unlock(&dev->struct_mutex); | |
2312 | return -ENOENT; | |
2313 | } | |
2314 | ||
30dfebf3 DV |
2315 | /* Need to make sure the object gets inactive eventually. */ |
2316 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2317 | if (ret) |
2318 | goto out; | |
2319 | ||
2320 | if (obj->active) { | |
0201f1ec | 2321 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2322 | ring = obj->ring; |
2323 | } | |
2324 | ||
2325 | if (seqno == 0) | |
2326 | goto out; | |
2327 | ||
23ba4fd0 BW |
2328 | /* Do this after OLR check to make sure we make forward progress polling |
2329 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2330 | */ | |
2331 | if (!args->timeout_ns) { | |
2332 | ret = -ETIME; | |
2333 | goto out; | |
2334 | } | |
2335 | ||
2336 | drm_gem_object_unreference(&obj->base); | |
2337 | mutex_unlock(&dev->struct_mutex); | |
2338 | ||
eac1f14f BW |
2339 | ret = __wait_seqno(ring, seqno, true, timeout); |
2340 | if (timeout) { | |
2341 | WARN_ON(!timespec_valid(timeout)); | |
2342 | args->timeout_ns = timespec_to_ns(timeout); | |
2343 | } | |
23ba4fd0 BW |
2344 | return ret; |
2345 | ||
2346 | out: | |
2347 | drm_gem_object_unreference(&obj->base); | |
2348 | mutex_unlock(&dev->struct_mutex); | |
2349 | return ret; | |
2350 | } | |
2351 | ||
5816d648 BW |
2352 | /** |
2353 | * i915_gem_object_sync - sync an object to a ring. | |
2354 | * | |
2355 | * @obj: object which may be in use on another ring. | |
2356 | * @to: ring we wish to use the object on. May be NULL. | |
2357 | * | |
2358 | * This code is meant to abstract object synchronization with the GPU. | |
2359 | * Calling with NULL implies synchronizing the object with the CPU | |
2360 | * rather than a particular GPU ring. | |
2361 | * | |
2362 | * Returns 0 if successful, else propagates up the lower layer error. | |
2363 | */ | |
2911a35b BW |
2364 | int |
2365 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2366 | struct intel_ring_buffer *to) | |
2367 | { | |
2368 | struct intel_ring_buffer *from = obj->ring; | |
2369 | u32 seqno; | |
2370 | int ret, idx; | |
2371 | ||
2372 | if (from == NULL || to == from) | |
2373 | return 0; | |
2374 | ||
5816d648 | 2375 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2376 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2377 | |
2378 | idx = intel_ring_sync_index(from, to); | |
2379 | ||
0201f1ec | 2380 | seqno = obj->last_read_seqno; |
2911a35b BW |
2381 | if (seqno <= from->sync_seqno[idx]) |
2382 | return 0; | |
2383 | ||
b4aca010 BW |
2384 | ret = i915_gem_check_olr(obj->ring, seqno); |
2385 | if (ret) | |
2386 | return ret; | |
2911a35b | 2387 | |
1500f7ea | 2388 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
2389 | if (!ret) |
2390 | from->sync_seqno[idx] = seqno; | |
2911a35b | 2391 | |
e3a5a225 | 2392 | return ret; |
2911a35b BW |
2393 | } |
2394 | ||
b5ffc9bc CW |
2395 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2396 | { | |
2397 | u32 old_write_domain, old_read_domains; | |
2398 | ||
b5ffc9bc CW |
2399 | /* Act a barrier for all accesses through the GTT */ |
2400 | mb(); | |
2401 | ||
2402 | /* Force a pagefault for domain tracking on next user access */ | |
2403 | i915_gem_release_mmap(obj); | |
2404 | ||
b97c3d9c KP |
2405 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2406 | return; | |
2407 | ||
b5ffc9bc CW |
2408 | old_read_domains = obj->base.read_domains; |
2409 | old_write_domain = obj->base.write_domain; | |
2410 | ||
2411 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2412 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2413 | ||
2414 | trace_i915_gem_object_change_domain(obj, | |
2415 | old_read_domains, | |
2416 | old_write_domain); | |
2417 | } | |
2418 | ||
673a394b EA |
2419 | /** |
2420 | * Unbinds an object from the GTT aperture. | |
2421 | */ | |
0f973f27 | 2422 | int |
05394f39 | 2423 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2424 | { |
7bddb01f | 2425 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2426 | int ret = 0; |
2427 | ||
05394f39 | 2428 | if (obj->gtt_space == NULL) |
673a394b EA |
2429 | return 0; |
2430 | ||
31d8d651 CW |
2431 | if (obj->pin_count) |
2432 | return -EBUSY; | |
673a394b | 2433 | |
c4670ad0 CW |
2434 | BUG_ON(obj->pages == NULL); |
2435 | ||
a8198eea | 2436 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2437 | if (ret) |
a8198eea CW |
2438 | return ret; |
2439 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2440 | * should be safe and we need to cleanup or else we might | |
2441 | * cause memory corruption through use-after-free. | |
2442 | */ | |
2443 | ||
b5ffc9bc | 2444 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2445 | |
96b47b65 | 2446 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2447 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2448 | if (ret) |
d9e86c0e | 2449 | return ret; |
96b47b65 | 2450 | |
db53a302 CW |
2451 | trace_i915_gem_object_unbind(obj); |
2452 | ||
74898d7e DV |
2453 | if (obj->has_global_gtt_mapping) |
2454 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2455 | if (obj->has_aliasing_ppgtt_mapping) { |
2456 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2457 | obj->has_aliasing_ppgtt_mapping = 0; | |
2458 | } | |
74163907 | 2459 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2460 | |
6c085a72 CW |
2461 | list_del(&obj->mm_list); |
2462 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2463 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2464 | obj->map_and_fenceable = true; |
673a394b | 2465 | |
05394f39 CW |
2466 | drm_mm_put_block(obj->gtt_space); |
2467 | obj->gtt_space = NULL; | |
2468 | obj->gtt_offset = 0; | |
673a394b | 2469 | |
6c085a72 | 2470 | return 0; |
673a394b EA |
2471 | } |
2472 | ||
b2da9fe5 | 2473 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2474 | { |
69c2fc89 | 2475 | if (list_empty(&ring->active_list)) |
64193406 CW |
2476 | return 0; |
2477 | ||
199b2bc2 | 2478 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2479 | } |
2480 | ||
b2da9fe5 | 2481 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2482 | { |
2483 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2484 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2485 | int ret, i; |
4df2faf4 | 2486 | |
4df2faf4 | 2487 | /* Flush everything onto the inactive list. */ |
b4519513 | 2488 | for_each_ring(ring, dev_priv, i) { |
b6c7488d | 2489 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
1ec14ad3 CW |
2490 | if (ret) |
2491 | return ret; | |
b4519513 | 2492 | |
b4519513 | 2493 | ret = i915_ring_idle(ring); |
f2ef6eb1 BW |
2494 | if (ret) |
2495 | return ret; | |
1ec14ad3 | 2496 | } |
4df2faf4 | 2497 | |
8a1a49f9 | 2498 | return 0; |
4df2faf4 DV |
2499 | } |
2500 | ||
9ce079e4 CW |
2501 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2502 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2503 | { |
4e901fdc | 2504 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2505 | uint64_t val; |
2506 | ||
9ce079e4 CW |
2507 | if (obj) { |
2508 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2509 | |
9ce079e4 CW |
2510 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2511 | 0xfffff000) << 32; | |
2512 | val |= obj->gtt_offset & 0xfffff000; | |
2513 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2514 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2515 | |
9ce079e4 CW |
2516 | if (obj->tiling_mode == I915_TILING_Y) |
2517 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2518 | val |= I965_FENCE_REG_VALID; | |
2519 | } else | |
2520 | val = 0; | |
c6642782 | 2521 | |
9ce079e4 CW |
2522 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2523 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2524 | } |
2525 | ||
9ce079e4 CW |
2526 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2527 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2528 | { |
de151cf6 | 2529 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2530 | uint64_t val; |
2531 | ||
9ce079e4 CW |
2532 | if (obj) { |
2533 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2534 | |
9ce079e4 CW |
2535 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2536 | 0xfffff000) << 32; | |
2537 | val |= obj->gtt_offset & 0xfffff000; | |
2538 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2539 | if (obj->tiling_mode == I915_TILING_Y) | |
2540 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2541 | val |= I965_FENCE_REG_VALID; | |
2542 | } else | |
2543 | val = 0; | |
c6642782 | 2544 | |
9ce079e4 CW |
2545 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2546 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2547 | } |
2548 | ||
9ce079e4 CW |
2549 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2550 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2551 | { |
de151cf6 | 2552 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2553 | u32 val; |
de151cf6 | 2554 | |
9ce079e4 CW |
2555 | if (obj) { |
2556 | u32 size = obj->gtt_space->size; | |
2557 | int pitch_val; | |
2558 | int tile_width; | |
c6642782 | 2559 | |
9ce079e4 CW |
2560 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2561 | (size & -size) != size || | |
2562 | (obj->gtt_offset & (size - 1)), | |
2563 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2564 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2565 | |
9ce079e4 CW |
2566 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2567 | tile_width = 128; | |
2568 | else | |
2569 | tile_width = 512; | |
2570 | ||
2571 | /* Note: pitch better be a power of two tile widths */ | |
2572 | pitch_val = obj->stride / tile_width; | |
2573 | pitch_val = ffs(pitch_val) - 1; | |
2574 | ||
2575 | val = obj->gtt_offset; | |
2576 | if (obj->tiling_mode == I915_TILING_Y) | |
2577 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2578 | val |= I915_FENCE_SIZE_BITS(size); | |
2579 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2580 | val |= I830_FENCE_REG_VALID; | |
2581 | } else | |
2582 | val = 0; | |
2583 | ||
2584 | if (reg < 8) | |
2585 | reg = FENCE_REG_830_0 + reg * 4; | |
2586 | else | |
2587 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2588 | ||
2589 | I915_WRITE(reg, val); | |
2590 | POSTING_READ(reg); | |
de151cf6 JB |
2591 | } |
2592 | ||
9ce079e4 CW |
2593 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2594 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2595 | { |
de151cf6 | 2596 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2597 | uint32_t val; |
de151cf6 | 2598 | |
9ce079e4 CW |
2599 | if (obj) { |
2600 | u32 size = obj->gtt_space->size; | |
2601 | uint32_t pitch_val; | |
de151cf6 | 2602 | |
9ce079e4 CW |
2603 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2604 | (size & -size) != size || | |
2605 | (obj->gtt_offset & (size - 1)), | |
2606 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2607 | obj->gtt_offset, size); | |
e76a16de | 2608 | |
9ce079e4 CW |
2609 | pitch_val = obj->stride / 128; |
2610 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2611 | |
9ce079e4 CW |
2612 | val = obj->gtt_offset; |
2613 | if (obj->tiling_mode == I915_TILING_Y) | |
2614 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2615 | val |= I830_FENCE_SIZE_BITS(size); | |
2616 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2617 | val |= I830_FENCE_REG_VALID; | |
2618 | } else | |
2619 | val = 0; | |
c6642782 | 2620 | |
9ce079e4 CW |
2621 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2622 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2623 | } | |
2624 | ||
2625 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2626 | struct drm_i915_gem_object *obj) | |
2627 | { | |
2628 | switch (INTEL_INFO(dev)->gen) { | |
2629 | case 7: | |
2630 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2631 | case 5: | |
2632 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2633 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2634 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2635 | default: break; | |
2636 | } | |
de151cf6 JB |
2637 | } |
2638 | ||
61050808 CW |
2639 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2640 | struct drm_i915_fence_reg *fence) | |
2641 | { | |
2642 | return fence - dev_priv->fence_regs; | |
2643 | } | |
2644 | ||
2645 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2646 | struct drm_i915_fence_reg *fence, | |
2647 | bool enable) | |
2648 | { | |
2649 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2650 | int reg = fence_number(dev_priv, fence); | |
2651 | ||
2652 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2653 | ||
2654 | if (enable) { | |
2655 | obj->fence_reg = reg; | |
2656 | fence->obj = obj; | |
2657 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2658 | } else { | |
2659 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2660 | fence->obj = NULL; | |
2661 | list_del_init(&fence->lru_list); | |
2662 | } | |
2663 | } | |
2664 | ||
d9e86c0e | 2665 | static int |
a360bb1a | 2666 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2667 | { |
1c293ea3 | 2668 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2669 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2670 | if (ret) |
2671 | return ret; | |
d9e86c0e CW |
2672 | |
2673 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2674 | } |
2675 | ||
63256ec5 CW |
2676 | /* Ensure that all CPU reads are completed before installing a fence |
2677 | * and all writes before removing the fence. | |
2678 | */ | |
2679 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2680 | mb(); | |
2681 | ||
86d5bc37 | 2682 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2683 | return 0; |
2684 | } | |
2685 | ||
2686 | int | |
2687 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2688 | { | |
61050808 | 2689 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2690 | int ret; |
2691 | ||
a360bb1a | 2692 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2693 | if (ret) |
2694 | return ret; | |
2695 | ||
61050808 CW |
2696 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2697 | return 0; | |
d9e86c0e | 2698 | |
61050808 CW |
2699 | i915_gem_object_update_fence(obj, |
2700 | &dev_priv->fence_regs[obj->fence_reg], | |
2701 | false); | |
2702 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2703 | |
2704 | return 0; | |
2705 | } | |
2706 | ||
2707 | static struct drm_i915_fence_reg * | |
a360bb1a | 2708 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2709 | { |
ae3db24a | 2710 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2711 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2712 | int i; |
ae3db24a DV |
2713 | |
2714 | /* First try to find a free reg */ | |
d9e86c0e | 2715 | avail = NULL; |
ae3db24a DV |
2716 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2717 | reg = &dev_priv->fence_regs[i]; | |
2718 | if (!reg->obj) | |
d9e86c0e | 2719 | return reg; |
ae3db24a | 2720 | |
1690e1eb | 2721 | if (!reg->pin_count) |
d9e86c0e | 2722 | avail = reg; |
ae3db24a DV |
2723 | } |
2724 | ||
d9e86c0e CW |
2725 | if (avail == NULL) |
2726 | return NULL; | |
ae3db24a DV |
2727 | |
2728 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2729 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2730 | if (reg->pin_count) |
ae3db24a DV |
2731 | continue; |
2732 | ||
8fe301ad | 2733 | return reg; |
ae3db24a DV |
2734 | } |
2735 | ||
8fe301ad | 2736 | return NULL; |
ae3db24a DV |
2737 | } |
2738 | ||
de151cf6 | 2739 | /** |
9a5a53b3 | 2740 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2741 | * @obj: object to map through a fence reg |
2742 | * | |
2743 | * When mapping objects through the GTT, userspace wants to be able to write | |
2744 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2745 | * This function walks the fence regs looking for a free one for @obj, |
2746 | * stealing one if it can't find any. | |
2747 | * | |
2748 | * It then sets up the reg based on the object's properties: address, pitch | |
2749 | * and tiling format. | |
9a5a53b3 CW |
2750 | * |
2751 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2752 | */ |
8c4b8c3f | 2753 | int |
06d98131 | 2754 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2755 | { |
05394f39 | 2756 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2757 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2758 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2759 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2760 | int ret; |
de151cf6 | 2761 | |
14415745 CW |
2762 | /* Have we updated the tiling parameters upon the object and so |
2763 | * will need to serialise the write to the associated fence register? | |
2764 | */ | |
5d82e3e6 | 2765 | if (obj->fence_dirty) { |
14415745 CW |
2766 | ret = i915_gem_object_flush_fence(obj); |
2767 | if (ret) | |
2768 | return ret; | |
2769 | } | |
9a5a53b3 | 2770 | |
d9e86c0e | 2771 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2772 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2773 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2774 | if (!obj->fence_dirty) { |
14415745 CW |
2775 | list_move_tail(®->lru_list, |
2776 | &dev_priv->mm.fence_list); | |
2777 | return 0; | |
2778 | } | |
2779 | } else if (enable) { | |
2780 | reg = i915_find_fence_reg(dev); | |
2781 | if (reg == NULL) | |
2782 | return -EDEADLK; | |
d9e86c0e | 2783 | |
14415745 CW |
2784 | if (reg->obj) { |
2785 | struct drm_i915_gem_object *old = reg->obj; | |
2786 | ||
2787 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2788 | if (ret) |
2789 | return ret; | |
2790 | ||
14415745 | 2791 | i915_gem_object_fence_lost(old); |
29c5a587 | 2792 | } |
14415745 | 2793 | } else |
a09ba7fa | 2794 | return 0; |
a09ba7fa | 2795 | |
14415745 | 2796 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2797 | obj->fence_dirty = false; |
14415745 | 2798 | |
9ce079e4 | 2799 | return 0; |
de151cf6 JB |
2800 | } |
2801 | ||
42d6ab48 CW |
2802 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2803 | struct drm_mm_node *gtt_space, | |
2804 | unsigned long cache_level) | |
2805 | { | |
2806 | struct drm_mm_node *other; | |
2807 | ||
2808 | /* On non-LLC machines we have to be careful when putting differing | |
2809 | * types of snoopable memory together to avoid the prefetcher | |
2810 | * crossing memory domains and dieing. | |
2811 | */ | |
2812 | if (HAS_LLC(dev)) | |
2813 | return true; | |
2814 | ||
2815 | if (gtt_space == NULL) | |
2816 | return true; | |
2817 | ||
2818 | if (list_empty(>t_space->node_list)) | |
2819 | return true; | |
2820 | ||
2821 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2822 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2823 | return false; | |
2824 | ||
2825 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2826 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2827 | return false; | |
2828 | ||
2829 | return true; | |
2830 | } | |
2831 | ||
2832 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2833 | { | |
2834 | #if WATCH_GTT | |
2835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2836 | struct drm_i915_gem_object *obj; | |
2837 | int err = 0; | |
2838 | ||
2839 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2840 | if (obj->gtt_space == NULL) { | |
2841 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2842 | err++; | |
2843 | continue; | |
2844 | } | |
2845 | ||
2846 | if (obj->cache_level != obj->gtt_space->color) { | |
2847 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2848 | obj->gtt_space->start, | |
2849 | obj->gtt_space->start + obj->gtt_space->size, | |
2850 | obj->cache_level, | |
2851 | obj->gtt_space->color); | |
2852 | err++; | |
2853 | continue; | |
2854 | } | |
2855 | ||
2856 | if (!i915_gem_valid_gtt_space(dev, | |
2857 | obj->gtt_space, | |
2858 | obj->cache_level)) { | |
2859 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2860 | obj->gtt_space->start, | |
2861 | obj->gtt_space->start + obj->gtt_space->size, | |
2862 | obj->cache_level); | |
2863 | err++; | |
2864 | continue; | |
2865 | } | |
2866 | } | |
2867 | ||
2868 | WARN_ON(err); | |
2869 | #endif | |
2870 | } | |
2871 | ||
673a394b EA |
2872 | /** |
2873 | * Finds free space in the GTT aperture and binds the object there. | |
2874 | */ | |
2875 | static int | |
05394f39 | 2876 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2877 | unsigned alignment, |
86a1ee26 CW |
2878 | bool map_and_fenceable, |
2879 | bool nonblocking) | |
673a394b | 2880 | { |
05394f39 | 2881 | struct drm_device *dev = obj->base.dev; |
673a394b | 2882 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2883 | struct drm_mm_node *free_space; |
5e783301 | 2884 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2885 | bool mappable, fenceable; |
07f73f69 | 2886 | int ret; |
673a394b | 2887 | |
05394f39 | 2888 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2889 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2890 | return -EINVAL; | |
2891 | } | |
2892 | ||
e28f8711 CW |
2893 | fence_size = i915_gem_get_gtt_size(dev, |
2894 | obj->base.size, | |
2895 | obj->tiling_mode); | |
2896 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2897 | obj->base.size, | |
2898 | obj->tiling_mode); | |
2899 | unfenced_alignment = | |
2900 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2901 | obj->base.size, | |
2902 | obj->tiling_mode); | |
a00b10c3 | 2903 | |
673a394b | 2904 | if (alignment == 0) |
5e783301 DV |
2905 | alignment = map_and_fenceable ? fence_alignment : |
2906 | unfenced_alignment; | |
75e9e915 | 2907 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2908 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2909 | return -EINVAL; | |
2910 | } | |
2911 | ||
05394f39 | 2912 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2913 | |
654fc607 CW |
2914 | /* If the object is bigger than the entire aperture, reject it early |
2915 | * before evicting everything in a vain attempt to find space. | |
2916 | */ | |
05394f39 | 2917 | if (obj->base.size > |
75e9e915 | 2918 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2919 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2920 | return -E2BIG; | |
2921 | } | |
2922 | ||
37e680a1 | 2923 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2924 | if (ret) |
2925 | return ret; | |
2926 | ||
673a394b | 2927 | search_free: |
75e9e915 | 2928 | if (map_and_fenceable) |
920afa77 | 2929 | free_space = |
42d6ab48 CW |
2930 | drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space, |
2931 | size, alignment, obj->cache_level, | |
2932 | 0, dev_priv->mm.gtt_mappable_end, | |
2933 | false); | |
920afa77 | 2934 | else |
42d6ab48 CW |
2935 | free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space, |
2936 | size, alignment, obj->cache_level, | |
2937 | false); | |
920afa77 DV |
2938 | |
2939 | if (free_space != NULL) { | |
75e9e915 | 2940 | if (map_and_fenceable) |
05394f39 | 2941 | obj->gtt_space = |
920afa77 | 2942 | drm_mm_get_block_range_generic(free_space, |
42d6ab48 | 2943 | size, alignment, obj->cache_level, |
6b9d89b4 | 2944 | 0, dev_priv->mm.gtt_mappable_end, |
42d6ab48 | 2945 | false); |
920afa77 | 2946 | else |
05394f39 | 2947 | obj->gtt_space = |
42d6ab48 CW |
2948 | drm_mm_get_block_generic(free_space, |
2949 | size, alignment, obj->cache_level, | |
2950 | false); | |
920afa77 | 2951 | } |
05394f39 | 2952 | if (obj->gtt_space == NULL) { |
75e9e915 | 2953 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2954 | obj->cache_level, |
86a1ee26 CW |
2955 | map_and_fenceable, |
2956 | nonblocking); | |
9731129c | 2957 | if (ret) |
673a394b | 2958 | return ret; |
9731129c | 2959 | |
673a394b EA |
2960 | goto search_free; |
2961 | } | |
42d6ab48 CW |
2962 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, |
2963 | obj->gtt_space, | |
2964 | obj->cache_level))) { | |
2965 | drm_mm_put_block(obj->gtt_space); | |
2966 | obj->gtt_space = NULL; | |
2967 | return -EINVAL; | |
2968 | } | |
673a394b | 2969 | |
673a394b | 2970 | |
74163907 | 2971 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2972 | if (ret) { |
05394f39 CW |
2973 | drm_mm_put_block(obj->gtt_space); |
2974 | obj->gtt_space = NULL; | |
6c085a72 | 2975 | return ret; |
673a394b | 2976 | } |
673a394b | 2977 | |
0ebb9829 DV |
2978 | if (!dev_priv->mm.aliasing_ppgtt) |
2979 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2980 | |
6c085a72 | 2981 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2982 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2983 | |
6299f992 | 2984 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2985 | |
75e9e915 | 2986 | fenceable = |
05394f39 | 2987 | obj->gtt_space->size == fence_size && |
0206e353 | 2988 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2989 | |
75e9e915 | 2990 | mappable = |
05394f39 | 2991 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2992 | |
05394f39 | 2993 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2994 | |
db53a302 | 2995 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 2996 | i915_gem_verify_gtt(dev); |
673a394b EA |
2997 | return 0; |
2998 | } | |
2999 | ||
3000 | void | |
05394f39 | 3001 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 3002 | { |
673a394b EA |
3003 | /* If we don't have a page list set up, then we're not pinned |
3004 | * to GPU, and we can ignore the cache flush because it'll happen | |
3005 | * again at bind time. | |
3006 | */ | |
05394f39 | 3007 | if (obj->pages == NULL) |
673a394b EA |
3008 | return; |
3009 | ||
9c23f7fc CW |
3010 | /* If the GPU is snooping the contents of the CPU cache, |
3011 | * we do not need to manually clear the CPU cache lines. However, | |
3012 | * the caches are only snooped when the render cache is | |
3013 | * flushed/invalidated. As we always have to emit invalidations | |
3014 | * and flushes when moving into and out of the RENDER domain, correct | |
3015 | * snooping behaviour occurs naturally as the result of our domain | |
3016 | * tracking. | |
3017 | */ | |
3018 | if (obj->cache_level != I915_CACHE_NONE) | |
3019 | return; | |
3020 | ||
1c5d22f7 | 3021 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3022 | |
9da3da66 | 3023 | drm_clflush_sg(obj->pages); |
673a394b EA |
3024 | } |
3025 | ||
e47c68e9 EA |
3026 | /** Flushes the GTT write domain for the object if it's dirty. */ |
3027 | static void | |
05394f39 | 3028 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3029 | { |
1c5d22f7 CW |
3030 | uint32_t old_write_domain; |
3031 | ||
05394f39 | 3032 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3033 | return; |
3034 | ||
63256ec5 | 3035 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3036 | * to it immediately go to main memory as far as we know, so there's |
3037 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3038 | * |
3039 | * However, we do have to enforce the order so that all writes through | |
3040 | * the GTT land before any writes to the device, such as updates to | |
3041 | * the GATT itself. | |
e47c68e9 | 3042 | */ |
63256ec5 CW |
3043 | wmb(); |
3044 | ||
05394f39 CW |
3045 | old_write_domain = obj->base.write_domain; |
3046 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3047 | |
3048 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3049 | obj->base.read_domains, |
1c5d22f7 | 3050 | old_write_domain); |
e47c68e9 EA |
3051 | } |
3052 | ||
3053 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3054 | static void | |
05394f39 | 3055 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3056 | { |
1c5d22f7 | 3057 | uint32_t old_write_domain; |
e47c68e9 | 3058 | |
05394f39 | 3059 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3060 | return; |
3061 | ||
3062 | i915_gem_clflush_object(obj); | |
40ce6575 | 3063 | intel_gtt_chipset_flush(); |
05394f39 CW |
3064 | old_write_domain = obj->base.write_domain; |
3065 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3066 | |
3067 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3068 | obj->base.read_domains, |
1c5d22f7 | 3069 | old_write_domain); |
e47c68e9 EA |
3070 | } |
3071 | ||
2ef7eeaa EA |
3072 | /** |
3073 | * Moves a single object to the GTT read, and possibly write domain. | |
3074 | * | |
3075 | * This function returns when the move is complete, including waiting on | |
3076 | * flushes to occur. | |
3077 | */ | |
79e53945 | 3078 | int |
2021746e | 3079 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3080 | { |
8325a09d | 3081 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3082 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3083 | int ret; |
2ef7eeaa | 3084 | |
02354392 | 3085 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3086 | if (obj->gtt_space == NULL) |
02354392 EA |
3087 | return -EINVAL; |
3088 | ||
8d7e3de1 CW |
3089 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3090 | return 0; | |
3091 | ||
0201f1ec CW |
3092 | ret = i915_gem_object_wait_rendering(obj, !write); |
3093 | if (ret) | |
3094 | return ret; | |
2dafb1e0 | 3095 | |
7213342d | 3096 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3097 | |
05394f39 CW |
3098 | old_write_domain = obj->base.write_domain; |
3099 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3100 | |
e47c68e9 EA |
3101 | /* It should now be out of any other write domains, and we can update |
3102 | * the domain values for our changes. | |
3103 | */ | |
05394f39 CW |
3104 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3105 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3106 | if (write) { |
05394f39 CW |
3107 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3108 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3109 | obj->dirty = 1; | |
2ef7eeaa EA |
3110 | } |
3111 | ||
1c5d22f7 CW |
3112 | trace_i915_gem_object_change_domain(obj, |
3113 | old_read_domains, | |
3114 | old_write_domain); | |
3115 | ||
8325a09d CW |
3116 | /* And bump the LRU for this access */ |
3117 | if (i915_gem_object_is_inactive(obj)) | |
3118 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3119 | ||
e47c68e9 EA |
3120 | return 0; |
3121 | } | |
3122 | ||
e4ffd173 CW |
3123 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3124 | enum i915_cache_level cache_level) | |
3125 | { | |
7bddb01f DV |
3126 | struct drm_device *dev = obj->base.dev; |
3127 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3128 | int ret; |
3129 | ||
3130 | if (obj->cache_level == cache_level) | |
3131 | return 0; | |
3132 | ||
3133 | if (obj->pin_count) { | |
3134 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3135 | return -EBUSY; | |
3136 | } | |
3137 | ||
42d6ab48 CW |
3138 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3139 | ret = i915_gem_object_unbind(obj); | |
3140 | if (ret) | |
3141 | return ret; | |
3142 | } | |
3143 | ||
e4ffd173 CW |
3144 | if (obj->gtt_space) { |
3145 | ret = i915_gem_object_finish_gpu(obj); | |
3146 | if (ret) | |
3147 | return ret; | |
3148 | ||
3149 | i915_gem_object_finish_gtt(obj); | |
3150 | ||
3151 | /* Before SandyBridge, you could not use tiling or fence | |
3152 | * registers with snooped memory, so relinquish any fences | |
3153 | * currently pointing to our region in the aperture. | |
3154 | */ | |
42d6ab48 | 3155 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3156 | ret = i915_gem_object_put_fence(obj); |
3157 | if (ret) | |
3158 | return ret; | |
3159 | } | |
3160 | ||
74898d7e DV |
3161 | if (obj->has_global_gtt_mapping) |
3162 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3163 | if (obj->has_aliasing_ppgtt_mapping) |
3164 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3165 | obj, cache_level); | |
42d6ab48 CW |
3166 | |
3167 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3168 | } |
3169 | ||
3170 | if (cache_level == I915_CACHE_NONE) { | |
3171 | u32 old_read_domains, old_write_domain; | |
3172 | ||
3173 | /* If we're coming from LLC cached, then we haven't | |
3174 | * actually been tracking whether the data is in the | |
3175 | * CPU cache or not, since we only allow one bit set | |
3176 | * in obj->write_domain and have been skipping the clflushes. | |
3177 | * Just set it to the CPU cache for now. | |
3178 | */ | |
3179 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3180 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3181 | ||
3182 | old_read_domains = obj->base.read_domains; | |
3183 | old_write_domain = obj->base.write_domain; | |
3184 | ||
3185 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3186 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3187 | ||
3188 | trace_i915_gem_object_change_domain(obj, | |
3189 | old_read_domains, | |
3190 | old_write_domain); | |
3191 | } | |
3192 | ||
3193 | obj->cache_level = cache_level; | |
42d6ab48 | 3194 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3195 | return 0; |
3196 | } | |
3197 | ||
199adf40 BW |
3198 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3199 | struct drm_file *file) | |
e6994aee | 3200 | { |
199adf40 | 3201 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3202 | struct drm_i915_gem_object *obj; |
3203 | int ret; | |
3204 | ||
3205 | ret = i915_mutex_lock_interruptible(dev); | |
3206 | if (ret) | |
3207 | return ret; | |
3208 | ||
3209 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3210 | if (&obj->base == NULL) { | |
3211 | ret = -ENOENT; | |
3212 | goto unlock; | |
3213 | } | |
3214 | ||
199adf40 | 3215 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3216 | |
3217 | drm_gem_object_unreference(&obj->base); | |
3218 | unlock: | |
3219 | mutex_unlock(&dev->struct_mutex); | |
3220 | return ret; | |
3221 | } | |
3222 | ||
199adf40 BW |
3223 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3224 | struct drm_file *file) | |
e6994aee | 3225 | { |
199adf40 | 3226 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3227 | struct drm_i915_gem_object *obj; |
3228 | enum i915_cache_level level; | |
3229 | int ret; | |
3230 | ||
199adf40 BW |
3231 | switch (args->caching) { |
3232 | case I915_CACHING_NONE: | |
e6994aee CW |
3233 | level = I915_CACHE_NONE; |
3234 | break; | |
199adf40 | 3235 | case I915_CACHING_CACHED: |
e6994aee CW |
3236 | level = I915_CACHE_LLC; |
3237 | break; | |
3238 | default: | |
3239 | return -EINVAL; | |
3240 | } | |
3241 | ||
3bc2913e BW |
3242 | ret = i915_mutex_lock_interruptible(dev); |
3243 | if (ret) | |
3244 | return ret; | |
3245 | ||
e6994aee CW |
3246 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3247 | if (&obj->base == NULL) { | |
3248 | ret = -ENOENT; | |
3249 | goto unlock; | |
3250 | } | |
3251 | ||
3252 | ret = i915_gem_object_set_cache_level(obj, level); | |
3253 | ||
3254 | drm_gem_object_unreference(&obj->base); | |
3255 | unlock: | |
3256 | mutex_unlock(&dev->struct_mutex); | |
3257 | return ret; | |
3258 | } | |
3259 | ||
b9241ea3 | 3260 | /* |
2da3b9b9 CW |
3261 | * Prepare buffer for display plane (scanout, cursors, etc). |
3262 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3263 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3264 | */ |
3265 | int | |
2da3b9b9 CW |
3266 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3267 | u32 alignment, | |
919926ae | 3268 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3269 | { |
2da3b9b9 | 3270 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3271 | int ret; |
3272 | ||
0be73284 | 3273 | if (pipelined != obj->ring) { |
2911a35b BW |
3274 | ret = i915_gem_object_sync(obj, pipelined); |
3275 | if (ret) | |
b9241ea3 ZW |
3276 | return ret; |
3277 | } | |
3278 | ||
a7ef0640 EA |
3279 | /* The display engine is not coherent with the LLC cache on gen6. As |
3280 | * a result, we make sure that the pinning that is about to occur is | |
3281 | * done with uncached PTEs. This is lowest common denominator for all | |
3282 | * chipsets. | |
3283 | * | |
3284 | * However for gen6+, we could do better by using the GFDT bit instead | |
3285 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3286 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3287 | */ | |
3288 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3289 | if (ret) | |
3290 | return ret; | |
3291 | ||
2da3b9b9 CW |
3292 | /* As the user may map the buffer once pinned in the display plane |
3293 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3294 | * always use map_and_fenceable for all scanout buffers. | |
3295 | */ | |
86a1ee26 | 3296 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3297 | if (ret) |
3298 | return ret; | |
3299 | ||
b118c1e3 CW |
3300 | i915_gem_object_flush_cpu_write_domain(obj); |
3301 | ||
2da3b9b9 | 3302 | old_write_domain = obj->base.write_domain; |
05394f39 | 3303 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3304 | |
3305 | /* It should now be out of any other write domains, and we can update | |
3306 | * the domain values for our changes. | |
3307 | */ | |
e5f1d962 | 3308 | obj->base.write_domain = 0; |
05394f39 | 3309 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3310 | |
3311 | trace_i915_gem_object_change_domain(obj, | |
3312 | old_read_domains, | |
2da3b9b9 | 3313 | old_write_domain); |
b9241ea3 ZW |
3314 | |
3315 | return 0; | |
3316 | } | |
3317 | ||
85345517 | 3318 | int |
a8198eea | 3319 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3320 | { |
88241785 CW |
3321 | int ret; |
3322 | ||
a8198eea | 3323 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3324 | return 0; |
3325 | ||
0201f1ec | 3326 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3327 | if (ret) |
3328 | return ret; | |
3329 | ||
a8198eea CW |
3330 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3331 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3332 | return 0; |
85345517 CW |
3333 | } |
3334 | ||
e47c68e9 EA |
3335 | /** |
3336 | * Moves a single object to the CPU read, and possibly write domain. | |
3337 | * | |
3338 | * This function returns when the move is complete, including waiting on | |
3339 | * flushes to occur. | |
3340 | */ | |
dabdfe02 | 3341 | int |
919926ae | 3342 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3343 | { |
1c5d22f7 | 3344 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3345 | int ret; |
3346 | ||
8d7e3de1 CW |
3347 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3348 | return 0; | |
3349 | ||
0201f1ec CW |
3350 | ret = i915_gem_object_wait_rendering(obj, !write); |
3351 | if (ret) | |
3352 | return ret; | |
2ef7eeaa | 3353 | |
e47c68e9 | 3354 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3355 | |
05394f39 CW |
3356 | old_write_domain = obj->base.write_domain; |
3357 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3358 | |
e47c68e9 | 3359 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3360 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3361 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3362 | |
05394f39 | 3363 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3364 | } |
3365 | ||
3366 | /* It should now be out of any other write domains, and we can update | |
3367 | * the domain values for our changes. | |
3368 | */ | |
05394f39 | 3369 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3370 | |
3371 | /* If we're writing through the CPU, then the GPU read domains will | |
3372 | * need to be invalidated at next use. | |
3373 | */ | |
3374 | if (write) { | |
05394f39 CW |
3375 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3376 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3377 | } |
2ef7eeaa | 3378 | |
1c5d22f7 CW |
3379 | trace_i915_gem_object_change_domain(obj, |
3380 | old_read_domains, | |
3381 | old_write_domain); | |
3382 | ||
2ef7eeaa EA |
3383 | return 0; |
3384 | } | |
3385 | ||
673a394b EA |
3386 | /* Throttle our rendering by waiting until the ring has completed our requests |
3387 | * emitted over 20 msec ago. | |
3388 | * | |
b962442e EA |
3389 | * Note that if we were to use the current jiffies each time around the loop, |
3390 | * we wouldn't escape the function with any frames outstanding if the time to | |
3391 | * render a frame was over 20ms. | |
3392 | * | |
673a394b EA |
3393 | * This should get us reasonable parallelism between CPU and GPU but also |
3394 | * relatively low latency when blocking on a particular request to finish. | |
3395 | */ | |
40a5f0de | 3396 | static int |
f787a5f5 | 3397 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3398 | { |
f787a5f5 CW |
3399 | struct drm_i915_private *dev_priv = dev->dev_private; |
3400 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3401 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3402 | struct drm_i915_gem_request *request; |
3403 | struct intel_ring_buffer *ring = NULL; | |
3404 | u32 seqno = 0; | |
3405 | int ret; | |
93533c29 | 3406 | |
e110e8d6 CW |
3407 | if (atomic_read(&dev_priv->mm.wedged)) |
3408 | return -EIO; | |
3409 | ||
1c25595f | 3410 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3411 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3412 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3413 | break; | |
40a5f0de | 3414 | |
f787a5f5 CW |
3415 | ring = request->ring; |
3416 | seqno = request->seqno; | |
b962442e | 3417 | } |
1c25595f | 3418 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3419 | |
f787a5f5 CW |
3420 | if (seqno == 0) |
3421 | return 0; | |
2bc43b5c | 3422 | |
5c81fe85 | 3423 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3424 | if (ret == 0) |
3425 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3426 | |
3427 | return ret; | |
3428 | } | |
3429 | ||
673a394b | 3430 | int |
05394f39 CW |
3431 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3432 | uint32_t alignment, | |
86a1ee26 CW |
3433 | bool map_and_fenceable, |
3434 | bool nonblocking) | |
673a394b | 3435 | { |
673a394b EA |
3436 | int ret; |
3437 | ||
7e81a42e CW |
3438 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3439 | return -EBUSY; | |
ac0c6b5a | 3440 | |
05394f39 CW |
3441 | if (obj->gtt_space != NULL) { |
3442 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3443 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3444 | WARN(obj->pin_count, | |
ae7d49d8 | 3445 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3446 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3447 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3448 | obj->gtt_offset, alignment, |
75e9e915 | 3449 | map_and_fenceable, |
05394f39 | 3450 | obj->map_and_fenceable); |
ac0c6b5a CW |
3451 | ret = i915_gem_object_unbind(obj); |
3452 | if (ret) | |
3453 | return ret; | |
3454 | } | |
3455 | } | |
3456 | ||
05394f39 | 3457 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3458 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3459 | map_and_fenceable, |
3460 | nonblocking); | |
9731129c | 3461 | if (ret) |
673a394b | 3462 | return ret; |
22c344e9 | 3463 | } |
76446cac | 3464 | |
74898d7e DV |
3465 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3466 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3467 | ||
1b50247a | 3468 | obj->pin_count++; |
6299f992 | 3469 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3470 | |
3471 | return 0; | |
3472 | } | |
3473 | ||
3474 | void | |
05394f39 | 3475 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3476 | { |
05394f39 CW |
3477 | BUG_ON(obj->pin_count == 0); |
3478 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3479 | |
1b50247a | 3480 | if (--obj->pin_count == 0) |
6299f992 | 3481 | obj->pin_mappable = false; |
673a394b EA |
3482 | } |
3483 | ||
3484 | int | |
3485 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3486 | struct drm_file *file) |
673a394b EA |
3487 | { |
3488 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3489 | struct drm_i915_gem_object *obj; |
673a394b EA |
3490 | int ret; |
3491 | ||
1d7cfea1 CW |
3492 | ret = i915_mutex_lock_interruptible(dev); |
3493 | if (ret) | |
3494 | return ret; | |
673a394b | 3495 | |
05394f39 | 3496 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3497 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3498 | ret = -ENOENT; |
3499 | goto unlock; | |
673a394b | 3500 | } |
673a394b | 3501 | |
05394f39 | 3502 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3503 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3504 | ret = -EINVAL; |
3505 | goto out; | |
3ef94daa CW |
3506 | } |
3507 | ||
05394f39 | 3508 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3509 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3510 | args->handle); | |
1d7cfea1 CW |
3511 | ret = -EINVAL; |
3512 | goto out; | |
79e53945 JB |
3513 | } |
3514 | ||
05394f39 CW |
3515 | obj->user_pin_count++; |
3516 | obj->pin_filp = file; | |
3517 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3518 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3519 | if (ret) |
3520 | goto out; | |
673a394b EA |
3521 | } |
3522 | ||
3523 | /* XXX - flush the CPU caches for pinned objects | |
3524 | * as the X server doesn't manage domains yet | |
3525 | */ | |
e47c68e9 | 3526 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3527 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3528 | out: |
05394f39 | 3529 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3530 | unlock: |
673a394b | 3531 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3532 | return ret; |
673a394b EA |
3533 | } |
3534 | ||
3535 | int | |
3536 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3537 | struct drm_file *file) |
673a394b EA |
3538 | { |
3539 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3540 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3541 | int ret; |
673a394b | 3542 | |
1d7cfea1 CW |
3543 | ret = i915_mutex_lock_interruptible(dev); |
3544 | if (ret) | |
3545 | return ret; | |
673a394b | 3546 | |
05394f39 | 3547 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3548 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3549 | ret = -ENOENT; |
3550 | goto unlock; | |
673a394b | 3551 | } |
76c1dec1 | 3552 | |
05394f39 | 3553 | if (obj->pin_filp != file) { |
79e53945 JB |
3554 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3555 | args->handle); | |
1d7cfea1 CW |
3556 | ret = -EINVAL; |
3557 | goto out; | |
79e53945 | 3558 | } |
05394f39 CW |
3559 | obj->user_pin_count--; |
3560 | if (obj->user_pin_count == 0) { | |
3561 | obj->pin_filp = NULL; | |
79e53945 JB |
3562 | i915_gem_object_unpin(obj); |
3563 | } | |
673a394b | 3564 | |
1d7cfea1 | 3565 | out: |
05394f39 | 3566 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3567 | unlock: |
673a394b | 3568 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3569 | return ret; |
673a394b EA |
3570 | } |
3571 | ||
3572 | int | |
3573 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3574 | struct drm_file *file) |
673a394b EA |
3575 | { |
3576 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3577 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3578 | int ret; |
3579 | ||
76c1dec1 | 3580 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3581 | if (ret) |
76c1dec1 | 3582 | return ret; |
673a394b | 3583 | |
05394f39 | 3584 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3585 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3586 | ret = -ENOENT; |
3587 | goto unlock; | |
673a394b | 3588 | } |
d1b851fc | 3589 | |
0be555b6 CW |
3590 | /* Count all active objects as busy, even if they are currently not used |
3591 | * by the gpu. Users of this interface expect objects to eventually | |
3592 | * become non-busy without any further actions, therefore emit any | |
3593 | * necessary flushes here. | |
c4de0a5d | 3594 | */ |
30dfebf3 | 3595 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3596 | |
30dfebf3 | 3597 | args->busy = obj->active; |
e9808edd CW |
3598 | if (obj->ring) { |
3599 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3600 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3601 | } | |
673a394b | 3602 | |
05394f39 | 3603 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3604 | unlock: |
673a394b | 3605 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3606 | return ret; |
673a394b EA |
3607 | } |
3608 | ||
3609 | int | |
3610 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3611 | struct drm_file *file_priv) | |
3612 | { | |
0206e353 | 3613 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3614 | } |
3615 | ||
3ef94daa CW |
3616 | int |
3617 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3618 | struct drm_file *file_priv) | |
3619 | { | |
3620 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3621 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3622 | int ret; |
3ef94daa CW |
3623 | |
3624 | switch (args->madv) { | |
3625 | case I915_MADV_DONTNEED: | |
3626 | case I915_MADV_WILLNEED: | |
3627 | break; | |
3628 | default: | |
3629 | return -EINVAL; | |
3630 | } | |
3631 | ||
1d7cfea1 CW |
3632 | ret = i915_mutex_lock_interruptible(dev); |
3633 | if (ret) | |
3634 | return ret; | |
3635 | ||
05394f39 | 3636 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3637 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3638 | ret = -ENOENT; |
3639 | goto unlock; | |
3ef94daa | 3640 | } |
3ef94daa | 3641 | |
05394f39 | 3642 | if (obj->pin_count) { |
1d7cfea1 CW |
3643 | ret = -EINVAL; |
3644 | goto out; | |
3ef94daa CW |
3645 | } |
3646 | ||
05394f39 CW |
3647 | if (obj->madv != __I915_MADV_PURGED) |
3648 | obj->madv = args->madv; | |
3ef94daa | 3649 | |
6c085a72 CW |
3650 | /* if the object is no longer attached, discard its backing storage */ |
3651 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3652 | i915_gem_object_truncate(obj); |
3653 | ||
05394f39 | 3654 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3655 | |
1d7cfea1 | 3656 | out: |
05394f39 | 3657 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3658 | unlock: |
3ef94daa | 3659 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3660 | return ret; |
3ef94daa CW |
3661 | } |
3662 | ||
37e680a1 CW |
3663 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3664 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3665 | { |
0327d6ba CW |
3666 | INIT_LIST_HEAD(&obj->mm_list); |
3667 | INIT_LIST_HEAD(&obj->gtt_list); | |
3668 | INIT_LIST_HEAD(&obj->ring_list); | |
3669 | INIT_LIST_HEAD(&obj->exec_list); | |
3670 | ||
37e680a1 CW |
3671 | obj->ops = ops; |
3672 | ||
0327d6ba CW |
3673 | obj->fence_reg = I915_FENCE_REG_NONE; |
3674 | obj->madv = I915_MADV_WILLNEED; | |
3675 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3676 | obj->map_and_fenceable = true; | |
3677 | ||
3678 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3679 | } | |
3680 | ||
37e680a1 CW |
3681 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3682 | .get_pages = i915_gem_object_get_pages_gtt, | |
3683 | .put_pages = i915_gem_object_put_pages_gtt, | |
3684 | }; | |
3685 | ||
05394f39 CW |
3686 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3687 | size_t size) | |
ac52bc56 | 3688 | { |
c397b908 | 3689 | struct drm_i915_gem_object *obj; |
5949eac4 | 3690 | struct address_space *mapping; |
bed1ea95 | 3691 | u32 mask; |
ac52bc56 | 3692 | |
c397b908 DV |
3693 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3694 | if (obj == NULL) | |
3695 | return NULL; | |
673a394b | 3696 | |
c397b908 DV |
3697 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3698 | kfree(obj); | |
3699 | return NULL; | |
3700 | } | |
673a394b | 3701 | |
bed1ea95 CW |
3702 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3703 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3704 | /* 965gm cannot relocate objects above 4GiB. */ | |
3705 | mask &= ~__GFP_HIGHMEM; | |
3706 | mask |= __GFP_DMA32; | |
3707 | } | |
3708 | ||
5949eac4 | 3709 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3710 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3711 | |
37e680a1 | 3712 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3713 | |
c397b908 DV |
3714 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3715 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3716 | |
3d29b842 ED |
3717 | if (HAS_LLC(dev)) { |
3718 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3719 | * cache) for about a 10% performance improvement |
3720 | * compared to uncached. Graphics requests other than | |
3721 | * display scanout are coherent with the CPU in | |
3722 | * accessing this cache. This means in this mode we | |
3723 | * don't need to clflush on the CPU side, and on the | |
3724 | * GPU side we only need to flush internal caches to | |
3725 | * get data visible to the CPU. | |
3726 | * | |
3727 | * However, we maintain the display planes as UC, and so | |
3728 | * need to rebind when first used as such. | |
3729 | */ | |
3730 | obj->cache_level = I915_CACHE_LLC; | |
3731 | } else | |
3732 | obj->cache_level = I915_CACHE_NONE; | |
3733 | ||
05394f39 | 3734 | return obj; |
c397b908 DV |
3735 | } |
3736 | ||
3737 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3738 | { | |
3739 | BUG(); | |
de151cf6 | 3740 | |
673a394b EA |
3741 | return 0; |
3742 | } | |
3743 | ||
1488fc08 | 3744 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3745 | { |
1488fc08 | 3746 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3747 | struct drm_device *dev = obj->base.dev; |
be72615b | 3748 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3749 | |
26e12f89 CW |
3750 | trace_i915_gem_object_destroy(obj); |
3751 | ||
1488fc08 CW |
3752 | if (obj->phys_obj) |
3753 | i915_gem_detach_phys_object(dev, obj); | |
3754 | ||
3755 | obj->pin_count = 0; | |
3756 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3757 | bool was_interruptible; | |
3758 | ||
3759 | was_interruptible = dev_priv->mm.interruptible; | |
3760 | dev_priv->mm.interruptible = false; | |
3761 | ||
3762 | WARN_ON(i915_gem_object_unbind(obj)); | |
3763 | ||
3764 | dev_priv->mm.interruptible = was_interruptible; | |
3765 | } | |
3766 | ||
a5570178 | 3767 | obj->pages_pin_count = 0; |
37e680a1 | 3768 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3769 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 3770 | |
9da3da66 CW |
3771 | BUG_ON(obj->pages); |
3772 | ||
2f745ad3 CW |
3773 | if (obj->base.import_attach) |
3774 | drm_prime_gem_destroy(&obj->base, NULL); | |
3775 | ||
05394f39 CW |
3776 | drm_gem_object_release(&obj->base); |
3777 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3778 | |
05394f39 CW |
3779 | kfree(obj->bit_17); |
3780 | kfree(obj); | |
673a394b EA |
3781 | } |
3782 | ||
29105ccc CW |
3783 | int |
3784 | i915_gem_idle(struct drm_device *dev) | |
3785 | { | |
3786 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3787 | int ret; | |
28dfe52a | 3788 | |
29105ccc | 3789 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3790 | |
87acb0a5 | 3791 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3792 | mutex_unlock(&dev->struct_mutex); |
3793 | return 0; | |
28dfe52a EA |
3794 | } |
3795 | ||
b2da9fe5 | 3796 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3797 | if (ret) { |
3798 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3799 | return ret; |
6dbe2772 | 3800 | } |
b2da9fe5 | 3801 | i915_gem_retire_requests(dev); |
673a394b | 3802 | |
29105ccc | 3803 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3804 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3805 | i915_gem_evict_everything(dev); |
29105ccc | 3806 | |
312817a3 CW |
3807 | i915_gem_reset_fences(dev); |
3808 | ||
29105ccc CW |
3809 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3810 | * We need to replace this with a semaphore, or something. | |
3811 | * And not confound mm.suspended! | |
3812 | */ | |
3813 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3814 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3815 | |
3816 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3817 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3818 | |
6dbe2772 KP |
3819 | mutex_unlock(&dev->struct_mutex); |
3820 | ||
29105ccc CW |
3821 | /* Cancel the retire work handler, which should be idle now. */ |
3822 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3823 | ||
673a394b EA |
3824 | return 0; |
3825 | } | |
3826 | ||
b9524a1e BW |
3827 | void i915_gem_l3_remap(struct drm_device *dev) |
3828 | { | |
3829 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3830 | u32 misccpctl; | |
3831 | int i; | |
3832 | ||
3833 | if (!IS_IVYBRIDGE(dev)) | |
3834 | return; | |
3835 | ||
3836 | if (!dev_priv->mm.l3_remap_info) | |
3837 | return; | |
3838 | ||
3839 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3840 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3841 | POSTING_READ(GEN7_MISCCPCTL); | |
3842 | ||
3843 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3844 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
3845 | if (remap && remap != dev_priv->mm.l3_remap_info[i/4]) | |
3846 | DRM_DEBUG("0x%x was already programmed to %x\n", | |
3847 | GEN7_L3LOG_BASE + i, remap); | |
3848 | if (remap && !dev_priv->mm.l3_remap_info[i/4]) | |
3849 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); | |
3850 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]); | |
3851 | } | |
3852 | ||
3853 | /* Make sure all the writes land before disabling dop clock gating */ | |
3854 | POSTING_READ(GEN7_L3LOG_BASE); | |
3855 | ||
3856 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3857 | } | |
3858 | ||
f691e2f4 DV |
3859 | void i915_gem_init_swizzling(struct drm_device *dev) |
3860 | { | |
3861 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3862 | ||
11782b02 | 3863 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3864 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3865 | return; | |
3866 | ||
3867 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3868 | DISP_TILE_SURFACE_SWIZZLING); | |
3869 | ||
11782b02 DV |
3870 | if (IS_GEN5(dev)) |
3871 | return; | |
3872 | ||
f691e2f4 DV |
3873 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3874 | if (IS_GEN6(dev)) | |
6b26c86d | 3875 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3876 | else |
6b26c86d | 3877 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3878 | } |
e21af88d DV |
3879 | |
3880 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3881 | { | |
3882 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3883 | uint32_t pd_offset; | |
3884 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3885 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3886 | uint32_t __iomem *pd_addr; | |
3887 | uint32_t pd_entry; | |
e21af88d DV |
3888 | int i; |
3889 | ||
3890 | if (!dev_priv->mm.aliasing_ppgtt) | |
3891 | return; | |
3892 | ||
55a254ac DV |
3893 | |
3894 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3895 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3896 | dma_addr_t pt_addr; | |
3897 | ||
3898 | if (dev_priv->mm.gtt->needs_dmar) | |
3899 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3900 | else | |
3901 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3902 | ||
3903 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3904 | pd_entry |= GEN6_PDE_VALID; | |
3905 | ||
3906 | writel(pd_entry, pd_addr + i); | |
3907 | } | |
3908 | readl(pd_addr); | |
3909 | ||
3910 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3911 | pd_offset /= 64; /* in cachelines, */ |
3912 | pd_offset <<= 16; | |
3913 | ||
3914 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3915 | uint32_t ecochk, gab_ctl, ecobits; |
3916 | ||
3917 | ecobits = I915_READ(GAC_ECO_BITS); | |
3918 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3919 | |
3920 | gab_ctl = I915_READ(GAB_CTL); | |
3921 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3922 | ||
3923 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3924 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3925 | ECOCHK_PPGTT_CACHE64B); | |
6b26c86d | 3926 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3927 | } else if (INTEL_INFO(dev)->gen >= 7) { |
3928 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3929 | /* GFX_MODE is per-ring on gen7+ */ | |
3930 | } | |
3931 | ||
b4519513 | 3932 | for_each_ring(ring, dev_priv, i) { |
e21af88d DV |
3933 | if (INTEL_INFO(dev)->gen >= 7) |
3934 | I915_WRITE(RING_MODE_GEN7(ring), | |
6b26c86d | 3935 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3936 | |
3937 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3938 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3939 | } | |
3940 | } | |
3941 | ||
67b1b571 CW |
3942 | static bool |
3943 | intel_enable_blt(struct drm_device *dev) | |
3944 | { | |
3945 | if (!HAS_BLT(dev)) | |
3946 | return false; | |
3947 | ||
3948 | /* The blitter was dysfunctional on early prototypes */ | |
3949 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3950 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3951 | " graphics performance will be degraded.\n"); | |
3952 | return false; | |
3953 | } | |
3954 | ||
3955 | return true; | |
3956 | } | |
3957 | ||
8187a2b7 | 3958 | int |
f691e2f4 | 3959 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3960 | { |
3961 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3962 | int ret; | |
68f95ba9 | 3963 | |
8ecd1a66 DV |
3964 | if (!intel_enable_gtt()) |
3965 | return -EIO; | |
3966 | ||
eda2d7f5 RV |
3967 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
3968 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
3969 | ||
b9524a1e BW |
3970 | i915_gem_l3_remap(dev); |
3971 | ||
f691e2f4 DV |
3972 | i915_gem_init_swizzling(dev); |
3973 | ||
5c1143bb | 3974 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3975 | if (ret) |
b6913e4b | 3976 | return ret; |
68f95ba9 CW |
3977 | |
3978 | if (HAS_BSD(dev)) { | |
5c1143bb | 3979 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3980 | if (ret) |
3981 | goto cleanup_render_ring; | |
d1b851fc | 3982 | } |
68f95ba9 | 3983 | |
67b1b571 | 3984 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3985 | ret = intel_init_blt_ring_buffer(dev); |
3986 | if (ret) | |
3987 | goto cleanup_bsd_ring; | |
3988 | } | |
3989 | ||
6f392d54 CW |
3990 | dev_priv->next_seqno = 1; |
3991 | ||
254f965c BW |
3992 | /* |
3993 | * XXX: There was some w/a described somewhere suggesting loading | |
3994 | * contexts before PPGTT. | |
3995 | */ | |
3996 | i915_gem_context_init(dev); | |
e21af88d DV |
3997 | i915_gem_init_ppgtt(dev); |
3998 | ||
68f95ba9 CW |
3999 | return 0; |
4000 | ||
549f7365 | 4001 | cleanup_bsd_ring: |
1ec14ad3 | 4002 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 4003 | cleanup_render_ring: |
1ec14ad3 | 4004 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
4005 | return ret; |
4006 | } | |
4007 | ||
1070a42b CW |
4008 | static bool |
4009 | intel_enable_ppgtt(struct drm_device *dev) | |
4010 | { | |
4011 | if (i915_enable_ppgtt >= 0) | |
4012 | return i915_enable_ppgtt; | |
4013 | ||
4014 | #ifdef CONFIG_INTEL_IOMMU | |
4015 | /* Disable ppgtt on SNB if VT-d is on. */ | |
4016 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
4017 | return false; | |
4018 | #endif | |
4019 | ||
4020 | return true; | |
4021 | } | |
4022 | ||
4023 | int i915_gem_init(struct drm_device *dev) | |
4024 | { | |
4025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4026 | unsigned long gtt_size, mappable_size; | |
4027 | int ret; | |
4028 | ||
4029 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
4030 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
4031 | ||
4032 | mutex_lock(&dev->struct_mutex); | |
4033 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
4034 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
4035 | * aperture accordingly when using aliasing ppgtt. */ | |
4036 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
4037 | ||
4038 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
4039 | ||
4040 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
4041 | if (ret) { | |
4042 | mutex_unlock(&dev->struct_mutex); | |
4043 | return ret; | |
4044 | } | |
4045 | } else { | |
4046 | /* Let GEM Manage all of the aperture. | |
4047 | * | |
4048 | * However, leave one page at the end still bound to the scratch | |
4049 | * page. There are a number of places where the hardware | |
4050 | * apparently prefetches past the end of the object, and we've | |
4051 | * seen multiple hangs with the GPU head pointer stuck in a | |
4052 | * batchbuffer bound at the last page of the aperture. One page | |
4053 | * should be enough to keep any prefetching inside of the | |
4054 | * aperture. | |
4055 | */ | |
4056 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
4057 | gtt_size); | |
4058 | } | |
4059 | ||
4060 | ret = i915_gem_init_hw(dev); | |
4061 | mutex_unlock(&dev->struct_mutex); | |
4062 | if (ret) { | |
4063 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4064 | return ret; | |
4065 | } | |
4066 | ||
53ca26ca DV |
4067 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4068 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4069 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4070 | return 0; |
4071 | } | |
4072 | ||
8187a2b7 ZN |
4073 | void |
4074 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4075 | { | |
4076 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4077 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4078 | int i; |
8187a2b7 | 4079 | |
b4519513 CW |
4080 | for_each_ring(ring, dev_priv, i) |
4081 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4082 | } |
4083 | ||
673a394b EA |
4084 | int |
4085 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4086 | struct drm_file *file_priv) | |
4087 | { | |
4088 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4089 | int ret; |
673a394b | 4090 | |
79e53945 JB |
4091 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4092 | return 0; | |
4093 | ||
ba1234d1 | 4094 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4095 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4096 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4097 | } |
4098 | ||
673a394b | 4099 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4100 | dev_priv->mm.suspended = 0; |
4101 | ||
f691e2f4 | 4102 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4103 | if (ret != 0) { |
4104 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4105 | return ret; |
d816f6ac | 4106 | } |
9bb2d6f9 | 4107 | |
69dc4987 | 4108 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4109 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4110 | |
5f35308b CW |
4111 | ret = drm_irq_install(dev); |
4112 | if (ret) | |
4113 | goto cleanup_ringbuffer; | |
dbb19d30 | 4114 | |
673a394b | 4115 | return 0; |
5f35308b CW |
4116 | |
4117 | cleanup_ringbuffer: | |
4118 | mutex_lock(&dev->struct_mutex); | |
4119 | i915_gem_cleanup_ringbuffer(dev); | |
4120 | dev_priv->mm.suspended = 1; | |
4121 | mutex_unlock(&dev->struct_mutex); | |
4122 | ||
4123 | return ret; | |
673a394b EA |
4124 | } |
4125 | ||
4126 | int | |
4127 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4128 | struct drm_file *file_priv) | |
4129 | { | |
79e53945 JB |
4130 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4131 | return 0; | |
4132 | ||
dbb19d30 | 4133 | drm_irq_uninstall(dev); |
e6890f6f | 4134 | return i915_gem_idle(dev); |
673a394b EA |
4135 | } |
4136 | ||
4137 | void | |
4138 | i915_gem_lastclose(struct drm_device *dev) | |
4139 | { | |
4140 | int ret; | |
673a394b | 4141 | |
e806b495 EA |
4142 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4143 | return; | |
4144 | ||
6dbe2772 KP |
4145 | ret = i915_gem_idle(dev); |
4146 | if (ret) | |
4147 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4148 | } |
4149 | ||
64193406 CW |
4150 | static void |
4151 | init_ring_lists(struct intel_ring_buffer *ring) | |
4152 | { | |
4153 | INIT_LIST_HEAD(&ring->active_list); | |
4154 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4155 | } |
4156 | ||
673a394b EA |
4157 | void |
4158 | i915_gem_load(struct drm_device *dev) | |
4159 | { | |
b5aa8a0f | 4160 | int i; |
673a394b EA |
4161 | drm_i915_private_t *dev_priv = dev->dev_private; |
4162 | ||
69dc4987 | 4163 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4164 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4165 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4166 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4167 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4168 | for (i = 0; i < I915_NUM_RINGS; i++) |
4169 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4170 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4171 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4172 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4173 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4174 | init_completion(&dev_priv->error_completion); |
31169714 | 4175 | |
94400120 DA |
4176 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4177 | if (IS_GEN3(dev)) { | |
50743298 DV |
4178 | I915_WRITE(MI_ARB_STATE, |
4179 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4180 | } |
4181 | ||
72bfa19c CW |
4182 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4183 | ||
de151cf6 | 4184 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4185 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4186 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4187 | |
a6c45cf0 | 4188 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4189 | dev_priv->num_fence_regs = 16; |
4190 | else | |
4191 | dev_priv->num_fence_regs = 8; | |
4192 | ||
b5aa8a0f | 4193 | /* Initialize fence registers to zero */ |
ada726c7 | 4194 | i915_gem_reset_fences(dev); |
10ed13e4 | 4195 | |
673a394b | 4196 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4197 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4198 | |
ce453d81 CW |
4199 | dev_priv->mm.interruptible = true; |
4200 | ||
17250b71 CW |
4201 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4202 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4203 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4204 | } |
71acb5eb DA |
4205 | |
4206 | /* | |
4207 | * Create a physically contiguous memory object for this object | |
4208 | * e.g. for cursor + overlay regs | |
4209 | */ | |
995b6762 CW |
4210 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4211 | int id, int size, int align) | |
71acb5eb DA |
4212 | { |
4213 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4214 | struct drm_i915_gem_phys_object *phys_obj; | |
4215 | int ret; | |
4216 | ||
4217 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4218 | return 0; | |
4219 | ||
9a298b2a | 4220 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4221 | if (!phys_obj) |
4222 | return -ENOMEM; | |
4223 | ||
4224 | phys_obj->id = id; | |
4225 | ||
6eeefaf3 | 4226 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4227 | if (!phys_obj->handle) { |
4228 | ret = -ENOMEM; | |
4229 | goto kfree_obj; | |
4230 | } | |
4231 | #ifdef CONFIG_X86 | |
4232 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4233 | #endif | |
4234 | ||
4235 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4236 | ||
4237 | return 0; | |
4238 | kfree_obj: | |
9a298b2a | 4239 | kfree(phys_obj); |
71acb5eb DA |
4240 | return ret; |
4241 | } | |
4242 | ||
995b6762 | 4243 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4244 | { |
4245 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4246 | struct drm_i915_gem_phys_object *phys_obj; | |
4247 | ||
4248 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4249 | return; | |
4250 | ||
4251 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4252 | if (phys_obj->cur_obj) { | |
4253 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4254 | } | |
4255 | ||
4256 | #ifdef CONFIG_X86 | |
4257 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4258 | #endif | |
4259 | drm_pci_free(dev, phys_obj->handle); | |
4260 | kfree(phys_obj); | |
4261 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4262 | } | |
4263 | ||
4264 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4265 | { | |
4266 | int i; | |
4267 | ||
260883c8 | 4268 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4269 | i915_gem_free_phys_object(dev, i); |
4270 | } | |
4271 | ||
4272 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4273 | struct drm_i915_gem_object *obj) |
71acb5eb | 4274 | { |
05394f39 | 4275 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4276 | char *vaddr; |
71acb5eb | 4277 | int i; |
71acb5eb DA |
4278 | int page_count; |
4279 | ||
05394f39 | 4280 | if (!obj->phys_obj) |
71acb5eb | 4281 | return; |
05394f39 | 4282 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4283 | |
05394f39 | 4284 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4285 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4286 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4287 | if (!IS_ERR(page)) { |
4288 | char *dst = kmap_atomic(page); | |
4289 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4290 | kunmap_atomic(dst); | |
4291 | ||
4292 | drm_clflush_pages(&page, 1); | |
4293 | ||
4294 | set_page_dirty(page); | |
4295 | mark_page_accessed(page); | |
4296 | page_cache_release(page); | |
4297 | } | |
71acb5eb | 4298 | } |
40ce6575 | 4299 | intel_gtt_chipset_flush(); |
d78b47b9 | 4300 | |
05394f39 CW |
4301 | obj->phys_obj->cur_obj = NULL; |
4302 | obj->phys_obj = NULL; | |
71acb5eb DA |
4303 | } |
4304 | ||
4305 | int | |
4306 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4307 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4308 | int id, |
4309 | int align) | |
71acb5eb | 4310 | { |
05394f39 | 4311 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4312 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4313 | int ret = 0; |
4314 | int page_count; | |
4315 | int i; | |
4316 | ||
4317 | if (id > I915_MAX_PHYS_OBJECT) | |
4318 | return -EINVAL; | |
4319 | ||
05394f39 CW |
4320 | if (obj->phys_obj) { |
4321 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4322 | return 0; |
4323 | i915_gem_detach_phys_object(dev, obj); | |
4324 | } | |
4325 | ||
71acb5eb DA |
4326 | /* create a new object */ |
4327 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4328 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4329 | obj->base.size, align); |
71acb5eb | 4330 | if (ret) { |
05394f39 CW |
4331 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4332 | id, obj->base.size); | |
e5281ccd | 4333 | return ret; |
71acb5eb DA |
4334 | } |
4335 | } | |
4336 | ||
4337 | /* bind to the object */ | |
05394f39 CW |
4338 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4339 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4340 | |
05394f39 | 4341 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4342 | |
4343 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4344 | struct page *page; |
4345 | char *dst, *src; | |
4346 | ||
5949eac4 | 4347 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4348 | if (IS_ERR(page)) |
4349 | return PTR_ERR(page); | |
71acb5eb | 4350 | |
ff75b9bc | 4351 | src = kmap_atomic(page); |
05394f39 | 4352 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4353 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4354 | kunmap_atomic(src); |
71acb5eb | 4355 | |
e5281ccd CW |
4356 | mark_page_accessed(page); |
4357 | page_cache_release(page); | |
4358 | } | |
d78b47b9 | 4359 | |
71acb5eb | 4360 | return 0; |
71acb5eb DA |
4361 | } |
4362 | ||
4363 | static int | |
05394f39 CW |
4364 | i915_gem_phys_pwrite(struct drm_device *dev, |
4365 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4366 | struct drm_i915_gem_pwrite *args, |
4367 | struct drm_file *file_priv) | |
4368 | { | |
05394f39 | 4369 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4370 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4371 | |
b47b30cc CW |
4372 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4373 | unsigned long unwritten; | |
4374 | ||
4375 | /* The physical object once assigned is fixed for the lifetime | |
4376 | * of the obj, so we can safely drop the lock and continue | |
4377 | * to access vaddr. | |
4378 | */ | |
4379 | mutex_unlock(&dev->struct_mutex); | |
4380 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4381 | mutex_lock(&dev->struct_mutex); | |
4382 | if (unwritten) | |
4383 | return -EFAULT; | |
4384 | } | |
71acb5eb | 4385 | |
40ce6575 | 4386 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4387 | return 0; |
4388 | } | |
b962442e | 4389 | |
f787a5f5 | 4390 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4391 | { |
f787a5f5 | 4392 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4393 | |
4394 | /* Clean up our request list when the client is going away, so that | |
4395 | * later retire_requests won't dereference our soon-to-be-gone | |
4396 | * file_priv. | |
4397 | */ | |
1c25595f | 4398 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4399 | while (!list_empty(&file_priv->mm.request_list)) { |
4400 | struct drm_i915_gem_request *request; | |
4401 | ||
4402 | request = list_first_entry(&file_priv->mm.request_list, | |
4403 | struct drm_i915_gem_request, | |
4404 | client_list); | |
4405 | list_del(&request->client_list); | |
4406 | request->file_priv = NULL; | |
4407 | } | |
1c25595f | 4408 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4409 | } |
31169714 | 4410 | |
31169714 | 4411 | static int |
1495f230 | 4412 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4413 | { |
17250b71 CW |
4414 | struct drm_i915_private *dev_priv = |
4415 | container_of(shrinker, | |
4416 | struct drm_i915_private, | |
4417 | mm.inactive_shrinker); | |
4418 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4419 | struct drm_i915_gem_object *obj; |
1495f230 | 4420 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4421 | int cnt; |
4422 | ||
4423 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4424 | return 0; |
31169714 | 4425 | |
6c085a72 CW |
4426 | if (nr_to_scan) { |
4427 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4428 | if (nr_to_scan > 0) | |
4429 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4430 | } |
4431 | ||
17250b71 | 4432 | cnt = 0; |
6c085a72 | 4433 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4434 | if (obj->pages_pin_count == 0) |
4435 | cnt += obj->base.size >> PAGE_SHIFT; | |
6c085a72 | 4436 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
a5570178 | 4437 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4438 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4439 | |
17250b71 | 4440 | mutex_unlock(&dev->struct_mutex); |
6c085a72 | 4441 | return cnt; |
31169714 | 4442 | } |