Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
c13d87ea | 32 | #include "i915_gem_dmabuf.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
5d723d7a | 36 | #include "intel_frontbuffer.h" |
0ccdacf6 | 37 | #include "intel_mocs.h" |
c13d87ea | 38 | #include <linux/reservation.h> |
5949eac4 | 39 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
673a394b | 41 | #include <linux/swap.h> |
79e53945 | 42 | #include <linux/pci.h> |
1286ff73 | 43 | #include <linux/dma-buf.h> |
673a394b | 44 | |
05394f39 | 45 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 46 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 47 | |
c76ce038 CW |
48 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
49 | enum i915_cache_level level) | |
50 | { | |
51 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
52 | } | |
53 | ||
2c22569b CW |
54 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
55 | { | |
b50a5371 AS |
56 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
57 | return false; | |
58 | ||
2c22569b CW |
59 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
60 | return true; | |
61 | ||
62 | return obj->pin_display; | |
63 | } | |
64 | ||
4f1959ee AS |
65 | static int |
66 | insert_mappable_node(struct drm_i915_private *i915, | |
67 | struct drm_mm_node *node, u32 size) | |
68 | { | |
69 | memset(node, 0, sizeof(*node)); | |
70 | return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node, | |
71 | size, 0, 0, 0, | |
72 | i915->ggtt.mappable_end, | |
73 | DRM_MM_SEARCH_DEFAULT, | |
74 | DRM_MM_CREATE_DEFAULT); | |
75 | } | |
76 | ||
77 | static void | |
78 | remove_mappable_node(struct drm_mm_node *node) | |
79 | { | |
80 | drm_mm_remove_node(node); | |
81 | } | |
82 | ||
73aa808f CW |
83 | /* some bookkeeping */ |
84 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
85 | size_t size) | |
86 | { | |
c20e8355 | 87 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
88 | dev_priv->mm.object_count++; |
89 | dev_priv->mm.object_memory += size; | |
c20e8355 | 90 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | } |
92 | ||
93 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count--; |
98 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
21dd3734 | 102 | static int |
33196ded | 103 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 104 | { |
30dbf0c0 CW |
105 | int ret; |
106 | ||
d98c52cf | 107 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
108 | return 0; |
109 | ||
0a6759c6 DV |
110 | /* |
111 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
112 | * userspace. If it takes that long something really bad is going on and | |
113 | * we should simply try to bail out and fail as gracefully as possible. | |
114 | */ | |
1f83fee0 | 115 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 116 | !i915_reset_in_progress(error), |
1f83fee0 | 117 | 10*HZ); |
0a6759c6 DV |
118 | if (ret == 0) { |
119 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
120 | return -EIO; | |
121 | } else if (ret < 0) { | |
30dbf0c0 | 122 | return ret; |
d98c52cf CW |
123 | } else { |
124 | return 0; | |
0a6759c6 | 125 | } |
30dbf0c0 CW |
126 | } |
127 | ||
54cf91dc | 128 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 129 | { |
fac5e23e | 130 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
131 | int ret; |
132 | ||
33196ded | 133 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
134 | if (ret) |
135 | return ret; | |
136 | ||
137 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
138 | if (ret) | |
139 | return ret; | |
140 | ||
76c1dec1 CW |
141 | return 0; |
142 | } | |
30dbf0c0 | 143 | |
5a125c3c EA |
144 | int |
145 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 146 | struct drm_file *file) |
5a125c3c | 147 | { |
72e96d64 | 148 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 149 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 150 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 151 | struct i915_vma *vma; |
6299f992 | 152 | size_t pinned; |
5a125c3c | 153 | |
6299f992 | 154 | pinned = 0; |
73aa808f | 155 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 156 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 157 | if (i915_vma_is_pinned(vma)) |
ca1543be | 158 | pinned += vma->node.size; |
1c7f4bca | 159 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 160 | if (i915_vma_is_pinned(vma)) |
ca1543be | 161 | pinned += vma->node.size; |
73aa808f | 162 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 163 | |
72e96d64 | 164 | args->aper_size = ggtt->base.total; |
0206e353 | 165 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 166 | |
5a125c3c EA |
167 | return 0; |
168 | } | |
169 | ||
6a2c4232 CW |
170 | static int |
171 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 172 | { |
93c76a3d | 173 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 CW |
174 | char *vaddr = obj->phys_handle->vaddr; |
175 | struct sg_table *st; | |
176 | struct scatterlist *sg; | |
177 | int i; | |
00731155 | 178 | |
6a2c4232 CW |
179 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
180 | return -EINVAL; | |
181 | ||
182 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
183 | struct page *page; | |
184 | char *src; | |
185 | ||
186 | page = shmem_read_mapping_page(mapping, i); | |
187 | if (IS_ERR(page)) | |
188 | return PTR_ERR(page); | |
189 | ||
190 | src = kmap_atomic(page); | |
191 | memcpy(vaddr, src, PAGE_SIZE); | |
192 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
193 | kunmap_atomic(src); | |
194 | ||
09cbfeaf | 195 | put_page(page); |
6a2c4232 CW |
196 | vaddr += PAGE_SIZE; |
197 | } | |
198 | ||
c033666a | 199 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
200 | |
201 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
202 | if (st == NULL) | |
203 | return -ENOMEM; | |
204 | ||
205 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
206 | kfree(st); | |
207 | return -ENOMEM; | |
208 | } | |
209 | ||
210 | sg = st->sgl; | |
211 | sg->offset = 0; | |
212 | sg->length = obj->base.size; | |
00731155 | 213 | |
6a2c4232 CW |
214 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
215 | sg_dma_len(sg) = obj->base.size; | |
216 | ||
217 | obj->pages = st; | |
6a2c4232 CW |
218 | return 0; |
219 | } | |
220 | ||
221 | static void | |
222 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
223 | { | |
224 | int ret; | |
225 | ||
226 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 227 | |
6a2c4232 | 228 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 229 | if (WARN_ON(ret)) { |
6a2c4232 CW |
230 | /* In the event of a disaster, abandon all caches and |
231 | * hope for the best. | |
232 | */ | |
6a2c4232 CW |
233 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
234 | } | |
235 | ||
236 | if (obj->madv == I915_MADV_DONTNEED) | |
237 | obj->dirty = 0; | |
238 | ||
239 | if (obj->dirty) { | |
93c76a3d | 240 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 241 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
242 | int i; |
243 | ||
244 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
245 | struct page *page; |
246 | char *dst; | |
247 | ||
248 | page = shmem_read_mapping_page(mapping, i); | |
249 | if (IS_ERR(page)) | |
250 | continue; | |
251 | ||
252 | dst = kmap_atomic(page); | |
253 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
254 | memcpy(dst, vaddr, PAGE_SIZE); | |
255 | kunmap_atomic(dst); | |
256 | ||
257 | set_page_dirty(page); | |
258 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 259 | mark_page_accessed(page); |
09cbfeaf | 260 | put_page(page); |
00731155 CW |
261 | vaddr += PAGE_SIZE; |
262 | } | |
6a2c4232 | 263 | obj->dirty = 0; |
00731155 CW |
264 | } |
265 | ||
6a2c4232 CW |
266 | sg_free_table(obj->pages); |
267 | kfree(obj->pages); | |
6a2c4232 CW |
268 | } |
269 | ||
270 | static void | |
271 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
272 | { | |
273 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
274 | } | |
275 | ||
276 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
277 | .get_pages = i915_gem_object_get_pages_phys, | |
278 | .put_pages = i915_gem_object_put_pages_phys, | |
279 | .release = i915_gem_object_release_phys, | |
280 | }; | |
281 | ||
35a9611c | 282 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
283 | { |
284 | struct i915_vma *vma; | |
285 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
286 | int ret; |
287 | ||
288 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 289 | |
02bef8f9 CW |
290 | /* Closed vma are removed from the obj->vma_list - but they may |
291 | * still have an active binding on the object. To remove those we | |
292 | * must wait for all rendering to complete to the object (as unbinding | |
293 | * must anyway), and retire the requests. | |
aa653a68 | 294 | */ |
02bef8f9 CW |
295 | ret = i915_gem_object_wait_rendering(obj, false); |
296 | if (ret) | |
297 | return ret; | |
298 | ||
299 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
300 | ||
aa653a68 CW |
301 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
302 | struct i915_vma, | |
303 | obj_link))) { | |
304 | list_move_tail(&vma->obj_link, &still_in_list); | |
305 | ret = i915_vma_unbind(vma); | |
306 | if (ret) | |
307 | break; | |
308 | } | |
309 | list_splice(&still_in_list, &obj->vma_list); | |
310 | ||
311 | return ret; | |
312 | } | |
313 | ||
00e60f26 CW |
314 | /** |
315 | * Ensures that all rendering to the object has completed and the object is | |
316 | * safe to unbind from the GTT or access from the CPU. | |
317 | * @obj: i915 gem object | |
318 | * @readonly: waiting for just read access or read-write access | |
319 | */ | |
320 | int | |
321 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
322 | bool readonly) | |
323 | { | |
324 | struct reservation_object *resv; | |
325 | struct i915_gem_active *active; | |
326 | unsigned long active_mask; | |
327 | int idx; | |
328 | ||
329 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
330 | ||
331 | if (!readonly) { | |
332 | active = obj->last_read; | |
333 | active_mask = i915_gem_object_get_active(obj); | |
334 | } else { | |
335 | active_mask = 1; | |
336 | active = &obj->last_write; | |
337 | } | |
338 | ||
339 | for_each_active(active_mask, idx) { | |
340 | int ret; | |
341 | ||
342 | ret = i915_gem_active_wait(&active[idx], | |
343 | &obj->base.dev->struct_mutex); | |
344 | if (ret) | |
345 | return ret; | |
346 | } | |
347 | ||
348 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
349 | if (resv) { | |
350 | long err; | |
351 | ||
352 | err = reservation_object_wait_timeout_rcu(resv, !readonly, true, | |
353 | MAX_SCHEDULE_TIMEOUT); | |
354 | if (err < 0) | |
355 | return err; | |
356 | } | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
b8f9096d CW |
361 | /* A nonblocking variant of the above wait. Must be called prior to |
362 | * acquiring the mutex for the object, as the object state may change | |
363 | * during this call. A reference must be held by the caller for the object. | |
00e60f26 CW |
364 | */ |
365 | static __must_check int | |
b8f9096d CW |
366 | __unsafe_wait_rendering(struct drm_i915_gem_object *obj, |
367 | struct intel_rps_client *rps, | |
368 | bool readonly) | |
00e60f26 | 369 | { |
00e60f26 CW |
370 | struct i915_gem_active *active; |
371 | unsigned long active_mask; | |
b8f9096d | 372 | int idx; |
00e60f26 | 373 | |
b8f9096d | 374 | active_mask = __I915_BO_ACTIVE(obj); |
00e60f26 CW |
375 | if (!active_mask) |
376 | return 0; | |
377 | ||
378 | if (!readonly) { | |
379 | active = obj->last_read; | |
380 | } else { | |
381 | active_mask = 1; | |
382 | active = &obj->last_write; | |
383 | } | |
384 | ||
b8f9096d CW |
385 | for_each_active(active_mask, idx) { |
386 | int ret; | |
00e60f26 | 387 | |
b8f9096d | 388 | ret = i915_gem_active_wait_unlocked(&active[idx], |
ea746f36 CW |
389 | I915_WAIT_INTERRUPTIBLE, |
390 | NULL, rps); | |
b8f9096d CW |
391 | if (ret) |
392 | return ret; | |
00e60f26 CW |
393 | } |
394 | ||
b8f9096d | 395 | return 0; |
00e60f26 CW |
396 | } |
397 | ||
398 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
399 | { | |
400 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
401 | ||
402 | return &fpriv->rps; | |
403 | } | |
404 | ||
00731155 CW |
405 | int |
406 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
407 | int align) | |
408 | { | |
409 | drm_dma_handle_t *phys; | |
6a2c4232 | 410 | int ret; |
00731155 CW |
411 | |
412 | if (obj->phys_handle) { | |
413 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
414 | return -EBUSY; | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
419 | if (obj->madv != I915_MADV_WILLNEED) | |
420 | return -EFAULT; | |
421 | ||
422 | if (obj->base.filp == NULL) | |
423 | return -EINVAL; | |
424 | ||
4717ca9e CW |
425 | ret = i915_gem_object_unbind(obj); |
426 | if (ret) | |
427 | return ret; | |
428 | ||
429 | ret = i915_gem_object_put_pages(obj); | |
6a2c4232 CW |
430 | if (ret) |
431 | return ret; | |
432 | ||
00731155 CW |
433 | /* create a new object */ |
434 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
435 | if (!phys) | |
436 | return -ENOMEM; | |
437 | ||
00731155 | 438 | obj->phys_handle = phys; |
6a2c4232 CW |
439 | obj->ops = &i915_gem_phys_ops; |
440 | ||
441 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
442 | } |
443 | ||
444 | static int | |
445 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
446 | struct drm_i915_gem_pwrite *args, | |
447 | struct drm_file *file_priv) | |
448 | { | |
449 | struct drm_device *dev = obj->base.dev; | |
450 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 451 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
063e4e6b | 452 | int ret = 0; |
6a2c4232 CW |
453 | |
454 | /* We manually control the domain here and pretend that it | |
455 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
456 | */ | |
457 | ret = i915_gem_object_wait_rendering(obj, false); | |
458 | if (ret) | |
459 | return ret; | |
00731155 | 460 | |
77a0d1ca | 461 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
462 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
463 | unsigned long unwritten; | |
464 | ||
465 | /* The physical object once assigned is fixed for the lifetime | |
466 | * of the obj, so we can safely drop the lock and continue | |
467 | * to access vaddr. | |
468 | */ | |
469 | mutex_unlock(&dev->struct_mutex); | |
470 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
471 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
472 | if (unwritten) { |
473 | ret = -EFAULT; | |
474 | goto out; | |
475 | } | |
00731155 CW |
476 | } |
477 | ||
6a2c4232 | 478 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 479 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
480 | |
481 | out: | |
de152b62 | 482 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 483 | return ret; |
00731155 CW |
484 | } |
485 | ||
42dcedd4 CW |
486 | void *i915_gem_object_alloc(struct drm_device *dev) |
487 | { | |
fac5e23e | 488 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 489 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
490 | } |
491 | ||
492 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
493 | { | |
fac5e23e | 494 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 495 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
496 | } |
497 | ||
ff72145b DA |
498 | static int |
499 | i915_gem_create(struct drm_file *file, | |
500 | struct drm_device *dev, | |
501 | uint64_t size, | |
502 | uint32_t *handle_p) | |
673a394b | 503 | { |
05394f39 | 504 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
505 | int ret; |
506 | u32 handle; | |
673a394b | 507 | |
ff72145b | 508 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
509 | if (size == 0) |
510 | return -EINVAL; | |
673a394b EA |
511 | |
512 | /* Allocate the new object */ | |
d37cd8a8 | 513 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
514 | if (IS_ERR(obj)) |
515 | return PTR_ERR(obj); | |
673a394b | 516 | |
05394f39 | 517 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 518 | /* drop reference from allocate - handle holds it now */ |
34911fd3 | 519 | i915_gem_object_put_unlocked(obj); |
d861e338 DV |
520 | if (ret) |
521 | return ret; | |
202f2fef | 522 | |
ff72145b | 523 | *handle_p = handle; |
673a394b EA |
524 | return 0; |
525 | } | |
526 | ||
ff72145b DA |
527 | int |
528 | i915_gem_dumb_create(struct drm_file *file, | |
529 | struct drm_device *dev, | |
530 | struct drm_mode_create_dumb *args) | |
531 | { | |
532 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 533 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
534 | args->size = args->pitch * args->height; |
535 | return i915_gem_create(file, dev, | |
da6b51d0 | 536 | args->size, &args->handle); |
ff72145b DA |
537 | } |
538 | ||
ff72145b DA |
539 | /** |
540 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
541 | * @dev: drm device pointer |
542 | * @data: ioctl data blob | |
543 | * @file: drm file pointer | |
ff72145b DA |
544 | */ |
545 | int | |
546 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
547 | struct drm_file *file) | |
548 | { | |
549 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 550 | |
ff72145b | 551 | return i915_gem_create(file, dev, |
da6b51d0 | 552 | args->size, &args->handle); |
ff72145b DA |
553 | } |
554 | ||
8461d226 DV |
555 | static inline int |
556 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
557 | const char *gpu_vaddr, int gpu_offset, | |
558 | int length) | |
559 | { | |
560 | int ret, cpu_offset = 0; | |
561 | ||
562 | while (length > 0) { | |
563 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
564 | int this_length = min(cacheline_end - gpu_offset, length); | |
565 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
566 | ||
567 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
568 | gpu_vaddr + swizzled_gpu_offset, | |
569 | this_length); | |
570 | if (ret) | |
571 | return ret + length; | |
572 | ||
573 | cpu_offset += this_length; | |
574 | gpu_offset += this_length; | |
575 | length -= this_length; | |
576 | } | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
8c59967c | 581 | static inline int |
4f0c7cfb BW |
582 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
583 | const char __user *cpu_vaddr, | |
8c59967c DV |
584 | int length) |
585 | { | |
586 | int ret, cpu_offset = 0; | |
587 | ||
588 | while (length > 0) { | |
589 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
590 | int this_length = min(cacheline_end - gpu_offset, length); | |
591 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
592 | ||
593 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
594 | cpu_vaddr + cpu_offset, | |
595 | this_length); | |
596 | if (ret) | |
597 | return ret + length; | |
598 | ||
599 | cpu_offset += this_length; | |
600 | gpu_offset += this_length; | |
601 | length -= this_length; | |
602 | } | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
4c914c0c BV |
607 | /* |
608 | * Pins the specified object's pages and synchronizes the object with | |
609 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
610 | * flush the object from the CPU cache. | |
611 | */ | |
612 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 613 | unsigned int *needs_clflush) |
4c914c0c BV |
614 | { |
615 | int ret; | |
616 | ||
617 | *needs_clflush = 0; | |
618 | ||
43394c7d CW |
619 | if (!i915_gem_object_has_struct_page(obj)) |
620 | return -ENODEV; | |
4c914c0c | 621 | |
c13d87ea CW |
622 | ret = i915_gem_object_wait_rendering(obj, true); |
623 | if (ret) | |
624 | return ret; | |
625 | ||
9764951e CW |
626 | ret = i915_gem_object_get_pages(obj); |
627 | if (ret) | |
628 | return ret; | |
629 | ||
630 | i915_gem_object_pin_pages(obj); | |
631 | ||
a314d5cb CW |
632 | i915_gem_object_flush_gtt_write_domain(obj); |
633 | ||
43394c7d CW |
634 | /* If we're not in the cpu read domain, set ourself into the gtt |
635 | * read domain and manually flush cachelines (if required). This | |
636 | * optimizes for the case when the gpu will dirty the data | |
637 | * anyway again before the next pread happens. | |
638 | */ | |
639 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
4c914c0c BV |
640 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
641 | obj->cache_level); | |
43394c7d | 642 | |
43394c7d CW |
643 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
644 | ret = i915_gem_object_set_to_cpu_domain(obj, false); | |
9764951e CW |
645 | if (ret) |
646 | goto err_unpin; | |
647 | ||
43394c7d | 648 | *needs_clflush = 0; |
4c914c0c BV |
649 | } |
650 | ||
9764951e | 651 | /* return with the pages pinned */ |
43394c7d | 652 | return 0; |
9764951e CW |
653 | |
654 | err_unpin: | |
655 | i915_gem_object_unpin_pages(obj); | |
656 | return ret; | |
43394c7d CW |
657 | } |
658 | ||
659 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
660 | unsigned int *needs_clflush) | |
661 | { | |
662 | int ret; | |
663 | ||
664 | *needs_clflush = 0; | |
665 | if (!i915_gem_object_has_struct_page(obj)) | |
666 | return -ENODEV; | |
667 | ||
668 | ret = i915_gem_object_wait_rendering(obj, false); | |
669 | if (ret) | |
670 | return ret; | |
671 | ||
9764951e CW |
672 | ret = i915_gem_object_get_pages(obj); |
673 | if (ret) | |
674 | return ret; | |
675 | ||
676 | i915_gem_object_pin_pages(obj); | |
677 | ||
a314d5cb CW |
678 | i915_gem_object_flush_gtt_write_domain(obj); |
679 | ||
43394c7d CW |
680 | /* If we're not in the cpu write domain, set ourself into the |
681 | * gtt write domain and manually flush cachelines (as required). | |
682 | * This optimizes for the case when the gpu will use the data | |
683 | * right away and we therefore have to clflush anyway. | |
684 | */ | |
685 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
686 | *needs_clflush |= cpu_write_needs_clflush(obj) << 1; | |
687 | ||
688 | /* Same trick applies to invalidate partially written cachelines read | |
689 | * before writing. | |
690 | */ | |
691 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
692 | *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev, | |
693 | obj->cache_level); | |
694 | ||
43394c7d CW |
695 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
696 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
9764951e CW |
697 | if (ret) |
698 | goto err_unpin; | |
699 | ||
43394c7d CW |
700 | *needs_clflush = 0; |
701 | } | |
702 | ||
703 | if ((*needs_clflush & CLFLUSH_AFTER) == 0) | |
704 | obj->cache_dirty = true; | |
705 | ||
706 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
707 | obj->dirty = 1; | |
9764951e | 708 | /* return with the pages pinned */ |
43394c7d | 709 | return 0; |
9764951e CW |
710 | |
711 | err_unpin: | |
712 | i915_gem_object_unpin_pages(obj); | |
713 | return ret; | |
4c914c0c BV |
714 | } |
715 | ||
d174bd64 DV |
716 | /* Per-page copy function for the shmem pread fastpath. |
717 | * Flushes invalid cachelines before reading the target if | |
718 | * needs_clflush is set. */ | |
eb01459f | 719 | static int |
d174bd64 DV |
720 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
721 | char __user *user_data, | |
722 | bool page_do_bit17_swizzling, bool needs_clflush) | |
723 | { | |
724 | char *vaddr; | |
725 | int ret; | |
726 | ||
e7e58eb5 | 727 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
728 | return -EINVAL; |
729 | ||
730 | vaddr = kmap_atomic(page); | |
731 | if (needs_clflush) | |
732 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
733 | page_length); | |
734 | ret = __copy_to_user_inatomic(user_data, | |
735 | vaddr + shmem_page_offset, | |
736 | page_length); | |
737 | kunmap_atomic(vaddr); | |
738 | ||
f60d7f0c | 739 | return ret ? -EFAULT : 0; |
d174bd64 DV |
740 | } |
741 | ||
23c18c71 DV |
742 | static void |
743 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
744 | bool swizzled) | |
745 | { | |
e7e58eb5 | 746 | if (unlikely(swizzled)) { |
23c18c71 DV |
747 | unsigned long start = (unsigned long) addr; |
748 | unsigned long end = (unsigned long) addr + length; | |
749 | ||
750 | /* For swizzling simply ensure that we always flush both | |
751 | * channels. Lame, but simple and it works. Swizzled | |
752 | * pwrite/pread is far from a hotpath - current userspace | |
753 | * doesn't use it at all. */ | |
754 | start = round_down(start, 128); | |
755 | end = round_up(end, 128); | |
756 | ||
757 | drm_clflush_virt_range((void *)start, end - start); | |
758 | } else { | |
759 | drm_clflush_virt_range(addr, length); | |
760 | } | |
761 | ||
762 | } | |
763 | ||
d174bd64 DV |
764 | /* Only difference to the fast-path function is that this can handle bit17 |
765 | * and uses non-atomic copy and kmap functions. */ | |
766 | static int | |
767 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
768 | char __user *user_data, | |
769 | bool page_do_bit17_swizzling, bool needs_clflush) | |
770 | { | |
771 | char *vaddr; | |
772 | int ret; | |
773 | ||
774 | vaddr = kmap(page); | |
775 | if (needs_clflush) | |
23c18c71 DV |
776 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
777 | page_length, | |
778 | page_do_bit17_swizzling); | |
d174bd64 DV |
779 | |
780 | if (page_do_bit17_swizzling) | |
781 | ret = __copy_to_user_swizzled(user_data, | |
782 | vaddr, shmem_page_offset, | |
783 | page_length); | |
784 | else | |
785 | ret = __copy_to_user(user_data, | |
786 | vaddr + shmem_page_offset, | |
787 | page_length); | |
788 | kunmap(page); | |
789 | ||
f60d7f0c | 790 | return ret ? - EFAULT : 0; |
d174bd64 DV |
791 | } |
792 | ||
b50a5371 AS |
793 | static inline unsigned long |
794 | slow_user_access(struct io_mapping *mapping, | |
795 | uint64_t page_base, int page_offset, | |
796 | char __user *user_data, | |
797 | unsigned long length, bool pwrite) | |
798 | { | |
799 | void __iomem *ioaddr; | |
800 | void *vaddr; | |
801 | uint64_t unwritten; | |
802 | ||
803 | ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE); | |
804 | /* We can use the cpu mem copy function because this is X86. */ | |
805 | vaddr = (void __force *)ioaddr + page_offset; | |
806 | if (pwrite) | |
807 | unwritten = __copy_from_user(vaddr, user_data, length); | |
808 | else | |
809 | unwritten = __copy_to_user(user_data, vaddr, length); | |
810 | ||
811 | io_mapping_unmap(ioaddr); | |
812 | return unwritten; | |
813 | } | |
814 | ||
815 | static int | |
816 | i915_gem_gtt_pread(struct drm_device *dev, | |
817 | struct drm_i915_gem_object *obj, uint64_t size, | |
818 | uint64_t data_offset, uint64_t data_ptr) | |
819 | { | |
fac5e23e | 820 | struct drm_i915_private *dev_priv = to_i915(dev); |
b50a5371 | 821 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
058d88c4 | 822 | struct i915_vma *vma; |
b50a5371 AS |
823 | struct drm_mm_node node; |
824 | char __user *user_data; | |
825 | uint64_t remain; | |
826 | uint64_t offset; | |
827 | int ret; | |
828 | ||
058d88c4 | 829 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); |
18034584 CW |
830 | if (!IS_ERR(vma)) { |
831 | node.start = i915_ggtt_offset(vma); | |
832 | node.allocated = false; | |
49ef5294 | 833 | ret = i915_vma_put_fence(vma); |
18034584 CW |
834 | if (ret) { |
835 | i915_vma_unpin(vma); | |
836 | vma = ERR_PTR(ret); | |
837 | } | |
838 | } | |
058d88c4 | 839 | if (IS_ERR(vma)) { |
b50a5371 AS |
840 | ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE); |
841 | if (ret) | |
842 | goto out; | |
843 | ||
844 | ret = i915_gem_object_get_pages(obj); | |
845 | if (ret) { | |
846 | remove_mappable_node(&node); | |
847 | goto out; | |
848 | } | |
849 | ||
850 | i915_gem_object_pin_pages(obj); | |
b50a5371 AS |
851 | } |
852 | ||
853 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
854 | if (ret) | |
855 | goto out_unpin; | |
856 | ||
857 | user_data = u64_to_user_ptr(data_ptr); | |
858 | remain = size; | |
859 | offset = data_offset; | |
860 | ||
861 | mutex_unlock(&dev->struct_mutex); | |
862 | if (likely(!i915.prefault_disable)) { | |
863 | ret = fault_in_multipages_writeable(user_data, remain); | |
864 | if (ret) { | |
865 | mutex_lock(&dev->struct_mutex); | |
866 | goto out_unpin; | |
867 | } | |
868 | } | |
869 | ||
870 | while (remain > 0) { | |
871 | /* Operation in this page | |
872 | * | |
873 | * page_base = page offset within aperture | |
874 | * page_offset = offset within page | |
875 | * page_length = bytes to copy for this page | |
876 | */ | |
877 | u32 page_base = node.start; | |
878 | unsigned page_offset = offset_in_page(offset); | |
879 | unsigned page_length = PAGE_SIZE - page_offset; | |
880 | page_length = remain < page_length ? remain : page_length; | |
881 | if (node.allocated) { | |
882 | wmb(); | |
883 | ggtt->base.insert_page(&ggtt->base, | |
884 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
885 | node.start, | |
886 | I915_CACHE_NONE, 0); | |
887 | wmb(); | |
888 | } else { | |
889 | page_base += offset & PAGE_MASK; | |
890 | } | |
891 | /* This is a slow read/write as it tries to read from | |
892 | * and write to user memory which may result into page | |
893 | * faults, and so we cannot perform this under struct_mutex. | |
894 | */ | |
f7bbe788 | 895 | if (slow_user_access(&ggtt->mappable, page_base, |
b50a5371 AS |
896 | page_offset, user_data, |
897 | page_length, false)) { | |
898 | ret = -EFAULT; | |
899 | break; | |
900 | } | |
901 | ||
902 | remain -= page_length; | |
903 | user_data += page_length; | |
904 | offset += page_length; | |
905 | } | |
906 | ||
907 | mutex_lock(&dev->struct_mutex); | |
908 | if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
909 | /* The user has modified the object whilst we tried | |
910 | * reading from it, and we now have no idea what domain | |
911 | * the pages should be in. As we have just been touching | |
912 | * them directly, flush everything back to the GTT | |
913 | * domain. | |
914 | */ | |
915 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
916 | } | |
917 | ||
918 | out_unpin: | |
919 | if (node.allocated) { | |
920 | wmb(); | |
921 | ggtt->base.clear_range(&ggtt->base, | |
922 | node.start, node.size, | |
923 | true); | |
924 | i915_gem_object_unpin_pages(obj); | |
925 | remove_mappable_node(&node); | |
926 | } else { | |
058d88c4 | 927 | i915_vma_unpin(vma); |
b50a5371 AS |
928 | } |
929 | out: | |
930 | return ret; | |
931 | } | |
932 | ||
eb01459f | 933 | static int |
dbf7bff0 DV |
934 | i915_gem_shmem_pread(struct drm_device *dev, |
935 | struct drm_i915_gem_object *obj, | |
936 | struct drm_i915_gem_pread *args, | |
937 | struct drm_file *file) | |
eb01459f | 938 | { |
8461d226 | 939 | char __user *user_data; |
eb01459f | 940 | ssize_t remain; |
8461d226 | 941 | loff_t offset; |
eb2c0c81 | 942 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 943 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 944 | int prefaulted = 0; |
8489731c | 945 | int needs_clflush = 0; |
67d5a50c | 946 | struct sg_page_iter sg_iter; |
eb01459f | 947 | |
4c914c0c | 948 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
949 | if (ret) |
950 | return ret; | |
951 | ||
43394c7d CW |
952 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
953 | user_data = u64_to_user_ptr(args->data_ptr); | |
8461d226 | 954 | offset = args->offset; |
43394c7d | 955 | remain = args->size; |
eb01459f | 956 | |
67d5a50c ID |
957 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
958 | offset >> PAGE_SHIFT) { | |
2db76d7c | 959 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
960 | |
961 | if (remain <= 0) | |
962 | break; | |
963 | ||
eb01459f EA |
964 | /* Operation in this page |
965 | * | |
eb01459f | 966 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
967 | * page_length = bytes to copy for this page |
968 | */ | |
c8cbbb8b | 969 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
970 | page_length = remain; |
971 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
972 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 973 | |
8461d226 DV |
974 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
975 | (page_to_phys(page) & (1 << 17)) != 0; | |
976 | ||
d174bd64 DV |
977 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
978 | user_data, page_do_bit17_swizzling, | |
979 | needs_clflush); | |
980 | if (ret == 0) | |
981 | goto next_page; | |
dbf7bff0 | 982 | |
dbf7bff0 DV |
983 | mutex_unlock(&dev->struct_mutex); |
984 | ||
d330a953 | 985 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 986 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
987 | /* Userspace is tricking us, but we've already clobbered |
988 | * its pages with the prefault and promised to write the | |
989 | * data up to the first fault. Hence ignore any errors | |
990 | * and just continue. */ | |
991 | (void)ret; | |
992 | prefaulted = 1; | |
993 | } | |
eb01459f | 994 | |
d174bd64 DV |
995 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
996 | user_data, page_do_bit17_swizzling, | |
997 | needs_clflush); | |
eb01459f | 998 | |
dbf7bff0 | 999 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 1000 | |
f60d7f0c | 1001 | if (ret) |
8461d226 | 1002 | goto out; |
8461d226 | 1003 | |
17793c9a | 1004 | next_page: |
eb01459f | 1005 | remain -= page_length; |
8461d226 | 1006 | user_data += page_length; |
eb01459f EA |
1007 | offset += page_length; |
1008 | } | |
1009 | ||
4f27b75d | 1010 | out: |
43394c7d | 1011 | i915_gem_obj_finish_shmem_access(obj); |
f60d7f0c | 1012 | |
eb01459f EA |
1013 | return ret; |
1014 | } | |
1015 | ||
673a394b EA |
1016 | /** |
1017 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1018 | * @dev: drm device pointer |
1019 | * @data: ioctl data blob | |
1020 | * @file: drm file pointer | |
673a394b EA |
1021 | * |
1022 | * On error, the contents of *data are undefined. | |
1023 | */ | |
1024 | int | |
1025 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1026 | struct drm_file *file) |
673a394b EA |
1027 | { |
1028 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1029 | struct drm_i915_gem_object *obj; |
35b62a89 | 1030 | int ret = 0; |
673a394b | 1031 | |
51311d0a CW |
1032 | if (args->size == 0) |
1033 | return 0; | |
1034 | ||
1035 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1036 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1037 | args->size)) |
1038 | return -EFAULT; | |
1039 | ||
03ac0642 | 1040 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1041 | if (!obj) |
1042 | return -ENOENT; | |
673a394b | 1043 | |
7dcd2499 | 1044 | /* Bounds check source. */ |
05394f39 CW |
1045 | if (args->offset > obj->base.size || |
1046 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1047 | ret = -EINVAL; |
258a5ede | 1048 | goto err; |
ce9d419d CW |
1049 | } |
1050 | ||
db53a302 CW |
1051 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1052 | ||
258a5ede CW |
1053 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), true); |
1054 | if (ret) | |
1055 | goto err; | |
1056 | ||
1057 | ret = i915_mutex_lock_interruptible(dev); | |
1058 | if (ret) | |
1059 | goto err; | |
1060 | ||
dbf7bff0 | 1061 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 1062 | |
b50a5371 | 1063 | /* pread for non shmem backed objects */ |
1dd5b6f2 CW |
1064 | if (ret == -EFAULT || ret == -ENODEV) { |
1065 | intel_runtime_pm_get(to_i915(dev)); | |
b50a5371 AS |
1066 | ret = i915_gem_gtt_pread(dev, obj, args->size, |
1067 | args->offset, args->data_ptr); | |
1dd5b6f2 CW |
1068 | intel_runtime_pm_put(to_i915(dev)); |
1069 | } | |
b50a5371 | 1070 | |
f8c417cd | 1071 | i915_gem_object_put(obj); |
4f27b75d | 1072 | mutex_unlock(&dev->struct_mutex); |
258a5ede CW |
1073 | |
1074 | return ret; | |
1075 | ||
1076 | err: | |
1077 | i915_gem_object_put_unlocked(obj); | |
eb01459f | 1078 | return ret; |
673a394b EA |
1079 | } |
1080 | ||
0839ccb8 KP |
1081 | /* This is the fast write path which cannot handle |
1082 | * page faults in the source data | |
9b7530cc | 1083 | */ |
0839ccb8 KP |
1084 | |
1085 | static inline int | |
1086 | fast_user_write(struct io_mapping *mapping, | |
1087 | loff_t page_base, int page_offset, | |
1088 | char __user *user_data, | |
1089 | int length) | |
9b7530cc | 1090 | { |
4f0c7cfb BW |
1091 | void __iomem *vaddr_atomic; |
1092 | void *vaddr; | |
0839ccb8 | 1093 | unsigned long unwritten; |
9b7530cc | 1094 | |
3e4d3af5 | 1095 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
1096 | /* We can use the cpu mem copy function because this is X86. */ |
1097 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
1098 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 1099 | user_data, length); |
3e4d3af5 | 1100 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 1101 | return unwritten; |
0839ccb8 KP |
1102 | } |
1103 | ||
3de09aa3 EA |
1104 | /** |
1105 | * This is the fast pwrite path, where we copy the data directly from the | |
1106 | * user into the GTT, uncached. | |
62f90b38 | 1107 | * @i915: i915 device private data |
14bb2c11 TU |
1108 | * @obj: i915 gem object |
1109 | * @args: pwrite arguments structure | |
1110 | * @file: drm file pointer | |
3de09aa3 | 1111 | */ |
673a394b | 1112 | static int |
4f1959ee | 1113 | i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915, |
05394f39 | 1114 | struct drm_i915_gem_object *obj, |
3de09aa3 | 1115 | struct drm_i915_gem_pwrite *args, |
05394f39 | 1116 | struct drm_file *file) |
673a394b | 1117 | { |
4f1959ee | 1118 | struct i915_ggtt *ggtt = &i915->ggtt; |
b50a5371 | 1119 | struct drm_device *dev = obj->base.dev; |
058d88c4 | 1120 | struct i915_vma *vma; |
4f1959ee AS |
1121 | struct drm_mm_node node; |
1122 | uint64_t remain, offset; | |
673a394b | 1123 | char __user *user_data; |
4f1959ee | 1124 | int ret; |
b50a5371 AS |
1125 | bool hit_slow_path = false; |
1126 | ||
3e510a8e | 1127 | if (i915_gem_object_is_tiled(obj)) |
b50a5371 | 1128 | return -EFAULT; |
935aaa69 | 1129 | |
058d88c4 | 1130 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1131 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1132 | if (!IS_ERR(vma)) { |
1133 | node.start = i915_ggtt_offset(vma); | |
1134 | node.allocated = false; | |
49ef5294 | 1135 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1136 | if (ret) { |
1137 | i915_vma_unpin(vma); | |
1138 | vma = ERR_PTR(ret); | |
1139 | } | |
1140 | } | |
058d88c4 | 1141 | if (IS_ERR(vma)) { |
4f1959ee AS |
1142 | ret = insert_mappable_node(i915, &node, PAGE_SIZE); |
1143 | if (ret) | |
1144 | goto out; | |
1145 | ||
1146 | ret = i915_gem_object_get_pages(obj); | |
1147 | if (ret) { | |
1148 | remove_mappable_node(&node); | |
1149 | goto out; | |
1150 | } | |
1151 | ||
1152 | i915_gem_object_pin_pages(obj); | |
4f1959ee | 1153 | } |
935aaa69 DV |
1154 | |
1155 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1156 | if (ret) | |
1157 | goto out_unpin; | |
1158 | ||
b19482d7 | 1159 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
4f1959ee | 1160 | obj->dirty = true; |
063e4e6b | 1161 | |
4f1959ee AS |
1162 | user_data = u64_to_user_ptr(args->data_ptr); |
1163 | offset = args->offset; | |
1164 | remain = args->size; | |
1165 | while (remain) { | |
673a394b EA |
1166 | /* Operation in this page |
1167 | * | |
0839ccb8 KP |
1168 | * page_base = page offset within aperture |
1169 | * page_offset = offset within page | |
1170 | * page_length = bytes to copy for this page | |
673a394b | 1171 | */ |
4f1959ee AS |
1172 | u32 page_base = node.start; |
1173 | unsigned page_offset = offset_in_page(offset); | |
1174 | unsigned page_length = PAGE_SIZE - page_offset; | |
1175 | page_length = remain < page_length ? remain : page_length; | |
1176 | if (node.allocated) { | |
1177 | wmb(); /* flush the write before we modify the GGTT */ | |
1178 | ggtt->base.insert_page(&ggtt->base, | |
1179 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1180 | node.start, I915_CACHE_NONE, 0); | |
1181 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1182 | } else { | |
1183 | page_base += offset & PAGE_MASK; | |
1184 | } | |
0839ccb8 | 1185 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1186 | * source page isn't available. Return the error and we'll |
1187 | * retry in the slow path. | |
b50a5371 AS |
1188 | * If the object is non-shmem backed, we retry again with the |
1189 | * path that handles page fault. | |
0839ccb8 | 1190 | */ |
f7bbe788 | 1191 | if (fast_user_write(&ggtt->mappable, page_base, |
935aaa69 | 1192 | page_offset, user_data, page_length)) { |
b50a5371 AS |
1193 | hit_slow_path = true; |
1194 | mutex_unlock(&dev->struct_mutex); | |
f7bbe788 | 1195 | if (slow_user_access(&ggtt->mappable, |
b50a5371 AS |
1196 | page_base, |
1197 | page_offset, user_data, | |
1198 | page_length, true)) { | |
1199 | ret = -EFAULT; | |
1200 | mutex_lock(&dev->struct_mutex); | |
1201 | goto out_flush; | |
1202 | } | |
1203 | ||
1204 | mutex_lock(&dev->struct_mutex); | |
935aaa69 | 1205 | } |
673a394b | 1206 | |
0839ccb8 KP |
1207 | remain -= page_length; |
1208 | user_data += page_length; | |
1209 | offset += page_length; | |
673a394b | 1210 | } |
673a394b | 1211 | |
063e4e6b | 1212 | out_flush: |
b50a5371 AS |
1213 | if (hit_slow_path) { |
1214 | if (ret == 0 && | |
1215 | (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
1216 | /* The user has modified the object whilst we tried | |
1217 | * reading from it, and we now have no idea what domain | |
1218 | * the pages should be in. As we have just been touching | |
1219 | * them directly, flush everything back to the GTT | |
1220 | * domain. | |
1221 | */ | |
1222 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1223 | } | |
1224 | } | |
1225 | ||
b19482d7 | 1226 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
935aaa69 | 1227 | out_unpin: |
4f1959ee AS |
1228 | if (node.allocated) { |
1229 | wmb(); | |
1230 | ggtt->base.clear_range(&ggtt->base, | |
1231 | node.start, node.size, | |
1232 | true); | |
1233 | i915_gem_object_unpin_pages(obj); | |
1234 | remove_mappable_node(&node); | |
1235 | } else { | |
058d88c4 | 1236 | i915_vma_unpin(vma); |
4f1959ee | 1237 | } |
935aaa69 | 1238 | out: |
3de09aa3 | 1239 | return ret; |
673a394b EA |
1240 | } |
1241 | ||
d174bd64 DV |
1242 | /* Per-page copy function for the shmem pwrite fastpath. |
1243 | * Flushes invalid cachelines before writing to the target if | |
1244 | * needs_clflush_before is set and flushes out any written cachelines after | |
1245 | * writing if needs_clflush is set. */ | |
3043c60c | 1246 | static int |
d174bd64 DV |
1247 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
1248 | char __user *user_data, | |
1249 | bool page_do_bit17_swizzling, | |
1250 | bool needs_clflush_before, | |
1251 | bool needs_clflush_after) | |
673a394b | 1252 | { |
d174bd64 | 1253 | char *vaddr; |
673a394b | 1254 | int ret; |
3de09aa3 | 1255 | |
e7e58eb5 | 1256 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 1257 | return -EINVAL; |
3de09aa3 | 1258 | |
d174bd64 DV |
1259 | vaddr = kmap_atomic(page); |
1260 | if (needs_clflush_before) | |
1261 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1262 | page_length); | |
c2831a94 CW |
1263 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
1264 | user_data, page_length); | |
d174bd64 DV |
1265 | if (needs_clflush_after) |
1266 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1267 | page_length); | |
1268 | kunmap_atomic(vaddr); | |
3de09aa3 | 1269 | |
755d2218 | 1270 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
1271 | } |
1272 | ||
d174bd64 DV |
1273 | /* Only difference to the fast-path function is that this can handle bit17 |
1274 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 1275 | static int |
d174bd64 DV |
1276 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
1277 | char __user *user_data, | |
1278 | bool page_do_bit17_swizzling, | |
1279 | bool needs_clflush_before, | |
1280 | bool needs_clflush_after) | |
673a394b | 1281 | { |
d174bd64 DV |
1282 | char *vaddr; |
1283 | int ret; | |
e5281ccd | 1284 | |
d174bd64 | 1285 | vaddr = kmap(page); |
e7e58eb5 | 1286 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
1287 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1288 | page_length, | |
1289 | page_do_bit17_swizzling); | |
d174bd64 DV |
1290 | if (page_do_bit17_swizzling) |
1291 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
1292 | user_data, |
1293 | page_length); | |
d174bd64 DV |
1294 | else |
1295 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
1296 | user_data, | |
1297 | page_length); | |
1298 | if (needs_clflush_after) | |
23c18c71 DV |
1299 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1300 | page_length, | |
1301 | page_do_bit17_swizzling); | |
d174bd64 | 1302 | kunmap(page); |
40123c1f | 1303 | |
755d2218 | 1304 | return ret ? -EFAULT : 0; |
40123c1f EA |
1305 | } |
1306 | ||
40123c1f | 1307 | static int |
e244a443 DV |
1308 | i915_gem_shmem_pwrite(struct drm_device *dev, |
1309 | struct drm_i915_gem_object *obj, | |
1310 | struct drm_i915_gem_pwrite *args, | |
1311 | struct drm_file *file) | |
40123c1f | 1312 | { |
40123c1f | 1313 | ssize_t remain; |
8c59967c DV |
1314 | loff_t offset; |
1315 | char __user *user_data; | |
eb2c0c81 | 1316 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 1317 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 1318 | int hit_slowpath = 0; |
43394c7d | 1319 | unsigned int needs_clflush; |
67d5a50c | 1320 | struct sg_page_iter sg_iter; |
40123c1f | 1321 | |
43394c7d | 1322 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
755d2218 CW |
1323 | if (ret) |
1324 | return ret; | |
1325 | ||
43394c7d CW |
1326 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
1327 | user_data = u64_to_user_ptr(args->data_ptr); | |
673a394b | 1328 | offset = args->offset; |
43394c7d | 1329 | remain = args->size; |
673a394b | 1330 | |
67d5a50c ID |
1331 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
1332 | offset >> PAGE_SHIFT) { | |
2db76d7c | 1333 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 1334 | int partial_cacheline_write; |
e5281ccd | 1335 | |
9da3da66 CW |
1336 | if (remain <= 0) |
1337 | break; | |
1338 | ||
40123c1f EA |
1339 | /* Operation in this page |
1340 | * | |
40123c1f | 1341 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
1342 | * page_length = bytes to copy for this page |
1343 | */ | |
c8cbbb8b | 1344 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
1345 | |
1346 | page_length = remain; | |
1347 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1348 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 1349 | |
58642885 DV |
1350 | /* If we don't overwrite a cacheline completely we need to be |
1351 | * careful to have up-to-date data by first clflushing. Don't | |
1352 | * overcomplicate things and flush the entire patch. */ | |
43394c7d | 1353 | partial_cacheline_write = needs_clflush & CLFLUSH_BEFORE && |
58642885 DV |
1354 | ((shmem_page_offset | page_length) |
1355 | & (boot_cpu_data.x86_clflush_size - 1)); | |
1356 | ||
8c59967c DV |
1357 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
1358 | (page_to_phys(page) & (1 << 17)) != 0; | |
1359 | ||
d174bd64 DV |
1360 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
1361 | user_data, page_do_bit17_swizzling, | |
1362 | partial_cacheline_write, | |
43394c7d | 1363 | needs_clflush & CLFLUSH_AFTER); |
d174bd64 DV |
1364 | if (ret == 0) |
1365 | goto next_page; | |
e244a443 DV |
1366 | |
1367 | hit_slowpath = 1; | |
e244a443 | 1368 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1369 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1370 | user_data, page_do_bit17_swizzling, | |
1371 | partial_cacheline_write, | |
43394c7d | 1372 | needs_clflush & CLFLUSH_AFTER); |
40123c1f | 1373 | |
e244a443 | 1374 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1375 | |
755d2218 | 1376 | if (ret) |
8c59967c | 1377 | goto out; |
8c59967c | 1378 | |
17793c9a | 1379 | next_page: |
40123c1f | 1380 | remain -= page_length; |
8c59967c | 1381 | user_data += page_length; |
40123c1f | 1382 | offset += page_length; |
673a394b EA |
1383 | } |
1384 | ||
fbd5a26d | 1385 | out: |
43394c7d | 1386 | i915_gem_obj_finish_shmem_access(obj); |
755d2218 | 1387 | |
e244a443 | 1388 | if (hit_slowpath) { |
8dcf015e DV |
1389 | /* |
1390 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1391 | * cachelines in-line while writing and the object moved | |
1392 | * out of the cpu write domain while we've dropped the lock. | |
1393 | */ | |
43394c7d | 1394 | if (!(needs_clflush & CLFLUSH_AFTER) && |
8dcf015e | 1395 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
000433b6 | 1396 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
43394c7d | 1397 | needs_clflush |= CLFLUSH_AFTER; |
e244a443 | 1398 | } |
8c59967c | 1399 | } |
673a394b | 1400 | |
43394c7d | 1401 | if (needs_clflush & CLFLUSH_AFTER) |
c033666a | 1402 | i915_gem_chipset_flush(to_i915(dev)); |
58642885 | 1403 | |
de152b62 | 1404 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1405 | return ret; |
673a394b EA |
1406 | } |
1407 | ||
1408 | /** | |
1409 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1410 | * @dev: drm device |
1411 | * @data: ioctl data blob | |
1412 | * @file: drm file | |
673a394b EA |
1413 | * |
1414 | * On error, the contents of the buffer that were to be modified are undefined. | |
1415 | */ | |
1416 | int | |
1417 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1418 | struct drm_file *file) |
673a394b | 1419 | { |
fac5e23e | 1420 | struct drm_i915_private *dev_priv = to_i915(dev); |
673a394b | 1421 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1422 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1423 | int ret; |
1424 | ||
1425 | if (args->size == 0) | |
1426 | return 0; | |
1427 | ||
1428 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1429 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1430 | args->size)) |
1431 | return -EFAULT; | |
1432 | ||
d330a953 | 1433 | if (likely(!i915.prefault_disable)) { |
3ed605bc | 1434 | ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr), |
0b74b508 XZ |
1435 | args->size); |
1436 | if (ret) | |
1437 | return -EFAULT; | |
1438 | } | |
673a394b | 1439 | |
03ac0642 | 1440 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1441 | if (!obj) |
1442 | return -ENOENT; | |
673a394b | 1443 | |
7dcd2499 | 1444 | /* Bounds check destination. */ |
05394f39 CW |
1445 | if (args->offset > obj->base.size || |
1446 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1447 | ret = -EINVAL; |
258a5ede | 1448 | goto err; |
ce9d419d CW |
1449 | } |
1450 | ||
db53a302 CW |
1451 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1452 | ||
258a5ede CW |
1453 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), false); |
1454 | if (ret) | |
1455 | goto err; | |
1456 | ||
1457 | intel_runtime_pm_get(dev_priv); | |
1458 | ||
1459 | ret = i915_mutex_lock_interruptible(dev); | |
1460 | if (ret) | |
1461 | goto err_rpm; | |
1462 | ||
935aaa69 | 1463 | ret = -EFAULT; |
673a394b EA |
1464 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1465 | * it would end up going through the fenced access, and we'll get | |
1466 | * different detiling behavior between reading and writing. | |
1467 | * pread/pwrite currently are reading and writing from the CPU | |
1468 | * perspective, requiring manual detiling by the client. | |
1469 | */ | |
6eae0059 CW |
1470 | if (!i915_gem_object_has_struct_page(obj) || |
1471 | cpu_write_needs_clflush(obj)) { | |
4f1959ee | 1472 | ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file); |
935aaa69 DV |
1473 | /* Note that the gtt paths might fail with non-page-backed user |
1474 | * pointers (e.g. gtt mappings when moving data between | |
1475 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1476 | } |
673a394b | 1477 | |
d1054ee4 | 1478 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1479 | if (obj->phys_handle) |
1480 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1481 | else |
43394c7d | 1482 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
6a2c4232 | 1483 | } |
5c0480f2 | 1484 | |
f8c417cd | 1485 | i915_gem_object_put(obj); |
fbd5a26d | 1486 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1487 | intel_runtime_pm_put(dev_priv); |
1488 | ||
673a394b | 1489 | return ret; |
258a5ede CW |
1490 | |
1491 | err_rpm: | |
1492 | intel_runtime_pm_put(dev_priv); | |
1493 | err: | |
1494 | i915_gem_object_put_unlocked(obj); | |
1495 | return ret; | |
673a394b EA |
1496 | } |
1497 | ||
d243ad82 | 1498 | static inline enum fb_op_origin |
aeecc969 CW |
1499 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) |
1500 | { | |
50349247 CW |
1501 | return (domain == I915_GEM_DOMAIN_GTT ? |
1502 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
aeecc969 CW |
1503 | } |
1504 | ||
673a394b | 1505 | /** |
2ef7eeaa EA |
1506 | * Called when user space prepares to use an object with the CPU, either |
1507 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1508 | * @dev: drm device |
1509 | * @data: ioctl data blob | |
1510 | * @file: drm file | |
673a394b EA |
1511 | */ |
1512 | int | |
1513 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1514 | struct drm_file *file) |
673a394b EA |
1515 | { |
1516 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1517 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1518 | uint32_t read_domains = args->read_domains; |
1519 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1520 | int ret; |
1521 | ||
2ef7eeaa | 1522 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1523 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1524 | return -EINVAL; |
1525 | ||
1526 | /* Having something in the write domain implies it's in the read | |
1527 | * domain, and only that read domain. Enforce that in the request. | |
1528 | */ | |
1529 | if (write_domain != 0 && read_domains != write_domain) | |
1530 | return -EINVAL; | |
1531 | ||
03ac0642 | 1532 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1533 | if (!obj) |
1534 | return -ENOENT; | |
673a394b | 1535 | |
3236f57a CW |
1536 | /* Try to flush the object off the GPU without holding the lock. |
1537 | * We will repeat the flush holding the lock in the normal manner | |
1538 | * to catch cases where we are gazumped. | |
1539 | */ | |
b8f9096d CW |
1540 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), !write_domain); |
1541 | if (ret) | |
1542 | goto err; | |
1543 | ||
1544 | ret = i915_mutex_lock_interruptible(dev); | |
3236f57a | 1545 | if (ret) |
b8f9096d | 1546 | goto err; |
3236f57a | 1547 | |
43566ded | 1548 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1549 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1550 | else |
e47c68e9 | 1551 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1552 | |
031b698a | 1553 | if (write_domain != 0) |
aeecc969 | 1554 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); |
031b698a | 1555 | |
f8c417cd | 1556 | i915_gem_object_put(obj); |
673a394b EA |
1557 | mutex_unlock(&dev->struct_mutex); |
1558 | return ret; | |
b8f9096d CW |
1559 | |
1560 | err: | |
1561 | i915_gem_object_put_unlocked(obj); | |
1562 | return ret; | |
673a394b EA |
1563 | } |
1564 | ||
1565 | /** | |
1566 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1567 | * @dev: drm device |
1568 | * @data: ioctl data blob | |
1569 | * @file: drm file | |
673a394b EA |
1570 | */ |
1571 | int | |
1572 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1573 | struct drm_file *file) |
673a394b EA |
1574 | { |
1575 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1576 | struct drm_i915_gem_object *obj; |
c21724cc | 1577 | int err = 0; |
1d7cfea1 | 1578 | |
03ac0642 | 1579 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1580 | if (!obj) |
1581 | return -ENOENT; | |
673a394b | 1582 | |
673a394b | 1583 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1584 | if (READ_ONCE(obj->pin_display)) { |
1585 | err = i915_mutex_lock_interruptible(dev); | |
1586 | if (!err) { | |
1587 | i915_gem_object_flush_cpu_write_domain(obj); | |
1588 | mutex_unlock(&dev->struct_mutex); | |
1589 | } | |
1590 | } | |
e47c68e9 | 1591 | |
c21724cc CW |
1592 | i915_gem_object_put_unlocked(obj); |
1593 | return err; | |
673a394b EA |
1594 | } |
1595 | ||
1596 | /** | |
14bb2c11 TU |
1597 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1598 | * it is mapped to. | |
1599 | * @dev: drm device | |
1600 | * @data: ioctl data blob | |
1601 | * @file: drm file | |
673a394b EA |
1602 | * |
1603 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1604 | * imply a ref on the object itself. | |
34367381 DV |
1605 | * |
1606 | * IMPORTANT: | |
1607 | * | |
1608 | * DRM driver writers who look a this function as an example for how to do GEM | |
1609 | * mmap support, please don't implement mmap support like here. The modern way | |
1610 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1611 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1612 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1613 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1614 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1615 | */ |
1616 | int | |
1617 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1618 | struct drm_file *file) |
673a394b EA |
1619 | { |
1620 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1621 | struct drm_i915_gem_object *obj; |
673a394b EA |
1622 | unsigned long addr; |
1623 | ||
1816f923 AG |
1624 | if (args->flags & ~(I915_MMAP_WC)) |
1625 | return -EINVAL; | |
1626 | ||
568a58e5 | 1627 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1628 | return -ENODEV; |
1629 | ||
03ac0642 CW |
1630 | obj = i915_gem_object_lookup(file, args->handle); |
1631 | if (!obj) | |
bf79cb91 | 1632 | return -ENOENT; |
673a394b | 1633 | |
1286ff73 DV |
1634 | /* prime objects have no backing filp to GEM mmap |
1635 | * pages from. | |
1636 | */ | |
03ac0642 | 1637 | if (!obj->base.filp) { |
34911fd3 | 1638 | i915_gem_object_put_unlocked(obj); |
1286ff73 DV |
1639 | return -EINVAL; |
1640 | } | |
1641 | ||
03ac0642 | 1642 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1643 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1644 | args->offset); | |
1816f923 AG |
1645 | if (args->flags & I915_MMAP_WC) { |
1646 | struct mm_struct *mm = current->mm; | |
1647 | struct vm_area_struct *vma; | |
1648 | ||
80a89a5e | 1649 | if (down_write_killable(&mm->mmap_sem)) { |
34911fd3 | 1650 | i915_gem_object_put_unlocked(obj); |
80a89a5e MH |
1651 | return -EINTR; |
1652 | } | |
1816f923 AG |
1653 | vma = find_vma(mm, addr); |
1654 | if (vma) | |
1655 | vma->vm_page_prot = | |
1656 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1657 | else | |
1658 | addr = -ENOMEM; | |
1659 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1660 | |
1661 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1662 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1663 | } |
34911fd3 | 1664 | i915_gem_object_put_unlocked(obj); |
673a394b EA |
1665 | if (IS_ERR((void *)addr)) |
1666 | return addr; | |
1667 | ||
1668 | args->addr_ptr = (uint64_t) addr; | |
1669 | ||
1670 | return 0; | |
1671 | } | |
1672 | ||
03af84fe CW |
1673 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1674 | { | |
1675 | u64 size; | |
1676 | ||
1677 | size = i915_gem_object_get_stride(obj); | |
1678 | size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8; | |
1679 | ||
1680 | return size >> PAGE_SHIFT; | |
1681 | } | |
1682 | ||
4cc69075 CW |
1683 | /** |
1684 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1685 | * | |
1686 | * A history of the GTT mmap interface: | |
1687 | * | |
1688 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1689 | * aligned and suitable for fencing, and still fit into the available | |
1690 | * mappable space left by the pinned display objects. A classic problem | |
1691 | * we called the page-fault-of-doom where we would ping-pong between | |
1692 | * two objects that could not fit inside the GTT and so the memcpy | |
1693 | * would page one object in at the expense of the other between every | |
1694 | * single byte. | |
1695 | * | |
1696 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1697 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1698 | * object is too large for the available space (or simply too large | |
1699 | * for the mappable aperture!), a view is created instead and faulted | |
1700 | * into userspace. (This view is aligned and sized appropriately for | |
1701 | * fenced access.) | |
1702 | * | |
1703 | * Restrictions: | |
1704 | * | |
1705 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1706 | * hangs on some architectures, corruption on others. An attempt to service | |
1707 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1708 | * | |
1709 | * * the object must be able to fit into RAM (physical memory, though no | |
1710 | * limited to the mappable aperture). | |
1711 | * | |
1712 | * | |
1713 | * Caveats: | |
1714 | * | |
1715 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1716 | * all data to system memory. Subsequent access will not be synchronized. | |
1717 | * | |
1718 | * * all mappings are revoked on runtime device suspend. | |
1719 | * | |
1720 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1721 | * (older machines require fence register for display and blitter access | |
1722 | * as well). Contention of the fence registers will cause the previous users | |
1723 | * to be unmapped and any new access will generate new page faults. | |
1724 | * | |
1725 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1726 | * rather than the expected SIGSEGV. | |
1727 | */ | |
1728 | int i915_gem_mmap_gtt_version(void) | |
1729 | { | |
1730 | return 1; | |
1731 | } | |
1732 | ||
de151cf6 JB |
1733 | /** |
1734 | * i915_gem_fault - fault a page into the GTT | |
058d88c4 | 1735 | * @area: CPU VMA in question |
d9072a3e | 1736 | * @vmf: fault info |
de151cf6 JB |
1737 | * |
1738 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1739 | * from userspace. The fault handler takes care of binding the object to | |
1740 | * the GTT (if needed), allocating and programming a fence register (again, | |
1741 | * only if needed based on whether the old reg is still valid or the object | |
1742 | * is tiled) and inserting a new PTE into the faulting process. | |
1743 | * | |
1744 | * Note that the faulting process may involve evicting existing objects | |
1745 | * from the GTT and/or fence registers to make room. So performance may | |
1746 | * suffer if the GTT working set is large or there are few fence registers | |
1747 | * left. | |
4cc69075 CW |
1748 | * |
1749 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1750 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1751 | */ |
058d88c4 | 1752 | int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) |
de151cf6 | 1753 | { |
03af84fe | 1754 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
058d88c4 | 1755 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1756 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1757 | struct drm_i915_private *dev_priv = to_i915(dev); |
1758 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1759 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1760 | struct i915_vma *vma; |
de151cf6 | 1761 | pgoff_t page_offset; |
82118877 | 1762 | unsigned int flags; |
b8f9096d | 1763 | int ret; |
f65c9168 | 1764 | |
de151cf6 | 1765 | /* We don't use vmf->pgoff since that has the fake offset */ |
058d88c4 | 1766 | page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >> |
de151cf6 JB |
1767 | PAGE_SHIFT; |
1768 | ||
db53a302 CW |
1769 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1770 | ||
6e4930f6 | 1771 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1772 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1773 | * repeat the flush holding the lock in the normal manner to catch cases |
1774 | * where we are gazumped. | |
1775 | */ | |
b8f9096d | 1776 | ret = __unsafe_wait_rendering(obj, NULL, !write); |
6e4930f6 | 1777 | if (ret) |
b8f9096d CW |
1778 | goto err; |
1779 | ||
1780 | intel_runtime_pm_get(dev_priv); | |
1781 | ||
1782 | ret = i915_mutex_lock_interruptible(dev); | |
1783 | if (ret) | |
1784 | goto err_rpm; | |
6e4930f6 | 1785 | |
eb119bd6 CW |
1786 | /* Access to snoopable pages through the GTT is incoherent. */ |
1787 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1788 | ret = -EFAULT; |
b8f9096d | 1789 | goto err_unlock; |
eb119bd6 CW |
1790 | } |
1791 | ||
82118877 CW |
1792 | /* If the object is smaller than a couple of partial vma, it is |
1793 | * not worth only creating a single partial vma - we may as well | |
1794 | * clear enough space for the full object. | |
1795 | */ | |
1796 | flags = PIN_MAPPABLE; | |
1797 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1798 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1799 | ||
a61007a8 | 1800 | /* Now pin it into the GTT as needed */ |
82118877 | 1801 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 CW |
1802 | if (IS_ERR(vma)) { |
1803 | struct i915_ggtt_view view; | |
03af84fe CW |
1804 | unsigned int chunk_size; |
1805 | ||
a61007a8 | 1806 | /* Use a partial view if it is bigger than available space */ |
03af84fe CW |
1807 | chunk_size = MIN_CHUNK_PAGES; |
1808 | if (i915_gem_object_is_tiled(obj)) | |
1809 | chunk_size = max(chunk_size, tile_row_pages(obj)); | |
e7ded2d7 | 1810 | |
c5ad54cf JL |
1811 | memset(&view, 0, sizeof(view)); |
1812 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1813 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1814 | view.params.partial.size = | |
a61007a8 | 1815 | min_t(unsigned int, chunk_size, |
058d88c4 | 1816 | (area->vm_end - area->vm_start) / PAGE_SIZE - |
c5ad54cf | 1817 | view.params.partial.offset); |
c5ad54cf | 1818 | |
aa136d9d CW |
1819 | /* If the partial covers the entire object, just create a |
1820 | * normal VMA. | |
1821 | */ | |
1822 | if (chunk_size >= obj->base.size >> PAGE_SHIFT) | |
1823 | view.type = I915_GGTT_VIEW_NORMAL; | |
1824 | ||
50349247 CW |
1825 | /* Userspace is now writing through an untracked VMA, abandon |
1826 | * all hope that the hardware is able to track future writes. | |
1827 | */ | |
1828 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1829 | ||
a61007a8 CW |
1830 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1831 | } | |
058d88c4 CW |
1832 | if (IS_ERR(vma)) { |
1833 | ret = PTR_ERR(vma); | |
b8f9096d | 1834 | goto err_unlock; |
058d88c4 | 1835 | } |
4a684a41 | 1836 | |
c9839303 CW |
1837 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1838 | if (ret) | |
b8f9096d | 1839 | goto err_unpin; |
74898d7e | 1840 | |
49ef5294 | 1841 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1842 | if (ret) |
b8f9096d | 1843 | goto err_unpin; |
7d1c4804 | 1844 | |
b90b91d8 | 1845 | /* Finally, remap it using the new GTT offset */ |
c58305af CW |
1846 | ret = remap_io_mapping(area, |
1847 | area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT), | |
1848 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, | |
1849 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1850 | &ggtt->mappable); | |
1851 | if (ret) | |
1852 | goto err_unpin; | |
a61007a8 CW |
1853 | |
1854 | obj->fault_mappable = true; | |
b8f9096d | 1855 | err_unpin: |
058d88c4 | 1856 | __i915_vma_unpin(vma); |
b8f9096d | 1857 | err_unlock: |
de151cf6 | 1858 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1859 | err_rpm: |
1860 | intel_runtime_pm_put(dev_priv); | |
1861 | err: | |
de151cf6 | 1862 | switch (ret) { |
d9bc7e9f | 1863 | case -EIO: |
2232f031 DV |
1864 | /* |
1865 | * We eat errors when the gpu is terminally wedged to avoid | |
1866 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1867 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1868 | * and so needs to be reported. | |
1869 | */ | |
1870 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1871 | ret = VM_FAULT_SIGBUS; |
1872 | break; | |
1873 | } | |
045e769a | 1874 | case -EAGAIN: |
571c608d DV |
1875 | /* |
1876 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1877 | * handler to reset everything when re-faulting in | |
1878 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1879 | */ |
c715089f CW |
1880 | case 0: |
1881 | case -ERESTARTSYS: | |
bed636ab | 1882 | case -EINTR: |
e79e0fe3 DR |
1883 | case -EBUSY: |
1884 | /* | |
1885 | * EBUSY is ok: this just means that another thread | |
1886 | * already did the job. | |
1887 | */ | |
f65c9168 PZ |
1888 | ret = VM_FAULT_NOPAGE; |
1889 | break; | |
de151cf6 | 1890 | case -ENOMEM: |
f65c9168 PZ |
1891 | ret = VM_FAULT_OOM; |
1892 | break; | |
a7c2e1aa | 1893 | case -ENOSPC: |
45d67817 | 1894 | case -EFAULT: |
f65c9168 PZ |
1895 | ret = VM_FAULT_SIGBUS; |
1896 | break; | |
de151cf6 | 1897 | default: |
a7c2e1aa | 1898 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1899 | ret = VM_FAULT_SIGBUS; |
1900 | break; | |
de151cf6 | 1901 | } |
f65c9168 | 1902 | return ret; |
de151cf6 JB |
1903 | } |
1904 | ||
901782b2 CW |
1905 | /** |
1906 | * i915_gem_release_mmap - remove physical page mappings | |
1907 | * @obj: obj in question | |
1908 | * | |
af901ca1 | 1909 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1910 | * relinquish ownership of the pages back to the system. |
1911 | * | |
1912 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1913 | * object through the GTT and then lose the fence register due to | |
1914 | * resource pressure. Similarly if the object has been moved out of the | |
1915 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1916 | * mapping will then trigger a page fault on the next user access, allowing | |
1917 | * fixup by i915_gem_fault(). | |
1918 | */ | |
d05ca301 | 1919 | void |
05394f39 | 1920 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1921 | { |
349f2ccf CW |
1922 | /* Serialisation between user GTT access and our code depends upon |
1923 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1924 | * pagefault then has to wait until we release the mutex. | |
1925 | */ | |
1926 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
1927 | ||
6299f992 CW |
1928 | if (!obj->fault_mappable) |
1929 | return; | |
901782b2 | 1930 | |
6796cb16 DH |
1931 | drm_vma_node_unmap(&obj->base.vma_node, |
1932 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1933 | |
1934 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1935 | * memory transactions from userspace before we return. The TLB | |
1936 | * flushing implied above by changing the PTE above *should* be | |
1937 | * sufficient, an extra barrier here just provides us with a bit | |
1938 | * of paranoid documentation about our requirement to serialise | |
1939 | * memory writes before touching registers / GSM. | |
1940 | */ | |
1941 | wmb(); | |
1942 | ||
6299f992 | 1943 | obj->fault_mappable = false; |
901782b2 CW |
1944 | } |
1945 | ||
eedd10f4 CW |
1946 | void |
1947 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1948 | { | |
1949 | struct drm_i915_gem_object *obj; | |
1950 | ||
1951 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1952 | i915_gem_release_mmap(obj); | |
1953 | } | |
1954 | ||
ad1a7d20 CW |
1955 | /** |
1956 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 1957 | * @dev_priv: i915 device |
ad1a7d20 CW |
1958 | * @size: object size |
1959 | * @tiling_mode: tiling mode | |
1960 | * | |
1961 | * Return the required global GTT size for an object, taking into account | |
1962 | * potential fence register mapping. | |
1963 | */ | |
a9f1481f CW |
1964 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
1965 | u64 size, int tiling_mode) | |
92b88aeb | 1966 | { |
ad1a7d20 | 1967 | u64 ggtt_size; |
92b88aeb | 1968 | |
ad1a7d20 CW |
1969 | GEM_BUG_ON(size == 0); |
1970 | ||
a9f1481f | 1971 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
1972 | tiling_mode == I915_TILING_NONE) |
1973 | return size; | |
92b88aeb CW |
1974 | |
1975 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 1976 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 1977 | ggtt_size = 1024*1024; |
92b88aeb | 1978 | else |
ad1a7d20 | 1979 | ggtt_size = 512*1024; |
92b88aeb | 1980 | |
ad1a7d20 CW |
1981 | while (ggtt_size < size) |
1982 | ggtt_size <<= 1; | |
92b88aeb | 1983 | |
ad1a7d20 | 1984 | return ggtt_size; |
92b88aeb CW |
1985 | } |
1986 | ||
de151cf6 | 1987 | /** |
ad1a7d20 | 1988 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 1989 | * @dev_priv: i915 device |
14bb2c11 TU |
1990 | * @size: object size |
1991 | * @tiling_mode: tiling mode | |
ad1a7d20 | 1992 | * @fenced: is fenced alignment required or not |
de151cf6 | 1993 | * |
ad1a7d20 | 1994 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 1995 | * potential fence register mapping. |
de151cf6 | 1996 | */ |
a9f1481f | 1997 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 1998 | int tiling_mode, bool fenced) |
de151cf6 | 1999 | { |
ad1a7d20 CW |
2000 | GEM_BUG_ON(size == 0); |
2001 | ||
de151cf6 JB |
2002 | /* |
2003 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2004 | * if a fence register is needed for the object. | |
2005 | */ | |
a9f1481f | 2006 | if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) || |
e28f8711 | 2007 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2008 | return 4096; |
2009 | ||
a00b10c3 CW |
2010 | /* |
2011 | * Previous chips need to be aligned to the size of the smallest | |
2012 | * fence register that can contain the object. | |
2013 | */ | |
a9f1481f | 2014 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
2015 | } |
2016 | ||
d8cb5086 CW |
2017 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2018 | { | |
fac5e23e | 2019 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2020 | int err; |
da494d7c | 2021 | |
f3f6184c CW |
2022 | err = drm_gem_create_mmap_offset(&obj->base); |
2023 | if (!err) | |
2024 | return 0; | |
d8cb5086 | 2025 | |
f3f6184c CW |
2026 | /* We can idle the GPU locklessly to flush stale objects, but in order |
2027 | * to claim that space for ourselves, we need to take the big | |
2028 | * struct_mutex to free the requests+objects and allocate our slot. | |
d8cb5086 | 2029 | */ |
ea746f36 | 2030 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); |
f3f6184c CW |
2031 | if (err) |
2032 | return err; | |
2033 | ||
2034 | err = i915_mutex_lock_interruptible(&dev_priv->drm); | |
2035 | if (!err) { | |
2036 | i915_gem_retire_requests(dev_priv); | |
2037 | err = drm_gem_create_mmap_offset(&obj->base); | |
2038 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
2039 | } | |
da494d7c | 2040 | |
f3f6184c | 2041 | return err; |
d8cb5086 CW |
2042 | } |
2043 | ||
2044 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2045 | { | |
d8cb5086 CW |
2046 | drm_gem_free_mmap_offset(&obj->base); |
2047 | } | |
2048 | ||
da6b51d0 | 2049 | int |
ff72145b DA |
2050 | i915_gem_mmap_gtt(struct drm_file *file, |
2051 | struct drm_device *dev, | |
da6b51d0 | 2052 | uint32_t handle, |
ff72145b | 2053 | uint64_t *offset) |
de151cf6 | 2054 | { |
05394f39 | 2055 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2056 | int ret; |
2057 | ||
03ac0642 | 2058 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2059 | if (!obj) |
2060 | return -ENOENT; | |
ab18282d | 2061 | |
d8cb5086 | 2062 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2063 | if (ret == 0) |
2064 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2065 | |
f3f6184c | 2066 | i915_gem_object_put_unlocked(obj); |
1d7cfea1 | 2067 | return ret; |
de151cf6 JB |
2068 | } |
2069 | ||
ff72145b DA |
2070 | /** |
2071 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2072 | * @dev: DRM device | |
2073 | * @data: GTT mapping ioctl data | |
2074 | * @file: GEM object info | |
2075 | * | |
2076 | * Simply returns the fake offset to userspace so it can mmap it. | |
2077 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2078 | * up so we can get faults in the handler above. | |
2079 | * | |
2080 | * The fault handler will take care of binding the object into the GTT | |
2081 | * (since it may have been evicted to make room for something), allocating | |
2082 | * a fence register, and mapping the appropriate aperture address into | |
2083 | * userspace. | |
2084 | */ | |
2085 | int | |
2086 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2087 | struct drm_file *file) | |
2088 | { | |
2089 | struct drm_i915_gem_mmap_gtt *args = data; | |
2090 | ||
da6b51d0 | 2091 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2092 | } |
2093 | ||
225067ee DV |
2094 | /* Immediately discard the backing storage */ |
2095 | static void | |
2096 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2097 | { |
4d6294bf | 2098 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2099 | |
4d6294bf CW |
2100 | if (obj->base.filp == NULL) |
2101 | return; | |
e5281ccd | 2102 | |
225067ee DV |
2103 | /* Our goal here is to return as much of the memory as |
2104 | * is possible back to the system as we are called from OOM. | |
2105 | * To do this we must instruct the shmfs to drop all of its | |
2106 | * backing pages, *now*. | |
2107 | */ | |
5537252b | 2108 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2109 | obj->madv = __I915_MADV_PURGED; |
2110 | } | |
e5281ccd | 2111 | |
5537252b CW |
2112 | /* Try to discard unwanted pages */ |
2113 | static void | |
2114 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2115 | { |
5537252b CW |
2116 | struct address_space *mapping; |
2117 | ||
2118 | switch (obj->madv) { | |
2119 | case I915_MADV_DONTNEED: | |
2120 | i915_gem_object_truncate(obj); | |
2121 | case __I915_MADV_PURGED: | |
2122 | return; | |
2123 | } | |
2124 | ||
2125 | if (obj->base.filp == NULL) | |
2126 | return; | |
2127 | ||
93c76a3d | 2128 | mapping = obj->base.filp->f_mapping, |
5537252b | 2129 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2130 | } |
2131 | ||
5cdf5881 | 2132 | static void |
05394f39 | 2133 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2134 | { |
85d1225e DG |
2135 | struct sgt_iter sgt_iter; |
2136 | struct page *page; | |
90797e6d | 2137 | int ret; |
1286ff73 | 2138 | |
05394f39 | 2139 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2140 | |
6c085a72 | 2141 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2142 | if (WARN_ON(ret)) { |
6c085a72 CW |
2143 | /* In the event of a disaster, abandon all caches and |
2144 | * hope for the best. | |
2145 | */ | |
2c22569b | 2146 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2147 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2148 | } | |
2149 | ||
e2273302 ID |
2150 | i915_gem_gtt_finish_object(obj); |
2151 | ||
6dacfd2f | 2152 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2153 | i915_gem_object_save_bit_17_swizzle(obj); |
2154 | ||
05394f39 CW |
2155 | if (obj->madv == I915_MADV_DONTNEED) |
2156 | obj->dirty = 0; | |
3ef94daa | 2157 | |
85d1225e | 2158 | for_each_sgt_page(page, sgt_iter, obj->pages) { |
05394f39 | 2159 | if (obj->dirty) |
9da3da66 | 2160 | set_page_dirty(page); |
3ef94daa | 2161 | |
05394f39 | 2162 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2163 | mark_page_accessed(page); |
3ef94daa | 2164 | |
09cbfeaf | 2165 | put_page(page); |
3ef94daa | 2166 | } |
05394f39 | 2167 | obj->dirty = 0; |
673a394b | 2168 | |
9da3da66 CW |
2169 | sg_free_table(obj->pages); |
2170 | kfree(obj->pages); | |
37e680a1 | 2171 | } |
6c085a72 | 2172 | |
dd624afd | 2173 | int |
37e680a1 CW |
2174 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2175 | { | |
2176 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2177 | ||
2f745ad3 | 2178 | if (obj->pages == NULL) |
37e680a1 CW |
2179 | return 0; |
2180 | ||
a5570178 CW |
2181 | if (obj->pages_pin_count) |
2182 | return -EBUSY; | |
2183 | ||
15717de2 | 2184 | GEM_BUG_ON(obj->bind_count); |
3e123027 | 2185 | |
a2165e31 CW |
2186 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2187 | * array, hence protect them from being reaped by removing them from gtt | |
2188 | * lists early. */ | |
35c20a60 | 2189 | list_del(&obj->global_list); |
a2165e31 | 2190 | |
0a798eb9 | 2191 | if (obj->mapping) { |
4b30cb23 CW |
2192 | void *ptr; |
2193 | ||
2194 | ptr = ptr_mask_bits(obj->mapping); | |
2195 | if (is_vmalloc_addr(ptr)) | |
2196 | vunmap(ptr); | |
fb8621d3 | 2197 | else |
4b30cb23 CW |
2198 | kunmap(kmap_to_page(ptr)); |
2199 | ||
0a798eb9 CW |
2200 | obj->mapping = NULL; |
2201 | } | |
2202 | ||
37e680a1 | 2203 | ops->put_pages(obj); |
05394f39 | 2204 | obj->pages = NULL; |
37e680a1 | 2205 | |
5537252b | 2206 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2207 | |
2208 | return 0; | |
2209 | } | |
2210 | ||
37e680a1 | 2211 | static int |
6c085a72 | 2212 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2213 | { |
fac5e23e | 2214 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2215 | int page_count, i; |
2216 | struct address_space *mapping; | |
9da3da66 CW |
2217 | struct sg_table *st; |
2218 | struct scatterlist *sg; | |
85d1225e | 2219 | struct sgt_iter sgt_iter; |
e5281ccd | 2220 | struct page *page; |
90797e6d | 2221 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2222 | int ret; |
6c085a72 | 2223 | gfp_t gfp; |
e5281ccd | 2224 | |
6c085a72 CW |
2225 | /* Assert that the object is not currently in any GPU domain. As it |
2226 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2227 | * a GPU cache | |
2228 | */ | |
2229 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2230 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2231 | ||
9da3da66 CW |
2232 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2233 | if (st == NULL) | |
2234 | return -ENOMEM; | |
2235 | ||
05394f39 | 2236 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2237 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2238 | kfree(st); |
e5281ccd | 2239 | return -ENOMEM; |
9da3da66 | 2240 | } |
e5281ccd | 2241 | |
9da3da66 CW |
2242 | /* Get the list of pages out of our struct file. They'll be pinned |
2243 | * at this point until we release them. | |
2244 | * | |
2245 | * Fail silently without starting the shrinker | |
2246 | */ | |
93c76a3d | 2247 | mapping = obj->base.filp->f_mapping; |
c62d2555 | 2248 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2249 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2250 | sg = st->sgl; |
2251 | st->nents = 0; | |
2252 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2253 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2254 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2255 | i915_gem_shrink(dev_priv, |
2256 | page_count, | |
2257 | I915_SHRINK_BOUND | | |
2258 | I915_SHRINK_UNBOUND | | |
2259 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2260 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2261 | } | |
2262 | if (IS_ERR(page)) { | |
2263 | /* We've tried hard to allocate the memory by reaping | |
2264 | * our own buffer, now let the real VM do its job and | |
2265 | * go down in flames if truly OOM. | |
2266 | */ | |
6c085a72 | 2267 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2268 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2269 | if (IS_ERR(page)) { |
2270 | ret = PTR_ERR(page); | |
6c085a72 | 2271 | goto err_pages; |
e2273302 | 2272 | } |
6c085a72 | 2273 | } |
426729dc KRW |
2274 | #ifdef CONFIG_SWIOTLB |
2275 | if (swiotlb_nr_tbl()) { | |
2276 | st->nents++; | |
2277 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2278 | sg = sg_next(sg); | |
2279 | continue; | |
2280 | } | |
2281 | #endif | |
90797e6d ID |
2282 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2283 | if (i) | |
2284 | sg = sg_next(sg); | |
2285 | st->nents++; | |
2286 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2287 | } else { | |
2288 | sg->length += PAGE_SIZE; | |
2289 | } | |
2290 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2291 | |
2292 | /* Check that the i965g/gm workaround works. */ | |
2293 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2294 | } |
426729dc KRW |
2295 | #ifdef CONFIG_SWIOTLB |
2296 | if (!swiotlb_nr_tbl()) | |
2297 | #endif | |
2298 | sg_mark_end(sg); | |
74ce6b6c CW |
2299 | obj->pages = st; |
2300 | ||
e2273302 ID |
2301 | ret = i915_gem_gtt_prepare_object(obj); |
2302 | if (ret) | |
2303 | goto err_pages; | |
2304 | ||
6dacfd2f | 2305 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2306 | i915_gem_object_do_bit_17_swizzle(obj); |
2307 | ||
3e510a8e | 2308 | if (i915_gem_object_is_tiled(obj) && |
656bfa3a DV |
2309 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
2310 | i915_gem_object_pin_pages(obj); | |
2311 | ||
e5281ccd CW |
2312 | return 0; |
2313 | ||
2314 | err_pages: | |
90797e6d | 2315 | sg_mark_end(sg); |
85d1225e DG |
2316 | for_each_sgt_page(page, sgt_iter, st) |
2317 | put_page(page); | |
9da3da66 CW |
2318 | sg_free_table(st); |
2319 | kfree(st); | |
0820baf3 CW |
2320 | |
2321 | /* shmemfs first checks if there is enough memory to allocate the page | |
2322 | * and reports ENOSPC should there be insufficient, along with the usual | |
2323 | * ENOMEM for a genuine allocation failure. | |
2324 | * | |
2325 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2326 | * space and so want to translate the error from shmemfs back to our | |
2327 | * usual understanding of ENOMEM. | |
2328 | */ | |
e2273302 ID |
2329 | if (ret == -ENOSPC) |
2330 | ret = -ENOMEM; | |
2331 | ||
2332 | return ret; | |
673a394b EA |
2333 | } |
2334 | ||
37e680a1 CW |
2335 | /* Ensure that the associated pages are gathered from the backing storage |
2336 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2337 | * multiple times before they are released by a single call to | |
2338 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2339 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2340 | * or as the object is itself released. | |
2341 | */ | |
2342 | int | |
2343 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2344 | { | |
fac5e23e | 2345 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
37e680a1 CW |
2346 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
2347 | int ret; | |
2348 | ||
2f745ad3 | 2349 | if (obj->pages) |
37e680a1 CW |
2350 | return 0; |
2351 | ||
43e28f09 | 2352 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2353 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2354 | return -EFAULT; |
43e28f09 CW |
2355 | } |
2356 | ||
a5570178 CW |
2357 | BUG_ON(obj->pages_pin_count); |
2358 | ||
37e680a1 CW |
2359 | ret = ops->get_pages(obj); |
2360 | if (ret) | |
2361 | return ret; | |
2362 | ||
35c20a60 | 2363 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2364 | |
2365 | obj->get_page.sg = obj->pages->sgl; | |
2366 | obj->get_page.last = 0; | |
2367 | ||
37e680a1 | 2368 | return 0; |
673a394b EA |
2369 | } |
2370 | ||
dd6034c6 | 2371 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2372 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2373 | enum i915_map_type type) | |
dd6034c6 DG |
2374 | { |
2375 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
2376 | struct sg_table *sgt = obj->pages; | |
85d1225e DG |
2377 | struct sgt_iter sgt_iter; |
2378 | struct page *page; | |
b338fa47 DG |
2379 | struct page *stack_pages[32]; |
2380 | struct page **pages = stack_pages; | |
dd6034c6 | 2381 | unsigned long i = 0; |
d31d7cb1 | 2382 | pgprot_t pgprot; |
dd6034c6 DG |
2383 | void *addr; |
2384 | ||
2385 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2386 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2387 | return kmap(sg_page(sgt->sgl)); |
2388 | ||
b338fa47 DG |
2389 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2390 | /* Too big for stack -- allocate temporary array instead */ | |
2391 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2392 | if (!pages) | |
2393 | return NULL; | |
2394 | } | |
dd6034c6 | 2395 | |
85d1225e DG |
2396 | for_each_sgt_page(page, sgt_iter, sgt) |
2397 | pages[i++] = page; | |
dd6034c6 DG |
2398 | |
2399 | /* Check that we have the expected number of pages */ | |
2400 | GEM_BUG_ON(i != n_pages); | |
2401 | ||
d31d7cb1 CW |
2402 | switch (type) { |
2403 | case I915_MAP_WB: | |
2404 | pgprot = PAGE_KERNEL; | |
2405 | break; | |
2406 | case I915_MAP_WC: | |
2407 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2408 | break; | |
2409 | } | |
2410 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2411 | |
b338fa47 DG |
2412 | if (pages != stack_pages) |
2413 | drm_free_large(pages); | |
dd6034c6 DG |
2414 | |
2415 | return addr; | |
2416 | } | |
2417 | ||
2418 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2419 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2420 | enum i915_map_type type) | |
0a798eb9 | 2421 | { |
d31d7cb1 CW |
2422 | enum i915_map_type has_type; |
2423 | bool pinned; | |
2424 | void *ptr; | |
0a798eb9 CW |
2425 | int ret; |
2426 | ||
2427 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
d31d7cb1 | 2428 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 CW |
2429 | |
2430 | ret = i915_gem_object_get_pages(obj); | |
2431 | if (ret) | |
2432 | return ERR_PTR(ret); | |
2433 | ||
2434 | i915_gem_object_pin_pages(obj); | |
d31d7cb1 | 2435 | pinned = obj->pages_pin_count > 1; |
0a798eb9 | 2436 | |
d31d7cb1 CW |
2437 | ptr = ptr_unpack_bits(obj->mapping, has_type); |
2438 | if (ptr && has_type != type) { | |
2439 | if (pinned) { | |
2440 | ret = -EBUSY; | |
2441 | goto err; | |
0a798eb9 | 2442 | } |
d31d7cb1 CW |
2443 | |
2444 | if (is_vmalloc_addr(ptr)) | |
2445 | vunmap(ptr); | |
2446 | else | |
2447 | kunmap(kmap_to_page(ptr)); | |
2448 | ||
2449 | ptr = obj->mapping = NULL; | |
0a798eb9 CW |
2450 | } |
2451 | ||
d31d7cb1 CW |
2452 | if (!ptr) { |
2453 | ptr = i915_gem_object_map(obj, type); | |
2454 | if (!ptr) { | |
2455 | ret = -ENOMEM; | |
2456 | goto err; | |
2457 | } | |
2458 | ||
2459 | obj->mapping = ptr_pack_bits(ptr, type); | |
2460 | } | |
2461 | ||
2462 | return ptr; | |
2463 | ||
2464 | err: | |
2465 | i915_gem_object_unpin_pages(obj); | |
2466 | return ERR_PTR(ret); | |
0a798eb9 CW |
2467 | } |
2468 | ||
b4716185 | 2469 | static void |
fa545cbf CW |
2470 | i915_gem_object_retire__write(struct i915_gem_active *active, |
2471 | struct drm_i915_gem_request *request) | |
e2d05a8b | 2472 | { |
fa545cbf CW |
2473 | struct drm_i915_gem_object *obj = |
2474 | container_of(active, struct drm_i915_gem_object, last_write); | |
b4716185 | 2475 | |
de152b62 | 2476 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2477 | } |
2478 | ||
caea7476 | 2479 | static void |
fa545cbf CW |
2480 | i915_gem_object_retire__read(struct i915_gem_active *active, |
2481 | struct drm_i915_gem_request *request) | |
ce44b0ea | 2482 | { |
fa545cbf CW |
2483 | int idx = request->engine->id; |
2484 | struct drm_i915_gem_object *obj = | |
2485 | container_of(active, struct drm_i915_gem_object, last_read[idx]); | |
ce44b0ea | 2486 | |
573adb39 | 2487 | GEM_BUG_ON(!i915_gem_object_has_active_engine(obj, idx)); |
b4716185 | 2488 | |
573adb39 CW |
2489 | i915_gem_object_clear_active(obj, idx); |
2490 | if (i915_gem_object_is_active(obj)) | |
b4716185 | 2491 | return; |
caea7476 | 2492 | |
6c246959 CW |
2493 | /* Bump our place on the bound list to keep it roughly in LRU order |
2494 | * so that we don't steal from recently used but inactive objects | |
2495 | * (unless we are forced to ofc!) | |
2496 | */ | |
b0decaf7 CW |
2497 | if (obj->bind_count) |
2498 | list_move_tail(&obj->global_list, | |
2499 | &request->i915->mm.bound_list); | |
caea7476 | 2500 | |
f8c417cd | 2501 | i915_gem_object_put(obj); |
c8725f3d CW |
2502 | } |
2503 | ||
7b4d3a16 | 2504 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2505 | { |
44e2c070 | 2506 | unsigned long elapsed; |
be62acb4 | 2507 | |
44e2c070 | 2508 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2509 | return true; |
2510 | ||
7b4d3a16 | 2511 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2512 | if (ctx->hang_stats.ban_period_seconds && |
2513 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2514 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2515 | return true; | |
be62acb4 MK |
2516 | } |
2517 | ||
2518 | return false; | |
2519 | } | |
2520 | ||
7b4d3a16 | 2521 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2522 | const bool guilty) |
aa60c664 | 2523 | { |
7b4d3a16 | 2524 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2525 | |
2526 | if (guilty) { | |
7b4d3a16 | 2527 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2528 | hs->batch_active++; |
2529 | hs->guilty_ts = get_seconds(); | |
2530 | } else { | |
2531 | hs->batch_pending++; | |
aa60c664 MK |
2532 | } |
2533 | } | |
2534 | ||
8d9fc7fd | 2535 | struct drm_i915_gem_request * |
0bc40be8 | 2536 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2537 | { |
4db080f9 CW |
2538 | struct drm_i915_gem_request *request; |
2539 | ||
f69a02c9 CW |
2540 | /* We are called by the error capture and reset at a random |
2541 | * point in time. In particular, note that neither is crucially | |
2542 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2543 | * assume that no more writes can happen (we waited long enough for | |
2544 | * all writes that were in transaction to be flushed) - adding an | |
2545 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2546 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2547 | */ | |
efdf7c06 | 2548 | list_for_each_entry(request, &engine->request_list, link) { |
f69a02c9 | 2549 | if (i915_gem_request_completed(request)) |
4db080f9 | 2550 | continue; |
aa60c664 | 2551 | |
5590af3e CW |
2552 | if (!i915_sw_fence_done(&request->submit)) |
2553 | break; | |
2554 | ||
b6b0fac0 | 2555 | return request; |
4db080f9 | 2556 | } |
b6b0fac0 MK |
2557 | |
2558 | return NULL; | |
2559 | } | |
2560 | ||
821ed7df CW |
2561 | static void reset_request(struct drm_i915_gem_request *request) |
2562 | { | |
2563 | void *vaddr = request->ring->vaddr; | |
2564 | u32 head; | |
2565 | ||
2566 | /* As this request likely depends on state from the lost | |
2567 | * context, clear out all the user operations leaving the | |
2568 | * breadcrumb at the end (so we get the fence notifications). | |
2569 | */ | |
2570 | head = request->head; | |
2571 | if (request->postfix < head) { | |
2572 | memset(vaddr + head, 0, request->ring->size - head); | |
2573 | head = 0; | |
2574 | } | |
2575 | memset(vaddr + head, 0, request->postfix - head); | |
2576 | } | |
2577 | ||
2578 | static void i915_gem_reset_engine(struct intel_engine_cs *engine) | |
b6b0fac0 MK |
2579 | { |
2580 | struct drm_i915_gem_request *request; | |
821ed7df | 2581 | struct i915_gem_context *incomplete_ctx; |
b6b0fac0 MK |
2582 | bool ring_hung; |
2583 | ||
821ed7df CW |
2584 | /* Ensure irq handler finishes, and not run again. */ |
2585 | tasklet_kill(&engine->irq_tasklet); | |
2586 | if (engine->irq_seqno_barrier) | |
2587 | engine->irq_seqno_barrier(engine); | |
2588 | ||
0bc40be8 | 2589 | request = i915_gem_find_active_request(engine); |
821ed7df | 2590 | if (!request) |
b6b0fac0 MK |
2591 | return; |
2592 | ||
0bc40be8 | 2593 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
7b4d3a16 | 2594 | i915_set_reset_status(request->ctx, ring_hung); |
821ed7df CW |
2595 | if (!ring_hung) |
2596 | return; | |
2597 | ||
2598 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
2599 | engine->name, request->fence.seqno); | |
2600 | ||
2601 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2602 | engine->reset_hw(engine, request); | |
2603 | ||
2604 | /* Users of the default context do not rely on logical state | |
2605 | * preserved between batches. They have to emit full state on | |
2606 | * every batch and so it is safe to execute queued requests following | |
2607 | * the hang. | |
2608 | * | |
2609 | * Other contexts preserve state, now corrupt. We want to skip all | |
2610 | * queued requests that reference the corrupt context. | |
2611 | */ | |
2612 | incomplete_ctx = request->ctx; | |
2613 | if (i915_gem_context_is_default(incomplete_ctx)) | |
2614 | return; | |
2615 | ||
efdf7c06 | 2616 | list_for_each_entry_continue(request, &engine->request_list, link) |
821ed7df CW |
2617 | if (request->ctx == incomplete_ctx) |
2618 | reset_request(request); | |
4db080f9 | 2619 | } |
aa60c664 | 2620 | |
821ed7df | 2621 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2622 | { |
821ed7df | 2623 | struct intel_engine_cs *engine; |
608c1a52 | 2624 | |
821ed7df CW |
2625 | i915_gem_retire_requests(dev_priv); |
2626 | ||
2627 | for_each_engine(engine, dev_priv) | |
2628 | i915_gem_reset_engine(engine); | |
2629 | ||
2630 | i915_gem_restore_fences(&dev_priv->drm); | |
2631 | } | |
2632 | ||
2633 | static void nop_submit_request(struct drm_i915_gem_request *request) | |
2634 | { | |
2635 | } | |
2636 | ||
2637 | static void i915_gem_cleanup_engine(struct intel_engine_cs *engine) | |
2638 | { | |
2639 | engine->submit_request = nop_submit_request; | |
70c2a24d | 2640 | |
c4b0930b CW |
2641 | /* Mark all pending requests as complete so that any concurrent |
2642 | * (lockless) lookup doesn't try and wait upon the request as we | |
2643 | * reset it. | |
2644 | */ | |
87b723a1 | 2645 | intel_engine_init_seqno(engine, engine->last_submitted_seqno); |
c4b0930b | 2646 | |
dcb4c12a OM |
2647 | /* |
2648 | * Clear the execlists queue up before freeing the requests, as those | |
2649 | * are the ones that keep the context and ringbuffer backing objects | |
2650 | * pinned in place. | |
2651 | */ | |
dcb4c12a | 2652 | |
7de1691a | 2653 | if (i915.enable_execlists) { |
70c2a24d CW |
2654 | spin_lock(&engine->execlist_lock); |
2655 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2656 | i915_gem_request_put(engine->execlist_port[0].request); | |
2657 | i915_gem_request_put(engine->execlist_port[1].request); | |
2658 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
2659 | spin_unlock(&engine->execlist_lock); | |
dcb4c12a OM |
2660 | } |
2661 | ||
b913b33c | 2662 | engine->i915->gt.active_engines &= ~intel_engine_flag(engine); |
673a394b EA |
2663 | } |
2664 | ||
821ed7df | 2665 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) |
673a394b | 2666 | { |
e2f80391 | 2667 | struct intel_engine_cs *engine; |
673a394b | 2668 | |
821ed7df CW |
2669 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2670 | set_bit(I915_WEDGED, &dev_priv->gpu_error.flags); | |
4db080f9 | 2671 | |
821ed7df | 2672 | i915_gem_context_lost(dev_priv); |
b4ac5afc | 2673 | for_each_engine(engine, dev_priv) |
821ed7df | 2674 | i915_gem_cleanup_engine(engine); |
b913b33c | 2675 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); |
dfaae392 | 2676 | |
821ed7df | 2677 | i915_gem_retire_requests(dev_priv); |
673a394b EA |
2678 | } |
2679 | ||
75ef9da2 | 2680 | static void |
673a394b EA |
2681 | i915_gem_retire_work_handler(struct work_struct *work) |
2682 | { | |
b29c19b6 | 2683 | struct drm_i915_private *dev_priv = |
67d97da3 | 2684 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2685 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2686 | |
891b48cf | 2687 | /* Come back later if the device is busy... */ |
b29c19b6 | 2688 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2689 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2690 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2691 | } |
67d97da3 CW |
2692 | |
2693 | /* Keep the retire handler running until we are finally idle. | |
2694 | * We do not need to do this test under locking as in the worst-case | |
2695 | * we queue the retire worker once too often. | |
2696 | */ | |
c9615613 CW |
2697 | if (READ_ONCE(dev_priv->gt.awake)) { |
2698 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2699 | queue_delayed_work(dev_priv->wq, |
2700 | &dev_priv->gt.retire_work, | |
bcb45086 | 2701 | round_jiffies_up_relative(HZ)); |
c9615613 | 2702 | } |
b29c19b6 | 2703 | } |
0a58705b | 2704 | |
b29c19b6 CW |
2705 | static void |
2706 | i915_gem_idle_work_handler(struct work_struct *work) | |
2707 | { | |
2708 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2709 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2710 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2711 | struct intel_engine_cs *engine; |
67d97da3 CW |
2712 | bool rearm_hangcheck; |
2713 | ||
2714 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2715 | return; | |
2716 | ||
2717 | if (READ_ONCE(dev_priv->gt.active_engines)) | |
2718 | return; | |
2719 | ||
2720 | rearm_hangcheck = | |
2721 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2722 | ||
2723 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2724 | /* Currently busy, come back later */ | |
2725 | mod_delayed_work(dev_priv->wq, | |
2726 | &dev_priv->gt.idle_work, | |
2727 | msecs_to_jiffies(50)); | |
2728 | goto out_rearm; | |
2729 | } | |
2730 | ||
2731 | if (dev_priv->gt.active_engines) | |
2732 | goto out_unlock; | |
b29c19b6 | 2733 | |
b4ac5afc | 2734 | for_each_engine(engine, dev_priv) |
67d97da3 | 2735 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2736 | |
67d97da3 CW |
2737 | GEM_BUG_ON(!dev_priv->gt.awake); |
2738 | dev_priv->gt.awake = false; | |
2739 | rearm_hangcheck = false; | |
30ecad77 | 2740 | |
67d97da3 CW |
2741 | if (INTEL_GEN(dev_priv) >= 6) |
2742 | gen6_rps_idle(dev_priv); | |
2743 | intel_runtime_pm_put(dev_priv); | |
2744 | out_unlock: | |
2745 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2746 | |
67d97da3 CW |
2747 | out_rearm: |
2748 | if (rearm_hangcheck) { | |
2749 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2750 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2751 | } |
673a394b EA |
2752 | } |
2753 | ||
b1f788c6 CW |
2754 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2755 | { | |
2756 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2757 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2758 | struct i915_vma *vma, *vn; | |
2759 | ||
2760 | mutex_lock(&obj->base.dev->struct_mutex); | |
2761 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2762 | if (vma->vm->file == fpriv) | |
2763 | i915_vma_close(vma); | |
2764 | mutex_unlock(&obj->base.dev->struct_mutex); | |
2765 | } | |
2766 | ||
23ba4fd0 BW |
2767 | /** |
2768 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2769 | * @dev: drm device pointer |
2770 | * @data: ioctl data blob | |
2771 | * @file: drm file pointer | |
23ba4fd0 BW |
2772 | * |
2773 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2774 | * the timeout parameter. | |
2775 | * -ETIME: object is still busy after timeout | |
2776 | * -ERESTARTSYS: signal interrupted the wait | |
2777 | * -ENONENT: object doesn't exist | |
2778 | * Also possible, but rare: | |
2779 | * -EAGAIN: GPU wedged | |
2780 | * -ENOMEM: damn | |
2781 | * -ENODEV: Internal IRQ fail | |
2782 | * -E?: The add request failed | |
2783 | * | |
2784 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2785 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2786 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2787 | * without holding struct_mutex the object may become re-busied before this | |
2788 | * function completes. A similar but shorter * race condition exists in the busy | |
2789 | * ioctl | |
2790 | */ | |
2791 | int | |
2792 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2793 | { | |
2794 | struct drm_i915_gem_wait *args = data; | |
033d549b | 2795 | struct intel_rps_client *rps = to_rps_client(file); |
23ba4fd0 | 2796 | struct drm_i915_gem_object *obj; |
033d549b CW |
2797 | unsigned long active; |
2798 | int idx, ret = 0; | |
23ba4fd0 | 2799 | |
11b5d511 DV |
2800 | if (args->flags != 0) |
2801 | return -EINVAL; | |
2802 | ||
03ac0642 | 2803 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 2804 | if (!obj) |
23ba4fd0 | 2805 | return -ENOENT; |
23ba4fd0 | 2806 | |
033d549b CW |
2807 | active = __I915_BO_ACTIVE(obj); |
2808 | for_each_active(active, idx) { | |
2809 | s64 *timeout = args->timeout_ns >= 0 ? &args->timeout_ns : NULL; | |
ea746f36 CW |
2810 | ret = i915_gem_active_wait_unlocked(&obj->last_read[idx], |
2811 | I915_WAIT_INTERRUPTIBLE, | |
033d549b CW |
2812 | timeout, rps); |
2813 | if (ret) | |
2814 | break; | |
b4716185 CW |
2815 | } |
2816 | ||
033d549b | 2817 | i915_gem_object_put_unlocked(obj); |
ff865885 | 2818 | return ret; |
23ba4fd0 BW |
2819 | } |
2820 | ||
8ef8561f CW |
2821 | static void __i915_vma_iounmap(struct i915_vma *vma) |
2822 | { | |
20dfbde4 | 2823 | GEM_BUG_ON(i915_vma_is_pinned(vma)); |
8ef8561f CW |
2824 | |
2825 | if (vma->iomap == NULL) | |
2826 | return; | |
2827 | ||
2828 | io_mapping_unmap(vma->iomap); | |
2829 | vma->iomap = NULL; | |
2830 | } | |
2831 | ||
df0e9a28 | 2832 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2833 | { |
07fe0b12 | 2834 | struct drm_i915_gem_object *obj = vma->obj; |
b0decaf7 | 2835 | unsigned long active; |
43e28f09 | 2836 | int ret; |
673a394b | 2837 | |
b0decaf7 CW |
2838 | /* First wait upon any activity as retiring the request may |
2839 | * have side-effects such as unpinning or even unbinding this vma. | |
2840 | */ | |
2841 | active = i915_vma_get_active(vma); | |
df0e9a28 | 2842 | if (active) { |
b0decaf7 CW |
2843 | int idx; |
2844 | ||
b1f788c6 CW |
2845 | /* When a closed VMA is retired, it is unbound - eek. |
2846 | * In order to prevent it from being recursively closed, | |
2847 | * take a pin on the vma so that the second unbind is | |
2848 | * aborted. | |
2849 | */ | |
20dfbde4 | 2850 | __i915_vma_pin(vma); |
b1f788c6 | 2851 | |
b0decaf7 CW |
2852 | for_each_active(active, idx) { |
2853 | ret = i915_gem_active_retire(&vma->last_read[idx], | |
2854 | &vma->vm->dev->struct_mutex); | |
2855 | if (ret) | |
b1f788c6 | 2856 | break; |
b0decaf7 CW |
2857 | } |
2858 | ||
20dfbde4 | 2859 | __i915_vma_unpin(vma); |
b1f788c6 CW |
2860 | if (ret) |
2861 | return ret; | |
2862 | ||
b0decaf7 CW |
2863 | GEM_BUG_ON(i915_vma_is_active(vma)); |
2864 | } | |
2865 | ||
20dfbde4 | 2866 | if (i915_vma_is_pinned(vma)) |
b0decaf7 CW |
2867 | return -EBUSY; |
2868 | ||
b1f788c6 CW |
2869 | if (!drm_mm_node_allocated(&vma->node)) |
2870 | goto destroy; | |
433544bd | 2871 | |
15717de2 CW |
2872 | GEM_BUG_ON(obj->bind_count == 0); |
2873 | GEM_BUG_ON(!obj->pages); | |
c4670ad0 | 2874 | |
05a20d09 | 2875 | if (i915_vma_is_map_and_fenceable(vma)) { |
8b1bc9b4 | 2876 | /* release the fence reg _after_ flushing */ |
49ef5294 | 2877 | ret = i915_vma_put_fence(vma); |
8b1bc9b4 DV |
2878 | if (ret) |
2879 | return ret; | |
8ef8561f | 2880 | |
cd3127d6 CW |
2881 | /* Force a pagefault for domain tracking on next user access */ |
2882 | i915_gem_release_mmap(obj); | |
2883 | ||
8ef8561f | 2884 | __i915_vma_iounmap(vma); |
05a20d09 | 2885 | vma->flags &= ~I915_VMA_CAN_FENCE; |
8b1bc9b4 | 2886 | } |
96b47b65 | 2887 | |
50e046b6 CW |
2888 | if (likely(!vma->vm->closed)) { |
2889 | trace_i915_vma_unbind(vma); | |
2890 | vma->vm->unbind_vma(vma); | |
2891 | } | |
3272db53 | 2892 | vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); |
6f65e29a | 2893 | |
50e046b6 CW |
2894 | drm_mm_remove_node(&vma->node); |
2895 | list_move_tail(&vma->vm_link, &vma->vm->unbound_list); | |
2896 | ||
05a20d09 CW |
2897 | if (vma->pages != obj->pages) { |
2898 | GEM_BUG_ON(!vma->pages); | |
2899 | sg_free_table(vma->pages); | |
2900 | kfree(vma->pages); | |
fe14d5f4 | 2901 | } |
247177dd | 2902 | vma->pages = NULL; |
673a394b | 2903 | |
2f633156 | 2904 | /* Since the unbound list is global, only move to that list if |
b93dab6e | 2905 | * no more VMAs exist. */ |
15717de2 CW |
2906 | if (--obj->bind_count == 0) |
2907 | list_move_tail(&obj->global_list, | |
2908 | &to_i915(obj->base.dev)->mm.unbound_list); | |
673a394b | 2909 | |
70903c3b CW |
2910 | /* And finally now the object is completely decoupled from this vma, |
2911 | * we can drop its hold on the backing storage and allow it to be | |
2912 | * reaped by the shrinker. | |
2913 | */ | |
2914 | i915_gem_object_unpin_pages(obj); | |
2915 | ||
b1f788c6 | 2916 | destroy: |
3272db53 | 2917 | if (unlikely(i915_vma_is_closed(vma))) |
b1f788c6 CW |
2918 | i915_vma_destroy(vma); |
2919 | ||
88241785 | 2920 | return 0; |
54cf91dc CW |
2921 | } |
2922 | ||
dcff85c8 | 2923 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
ea746f36 | 2924 | unsigned int flags) |
4df2faf4 | 2925 | { |
e2f80391 | 2926 | struct intel_engine_cs *engine; |
b4ac5afc | 2927 | int ret; |
4df2faf4 | 2928 | |
b4ac5afc | 2929 | for_each_engine(engine, dev_priv) { |
62e63007 CW |
2930 | if (engine->last_context == NULL) |
2931 | continue; | |
2932 | ||
ea746f36 | 2933 | ret = intel_engine_idle(engine, flags); |
1ec14ad3 CW |
2934 | if (ret) |
2935 | return ret; | |
2936 | } | |
4df2faf4 | 2937 | |
8a1a49f9 | 2938 | return 0; |
4df2faf4 DV |
2939 | } |
2940 | ||
4144f9b5 | 2941 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
2942 | unsigned long cache_level) |
2943 | { | |
4144f9b5 | 2944 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
2945 | struct drm_mm_node *other; |
2946 | ||
4144f9b5 CW |
2947 | /* |
2948 | * On some machines we have to be careful when putting differing types | |
2949 | * of snoopable memory together to avoid the prefetcher crossing memory | |
2950 | * domains and dying. During vm initialisation, we decide whether or not | |
2951 | * these constraints apply and set the drm_mm.color_adjust | |
2952 | * appropriately. | |
42d6ab48 | 2953 | */ |
4144f9b5 | 2954 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
2955 | return true; |
2956 | ||
c6cfb325 | 2957 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
2958 | return true; |
2959 | ||
2960 | if (list_empty(>t_space->node_list)) | |
2961 | return true; | |
2962 | ||
2963 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2964 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2965 | return false; | |
2966 | ||
2967 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2968 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2969 | return false; | |
2970 | ||
2971 | return true; | |
2972 | } | |
2973 | ||
673a394b | 2974 | /** |
59bfa124 CW |
2975 | * i915_vma_insert - finds a slot for the vma in its address space |
2976 | * @vma: the vma | |
91b2db6f | 2977 | * @size: requested size in bytes (can be larger than the VMA) |
59bfa124 | 2978 | * @alignment: required alignment |
14bb2c11 | 2979 | * @flags: mask of PIN_* flags to use |
59bfa124 CW |
2980 | * |
2981 | * First we try to allocate some free space that meets the requirements for | |
2982 | * the VMA. Failiing that, if the flags permit, it will evict an old VMA, | |
2983 | * preferrably the oldest idle entry to make room for the new VMA. | |
2984 | * | |
2985 | * Returns: | |
2986 | * 0 on success, negative error code otherwise. | |
673a394b | 2987 | */ |
59bfa124 CW |
2988 | static int |
2989 | i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) | |
673a394b | 2990 | { |
59bfa124 CW |
2991 | struct drm_i915_private *dev_priv = to_i915(vma->vm->dev); |
2992 | struct drm_i915_gem_object *obj = vma->obj; | |
de180033 | 2993 | u64 start, end; |
07f73f69 | 2994 | int ret; |
673a394b | 2995 | |
3272db53 | 2996 | GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); |
59bfa124 | 2997 | GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); |
de180033 CW |
2998 | |
2999 | size = max(size, vma->size); | |
3000 | if (flags & PIN_MAPPABLE) | |
3e510a8e CW |
3001 | size = i915_gem_get_ggtt_size(dev_priv, size, |
3002 | i915_gem_object_get_tiling(obj)); | |
de180033 | 3003 | |
d8923dcf CW |
3004 | alignment = max(max(alignment, vma->display_alignment), |
3005 | i915_gem_get_ggtt_alignment(dev_priv, size, | |
3006 | i915_gem_object_get_tiling(obj), | |
3007 | flags & PIN_MAPPABLE)); | |
a00b10c3 | 3008 | |
101b506a | 3009 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
de180033 CW |
3010 | |
3011 | end = vma->vm->total; | |
101b506a | 3012 | if (flags & PIN_MAPPABLE) |
91b2db6f | 3013 | end = min_t(u64, end, dev_priv->ggtt.mappable_end); |
101b506a | 3014 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3015 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3016 | |
91e6711e JL |
3017 | /* If binding the object/GGTT view requires more space than the entire |
3018 | * aperture has, reject it early before evicting everything in a vain | |
3019 | * attempt to find space. | |
654fc607 | 3020 | */ |
91e6711e | 3021 | if (size > end) { |
de180033 | 3022 | DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n", |
91b2db6f | 3023 | size, obj->base.size, |
1ec9e26d | 3024 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3025 | end); |
59bfa124 | 3026 | return -E2BIG; |
654fc607 CW |
3027 | } |
3028 | ||
37e680a1 | 3029 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3030 | if (ret) |
59bfa124 | 3031 | return ret; |
6c085a72 | 3032 | |
fbdda6fb CW |
3033 | i915_gem_object_pin_pages(obj); |
3034 | ||
506a8e87 | 3035 | if (flags & PIN_OFFSET_FIXED) { |
59bfa124 | 3036 | u64 offset = flags & PIN_OFFSET_MASK; |
de180033 | 3037 | if (offset & (alignment - 1) || offset > end - size) { |
506a8e87 | 3038 | ret = -EINVAL; |
de180033 | 3039 | goto err_unpin; |
506a8e87 | 3040 | } |
de180033 | 3041 | |
506a8e87 CW |
3042 | vma->node.start = offset; |
3043 | vma->node.size = size; | |
3044 | vma->node.color = obj->cache_level; | |
de180033 | 3045 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
506a8e87 CW |
3046 | if (ret) { |
3047 | ret = i915_gem_evict_for_vma(vma); | |
3048 | if (ret == 0) | |
de180033 CW |
3049 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
3050 | if (ret) | |
3051 | goto err_unpin; | |
506a8e87 | 3052 | } |
101b506a | 3053 | } else { |
de180033 CW |
3054 | u32 search_flag, alloc_flag; |
3055 | ||
506a8e87 CW |
3056 | if (flags & PIN_HIGH) { |
3057 | search_flag = DRM_MM_SEARCH_BELOW; | |
3058 | alloc_flag = DRM_MM_CREATE_TOP; | |
3059 | } else { | |
3060 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3061 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3062 | } | |
101b506a | 3063 | |
954c4691 CW |
3064 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, |
3065 | * so we know that we always have a minimum alignment of 4096. | |
3066 | * The drm_mm range manager is optimised to return results | |
3067 | * with zero alignment, so where possible use the optimal | |
3068 | * path. | |
3069 | */ | |
3070 | if (alignment <= 4096) | |
3071 | alignment = 0; | |
3072 | ||
0a9ae0d7 | 3073 | search_free: |
de180033 CW |
3074 | ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm, |
3075 | &vma->node, | |
506a8e87 CW |
3076 | size, alignment, |
3077 | obj->cache_level, | |
3078 | start, end, | |
3079 | search_flag, | |
3080 | alloc_flag); | |
3081 | if (ret) { | |
de180033 | 3082 | ret = i915_gem_evict_something(vma->vm, size, alignment, |
506a8e87 CW |
3083 | obj->cache_level, |
3084 | start, end, | |
3085 | flags); | |
3086 | if (ret == 0) | |
3087 | goto search_free; | |
9731129c | 3088 | |
de180033 | 3089 | goto err_unpin; |
506a8e87 | 3090 | } |
673a394b | 3091 | } |
37508589 | 3092 | GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level)); |
673a394b | 3093 | |
35c20a60 | 3094 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
de180033 | 3095 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
15717de2 | 3096 | obj->bind_count++; |
bf1a1092 | 3097 | |
59bfa124 | 3098 | return 0; |
2f633156 | 3099 | |
bc6bc15b | 3100 | err_unpin: |
2f633156 | 3101 | i915_gem_object_unpin_pages(obj); |
59bfa124 | 3102 | return ret; |
673a394b EA |
3103 | } |
3104 | ||
000433b6 | 3105 | bool |
2c22569b CW |
3106 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3107 | bool force) | |
673a394b | 3108 | { |
673a394b EA |
3109 | /* If we don't have a page list set up, then we're not pinned |
3110 | * to GPU, and we can ignore the cache flush because it'll happen | |
3111 | * again at bind time. | |
3112 | */ | |
05394f39 | 3113 | if (obj->pages == NULL) |
000433b6 | 3114 | return false; |
673a394b | 3115 | |
769ce464 ID |
3116 | /* |
3117 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3118 | * marked as wc by the system, or the system is cache-coherent. | |
3119 | */ | |
6a2c4232 | 3120 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3121 | return false; |
769ce464 | 3122 | |
9c23f7fc CW |
3123 | /* If the GPU is snooping the contents of the CPU cache, |
3124 | * we do not need to manually clear the CPU cache lines. However, | |
3125 | * the caches are only snooped when the render cache is | |
3126 | * flushed/invalidated. As we always have to emit invalidations | |
3127 | * and flushes when moving into and out of the RENDER domain, correct | |
3128 | * snooping behaviour occurs naturally as the result of our domain | |
3129 | * tracking. | |
3130 | */ | |
0f71979a CW |
3131 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3132 | obj->cache_dirty = true; | |
000433b6 | 3133 | return false; |
0f71979a | 3134 | } |
9c23f7fc | 3135 | |
1c5d22f7 | 3136 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3137 | drm_clflush_sg(obj->pages); |
0f71979a | 3138 | obj->cache_dirty = false; |
000433b6 CW |
3139 | |
3140 | return true; | |
e47c68e9 EA |
3141 | } |
3142 | ||
3143 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3144 | static void | |
05394f39 | 3145 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3146 | { |
3b5724d7 | 3147 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
1c5d22f7 | 3148 | |
05394f39 | 3149 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3150 | return; |
3151 | ||
63256ec5 | 3152 | /* No actual flushing is required for the GTT write domain. Writes |
3b5724d7 | 3153 | * to it "immediately" go to main memory as far as we know, so there's |
e47c68e9 | 3154 | * no chipset flush. It also doesn't land in render cache. |
63256ec5 CW |
3155 | * |
3156 | * However, we do have to enforce the order so that all writes through | |
3157 | * the GTT land before any writes to the device, such as updates to | |
3158 | * the GATT itself. | |
3b5724d7 CW |
3159 | * |
3160 | * We also have to wait a bit for the writes to land from the GTT. | |
3161 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
3162 | * timing. This issue has only been observed when switching quickly | |
3163 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
3164 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
3165 | * system agents we cannot reproduce this behaviour). | |
e47c68e9 | 3166 | */ |
63256ec5 | 3167 | wmb(); |
3b5724d7 CW |
3168 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) |
3169 | POSTING_READ(RING_ACTHD(dev_priv->engine[RCS].mmio_base)); | |
63256ec5 | 3170 | |
d243ad82 | 3171 | intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); |
f99d7069 | 3172 | |
b0dc465f | 3173 | obj->base.write_domain = 0; |
1c5d22f7 | 3174 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3175 | obj->base.read_domains, |
b0dc465f | 3176 | I915_GEM_DOMAIN_GTT); |
e47c68e9 EA |
3177 | } |
3178 | ||
3179 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3180 | static void | |
e62b59e4 | 3181 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3182 | { |
05394f39 | 3183 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3184 | return; |
3185 | ||
e62b59e4 | 3186 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 3187 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 3188 | |
de152b62 | 3189 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3190 | |
b0dc465f | 3191 | obj->base.write_domain = 0; |
1c5d22f7 | 3192 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3193 | obj->base.read_domains, |
b0dc465f | 3194 | I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3195 | } |
3196 | ||
383d5823 CW |
3197 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
3198 | { | |
3199 | struct i915_vma *vma; | |
3200 | ||
3201 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
3202 | if (!i915_vma_is_ggtt(vma)) | |
3203 | continue; | |
3204 | ||
3205 | if (i915_vma_is_active(vma)) | |
3206 | continue; | |
3207 | ||
3208 | if (!drm_mm_node_allocated(&vma->node)) | |
3209 | continue; | |
3210 | ||
3211 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3212 | } | |
3213 | } | |
3214 | ||
2ef7eeaa EA |
3215 | /** |
3216 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3217 | * @obj: object to act on |
3218 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3219 | * |
3220 | * This function returns when the move is complete, including waiting on | |
3221 | * flushes to occur. | |
3222 | */ | |
79e53945 | 3223 | int |
2021746e | 3224 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3225 | { |
1c5d22f7 | 3226 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3227 | int ret; |
2ef7eeaa | 3228 | |
0201f1ec | 3229 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3230 | if (ret) |
3231 | return ret; | |
3232 | ||
c13d87ea CW |
3233 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3234 | return 0; | |
3235 | ||
43566ded CW |
3236 | /* Flush and acquire obj->pages so that we are coherent through |
3237 | * direct access in memory with previous cached writes through | |
3238 | * shmemfs and that our cache domain tracking remains valid. | |
3239 | * For example, if the obj->filp was moved to swap without us | |
3240 | * being notified and releasing the pages, we would mistakenly | |
3241 | * continue to assume that the obj remained out of the CPU cached | |
3242 | * domain. | |
3243 | */ | |
3244 | ret = i915_gem_object_get_pages(obj); | |
3245 | if (ret) | |
3246 | return ret; | |
3247 | ||
e62b59e4 | 3248 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3249 | |
d0a57789 CW |
3250 | /* Serialise direct access to this object with the barriers for |
3251 | * coherent writes from the GPU, by effectively invalidating the | |
3252 | * GTT domain upon first access. | |
3253 | */ | |
3254 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3255 | mb(); | |
3256 | ||
05394f39 CW |
3257 | old_write_domain = obj->base.write_domain; |
3258 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3259 | |
e47c68e9 EA |
3260 | /* It should now be out of any other write domains, and we can update |
3261 | * the domain values for our changes. | |
3262 | */ | |
05394f39 CW |
3263 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3264 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3265 | if (write) { |
05394f39 CW |
3266 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3267 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3268 | obj->dirty = 1; | |
2ef7eeaa EA |
3269 | } |
3270 | ||
1c5d22f7 CW |
3271 | trace_i915_gem_object_change_domain(obj, |
3272 | old_read_domains, | |
3273 | old_write_domain); | |
3274 | ||
8325a09d | 3275 | /* And bump the LRU for this access */ |
383d5823 | 3276 | i915_gem_object_bump_inactive_ggtt(obj); |
8325a09d | 3277 | |
e47c68e9 EA |
3278 | return 0; |
3279 | } | |
3280 | ||
ef55f92a CW |
3281 | /** |
3282 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3283 | * @obj: object to act on |
3284 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3285 | * |
3286 | * After this function returns, the object will be in the new cache-level | |
3287 | * across all GTT and the contents of the backing storage will be coherent, | |
3288 | * with respect to the new cache-level. In order to keep the backing storage | |
3289 | * coherent for all users, we only allow a single cache level to be set | |
3290 | * globally on the object and prevent it from being changed whilst the | |
3291 | * hardware is reading from the object. That is if the object is currently | |
3292 | * on the scanout it will be set to uncached (or equivalent display | |
3293 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3294 | * that all direct access to the scanout remains coherent. | |
3295 | */ | |
e4ffd173 CW |
3296 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3297 | enum i915_cache_level cache_level) | |
3298 | { | |
aa653a68 | 3299 | struct i915_vma *vma; |
ed75a55b | 3300 | int ret = 0; |
e4ffd173 CW |
3301 | |
3302 | if (obj->cache_level == cache_level) | |
ed75a55b | 3303 | goto out; |
e4ffd173 | 3304 | |
ef55f92a CW |
3305 | /* Inspect the list of currently bound VMA and unbind any that would |
3306 | * be invalid given the new cache-level. This is principally to | |
3307 | * catch the issue of the CS prefetch crossing page boundaries and | |
3308 | * reading an invalid PTE on older architectures. | |
3309 | */ | |
aa653a68 CW |
3310 | restart: |
3311 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3312 | if (!drm_mm_node_allocated(&vma->node)) |
3313 | continue; | |
3314 | ||
20dfbde4 | 3315 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3316 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3317 | return -EBUSY; | |
3318 | } | |
3319 | ||
aa653a68 CW |
3320 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3321 | continue; | |
3322 | ||
3323 | ret = i915_vma_unbind(vma); | |
3324 | if (ret) | |
3325 | return ret; | |
3326 | ||
3327 | /* As unbinding may affect other elements in the | |
3328 | * obj->vma_list (due to side-effects from retiring | |
3329 | * an active vma), play safe and restart the iterator. | |
3330 | */ | |
3331 | goto restart; | |
42d6ab48 CW |
3332 | } |
3333 | ||
ef55f92a CW |
3334 | /* We can reuse the existing drm_mm nodes but need to change the |
3335 | * cache-level on the PTE. We could simply unbind them all and | |
3336 | * rebind with the correct cache-level on next use. However since | |
3337 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3338 | * rewrite the PTE in the belief that doing so tramples upon less | |
3339 | * state and so involves less work. | |
3340 | */ | |
15717de2 | 3341 | if (obj->bind_count) { |
ef55f92a CW |
3342 | /* Before we change the PTE, the GPU must not be accessing it. |
3343 | * If we wait upon the object, we know that all the bound | |
3344 | * VMA are no longer active. | |
3345 | */ | |
2e2f351d | 3346 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3347 | if (ret) |
3348 | return ret; | |
3349 | ||
aa653a68 | 3350 | if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) { |
ef55f92a CW |
3351 | /* Access to snoopable pages through the GTT is |
3352 | * incoherent and on some machines causes a hard | |
3353 | * lockup. Relinquish the CPU mmaping to force | |
3354 | * userspace to refault in the pages and we can | |
3355 | * then double check if the GTT mapping is still | |
3356 | * valid for that pointer access. | |
3357 | */ | |
3358 | i915_gem_release_mmap(obj); | |
3359 | ||
3360 | /* As we no longer need a fence for GTT access, | |
3361 | * we can relinquish it now (and so prevent having | |
3362 | * to steal a fence from someone else on the next | |
3363 | * fence request). Note GPU activity would have | |
3364 | * dropped the fence as all snoopable access is | |
3365 | * supposed to be linear. | |
3366 | */ | |
49ef5294 CW |
3367 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3368 | ret = i915_vma_put_fence(vma); | |
3369 | if (ret) | |
3370 | return ret; | |
3371 | } | |
ef55f92a CW |
3372 | } else { |
3373 | /* We either have incoherent backing store and | |
3374 | * so no GTT access or the architecture is fully | |
3375 | * coherent. In such cases, existing GTT mmaps | |
3376 | * ignore the cache bit in the PTE and we can | |
3377 | * rewrite it without confusing the GPU or having | |
3378 | * to force userspace to fault back in its mmaps. | |
3379 | */ | |
e4ffd173 CW |
3380 | } |
3381 | ||
1c7f4bca | 3382 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3383 | if (!drm_mm_node_allocated(&vma->node)) |
3384 | continue; | |
3385 | ||
3386 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3387 | if (ret) | |
3388 | return ret; | |
3389 | } | |
e4ffd173 CW |
3390 | } |
3391 | ||
1c7f4bca | 3392 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3393 | vma->node.color = cache_level; |
3394 | obj->cache_level = cache_level; | |
3395 | ||
ed75a55b | 3396 | out: |
ef55f92a CW |
3397 | /* Flush the dirty CPU caches to the backing storage so that the |
3398 | * object is now coherent at its new cache level (with respect | |
3399 | * to the access domain). | |
3400 | */ | |
b50a5371 | 3401 | if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { |
0f71979a | 3402 | if (i915_gem_clflush_object(obj, true)) |
c033666a | 3403 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
3404 | } |
3405 | ||
e4ffd173 CW |
3406 | return 0; |
3407 | } | |
3408 | ||
199adf40 BW |
3409 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3410 | struct drm_file *file) | |
e6994aee | 3411 | { |
199adf40 | 3412 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3413 | struct drm_i915_gem_object *obj; |
e6994aee | 3414 | |
03ac0642 CW |
3415 | obj = i915_gem_object_lookup(file, args->handle); |
3416 | if (!obj) | |
432be69d | 3417 | return -ENOENT; |
e6994aee | 3418 | |
651d794f CW |
3419 | switch (obj->cache_level) { |
3420 | case I915_CACHE_LLC: | |
3421 | case I915_CACHE_L3_LLC: | |
3422 | args->caching = I915_CACHING_CACHED; | |
3423 | break; | |
3424 | ||
4257d3ba CW |
3425 | case I915_CACHE_WT: |
3426 | args->caching = I915_CACHING_DISPLAY; | |
3427 | break; | |
3428 | ||
651d794f CW |
3429 | default: |
3430 | args->caching = I915_CACHING_NONE; | |
3431 | break; | |
3432 | } | |
e6994aee | 3433 | |
34911fd3 | 3434 | i915_gem_object_put_unlocked(obj); |
432be69d | 3435 | return 0; |
e6994aee CW |
3436 | } |
3437 | ||
199adf40 BW |
3438 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3439 | struct drm_file *file) | |
e6994aee | 3440 | { |
fac5e23e | 3441 | struct drm_i915_private *dev_priv = to_i915(dev); |
199adf40 | 3442 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3443 | struct drm_i915_gem_object *obj; |
3444 | enum i915_cache_level level; | |
3445 | int ret; | |
3446 | ||
199adf40 BW |
3447 | switch (args->caching) { |
3448 | case I915_CACHING_NONE: | |
e6994aee CW |
3449 | level = I915_CACHE_NONE; |
3450 | break; | |
199adf40 | 3451 | case I915_CACHING_CACHED: |
e5756c10 ID |
3452 | /* |
3453 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3454 | * snooped mapping may leave stale data in a corresponding CPU | |
3455 | * cacheline, whereas normally such cachelines would get | |
3456 | * invalidated. | |
3457 | */ | |
ca377809 | 3458 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
3459 | return -ENODEV; |
3460 | ||
e6994aee CW |
3461 | level = I915_CACHE_LLC; |
3462 | break; | |
4257d3ba CW |
3463 | case I915_CACHING_DISPLAY: |
3464 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3465 | break; | |
e6994aee CW |
3466 | default: |
3467 | return -EINVAL; | |
3468 | } | |
3469 | ||
fd0fe6ac ID |
3470 | intel_runtime_pm_get(dev_priv); |
3471 | ||
3bc2913e BW |
3472 | ret = i915_mutex_lock_interruptible(dev); |
3473 | if (ret) | |
fd0fe6ac | 3474 | goto rpm_put; |
3bc2913e | 3475 | |
03ac0642 CW |
3476 | obj = i915_gem_object_lookup(file, args->handle); |
3477 | if (!obj) { | |
e6994aee CW |
3478 | ret = -ENOENT; |
3479 | goto unlock; | |
3480 | } | |
3481 | ||
3482 | ret = i915_gem_object_set_cache_level(obj, level); | |
3483 | ||
f8c417cd | 3484 | i915_gem_object_put(obj); |
e6994aee CW |
3485 | unlock: |
3486 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
3487 | rpm_put: |
3488 | intel_runtime_pm_put(dev_priv); | |
3489 | ||
e6994aee CW |
3490 | return ret; |
3491 | } | |
3492 | ||
b9241ea3 | 3493 | /* |
2da3b9b9 CW |
3494 | * Prepare buffer for display plane (scanout, cursors, etc). |
3495 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3496 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3497 | */ |
058d88c4 | 3498 | struct i915_vma * |
2da3b9b9 CW |
3499 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3500 | u32 alignment, | |
e6617330 | 3501 | const struct i915_ggtt_view *view) |
b9241ea3 | 3502 | { |
058d88c4 | 3503 | struct i915_vma *vma; |
2da3b9b9 | 3504 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3505 | int ret; |
3506 | ||
cc98b413 CW |
3507 | /* Mark the pin_display early so that we account for the |
3508 | * display coherency whilst setting up the cache domains. | |
3509 | */ | |
8a0c39b1 | 3510 | obj->pin_display++; |
cc98b413 | 3511 | |
a7ef0640 EA |
3512 | /* The display engine is not coherent with the LLC cache on gen6. As |
3513 | * a result, we make sure that the pinning that is about to occur is | |
3514 | * done with uncached PTEs. This is lowest common denominator for all | |
3515 | * chipsets. | |
3516 | * | |
3517 | * However for gen6+, we could do better by using the GFDT bit instead | |
3518 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3519 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3520 | */ | |
651d794f CW |
3521 | ret = i915_gem_object_set_cache_level(obj, |
3522 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3523 | if (ret) { |
3524 | vma = ERR_PTR(ret); | |
cc98b413 | 3525 | goto err_unpin_display; |
058d88c4 | 3526 | } |
a7ef0640 | 3527 | |
2da3b9b9 CW |
3528 | /* As the user may map the buffer once pinned in the display plane |
3529 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3530 | * always use map_and_fenceable for all scanout buffers. However, |
3531 | * it may simply be too big to fit into mappable, in which case | |
3532 | * put it anyway and hope that userspace can cope (but always first | |
3533 | * try to preserve the existing ABI). | |
2da3b9b9 | 3534 | */ |
2efb813d CW |
3535 | vma = ERR_PTR(-ENOSPC); |
3536 | if (view->type == I915_GGTT_VIEW_NORMAL) | |
3537 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, | |
3538 | PIN_MAPPABLE | PIN_NONBLOCK); | |
3539 | if (IS_ERR(vma)) | |
3540 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, 0); | |
058d88c4 | 3541 | if (IS_ERR(vma)) |
cc98b413 | 3542 | goto err_unpin_display; |
2da3b9b9 | 3543 | |
d8923dcf CW |
3544 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3545 | ||
058d88c4 CW |
3546 | WARN_ON(obj->pin_display > i915_vma_pin_count(vma)); |
3547 | ||
e62b59e4 | 3548 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3549 | |
2da3b9b9 | 3550 | old_write_domain = obj->base.write_domain; |
05394f39 | 3551 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3552 | |
3553 | /* It should now be out of any other write domains, and we can update | |
3554 | * the domain values for our changes. | |
3555 | */ | |
e5f1d962 | 3556 | obj->base.write_domain = 0; |
05394f39 | 3557 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3558 | |
3559 | trace_i915_gem_object_change_domain(obj, | |
3560 | old_read_domains, | |
2da3b9b9 | 3561 | old_write_domain); |
b9241ea3 | 3562 | |
058d88c4 | 3563 | return vma; |
cc98b413 CW |
3564 | |
3565 | err_unpin_display: | |
8a0c39b1 | 3566 | obj->pin_display--; |
058d88c4 | 3567 | return vma; |
cc98b413 CW |
3568 | } |
3569 | ||
3570 | void | |
058d88c4 | 3571 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3572 | { |
058d88c4 | 3573 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3574 | return; |
3575 | ||
d8923dcf CW |
3576 | if (--vma->obj->pin_display == 0) |
3577 | vma->display_alignment = 0; | |
e6617330 | 3578 | |
383d5823 CW |
3579 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
3580 | if (!i915_vma_is_active(vma)) | |
3581 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3582 | ||
058d88c4 CW |
3583 | i915_vma_unpin(vma); |
3584 | WARN_ON(vma->obj->pin_display > i915_vma_pin_count(vma)); | |
b9241ea3 ZW |
3585 | } |
3586 | ||
e47c68e9 EA |
3587 | /** |
3588 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3589 | * @obj: object to act on |
3590 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3591 | * |
3592 | * This function returns when the move is complete, including waiting on | |
3593 | * flushes to occur. | |
3594 | */ | |
dabdfe02 | 3595 | int |
919926ae | 3596 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3597 | { |
1c5d22f7 | 3598 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3599 | int ret; |
3600 | ||
0201f1ec | 3601 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3602 | if (ret) |
3603 | return ret; | |
3604 | ||
c13d87ea CW |
3605 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3606 | return 0; | |
3607 | ||
e47c68e9 | 3608 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3609 | |
05394f39 CW |
3610 | old_write_domain = obj->base.write_domain; |
3611 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3612 | |
e47c68e9 | 3613 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3614 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3615 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3616 | |
05394f39 | 3617 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3618 | } |
3619 | ||
3620 | /* It should now be out of any other write domains, and we can update | |
3621 | * the domain values for our changes. | |
3622 | */ | |
05394f39 | 3623 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3624 | |
3625 | /* If we're writing through the CPU, then the GPU read domains will | |
3626 | * need to be invalidated at next use. | |
3627 | */ | |
3628 | if (write) { | |
05394f39 CW |
3629 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3630 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3631 | } |
2ef7eeaa | 3632 | |
1c5d22f7 CW |
3633 | trace_i915_gem_object_change_domain(obj, |
3634 | old_read_domains, | |
3635 | old_write_domain); | |
3636 | ||
2ef7eeaa EA |
3637 | return 0; |
3638 | } | |
3639 | ||
673a394b EA |
3640 | /* Throttle our rendering by waiting until the ring has completed our requests |
3641 | * emitted over 20 msec ago. | |
3642 | * | |
b962442e EA |
3643 | * Note that if we were to use the current jiffies each time around the loop, |
3644 | * we wouldn't escape the function with any frames outstanding if the time to | |
3645 | * render a frame was over 20ms. | |
3646 | * | |
673a394b EA |
3647 | * This should get us reasonable parallelism between CPU and GPU but also |
3648 | * relatively low latency when blocking on a particular request to finish. | |
3649 | */ | |
40a5f0de | 3650 | static int |
f787a5f5 | 3651 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3652 | { |
fac5e23e | 3653 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3654 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3655 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3656 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 3657 | int ret; |
93533c29 | 3658 | |
308887aa DV |
3659 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3660 | if (ret) | |
3661 | return ret; | |
3662 | ||
f4457ae7 CW |
3663 | /* ABI: return -EIO if already wedged */ |
3664 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3665 | return -EIO; | |
e110e8d6 | 3666 | |
1c25595f | 3667 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3668 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3669 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3670 | break; | |
40a5f0de | 3671 | |
fcfa423c JH |
3672 | /* |
3673 | * Note that the request might not have been submitted yet. | |
3674 | * In which case emitted_jiffies will be zero. | |
3675 | */ | |
3676 | if (!request->emitted_jiffies) | |
3677 | continue; | |
3678 | ||
54fb2411 | 3679 | target = request; |
b962442e | 3680 | } |
ff865885 | 3681 | if (target) |
e8a261ea | 3682 | i915_gem_request_get(target); |
1c25595f | 3683 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3684 | |
54fb2411 | 3685 | if (target == NULL) |
f787a5f5 | 3686 | return 0; |
2bc43b5c | 3687 | |
ea746f36 | 3688 | ret = i915_wait_request(target, I915_WAIT_INTERRUPTIBLE, NULL, NULL); |
e8a261ea | 3689 | i915_gem_request_put(target); |
ff865885 | 3690 | |
40a5f0de EA |
3691 | return ret; |
3692 | } | |
3693 | ||
d23db88c | 3694 | static bool |
91b2db6f | 3695 | i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) |
d23db88c | 3696 | { |
59bfa124 CW |
3697 | if (!drm_mm_node_allocated(&vma->node)) |
3698 | return false; | |
3699 | ||
91b2db6f CW |
3700 | if (vma->node.size < size) |
3701 | return true; | |
3702 | ||
3703 | if (alignment && vma->node.start & (alignment - 1)) | |
d23db88c CW |
3704 | return true; |
3705 | ||
05a20d09 | 3706 | if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma)) |
d23db88c CW |
3707 | return true; |
3708 | ||
3709 | if (flags & PIN_OFFSET_BIAS && | |
3710 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
3711 | return true; | |
3712 | ||
506a8e87 CW |
3713 | if (flags & PIN_OFFSET_FIXED && |
3714 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
3715 | return true; | |
3716 | ||
d23db88c CW |
3717 | return false; |
3718 | } | |
3719 | ||
d0710abb CW |
3720 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
3721 | { | |
3722 | struct drm_i915_gem_object *obj = vma->obj; | |
a9f1481f | 3723 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d0710abb CW |
3724 | bool mappable, fenceable; |
3725 | u32 fence_size, fence_alignment; | |
3726 | ||
a9f1481f | 3727 | fence_size = i915_gem_get_ggtt_size(dev_priv, |
05a20d09 | 3728 | vma->size, |
3e510a8e | 3729 | i915_gem_object_get_tiling(obj)); |
a9f1481f | 3730 | fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, |
05a20d09 | 3731 | vma->size, |
3e510a8e | 3732 | i915_gem_object_get_tiling(obj), |
ad1a7d20 | 3733 | true); |
d0710abb CW |
3734 | |
3735 | fenceable = (vma->node.size == fence_size && | |
3736 | (vma->node.start & (fence_alignment - 1)) == 0); | |
3737 | ||
3738 | mappable = (vma->node.start + fence_size <= | |
a9f1481f | 3739 | dev_priv->ggtt.mappable_end); |
d0710abb | 3740 | |
05a20d09 CW |
3741 | if (mappable && fenceable) |
3742 | vma->flags |= I915_VMA_CAN_FENCE; | |
3743 | else | |
3744 | vma->flags &= ~I915_VMA_CAN_FENCE; | |
d0710abb CW |
3745 | } |
3746 | ||
305bc234 CW |
3747 | int __i915_vma_do_pin(struct i915_vma *vma, |
3748 | u64 size, u64 alignment, u64 flags) | |
673a394b | 3749 | { |
305bc234 | 3750 | unsigned int bound = vma->flags; |
673a394b EA |
3751 | int ret; |
3752 | ||
59bfa124 | 3753 | GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0); |
3272db53 | 3754 | GEM_BUG_ON((flags & PIN_GLOBAL) && !i915_vma_is_ggtt(vma)); |
d7f46fc4 | 3755 | |
305bc234 CW |
3756 | if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) { |
3757 | ret = -EBUSY; | |
3758 | goto err; | |
3759 | } | |
ac0c6b5a | 3760 | |
de895082 | 3761 | if ((bound & I915_VMA_BIND_MASK) == 0) { |
59bfa124 CW |
3762 | ret = i915_vma_insert(vma, size, alignment, flags); |
3763 | if (ret) | |
3764 | goto err; | |
fe14d5f4 | 3765 | } |
74898d7e | 3766 | |
59bfa124 | 3767 | ret = i915_vma_bind(vma, vma->obj->cache_level, flags); |
3b16525c | 3768 | if (ret) |
59bfa124 | 3769 | goto err; |
3b16525c | 3770 | |
3272db53 | 3771 | if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND) |
d0710abb | 3772 | __i915_vma_set_map_and_fenceable(vma); |
ef79e17c | 3773 | |
3b16525c | 3774 | GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags)); |
673a394b | 3775 | return 0; |
673a394b | 3776 | |
59bfa124 CW |
3777 | err: |
3778 | __i915_vma_unpin(vma); | |
3779 | return ret; | |
ec7adb6e JL |
3780 | } |
3781 | ||
058d88c4 | 3782 | struct i915_vma * |
ec7adb6e JL |
3783 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3784 | const struct i915_ggtt_view *view, | |
91b2db6f | 3785 | u64 size, |
2ffffd0f CW |
3786 | u64 alignment, |
3787 | u64 flags) | |
ec7adb6e | 3788 | { |
058d88c4 | 3789 | struct i915_address_space *vm = &to_i915(obj->base.dev)->ggtt.base; |
59bfa124 CW |
3790 | struct i915_vma *vma; |
3791 | int ret; | |
72e96d64 | 3792 | |
058d88c4 | 3793 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view); |
59bfa124 | 3794 | if (IS_ERR(vma)) |
058d88c4 | 3795 | return vma; |
59bfa124 CW |
3796 | |
3797 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3798 | if (flags & PIN_NONBLOCK && | |
3799 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 3800 | return ERR_PTR(-ENOSPC); |
59bfa124 CW |
3801 | |
3802 | WARN(i915_vma_is_pinned(vma), | |
3803 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
3804 | " offset=%08x, req.alignment=%llx," |
3805 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
3806 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 3807 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 3808 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
3809 | ret = i915_vma_unbind(vma); |
3810 | if (ret) | |
058d88c4 | 3811 | return ERR_PTR(ret); |
59bfa124 CW |
3812 | } |
3813 | ||
058d88c4 CW |
3814 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
3815 | if (ret) | |
3816 | return ERR_PTR(ret); | |
ec7adb6e | 3817 | |
058d88c4 | 3818 | return vma; |
673a394b EA |
3819 | } |
3820 | ||
edf6b76f | 3821 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
3822 | { |
3823 | /* Note that we could alias engines in the execbuf API, but | |
3824 | * that would be very unwise as it prevents userspace from | |
3825 | * fine control over engine selection. Ahem. | |
3826 | * | |
3827 | * This should be something like EXEC_MAX_ENGINE instead of | |
3828 | * I915_NUM_ENGINES. | |
3829 | */ | |
3830 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3831 | return 0x10000 << id; | |
3832 | } | |
3833 | ||
3834 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3835 | { | |
70cb472c CW |
3836 | /* The uABI guarantees an active writer is also amongst the read |
3837 | * engines. This would be true if we accessed the activity tracking | |
3838 | * under the lock, but as we perform the lookup of the object and | |
3839 | * its activity locklessly we can not guarantee that the last_write | |
3840 | * being active implies that we have set the same engine flag from | |
3841 | * last_read - hence we always set both read and write busy for | |
3842 | * last_write. | |
3843 | */ | |
3844 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
3845 | } |
3846 | ||
edf6b76f | 3847 | static __always_inline unsigned int |
3fdc13c7 CW |
3848 | __busy_set_if_active(const struct i915_gem_active *active, |
3849 | unsigned int (*flag)(unsigned int id)) | |
3850 | { | |
1255501d | 3851 | struct drm_i915_gem_request *request; |
3fdc13c7 | 3852 | |
1255501d CW |
3853 | request = rcu_dereference(active->request); |
3854 | if (!request || i915_gem_request_completed(request)) | |
3855 | return 0; | |
3fdc13c7 | 3856 | |
1255501d CW |
3857 | /* This is racy. See __i915_gem_active_get_rcu() for an in detail |
3858 | * discussion of how to handle the race correctly, but for reporting | |
3859 | * the busy state we err on the side of potentially reporting the | |
3860 | * wrong engine as being busy (but we guarantee that the result | |
3861 | * is at least self-consistent). | |
3862 | * | |
3863 | * As we use SLAB_DESTROY_BY_RCU, the request may be reallocated | |
3864 | * whilst we are inspecting it, even under the RCU read lock as we are. | |
3865 | * This means that there is a small window for the engine and/or the | |
3866 | * seqno to have been overwritten. The seqno will always be in the | |
3867 | * future compared to the intended, and so we know that if that | |
3868 | * seqno is idle (on whatever engine) our request is idle and the | |
3869 | * return 0 above is correct. | |
3870 | * | |
3871 | * The issue is that if the engine is switched, it is just as likely | |
3872 | * to report that it is busy (but since the switch happened, we know | |
3873 | * the request should be idle). So there is a small chance that a busy | |
3874 | * result is actually the wrong engine. | |
3875 | * | |
3876 | * So why don't we care? | |
3877 | * | |
3878 | * For starters, the busy ioctl is a heuristic that is by definition | |
3879 | * racy. Even with perfect serialisation in the driver, the hardware | |
3880 | * state is constantly advancing - the state we report to the user | |
3881 | * is stale. | |
3882 | * | |
3883 | * The critical information for the busy-ioctl is whether the object | |
3884 | * is idle as userspace relies on that to detect whether its next | |
3885 | * access will stall, or if it has missed submitting commands to | |
3886 | * the hardware allowing the GPU to stall. We never generate a | |
3887 | * false-positive for idleness, thus busy-ioctl is reliable at the | |
3888 | * most fundamental level, and we maintain the guarantee that a | |
3889 | * busy object left to itself will eventually become idle (and stay | |
3890 | * idle!). | |
3891 | * | |
3892 | * We allow ourselves the leeway of potentially misreporting the busy | |
3893 | * state because that is an optimisation heuristic that is constantly | |
3894 | * in flux. Being quickly able to detect the busy/idle state is much | |
3895 | * more important than accurate logging of exactly which engines were | |
3896 | * busy. | |
3897 | * | |
3898 | * For accuracy in reporting the engine, we could use | |
3899 | * | |
3900 | * result = 0; | |
3901 | * request = __i915_gem_active_get_rcu(active); | |
3902 | * if (request) { | |
3903 | * if (!i915_gem_request_completed(request)) | |
3904 | * result = flag(request->engine->exec_id); | |
3905 | * i915_gem_request_put(request); | |
3906 | * } | |
3907 | * | |
3908 | * but that still remains susceptible to both hardware and userspace | |
3909 | * races. So we accept making the result of that race slightly worse, | |
3910 | * given the rarity of the race and its low impact on the result. | |
3911 | */ | |
3912 | return flag(READ_ONCE(request->engine->exec_id)); | |
3fdc13c7 CW |
3913 | } |
3914 | ||
edf6b76f | 3915 | static __always_inline unsigned int |
3fdc13c7 CW |
3916 | busy_check_reader(const struct i915_gem_active *active) |
3917 | { | |
3918 | return __busy_set_if_active(active, __busy_read_flag); | |
3919 | } | |
3920 | ||
edf6b76f | 3921 | static __always_inline unsigned int |
3fdc13c7 CW |
3922 | busy_check_writer(const struct i915_gem_active *active) |
3923 | { | |
3924 | return __busy_set_if_active(active, __busy_write_id); | |
3925 | } | |
3926 | ||
673a394b EA |
3927 | int |
3928 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3929 | struct drm_file *file) |
673a394b EA |
3930 | { |
3931 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3932 | struct drm_i915_gem_object *obj; |
3fdc13c7 | 3933 | unsigned long active; |
673a394b | 3934 | |
03ac0642 | 3935 | obj = i915_gem_object_lookup(file, args->handle); |
3fdc13c7 CW |
3936 | if (!obj) |
3937 | return -ENOENT; | |
d1b851fc | 3938 | |
426960be | 3939 | args->busy = 0; |
3fdc13c7 CW |
3940 | active = __I915_BO_ACTIVE(obj); |
3941 | if (active) { | |
3942 | int idx; | |
426960be | 3943 | |
3fdc13c7 CW |
3944 | /* Yes, the lookups are intentionally racy. |
3945 | * | |
3946 | * First, we cannot simply rely on __I915_BO_ACTIVE. We have | |
3947 | * to regard the value as stale and as our ABI guarantees | |
3948 | * forward progress, we confirm the status of each active | |
3949 | * request with the hardware. | |
3950 | * | |
3951 | * Even though we guard the pointer lookup by RCU, that only | |
3952 | * guarantees that the pointer and its contents remain | |
3953 | * dereferencable and does *not* mean that the request we | |
3954 | * have is the same as the one being tracked by the object. | |
3955 | * | |
3956 | * Consider that we lookup the request just as it is being | |
3957 | * retired and freed. We take a local copy of the pointer, | |
3958 | * but before we add its engine into the busy set, the other | |
3959 | * thread reallocates it and assigns it to a task on another | |
1255501d CW |
3960 | * engine with a fresh and incomplete seqno. Guarding against |
3961 | * that requires careful serialisation and reference counting, | |
3962 | * i.e. using __i915_gem_active_get_request_rcu(). We don't, | |
3963 | * instead we expect that if the result is busy, which engines | |
3964 | * are busy is not completely reliable - we only guarantee | |
3965 | * that the object was busy. | |
3fdc13c7 CW |
3966 | */ |
3967 | rcu_read_lock(); | |
3968 | ||
3969 | for_each_active(active, idx) | |
3970 | args->busy |= busy_check_reader(&obj->last_read[idx]); | |
3971 | ||
3972 | /* For ABI sanity, we only care that the write engine is in | |
70cb472c CW |
3973 | * the set of read engines. This should be ensured by the |
3974 | * ordering of setting last_read/last_write in | |
3975 | * i915_vma_move_to_active(), and then in reverse in retire. | |
3976 | * However, for good measure, we always report the last_write | |
3977 | * request as a busy read as well as being a busy write. | |
3fdc13c7 CW |
3978 | * |
3979 | * We don't care that the set of active read/write engines | |
3980 | * may change during construction of the result, as it is | |
3981 | * equally liable to change before userspace can inspect | |
3982 | * the result. | |
3983 | */ | |
3984 | args->busy |= busy_check_writer(&obj->last_write); | |
3985 | ||
3986 | rcu_read_unlock(); | |
426960be | 3987 | } |
673a394b | 3988 | |
3fdc13c7 CW |
3989 | i915_gem_object_put_unlocked(obj); |
3990 | return 0; | |
673a394b EA |
3991 | } |
3992 | ||
3993 | int | |
3994 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3995 | struct drm_file *file_priv) | |
3996 | { | |
0206e353 | 3997 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3998 | } |
3999 | ||
3ef94daa CW |
4000 | int |
4001 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4002 | struct drm_file *file_priv) | |
4003 | { | |
fac5e23e | 4004 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4005 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4006 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4007 | int ret; |
3ef94daa CW |
4008 | |
4009 | switch (args->madv) { | |
4010 | case I915_MADV_DONTNEED: | |
4011 | case I915_MADV_WILLNEED: | |
4012 | break; | |
4013 | default: | |
4014 | return -EINVAL; | |
4015 | } | |
4016 | ||
1d7cfea1 CW |
4017 | ret = i915_mutex_lock_interruptible(dev); |
4018 | if (ret) | |
4019 | return ret; | |
4020 | ||
03ac0642 CW |
4021 | obj = i915_gem_object_lookup(file_priv, args->handle); |
4022 | if (!obj) { | |
1d7cfea1 CW |
4023 | ret = -ENOENT; |
4024 | goto unlock; | |
3ef94daa | 4025 | } |
3ef94daa | 4026 | |
656bfa3a | 4027 | if (obj->pages && |
3e510a8e | 4028 | i915_gem_object_is_tiled(obj) && |
656bfa3a DV |
4029 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
4030 | if (obj->madv == I915_MADV_WILLNEED) | |
4031 | i915_gem_object_unpin_pages(obj); | |
4032 | if (args->madv == I915_MADV_WILLNEED) | |
4033 | i915_gem_object_pin_pages(obj); | |
4034 | } | |
4035 | ||
05394f39 CW |
4036 | if (obj->madv != __I915_MADV_PURGED) |
4037 | obj->madv = args->madv; | |
3ef94daa | 4038 | |
6c085a72 | 4039 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4040 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4041 | i915_gem_object_truncate(obj); |
4042 | ||
05394f39 | 4043 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4044 | |
f8c417cd | 4045 | i915_gem_object_put(obj); |
1d7cfea1 | 4046 | unlock: |
3ef94daa | 4047 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4048 | return ret; |
3ef94daa CW |
4049 | } |
4050 | ||
37e680a1 CW |
4051 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4052 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4053 | { |
b4716185 CW |
4054 | int i; |
4055 | ||
35c20a60 | 4056 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 4057 | for (i = 0; i < I915_NUM_ENGINES; i++) |
fa545cbf CW |
4058 | init_request_active(&obj->last_read[i], |
4059 | i915_gem_object_retire__read); | |
4060 | init_request_active(&obj->last_write, | |
4061 | i915_gem_object_retire__write); | |
b25cb2f8 | 4062 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4063 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4064 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4065 | |
37e680a1 CW |
4066 | obj->ops = ops; |
4067 | ||
50349247 | 4068 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
0327d6ba | 4069 | obj->madv = I915_MADV_WILLNEED; |
0327d6ba | 4070 | |
f19ec8cb | 4071 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4072 | } |
4073 | ||
37e680a1 | 4074 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 4075 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
4076 | .get_pages = i915_gem_object_get_pages_gtt, |
4077 | .put_pages = i915_gem_object_put_pages_gtt, | |
4078 | }; | |
4079 | ||
d37cd8a8 | 4080 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 4081 | size_t size) |
ac52bc56 | 4082 | { |
c397b908 | 4083 | struct drm_i915_gem_object *obj; |
5949eac4 | 4084 | struct address_space *mapping; |
1a240d4d | 4085 | gfp_t mask; |
fe3db79b | 4086 | int ret; |
ac52bc56 | 4087 | |
42dcedd4 | 4088 | obj = i915_gem_object_alloc(dev); |
c397b908 | 4089 | if (obj == NULL) |
fe3db79b | 4090 | return ERR_PTR(-ENOMEM); |
673a394b | 4091 | |
fe3db79b CW |
4092 | ret = drm_gem_object_init(dev, &obj->base, size); |
4093 | if (ret) | |
4094 | goto fail; | |
673a394b | 4095 | |
bed1ea95 CW |
4096 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4097 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4098 | /* 965gm cannot relocate objects above 4GiB. */ | |
4099 | mask &= ~__GFP_HIGHMEM; | |
4100 | mask |= __GFP_DMA32; | |
4101 | } | |
4102 | ||
93c76a3d | 4103 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4104 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4105 | |
37e680a1 | 4106 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4107 | |
c397b908 DV |
4108 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4109 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4110 | |
3d29b842 ED |
4111 | if (HAS_LLC(dev)) { |
4112 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4113 | * cache) for about a 10% performance improvement |
4114 | * compared to uncached. Graphics requests other than | |
4115 | * display scanout are coherent with the CPU in | |
4116 | * accessing this cache. This means in this mode we | |
4117 | * don't need to clflush on the CPU side, and on the | |
4118 | * GPU side we only need to flush internal caches to | |
4119 | * get data visible to the CPU. | |
4120 | * | |
4121 | * However, we maintain the display planes as UC, and so | |
4122 | * need to rebind when first used as such. | |
4123 | */ | |
4124 | obj->cache_level = I915_CACHE_LLC; | |
4125 | } else | |
4126 | obj->cache_level = I915_CACHE_NONE; | |
4127 | ||
d861e338 DV |
4128 | trace_i915_gem_object_create(obj); |
4129 | ||
05394f39 | 4130 | return obj; |
fe3db79b CW |
4131 | |
4132 | fail: | |
4133 | i915_gem_object_free(obj); | |
4134 | ||
4135 | return ERR_PTR(ret); | |
c397b908 DV |
4136 | } |
4137 | ||
340fbd8c CW |
4138 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4139 | { | |
4140 | /* If we are the last user of the backing storage (be it shmemfs | |
4141 | * pages or stolen etc), we know that the pages are going to be | |
4142 | * immediately released. In this case, we can then skip copying | |
4143 | * back the contents from the GPU. | |
4144 | */ | |
4145 | ||
4146 | if (obj->madv != I915_MADV_WILLNEED) | |
4147 | return false; | |
4148 | ||
4149 | if (obj->base.filp == NULL) | |
4150 | return true; | |
4151 | ||
4152 | /* At first glance, this looks racy, but then again so would be | |
4153 | * userspace racing mmap against close. However, the first external | |
4154 | * reference to the filp can only be obtained through the | |
4155 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4156 | * acquiring such a reference whilst we are in the middle of | |
4157 | * freeing the object. | |
4158 | */ | |
4159 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4160 | } | |
4161 | ||
1488fc08 | 4162 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4163 | { |
1488fc08 | 4164 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4165 | struct drm_device *dev = obj->base.dev; |
fac5e23e | 4166 | struct drm_i915_private *dev_priv = to_i915(dev); |
07fe0b12 | 4167 | struct i915_vma *vma, *next; |
673a394b | 4168 | |
f65c9168 PZ |
4169 | intel_runtime_pm_get(dev_priv); |
4170 | ||
26e12f89 CW |
4171 | trace_i915_gem_object_destroy(obj); |
4172 | ||
b1f788c6 CW |
4173 | /* All file-owned VMA should have been released by this point through |
4174 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4175 | * However, the object may also be bound into the global GTT (e.g. | |
4176 | * older GPUs without per-process support, or for direct access through | |
4177 | * the GTT either for the user or for scanout). Those VMA still need to | |
4178 | * unbound now. | |
4179 | */ | |
1c7f4bca | 4180 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
3272db53 | 4181 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); |
b1f788c6 | 4182 | GEM_BUG_ON(i915_vma_is_active(vma)); |
3272db53 | 4183 | vma->flags &= ~I915_VMA_PIN_MASK; |
b1f788c6 | 4184 | i915_vma_close(vma); |
1488fc08 | 4185 | } |
15717de2 | 4186 | GEM_BUG_ON(obj->bind_count); |
1488fc08 | 4187 | |
1d64ae71 BW |
4188 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4189 | * before progressing. */ | |
4190 | if (obj->stolen) | |
4191 | i915_gem_object_unpin_pages(obj); | |
4192 | ||
faf5bf0a | 4193 | WARN_ON(atomic_read(&obj->frontbuffer_bits)); |
a071fa00 | 4194 | |
656bfa3a DV |
4195 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4196 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
3e510a8e | 4197 | i915_gem_object_is_tiled(obj)) |
656bfa3a DV |
4198 | i915_gem_object_unpin_pages(obj); |
4199 | ||
401c29f6 BW |
4200 | if (WARN_ON(obj->pages_pin_count)) |
4201 | obj->pages_pin_count = 0; | |
340fbd8c | 4202 | if (discard_backing_storage(obj)) |
5537252b | 4203 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4204 | i915_gem_object_put_pages(obj); |
de151cf6 | 4205 | |
9da3da66 CW |
4206 | BUG_ON(obj->pages); |
4207 | ||
2f745ad3 CW |
4208 | if (obj->base.import_attach) |
4209 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4210 | |
5cc9ed4b CW |
4211 | if (obj->ops->release) |
4212 | obj->ops->release(obj); | |
4213 | ||
05394f39 CW |
4214 | drm_gem_object_release(&obj->base); |
4215 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4216 | |
05394f39 | 4217 | kfree(obj->bit_17); |
42dcedd4 | 4218 | i915_gem_object_free(obj); |
f65c9168 PZ |
4219 | |
4220 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4221 | } |
4222 | ||
dcff85c8 | 4223 | int i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4224 | { |
fac5e23e | 4225 | struct drm_i915_private *dev_priv = to_i915(dev); |
dcff85c8 | 4226 | int ret; |
28dfe52a | 4227 | |
54b4f68f CW |
4228 | intel_suspend_gt_powersave(dev_priv); |
4229 | ||
45c5f202 | 4230 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4231 | |
4232 | /* We have to flush all the executing contexts to main memory so | |
4233 | * that they can saved in the hibernation image. To ensure the last | |
4234 | * context image is coherent, we have to switch away from it. That | |
4235 | * leaves the dev_priv->kernel_context still active when | |
4236 | * we actually suspend, and its image in memory may not match the GPU | |
4237 | * state. Fortunately, the kernel_context is disposable and we do | |
4238 | * not rely on its state. | |
4239 | */ | |
4240 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4241 | if (ret) | |
4242 | goto err; | |
4243 | ||
22dd3bb9 CW |
4244 | ret = i915_gem_wait_for_idle(dev_priv, |
4245 | I915_WAIT_INTERRUPTIBLE | | |
4246 | I915_WAIT_LOCKED); | |
f7403347 | 4247 | if (ret) |
45c5f202 | 4248 | goto err; |
f7403347 | 4249 | |
c033666a | 4250 | i915_gem_retire_requests(dev_priv); |
673a394b | 4251 | |
b2e862d0 | 4252 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4253 | mutex_unlock(&dev->struct_mutex); |
4254 | ||
737b1506 | 4255 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4256 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4257 | flush_delayed_work(&dev_priv->gt.idle_work); | |
29105ccc | 4258 | |
bdcf120b CW |
4259 | /* Assert that we sucessfully flushed all the work and |
4260 | * reset the GPU back to its idle, low power state. | |
4261 | */ | |
67d97da3 | 4262 | WARN_ON(dev_priv->gt.awake); |
bdcf120b | 4263 | |
673a394b | 4264 | return 0; |
45c5f202 CW |
4265 | |
4266 | err: | |
4267 | mutex_unlock(&dev->struct_mutex); | |
4268 | return ret; | |
673a394b EA |
4269 | } |
4270 | ||
5ab57c70 CW |
4271 | void i915_gem_resume(struct drm_device *dev) |
4272 | { | |
4273 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4274 | ||
4275 | mutex_lock(&dev->struct_mutex); | |
4276 | i915_gem_restore_gtt_mappings(dev); | |
4277 | ||
4278 | /* As we didn't flush the kernel context before suspend, we cannot | |
4279 | * guarantee that the context image is complete. So let's just reset | |
4280 | * it and start again. | |
4281 | */ | |
821ed7df | 4282 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4283 | |
4284 | mutex_unlock(&dev->struct_mutex); | |
4285 | } | |
4286 | ||
f691e2f4 DV |
4287 | void i915_gem_init_swizzling(struct drm_device *dev) |
4288 | { | |
fac5e23e | 4289 | struct drm_i915_private *dev_priv = to_i915(dev); |
f691e2f4 | 4290 | |
11782b02 | 4291 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4292 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4293 | return; | |
4294 | ||
4295 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4296 | DISP_TILE_SURFACE_SWIZZLING); | |
4297 | ||
11782b02 DV |
4298 | if (IS_GEN5(dev)) |
4299 | return; | |
4300 | ||
f691e2f4 DV |
4301 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4302 | if (IS_GEN6(dev)) | |
6b26c86d | 4303 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4304 | else if (IS_GEN7(dev)) |
6b26c86d | 4305 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4306 | else if (IS_GEN8(dev)) |
4307 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4308 | else |
4309 | BUG(); | |
f691e2f4 | 4310 | } |
e21af88d | 4311 | |
81e7f200 VS |
4312 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4313 | { | |
fac5e23e | 4314 | struct drm_i915_private *dev_priv = to_i915(dev); |
81e7f200 VS |
4315 | |
4316 | I915_WRITE(RING_CTL(base), 0); | |
4317 | I915_WRITE(RING_HEAD(base), 0); | |
4318 | I915_WRITE(RING_TAIL(base), 0); | |
4319 | I915_WRITE(RING_START(base), 0); | |
4320 | } | |
4321 | ||
4322 | static void init_unused_rings(struct drm_device *dev) | |
4323 | { | |
4324 | if (IS_I830(dev)) { | |
4325 | init_unused_ring(dev, PRB1_BASE); | |
4326 | init_unused_ring(dev, SRB0_BASE); | |
4327 | init_unused_ring(dev, SRB1_BASE); | |
4328 | init_unused_ring(dev, SRB2_BASE); | |
4329 | init_unused_ring(dev, SRB3_BASE); | |
4330 | } else if (IS_GEN2(dev)) { | |
4331 | init_unused_ring(dev, SRB0_BASE); | |
4332 | init_unused_ring(dev, SRB1_BASE); | |
4333 | } else if (IS_GEN3(dev)) { | |
4334 | init_unused_ring(dev, PRB1_BASE); | |
4335 | init_unused_ring(dev, PRB2_BASE); | |
4336 | } | |
4337 | } | |
4338 | ||
4fc7c971 BW |
4339 | int |
4340 | i915_gem_init_hw(struct drm_device *dev) | |
4341 | { | |
fac5e23e | 4342 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4343 | struct intel_engine_cs *engine; |
d200cda6 | 4344 | int ret; |
4fc7c971 | 4345 | |
5e4f5189 CW |
4346 | /* Double layer security blanket, see i915_gem_init() */ |
4347 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4348 | ||
3accaf7e | 4349 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4350 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4351 | |
0bf21347 VS |
4352 | if (IS_HASWELL(dev)) |
4353 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4354 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4355 | |
88a2b2a3 | 4356 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4357 | if (IS_IVYBRIDGE(dev)) { |
4358 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4359 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4360 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4361 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4362 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4363 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4364 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4365 | } | |
88a2b2a3 BW |
4366 | } |
4367 | ||
4fc7c971 BW |
4368 | i915_gem_init_swizzling(dev); |
4369 | ||
d5abdfda DV |
4370 | /* |
4371 | * At least 830 can leave some of the unused rings | |
4372 | * "active" (ie. head != tail) after resume which | |
4373 | * will prevent c3 entry. Makes sure all unused rings | |
4374 | * are totally idle. | |
4375 | */ | |
4376 | init_unused_rings(dev); | |
4377 | ||
ed54c1a1 | 4378 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4379 | |
4ad2fd88 JH |
4380 | ret = i915_ppgtt_init_hw(dev); |
4381 | if (ret) { | |
4382 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4383 | goto out; | |
4384 | } | |
4385 | ||
4386 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4387 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4388 | ret = engine->init_hw(engine); |
35a57ffb | 4389 | if (ret) |
5e4f5189 | 4390 | goto out; |
35a57ffb | 4391 | } |
99433931 | 4392 | |
0ccdacf6 PA |
4393 | intel_mocs_init_l3cc_table(dev); |
4394 | ||
33a732f4 | 4395 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
4396 | ret = intel_guc_setup(dev); |
4397 | if (ret) | |
4398 | goto out; | |
33a732f4 | 4399 | |
5e4f5189 CW |
4400 | out: |
4401 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4402 | return ret; |
8187a2b7 ZN |
4403 | } |
4404 | ||
39df9190 CW |
4405 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4406 | { | |
4407 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4408 | return false; | |
4409 | ||
4410 | /* TODO: make semaphores and Execlists play nicely together */ | |
4411 | if (i915.enable_execlists) | |
4412 | return false; | |
4413 | ||
4414 | if (value >= 0) | |
4415 | return value; | |
4416 | ||
4417 | #ifdef CONFIG_INTEL_IOMMU | |
4418 | /* Enable semaphores on SNB when IO remapping is off */ | |
4419 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4420 | return false; | |
4421 | #endif | |
4422 | ||
4423 | return true; | |
4424 | } | |
4425 | ||
1070a42b CW |
4426 | int i915_gem_init(struct drm_device *dev) |
4427 | { | |
fac5e23e | 4428 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
4429 | int ret; |
4430 | ||
1070a42b | 4431 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4432 | |
a83014d3 | 4433 | if (!i915.enable_execlists) { |
821ed7df | 4434 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4435 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4436 | } else { |
821ed7df | 4437 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4438 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4439 | } |
4440 | ||
5e4f5189 CW |
4441 | /* This is just a security blanket to placate dragons. |
4442 | * On some systems, we very sporadically observe that the first TLBs | |
4443 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4444 | * we hold the forcewake during initialisation these problems | |
4445 | * just magically go away. | |
4446 | */ | |
4447 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4448 | ||
72778cb2 | 4449 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4450 | |
4451 | ret = i915_gem_init_ggtt(dev_priv); | |
4452 | if (ret) | |
4453 | goto out_unlock; | |
d62b4892 | 4454 | |
2fa48d8d | 4455 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4456 | if (ret) |
4457 | goto out_unlock; | |
2fa48d8d | 4458 | |
8b3e2d36 | 4459 | ret = intel_engines_init(dev); |
35a57ffb | 4460 | if (ret) |
7bcc3777 | 4461 | goto out_unlock; |
2fa48d8d | 4462 | |
1070a42b | 4463 | ret = i915_gem_init_hw(dev); |
60990320 | 4464 | if (ret == -EIO) { |
7e21d648 | 4465 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4466 | * wedged. But we only want to do this where the GPU is angry, |
4467 | * for all other failure, such as an allocation failure, bail. | |
4468 | */ | |
4469 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4470 | i915_gem_set_wedged(dev_priv); |
60990320 | 4471 | ret = 0; |
1070a42b | 4472 | } |
7bcc3777 JN |
4473 | |
4474 | out_unlock: | |
5e4f5189 | 4475 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4476 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4477 | |
60990320 | 4478 | return ret; |
1070a42b CW |
4479 | } |
4480 | ||
8187a2b7 | 4481 | void |
117897f4 | 4482 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4483 | { |
fac5e23e | 4484 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4485 | struct intel_engine_cs *engine; |
8187a2b7 | 4486 | |
b4ac5afc | 4487 | for_each_engine(engine, dev_priv) |
117897f4 | 4488 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4489 | } |
4490 | ||
64193406 | 4491 | static void |
666796da | 4492 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 4493 | { |
0bc40be8 | 4494 | INIT_LIST_HEAD(&engine->request_list); |
64193406 CW |
4495 | } |
4496 | ||
40ae4e16 ID |
4497 | void |
4498 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4499 | { | |
91c8a326 | 4500 | struct drm_device *dev = &dev_priv->drm; |
49ef5294 | 4501 | int i; |
40ae4e16 ID |
4502 | |
4503 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4504 | !IS_CHERRYVIEW(dev_priv)) | |
4505 | dev_priv->num_fence_regs = 32; | |
4506 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4507 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4508 | dev_priv->num_fence_regs = 16; | |
4509 | else | |
4510 | dev_priv->num_fence_regs = 8; | |
4511 | ||
c033666a | 4512 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4513 | dev_priv->num_fence_regs = |
4514 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4515 | ||
4516 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4517 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4518 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4519 | ||
4520 | fence->i915 = dev_priv; | |
4521 | fence->id = i; | |
4522 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4523 | } | |
40ae4e16 ID |
4524 | i915_gem_restore_fences(dev); |
4525 | ||
4526 | i915_gem_detect_bit_6_swizzle(dev); | |
4527 | } | |
4528 | ||
673a394b | 4529 | void |
d64aa096 | 4530 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 4531 | { |
fac5e23e | 4532 | struct drm_i915_private *dev_priv = to_i915(dev); |
42dcedd4 CW |
4533 | int i; |
4534 | ||
efab6d8d | 4535 | dev_priv->objects = |
42dcedd4 CW |
4536 | kmem_cache_create("i915_gem_object", |
4537 | sizeof(struct drm_i915_gem_object), 0, | |
4538 | SLAB_HWCACHE_ALIGN, | |
4539 | NULL); | |
e20d2ab7 CW |
4540 | dev_priv->vmas = |
4541 | kmem_cache_create("i915_gem_vma", | |
4542 | sizeof(struct i915_vma), 0, | |
4543 | SLAB_HWCACHE_ALIGN, | |
4544 | NULL); | |
efab6d8d CW |
4545 | dev_priv->requests = |
4546 | kmem_cache_create("i915_gem_request", | |
4547 | sizeof(struct drm_i915_gem_request), 0, | |
0eafec6d CW |
4548 | SLAB_HWCACHE_ALIGN | |
4549 | SLAB_RECLAIM_ACCOUNT | | |
4550 | SLAB_DESTROY_BY_RCU, | |
efab6d8d | 4551 | NULL); |
673a394b | 4552 | |
a33afea5 | 4553 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4554 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4555 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4556 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
4557 | for (i = 0; i < I915_NUM_ENGINES; i++) |
4558 | init_engine_lists(&dev_priv->engine[i]); | |
67d97da3 | 4559 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4560 | i915_gem_retire_work_handler); |
67d97da3 | 4561 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4562 | i915_gem_idle_work_handler); |
1f15b76f | 4563 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4564 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4565 | |
72bfa19c CW |
4566 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4567 | ||
6b95a207 | 4568 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4569 | |
ce453d81 CW |
4570 | dev_priv->mm.interruptible = true; |
4571 | ||
6f633402 JL |
4572 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4573 | ||
b5add959 | 4574 | spin_lock_init(&dev_priv->fb_tracking.lock); |
673a394b | 4575 | } |
71acb5eb | 4576 | |
d64aa096 ID |
4577 | void i915_gem_load_cleanup(struct drm_device *dev) |
4578 | { | |
4579 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4580 | ||
4581 | kmem_cache_destroy(dev_priv->requests); | |
4582 | kmem_cache_destroy(dev_priv->vmas); | |
4583 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4584 | |
4585 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4586 | rcu_barrier(); | |
d64aa096 ID |
4587 | } |
4588 | ||
461fb99c CW |
4589 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4590 | { | |
4591 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4592 | struct list_head *phases[] = { |
4593 | &dev_priv->mm.unbound_list, | |
4594 | &dev_priv->mm.bound_list, | |
4595 | NULL | |
4596 | }, **p; | |
461fb99c CW |
4597 | |
4598 | /* Called just before we write the hibernation image. | |
4599 | * | |
4600 | * We need to update the domain tracking to reflect that the CPU | |
4601 | * will be accessing all the pages to create and restore from the | |
4602 | * hibernation, and so upon restoration those pages will be in the | |
4603 | * CPU domain. | |
4604 | * | |
4605 | * To make sure the hibernation image contains the latest state, | |
4606 | * we update that state just before writing out the image. | |
7aab2d53 CW |
4607 | * |
4608 | * To try and reduce the hibernation image, we manually shrink | |
4609 | * the objects as well. | |
461fb99c CW |
4610 | */ |
4611 | ||
7aab2d53 | 4612 | i915_gem_shrink_all(dev_priv); |
461fb99c | 4613 | |
7aab2d53 CW |
4614 | for (p = phases; *p; p++) { |
4615 | list_for_each_entry(obj, *p, global_list) { | |
4616 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4617 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4618 | } | |
461fb99c CW |
4619 | } |
4620 | ||
4621 | return 0; | |
4622 | } | |
4623 | ||
f787a5f5 | 4624 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4625 | { |
f787a5f5 | 4626 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4627 | struct drm_i915_gem_request *request; |
b962442e EA |
4628 | |
4629 | /* Clean up our request list when the client is going away, so that | |
4630 | * later retire_requests won't dereference our soon-to-be-gone | |
4631 | * file_priv. | |
4632 | */ | |
1c25595f | 4633 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4634 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4635 | request->file_priv = NULL; |
1c25595f | 4636 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4637 | |
2e1b8730 | 4638 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4639 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4640 | list_del(&file_priv->rps.link); |
8d3afd7d | 4641 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4642 | } |
b29c19b6 CW |
4643 | } |
4644 | ||
4645 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4646 | { | |
4647 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4648 | int ret; |
b29c19b6 CW |
4649 | |
4650 | DRM_DEBUG_DRIVER("\n"); | |
4651 | ||
4652 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4653 | if (!file_priv) | |
4654 | return -ENOMEM; | |
4655 | ||
4656 | file->driver_priv = file_priv; | |
f19ec8cb | 4657 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4658 | file_priv->file = file; |
2e1b8730 | 4659 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4660 | |
4661 | spin_lock_init(&file_priv->mm.lock); | |
4662 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4663 | |
c80ff16e | 4664 | file_priv->bsd_engine = -1; |
de1add36 | 4665 | |
e422b888 BW |
4666 | ret = i915_gem_context_open(dev, file); |
4667 | if (ret) | |
4668 | kfree(file_priv); | |
b29c19b6 | 4669 | |
e422b888 | 4670 | return ret; |
b29c19b6 CW |
4671 | } |
4672 | ||
b680c37a DV |
4673 | /** |
4674 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4675 | * @old: current GEM buffer for the frontbuffer slots |
4676 | * @new: new GEM buffer for the frontbuffer slots | |
4677 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4678 | * |
4679 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4680 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4681 | */ | |
a071fa00 DV |
4682 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4683 | struct drm_i915_gem_object *new, | |
4684 | unsigned frontbuffer_bits) | |
4685 | { | |
faf5bf0a CW |
4686 | /* Control of individual bits within the mask are guarded by |
4687 | * the owning plane->mutex, i.e. we can never see concurrent | |
4688 | * manipulation of individual bits. But since the bitfield as a whole | |
4689 | * is updated using RMW, we need to use atomics in order to update | |
4690 | * the bits. | |
4691 | */ | |
4692 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4693 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4694 | ||
a071fa00 | 4695 | if (old) { |
faf5bf0a CW |
4696 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4697 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4698 | } |
4699 | ||
4700 | if (new) { | |
faf5bf0a CW |
4701 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4702 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4703 | } |
4704 | } | |
4705 | ||
033908ae DG |
4706 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
4707 | struct page * | |
4708 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
4709 | { | |
4710 | struct page *page; | |
4711 | ||
4712 | /* Only default objects have per-page dirty tracking */ | |
b9bcd14a | 4713 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
033908ae DG |
4714 | return NULL; |
4715 | ||
4716 | page = i915_gem_object_get_page(obj, n); | |
4717 | set_page_dirty(page); | |
4718 | return page; | |
4719 | } | |
4720 | ||
ea70299d DG |
4721 | /* Allocate a new GEM object and fill it with the supplied data */ |
4722 | struct drm_i915_gem_object * | |
4723 | i915_gem_object_create_from_data(struct drm_device *dev, | |
4724 | const void *data, size_t size) | |
4725 | { | |
4726 | struct drm_i915_gem_object *obj; | |
4727 | struct sg_table *sg; | |
4728 | size_t bytes; | |
4729 | int ret; | |
4730 | ||
d37cd8a8 | 4731 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 4732 | if (IS_ERR(obj)) |
ea70299d DG |
4733 | return obj; |
4734 | ||
4735 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4736 | if (ret) | |
4737 | goto fail; | |
4738 | ||
4739 | ret = i915_gem_object_get_pages(obj); | |
4740 | if (ret) | |
4741 | goto fail; | |
4742 | ||
4743 | i915_gem_object_pin_pages(obj); | |
4744 | sg = obj->pages; | |
4745 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 4746 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
4747 | i915_gem_object_unpin_pages(obj); |
4748 | ||
4749 | if (WARN_ON(bytes != size)) { | |
4750 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4751 | ret = -EFAULT; | |
4752 | goto fail; | |
4753 | } | |
4754 | ||
4755 | return obj; | |
4756 | ||
4757 | fail: | |
f8c417cd | 4758 | i915_gem_object_put(obj); |
ea70299d DG |
4759 | return ERR_PTR(ret); |
4760 | } |