Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
42 | bool force); | |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
05394f39 CW |
46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
47 | struct drm_i915_gem_object *obj, | |
71acb5eb | 48 | struct drm_i915_gem_pwrite *args, |
05394f39 | 49 | struct drm_file *file); |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
7dc19d5a DC |
57 | static unsigned long i915_gem_inactive_count(struct shrinker *shrinker, |
58 | struct shrink_control *sc); | |
59 | static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker, | |
60 | struct shrink_control *sc); | |
d9973b43 CW |
61 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
62 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 63 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
cb216aa8 | 64 | static void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
31169714 | 65 | |
c76ce038 CW |
66 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
67 | enum i915_cache_level level) | |
68 | { | |
69 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
70 | } | |
71 | ||
2c22569b CW |
72 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
73 | { | |
74 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
75 | return true; | |
76 | ||
77 | return obj->pin_display; | |
78 | } | |
79 | ||
61050808 CW |
80 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
81 | { | |
82 | if (obj->tiling_mode) | |
83 | i915_gem_release_mmap(obj); | |
84 | ||
85 | /* As we do not have an associated fence register, we will force | |
86 | * a tiling change if we ever need to acquire one. | |
87 | */ | |
5d82e3e6 | 88 | obj->fence_dirty = false; |
61050808 CW |
89 | obj->fence_reg = I915_FENCE_REG_NONE; |
90 | } | |
91 | ||
73aa808f CW |
92 | /* some bookkeeping */ |
93 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count++; |
98 | dev_priv->mm.object_memory += size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
102 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
103 | size_t size) | |
104 | { | |
c20e8355 | 105 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
106 | dev_priv->mm.object_count--; |
107 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 108 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
109 | } |
110 | ||
21dd3734 | 111 | static int |
33196ded | 112 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 113 | { |
30dbf0c0 CW |
114 | int ret; |
115 | ||
7abb690a DV |
116 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
117 | i915_terminally_wedged(error)) | |
1f83fee0 | 118 | if (EXIT_COND) |
30dbf0c0 CW |
119 | return 0; |
120 | ||
0a6759c6 DV |
121 | /* |
122 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
123 | * userspace. If it takes that long something really bad is going on and | |
124 | * we should simply try to bail out and fail as gracefully as possible. | |
125 | */ | |
1f83fee0 DV |
126 | ret = wait_event_interruptible_timeout(error->reset_queue, |
127 | EXIT_COND, | |
128 | 10*HZ); | |
0a6759c6 DV |
129 | if (ret == 0) { |
130 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
131 | return -EIO; | |
132 | } else if (ret < 0) { | |
30dbf0c0 | 133 | return ret; |
0a6759c6 | 134 | } |
1f83fee0 | 135 | #undef EXIT_COND |
30dbf0c0 | 136 | |
21dd3734 | 137 | return 0; |
30dbf0c0 CW |
138 | } |
139 | ||
54cf91dc | 140 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 141 | { |
33196ded | 142 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
143 | int ret; |
144 | ||
33196ded | 145 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
146 | if (ret) |
147 | return ret; | |
148 | ||
149 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
23bc5982 | 153 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
154 | return 0; |
155 | } | |
30dbf0c0 | 156 | |
7d1c4804 | 157 | static inline bool |
05394f39 | 158 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 159 | { |
9843877d | 160 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
161 | } |
162 | ||
79e53945 JB |
163 | int |
164 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 165 | struct drm_file *file) |
79e53945 | 166 | { |
93d18799 | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 168 | struct drm_i915_gem_init *args = data; |
2021746e | 169 | |
7bb6fb8d DV |
170 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
171 | return -ENODEV; | |
172 | ||
2021746e CW |
173 | if (args->gtt_start >= args->gtt_end || |
174 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
175 | return -EINVAL; | |
79e53945 | 176 | |
f534bc0b DV |
177 | /* GEM with user mode setting was never supported on ilk and later. */ |
178 | if (INTEL_INFO(dev)->gen >= 5) | |
179 | return -ENODEV; | |
180 | ||
79e53945 | 181 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
182 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
183 | args->gtt_end); | |
93d18799 | 184 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
185 | mutex_unlock(&dev->struct_mutex); |
186 | ||
2021746e | 187 | return 0; |
673a394b EA |
188 | } |
189 | ||
5a125c3c EA |
190 | int |
191 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 192 | struct drm_file *file) |
5a125c3c | 193 | { |
73aa808f | 194 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 195 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
196 | struct drm_i915_gem_object *obj; |
197 | size_t pinned; | |
5a125c3c | 198 | |
6299f992 | 199 | pinned = 0; |
73aa808f | 200 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 201 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 202 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 203 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 204 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 205 | |
853ba5d2 | 206 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 207 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 208 | |
5a125c3c EA |
209 | return 0; |
210 | } | |
211 | ||
42dcedd4 CW |
212 | void *i915_gem_object_alloc(struct drm_device *dev) |
213 | { | |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 215 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
216 | } |
217 | ||
218 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
219 | { | |
220 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
221 | kmem_cache_free(dev_priv->slab, obj); | |
222 | } | |
223 | ||
ff72145b DA |
224 | static int |
225 | i915_gem_create(struct drm_file *file, | |
226 | struct drm_device *dev, | |
227 | uint64_t size, | |
228 | uint32_t *handle_p) | |
673a394b | 229 | { |
05394f39 | 230 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
231 | int ret; |
232 | u32 handle; | |
673a394b | 233 | |
ff72145b | 234 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
235 | if (size == 0) |
236 | return -EINVAL; | |
673a394b EA |
237 | |
238 | /* Allocate the new object */ | |
ff72145b | 239 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
240 | if (obj == NULL) |
241 | return -ENOMEM; | |
242 | ||
05394f39 | 243 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 244 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
245 | drm_gem_object_unreference_unlocked(&obj->base); |
246 | if (ret) | |
247 | return ret; | |
202f2fef | 248 | |
ff72145b | 249 | *handle_p = handle; |
673a394b EA |
250 | return 0; |
251 | } | |
252 | ||
ff72145b DA |
253 | int |
254 | i915_gem_dumb_create(struct drm_file *file, | |
255 | struct drm_device *dev, | |
256 | struct drm_mode_create_dumb *args) | |
257 | { | |
258 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 259 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
260 | args->size = args->pitch * args->height; |
261 | return i915_gem_create(file, dev, | |
262 | args->size, &args->handle); | |
263 | } | |
264 | ||
ff72145b DA |
265 | /** |
266 | * Creates a new mm object and returns a handle to it. | |
267 | */ | |
268 | int | |
269 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
270 | struct drm_file *file) | |
271 | { | |
272 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 273 | |
ff72145b DA |
274 | return i915_gem_create(file, dev, |
275 | args->size, &args->handle); | |
276 | } | |
277 | ||
8461d226 DV |
278 | static inline int |
279 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
280 | const char *gpu_vaddr, int gpu_offset, | |
281 | int length) | |
282 | { | |
283 | int ret, cpu_offset = 0; | |
284 | ||
285 | while (length > 0) { | |
286 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
287 | int this_length = min(cacheline_end - gpu_offset, length); | |
288 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
289 | ||
290 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
291 | gpu_vaddr + swizzled_gpu_offset, | |
292 | this_length); | |
293 | if (ret) | |
294 | return ret + length; | |
295 | ||
296 | cpu_offset += this_length; | |
297 | gpu_offset += this_length; | |
298 | length -= this_length; | |
299 | } | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
8c59967c | 304 | static inline int |
4f0c7cfb BW |
305 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
306 | const char __user *cpu_vaddr, | |
8c59967c DV |
307 | int length) |
308 | { | |
309 | int ret, cpu_offset = 0; | |
310 | ||
311 | while (length > 0) { | |
312 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
313 | int this_length = min(cacheline_end - gpu_offset, length); | |
314 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
315 | ||
316 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
317 | cpu_vaddr + cpu_offset, | |
318 | this_length); | |
319 | if (ret) | |
320 | return ret + length; | |
321 | ||
322 | cpu_offset += this_length; | |
323 | gpu_offset += this_length; | |
324 | length -= this_length; | |
325 | } | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
4c914c0c BV |
330 | /* |
331 | * Pins the specified object's pages and synchronizes the object with | |
332 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
333 | * flush the object from the CPU cache. | |
334 | */ | |
335 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
336 | int *needs_clflush) | |
337 | { | |
338 | int ret; | |
339 | ||
340 | *needs_clflush = 0; | |
341 | ||
342 | if (!obj->base.filp) | |
343 | return -EINVAL; | |
344 | ||
345 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
346 | /* If we're not in the cpu read domain, set ourself into the gtt | |
347 | * read domain and manually flush cachelines (if required). This | |
348 | * optimizes for the case when the gpu will dirty the data | |
349 | * anyway again before the next pread happens. */ | |
350 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
351 | obj->cache_level); | |
352 | ret = i915_gem_object_wait_rendering(obj, true); | |
353 | if (ret) | |
354 | return ret; | |
355 | } | |
356 | ||
357 | ret = i915_gem_object_get_pages(obj); | |
358 | if (ret) | |
359 | return ret; | |
360 | ||
361 | i915_gem_object_pin_pages(obj); | |
362 | ||
363 | return ret; | |
364 | } | |
365 | ||
d174bd64 DV |
366 | /* Per-page copy function for the shmem pread fastpath. |
367 | * Flushes invalid cachelines before reading the target if | |
368 | * needs_clflush is set. */ | |
eb01459f | 369 | static int |
d174bd64 DV |
370 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
371 | char __user *user_data, | |
372 | bool page_do_bit17_swizzling, bool needs_clflush) | |
373 | { | |
374 | char *vaddr; | |
375 | int ret; | |
376 | ||
e7e58eb5 | 377 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
378 | return -EINVAL; |
379 | ||
380 | vaddr = kmap_atomic(page); | |
381 | if (needs_clflush) | |
382 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
383 | page_length); | |
384 | ret = __copy_to_user_inatomic(user_data, | |
385 | vaddr + shmem_page_offset, | |
386 | page_length); | |
387 | kunmap_atomic(vaddr); | |
388 | ||
f60d7f0c | 389 | return ret ? -EFAULT : 0; |
d174bd64 DV |
390 | } |
391 | ||
23c18c71 DV |
392 | static void |
393 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
394 | bool swizzled) | |
395 | { | |
e7e58eb5 | 396 | if (unlikely(swizzled)) { |
23c18c71 DV |
397 | unsigned long start = (unsigned long) addr; |
398 | unsigned long end = (unsigned long) addr + length; | |
399 | ||
400 | /* For swizzling simply ensure that we always flush both | |
401 | * channels. Lame, but simple and it works. Swizzled | |
402 | * pwrite/pread is far from a hotpath - current userspace | |
403 | * doesn't use it at all. */ | |
404 | start = round_down(start, 128); | |
405 | end = round_up(end, 128); | |
406 | ||
407 | drm_clflush_virt_range((void *)start, end - start); | |
408 | } else { | |
409 | drm_clflush_virt_range(addr, length); | |
410 | } | |
411 | ||
412 | } | |
413 | ||
d174bd64 DV |
414 | /* Only difference to the fast-path function is that this can handle bit17 |
415 | * and uses non-atomic copy and kmap functions. */ | |
416 | static int | |
417 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
418 | char __user *user_data, | |
419 | bool page_do_bit17_swizzling, bool needs_clflush) | |
420 | { | |
421 | char *vaddr; | |
422 | int ret; | |
423 | ||
424 | vaddr = kmap(page); | |
425 | if (needs_clflush) | |
23c18c71 DV |
426 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
427 | page_length, | |
428 | page_do_bit17_swizzling); | |
d174bd64 DV |
429 | |
430 | if (page_do_bit17_swizzling) | |
431 | ret = __copy_to_user_swizzled(user_data, | |
432 | vaddr, shmem_page_offset, | |
433 | page_length); | |
434 | else | |
435 | ret = __copy_to_user(user_data, | |
436 | vaddr + shmem_page_offset, | |
437 | page_length); | |
438 | kunmap(page); | |
439 | ||
f60d7f0c | 440 | return ret ? - EFAULT : 0; |
d174bd64 DV |
441 | } |
442 | ||
eb01459f | 443 | static int |
dbf7bff0 DV |
444 | i915_gem_shmem_pread(struct drm_device *dev, |
445 | struct drm_i915_gem_object *obj, | |
446 | struct drm_i915_gem_pread *args, | |
447 | struct drm_file *file) | |
eb01459f | 448 | { |
8461d226 | 449 | char __user *user_data; |
eb01459f | 450 | ssize_t remain; |
8461d226 | 451 | loff_t offset; |
eb2c0c81 | 452 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 453 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 454 | int prefaulted = 0; |
8489731c | 455 | int needs_clflush = 0; |
67d5a50c | 456 | struct sg_page_iter sg_iter; |
eb01459f | 457 | |
2bb4629a | 458 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
459 | remain = args->size; |
460 | ||
8461d226 | 461 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 462 | |
4c914c0c | 463 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
464 | if (ret) |
465 | return ret; | |
466 | ||
8461d226 | 467 | offset = args->offset; |
eb01459f | 468 | |
67d5a50c ID |
469 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
470 | offset >> PAGE_SHIFT) { | |
2db76d7c | 471 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
472 | |
473 | if (remain <= 0) | |
474 | break; | |
475 | ||
eb01459f EA |
476 | /* Operation in this page |
477 | * | |
eb01459f | 478 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
479 | * page_length = bytes to copy for this page |
480 | */ | |
c8cbbb8b | 481 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
482 | page_length = remain; |
483 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
484 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 485 | |
8461d226 DV |
486 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
487 | (page_to_phys(page) & (1 << 17)) != 0; | |
488 | ||
d174bd64 DV |
489 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
490 | user_data, page_do_bit17_swizzling, | |
491 | needs_clflush); | |
492 | if (ret == 0) | |
493 | goto next_page; | |
dbf7bff0 | 494 | |
dbf7bff0 DV |
495 | mutex_unlock(&dev->struct_mutex); |
496 | ||
d330a953 | 497 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 498 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
499 | /* Userspace is tricking us, but we've already clobbered |
500 | * its pages with the prefault and promised to write the | |
501 | * data up to the first fault. Hence ignore any errors | |
502 | * and just continue. */ | |
503 | (void)ret; | |
504 | prefaulted = 1; | |
505 | } | |
eb01459f | 506 | |
d174bd64 DV |
507 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
508 | user_data, page_do_bit17_swizzling, | |
509 | needs_clflush); | |
eb01459f | 510 | |
dbf7bff0 | 511 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 512 | |
f60d7f0c | 513 | if (ret) |
8461d226 | 514 | goto out; |
8461d226 | 515 | |
17793c9a | 516 | next_page: |
eb01459f | 517 | remain -= page_length; |
8461d226 | 518 | user_data += page_length; |
eb01459f EA |
519 | offset += page_length; |
520 | } | |
521 | ||
4f27b75d | 522 | out: |
f60d7f0c CW |
523 | i915_gem_object_unpin_pages(obj); |
524 | ||
eb01459f EA |
525 | return ret; |
526 | } | |
527 | ||
673a394b EA |
528 | /** |
529 | * Reads data from the object referenced by handle. | |
530 | * | |
531 | * On error, the contents of *data are undefined. | |
532 | */ | |
533 | int | |
534 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 535 | struct drm_file *file) |
673a394b EA |
536 | { |
537 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 538 | struct drm_i915_gem_object *obj; |
35b62a89 | 539 | int ret = 0; |
673a394b | 540 | |
51311d0a CW |
541 | if (args->size == 0) |
542 | return 0; | |
543 | ||
544 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 545 | to_user_ptr(args->data_ptr), |
51311d0a CW |
546 | args->size)) |
547 | return -EFAULT; | |
548 | ||
4f27b75d | 549 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 550 | if (ret) |
4f27b75d | 551 | return ret; |
673a394b | 552 | |
05394f39 | 553 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 554 | if (&obj->base == NULL) { |
1d7cfea1 CW |
555 | ret = -ENOENT; |
556 | goto unlock; | |
4f27b75d | 557 | } |
673a394b | 558 | |
7dcd2499 | 559 | /* Bounds check source. */ |
05394f39 CW |
560 | if (args->offset > obj->base.size || |
561 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 562 | ret = -EINVAL; |
35b62a89 | 563 | goto out; |
ce9d419d CW |
564 | } |
565 | ||
1286ff73 DV |
566 | /* prime objects have no backing filp to GEM pread/pwrite |
567 | * pages from. | |
568 | */ | |
569 | if (!obj->base.filp) { | |
570 | ret = -EINVAL; | |
571 | goto out; | |
572 | } | |
573 | ||
db53a302 CW |
574 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
575 | ||
dbf7bff0 | 576 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 577 | |
35b62a89 | 578 | out: |
05394f39 | 579 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 580 | unlock: |
4f27b75d | 581 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 582 | return ret; |
673a394b EA |
583 | } |
584 | ||
0839ccb8 KP |
585 | /* This is the fast write path which cannot handle |
586 | * page faults in the source data | |
9b7530cc | 587 | */ |
0839ccb8 KP |
588 | |
589 | static inline int | |
590 | fast_user_write(struct io_mapping *mapping, | |
591 | loff_t page_base, int page_offset, | |
592 | char __user *user_data, | |
593 | int length) | |
9b7530cc | 594 | { |
4f0c7cfb BW |
595 | void __iomem *vaddr_atomic; |
596 | void *vaddr; | |
0839ccb8 | 597 | unsigned long unwritten; |
9b7530cc | 598 | |
3e4d3af5 | 599 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
600 | /* We can use the cpu mem copy function because this is X86. */ |
601 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
602 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 603 | user_data, length); |
3e4d3af5 | 604 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 605 | return unwritten; |
0839ccb8 KP |
606 | } |
607 | ||
3de09aa3 EA |
608 | /** |
609 | * This is the fast pwrite path, where we copy the data directly from the | |
610 | * user into the GTT, uncached. | |
611 | */ | |
673a394b | 612 | static int |
05394f39 CW |
613 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
614 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 615 | struct drm_i915_gem_pwrite *args, |
05394f39 | 616 | struct drm_file *file) |
673a394b | 617 | { |
3e31c6c0 | 618 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 619 | ssize_t remain; |
0839ccb8 | 620 | loff_t offset, page_base; |
673a394b | 621 | char __user *user_data; |
935aaa69 DV |
622 | int page_offset, page_length, ret; |
623 | ||
1ec9e26d | 624 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
625 | if (ret) |
626 | goto out; | |
627 | ||
628 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
629 | if (ret) | |
630 | goto out_unpin; | |
631 | ||
632 | ret = i915_gem_object_put_fence(obj); | |
633 | if (ret) | |
634 | goto out_unpin; | |
673a394b | 635 | |
2bb4629a | 636 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 637 | remain = args->size; |
673a394b | 638 | |
f343c5f6 | 639 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
640 | |
641 | while (remain > 0) { | |
642 | /* Operation in this page | |
643 | * | |
0839ccb8 KP |
644 | * page_base = page offset within aperture |
645 | * page_offset = offset within page | |
646 | * page_length = bytes to copy for this page | |
673a394b | 647 | */ |
c8cbbb8b CW |
648 | page_base = offset & PAGE_MASK; |
649 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
650 | page_length = remain; |
651 | if ((page_offset + remain) > PAGE_SIZE) | |
652 | page_length = PAGE_SIZE - page_offset; | |
653 | ||
0839ccb8 | 654 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
655 | * source page isn't available. Return the error and we'll |
656 | * retry in the slow path. | |
0839ccb8 | 657 | */ |
5d4545ae | 658 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
659 | page_offset, user_data, page_length)) { |
660 | ret = -EFAULT; | |
661 | goto out_unpin; | |
662 | } | |
673a394b | 663 | |
0839ccb8 KP |
664 | remain -= page_length; |
665 | user_data += page_length; | |
666 | offset += page_length; | |
673a394b | 667 | } |
673a394b | 668 | |
935aaa69 | 669 | out_unpin: |
d7f46fc4 | 670 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 671 | out: |
3de09aa3 | 672 | return ret; |
673a394b EA |
673 | } |
674 | ||
d174bd64 DV |
675 | /* Per-page copy function for the shmem pwrite fastpath. |
676 | * Flushes invalid cachelines before writing to the target if | |
677 | * needs_clflush_before is set and flushes out any written cachelines after | |
678 | * writing if needs_clflush is set. */ | |
3043c60c | 679 | static int |
d174bd64 DV |
680 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
681 | char __user *user_data, | |
682 | bool page_do_bit17_swizzling, | |
683 | bool needs_clflush_before, | |
684 | bool needs_clflush_after) | |
673a394b | 685 | { |
d174bd64 | 686 | char *vaddr; |
673a394b | 687 | int ret; |
3de09aa3 | 688 | |
e7e58eb5 | 689 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 690 | return -EINVAL; |
3de09aa3 | 691 | |
d174bd64 DV |
692 | vaddr = kmap_atomic(page); |
693 | if (needs_clflush_before) | |
694 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
695 | page_length); | |
c2831a94 CW |
696 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
697 | user_data, page_length); | |
d174bd64 DV |
698 | if (needs_clflush_after) |
699 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
700 | page_length); | |
701 | kunmap_atomic(vaddr); | |
3de09aa3 | 702 | |
755d2218 | 703 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
704 | } |
705 | ||
d174bd64 DV |
706 | /* Only difference to the fast-path function is that this can handle bit17 |
707 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 708 | static int |
d174bd64 DV |
709 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
710 | char __user *user_data, | |
711 | bool page_do_bit17_swizzling, | |
712 | bool needs_clflush_before, | |
713 | bool needs_clflush_after) | |
673a394b | 714 | { |
d174bd64 DV |
715 | char *vaddr; |
716 | int ret; | |
e5281ccd | 717 | |
d174bd64 | 718 | vaddr = kmap(page); |
e7e58eb5 | 719 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
720 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
721 | page_length, | |
722 | page_do_bit17_swizzling); | |
d174bd64 DV |
723 | if (page_do_bit17_swizzling) |
724 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
725 | user_data, |
726 | page_length); | |
d174bd64 DV |
727 | else |
728 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
729 | user_data, | |
730 | page_length); | |
731 | if (needs_clflush_after) | |
23c18c71 DV |
732 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
733 | page_length, | |
734 | page_do_bit17_swizzling); | |
d174bd64 | 735 | kunmap(page); |
40123c1f | 736 | |
755d2218 | 737 | return ret ? -EFAULT : 0; |
40123c1f EA |
738 | } |
739 | ||
40123c1f | 740 | static int |
e244a443 DV |
741 | i915_gem_shmem_pwrite(struct drm_device *dev, |
742 | struct drm_i915_gem_object *obj, | |
743 | struct drm_i915_gem_pwrite *args, | |
744 | struct drm_file *file) | |
40123c1f | 745 | { |
40123c1f | 746 | ssize_t remain; |
8c59967c DV |
747 | loff_t offset; |
748 | char __user *user_data; | |
eb2c0c81 | 749 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 750 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 751 | int hit_slowpath = 0; |
58642885 DV |
752 | int needs_clflush_after = 0; |
753 | int needs_clflush_before = 0; | |
67d5a50c | 754 | struct sg_page_iter sg_iter; |
40123c1f | 755 | |
2bb4629a | 756 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
757 | remain = args->size; |
758 | ||
8c59967c | 759 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 760 | |
58642885 DV |
761 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
762 | /* If we're not in the cpu write domain, set ourself into the gtt | |
763 | * write domain and manually flush cachelines (if required). This | |
764 | * optimizes for the case when the gpu will use the data | |
765 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 766 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
767 | ret = i915_gem_object_wait_rendering(obj, false); |
768 | if (ret) | |
769 | return ret; | |
58642885 | 770 | } |
c76ce038 CW |
771 | /* Same trick applies to invalidate partially written cachelines read |
772 | * before writing. */ | |
773 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
774 | needs_clflush_before = | |
775 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 776 | |
755d2218 CW |
777 | ret = i915_gem_object_get_pages(obj); |
778 | if (ret) | |
779 | return ret; | |
780 | ||
781 | i915_gem_object_pin_pages(obj); | |
782 | ||
673a394b | 783 | offset = args->offset; |
05394f39 | 784 | obj->dirty = 1; |
673a394b | 785 | |
67d5a50c ID |
786 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
787 | offset >> PAGE_SHIFT) { | |
2db76d7c | 788 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 789 | int partial_cacheline_write; |
e5281ccd | 790 | |
9da3da66 CW |
791 | if (remain <= 0) |
792 | break; | |
793 | ||
40123c1f EA |
794 | /* Operation in this page |
795 | * | |
40123c1f | 796 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
797 | * page_length = bytes to copy for this page |
798 | */ | |
c8cbbb8b | 799 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
800 | |
801 | page_length = remain; | |
802 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
803 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 804 | |
58642885 DV |
805 | /* If we don't overwrite a cacheline completely we need to be |
806 | * careful to have up-to-date data by first clflushing. Don't | |
807 | * overcomplicate things and flush the entire patch. */ | |
808 | partial_cacheline_write = needs_clflush_before && | |
809 | ((shmem_page_offset | page_length) | |
810 | & (boot_cpu_data.x86_clflush_size - 1)); | |
811 | ||
8c59967c DV |
812 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
813 | (page_to_phys(page) & (1 << 17)) != 0; | |
814 | ||
d174bd64 DV |
815 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
816 | user_data, page_do_bit17_swizzling, | |
817 | partial_cacheline_write, | |
818 | needs_clflush_after); | |
819 | if (ret == 0) | |
820 | goto next_page; | |
e244a443 DV |
821 | |
822 | hit_slowpath = 1; | |
e244a443 | 823 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
824 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
825 | user_data, page_do_bit17_swizzling, | |
826 | partial_cacheline_write, | |
827 | needs_clflush_after); | |
40123c1f | 828 | |
e244a443 | 829 | mutex_lock(&dev->struct_mutex); |
755d2218 | 830 | |
755d2218 | 831 | if (ret) |
8c59967c | 832 | goto out; |
8c59967c | 833 | |
17793c9a | 834 | next_page: |
40123c1f | 835 | remain -= page_length; |
8c59967c | 836 | user_data += page_length; |
40123c1f | 837 | offset += page_length; |
673a394b EA |
838 | } |
839 | ||
fbd5a26d | 840 | out: |
755d2218 CW |
841 | i915_gem_object_unpin_pages(obj); |
842 | ||
e244a443 | 843 | if (hit_slowpath) { |
8dcf015e DV |
844 | /* |
845 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
846 | * cachelines in-line while writing and the object moved | |
847 | * out of the cpu write domain while we've dropped the lock. | |
848 | */ | |
849 | if (!needs_clflush_after && | |
850 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
851 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
852 | i915_gem_chipset_flush(dev); | |
e244a443 | 853 | } |
8c59967c | 854 | } |
673a394b | 855 | |
58642885 | 856 | if (needs_clflush_after) |
e76e9aeb | 857 | i915_gem_chipset_flush(dev); |
58642885 | 858 | |
40123c1f | 859 | return ret; |
673a394b EA |
860 | } |
861 | ||
862 | /** | |
863 | * Writes data to the object referenced by handle. | |
864 | * | |
865 | * On error, the contents of the buffer that were to be modified are undefined. | |
866 | */ | |
867 | int | |
868 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 869 | struct drm_file *file) |
673a394b EA |
870 | { |
871 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 872 | struct drm_i915_gem_object *obj; |
51311d0a CW |
873 | int ret; |
874 | ||
875 | if (args->size == 0) | |
876 | return 0; | |
877 | ||
878 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 879 | to_user_ptr(args->data_ptr), |
51311d0a CW |
880 | args->size)) |
881 | return -EFAULT; | |
882 | ||
d330a953 | 883 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
884 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
885 | args->size); | |
886 | if (ret) | |
887 | return -EFAULT; | |
888 | } | |
673a394b | 889 | |
fbd5a26d | 890 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 891 | if (ret) |
fbd5a26d | 892 | return ret; |
1d7cfea1 | 893 | |
05394f39 | 894 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 895 | if (&obj->base == NULL) { |
1d7cfea1 CW |
896 | ret = -ENOENT; |
897 | goto unlock; | |
fbd5a26d | 898 | } |
673a394b | 899 | |
7dcd2499 | 900 | /* Bounds check destination. */ |
05394f39 CW |
901 | if (args->offset > obj->base.size || |
902 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 903 | ret = -EINVAL; |
35b62a89 | 904 | goto out; |
ce9d419d CW |
905 | } |
906 | ||
1286ff73 DV |
907 | /* prime objects have no backing filp to GEM pread/pwrite |
908 | * pages from. | |
909 | */ | |
910 | if (!obj->base.filp) { | |
911 | ret = -EINVAL; | |
912 | goto out; | |
913 | } | |
914 | ||
db53a302 CW |
915 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
916 | ||
935aaa69 | 917 | ret = -EFAULT; |
673a394b EA |
918 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
919 | * it would end up going through the fenced access, and we'll get | |
920 | * different detiling behavior between reading and writing. | |
921 | * pread/pwrite currently are reading and writing from the CPU | |
922 | * perspective, requiring manual detiling by the client. | |
923 | */ | |
5c0480f2 | 924 | if (obj->phys_obj) { |
fbd5a26d | 925 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
926 | goto out; |
927 | } | |
928 | ||
2c22569b CW |
929 | if (obj->tiling_mode == I915_TILING_NONE && |
930 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
931 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 932 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
933 | /* Note that the gtt paths might fail with non-page-backed user |
934 | * pointers (e.g. gtt mappings when moving data between | |
935 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 936 | } |
673a394b | 937 | |
86a1ee26 | 938 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 939 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 940 | |
35b62a89 | 941 | out: |
05394f39 | 942 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 943 | unlock: |
fbd5a26d | 944 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
945 | return ret; |
946 | } | |
947 | ||
b361237b | 948 | int |
33196ded | 949 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
950 | bool interruptible) |
951 | { | |
1f83fee0 | 952 | if (i915_reset_in_progress(error)) { |
b361237b CW |
953 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
954 | * -EIO unconditionally for these. */ | |
955 | if (!interruptible) | |
956 | return -EIO; | |
957 | ||
1f83fee0 DV |
958 | /* Recovery complete, but the reset failed ... */ |
959 | if (i915_terminally_wedged(error)) | |
b361237b CW |
960 | return -EIO; |
961 | ||
962 | return -EAGAIN; | |
963 | } | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | /* | |
969 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
970 | * equal. | |
971 | */ | |
972 | static int | |
973 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
974 | { | |
975 | int ret; | |
976 | ||
977 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
978 | ||
979 | ret = 0; | |
1823521d | 980 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 981 | ret = i915_add_request(ring, NULL); |
b361237b CW |
982 | |
983 | return ret; | |
984 | } | |
985 | ||
094f9a54 CW |
986 | static void fake_irq(unsigned long data) |
987 | { | |
988 | wake_up_process((struct task_struct *)data); | |
989 | } | |
990 | ||
991 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
992 | struct intel_ring_buffer *ring) | |
993 | { | |
994 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
995 | } | |
996 | ||
b29c19b6 CW |
997 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
998 | { | |
999 | if (file_priv == NULL) | |
1000 | return true; | |
1001 | ||
1002 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1003 | } | |
1004 | ||
b361237b CW |
1005 | /** |
1006 | * __wait_seqno - wait until execution of seqno has finished | |
1007 | * @ring: the ring expected to report seqno | |
1008 | * @seqno: duh! | |
f69061be | 1009 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
1010 | * @interruptible: do an interruptible wait (normally yes) |
1011 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1012 | * | |
f69061be DV |
1013 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1014 | * values have been read by the caller in an smp safe manner. Where read-side | |
1015 | * locks are involved, it is sufficient to read the reset_counter before | |
1016 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1017 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1018 | * inserted. | |
1019 | * | |
b361237b CW |
1020 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1021 | * errno with remaining time filled in timeout argument. | |
1022 | */ | |
1023 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 1024 | unsigned reset_counter, |
b29c19b6 CW |
1025 | bool interruptible, |
1026 | struct timespec *timeout, | |
1027 | struct drm_i915_file_private *file_priv) | |
b361237b | 1028 | { |
3d13ef2e | 1029 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1030 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1031 | const bool irq_test_in_progress = |
1032 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 CW |
1033 | struct timespec before, now; |
1034 | DEFINE_WAIT(wait); | |
47e9766d | 1035 | unsigned long timeout_expire; |
b361237b CW |
1036 | int ret; |
1037 | ||
5d584b2e | 1038 | WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n"); |
c67a470b | 1039 | |
b361237b CW |
1040 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1041 | return 0; | |
1042 | ||
47e9766d | 1043 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
b361237b | 1044 | |
3d13ef2e | 1045 | if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1046 | gen6_rps_boost(dev_priv); |
1047 | if (file_priv) | |
1048 | mod_delayed_work(dev_priv->wq, | |
1049 | &file_priv->mm.idle_work, | |
1050 | msecs_to_jiffies(100)); | |
1051 | } | |
1052 | ||
168c3f21 | 1053 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1054 | return -ENODEV; |
1055 | ||
094f9a54 CW |
1056 | /* Record current time in case interrupted by signal, or wedged */ |
1057 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1058 | getrawmonotonic(&before); |
094f9a54 CW |
1059 | for (;;) { |
1060 | struct timer_list timer; | |
b361237b | 1061 | |
094f9a54 CW |
1062 | prepare_to_wait(&ring->irq_queue, &wait, |
1063 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1064 | |
f69061be DV |
1065 | /* We need to check whether any gpu reset happened in between |
1066 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1067 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1068 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1069 | * is truely gone. */ | |
1070 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1071 | if (ret == 0) | |
1072 | ret = -EAGAIN; | |
1073 | break; | |
1074 | } | |
f69061be | 1075 | |
094f9a54 CW |
1076 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1077 | ret = 0; | |
1078 | break; | |
1079 | } | |
b361237b | 1080 | |
094f9a54 CW |
1081 | if (interruptible && signal_pending(current)) { |
1082 | ret = -ERESTARTSYS; | |
1083 | break; | |
1084 | } | |
1085 | ||
47e9766d | 1086 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1087 | ret = -ETIME; |
1088 | break; | |
1089 | } | |
1090 | ||
1091 | timer.function = NULL; | |
1092 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1093 | unsigned long expire; |
1094 | ||
094f9a54 | 1095 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1096 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1097 | mod_timer(&timer, expire); |
1098 | } | |
1099 | ||
5035c275 | 1100 | io_schedule(); |
094f9a54 | 1101 | |
094f9a54 CW |
1102 | if (timer.function) { |
1103 | del_singleshot_timer_sync(&timer); | |
1104 | destroy_timer_on_stack(&timer); | |
1105 | } | |
1106 | } | |
b361237b | 1107 | getrawmonotonic(&now); |
094f9a54 | 1108 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1109 | |
168c3f21 MK |
1110 | if (!irq_test_in_progress) |
1111 | ring->irq_put(ring); | |
094f9a54 CW |
1112 | |
1113 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1114 | |
1115 | if (timeout) { | |
1116 | struct timespec sleep_time = timespec_sub(now, before); | |
1117 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1118 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1119 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1120 | } |
1121 | ||
094f9a54 | 1122 | return ret; |
b361237b CW |
1123 | } |
1124 | ||
1125 | /** | |
1126 | * Waits for a sequence number to be signaled, and cleans up the | |
1127 | * request and object lists appropriately for that event. | |
1128 | */ | |
1129 | int | |
1130 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1131 | { | |
1132 | struct drm_device *dev = ring->dev; | |
1133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1134 | bool interruptible = dev_priv->mm.interruptible; | |
1135 | int ret; | |
1136 | ||
1137 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1138 | BUG_ON(seqno == 0); | |
1139 | ||
33196ded | 1140 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1141 | if (ret) |
1142 | return ret; | |
1143 | ||
1144 | ret = i915_gem_check_olr(ring, seqno); | |
1145 | if (ret) | |
1146 | return ret; | |
1147 | ||
f69061be DV |
1148 | return __wait_seqno(ring, seqno, |
1149 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1150 | interruptible, NULL, NULL); |
b361237b CW |
1151 | } |
1152 | ||
d26e3af8 CW |
1153 | static int |
1154 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1155 | struct intel_ring_buffer *ring) | |
1156 | { | |
1157 | i915_gem_retire_requests_ring(ring); | |
1158 | ||
1159 | /* Manually manage the write flush as we may have not yet | |
1160 | * retired the buffer. | |
1161 | * | |
1162 | * Note that the last_write_seqno is always the earlier of | |
1163 | * the two (read/write) seqno, so if we haved successfully waited, | |
1164 | * we know we have passed the last write. | |
1165 | */ | |
1166 | obj->last_write_seqno = 0; | |
1167 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1168 | ||
1169 | return 0; | |
1170 | } | |
1171 | ||
b361237b CW |
1172 | /** |
1173 | * Ensures that all rendering to the object has completed and the object is | |
1174 | * safe to unbind from the GTT or access from the CPU. | |
1175 | */ | |
1176 | static __must_check int | |
1177 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1178 | bool readonly) | |
1179 | { | |
1180 | struct intel_ring_buffer *ring = obj->ring; | |
1181 | u32 seqno; | |
1182 | int ret; | |
1183 | ||
1184 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1185 | if (seqno == 0) | |
1186 | return 0; | |
1187 | ||
1188 | ret = i915_wait_seqno(ring, seqno); | |
1189 | if (ret) | |
1190 | return ret; | |
1191 | ||
d26e3af8 | 1192 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1193 | } |
1194 | ||
3236f57a CW |
1195 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1196 | * as the object state may change during this call. | |
1197 | */ | |
1198 | static __must_check int | |
1199 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1200 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1201 | bool readonly) |
1202 | { | |
1203 | struct drm_device *dev = obj->base.dev; | |
1204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1205 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1206 | unsigned reset_counter; |
3236f57a CW |
1207 | u32 seqno; |
1208 | int ret; | |
1209 | ||
1210 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1211 | BUG_ON(!dev_priv->mm.interruptible); | |
1212 | ||
1213 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1214 | if (seqno == 0) | |
1215 | return 0; | |
1216 | ||
33196ded | 1217 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1218 | if (ret) |
1219 | return ret; | |
1220 | ||
1221 | ret = i915_gem_check_olr(ring, seqno); | |
1222 | if (ret) | |
1223 | return ret; | |
1224 | ||
f69061be | 1225 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1226 | mutex_unlock(&dev->struct_mutex); |
6e4930f6 | 1227 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
3236f57a | 1228 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1229 | if (ret) |
1230 | return ret; | |
3236f57a | 1231 | |
d26e3af8 | 1232 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1233 | } |
1234 | ||
673a394b | 1235 | /** |
2ef7eeaa EA |
1236 | * Called when user space prepares to use an object with the CPU, either |
1237 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1238 | */ |
1239 | int | |
1240 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1241 | struct drm_file *file) |
673a394b EA |
1242 | { |
1243 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1244 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1245 | uint32_t read_domains = args->read_domains; |
1246 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1247 | int ret; |
1248 | ||
2ef7eeaa | 1249 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1250 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1251 | return -EINVAL; |
1252 | ||
21d509e3 | 1253 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1254 | return -EINVAL; |
1255 | ||
1256 | /* Having something in the write domain implies it's in the read | |
1257 | * domain, and only that read domain. Enforce that in the request. | |
1258 | */ | |
1259 | if (write_domain != 0 && read_domains != write_domain) | |
1260 | return -EINVAL; | |
1261 | ||
76c1dec1 | 1262 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1263 | if (ret) |
76c1dec1 | 1264 | return ret; |
1d7cfea1 | 1265 | |
05394f39 | 1266 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1267 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1268 | ret = -ENOENT; |
1269 | goto unlock; | |
76c1dec1 | 1270 | } |
673a394b | 1271 | |
3236f57a CW |
1272 | /* Try to flush the object off the GPU without holding the lock. |
1273 | * We will repeat the flush holding the lock in the normal manner | |
1274 | * to catch cases where we are gazumped. | |
1275 | */ | |
6e4930f6 CW |
1276 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1277 | file->driver_priv, | |
1278 | !write_domain); | |
3236f57a CW |
1279 | if (ret) |
1280 | goto unref; | |
1281 | ||
2ef7eeaa EA |
1282 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1283 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1284 | |
1285 | /* Silently promote "you're not bound, there was nothing to do" | |
1286 | * to success, since the client was just asking us to | |
1287 | * make sure everything was done. | |
1288 | */ | |
1289 | if (ret == -EINVAL) | |
1290 | ret = 0; | |
2ef7eeaa | 1291 | } else { |
e47c68e9 | 1292 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1293 | } |
1294 | ||
3236f57a | 1295 | unref: |
05394f39 | 1296 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1297 | unlock: |
673a394b EA |
1298 | mutex_unlock(&dev->struct_mutex); |
1299 | return ret; | |
1300 | } | |
1301 | ||
1302 | /** | |
1303 | * Called when user space has done writes to this buffer | |
1304 | */ | |
1305 | int | |
1306 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1307 | struct drm_file *file) |
673a394b EA |
1308 | { |
1309 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1310 | struct drm_i915_gem_object *obj; |
673a394b EA |
1311 | int ret = 0; |
1312 | ||
76c1dec1 | 1313 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1314 | if (ret) |
76c1dec1 | 1315 | return ret; |
1d7cfea1 | 1316 | |
05394f39 | 1317 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1318 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1319 | ret = -ENOENT; |
1320 | goto unlock; | |
673a394b EA |
1321 | } |
1322 | ||
673a394b | 1323 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1324 | if (obj->pin_display) |
1325 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1326 | |
05394f39 | 1327 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1328 | unlock: |
673a394b EA |
1329 | mutex_unlock(&dev->struct_mutex); |
1330 | return ret; | |
1331 | } | |
1332 | ||
1333 | /** | |
1334 | * Maps the contents of an object, returning the address it is mapped | |
1335 | * into. | |
1336 | * | |
1337 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1338 | * imply a ref on the object itself. | |
1339 | */ | |
1340 | int | |
1341 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1342 | struct drm_file *file) |
673a394b EA |
1343 | { |
1344 | struct drm_i915_gem_mmap *args = data; | |
1345 | struct drm_gem_object *obj; | |
673a394b EA |
1346 | unsigned long addr; |
1347 | ||
05394f39 | 1348 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1349 | if (obj == NULL) |
bf79cb91 | 1350 | return -ENOENT; |
673a394b | 1351 | |
1286ff73 DV |
1352 | /* prime objects have no backing filp to GEM mmap |
1353 | * pages from. | |
1354 | */ | |
1355 | if (!obj->filp) { | |
1356 | drm_gem_object_unreference_unlocked(obj); | |
1357 | return -EINVAL; | |
1358 | } | |
1359 | ||
6be5ceb0 | 1360 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1361 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1362 | args->offset); | |
bc9025bd | 1363 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1364 | if (IS_ERR((void *)addr)) |
1365 | return addr; | |
1366 | ||
1367 | args->addr_ptr = (uint64_t) addr; | |
1368 | ||
1369 | return 0; | |
1370 | } | |
1371 | ||
de151cf6 JB |
1372 | /** |
1373 | * i915_gem_fault - fault a page into the GTT | |
1374 | * vma: VMA in question | |
1375 | * vmf: fault info | |
1376 | * | |
1377 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1378 | * from userspace. The fault handler takes care of binding the object to | |
1379 | * the GTT (if needed), allocating and programming a fence register (again, | |
1380 | * only if needed based on whether the old reg is still valid or the object | |
1381 | * is tiled) and inserting a new PTE into the faulting process. | |
1382 | * | |
1383 | * Note that the faulting process may involve evicting existing objects | |
1384 | * from the GTT and/or fence registers to make room. So performance may | |
1385 | * suffer if the GTT working set is large or there are few fence registers | |
1386 | * left. | |
1387 | */ | |
1388 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1389 | { | |
05394f39 CW |
1390 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1391 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1392 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1393 | pgoff_t page_offset; |
1394 | unsigned long pfn; | |
1395 | int ret = 0; | |
0f973f27 | 1396 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1397 | |
f65c9168 PZ |
1398 | intel_runtime_pm_get(dev_priv); |
1399 | ||
de151cf6 JB |
1400 | /* We don't use vmf->pgoff since that has the fake offset */ |
1401 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1402 | PAGE_SHIFT; | |
1403 | ||
d9bc7e9f CW |
1404 | ret = i915_mutex_lock_interruptible(dev); |
1405 | if (ret) | |
1406 | goto out; | |
a00b10c3 | 1407 | |
db53a302 CW |
1408 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1409 | ||
6e4930f6 CW |
1410 | /* Try to flush the object off the GPU first without holding the lock. |
1411 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1412 | * repeat the flush holding the lock in the normal manner to catch cases | |
1413 | * where we are gazumped. | |
1414 | */ | |
1415 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1416 | if (ret) | |
1417 | goto unlock; | |
1418 | ||
eb119bd6 CW |
1419 | /* Access to snoopable pages through the GTT is incoherent. */ |
1420 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1421 | ret = -EINVAL; | |
1422 | goto unlock; | |
1423 | } | |
1424 | ||
d9bc7e9f | 1425 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1426 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1427 | if (ret) |
1428 | goto unlock; | |
4a684a41 | 1429 | |
c9839303 CW |
1430 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1431 | if (ret) | |
1432 | goto unpin; | |
74898d7e | 1433 | |
06d98131 | 1434 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1435 | if (ret) |
c9839303 | 1436 | goto unpin; |
7d1c4804 | 1437 | |
6299f992 CW |
1438 | obj->fault_mappable = true; |
1439 | ||
f343c5f6 BW |
1440 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1441 | pfn >>= PAGE_SHIFT; | |
1442 | pfn += page_offset; | |
de151cf6 JB |
1443 | |
1444 | /* Finally, remap it using the new GTT offset */ | |
1445 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 | 1446 | unpin: |
d7f46fc4 | 1447 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1448 | unlock: |
de151cf6 | 1449 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1450 | out: |
de151cf6 | 1451 | switch (ret) { |
d9bc7e9f | 1452 | case -EIO: |
a9340cca DV |
1453 | /* If this -EIO is due to a gpu hang, give the reset code a |
1454 | * chance to clean up the mess. Otherwise return the proper | |
1455 | * SIGBUS. */ | |
f65c9168 PZ |
1456 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
1457 | ret = VM_FAULT_SIGBUS; | |
1458 | break; | |
1459 | } | |
045e769a | 1460 | case -EAGAIN: |
571c608d DV |
1461 | /* |
1462 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1463 | * handler to reset everything when re-faulting in | |
1464 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1465 | */ |
c715089f CW |
1466 | case 0: |
1467 | case -ERESTARTSYS: | |
bed636ab | 1468 | case -EINTR: |
e79e0fe3 DR |
1469 | case -EBUSY: |
1470 | /* | |
1471 | * EBUSY is ok: this just means that another thread | |
1472 | * already did the job. | |
1473 | */ | |
f65c9168 PZ |
1474 | ret = VM_FAULT_NOPAGE; |
1475 | break; | |
de151cf6 | 1476 | case -ENOMEM: |
f65c9168 PZ |
1477 | ret = VM_FAULT_OOM; |
1478 | break; | |
a7c2e1aa | 1479 | case -ENOSPC: |
45d67817 | 1480 | case -EFAULT: |
f65c9168 PZ |
1481 | ret = VM_FAULT_SIGBUS; |
1482 | break; | |
de151cf6 | 1483 | default: |
a7c2e1aa | 1484 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1485 | ret = VM_FAULT_SIGBUS; |
1486 | break; | |
de151cf6 | 1487 | } |
f65c9168 PZ |
1488 | |
1489 | intel_runtime_pm_put(dev_priv); | |
1490 | return ret; | |
de151cf6 JB |
1491 | } |
1492 | ||
48018a57 PZ |
1493 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
1494 | { | |
1495 | struct i915_vma *vma; | |
1496 | ||
1497 | /* | |
1498 | * Only the global gtt is relevant for gtt memory mappings, so restrict | |
1499 | * list traversal to objects bound into the global address space. Note | |
1500 | * that the active list should be empty, but better safe than sorry. | |
1501 | */ | |
1502 | WARN_ON(!list_empty(&dev_priv->gtt.base.active_list)); | |
1503 | list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list) | |
1504 | i915_gem_release_mmap(vma->obj); | |
1505 | list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list) | |
1506 | i915_gem_release_mmap(vma->obj); | |
1507 | } | |
1508 | ||
901782b2 CW |
1509 | /** |
1510 | * i915_gem_release_mmap - remove physical page mappings | |
1511 | * @obj: obj in question | |
1512 | * | |
af901ca1 | 1513 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1514 | * relinquish ownership of the pages back to the system. |
1515 | * | |
1516 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1517 | * object through the GTT and then lose the fence register due to | |
1518 | * resource pressure. Similarly if the object has been moved out of the | |
1519 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1520 | * mapping will then trigger a page fault on the next user access, allowing | |
1521 | * fixup by i915_gem_fault(). | |
1522 | */ | |
d05ca301 | 1523 | void |
05394f39 | 1524 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1525 | { |
6299f992 CW |
1526 | if (!obj->fault_mappable) |
1527 | return; | |
901782b2 | 1528 | |
6796cb16 DH |
1529 | drm_vma_node_unmap(&obj->base.vma_node, |
1530 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1531 | obj->fault_mappable = false; |
901782b2 CW |
1532 | } |
1533 | ||
0fa87796 | 1534 | uint32_t |
e28f8711 | 1535 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1536 | { |
e28f8711 | 1537 | uint32_t gtt_size; |
92b88aeb CW |
1538 | |
1539 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1540 | tiling_mode == I915_TILING_NONE) |
1541 | return size; | |
92b88aeb CW |
1542 | |
1543 | /* Previous chips need a power-of-two fence region when tiling */ | |
1544 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1545 | gtt_size = 1024*1024; |
92b88aeb | 1546 | else |
e28f8711 | 1547 | gtt_size = 512*1024; |
92b88aeb | 1548 | |
e28f8711 CW |
1549 | while (gtt_size < size) |
1550 | gtt_size <<= 1; | |
92b88aeb | 1551 | |
e28f8711 | 1552 | return gtt_size; |
92b88aeb CW |
1553 | } |
1554 | ||
de151cf6 JB |
1555 | /** |
1556 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1557 | * @obj: object to check | |
1558 | * | |
1559 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1560 | * potential fence register mapping. |
de151cf6 | 1561 | */ |
d865110c ID |
1562 | uint32_t |
1563 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1564 | int tiling_mode, bool fenced) | |
de151cf6 | 1565 | { |
de151cf6 JB |
1566 | /* |
1567 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1568 | * if a fence register is needed for the object. | |
1569 | */ | |
d865110c | 1570 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1571 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1572 | return 4096; |
1573 | ||
a00b10c3 CW |
1574 | /* |
1575 | * Previous chips need to be aligned to the size of the smallest | |
1576 | * fence register that can contain the object. | |
1577 | */ | |
e28f8711 | 1578 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1579 | } |
1580 | ||
d8cb5086 CW |
1581 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1582 | { | |
1583 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1584 | int ret; | |
1585 | ||
0de23977 | 1586 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1587 | return 0; |
1588 | ||
da494d7c DV |
1589 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1590 | ||
d8cb5086 CW |
1591 | ret = drm_gem_create_mmap_offset(&obj->base); |
1592 | if (ret != -ENOSPC) | |
da494d7c | 1593 | goto out; |
d8cb5086 CW |
1594 | |
1595 | /* Badly fragmented mmap space? The only way we can recover | |
1596 | * space is by destroying unwanted objects. We can't randomly release | |
1597 | * mmap_offsets as userspace expects them to be persistent for the | |
1598 | * lifetime of the objects. The closest we can is to release the | |
1599 | * offsets on purgeable objects by truncating it and marking it purged, | |
1600 | * which prevents userspace from ever using that object again. | |
1601 | */ | |
1602 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1603 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1604 | if (ret != -ENOSPC) | |
da494d7c | 1605 | goto out; |
d8cb5086 CW |
1606 | |
1607 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1608 | ret = drm_gem_create_mmap_offset(&obj->base); |
1609 | out: | |
1610 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1611 | ||
1612 | return ret; | |
d8cb5086 CW |
1613 | } |
1614 | ||
1615 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1616 | { | |
d8cb5086 CW |
1617 | drm_gem_free_mmap_offset(&obj->base); |
1618 | } | |
1619 | ||
de151cf6 | 1620 | int |
ff72145b DA |
1621 | i915_gem_mmap_gtt(struct drm_file *file, |
1622 | struct drm_device *dev, | |
1623 | uint32_t handle, | |
1624 | uint64_t *offset) | |
de151cf6 | 1625 | { |
da761a6e | 1626 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1627 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1628 | int ret; |
1629 | ||
76c1dec1 | 1630 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1631 | if (ret) |
76c1dec1 | 1632 | return ret; |
de151cf6 | 1633 | |
ff72145b | 1634 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1635 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1636 | ret = -ENOENT; |
1637 | goto unlock; | |
1638 | } | |
de151cf6 | 1639 | |
5d4545ae | 1640 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1641 | ret = -E2BIG; |
ff56b0bc | 1642 | goto out; |
da761a6e CW |
1643 | } |
1644 | ||
05394f39 | 1645 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1646 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1647 | ret = -EFAULT; |
1d7cfea1 | 1648 | goto out; |
ab18282d CW |
1649 | } |
1650 | ||
d8cb5086 CW |
1651 | ret = i915_gem_object_create_mmap_offset(obj); |
1652 | if (ret) | |
1653 | goto out; | |
de151cf6 | 1654 | |
0de23977 | 1655 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1656 | |
1d7cfea1 | 1657 | out: |
05394f39 | 1658 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1659 | unlock: |
de151cf6 | 1660 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1661 | return ret; |
de151cf6 JB |
1662 | } |
1663 | ||
ff72145b DA |
1664 | /** |
1665 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1666 | * @dev: DRM device | |
1667 | * @data: GTT mapping ioctl data | |
1668 | * @file: GEM object info | |
1669 | * | |
1670 | * Simply returns the fake offset to userspace so it can mmap it. | |
1671 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1672 | * up so we can get faults in the handler above. | |
1673 | * | |
1674 | * The fault handler will take care of binding the object into the GTT | |
1675 | * (since it may have been evicted to make room for something), allocating | |
1676 | * a fence register, and mapping the appropriate aperture address into | |
1677 | * userspace. | |
1678 | */ | |
1679 | int | |
1680 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1681 | struct drm_file *file) | |
1682 | { | |
1683 | struct drm_i915_gem_mmap_gtt *args = data; | |
1684 | ||
ff72145b DA |
1685 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1686 | } | |
1687 | ||
225067ee DV |
1688 | /* Immediately discard the backing storage */ |
1689 | static void | |
1690 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1691 | { |
e5281ccd | 1692 | struct inode *inode; |
e5281ccd | 1693 | |
4d6294bf | 1694 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1695 | |
4d6294bf CW |
1696 | if (obj->base.filp == NULL) |
1697 | return; | |
e5281ccd | 1698 | |
225067ee DV |
1699 | /* Our goal here is to return as much of the memory as |
1700 | * is possible back to the system as we are called from OOM. | |
1701 | * To do this we must instruct the shmfs to drop all of its | |
1702 | * backing pages, *now*. | |
1703 | */ | |
496ad9aa | 1704 | inode = file_inode(obj->base.filp); |
225067ee | 1705 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1706 | |
225067ee DV |
1707 | obj->madv = __I915_MADV_PURGED; |
1708 | } | |
e5281ccd | 1709 | |
225067ee DV |
1710 | static inline int |
1711 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1712 | { | |
1713 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1714 | } |
1715 | ||
5cdf5881 | 1716 | static void |
05394f39 | 1717 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1718 | { |
90797e6d ID |
1719 | struct sg_page_iter sg_iter; |
1720 | int ret; | |
1286ff73 | 1721 | |
05394f39 | 1722 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1723 | |
6c085a72 CW |
1724 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1725 | if (ret) { | |
1726 | /* In the event of a disaster, abandon all caches and | |
1727 | * hope for the best. | |
1728 | */ | |
1729 | WARN_ON(ret != -EIO); | |
2c22569b | 1730 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1731 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1732 | } | |
1733 | ||
6dacfd2f | 1734 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1735 | i915_gem_object_save_bit_17_swizzle(obj); |
1736 | ||
05394f39 CW |
1737 | if (obj->madv == I915_MADV_DONTNEED) |
1738 | obj->dirty = 0; | |
3ef94daa | 1739 | |
90797e6d | 1740 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1741 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1742 | |
05394f39 | 1743 | if (obj->dirty) |
9da3da66 | 1744 | set_page_dirty(page); |
3ef94daa | 1745 | |
05394f39 | 1746 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1747 | mark_page_accessed(page); |
3ef94daa | 1748 | |
9da3da66 | 1749 | page_cache_release(page); |
3ef94daa | 1750 | } |
05394f39 | 1751 | obj->dirty = 0; |
673a394b | 1752 | |
9da3da66 CW |
1753 | sg_free_table(obj->pages); |
1754 | kfree(obj->pages); | |
37e680a1 | 1755 | } |
6c085a72 | 1756 | |
dd624afd | 1757 | int |
37e680a1 CW |
1758 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1759 | { | |
1760 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1761 | ||
2f745ad3 | 1762 | if (obj->pages == NULL) |
37e680a1 CW |
1763 | return 0; |
1764 | ||
a5570178 CW |
1765 | if (obj->pages_pin_count) |
1766 | return -EBUSY; | |
1767 | ||
9843877d | 1768 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1769 | |
a2165e31 CW |
1770 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1771 | * array, hence protect them from being reaped by removing them from gtt | |
1772 | * lists early. */ | |
35c20a60 | 1773 | list_del(&obj->global_list); |
a2165e31 | 1774 | |
37e680a1 | 1775 | ops->put_pages(obj); |
05394f39 | 1776 | obj->pages = NULL; |
37e680a1 | 1777 | |
6c085a72 CW |
1778 | if (i915_gem_object_is_purgeable(obj)) |
1779 | i915_gem_object_truncate(obj); | |
1780 | ||
1781 | return 0; | |
1782 | } | |
1783 | ||
d9973b43 | 1784 | static unsigned long |
93927ca5 DV |
1785 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1786 | bool purgeable_only) | |
6c085a72 | 1787 | { |
57094f82 | 1788 | struct list_head still_bound_list; |
6c085a72 | 1789 | struct drm_i915_gem_object *obj, *next; |
d9973b43 | 1790 | unsigned long count = 0; |
6c085a72 CW |
1791 | |
1792 | list_for_each_entry_safe(obj, next, | |
1793 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1794 | global_list) { |
93927ca5 | 1795 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1796 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1797 | count += obj->base.size >> PAGE_SHIFT; |
1798 | if (count >= target) | |
1799 | return count; | |
1800 | } | |
1801 | } | |
1802 | ||
57094f82 CW |
1803 | /* |
1804 | * As we may completely rewrite the bound list whilst unbinding | |
1805 | * (due to retiring requests) we have to strictly process only | |
1806 | * one element of the list at the time, and recheck the list | |
1807 | * on every iteration. | |
1808 | */ | |
1809 | INIT_LIST_HEAD(&still_bound_list); | |
1810 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { | |
07fe0b12 | 1811 | struct i915_vma *vma, *v; |
80dcfdbd | 1812 | |
57094f82 CW |
1813 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1814 | typeof(*obj), global_list); | |
1815 | list_move_tail(&obj->global_list, &still_bound_list); | |
1816 | ||
80dcfdbd BW |
1817 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1818 | continue; | |
1819 | ||
57094f82 CW |
1820 | /* |
1821 | * Hold a reference whilst we unbind this object, as we may | |
1822 | * end up waiting for and retiring requests. This might | |
1823 | * release the final reference (held by the active list) | |
1824 | * and result in the object being freed from under us. | |
1825 | * in this object being freed. | |
1826 | * | |
1827 | * Note 1: Shrinking the bound list is special since only active | |
1828 | * (and hence bound objects) can contain such limbo objects, so | |
1829 | * we don't need special tricks for shrinking the unbound list. | |
1830 | * The only other place where we have to be careful with active | |
1831 | * objects suddenly disappearing due to retiring requests is the | |
1832 | * eviction code. | |
1833 | * | |
1834 | * Note 2: Even though the bound list doesn't hold a reference | |
1835 | * to the object we can safely grab one here: The final object | |
1836 | * unreferencing and the bound_list are both protected by the | |
1837 | * dev->struct_mutex and so we won't ever be able to observe an | |
1838 | * object on the bound_list with a reference count equals 0. | |
1839 | */ | |
1840 | drm_gem_object_reference(&obj->base); | |
1841 | ||
07fe0b12 BW |
1842 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1843 | if (i915_vma_unbind(vma)) | |
1844 | break; | |
80dcfdbd | 1845 | |
57094f82 | 1846 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1847 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1848 | |
1849 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1850 | } |
57094f82 | 1851 | list_splice(&still_bound_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1852 | |
1853 | return count; | |
1854 | } | |
1855 | ||
d9973b43 | 1856 | static unsigned long |
93927ca5 DV |
1857 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
1858 | { | |
1859 | return __i915_gem_shrink(dev_priv, target, true); | |
1860 | } | |
1861 | ||
d9973b43 | 1862 | static unsigned long |
6c085a72 CW |
1863 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
1864 | { | |
1865 | struct drm_i915_gem_object *obj, *next; | |
7dc19d5a | 1866 | long freed = 0; |
6c085a72 CW |
1867 | |
1868 | i915_gem_evict_everything(dev_priv->dev); | |
1869 | ||
35c20a60 | 1870 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
7dc19d5a | 1871 | global_list) { |
d9973b43 | 1872 | if (i915_gem_object_put_pages(obj) == 0) |
7dc19d5a | 1873 | freed += obj->base.size >> PAGE_SHIFT; |
7dc19d5a DC |
1874 | } |
1875 | return freed; | |
225067ee DV |
1876 | } |
1877 | ||
37e680a1 | 1878 | static int |
6c085a72 | 1879 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1880 | { |
6c085a72 | 1881 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1882 | int page_count, i; |
1883 | struct address_space *mapping; | |
9da3da66 CW |
1884 | struct sg_table *st; |
1885 | struct scatterlist *sg; | |
90797e6d | 1886 | struct sg_page_iter sg_iter; |
e5281ccd | 1887 | struct page *page; |
90797e6d | 1888 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1889 | gfp_t gfp; |
e5281ccd | 1890 | |
6c085a72 CW |
1891 | /* Assert that the object is not currently in any GPU domain. As it |
1892 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1893 | * a GPU cache | |
1894 | */ | |
1895 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1896 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1897 | ||
9da3da66 CW |
1898 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1899 | if (st == NULL) | |
1900 | return -ENOMEM; | |
1901 | ||
05394f39 | 1902 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1903 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 1904 | kfree(st); |
e5281ccd | 1905 | return -ENOMEM; |
9da3da66 | 1906 | } |
e5281ccd | 1907 | |
9da3da66 CW |
1908 | /* Get the list of pages out of our struct file. They'll be pinned |
1909 | * at this point until we release them. | |
1910 | * | |
1911 | * Fail silently without starting the shrinker | |
1912 | */ | |
496ad9aa | 1913 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1914 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1915 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1916 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1917 | sg = st->sgl; |
1918 | st->nents = 0; | |
1919 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1920 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1921 | if (IS_ERR(page)) { | |
1922 | i915_gem_purge(dev_priv, page_count); | |
1923 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1924 | } | |
1925 | if (IS_ERR(page)) { | |
1926 | /* We've tried hard to allocate the memory by reaping | |
1927 | * our own buffer, now let the real VM do its job and | |
1928 | * go down in flames if truly OOM. | |
1929 | */ | |
caf49191 | 1930 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1931 | gfp |= __GFP_IO | __GFP_WAIT; |
1932 | ||
1933 | i915_gem_shrink_all(dev_priv); | |
1934 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1935 | if (IS_ERR(page)) | |
1936 | goto err_pages; | |
1937 | ||
caf49191 | 1938 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1939 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1940 | } | |
426729dc KRW |
1941 | #ifdef CONFIG_SWIOTLB |
1942 | if (swiotlb_nr_tbl()) { | |
1943 | st->nents++; | |
1944 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1945 | sg = sg_next(sg); | |
1946 | continue; | |
1947 | } | |
1948 | #endif | |
90797e6d ID |
1949 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1950 | if (i) | |
1951 | sg = sg_next(sg); | |
1952 | st->nents++; | |
1953 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1954 | } else { | |
1955 | sg->length += PAGE_SIZE; | |
1956 | } | |
1957 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
1958 | |
1959 | /* Check that the i965g/gm workaround works. */ | |
1960 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 1961 | } |
426729dc KRW |
1962 | #ifdef CONFIG_SWIOTLB |
1963 | if (!swiotlb_nr_tbl()) | |
1964 | #endif | |
1965 | sg_mark_end(sg); | |
74ce6b6c CW |
1966 | obj->pages = st; |
1967 | ||
6dacfd2f | 1968 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1969 | i915_gem_object_do_bit_17_swizzle(obj); |
1970 | ||
1971 | return 0; | |
1972 | ||
1973 | err_pages: | |
90797e6d ID |
1974 | sg_mark_end(sg); |
1975 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1976 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1977 | sg_free_table(st); |
1978 | kfree(st); | |
e5281ccd | 1979 | return PTR_ERR(page); |
673a394b EA |
1980 | } |
1981 | ||
37e680a1 CW |
1982 | /* Ensure that the associated pages are gathered from the backing storage |
1983 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1984 | * multiple times before they are released by a single call to | |
1985 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1986 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1987 | * or as the object is itself released. | |
1988 | */ | |
1989 | int | |
1990 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1991 | { | |
1992 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1993 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1994 | int ret; | |
1995 | ||
2f745ad3 | 1996 | if (obj->pages) |
37e680a1 CW |
1997 | return 0; |
1998 | ||
43e28f09 | 1999 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2000 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2001 | return -EFAULT; |
43e28f09 CW |
2002 | } |
2003 | ||
a5570178 CW |
2004 | BUG_ON(obj->pages_pin_count); |
2005 | ||
37e680a1 CW |
2006 | ret = ops->get_pages(obj); |
2007 | if (ret) | |
2008 | return ret; | |
2009 | ||
35c20a60 | 2010 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2011 | return 0; |
673a394b EA |
2012 | } |
2013 | ||
e2d05a8b | 2014 | static void |
05394f39 | 2015 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 2016 | struct intel_ring_buffer *ring) |
673a394b | 2017 | { |
05394f39 | 2018 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 2019 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 2020 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 2021 | |
852835f3 | 2022 | BUG_ON(ring == NULL); |
02978ff5 CW |
2023 | if (obj->ring != ring && obj->last_write_seqno) { |
2024 | /* Keep the seqno relative to the current ring */ | |
2025 | obj->last_write_seqno = seqno; | |
2026 | } | |
05394f39 | 2027 | obj->ring = ring; |
673a394b EA |
2028 | |
2029 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2030 | if (!obj->active) { |
2031 | drm_gem_object_reference(&obj->base); | |
2032 | obj->active = 1; | |
673a394b | 2033 | } |
e35a41de | 2034 | |
05394f39 | 2035 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2036 | |
0201f1ec | 2037 | obj->last_read_seqno = seqno; |
caea7476 | 2038 | |
7dd49065 | 2039 | if (obj->fenced_gpu_access) { |
caea7476 | 2040 | obj->last_fenced_seqno = seqno; |
caea7476 | 2041 | |
7dd49065 CW |
2042 | /* Bump MRU to take account of the delayed flush */ |
2043 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2044 | struct drm_i915_fence_reg *reg; | |
2045 | ||
2046 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
2047 | list_move_tail(®->lru_list, | |
2048 | &dev_priv->mm.fence_list); | |
2049 | } | |
caea7476 CW |
2050 | } |
2051 | } | |
2052 | ||
e2d05a8b BW |
2053 | void i915_vma_move_to_active(struct i915_vma *vma, |
2054 | struct intel_ring_buffer *ring) | |
2055 | { | |
2056 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2057 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2058 | } | |
2059 | ||
caea7476 | 2060 | static void |
caea7476 | 2061 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2062 | { |
ca191b13 | 2063 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2064 | struct i915_address_space *vm; |
2065 | struct i915_vma *vma; | |
ce44b0ea | 2066 | |
65ce3027 | 2067 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2068 | BUG_ON(!obj->active); |
caea7476 | 2069 | |
feb822cf BW |
2070 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2071 | vma = i915_gem_obj_to_vma(obj, vm); | |
2072 | if (vma && !list_empty(&vma->mm_list)) | |
2073 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2074 | } | |
caea7476 | 2075 | |
65ce3027 | 2076 | list_del_init(&obj->ring_list); |
caea7476 CW |
2077 | obj->ring = NULL; |
2078 | ||
65ce3027 CW |
2079 | obj->last_read_seqno = 0; |
2080 | obj->last_write_seqno = 0; | |
2081 | obj->base.write_domain = 0; | |
2082 | ||
2083 | obj->last_fenced_seqno = 0; | |
caea7476 | 2084 | obj->fenced_gpu_access = false; |
caea7476 CW |
2085 | |
2086 | obj->active = 0; | |
2087 | drm_gem_object_unreference(&obj->base); | |
2088 | ||
2089 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2090 | } |
673a394b | 2091 | |
9d773091 | 2092 | static int |
fca26bb4 | 2093 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2094 | { |
9d773091 CW |
2095 | struct drm_i915_private *dev_priv = dev->dev_private; |
2096 | struct intel_ring_buffer *ring; | |
2097 | int ret, i, j; | |
53d227f2 | 2098 | |
107f27a5 | 2099 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2100 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2101 | ret = intel_ring_idle(ring); |
2102 | if (ret) | |
2103 | return ret; | |
9d773091 | 2104 | } |
9d773091 | 2105 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2106 | |
2107 | /* Finally reset hw state */ | |
9d773091 | 2108 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2109 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2110 | |
9d773091 CW |
2111 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
2112 | ring->sync_seqno[j] = 0; | |
2113 | } | |
53d227f2 | 2114 | |
9d773091 | 2115 | return 0; |
53d227f2 DV |
2116 | } |
2117 | ||
fca26bb4 MK |
2118 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2119 | { | |
2120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2121 | int ret; | |
2122 | ||
2123 | if (seqno == 0) | |
2124 | return -EINVAL; | |
2125 | ||
2126 | /* HWS page needs to be set less than what we | |
2127 | * will inject to ring | |
2128 | */ | |
2129 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2130 | if (ret) | |
2131 | return ret; | |
2132 | ||
2133 | /* Carefully set the last_seqno value so that wrap | |
2134 | * detection still works | |
2135 | */ | |
2136 | dev_priv->next_seqno = seqno; | |
2137 | dev_priv->last_seqno = seqno - 1; | |
2138 | if (dev_priv->last_seqno == 0) | |
2139 | dev_priv->last_seqno--; | |
2140 | ||
2141 | return 0; | |
2142 | } | |
2143 | ||
9d773091 CW |
2144 | int |
2145 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2146 | { |
9d773091 CW |
2147 | struct drm_i915_private *dev_priv = dev->dev_private; |
2148 | ||
2149 | /* reserve 0 for non-seqno */ | |
2150 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2151 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2152 | if (ret) |
2153 | return ret; | |
53d227f2 | 2154 | |
9d773091 CW |
2155 | dev_priv->next_seqno = 1; |
2156 | } | |
53d227f2 | 2157 | |
f72b3435 | 2158 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2159 | return 0; |
53d227f2 DV |
2160 | } |
2161 | ||
0025c077 MK |
2162 | int __i915_add_request(struct intel_ring_buffer *ring, |
2163 | struct drm_file *file, | |
7d736f4f | 2164 | struct drm_i915_gem_object *obj, |
0025c077 | 2165 | u32 *out_seqno) |
673a394b | 2166 | { |
3e31c6c0 | 2167 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2168 | struct drm_i915_gem_request *request; |
7d736f4f | 2169 | u32 request_ring_position, request_start; |
3cce469c CW |
2170 | int ret; |
2171 | ||
7d736f4f | 2172 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2173 | /* |
2174 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2175 | * after having emitted the batchbuffer command. Hence we need to fix | |
2176 | * things up similar to emitting the lazy request. The difference here | |
2177 | * is that the flush _must_ happen before the next request, no matter | |
2178 | * what. | |
2179 | */ | |
a7b9761d CW |
2180 | ret = intel_ring_flush_all_caches(ring); |
2181 | if (ret) | |
2182 | return ret; | |
cc889e0f | 2183 | |
3c0e234c CW |
2184 | request = ring->preallocated_lazy_request; |
2185 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2186 | return -ENOMEM; |
cc889e0f | 2187 | |
a71d8d94 CW |
2188 | /* Record the position of the start of the request so that |
2189 | * should we detect the updated seqno part-way through the | |
2190 | * GPU processing the request, we never over-estimate the | |
2191 | * position of the head. | |
2192 | */ | |
2193 | request_ring_position = intel_ring_get_tail(ring); | |
2194 | ||
9d773091 | 2195 | ret = ring->add_request(ring); |
3c0e234c | 2196 | if (ret) |
3bb73aba | 2197 | return ret; |
673a394b | 2198 | |
9d773091 | 2199 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2200 | request->ring = ring; |
7d736f4f | 2201 | request->head = request_start; |
a71d8d94 | 2202 | request->tail = request_ring_position; |
7d736f4f MK |
2203 | |
2204 | /* Whilst this request exists, batch_obj will be on the | |
2205 | * active_list, and so will hold the active reference. Only when this | |
2206 | * request is retired will the the batch_obj be moved onto the | |
2207 | * inactive_list and lose its active reference. Hence we do not need | |
2208 | * to explicitly hold another reference here. | |
2209 | */ | |
9a7e0c2a | 2210 | request->batch_obj = obj; |
0e50e96b | 2211 | |
9a7e0c2a CW |
2212 | /* Hold a reference to the current context so that we can inspect |
2213 | * it later in case a hangcheck error event fires. | |
2214 | */ | |
2215 | request->ctx = ring->last_context; | |
0e50e96b MK |
2216 | if (request->ctx) |
2217 | i915_gem_context_reference(request->ctx); | |
2218 | ||
673a394b | 2219 | request->emitted_jiffies = jiffies; |
852835f3 | 2220 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2221 | request->file_priv = NULL; |
852835f3 | 2222 | |
db53a302 CW |
2223 | if (file) { |
2224 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2225 | ||
1c25595f | 2226 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2227 | request->file_priv = file_priv; |
b962442e | 2228 | list_add_tail(&request->client_list, |
f787a5f5 | 2229 | &file_priv->mm.request_list); |
1c25595f | 2230 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2231 | } |
673a394b | 2232 | |
9d773091 | 2233 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2234 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2235 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2236 | |
db1b76ca | 2237 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2238 | i915_queue_hangcheck(ring->dev); |
2239 | ||
f62a0076 CW |
2240 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2241 | queue_delayed_work(dev_priv->wq, | |
2242 | &dev_priv->mm.retire_work, | |
2243 | round_jiffies_up_relative(HZ)); | |
2244 | intel_mark_busy(dev_priv->dev); | |
f65d9421 | 2245 | } |
cc889e0f | 2246 | |
acb868d3 | 2247 | if (out_seqno) |
9d773091 | 2248 | *out_seqno = request->seqno; |
3cce469c | 2249 | return 0; |
673a394b EA |
2250 | } |
2251 | ||
f787a5f5 CW |
2252 | static inline void |
2253 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2254 | { |
1c25595f | 2255 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2256 | |
1c25595f CW |
2257 | if (!file_priv) |
2258 | return; | |
1c5d22f7 | 2259 | |
1c25595f | 2260 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2261 | list_del(&request->client_list); |
2262 | request->file_priv = NULL; | |
1c25595f | 2263 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2264 | } |
673a394b | 2265 | |
939fd762 | 2266 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
44e2c070 | 2267 | const struct i915_hw_context *ctx) |
be62acb4 | 2268 | { |
44e2c070 | 2269 | unsigned long elapsed; |
be62acb4 | 2270 | |
44e2c070 MK |
2271 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2272 | ||
2273 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2274 | return true; |
2275 | ||
2276 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2277 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2278 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2279 | return true; |
88b4aa87 MK |
2280 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2281 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2282 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2283 | return true; |
3fac8978 | 2284 | } |
be62acb4 MK |
2285 | } |
2286 | ||
2287 | return false; | |
2288 | } | |
2289 | ||
939fd762 MK |
2290 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
2291 | struct i915_hw_context *ctx, | |
b6b0fac0 | 2292 | const bool guilty) |
aa60c664 | 2293 | { |
44e2c070 MK |
2294 | struct i915_ctx_hang_stats *hs; |
2295 | ||
2296 | if (WARN_ON(!ctx)) | |
2297 | return; | |
aa60c664 | 2298 | |
44e2c070 MK |
2299 | hs = &ctx->hang_stats; |
2300 | ||
2301 | if (guilty) { | |
939fd762 | 2302 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2303 | hs->batch_active++; |
2304 | hs->guilty_ts = get_seconds(); | |
2305 | } else { | |
2306 | hs->batch_pending++; | |
aa60c664 MK |
2307 | } |
2308 | } | |
2309 | ||
0e50e96b MK |
2310 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2311 | { | |
2312 | list_del(&request->list); | |
2313 | i915_gem_request_remove_from_client(request); | |
2314 | ||
2315 | if (request->ctx) | |
2316 | i915_gem_context_unreference(request->ctx); | |
2317 | ||
2318 | kfree(request); | |
2319 | } | |
2320 | ||
8d9fc7fd CW |
2321 | struct drm_i915_gem_request * |
2322 | i915_gem_find_active_request(struct intel_ring_buffer *ring) | |
9375e446 | 2323 | { |
4db080f9 | 2324 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2325 | u32 completed_seqno; |
2326 | ||
2327 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2328 | |
2329 | list_for_each_entry(request, &ring->request_list, list) { | |
2330 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2331 | continue; | |
aa60c664 | 2332 | |
b6b0fac0 | 2333 | return request; |
4db080f9 | 2334 | } |
b6b0fac0 MK |
2335 | |
2336 | return NULL; | |
2337 | } | |
2338 | ||
2339 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
2340 | struct intel_ring_buffer *ring) | |
2341 | { | |
2342 | struct drm_i915_gem_request *request; | |
2343 | bool ring_hung; | |
2344 | ||
8d9fc7fd | 2345 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2346 | |
2347 | if (request == NULL) | |
2348 | return; | |
2349 | ||
2350 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2351 | ||
939fd762 | 2352 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2353 | |
2354 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2355 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2356 | } |
aa60c664 | 2357 | |
4db080f9 CW |
2358 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
2359 | struct intel_ring_buffer *ring) | |
2360 | { | |
dfaae392 | 2361 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2362 | struct drm_i915_gem_object *obj; |
9375e446 | 2363 | |
05394f39 CW |
2364 | obj = list_first_entry(&ring->active_list, |
2365 | struct drm_i915_gem_object, | |
2366 | ring_list); | |
9375e446 | 2367 | |
05394f39 | 2368 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2369 | } |
1d62beea BW |
2370 | |
2371 | /* | |
2372 | * We must free the requests after all the corresponding objects have | |
2373 | * been moved off active lists. Which is the same order as the normal | |
2374 | * retire_requests function does. This is important if object hold | |
2375 | * implicit references on things like e.g. ppgtt address spaces through | |
2376 | * the request. | |
2377 | */ | |
2378 | while (!list_empty(&ring->request_list)) { | |
2379 | struct drm_i915_gem_request *request; | |
2380 | ||
2381 | request = list_first_entry(&ring->request_list, | |
2382 | struct drm_i915_gem_request, | |
2383 | list); | |
2384 | ||
2385 | i915_gem_free_request(request); | |
2386 | } | |
673a394b EA |
2387 | } |
2388 | ||
19b2dbde | 2389 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2390 | { |
2391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2392 | int i; | |
2393 | ||
4b9de737 | 2394 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2395 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2396 | |
94a335db DV |
2397 | /* |
2398 | * Commit delayed tiling changes if we have an object still | |
2399 | * attached to the fence, otherwise just clear the fence. | |
2400 | */ | |
2401 | if (reg->obj) { | |
2402 | i915_gem_object_update_fence(reg->obj, reg, | |
2403 | reg->obj->tiling_mode); | |
2404 | } else { | |
2405 | i915_gem_write_fence(dev, i, NULL); | |
2406 | } | |
312817a3 CW |
2407 | } |
2408 | } | |
2409 | ||
069efc1d | 2410 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2411 | { |
77f01230 | 2412 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2413 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2414 | int i; |
673a394b | 2415 | |
4db080f9 CW |
2416 | /* |
2417 | * Before we free the objects from the requests, we need to inspect | |
2418 | * them for finding the guilty party. As the requests only borrow | |
2419 | * their reference to the objects, the inspection must be done first. | |
2420 | */ | |
2421 | for_each_ring(ring, dev_priv, i) | |
2422 | i915_gem_reset_ring_status(dev_priv, ring); | |
2423 | ||
b4519513 | 2424 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2425 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2426 | |
3d57e5bd BW |
2427 | i915_gem_cleanup_ringbuffer(dev); |
2428 | ||
acce9ffa BW |
2429 | i915_gem_context_reset(dev); |
2430 | ||
19b2dbde | 2431 | i915_gem_restore_fences(dev); |
673a394b EA |
2432 | } |
2433 | ||
2434 | /** | |
2435 | * This function clears the request list as sequence numbers are passed. | |
2436 | */ | |
cb216aa8 | 2437 | static void |
db53a302 | 2438 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2439 | { |
673a394b EA |
2440 | uint32_t seqno; |
2441 | ||
db53a302 | 2442 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2443 | return; |
2444 | ||
db53a302 | 2445 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2446 | |
b2eadbc8 | 2447 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2448 | |
e9103038 CW |
2449 | /* Move any buffers on the active list that are no longer referenced |
2450 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2451 | * before we free the context associated with the requests. | |
2452 | */ | |
2453 | while (!list_empty(&ring->active_list)) { | |
2454 | struct drm_i915_gem_object *obj; | |
2455 | ||
2456 | obj = list_first_entry(&ring->active_list, | |
2457 | struct drm_i915_gem_object, | |
2458 | ring_list); | |
2459 | ||
2460 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) | |
2461 | break; | |
2462 | ||
2463 | i915_gem_object_move_to_inactive(obj); | |
2464 | } | |
2465 | ||
2466 | ||
852835f3 | 2467 | while (!list_empty(&ring->request_list)) { |
673a394b | 2468 | struct drm_i915_gem_request *request; |
673a394b | 2469 | |
852835f3 | 2470 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2471 | struct drm_i915_gem_request, |
2472 | list); | |
673a394b | 2473 | |
dfaae392 | 2474 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2475 | break; |
2476 | ||
db53a302 | 2477 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2478 | /* We know the GPU must have read the request to have |
2479 | * sent us the seqno + interrupt, so use the position | |
2480 | * of tail of the request to update the last known position | |
2481 | * of the GPU head. | |
2482 | */ | |
2483 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2484 | |
0e50e96b | 2485 | i915_gem_free_request(request); |
b84d5f0c | 2486 | } |
673a394b | 2487 | |
db53a302 CW |
2488 | if (unlikely(ring->trace_irq_seqno && |
2489 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2490 | ring->irq_put(ring); |
db53a302 | 2491 | ring->trace_irq_seqno = 0; |
9d34e5db | 2492 | } |
23bc5982 | 2493 | |
db53a302 | 2494 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2495 | } |
2496 | ||
b29c19b6 | 2497 | bool |
b09a1fec CW |
2498 | i915_gem_retire_requests(struct drm_device *dev) |
2499 | { | |
3e31c6c0 | 2500 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2501 | struct intel_ring_buffer *ring; |
b29c19b6 | 2502 | bool idle = true; |
1ec14ad3 | 2503 | int i; |
b09a1fec | 2504 | |
b29c19b6 | 2505 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2506 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2507 | idle &= list_empty(&ring->request_list); |
2508 | } | |
2509 | ||
2510 | if (idle) | |
2511 | mod_delayed_work(dev_priv->wq, | |
2512 | &dev_priv->mm.idle_work, | |
2513 | msecs_to_jiffies(100)); | |
2514 | ||
2515 | return idle; | |
b09a1fec CW |
2516 | } |
2517 | ||
75ef9da2 | 2518 | static void |
673a394b EA |
2519 | i915_gem_retire_work_handler(struct work_struct *work) |
2520 | { | |
b29c19b6 CW |
2521 | struct drm_i915_private *dev_priv = |
2522 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2523 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2524 | bool idle; |
673a394b | 2525 | |
891b48cf | 2526 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2527 | idle = false; |
2528 | if (mutex_trylock(&dev->struct_mutex)) { | |
2529 | idle = i915_gem_retire_requests(dev); | |
2530 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2531 | } |
b29c19b6 | 2532 | if (!idle) |
bcb45086 CW |
2533 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2534 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2535 | } |
0a58705b | 2536 | |
b29c19b6 CW |
2537 | static void |
2538 | i915_gem_idle_work_handler(struct work_struct *work) | |
2539 | { | |
2540 | struct drm_i915_private *dev_priv = | |
2541 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2542 | ||
2543 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2544 | } |
2545 | ||
30dfebf3 DV |
2546 | /** |
2547 | * Ensures that an object will eventually get non-busy by flushing any required | |
2548 | * write domains, emitting any outstanding lazy request and retiring and | |
2549 | * completed requests. | |
2550 | */ | |
2551 | static int | |
2552 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2553 | { | |
2554 | int ret; | |
2555 | ||
2556 | if (obj->active) { | |
0201f1ec | 2557 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2558 | if (ret) |
2559 | return ret; | |
2560 | ||
30dfebf3 DV |
2561 | i915_gem_retire_requests_ring(obj->ring); |
2562 | } | |
2563 | ||
2564 | return 0; | |
2565 | } | |
2566 | ||
23ba4fd0 BW |
2567 | /** |
2568 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2569 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2570 | * | |
2571 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2572 | * the timeout parameter. | |
2573 | * -ETIME: object is still busy after timeout | |
2574 | * -ERESTARTSYS: signal interrupted the wait | |
2575 | * -ENONENT: object doesn't exist | |
2576 | * Also possible, but rare: | |
2577 | * -EAGAIN: GPU wedged | |
2578 | * -ENOMEM: damn | |
2579 | * -ENODEV: Internal IRQ fail | |
2580 | * -E?: The add request failed | |
2581 | * | |
2582 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2583 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2584 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2585 | * without holding struct_mutex the object may become re-busied before this | |
2586 | * function completes. A similar but shorter * race condition exists in the busy | |
2587 | * ioctl | |
2588 | */ | |
2589 | int | |
2590 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2591 | { | |
3e31c6c0 | 2592 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2593 | struct drm_i915_gem_wait *args = data; |
2594 | struct drm_i915_gem_object *obj; | |
2595 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2596 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2597 | unsigned reset_counter; |
23ba4fd0 BW |
2598 | u32 seqno = 0; |
2599 | int ret = 0; | |
2600 | ||
eac1f14f BW |
2601 | if (args->timeout_ns >= 0) { |
2602 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2603 | timeout = &timeout_stack; | |
2604 | } | |
23ba4fd0 BW |
2605 | |
2606 | ret = i915_mutex_lock_interruptible(dev); | |
2607 | if (ret) | |
2608 | return ret; | |
2609 | ||
2610 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2611 | if (&obj->base == NULL) { | |
2612 | mutex_unlock(&dev->struct_mutex); | |
2613 | return -ENOENT; | |
2614 | } | |
2615 | ||
30dfebf3 DV |
2616 | /* Need to make sure the object gets inactive eventually. */ |
2617 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2618 | if (ret) |
2619 | goto out; | |
2620 | ||
2621 | if (obj->active) { | |
0201f1ec | 2622 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2623 | ring = obj->ring; |
2624 | } | |
2625 | ||
2626 | if (seqno == 0) | |
2627 | goto out; | |
2628 | ||
23ba4fd0 BW |
2629 | /* Do this after OLR check to make sure we make forward progress polling |
2630 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2631 | */ | |
2632 | if (!args->timeout_ns) { | |
2633 | ret = -ETIME; | |
2634 | goto out; | |
2635 | } | |
2636 | ||
2637 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2638 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2639 | mutex_unlock(&dev->struct_mutex); |
2640 | ||
b29c19b6 | 2641 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2642 | if (timeout) |
eac1f14f | 2643 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2644 | return ret; |
2645 | ||
2646 | out: | |
2647 | drm_gem_object_unreference(&obj->base); | |
2648 | mutex_unlock(&dev->struct_mutex); | |
2649 | return ret; | |
2650 | } | |
2651 | ||
5816d648 BW |
2652 | /** |
2653 | * i915_gem_object_sync - sync an object to a ring. | |
2654 | * | |
2655 | * @obj: object which may be in use on another ring. | |
2656 | * @to: ring we wish to use the object on. May be NULL. | |
2657 | * | |
2658 | * This code is meant to abstract object synchronization with the GPU. | |
2659 | * Calling with NULL implies synchronizing the object with the CPU | |
2660 | * rather than a particular GPU ring. | |
2661 | * | |
2662 | * Returns 0 if successful, else propagates up the lower layer error. | |
2663 | */ | |
2911a35b BW |
2664 | int |
2665 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2666 | struct intel_ring_buffer *to) | |
2667 | { | |
2668 | struct intel_ring_buffer *from = obj->ring; | |
2669 | u32 seqno; | |
2670 | int ret, idx; | |
2671 | ||
2672 | if (from == NULL || to == from) | |
2673 | return 0; | |
2674 | ||
5816d648 | 2675 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2676 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2677 | |
2678 | idx = intel_ring_sync_index(from, to); | |
2679 | ||
0201f1ec | 2680 | seqno = obj->last_read_seqno; |
2911a35b BW |
2681 | if (seqno <= from->sync_seqno[idx]) |
2682 | return 0; | |
2683 | ||
b4aca010 BW |
2684 | ret = i915_gem_check_olr(obj->ring, seqno); |
2685 | if (ret) | |
2686 | return ret; | |
2911a35b | 2687 | |
b52b89da | 2688 | trace_i915_gem_ring_sync_to(from, to, seqno); |
1500f7ea | 2689 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2690 | if (!ret) |
7b01e260 MK |
2691 | /* We use last_read_seqno because sync_to() |
2692 | * might have just caused seqno wrap under | |
2693 | * the radar. | |
2694 | */ | |
2695 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2696 | |
e3a5a225 | 2697 | return ret; |
2911a35b BW |
2698 | } |
2699 | ||
b5ffc9bc CW |
2700 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2701 | { | |
2702 | u32 old_write_domain, old_read_domains; | |
2703 | ||
b5ffc9bc CW |
2704 | /* Force a pagefault for domain tracking on next user access */ |
2705 | i915_gem_release_mmap(obj); | |
2706 | ||
b97c3d9c KP |
2707 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2708 | return; | |
2709 | ||
97c809fd CW |
2710 | /* Wait for any direct GTT access to complete */ |
2711 | mb(); | |
2712 | ||
b5ffc9bc CW |
2713 | old_read_domains = obj->base.read_domains; |
2714 | old_write_domain = obj->base.write_domain; | |
2715 | ||
2716 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2717 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2718 | ||
2719 | trace_i915_gem_object_change_domain(obj, | |
2720 | old_read_domains, | |
2721 | old_write_domain); | |
2722 | } | |
2723 | ||
07fe0b12 | 2724 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2725 | { |
07fe0b12 | 2726 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 2727 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2728 | int ret; |
673a394b | 2729 | |
07fe0b12 | 2730 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2731 | return 0; |
2732 | ||
0ff501cb DV |
2733 | if (!drm_mm_node_allocated(&vma->node)) { |
2734 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
2735 | return 0; |
2736 | } | |
433544bd | 2737 | |
d7f46fc4 | 2738 | if (vma->pin_count) |
31d8d651 | 2739 | return -EBUSY; |
673a394b | 2740 | |
c4670ad0 CW |
2741 | BUG_ON(obj->pages == NULL); |
2742 | ||
a8198eea | 2743 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2744 | if (ret) |
a8198eea CW |
2745 | return ret; |
2746 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2747 | * should be safe and we need to cleanup or else we might | |
2748 | * cause memory corruption through use-after-free. | |
2749 | */ | |
2750 | ||
b5ffc9bc | 2751 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2752 | |
96b47b65 | 2753 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2754 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2755 | if (ret) |
d9e86c0e | 2756 | return ret; |
96b47b65 | 2757 | |
07fe0b12 | 2758 | trace_i915_vma_unbind(vma); |
db53a302 | 2759 | |
6f65e29a BW |
2760 | vma->unbind_vma(vma); |
2761 | ||
74163907 | 2762 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2763 | |
64bf9303 | 2764 | list_del_init(&vma->mm_list); |
75e9e915 | 2765 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2766 | if (i915_is_ggtt(vma->vm)) |
2767 | obj->map_and_fenceable = true; | |
673a394b | 2768 | |
2f633156 BW |
2769 | drm_mm_remove_node(&vma->node); |
2770 | i915_gem_vma_destroy(vma); | |
2771 | ||
2772 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2773 | * no more VMAs exist. */ |
2f633156 BW |
2774 | if (list_empty(&obj->vma_list)) |
2775 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2776 | |
70903c3b CW |
2777 | /* And finally now the object is completely decoupled from this vma, |
2778 | * we can drop its hold on the backing storage and allow it to be | |
2779 | * reaped by the shrinker. | |
2780 | */ | |
2781 | i915_gem_object_unpin_pages(obj); | |
2782 | ||
88241785 | 2783 | return 0; |
54cf91dc CW |
2784 | } |
2785 | ||
b2da9fe5 | 2786 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 2787 | { |
3e31c6c0 | 2788 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2789 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2790 | int ret, i; |
4df2faf4 | 2791 | |
4df2faf4 | 2792 | /* Flush everything onto the inactive list. */ |
b4519513 | 2793 | for_each_ring(ring, dev_priv, i) { |
41bde553 | 2794 | ret = i915_switch_context(ring, NULL, ring->default_context); |
b6c7488d BW |
2795 | if (ret) |
2796 | return ret; | |
2797 | ||
3e960501 | 2798 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2799 | if (ret) |
2800 | return ret; | |
2801 | } | |
4df2faf4 | 2802 | |
8a1a49f9 | 2803 | return 0; |
4df2faf4 DV |
2804 | } |
2805 | ||
9ce079e4 CW |
2806 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2807 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2808 | { |
3e31c6c0 | 2809 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
2810 | int fence_reg; |
2811 | int fence_pitch_shift; | |
de151cf6 | 2812 | |
56c844e5 ID |
2813 | if (INTEL_INFO(dev)->gen >= 6) { |
2814 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2815 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2816 | } else { | |
2817 | fence_reg = FENCE_REG_965_0; | |
2818 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2819 | } | |
2820 | ||
d18b9619 CW |
2821 | fence_reg += reg * 8; |
2822 | ||
2823 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2824 | * we split the 64-bit update into two 32-bit writes. In order | |
2825 | * for a partial fence not to be evaluated between writes, we | |
2826 | * precede the update with write to turn off the fence register, | |
2827 | * and only enable the fence as the last step. | |
2828 | * | |
2829 | * For extra levels of paranoia, we make sure each step lands | |
2830 | * before applying the next step. | |
2831 | */ | |
2832 | I915_WRITE(fence_reg, 0); | |
2833 | POSTING_READ(fence_reg); | |
2834 | ||
9ce079e4 | 2835 | if (obj) { |
f343c5f6 | 2836 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2837 | uint64_t val; |
de151cf6 | 2838 | |
f343c5f6 | 2839 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2840 | 0xfffff000) << 32; |
f343c5f6 | 2841 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2842 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2843 | if (obj->tiling_mode == I915_TILING_Y) |
2844 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2845 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2846 | |
d18b9619 CW |
2847 | I915_WRITE(fence_reg + 4, val >> 32); |
2848 | POSTING_READ(fence_reg + 4); | |
2849 | ||
2850 | I915_WRITE(fence_reg + 0, val); | |
2851 | POSTING_READ(fence_reg); | |
2852 | } else { | |
2853 | I915_WRITE(fence_reg + 4, 0); | |
2854 | POSTING_READ(fence_reg + 4); | |
2855 | } | |
de151cf6 JB |
2856 | } |
2857 | ||
9ce079e4 CW |
2858 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2859 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2860 | { |
3e31c6c0 | 2861 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 2862 | u32 val; |
de151cf6 | 2863 | |
9ce079e4 | 2864 | if (obj) { |
f343c5f6 | 2865 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2866 | int pitch_val; |
2867 | int tile_width; | |
c6642782 | 2868 | |
f343c5f6 | 2869 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2870 | (size & -size) != size || |
f343c5f6 BW |
2871 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2872 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2873 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2874 | |
9ce079e4 CW |
2875 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2876 | tile_width = 128; | |
2877 | else | |
2878 | tile_width = 512; | |
2879 | ||
2880 | /* Note: pitch better be a power of two tile widths */ | |
2881 | pitch_val = obj->stride / tile_width; | |
2882 | pitch_val = ffs(pitch_val) - 1; | |
2883 | ||
f343c5f6 | 2884 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2885 | if (obj->tiling_mode == I915_TILING_Y) |
2886 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2887 | val |= I915_FENCE_SIZE_BITS(size); | |
2888 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2889 | val |= I830_FENCE_REG_VALID; | |
2890 | } else | |
2891 | val = 0; | |
2892 | ||
2893 | if (reg < 8) | |
2894 | reg = FENCE_REG_830_0 + reg * 4; | |
2895 | else | |
2896 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2897 | ||
2898 | I915_WRITE(reg, val); | |
2899 | POSTING_READ(reg); | |
de151cf6 JB |
2900 | } |
2901 | ||
9ce079e4 CW |
2902 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2903 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2904 | { |
3e31c6c0 | 2905 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 2906 | uint32_t val; |
de151cf6 | 2907 | |
9ce079e4 | 2908 | if (obj) { |
f343c5f6 | 2909 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2910 | uint32_t pitch_val; |
de151cf6 | 2911 | |
f343c5f6 | 2912 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2913 | (size & -size) != size || |
f343c5f6 BW |
2914 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2915 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2916 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2917 | |
9ce079e4 CW |
2918 | pitch_val = obj->stride / 128; |
2919 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2920 | |
f343c5f6 | 2921 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2922 | if (obj->tiling_mode == I915_TILING_Y) |
2923 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2924 | val |= I830_FENCE_SIZE_BITS(size); | |
2925 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2926 | val |= I830_FENCE_REG_VALID; | |
2927 | } else | |
2928 | val = 0; | |
c6642782 | 2929 | |
9ce079e4 CW |
2930 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2931 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2932 | } | |
2933 | ||
d0a57789 CW |
2934 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2935 | { | |
2936 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2937 | } | |
2938 | ||
9ce079e4 CW |
2939 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2940 | struct drm_i915_gem_object *obj) | |
2941 | { | |
d0a57789 CW |
2942 | struct drm_i915_private *dev_priv = dev->dev_private; |
2943 | ||
2944 | /* Ensure that all CPU reads are completed before installing a fence | |
2945 | * and all writes before removing the fence. | |
2946 | */ | |
2947 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2948 | mb(); | |
2949 | ||
94a335db DV |
2950 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2951 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2952 | obj->stride, obj->tiling_mode); | |
2953 | ||
9ce079e4 | 2954 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 2955 | case 8: |
9ce079e4 | 2956 | case 7: |
56c844e5 | 2957 | case 6: |
9ce079e4 CW |
2958 | case 5: |
2959 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2960 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2961 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2962 | default: BUG(); |
9ce079e4 | 2963 | } |
d0a57789 CW |
2964 | |
2965 | /* And similarly be paranoid that no direct access to this region | |
2966 | * is reordered to before the fence is installed. | |
2967 | */ | |
2968 | if (i915_gem_object_needs_mb(obj)) | |
2969 | mb(); | |
de151cf6 JB |
2970 | } |
2971 | ||
61050808 CW |
2972 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2973 | struct drm_i915_fence_reg *fence) | |
2974 | { | |
2975 | return fence - dev_priv->fence_regs; | |
2976 | } | |
2977 | ||
2978 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2979 | struct drm_i915_fence_reg *fence, | |
2980 | bool enable) | |
2981 | { | |
2dc8aae0 | 2982 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
2983 | int reg = fence_number(dev_priv, fence); |
2984 | ||
2985 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
2986 | |
2987 | if (enable) { | |
46a0b638 | 2988 | obj->fence_reg = reg; |
61050808 CW |
2989 | fence->obj = obj; |
2990 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2991 | } else { | |
2992 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2993 | fence->obj = NULL; | |
2994 | list_del_init(&fence->lru_list); | |
2995 | } | |
94a335db | 2996 | obj->fence_dirty = false; |
61050808 CW |
2997 | } |
2998 | ||
d9e86c0e | 2999 | static int |
d0a57789 | 3000 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3001 | { |
1c293ea3 | 3002 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3003 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3004 | if (ret) |
3005 | return ret; | |
d9e86c0e CW |
3006 | |
3007 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3008 | } |
3009 | ||
86d5bc37 | 3010 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3011 | return 0; |
3012 | } | |
3013 | ||
3014 | int | |
3015 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3016 | { | |
61050808 | 3017 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3018 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3019 | int ret; |
3020 | ||
d0a57789 | 3021 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3022 | if (ret) |
3023 | return ret; | |
3024 | ||
61050808 CW |
3025 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3026 | return 0; | |
d9e86c0e | 3027 | |
f9c513e9 CW |
3028 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3029 | ||
61050808 | 3030 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3031 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3032 | |
3033 | return 0; | |
3034 | } | |
3035 | ||
3036 | static struct drm_i915_fence_reg * | |
a360bb1a | 3037 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3038 | { |
ae3db24a | 3039 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3040 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3041 | int i; |
ae3db24a DV |
3042 | |
3043 | /* First try to find a free reg */ | |
d9e86c0e | 3044 | avail = NULL; |
ae3db24a DV |
3045 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3046 | reg = &dev_priv->fence_regs[i]; | |
3047 | if (!reg->obj) | |
d9e86c0e | 3048 | return reg; |
ae3db24a | 3049 | |
1690e1eb | 3050 | if (!reg->pin_count) |
d9e86c0e | 3051 | avail = reg; |
ae3db24a DV |
3052 | } |
3053 | ||
d9e86c0e | 3054 | if (avail == NULL) |
5dce5b93 | 3055 | goto deadlock; |
ae3db24a DV |
3056 | |
3057 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3058 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3059 | if (reg->pin_count) |
ae3db24a DV |
3060 | continue; |
3061 | ||
8fe301ad | 3062 | return reg; |
ae3db24a DV |
3063 | } |
3064 | ||
5dce5b93 CW |
3065 | deadlock: |
3066 | /* Wait for completion of pending flips which consume fences */ | |
3067 | if (intel_has_pending_fb_unpin(dev)) | |
3068 | return ERR_PTR(-EAGAIN); | |
3069 | ||
3070 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3071 | } |
3072 | ||
de151cf6 | 3073 | /** |
9a5a53b3 | 3074 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3075 | * @obj: object to map through a fence reg |
3076 | * | |
3077 | * When mapping objects through the GTT, userspace wants to be able to write | |
3078 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3079 | * This function walks the fence regs looking for a free one for @obj, |
3080 | * stealing one if it can't find any. | |
3081 | * | |
3082 | * It then sets up the reg based on the object's properties: address, pitch | |
3083 | * and tiling format. | |
9a5a53b3 CW |
3084 | * |
3085 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3086 | */ |
8c4b8c3f | 3087 | int |
06d98131 | 3088 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3089 | { |
05394f39 | 3090 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3091 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3092 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3093 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3094 | int ret; |
de151cf6 | 3095 | |
14415745 CW |
3096 | /* Have we updated the tiling parameters upon the object and so |
3097 | * will need to serialise the write to the associated fence register? | |
3098 | */ | |
5d82e3e6 | 3099 | if (obj->fence_dirty) { |
d0a57789 | 3100 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3101 | if (ret) |
3102 | return ret; | |
3103 | } | |
9a5a53b3 | 3104 | |
d9e86c0e | 3105 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3106 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3107 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3108 | if (!obj->fence_dirty) { |
14415745 CW |
3109 | list_move_tail(®->lru_list, |
3110 | &dev_priv->mm.fence_list); | |
3111 | return 0; | |
3112 | } | |
3113 | } else if (enable) { | |
3114 | reg = i915_find_fence_reg(dev); | |
5dce5b93 CW |
3115 | if (IS_ERR(reg)) |
3116 | return PTR_ERR(reg); | |
d9e86c0e | 3117 | |
14415745 CW |
3118 | if (reg->obj) { |
3119 | struct drm_i915_gem_object *old = reg->obj; | |
3120 | ||
d0a57789 | 3121 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3122 | if (ret) |
3123 | return ret; | |
3124 | ||
14415745 | 3125 | i915_gem_object_fence_lost(old); |
29c5a587 | 3126 | } |
14415745 | 3127 | } else |
a09ba7fa | 3128 | return 0; |
a09ba7fa | 3129 | |
14415745 | 3130 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3131 | |
9ce079e4 | 3132 | return 0; |
de151cf6 JB |
3133 | } |
3134 | ||
42d6ab48 CW |
3135 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3136 | struct drm_mm_node *gtt_space, | |
3137 | unsigned long cache_level) | |
3138 | { | |
3139 | struct drm_mm_node *other; | |
3140 | ||
3141 | /* On non-LLC machines we have to be careful when putting differing | |
3142 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3143 | * crossing memory domains and dying. |
42d6ab48 CW |
3144 | */ |
3145 | if (HAS_LLC(dev)) | |
3146 | return true; | |
3147 | ||
c6cfb325 | 3148 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3149 | return true; |
3150 | ||
3151 | if (list_empty(>t_space->node_list)) | |
3152 | return true; | |
3153 | ||
3154 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3155 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3156 | return false; | |
3157 | ||
3158 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3159 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3160 | return false; | |
3161 | ||
3162 | return true; | |
3163 | } | |
3164 | ||
3165 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3166 | { | |
3167 | #if WATCH_GTT | |
3168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3169 | struct drm_i915_gem_object *obj; | |
3170 | int err = 0; | |
3171 | ||
35c20a60 | 3172 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3173 | if (obj->gtt_space == NULL) { |
3174 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3175 | err++; | |
3176 | continue; | |
3177 | } | |
3178 | ||
3179 | if (obj->cache_level != obj->gtt_space->color) { | |
3180 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3181 | i915_gem_obj_ggtt_offset(obj), |
3182 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3183 | obj->cache_level, |
3184 | obj->gtt_space->color); | |
3185 | err++; | |
3186 | continue; | |
3187 | } | |
3188 | ||
3189 | if (!i915_gem_valid_gtt_space(dev, | |
3190 | obj->gtt_space, | |
3191 | obj->cache_level)) { | |
3192 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3193 | i915_gem_obj_ggtt_offset(obj), |
3194 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3195 | obj->cache_level); |
3196 | err++; | |
3197 | continue; | |
3198 | } | |
3199 | } | |
3200 | ||
3201 | WARN_ON(err); | |
3202 | #endif | |
3203 | } | |
3204 | ||
673a394b EA |
3205 | /** |
3206 | * Finds free space in the GTT aperture and binds the object there. | |
3207 | */ | |
262de145 | 3208 | static struct i915_vma * |
07fe0b12 BW |
3209 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3210 | struct i915_address_space *vm, | |
3211 | unsigned alignment, | |
1ec9e26d | 3212 | unsigned flags) |
673a394b | 3213 | { |
05394f39 | 3214 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3215 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3216 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 | 3217 | size_t gtt_max = |
1ec9e26d | 3218 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3219 | struct i915_vma *vma; |
07f73f69 | 3220 | int ret; |
673a394b | 3221 | |
e28f8711 CW |
3222 | fence_size = i915_gem_get_gtt_size(dev, |
3223 | obj->base.size, | |
3224 | obj->tiling_mode); | |
3225 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3226 | obj->base.size, | |
d865110c | 3227 | obj->tiling_mode, true); |
e28f8711 | 3228 | unfenced_alignment = |
d865110c | 3229 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3230 | obj->base.size, |
3231 | obj->tiling_mode, false); | |
a00b10c3 | 3232 | |
673a394b | 3233 | if (alignment == 0) |
1ec9e26d | 3234 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3235 | unfenced_alignment; |
1ec9e26d | 3236 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3237 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3238 | return ERR_PTR(-EINVAL); |
673a394b EA |
3239 | } |
3240 | ||
1ec9e26d | 3241 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3242 | |
654fc607 CW |
3243 | /* If the object is bigger than the entire aperture, reject it early |
3244 | * before evicting everything in a vain attempt to find space. | |
3245 | */ | |
0a9ae0d7 | 3246 | if (obj->base.size > gtt_max) { |
bd9b6a4e | 3247 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb | 3248 | obj->base.size, |
1ec9e26d | 3249 | flags & PIN_MAPPABLE ? "mappable" : "total", |
0a9ae0d7 | 3250 | gtt_max); |
262de145 | 3251 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3252 | } |
3253 | ||
37e680a1 | 3254 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3255 | if (ret) |
262de145 | 3256 | return ERR_PTR(ret); |
6c085a72 | 3257 | |
fbdda6fb CW |
3258 | i915_gem_object_pin_pages(obj); |
3259 | ||
accfef2e | 3260 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3261 | if (IS_ERR(vma)) |
bc6bc15b | 3262 | goto err_unpin; |
2f633156 | 3263 | |
0a9ae0d7 | 3264 | search_free: |
07fe0b12 | 3265 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3266 | size, alignment, |
31e5d7c6 | 3267 | obj->cache_level, 0, gtt_max, |
62347f9e LK |
3268 | DRM_MM_SEARCH_DEFAULT, |
3269 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3270 | if (ret) { |
f6cd1f15 | 3271 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
1ec9e26d | 3272 | obj->cache_level, flags); |
dc9dd7a2 CW |
3273 | if (ret == 0) |
3274 | goto search_free; | |
9731129c | 3275 | |
bc6bc15b | 3276 | goto err_free_vma; |
673a394b | 3277 | } |
2f633156 | 3278 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3279 | obj->cache_level))) { |
2f633156 | 3280 | ret = -EINVAL; |
bc6bc15b | 3281 | goto err_remove_node; |
673a394b EA |
3282 | } |
3283 | ||
74163907 | 3284 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3285 | if (ret) |
bc6bc15b | 3286 | goto err_remove_node; |
673a394b | 3287 | |
35c20a60 | 3288 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3289 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3290 | |
4bd561b3 BW |
3291 | if (i915_is_ggtt(vm)) { |
3292 | bool mappable, fenceable; | |
a00b10c3 | 3293 | |
49987099 DV |
3294 | fenceable = (vma->node.size == fence_size && |
3295 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3296 | |
49987099 DV |
3297 | mappable = (vma->node.start + obj->base.size <= |
3298 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3299 | |
5cacaac7 | 3300 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3301 | } |
75e9e915 | 3302 | |
1ec9e26d | 3303 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
75e9e915 | 3304 | |
1ec9e26d | 3305 | trace_i915_vma_bind(vma, flags); |
8ea99c92 DV |
3306 | vma->bind_vma(vma, obj->cache_level, |
3307 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); | |
3308 | ||
42d6ab48 | 3309 | i915_gem_verify_gtt(dev); |
262de145 | 3310 | return vma; |
2f633156 | 3311 | |
bc6bc15b | 3312 | err_remove_node: |
6286ef9b | 3313 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3314 | err_free_vma: |
2f633156 | 3315 | i915_gem_vma_destroy(vma); |
262de145 | 3316 | vma = ERR_PTR(ret); |
bc6bc15b | 3317 | err_unpin: |
2f633156 | 3318 | i915_gem_object_unpin_pages(obj); |
262de145 | 3319 | return vma; |
673a394b EA |
3320 | } |
3321 | ||
000433b6 | 3322 | bool |
2c22569b CW |
3323 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3324 | bool force) | |
673a394b | 3325 | { |
673a394b EA |
3326 | /* If we don't have a page list set up, then we're not pinned |
3327 | * to GPU, and we can ignore the cache flush because it'll happen | |
3328 | * again at bind time. | |
3329 | */ | |
05394f39 | 3330 | if (obj->pages == NULL) |
000433b6 | 3331 | return false; |
673a394b | 3332 | |
769ce464 ID |
3333 | /* |
3334 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3335 | * marked as wc by the system, or the system is cache-coherent. | |
3336 | */ | |
3337 | if (obj->stolen) | |
000433b6 | 3338 | return false; |
769ce464 | 3339 | |
9c23f7fc CW |
3340 | /* If the GPU is snooping the contents of the CPU cache, |
3341 | * we do not need to manually clear the CPU cache lines. However, | |
3342 | * the caches are only snooped when the render cache is | |
3343 | * flushed/invalidated. As we always have to emit invalidations | |
3344 | * and flushes when moving into and out of the RENDER domain, correct | |
3345 | * snooping behaviour occurs naturally as the result of our domain | |
3346 | * tracking. | |
3347 | */ | |
2c22569b | 3348 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3349 | return false; |
9c23f7fc | 3350 | |
1c5d22f7 | 3351 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3352 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3353 | |
3354 | return true; | |
e47c68e9 EA |
3355 | } |
3356 | ||
3357 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3358 | static void | |
05394f39 | 3359 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3360 | { |
1c5d22f7 CW |
3361 | uint32_t old_write_domain; |
3362 | ||
05394f39 | 3363 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3364 | return; |
3365 | ||
63256ec5 | 3366 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3367 | * to it immediately go to main memory as far as we know, so there's |
3368 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3369 | * |
3370 | * However, we do have to enforce the order so that all writes through | |
3371 | * the GTT land before any writes to the device, such as updates to | |
3372 | * the GATT itself. | |
e47c68e9 | 3373 | */ |
63256ec5 CW |
3374 | wmb(); |
3375 | ||
05394f39 CW |
3376 | old_write_domain = obj->base.write_domain; |
3377 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3378 | |
3379 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3380 | obj->base.read_domains, |
1c5d22f7 | 3381 | old_write_domain); |
e47c68e9 EA |
3382 | } |
3383 | ||
3384 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3385 | static void | |
2c22569b CW |
3386 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3387 | bool force) | |
e47c68e9 | 3388 | { |
1c5d22f7 | 3389 | uint32_t old_write_domain; |
e47c68e9 | 3390 | |
05394f39 | 3391 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3392 | return; |
3393 | ||
000433b6 CW |
3394 | if (i915_gem_clflush_object(obj, force)) |
3395 | i915_gem_chipset_flush(obj->base.dev); | |
3396 | ||
05394f39 CW |
3397 | old_write_domain = obj->base.write_domain; |
3398 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3399 | |
3400 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3401 | obj->base.read_domains, |
1c5d22f7 | 3402 | old_write_domain); |
e47c68e9 EA |
3403 | } |
3404 | ||
2ef7eeaa EA |
3405 | /** |
3406 | * Moves a single object to the GTT read, and possibly write domain. | |
3407 | * | |
3408 | * This function returns when the move is complete, including waiting on | |
3409 | * flushes to occur. | |
3410 | */ | |
79e53945 | 3411 | int |
2021746e | 3412 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3413 | { |
3e31c6c0 | 3414 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3415 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3416 | int ret; |
2ef7eeaa | 3417 | |
02354392 | 3418 | /* Not valid to be called on unbound objects. */ |
9843877d | 3419 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3420 | return -EINVAL; |
3421 | ||
8d7e3de1 CW |
3422 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3423 | return 0; | |
3424 | ||
0201f1ec | 3425 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3426 | if (ret) |
3427 | return ret; | |
3428 | ||
2c22569b | 3429 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3430 | |
d0a57789 CW |
3431 | /* Serialise direct access to this object with the barriers for |
3432 | * coherent writes from the GPU, by effectively invalidating the | |
3433 | * GTT domain upon first access. | |
3434 | */ | |
3435 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3436 | mb(); | |
3437 | ||
05394f39 CW |
3438 | old_write_domain = obj->base.write_domain; |
3439 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3440 | |
e47c68e9 EA |
3441 | /* It should now be out of any other write domains, and we can update |
3442 | * the domain values for our changes. | |
3443 | */ | |
05394f39 CW |
3444 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3445 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3446 | if (write) { |
05394f39 CW |
3447 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3448 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3449 | obj->dirty = 1; | |
2ef7eeaa EA |
3450 | } |
3451 | ||
1c5d22f7 CW |
3452 | trace_i915_gem_object_change_domain(obj, |
3453 | old_read_domains, | |
3454 | old_write_domain); | |
3455 | ||
8325a09d | 3456 | /* And bump the LRU for this access */ |
ca191b13 | 3457 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3458 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3459 | if (vma) |
3460 | list_move_tail(&vma->mm_list, | |
3461 | &dev_priv->gtt.base.inactive_list); | |
3462 | ||
3463 | } | |
8325a09d | 3464 | |
e47c68e9 EA |
3465 | return 0; |
3466 | } | |
3467 | ||
e4ffd173 CW |
3468 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3469 | enum i915_cache_level cache_level) | |
3470 | { | |
7bddb01f | 3471 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3472 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3473 | int ret; |
3474 | ||
3475 | if (obj->cache_level == cache_level) | |
3476 | return 0; | |
3477 | ||
d7f46fc4 | 3478 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3479 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3480 | return -EBUSY; | |
3481 | } | |
3482 | ||
df6f783a | 3483 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
3089c6f2 | 3484 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
07fe0b12 | 3485 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3486 | if (ret) |
3487 | return ret; | |
3089c6f2 | 3488 | } |
42d6ab48 CW |
3489 | } |
3490 | ||
3089c6f2 | 3491 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3492 | ret = i915_gem_object_finish_gpu(obj); |
3493 | if (ret) | |
3494 | return ret; | |
3495 | ||
3496 | i915_gem_object_finish_gtt(obj); | |
3497 | ||
3498 | /* Before SandyBridge, you could not use tiling or fence | |
3499 | * registers with snooped memory, so relinquish any fences | |
3500 | * currently pointing to our region in the aperture. | |
3501 | */ | |
42d6ab48 | 3502 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3503 | ret = i915_gem_object_put_fence(obj); |
3504 | if (ret) | |
3505 | return ret; | |
3506 | } | |
3507 | ||
6f65e29a | 3508 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3509 | if (drm_mm_node_allocated(&vma->node)) |
3510 | vma->bind_vma(vma, cache_level, | |
3511 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); | |
e4ffd173 CW |
3512 | } |
3513 | ||
2c22569b CW |
3514 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3515 | vma->node.color = cache_level; | |
3516 | obj->cache_level = cache_level; | |
3517 | ||
3518 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3519 | u32 old_read_domains, old_write_domain; |
3520 | ||
3521 | /* If we're coming from LLC cached, then we haven't | |
3522 | * actually been tracking whether the data is in the | |
3523 | * CPU cache or not, since we only allow one bit set | |
3524 | * in obj->write_domain and have been skipping the clflushes. | |
3525 | * Just set it to the CPU cache for now. | |
3526 | */ | |
3527 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
e4ffd173 CW |
3528 | |
3529 | old_read_domains = obj->base.read_domains; | |
3530 | old_write_domain = obj->base.write_domain; | |
3531 | ||
3532 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3533 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3534 | ||
3535 | trace_i915_gem_object_change_domain(obj, | |
3536 | old_read_domains, | |
3537 | old_write_domain); | |
3538 | } | |
3539 | ||
42d6ab48 | 3540 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3541 | return 0; |
3542 | } | |
3543 | ||
199adf40 BW |
3544 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3545 | struct drm_file *file) | |
e6994aee | 3546 | { |
199adf40 | 3547 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3548 | struct drm_i915_gem_object *obj; |
3549 | int ret; | |
3550 | ||
3551 | ret = i915_mutex_lock_interruptible(dev); | |
3552 | if (ret) | |
3553 | return ret; | |
3554 | ||
3555 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3556 | if (&obj->base == NULL) { | |
3557 | ret = -ENOENT; | |
3558 | goto unlock; | |
3559 | } | |
3560 | ||
651d794f CW |
3561 | switch (obj->cache_level) { |
3562 | case I915_CACHE_LLC: | |
3563 | case I915_CACHE_L3_LLC: | |
3564 | args->caching = I915_CACHING_CACHED; | |
3565 | break; | |
3566 | ||
4257d3ba CW |
3567 | case I915_CACHE_WT: |
3568 | args->caching = I915_CACHING_DISPLAY; | |
3569 | break; | |
3570 | ||
651d794f CW |
3571 | default: |
3572 | args->caching = I915_CACHING_NONE; | |
3573 | break; | |
3574 | } | |
e6994aee CW |
3575 | |
3576 | drm_gem_object_unreference(&obj->base); | |
3577 | unlock: | |
3578 | mutex_unlock(&dev->struct_mutex); | |
3579 | return ret; | |
3580 | } | |
3581 | ||
199adf40 BW |
3582 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3583 | struct drm_file *file) | |
e6994aee | 3584 | { |
199adf40 | 3585 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3586 | struct drm_i915_gem_object *obj; |
3587 | enum i915_cache_level level; | |
3588 | int ret; | |
3589 | ||
199adf40 BW |
3590 | switch (args->caching) { |
3591 | case I915_CACHING_NONE: | |
e6994aee CW |
3592 | level = I915_CACHE_NONE; |
3593 | break; | |
199adf40 | 3594 | case I915_CACHING_CACHED: |
e6994aee CW |
3595 | level = I915_CACHE_LLC; |
3596 | break; | |
4257d3ba CW |
3597 | case I915_CACHING_DISPLAY: |
3598 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3599 | break; | |
e6994aee CW |
3600 | default: |
3601 | return -EINVAL; | |
3602 | } | |
3603 | ||
3bc2913e BW |
3604 | ret = i915_mutex_lock_interruptible(dev); |
3605 | if (ret) | |
3606 | return ret; | |
3607 | ||
e6994aee CW |
3608 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3609 | if (&obj->base == NULL) { | |
3610 | ret = -ENOENT; | |
3611 | goto unlock; | |
3612 | } | |
3613 | ||
3614 | ret = i915_gem_object_set_cache_level(obj, level); | |
3615 | ||
3616 | drm_gem_object_unreference(&obj->base); | |
3617 | unlock: | |
3618 | mutex_unlock(&dev->struct_mutex); | |
3619 | return ret; | |
3620 | } | |
3621 | ||
cc98b413 CW |
3622 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3623 | { | |
3624 | /* There are 3 sources that pin objects: | |
3625 | * 1. The display engine (scanouts, sprites, cursors); | |
3626 | * 2. Reservations for execbuffer; | |
3627 | * 3. The user. | |
3628 | * | |
3629 | * We can ignore reservations as we hold the struct_mutex and | |
3630 | * are only called outside of the reservation path. The user | |
3631 | * can only increment pin_count once, and so if after | |
3632 | * subtracting the potential reference by the user, any pin_count | |
3633 | * remains, it must be due to another use by the display engine. | |
3634 | */ | |
d7f46fc4 | 3635 | return i915_gem_obj_to_ggtt(obj)->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3636 | } |
3637 | ||
b9241ea3 | 3638 | /* |
2da3b9b9 CW |
3639 | * Prepare buffer for display plane (scanout, cursors, etc). |
3640 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3641 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3642 | */ |
3643 | int | |
2da3b9b9 CW |
3644 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3645 | u32 alignment, | |
919926ae | 3646 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3647 | { |
2da3b9b9 | 3648 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3649 | int ret; |
3650 | ||
0be73284 | 3651 | if (pipelined != obj->ring) { |
2911a35b BW |
3652 | ret = i915_gem_object_sync(obj, pipelined); |
3653 | if (ret) | |
b9241ea3 ZW |
3654 | return ret; |
3655 | } | |
3656 | ||
cc98b413 CW |
3657 | /* Mark the pin_display early so that we account for the |
3658 | * display coherency whilst setting up the cache domains. | |
3659 | */ | |
3660 | obj->pin_display = true; | |
3661 | ||
a7ef0640 EA |
3662 | /* The display engine is not coherent with the LLC cache on gen6. As |
3663 | * a result, we make sure that the pinning that is about to occur is | |
3664 | * done with uncached PTEs. This is lowest common denominator for all | |
3665 | * chipsets. | |
3666 | * | |
3667 | * However for gen6+, we could do better by using the GFDT bit instead | |
3668 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3669 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3670 | */ | |
651d794f CW |
3671 | ret = i915_gem_object_set_cache_level(obj, |
3672 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3673 | if (ret) |
cc98b413 | 3674 | goto err_unpin_display; |
a7ef0640 | 3675 | |
2da3b9b9 CW |
3676 | /* As the user may map the buffer once pinned in the display plane |
3677 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3678 | * always use map_and_fenceable for all scanout buffers. | |
3679 | */ | |
1ec9e26d | 3680 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3681 | if (ret) |
cc98b413 | 3682 | goto err_unpin_display; |
2da3b9b9 | 3683 | |
2c22569b | 3684 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3685 | |
2da3b9b9 | 3686 | old_write_domain = obj->base.write_domain; |
05394f39 | 3687 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3688 | |
3689 | /* It should now be out of any other write domains, and we can update | |
3690 | * the domain values for our changes. | |
3691 | */ | |
e5f1d962 | 3692 | obj->base.write_domain = 0; |
05394f39 | 3693 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3694 | |
3695 | trace_i915_gem_object_change_domain(obj, | |
3696 | old_read_domains, | |
2da3b9b9 | 3697 | old_write_domain); |
b9241ea3 ZW |
3698 | |
3699 | return 0; | |
cc98b413 CW |
3700 | |
3701 | err_unpin_display: | |
3702 | obj->pin_display = is_pin_display(obj); | |
3703 | return ret; | |
3704 | } | |
3705 | ||
3706 | void | |
3707 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3708 | { | |
d7f46fc4 | 3709 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3710 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3711 | } |
3712 | ||
85345517 | 3713 | int |
a8198eea | 3714 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3715 | { |
88241785 CW |
3716 | int ret; |
3717 | ||
a8198eea | 3718 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3719 | return 0; |
3720 | ||
0201f1ec | 3721 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3722 | if (ret) |
3723 | return ret; | |
3724 | ||
a8198eea CW |
3725 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3726 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3727 | return 0; |
85345517 CW |
3728 | } |
3729 | ||
e47c68e9 EA |
3730 | /** |
3731 | * Moves a single object to the CPU read, and possibly write domain. | |
3732 | * | |
3733 | * This function returns when the move is complete, including waiting on | |
3734 | * flushes to occur. | |
3735 | */ | |
dabdfe02 | 3736 | int |
919926ae | 3737 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3738 | { |
1c5d22f7 | 3739 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3740 | int ret; |
3741 | ||
8d7e3de1 CW |
3742 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3743 | return 0; | |
3744 | ||
0201f1ec | 3745 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3746 | if (ret) |
3747 | return ret; | |
3748 | ||
e47c68e9 | 3749 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3750 | |
05394f39 CW |
3751 | old_write_domain = obj->base.write_domain; |
3752 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3753 | |
e47c68e9 | 3754 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3755 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3756 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3757 | |
05394f39 | 3758 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3759 | } |
3760 | ||
3761 | /* It should now be out of any other write domains, and we can update | |
3762 | * the domain values for our changes. | |
3763 | */ | |
05394f39 | 3764 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3765 | |
3766 | /* If we're writing through the CPU, then the GPU read domains will | |
3767 | * need to be invalidated at next use. | |
3768 | */ | |
3769 | if (write) { | |
05394f39 CW |
3770 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3771 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3772 | } |
2ef7eeaa | 3773 | |
1c5d22f7 CW |
3774 | trace_i915_gem_object_change_domain(obj, |
3775 | old_read_domains, | |
3776 | old_write_domain); | |
3777 | ||
2ef7eeaa EA |
3778 | return 0; |
3779 | } | |
3780 | ||
673a394b EA |
3781 | /* Throttle our rendering by waiting until the ring has completed our requests |
3782 | * emitted over 20 msec ago. | |
3783 | * | |
b962442e EA |
3784 | * Note that if we were to use the current jiffies each time around the loop, |
3785 | * we wouldn't escape the function with any frames outstanding if the time to | |
3786 | * render a frame was over 20ms. | |
3787 | * | |
673a394b EA |
3788 | * This should get us reasonable parallelism between CPU and GPU but also |
3789 | * relatively low latency when blocking on a particular request to finish. | |
3790 | */ | |
40a5f0de | 3791 | static int |
f787a5f5 | 3792 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3793 | { |
f787a5f5 CW |
3794 | struct drm_i915_private *dev_priv = dev->dev_private; |
3795 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3796 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3797 | struct drm_i915_gem_request *request; |
3798 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3799 | unsigned reset_counter; |
f787a5f5 CW |
3800 | u32 seqno = 0; |
3801 | int ret; | |
93533c29 | 3802 | |
308887aa DV |
3803 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3804 | if (ret) | |
3805 | return ret; | |
3806 | ||
3807 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3808 | if (ret) | |
3809 | return ret; | |
e110e8d6 | 3810 | |
1c25595f | 3811 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3812 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3813 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3814 | break; | |
40a5f0de | 3815 | |
f787a5f5 CW |
3816 | ring = request->ring; |
3817 | seqno = request->seqno; | |
b962442e | 3818 | } |
f69061be | 3819 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3820 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3821 | |
f787a5f5 CW |
3822 | if (seqno == 0) |
3823 | return 0; | |
2bc43b5c | 3824 | |
b29c19b6 | 3825 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
3826 | if (ret == 0) |
3827 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3828 | |
3829 | return ret; | |
3830 | } | |
3831 | ||
673a394b | 3832 | int |
05394f39 | 3833 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3834 | struct i915_address_space *vm, |
05394f39 | 3835 | uint32_t alignment, |
1ec9e26d | 3836 | unsigned flags) |
673a394b | 3837 | { |
07fe0b12 | 3838 | struct i915_vma *vma; |
673a394b EA |
3839 | int ret; |
3840 | ||
bf3d149b | 3841 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 3842 | return -EINVAL; |
07fe0b12 BW |
3843 | |
3844 | vma = i915_gem_obj_to_vma(obj, vm); | |
07fe0b12 | 3845 | if (vma) { |
d7f46fc4 BW |
3846 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3847 | return -EBUSY; | |
3848 | ||
07fe0b12 BW |
3849 | if ((alignment && |
3850 | vma->node.start & (alignment - 1)) || | |
1ec9e26d | 3851 | (flags & PIN_MAPPABLE && !obj->map_and_fenceable)) { |
d7f46fc4 | 3852 | WARN(vma->pin_count, |
ae7d49d8 | 3853 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3854 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3855 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3856 | i915_gem_obj_offset(obj, vm), alignment, |
1ec9e26d | 3857 | flags & PIN_MAPPABLE, |
05394f39 | 3858 | obj->map_and_fenceable); |
07fe0b12 | 3859 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3860 | if (ret) |
3861 | return ret; | |
8ea99c92 DV |
3862 | |
3863 | vma = NULL; | |
ac0c6b5a CW |
3864 | } |
3865 | } | |
3866 | ||
8ea99c92 | 3867 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
3868 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
3869 | if (IS_ERR(vma)) | |
3870 | return PTR_ERR(vma); | |
22c344e9 | 3871 | } |
76446cac | 3872 | |
8ea99c92 DV |
3873 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
3874 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
74898d7e | 3875 | |
8ea99c92 | 3876 | vma->pin_count++; |
1ec9e26d DV |
3877 | if (flags & PIN_MAPPABLE) |
3878 | obj->pin_mappable |= true; | |
673a394b EA |
3879 | |
3880 | return 0; | |
3881 | } | |
3882 | ||
3883 | void | |
d7f46fc4 | 3884 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3885 | { |
d7f46fc4 | 3886 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 3887 | |
d7f46fc4 BW |
3888 | BUG_ON(!vma); |
3889 | BUG_ON(vma->pin_count == 0); | |
3890 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
3891 | ||
3892 | if (--vma->pin_count == 0) | |
6299f992 | 3893 | obj->pin_mappable = false; |
673a394b EA |
3894 | } |
3895 | ||
3896 | int | |
3897 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3898 | struct drm_file *file) |
673a394b EA |
3899 | { |
3900 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3901 | struct drm_i915_gem_object *obj; |
673a394b EA |
3902 | int ret; |
3903 | ||
02f6bccc DV |
3904 | if (INTEL_INFO(dev)->gen >= 6) |
3905 | return -ENODEV; | |
3906 | ||
1d7cfea1 CW |
3907 | ret = i915_mutex_lock_interruptible(dev); |
3908 | if (ret) | |
3909 | return ret; | |
673a394b | 3910 | |
05394f39 | 3911 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3912 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3913 | ret = -ENOENT; |
3914 | goto unlock; | |
673a394b | 3915 | } |
673a394b | 3916 | |
05394f39 | 3917 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 3918 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
8c99e57d | 3919 | ret = -EFAULT; |
1d7cfea1 | 3920 | goto out; |
3ef94daa CW |
3921 | } |
3922 | ||
05394f39 | 3923 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
bd9b6a4e | 3924 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 3925 | args->handle); |
1d7cfea1 CW |
3926 | ret = -EINVAL; |
3927 | goto out; | |
79e53945 JB |
3928 | } |
3929 | ||
aa5f8021 DV |
3930 | if (obj->user_pin_count == ULONG_MAX) { |
3931 | ret = -EBUSY; | |
3932 | goto out; | |
3933 | } | |
3934 | ||
93be8788 | 3935 | if (obj->user_pin_count == 0) { |
1ec9e26d | 3936 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
1d7cfea1 CW |
3937 | if (ret) |
3938 | goto out; | |
673a394b EA |
3939 | } |
3940 | ||
93be8788 CW |
3941 | obj->user_pin_count++; |
3942 | obj->pin_filp = file; | |
3943 | ||
f343c5f6 | 3944 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 3945 | out: |
05394f39 | 3946 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3947 | unlock: |
673a394b | 3948 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3949 | return ret; |
673a394b EA |
3950 | } |
3951 | ||
3952 | int | |
3953 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3954 | struct drm_file *file) |
673a394b EA |
3955 | { |
3956 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3957 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3958 | int ret; |
673a394b | 3959 | |
1d7cfea1 CW |
3960 | ret = i915_mutex_lock_interruptible(dev); |
3961 | if (ret) | |
3962 | return ret; | |
673a394b | 3963 | |
05394f39 | 3964 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3965 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3966 | ret = -ENOENT; |
3967 | goto unlock; | |
673a394b | 3968 | } |
76c1dec1 | 3969 | |
05394f39 | 3970 | if (obj->pin_filp != file) { |
bd9b6a4e | 3971 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 3972 | args->handle); |
1d7cfea1 CW |
3973 | ret = -EINVAL; |
3974 | goto out; | |
79e53945 | 3975 | } |
05394f39 CW |
3976 | obj->user_pin_count--; |
3977 | if (obj->user_pin_count == 0) { | |
3978 | obj->pin_filp = NULL; | |
d7f46fc4 | 3979 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 3980 | } |
673a394b | 3981 | |
1d7cfea1 | 3982 | out: |
05394f39 | 3983 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3984 | unlock: |
673a394b | 3985 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3986 | return ret; |
673a394b EA |
3987 | } |
3988 | ||
3989 | int | |
3990 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3991 | struct drm_file *file) |
673a394b EA |
3992 | { |
3993 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3994 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3995 | int ret; |
3996 | ||
76c1dec1 | 3997 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3998 | if (ret) |
76c1dec1 | 3999 | return ret; |
673a394b | 4000 | |
05394f39 | 4001 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4002 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4003 | ret = -ENOENT; |
4004 | goto unlock; | |
673a394b | 4005 | } |
d1b851fc | 4006 | |
0be555b6 CW |
4007 | /* Count all active objects as busy, even if they are currently not used |
4008 | * by the gpu. Users of this interface expect objects to eventually | |
4009 | * become non-busy without any further actions, therefore emit any | |
4010 | * necessary flushes here. | |
c4de0a5d | 4011 | */ |
30dfebf3 | 4012 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4013 | |
30dfebf3 | 4014 | args->busy = obj->active; |
e9808edd CW |
4015 | if (obj->ring) { |
4016 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4017 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4018 | } | |
673a394b | 4019 | |
05394f39 | 4020 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4021 | unlock: |
673a394b | 4022 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4023 | return ret; |
673a394b EA |
4024 | } |
4025 | ||
4026 | int | |
4027 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4028 | struct drm_file *file_priv) | |
4029 | { | |
0206e353 | 4030 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4031 | } |
4032 | ||
3ef94daa CW |
4033 | int |
4034 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4035 | struct drm_file *file_priv) | |
4036 | { | |
4037 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4038 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4039 | int ret; |
3ef94daa CW |
4040 | |
4041 | switch (args->madv) { | |
4042 | case I915_MADV_DONTNEED: | |
4043 | case I915_MADV_WILLNEED: | |
4044 | break; | |
4045 | default: | |
4046 | return -EINVAL; | |
4047 | } | |
4048 | ||
1d7cfea1 CW |
4049 | ret = i915_mutex_lock_interruptible(dev); |
4050 | if (ret) | |
4051 | return ret; | |
4052 | ||
05394f39 | 4053 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4054 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4055 | ret = -ENOENT; |
4056 | goto unlock; | |
3ef94daa | 4057 | } |
3ef94daa | 4058 | |
d7f46fc4 | 4059 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4060 | ret = -EINVAL; |
4061 | goto out; | |
3ef94daa CW |
4062 | } |
4063 | ||
05394f39 CW |
4064 | if (obj->madv != __I915_MADV_PURGED) |
4065 | obj->madv = args->madv; | |
3ef94daa | 4066 | |
6c085a72 CW |
4067 | /* if the object is no longer attached, discard its backing storage */ |
4068 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4069 | i915_gem_object_truncate(obj); |
4070 | ||
05394f39 | 4071 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4072 | |
1d7cfea1 | 4073 | out: |
05394f39 | 4074 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4075 | unlock: |
3ef94daa | 4076 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4077 | return ret; |
3ef94daa CW |
4078 | } |
4079 | ||
37e680a1 CW |
4080 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4081 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4082 | { |
35c20a60 | 4083 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4084 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4085 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4086 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4087 | |
37e680a1 CW |
4088 | obj->ops = ops; |
4089 | ||
0327d6ba CW |
4090 | obj->fence_reg = I915_FENCE_REG_NONE; |
4091 | obj->madv = I915_MADV_WILLNEED; | |
4092 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4093 | obj->map_and_fenceable = true; | |
4094 | ||
4095 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4096 | } | |
4097 | ||
37e680a1 CW |
4098 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4099 | .get_pages = i915_gem_object_get_pages_gtt, | |
4100 | .put_pages = i915_gem_object_put_pages_gtt, | |
4101 | }; | |
4102 | ||
05394f39 CW |
4103 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4104 | size_t size) | |
ac52bc56 | 4105 | { |
c397b908 | 4106 | struct drm_i915_gem_object *obj; |
5949eac4 | 4107 | struct address_space *mapping; |
1a240d4d | 4108 | gfp_t mask; |
ac52bc56 | 4109 | |
42dcedd4 | 4110 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4111 | if (obj == NULL) |
4112 | return NULL; | |
673a394b | 4113 | |
c397b908 | 4114 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4115 | i915_gem_object_free(obj); |
c397b908 DV |
4116 | return NULL; |
4117 | } | |
673a394b | 4118 | |
bed1ea95 CW |
4119 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4120 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4121 | /* 965gm cannot relocate objects above 4GiB. */ | |
4122 | mask &= ~__GFP_HIGHMEM; | |
4123 | mask |= __GFP_DMA32; | |
4124 | } | |
4125 | ||
496ad9aa | 4126 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4127 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4128 | |
37e680a1 | 4129 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4130 | |
c397b908 DV |
4131 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4132 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4133 | |
3d29b842 ED |
4134 | if (HAS_LLC(dev)) { |
4135 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4136 | * cache) for about a 10% performance improvement |
4137 | * compared to uncached. Graphics requests other than | |
4138 | * display scanout are coherent with the CPU in | |
4139 | * accessing this cache. This means in this mode we | |
4140 | * don't need to clflush on the CPU side, and on the | |
4141 | * GPU side we only need to flush internal caches to | |
4142 | * get data visible to the CPU. | |
4143 | * | |
4144 | * However, we maintain the display planes as UC, and so | |
4145 | * need to rebind when first used as such. | |
4146 | */ | |
4147 | obj->cache_level = I915_CACHE_LLC; | |
4148 | } else | |
4149 | obj->cache_level = I915_CACHE_NONE; | |
4150 | ||
d861e338 DV |
4151 | trace_i915_gem_object_create(obj); |
4152 | ||
05394f39 | 4153 | return obj; |
c397b908 DV |
4154 | } |
4155 | ||
1488fc08 | 4156 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4157 | { |
1488fc08 | 4158 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4159 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4160 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4161 | struct i915_vma *vma, *next; |
673a394b | 4162 | |
f65c9168 PZ |
4163 | intel_runtime_pm_get(dev_priv); |
4164 | ||
26e12f89 CW |
4165 | trace_i915_gem_object_destroy(obj); |
4166 | ||
1488fc08 CW |
4167 | if (obj->phys_obj) |
4168 | i915_gem_detach_phys_object(dev, obj); | |
4169 | ||
07fe0b12 | 4170 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4171 | int ret; |
4172 | ||
4173 | vma->pin_count = 0; | |
4174 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4175 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4176 | bool was_interruptible; | |
1488fc08 | 4177 | |
07fe0b12 BW |
4178 | was_interruptible = dev_priv->mm.interruptible; |
4179 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4180 | |
07fe0b12 | 4181 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4182 | |
07fe0b12 BW |
4183 | dev_priv->mm.interruptible = was_interruptible; |
4184 | } | |
1488fc08 CW |
4185 | } |
4186 | ||
1d64ae71 BW |
4187 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4188 | * before progressing. */ | |
4189 | if (obj->stolen) | |
4190 | i915_gem_object_unpin_pages(obj); | |
4191 | ||
401c29f6 BW |
4192 | if (WARN_ON(obj->pages_pin_count)) |
4193 | obj->pages_pin_count = 0; | |
37e680a1 | 4194 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4195 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4196 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4197 | |
9da3da66 CW |
4198 | BUG_ON(obj->pages); |
4199 | ||
2f745ad3 CW |
4200 | if (obj->base.import_attach) |
4201 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4202 | |
05394f39 CW |
4203 | drm_gem_object_release(&obj->base); |
4204 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4205 | |
05394f39 | 4206 | kfree(obj->bit_17); |
42dcedd4 | 4207 | i915_gem_object_free(obj); |
f65c9168 PZ |
4208 | |
4209 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4210 | } |
4211 | ||
e656a6cb | 4212 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4213 | struct i915_address_space *vm) |
e656a6cb DV |
4214 | { |
4215 | struct i915_vma *vma; | |
4216 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4217 | if (vma->vm == vm) | |
4218 | return vma; | |
4219 | ||
4220 | return NULL; | |
4221 | } | |
4222 | ||
2f633156 BW |
4223 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4224 | { | |
4225 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4226 | |
4227 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4228 | if (!list_empty(&vma->exec_list)) | |
4229 | return; | |
4230 | ||
8b9c2b94 | 4231 | list_del(&vma->vma_link); |
b93dab6e | 4232 | |
2f633156 BW |
4233 | kfree(vma); |
4234 | } | |
4235 | ||
29105ccc | 4236 | int |
45c5f202 | 4237 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4238 | { |
3e31c6c0 | 4239 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4240 | int ret = 0; |
28dfe52a | 4241 | |
45c5f202 | 4242 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4243 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4244 | goto err; |
28dfe52a | 4245 | |
b2da9fe5 | 4246 | ret = i915_gpu_idle(dev); |
f7403347 | 4247 | if (ret) |
45c5f202 | 4248 | goto err; |
f7403347 | 4249 | |
b2da9fe5 | 4250 | i915_gem_retire_requests(dev); |
673a394b | 4251 | |
29105ccc | 4252 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4253 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4254 | i915_gem_evict_everything(dev); |
29105ccc | 4255 | |
29105ccc | 4256 | i915_kernel_lost_context(dev); |
6dbe2772 | 4257 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4258 | |
45c5f202 CW |
4259 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4260 | * We need to replace this with a semaphore, or something. | |
4261 | * And not confound ums.mm_suspended! | |
4262 | */ | |
4263 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4264 | DRIVER_MODESET); | |
4265 | mutex_unlock(&dev->struct_mutex); | |
4266 | ||
4267 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4268 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
b29c19b6 | 4269 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4270 | |
673a394b | 4271 | return 0; |
45c5f202 CW |
4272 | |
4273 | err: | |
4274 | mutex_unlock(&dev->struct_mutex); | |
4275 | return ret; | |
673a394b EA |
4276 | } |
4277 | ||
c3787e2e | 4278 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice) |
b9524a1e | 4279 | { |
c3787e2e | 4280 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4281 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4282 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4283 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4284 | int i, ret; |
b9524a1e | 4285 | |
040d2baa | 4286 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4287 | return 0; |
b9524a1e | 4288 | |
c3787e2e BW |
4289 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4290 | if (ret) | |
4291 | return ret; | |
b9524a1e | 4292 | |
c3787e2e BW |
4293 | /* |
4294 | * Note: We do not worry about the concurrent register cacheline hang | |
4295 | * here because no other code should access these registers other than | |
4296 | * at initialization time. | |
4297 | */ | |
b9524a1e | 4298 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4299 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4300 | intel_ring_emit(ring, reg_base + i); | |
4301 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4302 | } |
4303 | ||
c3787e2e | 4304 | intel_ring_advance(ring); |
b9524a1e | 4305 | |
c3787e2e | 4306 | return ret; |
b9524a1e BW |
4307 | } |
4308 | ||
f691e2f4 DV |
4309 | void i915_gem_init_swizzling(struct drm_device *dev) |
4310 | { | |
3e31c6c0 | 4311 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4312 | |
11782b02 | 4313 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4314 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4315 | return; | |
4316 | ||
4317 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4318 | DISP_TILE_SURFACE_SWIZZLING); | |
4319 | ||
11782b02 DV |
4320 | if (IS_GEN5(dev)) |
4321 | return; | |
4322 | ||
f691e2f4 DV |
4323 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4324 | if (IS_GEN6(dev)) | |
6b26c86d | 4325 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4326 | else if (IS_GEN7(dev)) |
6b26c86d | 4327 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4328 | else if (IS_GEN8(dev)) |
4329 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4330 | else |
4331 | BUG(); | |
f691e2f4 | 4332 | } |
e21af88d | 4333 | |
67b1b571 CW |
4334 | static bool |
4335 | intel_enable_blt(struct drm_device *dev) | |
4336 | { | |
4337 | if (!HAS_BLT(dev)) | |
4338 | return false; | |
4339 | ||
4340 | /* The blitter was dysfunctional on early prototypes */ | |
4341 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4342 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4343 | " graphics performance will be degraded.\n"); | |
4344 | return false; | |
4345 | } | |
4346 | ||
4347 | return true; | |
4348 | } | |
4349 | ||
4fc7c971 | 4350 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4351 | { |
4fc7c971 | 4352 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4353 | int ret; |
68f95ba9 | 4354 | |
5c1143bb | 4355 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4356 | if (ret) |
b6913e4b | 4357 | return ret; |
68f95ba9 CW |
4358 | |
4359 | if (HAS_BSD(dev)) { | |
5c1143bb | 4360 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4361 | if (ret) |
4362 | goto cleanup_render_ring; | |
d1b851fc | 4363 | } |
68f95ba9 | 4364 | |
67b1b571 | 4365 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4366 | ret = intel_init_blt_ring_buffer(dev); |
4367 | if (ret) | |
4368 | goto cleanup_bsd_ring; | |
4369 | } | |
4370 | ||
9a8a2213 BW |
4371 | if (HAS_VEBOX(dev)) { |
4372 | ret = intel_init_vebox_ring_buffer(dev); | |
4373 | if (ret) | |
4374 | goto cleanup_blt_ring; | |
4375 | } | |
4376 | ||
4377 | ||
99433931 | 4378 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4379 | if (ret) |
9a8a2213 | 4380 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4381 | |
4382 | return 0; | |
4383 | ||
9a8a2213 BW |
4384 | cleanup_vebox_ring: |
4385 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4386 | cleanup_blt_ring: |
4387 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4388 | cleanup_bsd_ring: | |
4389 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4390 | cleanup_render_ring: | |
4391 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4392 | ||
4393 | return ret; | |
4394 | } | |
4395 | ||
4396 | int | |
4397 | i915_gem_init_hw(struct drm_device *dev) | |
4398 | { | |
3e31c6c0 | 4399 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4400 | int ret, i; |
4fc7c971 BW |
4401 | |
4402 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4403 | return -EIO; | |
4404 | ||
59124506 | 4405 | if (dev_priv->ellc_size) |
05e21cc4 | 4406 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4407 | |
0bf21347 VS |
4408 | if (IS_HASWELL(dev)) |
4409 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4410 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4411 | |
88a2b2a3 | 4412 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4413 | if (IS_IVYBRIDGE(dev)) { |
4414 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4415 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4416 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4417 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4418 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4419 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4420 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4421 | } | |
88a2b2a3 BW |
4422 | } |
4423 | ||
4fc7c971 BW |
4424 | i915_gem_init_swizzling(dev); |
4425 | ||
4426 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4427 | if (ret) |
4428 | return ret; | |
4429 | ||
c3787e2e BW |
4430 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4431 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4432 | ||
254f965c | 4433 | /* |
2fa48d8d BW |
4434 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4435 | * default context switch however is something we'd like to do after | |
4436 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4437 | * goes with our code better). Context switching requires rings (for | |
4438 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4439 | */ |
2fa48d8d | 4440 | ret = i915_gem_context_enable(dev_priv); |
8245be31 | 4441 | if (ret) { |
2fa48d8d BW |
4442 | DRM_ERROR("Context enable failed %d\n", ret); |
4443 | goto err_out; | |
b7c36d25 | 4444 | } |
e21af88d | 4445 | |
68f95ba9 | 4446 | return 0; |
2fa48d8d BW |
4447 | |
4448 | err_out: | |
4449 | i915_gem_cleanup_ringbuffer(dev); | |
4450 | return ret; | |
8187a2b7 ZN |
4451 | } |
4452 | ||
1070a42b CW |
4453 | int i915_gem_init(struct drm_device *dev) |
4454 | { | |
4455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4456 | int ret; |
4457 | ||
1070a42b | 4458 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4459 | |
4460 | if (IS_VALLEYVIEW(dev)) { | |
4461 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4462 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4463 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4464 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4465 | } | |
4466 | ||
d7e5008f | 4467 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4468 | |
2fa48d8d | 4469 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4470 | if (ret) { |
4471 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4472 | return ret; |
e3848694 | 4473 | } |
2fa48d8d | 4474 | |
1070a42b CW |
4475 | ret = i915_gem_init_hw(dev); |
4476 | mutex_unlock(&dev->struct_mutex); | |
4477 | if (ret) { | |
bdf4fd7e | 4478 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
2fa48d8d | 4479 | i915_gem_context_fini(dev); |
c39538a8 | 4480 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
1070a42b CW |
4481 | return ret; |
4482 | } | |
4483 | ||
53ca26ca DV |
4484 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4485 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4486 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4487 | return 0; |
4488 | } | |
4489 | ||
8187a2b7 ZN |
4490 | void |
4491 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4492 | { | |
3e31c6c0 | 4493 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4494 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4495 | int i; |
8187a2b7 | 4496 | |
b4519513 CW |
4497 | for_each_ring(ring, dev_priv, i) |
4498 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4499 | } |
4500 | ||
673a394b EA |
4501 | int |
4502 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4503 | struct drm_file *file_priv) | |
4504 | { | |
db1b76ca | 4505 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4506 | int ret; |
673a394b | 4507 | |
79e53945 JB |
4508 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4509 | return 0; | |
4510 | ||
1f83fee0 | 4511 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4512 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4513 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4514 | } |
4515 | ||
673a394b | 4516 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4517 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4518 | |
f691e2f4 | 4519 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4520 | if (ret != 0) { |
4521 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4522 | return ret; |
d816f6ac | 4523 | } |
9bb2d6f9 | 4524 | |
5cef07e1 | 4525 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4526 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4527 | |
5f35308b CW |
4528 | ret = drm_irq_install(dev); |
4529 | if (ret) | |
4530 | goto cleanup_ringbuffer; | |
dbb19d30 | 4531 | |
673a394b | 4532 | return 0; |
5f35308b CW |
4533 | |
4534 | cleanup_ringbuffer: | |
4535 | mutex_lock(&dev->struct_mutex); | |
4536 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4537 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4538 | mutex_unlock(&dev->struct_mutex); |
4539 | ||
4540 | return ret; | |
673a394b EA |
4541 | } |
4542 | ||
4543 | int | |
4544 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4545 | struct drm_file *file_priv) | |
4546 | { | |
79e53945 JB |
4547 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4548 | return 0; | |
4549 | ||
dbb19d30 | 4550 | drm_irq_uninstall(dev); |
db1b76ca | 4551 | |
45c5f202 | 4552 | return i915_gem_suspend(dev); |
673a394b EA |
4553 | } |
4554 | ||
4555 | void | |
4556 | i915_gem_lastclose(struct drm_device *dev) | |
4557 | { | |
4558 | int ret; | |
673a394b | 4559 | |
e806b495 EA |
4560 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4561 | return; | |
4562 | ||
45c5f202 | 4563 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4564 | if (ret) |
4565 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4566 | } |
4567 | ||
64193406 CW |
4568 | static void |
4569 | init_ring_lists(struct intel_ring_buffer *ring) | |
4570 | { | |
4571 | INIT_LIST_HEAD(&ring->active_list); | |
4572 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4573 | } |
4574 | ||
7e0d96bc BW |
4575 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4576 | struct i915_address_space *vm) | |
fc8c067e | 4577 | { |
7e0d96bc BW |
4578 | if (!i915_is_ggtt(vm)) |
4579 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4580 | vm->dev = dev_priv->dev; |
4581 | INIT_LIST_HEAD(&vm->active_list); | |
4582 | INIT_LIST_HEAD(&vm->inactive_list); | |
4583 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4584 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4585 | } |
4586 | ||
673a394b EA |
4587 | void |
4588 | i915_gem_load(struct drm_device *dev) | |
4589 | { | |
3e31c6c0 | 4590 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4591 | int i; |
4592 | ||
4593 | dev_priv->slab = | |
4594 | kmem_cache_create("i915_gem_object", | |
4595 | sizeof(struct drm_i915_gem_object), 0, | |
4596 | SLAB_HWCACHE_ALIGN, | |
4597 | NULL); | |
673a394b | 4598 | |
fc8c067e BW |
4599 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4600 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4601 | ||
a33afea5 | 4602 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4603 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4604 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4605 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4606 | for (i = 0; i < I915_NUM_RINGS; i++) |
4607 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4608 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4609 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4610 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4611 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4612 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4613 | i915_gem_idle_work_handler); | |
1f83fee0 | 4614 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4615 | |
94400120 DA |
4616 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4617 | if (IS_GEN3(dev)) { | |
50743298 DV |
4618 | I915_WRITE(MI_ARB_STATE, |
4619 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4620 | } |
4621 | ||
72bfa19c CW |
4622 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4623 | ||
de151cf6 | 4624 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4625 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4626 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4627 | |
42b5aeab VS |
4628 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4629 | dev_priv->num_fence_regs = 32; | |
4630 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4631 | dev_priv->num_fence_regs = 16; |
4632 | else | |
4633 | dev_priv->num_fence_regs = 8; | |
4634 | ||
b5aa8a0f | 4635 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4636 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4637 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4638 | |
673a394b | 4639 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4640 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4641 | |
ce453d81 CW |
4642 | dev_priv->mm.interruptible = true; |
4643 | ||
7dc19d5a DC |
4644 | dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan; |
4645 | dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count; | |
17250b71 CW |
4646 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
4647 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4648 | } |
71acb5eb DA |
4649 | |
4650 | /* | |
4651 | * Create a physically contiguous memory object for this object | |
4652 | * e.g. for cursor + overlay regs | |
4653 | */ | |
995b6762 CW |
4654 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4655 | int id, int size, int align) | |
71acb5eb | 4656 | { |
3e31c6c0 | 4657 | struct drm_i915_private *dev_priv = dev->dev_private; |
71acb5eb DA |
4658 | struct drm_i915_gem_phys_object *phys_obj; |
4659 | int ret; | |
4660 | ||
4661 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4662 | return 0; | |
4663 | ||
b14c5679 | 4664 | phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL); |
71acb5eb DA |
4665 | if (!phys_obj) |
4666 | return -ENOMEM; | |
4667 | ||
4668 | phys_obj->id = id; | |
4669 | ||
6eeefaf3 | 4670 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4671 | if (!phys_obj->handle) { |
4672 | ret = -ENOMEM; | |
4673 | goto kfree_obj; | |
4674 | } | |
4675 | #ifdef CONFIG_X86 | |
4676 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4677 | #endif | |
4678 | ||
4679 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4680 | ||
4681 | return 0; | |
4682 | kfree_obj: | |
9a298b2a | 4683 | kfree(phys_obj); |
71acb5eb DA |
4684 | return ret; |
4685 | } | |
4686 | ||
995b6762 | 4687 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb | 4688 | { |
3e31c6c0 | 4689 | struct drm_i915_private *dev_priv = dev->dev_private; |
71acb5eb DA |
4690 | struct drm_i915_gem_phys_object *phys_obj; |
4691 | ||
4692 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4693 | return; | |
4694 | ||
4695 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4696 | if (phys_obj->cur_obj) { | |
4697 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4698 | } | |
4699 | ||
4700 | #ifdef CONFIG_X86 | |
4701 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4702 | #endif | |
4703 | drm_pci_free(dev, phys_obj->handle); | |
4704 | kfree(phys_obj); | |
4705 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4706 | } | |
4707 | ||
4708 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4709 | { | |
4710 | int i; | |
4711 | ||
260883c8 | 4712 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4713 | i915_gem_free_phys_object(dev, i); |
4714 | } | |
4715 | ||
4716 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4717 | struct drm_i915_gem_object *obj) |
71acb5eb | 4718 | { |
496ad9aa | 4719 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4720 | char *vaddr; |
71acb5eb | 4721 | int i; |
71acb5eb DA |
4722 | int page_count; |
4723 | ||
05394f39 | 4724 | if (!obj->phys_obj) |
71acb5eb | 4725 | return; |
05394f39 | 4726 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4727 | |
05394f39 | 4728 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4729 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4730 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4731 | if (!IS_ERR(page)) { |
4732 | char *dst = kmap_atomic(page); | |
4733 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4734 | kunmap_atomic(dst); | |
4735 | ||
4736 | drm_clflush_pages(&page, 1); | |
4737 | ||
4738 | set_page_dirty(page); | |
4739 | mark_page_accessed(page); | |
4740 | page_cache_release(page); | |
4741 | } | |
71acb5eb | 4742 | } |
e76e9aeb | 4743 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4744 | |
05394f39 CW |
4745 | obj->phys_obj->cur_obj = NULL; |
4746 | obj->phys_obj = NULL; | |
71acb5eb DA |
4747 | } |
4748 | ||
4749 | int | |
4750 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4751 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4752 | int id, |
4753 | int align) | |
71acb5eb | 4754 | { |
496ad9aa | 4755 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
3e31c6c0 | 4756 | struct drm_i915_private *dev_priv = dev->dev_private; |
71acb5eb DA |
4757 | int ret = 0; |
4758 | int page_count; | |
4759 | int i; | |
4760 | ||
4761 | if (id > I915_MAX_PHYS_OBJECT) | |
4762 | return -EINVAL; | |
4763 | ||
05394f39 CW |
4764 | if (obj->phys_obj) { |
4765 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4766 | return 0; |
4767 | i915_gem_detach_phys_object(dev, obj); | |
4768 | } | |
4769 | ||
71acb5eb DA |
4770 | /* create a new object */ |
4771 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4772 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4773 | obj->base.size, align); |
71acb5eb | 4774 | if (ret) { |
05394f39 CW |
4775 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4776 | id, obj->base.size); | |
e5281ccd | 4777 | return ret; |
71acb5eb DA |
4778 | } |
4779 | } | |
4780 | ||
4781 | /* bind to the object */ | |
05394f39 CW |
4782 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4783 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4784 | |
05394f39 | 4785 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4786 | |
4787 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4788 | struct page *page; |
4789 | char *dst, *src; | |
4790 | ||
5949eac4 | 4791 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4792 | if (IS_ERR(page)) |
4793 | return PTR_ERR(page); | |
71acb5eb | 4794 | |
ff75b9bc | 4795 | src = kmap_atomic(page); |
05394f39 | 4796 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4797 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4798 | kunmap_atomic(src); |
71acb5eb | 4799 | |
e5281ccd CW |
4800 | mark_page_accessed(page); |
4801 | page_cache_release(page); | |
4802 | } | |
d78b47b9 | 4803 | |
71acb5eb | 4804 | return 0; |
71acb5eb DA |
4805 | } |
4806 | ||
4807 | static int | |
05394f39 CW |
4808 | i915_gem_phys_pwrite(struct drm_device *dev, |
4809 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4810 | struct drm_i915_gem_pwrite *args, |
4811 | struct drm_file *file_priv) | |
4812 | { | |
05394f39 | 4813 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4814 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4815 | |
b47b30cc CW |
4816 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4817 | unsigned long unwritten; | |
4818 | ||
4819 | /* The physical object once assigned is fixed for the lifetime | |
4820 | * of the obj, so we can safely drop the lock and continue | |
4821 | * to access vaddr. | |
4822 | */ | |
4823 | mutex_unlock(&dev->struct_mutex); | |
4824 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4825 | mutex_lock(&dev->struct_mutex); | |
4826 | if (unwritten) | |
4827 | return -EFAULT; | |
4828 | } | |
71acb5eb | 4829 | |
e76e9aeb | 4830 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4831 | return 0; |
4832 | } | |
b962442e | 4833 | |
f787a5f5 | 4834 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4835 | { |
f787a5f5 | 4836 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4837 | |
b29c19b6 CW |
4838 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4839 | ||
b962442e EA |
4840 | /* Clean up our request list when the client is going away, so that |
4841 | * later retire_requests won't dereference our soon-to-be-gone | |
4842 | * file_priv. | |
4843 | */ | |
1c25595f | 4844 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4845 | while (!list_empty(&file_priv->mm.request_list)) { |
4846 | struct drm_i915_gem_request *request; | |
4847 | ||
4848 | request = list_first_entry(&file_priv->mm.request_list, | |
4849 | struct drm_i915_gem_request, | |
4850 | client_list); | |
4851 | list_del(&request->client_list); | |
4852 | request->file_priv = NULL; | |
4853 | } | |
1c25595f | 4854 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4855 | } |
31169714 | 4856 | |
b29c19b6 CW |
4857 | static void |
4858 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
4859 | { | |
4860 | struct drm_i915_file_private *file_priv = | |
4861 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
4862 | ||
4863 | atomic_set(&file_priv->rps_wait_boost, false); | |
4864 | } | |
4865 | ||
4866 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4867 | { | |
4868 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4869 | int ret; |
b29c19b6 CW |
4870 | |
4871 | DRM_DEBUG_DRIVER("\n"); | |
4872 | ||
4873 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4874 | if (!file_priv) | |
4875 | return -ENOMEM; | |
4876 | ||
4877 | file->driver_priv = file_priv; | |
4878 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 4879 | file_priv->file = file; |
b29c19b6 CW |
4880 | |
4881 | spin_lock_init(&file_priv->mm.lock); | |
4882 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4883 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
4884 | i915_gem_file_idle_work_handler); | |
4885 | ||
e422b888 BW |
4886 | ret = i915_gem_context_open(dev, file); |
4887 | if (ret) | |
4888 | kfree(file_priv); | |
b29c19b6 | 4889 | |
e422b888 | 4890 | return ret; |
b29c19b6 CW |
4891 | } |
4892 | ||
5774506f CW |
4893 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4894 | { | |
4895 | if (!mutex_is_locked(mutex)) | |
4896 | return false; | |
4897 | ||
4898 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4899 | return mutex->owner == task; | |
4900 | #else | |
4901 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4902 | return false; | |
4903 | #endif | |
4904 | } | |
4905 | ||
7dc19d5a DC |
4906 | static unsigned long |
4907 | i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc) | |
31169714 | 4908 | { |
17250b71 CW |
4909 | struct drm_i915_private *dev_priv = |
4910 | container_of(shrinker, | |
4911 | struct drm_i915_private, | |
4912 | mm.inactive_shrinker); | |
4913 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4914 | struct drm_i915_gem_object *obj; |
5774506f | 4915 | bool unlock = true; |
7dc19d5a | 4916 | unsigned long count; |
17250b71 | 4917 | |
5774506f CW |
4918 | if (!mutex_trylock(&dev->struct_mutex)) { |
4919 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 4920 | return 0; |
5774506f | 4921 | |
677feac2 | 4922 | if (dev_priv->mm.shrinker_no_lock_stealing) |
d3227046 | 4923 | return 0; |
677feac2 | 4924 | |
5774506f CW |
4925 | unlock = false; |
4926 | } | |
31169714 | 4927 | |
7dc19d5a | 4928 | count = 0; |
35c20a60 | 4929 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 4930 | if (obj->pages_pin_count == 0) |
7dc19d5a | 4931 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
4932 | |
4933 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4934 | if (obj->active) | |
4935 | continue; | |
4936 | ||
d7f46fc4 | 4937 | if (!i915_gem_obj_is_pinned(obj) && obj->pages_pin_count == 0) |
7dc19d5a | 4938 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 4939 | } |
17250b71 | 4940 | |
5774506f CW |
4941 | if (unlock) |
4942 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 4943 | |
7dc19d5a | 4944 | return count; |
31169714 | 4945 | } |
a70a3148 BW |
4946 | |
4947 | /* All the new VM stuff */ | |
4948 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4949 | struct i915_address_space *vm) | |
4950 | { | |
4951 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4952 | struct i915_vma *vma; | |
4953 | ||
6f425321 BW |
4954 | if (!dev_priv->mm.aliasing_ppgtt || |
4955 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
4956 | vm = &dev_priv->gtt.base; |
4957 | ||
4958 | BUG_ON(list_empty(&o->vma_list)); | |
4959 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4960 | if (vma->vm == vm) | |
4961 | return vma->node.start; | |
4962 | ||
4963 | } | |
4964 | return -1; | |
4965 | } | |
4966 | ||
4967 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4968 | struct i915_address_space *vm) | |
4969 | { | |
4970 | struct i915_vma *vma; | |
4971 | ||
4972 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 4973 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4974 | return true; |
4975 | ||
4976 | return false; | |
4977 | } | |
4978 | ||
4979 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
4980 | { | |
5a1d5eb0 | 4981 | struct i915_vma *vma; |
a70a3148 | 4982 | |
5a1d5eb0 CW |
4983 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4984 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
4985 | return true; |
4986 | ||
4987 | return false; | |
4988 | } | |
4989 | ||
4990 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
4991 | struct i915_address_space *vm) | |
4992 | { | |
4993 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4994 | struct i915_vma *vma; | |
4995 | ||
6f425321 BW |
4996 | if (!dev_priv->mm.aliasing_ppgtt || |
4997 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
4998 | vm = &dev_priv->gtt.base; |
4999 | ||
5000 | BUG_ON(list_empty(&o->vma_list)); | |
5001 | ||
5002 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5003 | if (vma->vm == vm) | |
5004 | return vma->node.size; | |
5005 | ||
5006 | return 0; | |
5007 | } | |
5008 | ||
7dc19d5a DC |
5009 | static unsigned long |
5010 | i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc) | |
5011 | { | |
5012 | struct drm_i915_private *dev_priv = | |
5013 | container_of(shrinker, | |
5014 | struct drm_i915_private, | |
5015 | mm.inactive_shrinker); | |
5016 | struct drm_device *dev = dev_priv->dev; | |
7dc19d5a DC |
5017 | unsigned long freed; |
5018 | bool unlock = true; | |
5019 | ||
5020 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5021 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 5022 | return SHRINK_STOP; |
7dc19d5a DC |
5023 | |
5024 | if (dev_priv->mm.shrinker_no_lock_stealing) | |
d3227046 | 5025 | return SHRINK_STOP; |
7dc19d5a DC |
5026 | |
5027 | unlock = false; | |
5028 | } | |
5029 | ||
d9973b43 CW |
5030 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
5031 | if (freed < sc->nr_to_scan) | |
5032 | freed += __i915_gem_shrink(dev_priv, | |
5033 | sc->nr_to_scan - freed, | |
5034 | false); | |
5035 | if (freed < sc->nr_to_scan) | |
7dc19d5a DC |
5036 | freed += i915_gem_shrink_all(dev_priv); |
5037 | ||
5038 | if (unlock) | |
5039 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5040 | |
7dc19d5a DC |
5041 | return freed; |
5042 | } | |
5c2abbea BW |
5043 | |
5044 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
5045 | { | |
5046 | struct i915_vma *vma; | |
5047 | ||
5048 | if (WARN_ON(list_empty(&obj->vma_list))) | |
5049 | return NULL; | |
5050 | ||
5051 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
6e164c33 | 5052 | if (vma->vm != obj_to_ggtt(obj)) |
5c2abbea BW |
5053 | return NULL; |
5054 | ||
5055 | return vma; | |
5056 | } |