Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
2dafb1e0 | 40 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
e47c68e9 EA |
41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
43 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
44 | int write); | |
45 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
46 | uint64_t offset, | |
47 | uint64_t size); | |
48 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
e35a41de DV |
49 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
50 | bool interruptible); | |
de151cf6 JB |
51 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
52 | unsigned alignment); | |
de151cf6 | 53 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
54 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
55 | struct drm_i915_gem_pwrite *args, | |
56 | struct drm_file *file_priv); | |
be72615b | 57 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 58 | |
31169714 CW |
59 | static LIST_HEAD(shrink_list); |
60 | static DEFINE_SPINLOCK(shrink_list_lock); | |
61 | ||
7d1c4804 CW |
62 | static inline bool |
63 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
64 | { | |
65 | return obj_priv->gtt_space && | |
66 | !obj_priv->active && | |
67 | obj_priv->pin_count == 0; | |
68 | } | |
69 | ||
79e53945 JB |
70 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
71 | unsigned long end) | |
673a394b EA |
72 | { |
73 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 74 | |
79e53945 JB |
75 | if (start >= end || |
76 | (start & (PAGE_SIZE - 1)) != 0 || | |
77 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
78 | return -EINVAL; |
79 | } | |
80 | ||
79e53945 JB |
81 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
82 | end - start); | |
673a394b | 83 | |
79e53945 JB |
84 | dev->gtt_total = (uint32_t) (end - start); |
85 | ||
86 | return 0; | |
87 | } | |
673a394b | 88 | |
79e53945 JB |
89 | int |
90 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
91 | struct drm_file *file_priv) | |
92 | { | |
93 | struct drm_i915_gem_init *args = data; | |
94 | int ret; | |
95 | ||
96 | mutex_lock(&dev->struct_mutex); | |
97 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
98 | mutex_unlock(&dev->struct_mutex); |
99 | ||
79e53945 | 100 | return ret; |
673a394b EA |
101 | } |
102 | ||
5a125c3c EA |
103 | int |
104 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
105 | struct drm_file *file_priv) | |
106 | { | |
5a125c3c | 107 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
108 | |
109 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
110 | return -ENODEV; | |
111 | ||
112 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
113 | args->aper_available_size = (args->aper_size - |
114 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
115 | |
116 | return 0; | |
117 | } | |
118 | ||
673a394b EA |
119 | |
120 | /** | |
121 | * Creates a new mm object and returns a handle to it. | |
122 | */ | |
123 | int | |
124 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
125 | struct drm_file *file_priv) | |
126 | { | |
127 | struct drm_i915_gem_create *args = data; | |
128 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
129 | int ret; |
130 | u32 handle; | |
673a394b EA |
131 | |
132 | args->size = roundup(args->size, PAGE_SIZE); | |
133 | ||
134 | /* Allocate the new object */ | |
ac52bc56 | 135 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
136 | if (obj == NULL) |
137 | return -ENOMEM; | |
138 | ||
139 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 CW |
140 | if (ret) { |
141 | drm_gem_object_unreference_unlocked(obj); | |
673a394b | 142 | return ret; |
1dfd9754 | 143 | } |
673a394b | 144 | |
1dfd9754 CW |
145 | /* Sink the floating reference from kref_init(handlecount) */ |
146 | drm_gem_object_handle_unreference_unlocked(obj); | |
673a394b | 147 | |
1dfd9754 | 148 | args->handle = handle; |
673a394b EA |
149 | return 0; |
150 | } | |
151 | ||
eb01459f EA |
152 | static inline int |
153 | fast_shmem_read(struct page **pages, | |
154 | loff_t page_base, int page_offset, | |
155 | char __user *data, | |
156 | int length) | |
157 | { | |
158 | char __iomem *vaddr; | |
2bc43b5c | 159 | int unwritten; |
eb01459f EA |
160 | |
161 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
162 | if (vaddr == NULL) | |
163 | return -ENOMEM; | |
2bc43b5c | 164 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
165 | kunmap_atomic(vaddr, KM_USER0); |
166 | ||
2bc43b5c FM |
167 | if (unwritten) |
168 | return -EFAULT; | |
169 | ||
170 | return 0; | |
eb01459f EA |
171 | } |
172 | ||
280b713b EA |
173 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
174 | { | |
175 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 176 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
177 | |
178 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
179 | obj_priv->tiling_mode != I915_TILING_NONE; | |
180 | } | |
181 | ||
99a03df5 | 182 | static inline void |
40123c1f EA |
183 | slow_shmem_copy(struct page *dst_page, |
184 | int dst_offset, | |
185 | struct page *src_page, | |
186 | int src_offset, | |
187 | int length) | |
188 | { | |
189 | char *dst_vaddr, *src_vaddr; | |
190 | ||
99a03df5 CW |
191 | dst_vaddr = kmap(dst_page); |
192 | src_vaddr = kmap(src_page); | |
40123c1f EA |
193 | |
194 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
195 | ||
99a03df5 CW |
196 | kunmap(src_page); |
197 | kunmap(dst_page); | |
40123c1f EA |
198 | } |
199 | ||
99a03df5 | 200 | static inline void |
280b713b EA |
201 | slow_shmem_bit17_copy(struct page *gpu_page, |
202 | int gpu_offset, | |
203 | struct page *cpu_page, | |
204 | int cpu_offset, | |
205 | int length, | |
206 | int is_read) | |
207 | { | |
208 | char *gpu_vaddr, *cpu_vaddr; | |
209 | ||
210 | /* Use the unswizzled path if this page isn't affected. */ | |
211 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
212 | if (is_read) | |
213 | return slow_shmem_copy(cpu_page, cpu_offset, | |
214 | gpu_page, gpu_offset, length); | |
215 | else | |
216 | return slow_shmem_copy(gpu_page, gpu_offset, | |
217 | cpu_page, cpu_offset, length); | |
218 | } | |
219 | ||
99a03df5 CW |
220 | gpu_vaddr = kmap(gpu_page); |
221 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
222 | |
223 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
224 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
225 | */ | |
226 | while (length > 0) { | |
227 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
228 | int this_length = min(cacheline_end - gpu_offset, length); | |
229 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
230 | ||
231 | if (is_read) { | |
232 | memcpy(cpu_vaddr + cpu_offset, | |
233 | gpu_vaddr + swizzled_gpu_offset, | |
234 | this_length); | |
235 | } else { | |
236 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
237 | cpu_vaddr + cpu_offset, | |
238 | this_length); | |
239 | } | |
240 | cpu_offset += this_length; | |
241 | gpu_offset += this_length; | |
242 | length -= this_length; | |
243 | } | |
244 | ||
99a03df5 CW |
245 | kunmap(cpu_page); |
246 | kunmap(gpu_page); | |
280b713b EA |
247 | } |
248 | ||
eb01459f EA |
249 | /** |
250 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
251 | * from the backing pages of the object to the user's address space. On a | |
252 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
253 | */ | |
254 | static int | |
255 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
256 | struct drm_i915_gem_pread *args, | |
257 | struct drm_file *file_priv) | |
258 | { | |
23010e43 | 259 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
260 | ssize_t remain; |
261 | loff_t offset, page_base; | |
262 | char __user *user_data; | |
263 | int page_offset, page_length; | |
264 | int ret; | |
265 | ||
266 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
267 | remain = args->size; | |
268 | ||
269 | mutex_lock(&dev->struct_mutex); | |
270 | ||
4bdadb97 | 271 | ret = i915_gem_object_get_pages(obj, 0); |
eb01459f EA |
272 | if (ret != 0) |
273 | goto fail_unlock; | |
274 | ||
275 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
276 | args->size); | |
277 | if (ret != 0) | |
278 | goto fail_put_pages; | |
279 | ||
23010e43 | 280 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
281 | offset = args->offset; |
282 | ||
283 | while (remain > 0) { | |
284 | /* Operation in this page | |
285 | * | |
286 | * page_base = page offset within aperture | |
287 | * page_offset = offset within page | |
288 | * page_length = bytes to copy for this page | |
289 | */ | |
290 | page_base = (offset & ~(PAGE_SIZE-1)); | |
291 | page_offset = offset & (PAGE_SIZE-1); | |
292 | page_length = remain; | |
293 | if ((page_offset + remain) > PAGE_SIZE) | |
294 | page_length = PAGE_SIZE - page_offset; | |
295 | ||
296 | ret = fast_shmem_read(obj_priv->pages, | |
297 | page_base, page_offset, | |
298 | user_data, page_length); | |
299 | if (ret) | |
300 | goto fail_put_pages; | |
301 | ||
302 | remain -= page_length; | |
303 | user_data += page_length; | |
304 | offset += page_length; | |
305 | } | |
306 | ||
307 | fail_put_pages: | |
308 | i915_gem_object_put_pages(obj); | |
309 | fail_unlock: | |
310 | mutex_unlock(&dev->struct_mutex); | |
311 | ||
312 | return ret; | |
313 | } | |
314 | ||
07f73f69 CW |
315 | static int |
316 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
317 | { | |
318 | int ret; | |
319 | ||
4bdadb97 | 320 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
321 | |
322 | /* If we've insufficient memory to map in the pages, attempt | |
323 | * to make some space by throwing out some old buffers. | |
324 | */ | |
325 | if (ret == -ENOMEM) { | |
326 | struct drm_device *dev = obj->dev; | |
07f73f69 | 327 | |
0108a3ed DV |
328 | ret = i915_gem_evict_something(dev, obj->size, |
329 | i915_gem_get_gtt_alignment(obj)); | |
07f73f69 CW |
330 | if (ret) |
331 | return ret; | |
332 | ||
4bdadb97 | 333 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
334 | } |
335 | ||
336 | return ret; | |
337 | } | |
338 | ||
eb01459f EA |
339 | /** |
340 | * This is the fallback shmem pread path, which allocates temporary storage | |
341 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
342 | * can copy out of the object's backing pages while holding the struct mutex | |
343 | * and not take page faults. | |
344 | */ | |
345 | static int | |
346 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
347 | struct drm_i915_gem_pread *args, | |
348 | struct drm_file *file_priv) | |
349 | { | |
23010e43 | 350 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
351 | struct mm_struct *mm = current->mm; |
352 | struct page **user_pages; | |
353 | ssize_t remain; | |
354 | loff_t offset, pinned_pages, i; | |
355 | loff_t first_data_page, last_data_page, num_pages; | |
356 | int shmem_page_index, shmem_page_offset; | |
357 | int data_page_index, data_page_offset; | |
358 | int page_length; | |
359 | int ret; | |
360 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 361 | int do_bit17_swizzling; |
eb01459f EA |
362 | |
363 | remain = args->size; | |
364 | ||
365 | /* Pin the user pages containing the data. We can't fault while | |
366 | * holding the struct mutex, yet we want to hold it while | |
367 | * dereferencing the user data. | |
368 | */ | |
369 | first_data_page = data_ptr / PAGE_SIZE; | |
370 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
371 | num_pages = last_data_page - first_data_page + 1; | |
372 | ||
8e7d2b2c | 373 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
374 | if (user_pages == NULL) |
375 | return -ENOMEM; | |
376 | ||
377 | down_read(&mm->mmap_sem); | |
378 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 379 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
380 | up_read(&mm->mmap_sem); |
381 | if (pinned_pages < num_pages) { | |
382 | ret = -EFAULT; | |
383 | goto fail_put_user_pages; | |
384 | } | |
385 | ||
280b713b EA |
386 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
387 | ||
eb01459f EA |
388 | mutex_lock(&dev->struct_mutex); |
389 | ||
07f73f69 CW |
390 | ret = i915_gem_object_get_pages_or_evict(obj); |
391 | if (ret) | |
eb01459f EA |
392 | goto fail_unlock; |
393 | ||
394 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
395 | args->size); | |
396 | if (ret != 0) | |
397 | goto fail_put_pages; | |
398 | ||
23010e43 | 399 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
400 | offset = args->offset; |
401 | ||
402 | while (remain > 0) { | |
403 | /* Operation in this page | |
404 | * | |
405 | * shmem_page_index = page number within shmem file | |
406 | * shmem_page_offset = offset within page in shmem file | |
407 | * data_page_index = page number in get_user_pages return | |
408 | * data_page_offset = offset with data_page_index page. | |
409 | * page_length = bytes to copy for this page | |
410 | */ | |
411 | shmem_page_index = offset / PAGE_SIZE; | |
412 | shmem_page_offset = offset & ~PAGE_MASK; | |
413 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
414 | data_page_offset = data_ptr & ~PAGE_MASK; | |
415 | ||
416 | page_length = remain; | |
417 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
418 | page_length = PAGE_SIZE - shmem_page_offset; | |
419 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
420 | page_length = PAGE_SIZE - data_page_offset; | |
421 | ||
280b713b | 422 | if (do_bit17_swizzling) { |
99a03df5 | 423 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 424 | shmem_page_offset, |
99a03df5 CW |
425 | user_pages[data_page_index], |
426 | data_page_offset, | |
427 | page_length, | |
428 | 1); | |
429 | } else { | |
430 | slow_shmem_copy(user_pages[data_page_index], | |
431 | data_page_offset, | |
432 | obj_priv->pages[shmem_page_index], | |
433 | shmem_page_offset, | |
434 | page_length); | |
280b713b | 435 | } |
eb01459f EA |
436 | |
437 | remain -= page_length; | |
438 | data_ptr += page_length; | |
439 | offset += page_length; | |
440 | } | |
441 | ||
442 | fail_put_pages: | |
443 | i915_gem_object_put_pages(obj); | |
444 | fail_unlock: | |
445 | mutex_unlock(&dev->struct_mutex); | |
446 | fail_put_user_pages: | |
447 | for (i = 0; i < pinned_pages; i++) { | |
448 | SetPageDirty(user_pages[i]); | |
449 | page_cache_release(user_pages[i]); | |
450 | } | |
8e7d2b2c | 451 | drm_free_large(user_pages); |
eb01459f EA |
452 | |
453 | return ret; | |
454 | } | |
455 | ||
673a394b EA |
456 | /** |
457 | * Reads data from the object referenced by handle. | |
458 | * | |
459 | * On error, the contents of *data are undefined. | |
460 | */ | |
461 | int | |
462 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
463 | struct drm_file *file_priv) | |
464 | { | |
465 | struct drm_i915_gem_pread *args = data; | |
466 | struct drm_gem_object *obj; | |
467 | struct drm_i915_gem_object *obj_priv; | |
673a394b EA |
468 | int ret; |
469 | ||
470 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
471 | if (obj == NULL) | |
bf79cb91 | 472 | return -ENOENT; |
23010e43 | 473 | obj_priv = to_intel_bo(obj); |
673a394b EA |
474 | |
475 | /* Bounds check source. | |
476 | * | |
477 | * XXX: This could use review for overflow issues... | |
478 | */ | |
479 | if (args->offset > obj->size || args->size > obj->size || | |
480 | args->offset + args->size > obj->size) { | |
bc9025bd | 481 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
482 | return -EINVAL; |
483 | } | |
484 | ||
280b713b | 485 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 486 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
487 | } else { |
488 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
489 | if (ret != 0) | |
490 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
491 | file_priv); | |
492 | } | |
673a394b | 493 | |
bc9025bd | 494 | drm_gem_object_unreference_unlocked(obj); |
673a394b | 495 | |
eb01459f | 496 | return ret; |
673a394b EA |
497 | } |
498 | ||
0839ccb8 KP |
499 | /* This is the fast write path which cannot handle |
500 | * page faults in the source data | |
9b7530cc | 501 | */ |
0839ccb8 KP |
502 | |
503 | static inline int | |
504 | fast_user_write(struct io_mapping *mapping, | |
505 | loff_t page_base, int page_offset, | |
506 | char __user *user_data, | |
507 | int length) | |
9b7530cc | 508 | { |
9b7530cc | 509 | char *vaddr_atomic; |
0839ccb8 | 510 | unsigned long unwritten; |
9b7530cc | 511 | |
fca3ec01 | 512 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
0839ccb8 KP |
513 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
514 | user_data, length); | |
fca3ec01 | 515 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
0839ccb8 KP |
516 | if (unwritten) |
517 | return -EFAULT; | |
518 | return 0; | |
519 | } | |
520 | ||
521 | /* Here's the write path which can sleep for | |
522 | * page faults | |
523 | */ | |
524 | ||
ab34c226 | 525 | static inline void |
3de09aa3 EA |
526 | slow_kernel_write(struct io_mapping *mapping, |
527 | loff_t gtt_base, int gtt_offset, | |
528 | struct page *user_page, int user_offset, | |
529 | int length) | |
0839ccb8 | 530 | { |
ab34c226 CW |
531 | char __iomem *dst_vaddr; |
532 | char *src_vaddr; | |
0839ccb8 | 533 | |
ab34c226 CW |
534 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
535 | src_vaddr = kmap(user_page); | |
536 | ||
537 | memcpy_toio(dst_vaddr + gtt_offset, | |
538 | src_vaddr + user_offset, | |
539 | length); | |
540 | ||
541 | kunmap(user_page); | |
542 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
543 | } |
544 | ||
40123c1f EA |
545 | static inline int |
546 | fast_shmem_write(struct page **pages, | |
547 | loff_t page_base, int page_offset, | |
548 | char __user *data, | |
549 | int length) | |
550 | { | |
551 | char __iomem *vaddr; | |
d0088775 | 552 | unsigned long unwritten; |
40123c1f EA |
553 | |
554 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
555 | if (vaddr == NULL) | |
556 | return -ENOMEM; | |
d0088775 | 557 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
558 | kunmap_atomic(vaddr, KM_USER0); |
559 | ||
d0088775 DA |
560 | if (unwritten) |
561 | return -EFAULT; | |
40123c1f EA |
562 | return 0; |
563 | } | |
564 | ||
3de09aa3 EA |
565 | /** |
566 | * This is the fast pwrite path, where we copy the data directly from the | |
567 | * user into the GTT, uncached. | |
568 | */ | |
673a394b | 569 | static int |
3de09aa3 EA |
570 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
571 | struct drm_i915_gem_pwrite *args, | |
572 | struct drm_file *file_priv) | |
673a394b | 573 | { |
23010e43 | 574 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 575 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 576 | ssize_t remain; |
0839ccb8 | 577 | loff_t offset, page_base; |
673a394b | 578 | char __user *user_data; |
0839ccb8 KP |
579 | int page_offset, page_length; |
580 | int ret; | |
673a394b EA |
581 | |
582 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
583 | remain = args->size; | |
584 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
585 | return -EFAULT; | |
586 | ||
587 | ||
588 | mutex_lock(&dev->struct_mutex); | |
589 | ret = i915_gem_object_pin(obj, 0); | |
590 | if (ret) { | |
591 | mutex_unlock(&dev->struct_mutex); | |
592 | return ret; | |
593 | } | |
2ef7eeaa | 594 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
595 | if (ret) |
596 | goto fail; | |
597 | ||
23010e43 | 598 | obj_priv = to_intel_bo(obj); |
673a394b | 599 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
600 | |
601 | while (remain > 0) { | |
602 | /* Operation in this page | |
603 | * | |
0839ccb8 KP |
604 | * page_base = page offset within aperture |
605 | * page_offset = offset within page | |
606 | * page_length = bytes to copy for this page | |
673a394b | 607 | */ |
0839ccb8 KP |
608 | page_base = (offset & ~(PAGE_SIZE-1)); |
609 | page_offset = offset & (PAGE_SIZE-1); | |
610 | page_length = remain; | |
611 | if ((page_offset + remain) > PAGE_SIZE) | |
612 | page_length = PAGE_SIZE - page_offset; | |
613 | ||
614 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
615 | page_offset, user_data, page_length); | |
616 | ||
617 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
618 | * source page isn't available. Return the error and we'll |
619 | * retry in the slow path. | |
0839ccb8 | 620 | */ |
3de09aa3 EA |
621 | if (ret) |
622 | goto fail; | |
673a394b | 623 | |
0839ccb8 KP |
624 | remain -= page_length; |
625 | user_data += page_length; | |
626 | offset += page_length; | |
673a394b | 627 | } |
673a394b EA |
628 | |
629 | fail: | |
630 | i915_gem_object_unpin(obj); | |
631 | mutex_unlock(&dev->struct_mutex); | |
632 | ||
633 | return ret; | |
634 | } | |
635 | ||
3de09aa3 EA |
636 | /** |
637 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
638 | * the memory and maps it using kmap_atomic for copying. | |
639 | * | |
640 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
641 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
642 | */ | |
3043c60c | 643 | static int |
3de09aa3 EA |
644 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
645 | struct drm_i915_gem_pwrite *args, | |
646 | struct drm_file *file_priv) | |
673a394b | 647 | { |
23010e43 | 648 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
649 | drm_i915_private_t *dev_priv = dev->dev_private; |
650 | ssize_t remain; | |
651 | loff_t gtt_page_base, offset; | |
652 | loff_t first_data_page, last_data_page, num_pages; | |
653 | loff_t pinned_pages, i; | |
654 | struct page **user_pages; | |
655 | struct mm_struct *mm = current->mm; | |
656 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 657 | int ret; |
3de09aa3 EA |
658 | uint64_t data_ptr = args->data_ptr; |
659 | ||
660 | remain = args->size; | |
661 | ||
662 | /* Pin the user pages containing the data. We can't fault while | |
663 | * holding the struct mutex, and all of the pwrite implementations | |
664 | * want to hold it while dereferencing the user data. | |
665 | */ | |
666 | first_data_page = data_ptr / PAGE_SIZE; | |
667 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
668 | num_pages = last_data_page - first_data_page + 1; | |
669 | ||
8e7d2b2c | 670 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
671 | if (user_pages == NULL) |
672 | return -ENOMEM; | |
673 | ||
674 | down_read(&mm->mmap_sem); | |
675 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
676 | num_pages, 0, 0, user_pages, NULL); | |
677 | up_read(&mm->mmap_sem); | |
678 | if (pinned_pages < num_pages) { | |
679 | ret = -EFAULT; | |
680 | goto out_unpin_pages; | |
681 | } | |
673a394b EA |
682 | |
683 | mutex_lock(&dev->struct_mutex); | |
3de09aa3 EA |
684 | ret = i915_gem_object_pin(obj, 0); |
685 | if (ret) | |
686 | goto out_unlock; | |
687 | ||
688 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
689 | if (ret) | |
690 | goto out_unpin_object; | |
691 | ||
23010e43 | 692 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
693 | offset = obj_priv->gtt_offset + args->offset; |
694 | ||
695 | while (remain > 0) { | |
696 | /* Operation in this page | |
697 | * | |
698 | * gtt_page_base = page offset within aperture | |
699 | * gtt_page_offset = offset within page in aperture | |
700 | * data_page_index = page number in get_user_pages return | |
701 | * data_page_offset = offset with data_page_index page. | |
702 | * page_length = bytes to copy for this page | |
703 | */ | |
704 | gtt_page_base = offset & PAGE_MASK; | |
705 | gtt_page_offset = offset & ~PAGE_MASK; | |
706 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
707 | data_page_offset = data_ptr & ~PAGE_MASK; | |
708 | ||
709 | page_length = remain; | |
710 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
711 | page_length = PAGE_SIZE - gtt_page_offset; | |
712 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
713 | page_length = PAGE_SIZE - data_page_offset; | |
714 | ||
ab34c226 CW |
715 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
716 | gtt_page_base, gtt_page_offset, | |
717 | user_pages[data_page_index], | |
718 | data_page_offset, | |
719 | page_length); | |
3de09aa3 EA |
720 | |
721 | remain -= page_length; | |
722 | offset += page_length; | |
723 | data_ptr += page_length; | |
724 | } | |
725 | ||
726 | out_unpin_object: | |
727 | i915_gem_object_unpin(obj); | |
728 | out_unlock: | |
729 | mutex_unlock(&dev->struct_mutex); | |
730 | out_unpin_pages: | |
731 | for (i = 0; i < pinned_pages; i++) | |
732 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 733 | drm_free_large(user_pages); |
3de09aa3 EA |
734 | |
735 | return ret; | |
736 | } | |
737 | ||
40123c1f EA |
738 | /** |
739 | * This is the fast shmem pwrite path, which attempts to directly | |
740 | * copy_from_user into the kmapped pages backing the object. | |
741 | */ | |
3043c60c | 742 | static int |
40123c1f EA |
743 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
744 | struct drm_i915_gem_pwrite *args, | |
745 | struct drm_file *file_priv) | |
673a394b | 746 | { |
23010e43 | 747 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
748 | ssize_t remain; |
749 | loff_t offset, page_base; | |
750 | char __user *user_data; | |
751 | int page_offset, page_length; | |
673a394b | 752 | int ret; |
40123c1f EA |
753 | |
754 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
755 | remain = args->size; | |
673a394b EA |
756 | |
757 | mutex_lock(&dev->struct_mutex); | |
758 | ||
4bdadb97 | 759 | ret = i915_gem_object_get_pages(obj, 0); |
40123c1f EA |
760 | if (ret != 0) |
761 | goto fail_unlock; | |
673a394b | 762 | |
e47c68e9 | 763 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
764 | if (ret != 0) |
765 | goto fail_put_pages; | |
766 | ||
23010e43 | 767 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
768 | offset = args->offset; |
769 | obj_priv->dirty = 1; | |
770 | ||
771 | while (remain > 0) { | |
772 | /* Operation in this page | |
773 | * | |
774 | * page_base = page offset within aperture | |
775 | * page_offset = offset within page | |
776 | * page_length = bytes to copy for this page | |
777 | */ | |
778 | page_base = (offset & ~(PAGE_SIZE-1)); | |
779 | page_offset = offset & (PAGE_SIZE-1); | |
780 | page_length = remain; | |
781 | if ((page_offset + remain) > PAGE_SIZE) | |
782 | page_length = PAGE_SIZE - page_offset; | |
783 | ||
784 | ret = fast_shmem_write(obj_priv->pages, | |
785 | page_base, page_offset, | |
786 | user_data, page_length); | |
787 | if (ret) | |
788 | goto fail_put_pages; | |
789 | ||
790 | remain -= page_length; | |
791 | user_data += page_length; | |
792 | offset += page_length; | |
793 | } | |
794 | ||
795 | fail_put_pages: | |
796 | i915_gem_object_put_pages(obj); | |
797 | fail_unlock: | |
798 | mutex_unlock(&dev->struct_mutex); | |
799 | ||
800 | return ret; | |
801 | } | |
802 | ||
803 | /** | |
804 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
805 | * the memory and maps it using kmap_atomic for copying. | |
806 | * | |
807 | * This avoids taking mmap_sem for faulting on the user's address while the | |
808 | * struct_mutex is held. | |
809 | */ | |
810 | static int | |
811 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
812 | struct drm_i915_gem_pwrite *args, | |
813 | struct drm_file *file_priv) | |
814 | { | |
23010e43 | 815 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
816 | struct mm_struct *mm = current->mm; |
817 | struct page **user_pages; | |
818 | ssize_t remain; | |
819 | loff_t offset, pinned_pages, i; | |
820 | loff_t first_data_page, last_data_page, num_pages; | |
821 | int shmem_page_index, shmem_page_offset; | |
822 | int data_page_index, data_page_offset; | |
823 | int page_length; | |
824 | int ret; | |
825 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 826 | int do_bit17_swizzling; |
40123c1f EA |
827 | |
828 | remain = args->size; | |
829 | ||
830 | /* Pin the user pages containing the data. We can't fault while | |
831 | * holding the struct mutex, and all of the pwrite implementations | |
832 | * want to hold it while dereferencing the user data. | |
833 | */ | |
834 | first_data_page = data_ptr / PAGE_SIZE; | |
835 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
836 | num_pages = last_data_page - first_data_page + 1; | |
837 | ||
8e7d2b2c | 838 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
839 | if (user_pages == NULL) |
840 | return -ENOMEM; | |
841 | ||
842 | down_read(&mm->mmap_sem); | |
843 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
844 | num_pages, 0, 0, user_pages, NULL); | |
845 | up_read(&mm->mmap_sem); | |
846 | if (pinned_pages < num_pages) { | |
847 | ret = -EFAULT; | |
848 | goto fail_put_user_pages; | |
673a394b EA |
849 | } |
850 | ||
280b713b EA |
851 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
852 | ||
40123c1f EA |
853 | mutex_lock(&dev->struct_mutex); |
854 | ||
07f73f69 CW |
855 | ret = i915_gem_object_get_pages_or_evict(obj); |
856 | if (ret) | |
40123c1f EA |
857 | goto fail_unlock; |
858 | ||
859 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
860 | if (ret != 0) | |
861 | goto fail_put_pages; | |
862 | ||
23010e43 | 863 | obj_priv = to_intel_bo(obj); |
673a394b | 864 | offset = args->offset; |
40123c1f | 865 | obj_priv->dirty = 1; |
673a394b | 866 | |
40123c1f EA |
867 | while (remain > 0) { |
868 | /* Operation in this page | |
869 | * | |
870 | * shmem_page_index = page number within shmem file | |
871 | * shmem_page_offset = offset within page in shmem file | |
872 | * data_page_index = page number in get_user_pages return | |
873 | * data_page_offset = offset with data_page_index page. | |
874 | * page_length = bytes to copy for this page | |
875 | */ | |
876 | shmem_page_index = offset / PAGE_SIZE; | |
877 | shmem_page_offset = offset & ~PAGE_MASK; | |
878 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
879 | data_page_offset = data_ptr & ~PAGE_MASK; | |
880 | ||
881 | page_length = remain; | |
882 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
883 | page_length = PAGE_SIZE - shmem_page_offset; | |
884 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
885 | page_length = PAGE_SIZE - data_page_offset; | |
886 | ||
280b713b | 887 | if (do_bit17_swizzling) { |
99a03df5 | 888 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
889 | shmem_page_offset, |
890 | user_pages[data_page_index], | |
891 | data_page_offset, | |
99a03df5 CW |
892 | page_length, |
893 | 0); | |
894 | } else { | |
895 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
896 | shmem_page_offset, | |
897 | user_pages[data_page_index], | |
898 | data_page_offset, | |
899 | page_length); | |
280b713b | 900 | } |
40123c1f EA |
901 | |
902 | remain -= page_length; | |
903 | data_ptr += page_length; | |
904 | offset += page_length; | |
673a394b EA |
905 | } |
906 | ||
40123c1f EA |
907 | fail_put_pages: |
908 | i915_gem_object_put_pages(obj); | |
909 | fail_unlock: | |
673a394b | 910 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
911 | fail_put_user_pages: |
912 | for (i = 0; i < pinned_pages; i++) | |
913 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 914 | drm_free_large(user_pages); |
673a394b | 915 | |
40123c1f | 916 | return ret; |
673a394b EA |
917 | } |
918 | ||
919 | /** | |
920 | * Writes data to the object referenced by handle. | |
921 | * | |
922 | * On error, the contents of the buffer that were to be modified are undefined. | |
923 | */ | |
924 | int | |
925 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
926 | struct drm_file *file_priv) | |
927 | { | |
928 | struct drm_i915_gem_pwrite *args = data; | |
929 | struct drm_gem_object *obj; | |
930 | struct drm_i915_gem_object *obj_priv; | |
931 | int ret = 0; | |
932 | ||
933 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
934 | if (obj == NULL) | |
bf79cb91 | 935 | return -ENOENT; |
23010e43 | 936 | obj_priv = to_intel_bo(obj); |
673a394b EA |
937 | |
938 | /* Bounds check destination. | |
939 | * | |
940 | * XXX: This could use review for overflow issues... | |
941 | */ | |
942 | if (args->offset > obj->size || args->size > obj->size || | |
943 | args->offset + args->size > obj->size) { | |
bc9025bd | 944 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
945 | return -EINVAL; |
946 | } | |
947 | ||
948 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
949 | * it would end up going through the fenced access, and we'll get | |
950 | * different detiling behavior between reading and writing. | |
951 | * pread/pwrite currently are reading and writing from the CPU | |
952 | * perspective, requiring manual detiling by the client. | |
953 | */ | |
71acb5eb DA |
954 | if (obj_priv->phys_obj) |
955 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
956 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
9b8c4a0b CW |
957 | dev->gtt_total != 0 && |
958 | obj->write_domain != I915_GEM_DOMAIN_CPU) { | |
3de09aa3 EA |
959 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
960 | if (ret == -EFAULT) { | |
961 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
962 | file_priv); | |
963 | } | |
280b713b EA |
964 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
965 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
966 | } else { |
967 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
968 | if (ret == -EFAULT) { | |
969 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
970 | file_priv); | |
971 | } | |
972 | } | |
673a394b EA |
973 | |
974 | #if WATCH_PWRITE | |
975 | if (ret) | |
976 | DRM_INFO("pwrite failed %d\n", ret); | |
977 | #endif | |
978 | ||
bc9025bd | 979 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
980 | |
981 | return ret; | |
982 | } | |
983 | ||
984 | /** | |
2ef7eeaa EA |
985 | * Called when user space prepares to use an object with the CPU, either |
986 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
987 | */ |
988 | int | |
989 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
990 | struct drm_file *file_priv) | |
991 | { | |
a09ba7fa | 992 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
993 | struct drm_i915_gem_set_domain *args = data; |
994 | struct drm_gem_object *obj; | |
652c393a | 995 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
996 | uint32_t read_domains = args->read_domains; |
997 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
998 | int ret; |
999 | ||
1000 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1001 | return -ENODEV; | |
1002 | ||
2ef7eeaa | 1003 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1004 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1005 | return -EINVAL; |
1006 | ||
21d509e3 | 1007 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1008 | return -EINVAL; |
1009 | ||
1010 | /* Having something in the write domain implies it's in the read | |
1011 | * domain, and only that read domain. Enforce that in the request. | |
1012 | */ | |
1013 | if (write_domain != 0 && read_domains != write_domain) | |
1014 | return -EINVAL; | |
1015 | ||
673a394b EA |
1016 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1017 | if (obj == NULL) | |
bf79cb91 | 1018 | return -ENOENT; |
23010e43 | 1019 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1020 | |
1021 | mutex_lock(&dev->struct_mutex); | |
652c393a JB |
1022 | |
1023 | intel_mark_busy(dev, obj); | |
1024 | ||
673a394b | 1025 | #if WATCH_BUF |
cfd43c02 | 1026 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
2ef7eeaa | 1027 | obj, obj->size, read_domains, write_domain); |
673a394b | 1028 | #endif |
2ef7eeaa EA |
1029 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1030 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1031 | |
a09ba7fa EA |
1032 | /* Update the LRU on the fence for the CPU access that's |
1033 | * about to occur. | |
1034 | */ | |
1035 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1036 | struct drm_i915_fence_reg *reg = |
1037 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1038 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1039 | &dev_priv->mm.fence_list); |
1040 | } | |
1041 | ||
02354392 EA |
1042 | /* Silently promote "you're not bound, there was nothing to do" |
1043 | * to success, since the client was just asking us to | |
1044 | * make sure everything was done. | |
1045 | */ | |
1046 | if (ret == -EINVAL) | |
1047 | ret = 0; | |
2ef7eeaa | 1048 | } else { |
e47c68e9 | 1049 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1050 | } |
1051 | ||
7d1c4804 CW |
1052 | |
1053 | /* Maintain LRU order of "inactive" objects */ | |
1054 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
1055 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1056 | ||
673a394b EA |
1057 | drm_gem_object_unreference(obj); |
1058 | mutex_unlock(&dev->struct_mutex); | |
1059 | return ret; | |
1060 | } | |
1061 | ||
1062 | /** | |
1063 | * Called when user space has done writes to this buffer | |
1064 | */ | |
1065 | int | |
1066 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1067 | struct drm_file *file_priv) | |
1068 | { | |
1069 | struct drm_i915_gem_sw_finish *args = data; | |
1070 | struct drm_gem_object *obj; | |
1071 | struct drm_i915_gem_object *obj_priv; | |
1072 | int ret = 0; | |
1073 | ||
1074 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1075 | return -ENODEV; | |
1076 | ||
1077 | mutex_lock(&dev->struct_mutex); | |
1078 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1079 | if (obj == NULL) { | |
1080 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 1081 | return -ENOENT; |
673a394b EA |
1082 | } |
1083 | ||
1084 | #if WATCH_BUF | |
cfd43c02 | 1085 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
673a394b EA |
1086 | __func__, args->handle, obj, obj->size); |
1087 | #endif | |
23010e43 | 1088 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1089 | |
1090 | /* Pinned buffers may be scanout, so flush the cache */ | |
e47c68e9 EA |
1091 | if (obj_priv->pin_count) |
1092 | i915_gem_object_flush_cpu_write_domain(obj); | |
1093 | ||
673a394b EA |
1094 | drm_gem_object_unreference(obj); |
1095 | mutex_unlock(&dev->struct_mutex); | |
1096 | return ret; | |
1097 | } | |
1098 | ||
1099 | /** | |
1100 | * Maps the contents of an object, returning the address it is mapped | |
1101 | * into. | |
1102 | * | |
1103 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1104 | * imply a ref on the object itself. | |
1105 | */ | |
1106 | int | |
1107 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1108 | struct drm_file *file_priv) | |
1109 | { | |
1110 | struct drm_i915_gem_mmap *args = data; | |
1111 | struct drm_gem_object *obj; | |
1112 | loff_t offset; | |
1113 | unsigned long addr; | |
1114 | ||
1115 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1116 | return -ENODEV; | |
1117 | ||
1118 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1119 | if (obj == NULL) | |
bf79cb91 | 1120 | return -ENOENT; |
673a394b EA |
1121 | |
1122 | offset = args->offset; | |
1123 | ||
1124 | down_write(¤t->mm->mmap_sem); | |
1125 | addr = do_mmap(obj->filp, 0, args->size, | |
1126 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1127 | args->offset); | |
1128 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1129 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1130 | if (IS_ERR((void *)addr)) |
1131 | return addr; | |
1132 | ||
1133 | args->addr_ptr = (uint64_t) addr; | |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
de151cf6 JB |
1138 | /** |
1139 | * i915_gem_fault - fault a page into the GTT | |
1140 | * vma: VMA in question | |
1141 | * vmf: fault info | |
1142 | * | |
1143 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1144 | * from userspace. The fault handler takes care of binding the object to | |
1145 | * the GTT (if needed), allocating and programming a fence register (again, | |
1146 | * only if needed based on whether the old reg is still valid or the object | |
1147 | * is tiled) and inserting a new PTE into the faulting process. | |
1148 | * | |
1149 | * Note that the faulting process may involve evicting existing objects | |
1150 | * from the GTT and/or fence registers to make room. So performance may | |
1151 | * suffer if the GTT working set is large or there are few fence registers | |
1152 | * left. | |
1153 | */ | |
1154 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1155 | { | |
1156 | struct drm_gem_object *obj = vma->vm_private_data; | |
1157 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1158 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1159 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1160 | pgoff_t page_offset; |
1161 | unsigned long pfn; | |
1162 | int ret = 0; | |
0f973f27 | 1163 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1164 | |
1165 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1166 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1167 | PAGE_SHIFT; | |
1168 | ||
1169 | /* Now bind it into the GTT if needed */ | |
1170 | mutex_lock(&dev->struct_mutex); | |
1171 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1172 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1173 | if (ret) |
1174 | goto unlock; | |
07f4f3e8 | 1175 | |
07f4f3e8 | 1176 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1177 | if (ret) |
1178 | goto unlock; | |
de151cf6 JB |
1179 | } |
1180 | ||
1181 | /* Need a new fence register? */ | |
a09ba7fa | 1182 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
8c4b8c3f | 1183 | ret = i915_gem_object_get_fence_reg(obj); |
c715089f CW |
1184 | if (ret) |
1185 | goto unlock; | |
d9ddcb96 | 1186 | } |
de151cf6 | 1187 | |
7d1c4804 CW |
1188 | if (i915_gem_object_is_inactive(obj_priv)) |
1189 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1190 | ||
de151cf6 JB |
1191 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1192 | page_offset; | |
1193 | ||
1194 | /* Finally, remap it using the new GTT offset */ | |
1195 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1196 | unlock: |
de151cf6 JB |
1197 | mutex_unlock(&dev->struct_mutex); |
1198 | ||
1199 | switch (ret) { | |
c715089f CW |
1200 | case 0: |
1201 | case -ERESTARTSYS: | |
1202 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1203 | case -ENOMEM: |
1204 | case -EAGAIN: | |
1205 | return VM_FAULT_OOM; | |
de151cf6 | 1206 | default: |
c715089f | 1207 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1208 | } |
1209 | } | |
1210 | ||
1211 | /** | |
1212 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1213 | * @obj: obj in question | |
1214 | * | |
1215 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1216 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1217 | * up the object based on the offset and sets up the various memory mapping | |
1218 | * structures. | |
1219 | * | |
1220 | * This routine allocates and attaches a fake offset for @obj. | |
1221 | */ | |
1222 | static int | |
1223 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1224 | { | |
1225 | struct drm_device *dev = obj->dev; | |
1226 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1227 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1228 | struct drm_map_list *list; |
f77d390c | 1229 | struct drm_local_map *map; |
de151cf6 JB |
1230 | int ret = 0; |
1231 | ||
1232 | /* Set the object up for mmap'ing */ | |
1233 | list = &obj->map_list; | |
9a298b2a | 1234 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1235 | if (!list->map) |
1236 | return -ENOMEM; | |
1237 | ||
1238 | map = list->map; | |
1239 | map->type = _DRM_GEM; | |
1240 | map->size = obj->size; | |
1241 | map->handle = obj; | |
1242 | ||
1243 | /* Get a DRM GEM mmap offset allocated... */ | |
1244 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1245 | obj->size / PAGE_SIZE, 0, 0); | |
1246 | if (!list->file_offset_node) { | |
1247 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
1248 | ret = -ENOMEM; | |
1249 | goto out_free_list; | |
1250 | } | |
1251 | ||
1252 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1253 | obj->size / PAGE_SIZE, 0); | |
1254 | if (!list->file_offset_node) { | |
1255 | ret = -ENOMEM; | |
1256 | goto out_free_list; | |
1257 | } | |
1258 | ||
1259 | list->hash.key = list->file_offset_node->start; | |
1260 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { | |
1261 | DRM_ERROR("failed to add to map hash\n"); | |
5618ca6a | 1262 | ret = -ENOMEM; |
de151cf6 JB |
1263 | goto out_free_mm; |
1264 | } | |
1265 | ||
1266 | /* By now we should be all set, any drm_mmap request on the offset | |
1267 | * below will get to our mmap & fault handler */ | |
1268 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1269 | ||
1270 | return 0; | |
1271 | ||
1272 | out_free_mm: | |
1273 | drm_mm_put_block(list->file_offset_node); | |
1274 | out_free_list: | |
9a298b2a | 1275 | kfree(list->map); |
de151cf6 JB |
1276 | |
1277 | return ret; | |
1278 | } | |
1279 | ||
901782b2 CW |
1280 | /** |
1281 | * i915_gem_release_mmap - remove physical page mappings | |
1282 | * @obj: obj in question | |
1283 | * | |
af901ca1 | 1284 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1285 | * relinquish ownership of the pages back to the system. |
1286 | * | |
1287 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1288 | * object through the GTT and then lose the fence register due to | |
1289 | * resource pressure. Similarly if the object has been moved out of the | |
1290 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1291 | * mapping will then trigger a page fault on the next user access, allowing | |
1292 | * fixup by i915_gem_fault(). | |
1293 | */ | |
d05ca301 | 1294 | void |
901782b2 CW |
1295 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1296 | { | |
1297 | struct drm_device *dev = obj->dev; | |
23010e43 | 1298 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1299 | |
1300 | if (dev->dev_mapping) | |
1301 | unmap_mapping_range(dev->dev_mapping, | |
1302 | obj_priv->mmap_offset, obj->size, 1); | |
1303 | } | |
1304 | ||
ab00b3e5 JB |
1305 | static void |
1306 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1307 | { | |
1308 | struct drm_device *dev = obj->dev; | |
23010e43 | 1309 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1310 | struct drm_gem_mm *mm = dev->mm_private; |
1311 | struct drm_map_list *list; | |
1312 | ||
1313 | list = &obj->map_list; | |
1314 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1315 | ||
1316 | if (list->file_offset_node) { | |
1317 | drm_mm_put_block(list->file_offset_node); | |
1318 | list->file_offset_node = NULL; | |
1319 | } | |
1320 | ||
1321 | if (list->map) { | |
9a298b2a | 1322 | kfree(list->map); |
ab00b3e5 JB |
1323 | list->map = NULL; |
1324 | } | |
1325 | ||
1326 | obj_priv->mmap_offset = 0; | |
1327 | } | |
1328 | ||
de151cf6 JB |
1329 | /** |
1330 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1331 | * @obj: object to check | |
1332 | * | |
1333 | * Return the required GTT alignment for an object, taking into account | |
1334 | * potential fence register mapping if needed. | |
1335 | */ | |
1336 | static uint32_t | |
1337 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1338 | { | |
1339 | struct drm_device *dev = obj->dev; | |
23010e43 | 1340 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1341 | int start, i; |
1342 | ||
1343 | /* | |
1344 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1345 | * if a fence register is needed for the object. | |
1346 | */ | |
1347 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) | |
1348 | return 4096; | |
1349 | ||
1350 | /* | |
1351 | * Previous chips need to be aligned to the size of the smallest | |
1352 | * fence register that can contain the object. | |
1353 | */ | |
1354 | if (IS_I9XX(dev)) | |
1355 | start = 1024*1024; | |
1356 | else | |
1357 | start = 512*1024; | |
1358 | ||
1359 | for (i = start; i < obj->size; i <<= 1) | |
1360 | ; | |
1361 | ||
1362 | return i; | |
1363 | } | |
1364 | ||
1365 | /** | |
1366 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1367 | * @dev: DRM device | |
1368 | * @data: GTT mapping ioctl data | |
1369 | * @file_priv: GEM object info | |
1370 | * | |
1371 | * Simply returns the fake offset to userspace so it can mmap it. | |
1372 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1373 | * up so we can get faults in the handler above. | |
1374 | * | |
1375 | * The fault handler will take care of binding the object into the GTT | |
1376 | * (since it may have been evicted to make room for something), allocating | |
1377 | * a fence register, and mapping the appropriate aperture address into | |
1378 | * userspace. | |
1379 | */ | |
1380 | int | |
1381 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1382 | struct drm_file *file_priv) | |
1383 | { | |
1384 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1385 | struct drm_gem_object *obj; |
1386 | struct drm_i915_gem_object *obj_priv; | |
1387 | int ret; | |
1388 | ||
1389 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1390 | return -ENODEV; | |
1391 | ||
1392 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1393 | if (obj == NULL) | |
bf79cb91 | 1394 | return -ENOENT; |
de151cf6 JB |
1395 | |
1396 | mutex_lock(&dev->struct_mutex); | |
1397 | ||
23010e43 | 1398 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1399 | |
ab18282d CW |
1400 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1401 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1402 | drm_gem_object_unreference(obj); | |
1403 | mutex_unlock(&dev->struct_mutex); | |
1404 | return -EINVAL; | |
1405 | } | |
1406 | ||
1407 | ||
de151cf6 JB |
1408 | if (!obj_priv->mmap_offset) { |
1409 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1410 | if (ret) { |
1411 | drm_gem_object_unreference(obj); | |
1412 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1413 | return ret; |
13af1062 | 1414 | } |
de151cf6 JB |
1415 | } |
1416 | ||
1417 | args->offset = obj_priv->mmap_offset; | |
1418 | ||
de151cf6 JB |
1419 | /* |
1420 | * Pull it into the GTT so that we have a page list (makes the | |
1421 | * initial fault faster and any subsequent flushing possible). | |
1422 | */ | |
1423 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1424 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1425 | if (ret) { |
1426 | drm_gem_object_unreference(obj); | |
1427 | mutex_unlock(&dev->struct_mutex); | |
1428 | return ret; | |
1429 | } | |
de151cf6 JB |
1430 | } |
1431 | ||
1432 | drm_gem_object_unreference(obj); | |
1433 | mutex_unlock(&dev->struct_mutex); | |
1434 | ||
1435 | return 0; | |
1436 | } | |
1437 | ||
6911a9b8 | 1438 | void |
856fa198 | 1439 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1440 | { |
23010e43 | 1441 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1442 | int page_count = obj->size / PAGE_SIZE; |
1443 | int i; | |
1444 | ||
856fa198 | 1445 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1446 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1447 | |
856fa198 EA |
1448 | if (--obj_priv->pages_refcount != 0) |
1449 | return; | |
673a394b | 1450 | |
280b713b EA |
1451 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1452 | i915_gem_object_save_bit_17_swizzle(obj); | |
1453 | ||
3ef94daa | 1454 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1455 | obj_priv->dirty = 0; |
3ef94daa CW |
1456 | |
1457 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1458 | if (obj_priv->dirty) |
1459 | set_page_dirty(obj_priv->pages[i]); | |
1460 | ||
1461 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1462 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1463 | |
1464 | page_cache_release(obj_priv->pages[i]); | |
1465 | } | |
673a394b EA |
1466 | obj_priv->dirty = 0; |
1467 | ||
8e7d2b2c | 1468 | drm_free_large(obj_priv->pages); |
856fa198 | 1469 | obj_priv->pages = NULL; |
673a394b EA |
1470 | } |
1471 | ||
e35a41de DV |
1472 | static uint32_t |
1473 | i915_gem_next_request_seqno(struct drm_device *dev) | |
1474 | { | |
1475 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1476 | ||
1477 | return dev_priv->next_seqno; | |
1478 | } | |
1479 | ||
673a394b | 1480 | static void |
852835f3 ZN |
1481 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno, |
1482 | struct intel_ring_buffer *ring) | |
673a394b EA |
1483 | { |
1484 | struct drm_device *dev = obj->dev; | |
1485 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1486 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
852835f3 ZN |
1487 | BUG_ON(ring == NULL); |
1488 | obj_priv->ring = ring; | |
673a394b EA |
1489 | |
1490 | /* Add a reference if we're newly entering the active list. */ | |
1491 | if (!obj_priv->active) { | |
1492 | drm_gem_object_reference(obj); | |
1493 | obj_priv->active = 1; | |
1494 | } | |
e35a41de DV |
1495 | |
1496 | /* Take the seqno of the next request if none is given */ | |
1497 | if (seqno == 0) | |
1498 | seqno = i915_gem_next_request_seqno(dev); | |
1499 | ||
673a394b | 1500 | /* Move from whatever list we were on to the tail of execution. */ |
5e118f41 | 1501 | spin_lock(&dev_priv->mm.active_list_lock); |
852835f3 | 1502 | list_move_tail(&obj_priv->list, &ring->active_list); |
5e118f41 | 1503 | spin_unlock(&dev_priv->mm.active_list_lock); |
ce44b0ea | 1504 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1505 | } |
1506 | ||
ce44b0ea EA |
1507 | static void |
1508 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1509 | { | |
1510 | struct drm_device *dev = obj->dev; | |
1511 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1512 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1513 | |
1514 | BUG_ON(!obj_priv->active); | |
1515 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1516 | obj_priv->last_rendering_seqno = 0; | |
1517 | } | |
673a394b | 1518 | |
963b4836 CW |
1519 | /* Immediately discard the backing storage */ |
1520 | static void | |
1521 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1522 | { | |
23010e43 | 1523 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1524 | struct inode *inode; |
963b4836 | 1525 | |
ae9fed6b CW |
1526 | /* Our goal here is to return as much of the memory as |
1527 | * is possible back to the system as we are called from OOM. | |
1528 | * To do this we must instruct the shmfs to drop all of its | |
1529 | * backing pages, *now*. Here we mirror the actions taken | |
1530 | * when by shmem_delete_inode() to release the backing store. | |
1531 | */ | |
bb6baf76 | 1532 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1533 | truncate_inode_pages(inode->i_mapping, 0); |
1534 | if (inode->i_op->truncate_range) | |
1535 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1536 | |
1537 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1538 | } |
1539 | ||
1540 | static inline int | |
1541 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1542 | { | |
1543 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1544 | } | |
1545 | ||
673a394b EA |
1546 | static void |
1547 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1548 | { | |
1549 | struct drm_device *dev = obj->dev; | |
1550 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1551 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1552 | |
1553 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1554 | if (obj_priv->pin_count != 0) | |
1555 | list_del_init(&obj_priv->list); | |
1556 | else | |
1557 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1558 | ||
99fcb766 DV |
1559 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1560 | ||
ce44b0ea | 1561 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1562 | obj_priv->ring = NULL; |
673a394b EA |
1563 | if (obj_priv->active) { |
1564 | obj_priv->active = 0; | |
1565 | drm_gem_object_unreference(obj); | |
1566 | } | |
1567 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1568 | } | |
1569 | ||
63560396 DV |
1570 | static void |
1571 | i915_gem_process_flushing_list(struct drm_device *dev, | |
852835f3 ZN |
1572 | uint32_t flush_domains, uint32_t seqno, |
1573 | struct intel_ring_buffer *ring) | |
63560396 DV |
1574 | { |
1575 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1576 | struct drm_i915_gem_object *obj_priv, *next; | |
1577 | ||
1578 | list_for_each_entry_safe(obj_priv, next, | |
1579 | &dev_priv->mm.gpu_write_list, | |
1580 | gpu_write_list) { | |
a8089e84 | 1581 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 DV |
1582 | |
1583 | if ((obj->write_domain & flush_domains) == | |
852835f3 ZN |
1584 | obj->write_domain && |
1585 | obj_priv->ring->ring_flag == ring->ring_flag) { | |
63560396 DV |
1586 | uint32_t old_write_domain = obj->write_domain; |
1587 | ||
1588 | obj->write_domain = 0; | |
1589 | list_del_init(&obj_priv->gpu_write_list); | |
852835f3 | 1590 | i915_gem_object_move_to_active(obj, seqno, ring); |
63560396 DV |
1591 | |
1592 | /* update the fence lru list */ | |
007cc8ac DV |
1593 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1594 | struct drm_i915_fence_reg *reg = | |
1595 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1596 | list_move_tail(®->lru_list, | |
63560396 | 1597 | &dev_priv->mm.fence_list); |
007cc8ac | 1598 | } |
63560396 DV |
1599 | |
1600 | trace_i915_gem_object_change_domain(obj, | |
1601 | obj->read_domains, | |
1602 | old_write_domain); | |
1603 | } | |
1604 | } | |
1605 | } | |
8187a2b7 | 1606 | |
5a5a0c64 | 1607 | uint32_t |
b962442e | 1608 | i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
852835f3 | 1609 | uint32_t flush_domains, struct intel_ring_buffer *ring) |
673a394b EA |
1610 | { |
1611 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b962442e | 1612 | struct drm_i915_file_private *i915_file_priv = NULL; |
673a394b EA |
1613 | struct drm_i915_gem_request *request; |
1614 | uint32_t seqno; | |
1615 | int was_empty; | |
673a394b | 1616 | |
b962442e EA |
1617 | if (file_priv != NULL) |
1618 | i915_file_priv = file_priv->driver_priv; | |
1619 | ||
9a298b2a | 1620 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
673a394b EA |
1621 | if (request == NULL) |
1622 | return 0; | |
1623 | ||
852835f3 | 1624 | seqno = ring->add_request(dev, ring, file_priv, flush_domains); |
673a394b EA |
1625 | |
1626 | request->seqno = seqno; | |
852835f3 | 1627 | request->ring = ring; |
673a394b | 1628 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1629 | was_empty = list_empty(&ring->request_list); |
1630 | list_add_tail(&request->list, &ring->request_list); | |
1631 | ||
b962442e EA |
1632 | if (i915_file_priv) { |
1633 | list_add_tail(&request->client_list, | |
1634 | &i915_file_priv->mm.request_list); | |
1635 | } else { | |
1636 | INIT_LIST_HEAD(&request->client_list); | |
1637 | } | |
673a394b | 1638 | |
ce44b0ea | 1639 | /* Associate any objects on the flushing list matching the write |
8bff917c | 1640 | * domain we're flushing with our request. |
ce44b0ea | 1641 | */ |
63560396 | 1642 | if (flush_domains != 0) |
852835f3 | 1643 | i915_gem_process_flushing_list(dev, flush_domains, seqno, ring); |
ce44b0ea | 1644 | |
f65d9421 BG |
1645 | if (!dev_priv->mm.suspended) { |
1646 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
1647 | if (was_empty) | |
1648 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1649 | } | |
673a394b EA |
1650 | return seqno; |
1651 | } | |
1652 | ||
1653 | /** | |
1654 | * Command execution barrier | |
1655 | * | |
1656 | * Ensures that all commands in the ring are finished | |
1657 | * before signalling the CPU | |
1658 | */ | |
3043c60c | 1659 | static uint32_t |
852835f3 | 1660 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1661 | { |
673a394b | 1662 | uint32_t flush_domains = 0; |
673a394b EA |
1663 | |
1664 | /* The sampler always gets flushed on i965 (sigh) */ | |
1665 | if (IS_I965G(dev)) | |
1666 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; | |
852835f3 ZN |
1667 | |
1668 | ring->flush(dev, ring, | |
1669 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1670 | return flush_domains; |
1671 | } | |
1672 | ||
1673 | /** | |
1674 | * Moves buffers associated only with the given active seqno from the active | |
1675 | * to inactive list, potentially freeing them. | |
1676 | */ | |
1677 | static void | |
1678 | i915_gem_retire_request(struct drm_device *dev, | |
1679 | struct drm_i915_gem_request *request) | |
1680 | { | |
1681 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1682 | ||
1c5d22f7 CW |
1683 | trace_i915_gem_request_retire(dev, request->seqno); |
1684 | ||
673a394b EA |
1685 | /* Move any buffers on the active list that are no longer referenced |
1686 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1687 | */ | |
5e118f41 | 1688 | spin_lock(&dev_priv->mm.active_list_lock); |
852835f3 | 1689 | while (!list_empty(&request->ring->active_list)) { |
673a394b EA |
1690 | struct drm_gem_object *obj; |
1691 | struct drm_i915_gem_object *obj_priv; | |
1692 | ||
852835f3 | 1693 | obj_priv = list_first_entry(&request->ring->active_list, |
673a394b EA |
1694 | struct drm_i915_gem_object, |
1695 | list); | |
a8089e84 | 1696 | obj = &obj_priv->base; |
673a394b EA |
1697 | |
1698 | /* If the seqno being retired doesn't match the oldest in the | |
1699 | * list, then the oldest in the list must still be newer than | |
1700 | * this seqno. | |
1701 | */ | |
1702 | if (obj_priv->last_rendering_seqno != request->seqno) | |
5e118f41 | 1703 | goto out; |
de151cf6 | 1704 | |
673a394b EA |
1705 | #if WATCH_LRU |
1706 | DRM_INFO("%s: retire %d moves to inactive list %p\n", | |
1707 | __func__, request->seqno, obj); | |
1708 | #endif | |
1709 | ||
ce44b0ea EA |
1710 | if (obj->write_domain != 0) |
1711 | i915_gem_object_move_to_flushing(obj); | |
68c84342 SL |
1712 | else { |
1713 | /* Take a reference on the object so it won't be | |
1714 | * freed while the spinlock is held. The list | |
1715 | * protection for this spinlock is safe when breaking | |
1716 | * the lock like this since the next thing we do | |
1717 | * is just get the head of the list again. | |
1718 | */ | |
1719 | drm_gem_object_reference(obj); | |
673a394b | 1720 | i915_gem_object_move_to_inactive(obj); |
68c84342 SL |
1721 | spin_unlock(&dev_priv->mm.active_list_lock); |
1722 | drm_gem_object_unreference(obj); | |
1723 | spin_lock(&dev_priv->mm.active_list_lock); | |
1724 | } | |
673a394b | 1725 | } |
5e118f41 CW |
1726 | out: |
1727 | spin_unlock(&dev_priv->mm.active_list_lock); | |
673a394b EA |
1728 | } |
1729 | ||
1730 | /** | |
1731 | * Returns true if seq1 is later than seq2. | |
1732 | */ | |
22be1724 | 1733 | bool |
673a394b EA |
1734 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1735 | { | |
1736 | return (int32_t)(seq1 - seq2) >= 0; | |
1737 | } | |
1738 | ||
1739 | uint32_t | |
852835f3 | 1740 | i915_get_gem_seqno(struct drm_device *dev, |
d1b851fc | 1741 | struct intel_ring_buffer *ring) |
673a394b | 1742 | { |
852835f3 | 1743 | return ring->get_gem_seqno(dev, ring); |
673a394b EA |
1744 | } |
1745 | ||
1746 | /** | |
1747 | * This function clears the request list as sequence numbers are passed. | |
1748 | */ | |
b09a1fec CW |
1749 | static void |
1750 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1751 | struct intel_ring_buffer *ring) | |
673a394b EA |
1752 | { |
1753 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1754 | uint32_t seqno; | |
1755 | ||
8187a2b7 | 1756 | if (!ring->status_page.page_addr |
852835f3 | 1757 | || list_empty(&ring->request_list)) |
6c0594a3 KW |
1758 | return; |
1759 | ||
852835f3 | 1760 | seqno = i915_get_gem_seqno(dev, ring); |
673a394b | 1761 | |
852835f3 | 1762 | while (!list_empty(&ring->request_list)) { |
673a394b EA |
1763 | struct drm_i915_gem_request *request; |
1764 | uint32_t retiring_seqno; | |
1765 | ||
852835f3 | 1766 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1767 | struct drm_i915_gem_request, |
1768 | list); | |
1769 | retiring_seqno = request->seqno; | |
1770 | ||
1771 | if (i915_seqno_passed(seqno, retiring_seqno) || | |
ba1234d1 | 1772 | atomic_read(&dev_priv->mm.wedged)) { |
673a394b EA |
1773 | i915_gem_retire_request(dev, request); |
1774 | ||
1775 | list_del(&request->list); | |
b962442e | 1776 | list_del(&request->client_list); |
9a298b2a | 1777 | kfree(request); |
673a394b EA |
1778 | } else |
1779 | break; | |
1780 | } | |
9d34e5db CW |
1781 | |
1782 | if (unlikely (dev_priv->trace_irq_seqno && | |
1783 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 ZN |
1784 | |
1785 | ring->user_irq_put(dev, ring); | |
9d34e5db CW |
1786 | dev_priv->trace_irq_seqno = 0; |
1787 | } | |
673a394b EA |
1788 | } |
1789 | ||
b09a1fec CW |
1790 | void |
1791 | i915_gem_retire_requests(struct drm_device *dev) | |
1792 | { | |
1793 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1794 | ||
be72615b CW |
1795 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1796 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1797 | ||
1798 | /* We must be careful that during unbind() we do not | |
1799 | * accidentally infinitely recurse into retire requests. | |
1800 | * Currently: | |
1801 | * retire -> free -> unbind -> wait -> retire_ring | |
1802 | */ | |
1803 | list_for_each_entry_safe(obj_priv, tmp, | |
1804 | &dev_priv->mm.deferred_free_list, | |
1805 | list) | |
1806 | i915_gem_free_object_tail(&obj_priv->base); | |
1807 | } | |
1808 | ||
b09a1fec CW |
1809 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
1810 | if (HAS_BSD(dev)) | |
1811 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); | |
1812 | } | |
1813 | ||
75ef9da2 | 1814 | static void |
673a394b EA |
1815 | i915_gem_retire_work_handler(struct work_struct *work) |
1816 | { | |
1817 | drm_i915_private_t *dev_priv; | |
1818 | struct drm_device *dev; | |
1819 | ||
1820 | dev_priv = container_of(work, drm_i915_private_t, | |
1821 | mm.retire_work.work); | |
1822 | dev = dev_priv->dev; | |
1823 | ||
1824 | mutex_lock(&dev->struct_mutex); | |
b09a1fec | 1825 | i915_gem_retire_requests(dev); |
d1b851fc | 1826 | |
6dbe2772 | 1827 | if (!dev_priv->mm.suspended && |
d1b851fc ZN |
1828 | (!list_empty(&dev_priv->render_ring.request_list) || |
1829 | (HAS_BSD(dev) && | |
1830 | !list_empty(&dev_priv->bsd_ring.request_list)))) | |
9c9fe1f8 | 1831 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1832 | mutex_unlock(&dev->struct_mutex); |
1833 | } | |
1834 | ||
5a5a0c64 | 1835 | int |
852835f3 ZN |
1836 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
1837 | int interruptible, struct intel_ring_buffer *ring) | |
673a394b EA |
1838 | { |
1839 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1840 | u32 ier; |
673a394b EA |
1841 | int ret = 0; |
1842 | ||
1843 | BUG_ON(seqno == 0); | |
1844 | ||
e35a41de DV |
1845 | if (seqno == dev_priv->next_seqno) { |
1846 | seqno = i915_add_request(dev, NULL, 0, ring); | |
1847 | if (seqno == 0) | |
1848 | return -ENOMEM; | |
1849 | } | |
1850 | ||
ba1234d1 | 1851 | if (atomic_read(&dev_priv->mm.wedged)) |
ffed1d09 BG |
1852 | return -EIO; |
1853 | ||
852835f3 | 1854 | if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) { |
bad720ff | 1855 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1856 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1857 | else | |
1858 | ier = I915_READ(IER); | |
802c7eb6 JB |
1859 | if (!ier) { |
1860 | DRM_ERROR("something (likely vbetool) disabled " | |
1861 | "interrupts, re-enabling\n"); | |
1862 | i915_driver_irq_preinstall(dev); | |
1863 | i915_driver_irq_postinstall(dev); | |
1864 | } | |
1865 | ||
1c5d22f7 CW |
1866 | trace_i915_gem_request_wait_begin(dev, seqno); |
1867 | ||
852835f3 | 1868 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 1869 | ring->user_irq_get(dev, ring); |
48764bf4 | 1870 | if (interruptible) |
852835f3 ZN |
1871 | ret = wait_event_interruptible(ring->irq_queue, |
1872 | i915_seqno_passed( | |
1873 | ring->get_gem_seqno(dev, ring), seqno) | |
1874 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1875 | else |
852835f3 ZN |
1876 | wait_event(ring->irq_queue, |
1877 | i915_seqno_passed( | |
1878 | ring->get_gem_seqno(dev, ring), seqno) | |
1879 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1880 | |
8187a2b7 | 1881 | ring->user_irq_put(dev, ring); |
852835f3 | 1882 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
1883 | |
1884 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 1885 | } |
ba1234d1 | 1886 | if (atomic_read(&dev_priv->mm.wedged)) |
673a394b EA |
1887 | ret = -EIO; |
1888 | ||
1889 | if (ret && ret != -ERESTARTSYS) | |
8bff917c DV |
1890 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
1891 | __func__, ret, seqno, ring->get_gem_seqno(dev, ring), | |
1892 | dev_priv->next_seqno); | |
673a394b EA |
1893 | |
1894 | /* Directly dispatch request retiring. While we have the work queue | |
1895 | * to handle this, the waiter on a request often wants an associated | |
1896 | * buffer to have made it to the inactive list, and we would need | |
1897 | * a separate wait queue to handle that. | |
1898 | */ | |
1899 | if (ret == 0) | |
b09a1fec | 1900 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
1901 | |
1902 | return ret; | |
1903 | } | |
1904 | ||
48764bf4 DV |
1905 | /** |
1906 | * Waits for a sequence number to be signaled, and cleans up the | |
1907 | * request and object lists appropriately for that event. | |
1908 | */ | |
1909 | static int | |
852835f3 ZN |
1910 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
1911 | struct intel_ring_buffer *ring) | |
48764bf4 | 1912 | { |
852835f3 | 1913 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
1914 | } |
1915 | ||
8187a2b7 ZN |
1916 | static void |
1917 | i915_gem_flush(struct drm_device *dev, | |
1918 | uint32_t invalidate_domains, | |
1919 | uint32_t flush_domains) | |
1920 | { | |
1921 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 1922 | |
8187a2b7 ZN |
1923 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
1924 | drm_agp_chipset_flush(dev); | |
8bff917c | 1925 | |
8187a2b7 ZN |
1926 | dev_priv->render_ring.flush(dev, &dev_priv->render_ring, |
1927 | invalidate_domains, | |
1928 | flush_domains); | |
d1b851fc ZN |
1929 | |
1930 | if (HAS_BSD(dev)) | |
1931 | dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring, | |
1932 | invalidate_domains, | |
1933 | flush_domains); | |
8bff917c DV |
1934 | |
1935 | /* Associate any objects on the flushing list matching the write | |
1936 | * domain we're flushing with the next request. | |
1937 | */ | |
1938 | if (flush_domains != 0) { | |
1939 | i915_gem_process_flushing_list(dev, flush_domains, 0, | |
1940 | &dev_priv->render_ring); | |
1941 | if (HAS_BSD(dev)) | |
1942 | i915_gem_process_flushing_list(dev, flush_domains, 0, | |
1943 | &dev_priv->bsd_ring); | |
1944 | } | |
8187a2b7 ZN |
1945 | } |
1946 | ||
673a394b EA |
1947 | /** |
1948 | * Ensures that all rendering to the object has completed and the object is | |
1949 | * safe to unbind from the GTT or access from the CPU. | |
1950 | */ | |
1951 | static int | |
e35a41de DV |
1952 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
1953 | bool interruptible) | |
673a394b EA |
1954 | { |
1955 | struct drm_device *dev = obj->dev; | |
23010e43 | 1956 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1957 | int ret; |
1958 | ||
e47c68e9 EA |
1959 | /* This function only exists to support waiting for existing rendering, |
1960 | * not for emitting required flushes. | |
673a394b | 1961 | */ |
e47c68e9 | 1962 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1963 | |
1964 | /* If there is rendering queued on the buffer being evicted, wait for | |
1965 | * it. | |
1966 | */ | |
1967 | if (obj_priv->active) { | |
1968 | #if WATCH_BUF | |
1969 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
1970 | __func__, obj, obj_priv->last_rendering_seqno); | |
1971 | #endif | |
e35a41de DV |
1972 | ret = i915_do_wait_request(dev, |
1973 | obj_priv->last_rendering_seqno, | |
1974 | interruptible, | |
1975 | obj_priv->ring); | |
673a394b EA |
1976 | if (ret != 0) |
1977 | return ret; | |
1978 | } | |
1979 | ||
1980 | return 0; | |
1981 | } | |
1982 | ||
1983 | /** | |
1984 | * Unbinds an object from the GTT aperture. | |
1985 | */ | |
0f973f27 | 1986 | int |
673a394b EA |
1987 | i915_gem_object_unbind(struct drm_gem_object *obj) |
1988 | { | |
1989 | struct drm_device *dev = obj->dev; | |
4a87b8ca | 1990 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1991 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1992 | int ret = 0; |
1993 | ||
1994 | #if WATCH_BUF | |
1995 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); | |
1996 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); | |
1997 | #endif | |
1998 | if (obj_priv->gtt_space == NULL) | |
1999 | return 0; | |
2000 | ||
2001 | if (obj_priv->pin_count != 0) { | |
2002 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2003 | return -EINVAL; | |
2004 | } | |
2005 | ||
5323fd04 EA |
2006 | /* blow away mappings if mapped through GTT */ |
2007 | i915_gem_release_mmap(obj); | |
2008 | ||
673a394b EA |
2009 | /* Move the object to the CPU domain to ensure that |
2010 | * any possible CPU writes while it's not in the GTT | |
2011 | * are flushed when we go to remap it. This will | |
2012 | * also ensure that all pending GPU writes are finished | |
2013 | * before we unbind. | |
2014 | */ | |
e47c68e9 | 2015 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2016 | if (ret == -ERESTARTSYS) |
673a394b | 2017 | return ret; |
8dc1775d CW |
2018 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2019 | * should be safe and we need to cleanup or else we might | |
2020 | * cause memory corruption through use-after-free. | |
2021 | */ | |
673a394b | 2022 | |
96b47b65 DV |
2023 | /* release the fence reg _after_ flushing */ |
2024 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2025 | i915_gem_clear_fence_reg(obj); | |
2026 | ||
673a394b EA |
2027 | if (obj_priv->agp_mem != NULL) { |
2028 | drm_unbind_agp(obj_priv->agp_mem); | |
2029 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
2030 | obj_priv->agp_mem = NULL; | |
2031 | } | |
2032 | ||
856fa198 | 2033 | i915_gem_object_put_pages(obj); |
a32808c0 | 2034 | BUG_ON(obj_priv->pages_refcount); |
673a394b EA |
2035 | |
2036 | if (obj_priv->gtt_space) { | |
2037 | atomic_dec(&dev->gtt_count); | |
2038 | atomic_sub(obj->size, &dev->gtt_memory); | |
2039 | ||
2040 | drm_mm_put_block(obj_priv->gtt_space); | |
2041 | obj_priv->gtt_space = NULL; | |
2042 | } | |
2043 | ||
2044 | /* Remove ourselves from the LRU list if present. */ | |
4a87b8ca | 2045 | spin_lock(&dev_priv->mm.active_list_lock); |
673a394b EA |
2046 | if (!list_empty(&obj_priv->list)) |
2047 | list_del_init(&obj_priv->list); | |
4a87b8ca | 2048 | spin_unlock(&dev_priv->mm.active_list_lock); |
673a394b | 2049 | |
963b4836 CW |
2050 | if (i915_gem_object_is_purgeable(obj_priv)) |
2051 | i915_gem_object_truncate(obj); | |
2052 | ||
1c5d22f7 CW |
2053 | trace_i915_gem_object_unbind(obj); |
2054 | ||
8dc1775d | 2055 | return ret; |
673a394b EA |
2056 | } |
2057 | ||
b47eb4a2 | 2058 | int |
4df2faf4 DV |
2059 | i915_gpu_idle(struct drm_device *dev) |
2060 | { | |
2061 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2062 | bool lists_empty; | |
d1b851fc | 2063 | uint32_t seqno1, seqno2; |
852835f3 | 2064 | int ret; |
4df2faf4 DV |
2065 | |
2066 | spin_lock(&dev_priv->mm.active_list_lock); | |
d1b851fc ZN |
2067 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2068 | list_empty(&dev_priv->render_ring.active_list) && | |
2069 | (!HAS_BSD(dev) || | |
2070 | list_empty(&dev_priv->bsd_ring.active_list))); | |
4df2faf4 DV |
2071 | spin_unlock(&dev_priv->mm.active_list_lock); |
2072 | ||
2073 | if (lists_empty) | |
2074 | return 0; | |
2075 | ||
2076 | /* Flush everything onto the inactive list. */ | |
2077 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
8bff917c | 2078 | seqno1 = i915_add_request(dev, NULL, 0, |
852835f3 | 2079 | &dev_priv->render_ring); |
d1b851fc | 2080 | if (seqno1 == 0) |
4df2faf4 | 2081 | return -ENOMEM; |
d1b851fc ZN |
2082 | ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring); |
2083 | ||
2084 | if (HAS_BSD(dev)) { | |
8bff917c | 2085 | seqno2 = i915_add_request(dev, NULL, 0, |
d1b851fc ZN |
2086 | &dev_priv->bsd_ring); |
2087 | if (seqno2 == 0) | |
2088 | return -ENOMEM; | |
2089 | ||
2090 | ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring); | |
2091 | if (ret) | |
2092 | return ret; | |
2093 | } | |
2094 | ||
852835f3 | 2095 | return ret; |
4df2faf4 DV |
2096 | } |
2097 | ||
6911a9b8 | 2098 | int |
4bdadb97 CW |
2099 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2100 | gfp_t gfpmask) | |
673a394b | 2101 | { |
23010e43 | 2102 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2103 | int page_count, i; |
2104 | struct address_space *mapping; | |
2105 | struct inode *inode; | |
2106 | struct page *page; | |
673a394b | 2107 | |
778c3544 DV |
2108 | BUG_ON(obj_priv->pages_refcount |
2109 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2110 | ||
856fa198 | 2111 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2112 | return 0; |
2113 | ||
2114 | /* Get the list of pages out of our struct file. They'll be pinned | |
2115 | * at this point until we release them. | |
2116 | */ | |
2117 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2118 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2119 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2120 | if (obj_priv->pages == NULL) { |
856fa198 | 2121 | obj_priv->pages_refcount--; |
673a394b EA |
2122 | return -ENOMEM; |
2123 | } | |
2124 | ||
2125 | inode = obj->filp->f_path.dentry->d_inode; | |
2126 | mapping = inode->i_mapping; | |
2127 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2128 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2129 | GFP_HIGHUSER | |
4bdadb97 | 2130 | __GFP_COLD | |
cd9f040d | 2131 | __GFP_RECLAIMABLE | |
4bdadb97 | 2132 | gfpmask); |
1f2b1013 CW |
2133 | if (IS_ERR(page)) |
2134 | goto err_pages; | |
2135 | ||
856fa198 | 2136 | obj_priv->pages[i] = page; |
673a394b | 2137 | } |
280b713b EA |
2138 | |
2139 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2140 | i915_gem_object_do_bit_17_swizzle(obj); | |
2141 | ||
673a394b | 2142 | return 0; |
1f2b1013 CW |
2143 | |
2144 | err_pages: | |
2145 | while (i--) | |
2146 | page_cache_release(obj_priv->pages[i]); | |
2147 | ||
2148 | drm_free_large(obj_priv->pages); | |
2149 | obj_priv->pages = NULL; | |
2150 | obj_priv->pages_refcount--; | |
2151 | return PTR_ERR(page); | |
673a394b EA |
2152 | } |
2153 | ||
4e901fdc EA |
2154 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2155 | { | |
2156 | struct drm_gem_object *obj = reg->obj; | |
2157 | struct drm_device *dev = obj->dev; | |
2158 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2159 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2160 | int regnum = obj_priv->fence_reg; |
2161 | uint64_t val; | |
2162 | ||
2163 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2164 | 0xfffff000) << 32; | |
2165 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2166 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2167 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2168 | ||
2169 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2170 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2171 | val |= I965_FENCE_REG_VALID; | |
2172 | ||
2173 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2174 | } | |
2175 | ||
de151cf6 JB |
2176 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2177 | { | |
2178 | struct drm_gem_object *obj = reg->obj; | |
2179 | struct drm_device *dev = obj->dev; | |
2180 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2181 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2182 | int regnum = obj_priv->fence_reg; |
2183 | uint64_t val; | |
2184 | ||
2185 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2186 | 0xfffff000) << 32; | |
2187 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2188 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2189 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2190 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2191 | val |= I965_FENCE_REG_VALID; | |
2192 | ||
2193 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2194 | } | |
2195 | ||
2196 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2197 | { | |
2198 | struct drm_gem_object *obj = reg->obj; | |
2199 | struct drm_device *dev = obj->dev; | |
2200 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2201 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2202 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2203 | int tile_width; |
dc529a4f | 2204 | uint32_t fence_reg, val; |
de151cf6 JB |
2205 | uint32_t pitch_val; |
2206 | ||
2207 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2208 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2209 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2210 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2211 | return; |
2212 | } | |
2213 | ||
0f973f27 JB |
2214 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2215 | HAS_128_BYTE_Y_TILING(dev)) | |
2216 | tile_width = 128; | |
de151cf6 | 2217 | else |
0f973f27 JB |
2218 | tile_width = 512; |
2219 | ||
2220 | /* Note: pitch better be a power of two tile widths */ | |
2221 | pitch_val = obj_priv->stride / tile_width; | |
2222 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2223 | |
c36a2a6d DV |
2224 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2225 | HAS_128_BYTE_Y_TILING(dev)) | |
2226 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2227 | else | |
2228 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2229 | ||
de151cf6 JB |
2230 | val = obj_priv->gtt_offset; |
2231 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2232 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2233 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2234 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2235 | val |= I830_FENCE_REG_VALID; | |
2236 | ||
dc529a4f EA |
2237 | if (regnum < 8) |
2238 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2239 | else | |
2240 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2241 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2242 | } |
2243 | ||
2244 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2245 | { | |
2246 | struct drm_gem_object *obj = reg->obj; | |
2247 | struct drm_device *dev = obj->dev; | |
2248 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2249 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2250 | int regnum = obj_priv->fence_reg; |
2251 | uint32_t val; | |
2252 | uint32_t pitch_val; | |
8d7773a3 | 2253 | uint32_t fence_size_bits; |
de151cf6 | 2254 | |
8d7773a3 | 2255 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2256 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2257 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2258 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2259 | return; |
2260 | } | |
2261 | ||
e76a16de EA |
2262 | pitch_val = obj_priv->stride / 128; |
2263 | pitch_val = ffs(pitch_val) - 1; | |
2264 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2265 | ||
de151cf6 JB |
2266 | val = obj_priv->gtt_offset; |
2267 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2268 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2269 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2270 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2271 | val |= fence_size_bits; | |
de151cf6 JB |
2272 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2273 | val |= I830_FENCE_REG_VALID; | |
2274 | ||
2275 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2276 | } |
2277 | ||
ae3db24a DV |
2278 | static int i915_find_fence_reg(struct drm_device *dev) |
2279 | { | |
2280 | struct drm_i915_fence_reg *reg = NULL; | |
2281 | struct drm_i915_gem_object *obj_priv = NULL; | |
2282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2283 | struct drm_gem_object *obj = NULL; | |
2284 | int i, avail, ret; | |
2285 | ||
2286 | /* First try to find a free reg */ | |
2287 | avail = 0; | |
2288 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2289 | reg = &dev_priv->fence_regs[i]; | |
2290 | if (!reg->obj) | |
2291 | return i; | |
2292 | ||
23010e43 | 2293 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2294 | if (!obj_priv->pin_count) |
2295 | avail++; | |
2296 | } | |
2297 | ||
2298 | if (avail == 0) | |
2299 | return -ENOSPC; | |
2300 | ||
2301 | /* None available, try to steal one or wait for a user to finish */ | |
2302 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2303 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2304 | lru_list) { | |
2305 | obj = reg->obj; | |
2306 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2307 | |
2308 | if (obj_priv->pin_count) | |
2309 | continue; | |
2310 | ||
2311 | /* found one! */ | |
2312 | i = obj_priv->fence_reg; | |
2313 | break; | |
2314 | } | |
2315 | ||
2316 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2317 | ||
2318 | /* We only have a reference on obj from the active list. put_fence_reg | |
2319 | * might drop that one, causing a use-after-free in it. So hold a | |
2320 | * private reference to obj like the other callers of put_fence_reg | |
2321 | * (set_tiling ioctl) do. */ | |
2322 | drm_gem_object_reference(obj); | |
2323 | ret = i915_gem_object_put_fence_reg(obj); | |
2324 | drm_gem_object_unreference(obj); | |
2325 | if (ret != 0) | |
2326 | return ret; | |
2327 | ||
2328 | return i; | |
2329 | } | |
2330 | ||
de151cf6 JB |
2331 | /** |
2332 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2333 | * @obj: object to map through a fence reg | |
2334 | * | |
2335 | * When mapping objects through the GTT, userspace wants to be able to write | |
2336 | * to them without having to worry about swizzling if the object is tiled. | |
2337 | * | |
2338 | * This function walks the fence regs looking for a free one for @obj, | |
2339 | * stealing one if it can't find any. | |
2340 | * | |
2341 | * It then sets up the reg based on the object's properties: address, pitch | |
2342 | * and tiling format. | |
2343 | */ | |
8c4b8c3f CW |
2344 | int |
2345 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) | |
de151cf6 JB |
2346 | { |
2347 | struct drm_device *dev = obj->dev; | |
79e53945 | 2348 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2349 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2350 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2351 | int ret; |
de151cf6 | 2352 | |
a09ba7fa EA |
2353 | /* Just update our place in the LRU if our fence is getting used. */ |
2354 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2355 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2356 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2357 | return 0; |
2358 | } | |
2359 | ||
de151cf6 JB |
2360 | switch (obj_priv->tiling_mode) { |
2361 | case I915_TILING_NONE: | |
2362 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2363 | break; | |
2364 | case I915_TILING_X: | |
0f973f27 JB |
2365 | if (!obj_priv->stride) |
2366 | return -EINVAL; | |
2367 | WARN((obj_priv->stride & (512 - 1)), | |
2368 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2369 | obj_priv->gtt_offset); | |
de151cf6 JB |
2370 | break; |
2371 | case I915_TILING_Y: | |
0f973f27 JB |
2372 | if (!obj_priv->stride) |
2373 | return -EINVAL; | |
2374 | WARN((obj_priv->stride & (128 - 1)), | |
2375 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2376 | obj_priv->gtt_offset); | |
de151cf6 JB |
2377 | break; |
2378 | } | |
2379 | ||
ae3db24a DV |
2380 | ret = i915_find_fence_reg(dev); |
2381 | if (ret < 0) | |
2382 | return ret; | |
de151cf6 | 2383 | |
ae3db24a DV |
2384 | obj_priv->fence_reg = ret; |
2385 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2386 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2387 | |
de151cf6 JB |
2388 | reg->obj = obj; |
2389 | ||
4e901fdc EA |
2390 | if (IS_GEN6(dev)) |
2391 | sandybridge_write_fence_reg(reg); | |
2392 | else if (IS_I965G(dev)) | |
de151cf6 JB |
2393 | i965_write_fence_reg(reg); |
2394 | else if (IS_I9XX(dev)) | |
2395 | i915_write_fence_reg(reg); | |
2396 | else | |
2397 | i830_write_fence_reg(reg); | |
d9ddcb96 | 2398 | |
ae3db24a DV |
2399 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2400 | obj_priv->tiling_mode); | |
1c5d22f7 | 2401 | |
d9ddcb96 | 2402 | return 0; |
de151cf6 JB |
2403 | } |
2404 | ||
2405 | /** | |
2406 | * i915_gem_clear_fence_reg - clear out fence register info | |
2407 | * @obj: object to clear | |
2408 | * | |
2409 | * Zeroes out the fence register itself and clears out the associated | |
2410 | * data structures in dev_priv and obj_priv. | |
2411 | */ | |
2412 | static void | |
2413 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2414 | { | |
2415 | struct drm_device *dev = obj->dev; | |
79e53945 | 2416 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2417 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2418 | struct drm_i915_fence_reg *reg = |
2419 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
de151cf6 | 2420 | |
4e901fdc EA |
2421 | if (IS_GEN6(dev)) { |
2422 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + | |
2423 | (obj_priv->fence_reg * 8), 0); | |
2424 | } else if (IS_I965G(dev)) { | |
de151cf6 | 2425 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
4e901fdc | 2426 | } else { |
dc529a4f EA |
2427 | uint32_t fence_reg; |
2428 | ||
2429 | if (obj_priv->fence_reg < 8) | |
2430 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
2431 | else | |
2432 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - | |
2433 | 8) * 4; | |
2434 | ||
2435 | I915_WRITE(fence_reg, 0); | |
2436 | } | |
de151cf6 | 2437 | |
007cc8ac | 2438 | reg->obj = NULL; |
de151cf6 | 2439 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2440 | list_del_init(®->lru_list); |
de151cf6 JB |
2441 | } |
2442 | ||
52dc7d32 CW |
2443 | /** |
2444 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2445 | * to the buffer to finish, and then resets the fence register. | |
2446 | * @obj: tiled object holding a fence register. | |
2447 | * | |
2448 | * Zeroes out the fence register itself and clears out the associated | |
2449 | * data structures in dev_priv and obj_priv. | |
2450 | */ | |
2451 | int | |
2452 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) | |
2453 | { | |
2454 | struct drm_device *dev = obj->dev; | |
23010e43 | 2455 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
52dc7d32 CW |
2456 | |
2457 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2458 | return 0; | |
2459 | ||
10ae9bd2 DV |
2460 | /* If we've changed tiling, GTT-mappings of the object |
2461 | * need to re-fault to ensure that the correct fence register | |
2462 | * setup is in place. | |
2463 | */ | |
2464 | i915_gem_release_mmap(obj); | |
2465 | ||
52dc7d32 CW |
2466 | /* On the i915, GPU access to tiled buffers is via a fence, |
2467 | * therefore we must wait for any outstanding access to complete | |
2468 | * before clearing the fence. | |
2469 | */ | |
2470 | if (!IS_I965G(dev)) { | |
2471 | int ret; | |
2472 | ||
2dafb1e0 CW |
2473 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2474 | if (ret != 0) | |
2475 | return ret; | |
2476 | ||
e35a41de | 2477 | ret = i915_gem_object_wait_rendering(obj, true); |
52dc7d32 CW |
2478 | if (ret != 0) |
2479 | return ret; | |
2480 | } | |
2481 | ||
4a726612 | 2482 | i915_gem_object_flush_gtt_write_domain(obj); |
52dc7d32 CW |
2483 | i915_gem_clear_fence_reg (obj); |
2484 | ||
2485 | return 0; | |
2486 | } | |
2487 | ||
673a394b EA |
2488 | /** |
2489 | * Finds free space in the GTT aperture and binds the object there. | |
2490 | */ | |
2491 | static int | |
2492 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2493 | { | |
2494 | struct drm_device *dev = obj->dev; | |
2495 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2496 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2497 | struct drm_mm_node *free_space; |
4bdadb97 | 2498 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2499 | int ret; |
673a394b | 2500 | |
bb6baf76 | 2501 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2502 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2503 | return -EINVAL; | |
2504 | } | |
2505 | ||
673a394b | 2506 | if (alignment == 0) |
0f973f27 | 2507 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2508 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2509 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2510 | return -EINVAL; | |
2511 | } | |
2512 | ||
654fc607 CW |
2513 | /* If the object is bigger than the entire aperture, reject it early |
2514 | * before evicting everything in a vain attempt to find space. | |
2515 | */ | |
2516 | if (obj->size > dev->gtt_total) { | |
2517 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); | |
2518 | return -E2BIG; | |
2519 | } | |
2520 | ||
673a394b EA |
2521 | search_free: |
2522 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2523 | obj->size, alignment, 0); | |
2524 | if (free_space != NULL) { | |
2525 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2526 | alignment); | |
db3307a9 | 2527 | if (obj_priv->gtt_space != NULL) |
673a394b | 2528 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
673a394b EA |
2529 | } |
2530 | if (obj_priv->gtt_space == NULL) { | |
2531 | /* If the gtt is empty and we're still having trouble | |
2532 | * fitting our object in, we're out of memory. | |
2533 | */ | |
2534 | #if WATCH_LRU | |
2535 | DRM_INFO("%s: GTT full, evicting something\n", __func__); | |
2536 | #endif | |
0108a3ed | 2537 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2538 | if (ret) |
673a394b | 2539 | return ret; |
9731129c | 2540 | |
673a394b EA |
2541 | goto search_free; |
2542 | } | |
2543 | ||
2544 | #if WATCH_BUF | |
cfd43c02 | 2545 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
673a394b EA |
2546 | obj->size, obj_priv->gtt_offset); |
2547 | #endif | |
4bdadb97 | 2548 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2549 | if (ret) { |
2550 | drm_mm_put_block(obj_priv->gtt_space); | |
2551 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2552 | |
2553 | if (ret == -ENOMEM) { | |
2554 | /* first try to clear up some space from the GTT */ | |
0108a3ed DV |
2555 | ret = i915_gem_evict_something(dev, obj->size, |
2556 | alignment); | |
07f73f69 | 2557 | if (ret) { |
07f73f69 | 2558 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2559 | if (gfpmask) { |
2560 | gfpmask = 0; | |
2561 | goto search_free; | |
07f73f69 CW |
2562 | } |
2563 | ||
2564 | return ret; | |
2565 | } | |
2566 | ||
2567 | goto search_free; | |
2568 | } | |
2569 | ||
673a394b EA |
2570 | return ret; |
2571 | } | |
2572 | ||
673a394b EA |
2573 | /* Create an AGP memory structure pointing at our pages, and bind it |
2574 | * into the GTT. | |
2575 | */ | |
2576 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2577 | obj_priv->pages, |
07f73f69 | 2578 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2579 | obj_priv->gtt_offset, |
2580 | obj_priv->agp_type); | |
673a394b | 2581 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2582 | i915_gem_object_put_pages(obj); |
673a394b EA |
2583 | drm_mm_put_block(obj_priv->gtt_space); |
2584 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2585 | |
0108a3ed | 2586 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2587 | if (ret) |
07f73f69 | 2588 | return ret; |
07f73f69 CW |
2589 | |
2590 | goto search_free; | |
673a394b EA |
2591 | } |
2592 | atomic_inc(&dev->gtt_count); | |
2593 | atomic_add(obj->size, &dev->gtt_memory); | |
2594 | ||
bf1a1092 CW |
2595 | /* keep track of bounds object by adding it to the inactive list */ |
2596 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
2597 | ||
673a394b EA |
2598 | /* Assert that the object is not currently in any GPU domain. As it |
2599 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2600 | * a GPU cache | |
2601 | */ | |
21d509e3 CW |
2602 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2603 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2604 | |
1c5d22f7 CW |
2605 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2606 | ||
673a394b EA |
2607 | return 0; |
2608 | } | |
2609 | ||
2610 | void | |
2611 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2612 | { | |
23010e43 | 2613 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2614 | |
2615 | /* If we don't have a page list set up, then we're not pinned | |
2616 | * to GPU, and we can ignore the cache flush because it'll happen | |
2617 | * again at bind time. | |
2618 | */ | |
856fa198 | 2619 | if (obj_priv->pages == NULL) |
673a394b EA |
2620 | return; |
2621 | ||
1c5d22f7 | 2622 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2623 | |
856fa198 | 2624 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2625 | } |
2626 | ||
e47c68e9 | 2627 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2628 | static int |
e47c68e9 EA |
2629 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) |
2630 | { | |
2631 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2632 | uint32_t old_write_domain; |
852835f3 | 2633 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
e47c68e9 EA |
2634 | |
2635 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2636 | return 0; |
e47c68e9 EA |
2637 | |
2638 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2639 | old_write_domain = obj->write_domain; |
e47c68e9 | 2640 | i915_gem_flush(dev, 0, obj->write_domain); |
2dafb1e0 CW |
2641 | if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0) |
2642 | return -ENOMEM; | |
1c5d22f7 CW |
2643 | |
2644 | trace_i915_gem_object_change_domain(obj, | |
2645 | obj->read_domains, | |
2646 | old_write_domain); | |
2dafb1e0 | 2647 | return 0; |
e47c68e9 EA |
2648 | } |
2649 | ||
2650 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2651 | static void | |
2652 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2653 | { | |
1c5d22f7 CW |
2654 | uint32_t old_write_domain; |
2655 | ||
e47c68e9 EA |
2656 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2657 | return; | |
2658 | ||
2659 | /* No actual flushing is required for the GTT write domain. Writes | |
2660 | * to it immediately go to main memory as far as we know, so there's | |
2661 | * no chipset flush. It also doesn't land in render cache. | |
2662 | */ | |
1c5d22f7 | 2663 | old_write_domain = obj->write_domain; |
e47c68e9 | 2664 | obj->write_domain = 0; |
1c5d22f7 CW |
2665 | |
2666 | trace_i915_gem_object_change_domain(obj, | |
2667 | obj->read_domains, | |
2668 | old_write_domain); | |
e47c68e9 EA |
2669 | } |
2670 | ||
2671 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2672 | static void | |
2673 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2674 | { | |
2675 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2676 | uint32_t old_write_domain; |
e47c68e9 EA |
2677 | |
2678 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2679 | return; | |
2680 | ||
2681 | i915_gem_clflush_object(obj); | |
2682 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2683 | old_write_domain = obj->write_domain; |
e47c68e9 | 2684 | obj->write_domain = 0; |
1c5d22f7 CW |
2685 | |
2686 | trace_i915_gem_object_change_domain(obj, | |
2687 | obj->read_domains, | |
2688 | old_write_domain); | |
e47c68e9 EA |
2689 | } |
2690 | ||
2dafb1e0 | 2691 | int |
6b95a207 KH |
2692 | i915_gem_object_flush_write_domain(struct drm_gem_object *obj) |
2693 | { | |
2dafb1e0 CW |
2694 | int ret = 0; |
2695 | ||
6b95a207 KH |
2696 | switch (obj->write_domain) { |
2697 | case I915_GEM_DOMAIN_GTT: | |
2698 | i915_gem_object_flush_gtt_write_domain(obj); | |
2699 | break; | |
2700 | case I915_GEM_DOMAIN_CPU: | |
2701 | i915_gem_object_flush_cpu_write_domain(obj); | |
2702 | break; | |
2703 | default: | |
2dafb1e0 | 2704 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
6b95a207 KH |
2705 | break; |
2706 | } | |
2dafb1e0 CW |
2707 | |
2708 | return ret; | |
6b95a207 KH |
2709 | } |
2710 | ||
2ef7eeaa EA |
2711 | /** |
2712 | * Moves a single object to the GTT read, and possibly write domain. | |
2713 | * | |
2714 | * This function returns when the move is complete, including waiting on | |
2715 | * flushes to occur. | |
2716 | */ | |
79e53945 | 2717 | int |
2ef7eeaa EA |
2718 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2719 | { | |
23010e43 | 2720 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2721 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2722 | int ret; |
2ef7eeaa | 2723 | |
02354392 EA |
2724 | /* Not valid to be called on unbound objects. */ |
2725 | if (obj_priv->gtt_space == NULL) | |
2726 | return -EINVAL; | |
2727 | ||
2dafb1e0 CW |
2728 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2729 | if (ret != 0) | |
2730 | return ret; | |
2731 | ||
e47c68e9 | 2732 | /* Wait on any GPU rendering and flushing to occur. */ |
e35a41de | 2733 | ret = i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2734 | if (ret != 0) |
2735 | return ret; | |
2736 | ||
1c5d22f7 CW |
2737 | old_write_domain = obj->write_domain; |
2738 | old_read_domains = obj->read_domains; | |
2739 | ||
e47c68e9 EA |
2740 | /* If we're writing through the GTT domain, then CPU and GPU caches |
2741 | * will need to be invalidated at next use. | |
2ef7eeaa | 2742 | */ |
e47c68e9 EA |
2743 | if (write) |
2744 | obj->read_domains &= I915_GEM_DOMAIN_GTT; | |
2ef7eeaa | 2745 | |
e47c68e9 | 2746 | i915_gem_object_flush_cpu_write_domain(obj); |
2ef7eeaa | 2747 | |
e47c68e9 EA |
2748 | /* It should now be out of any other write domains, and we can update |
2749 | * the domain values for our changes. | |
2750 | */ | |
2751 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2752 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2753 | if (write) { | |
2754 | obj->write_domain = I915_GEM_DOMAIN_GTT; | |
2755 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2756 | } |
2757 | ||
1c5d22f7 CW |
2758 | trace_i915_gem_object_change_domain(obj, |
2759 | old_read_domains, | |
2760 | old_write_domain); | |
2761 | ||
e47c68e9 EA |
2762 | return 0; |
2763 | } | |
2764 | ||
b9241ea3 ZW |
2765 | /* |
2766 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2767 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2768 | */ | |
2769 | int | |
2770 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj) | |
2771 | { | |
23010e43 | 2772 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
b9241ea3 ZW |
2773 | uint32_t old_write_domain, old_read_domains; |
2774 | int ret; | |
2775 | ||
2776 | /* Not valid to be called on unbound objects. */ | |
2777 | if (obj_priv->gtt_space == NULL) | |
2778 | return -EINVAL; | |
2779 | ||
2dafb1e0 CW |
2780 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2781 | if (ret) | |
2782 | return ret; | |
b9241ea3 ZW |
2783 | |
2784 | /* Wait on any GPU rendering and flushing to occur. */ | |
e35a41de DV |
2785 | ret = i915_gem_object_wait_rendering(obj, false); |
2786 | if (ret != 0) | |
2787 | return ret; | |
b9241ea3 | 2788 | |
b118c1e3 CW |
2789 | i915_gem_object_flush_cpu_write_domain(obj); |
2790 | ||
b9241ea3 ZW |
2791 | old_write_domain = obj->write_domain; |
2792 | old_read_domains = obj->read_domains; | |
2793 | ||
b9241ea3 ZW |
2794 | /* It should now be out of any other write domains, and we can update |
2795 | * the domain values for our changes. | |
2796 | */ | |
2797 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
b118c1e3 | 2798 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2799 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2800 | obj_priv->dirty = 1; | |
2801 | ||
2802 | trace_i915_gem_object_change_domain(obj, | |
2803 | old_read_domains, | |
2804 | old_write_domain); | |
2805 | ||
2806 | return 0; | |
2807 | } | |
2808 | ||
e47c68e9 EA |
2809 | /** |
2810 | * Moves a single object to the CPU read, and possibly write domain. | |
2811 | * | |
2812 | * This function returns when the move is complete, including waiting on | |
2813 | * flushes to occur. | |
2814 | */ | |
2815 | static int | |
2816 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2817 | { | |
1c5d22f7 | 2818 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2819 | int ret; |
2820 | ||
2dafb1e0 CW |
2821 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2822 | if (ret) | |
2823 | return ret; | |
2824 | ||
2ef7eeaa | 2825 | /* Wait on any GPU rendering and flushing to occur. */ |
e35a41de | 2826 | ret = i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2827 | if (ret != 0) |
2828 | return ret; | |
2ef7eeaa | 2829 | |
e47c68e9 | 2830 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2831 | |
e47c68e9 EA |
2832 | /* If we have a partially-valid cache of the object in the CPU, |
2833 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2834 | */ |
e47c68e9 | 2835 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2836 | |
1c5d22f7 CW |
2837 | old_write_domain = obj->write_domain; |
2838 | old_read_domains = obj->read_domains; | |
2839 | ||
e47c68e9 EA |
2840 | /* Flush the CPU cache if it's still invalid. */ |
2841 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2842 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2843 | |
e47c68e9 | 2844 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2845 | } |
2846 | ||
2847 | /* It should now be out of any other write domains, and we can update | |
2848 | * the domain values for our changes. | |
2849 | */ | |
e47c68e9 EA |
2850 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2851 | ||
2852 | /* If we're writing through the CPU, then the GPU read domains will | |
2853 | * need to be invalidated at next use. | |
2854 | */ | |
2855 | if (write) { | |
2856 | obj->read_domains &= I915_GEM_DOMAIN_CPU; | |
2857 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2858 | } | |
2ef7eeaa | 2859 | |
1c5d22f7 CW |
2860 | trace_i915_gem_object_change_domain(obj, |
2861 | old_read_domains, | |
2862 | old_write_domain); | |
2863 | ||
2ef7eeaa EA |
2864 | return 0; |
2865 | } | |
2866 | ||
673a394b EA |
2867 | /* |
2868 | * Set the next domain for the specified object. This | |
2869 | * may not actually perform the necessary flushing/invaliding though, | |
2870 | * as that may want to be batched with other set_domain operations | |
2871 | * | |
2872 | * This is (we hope) the only really tricky part of gem. The goal | |
2873 | * is fairly simple -- track which caches hold bits of the object | |
2874 | * and make sure they remain coherent. A few concrete examples may | |
2875 | * help to explain how it works. For shorthand, we use the notation | |
2876 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2877 | * a pair of read and write domain masks. | |
2878 | * | |
2879 | * Case 1: the batch buffer | |
2880 | * | |
2881 | * 1. Allocated | |
2882 | * 2. Written by CPU | |
2883 | * 3. Mapped to GTT | |
2884 | * 4. Read by GPU | |
2885 | * 5. Unmapped from GTT | |
2886 | * 6. Freed | |
2887 | * | |
2888 | * Let's take these a step at a time | |
2889 | * | |
2890 | * 1. Allocated | |
2891 | * Pages allocated from the kernel may still have | |
2892 | * cache contents, so we set them to (CPU, CPU) always. | |
2893 | * 2. Written by CPU (using pwrite) | |
2894 | * The pwrite function calls set_domain (CPU, CPU) and | |
2895 | * this function does nothing (as nothing changes) | |
2896 | * 3. Mapped by GTT | |
2897 | * This function asserts that the object is not | |
2898 | * currently in any GPU-based read or write domains | |
2899 | * 4. Read by GPU | |
2900 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
2901 | * As write_domain is zero, this function adds in the | |
2902 | * current read domains (CPU+COMMAND, 0). | |
2903 | * flush_domains is set to CPU. | |
2904 | * invalidate_domains is set to COMMAND | |
2905 | * clflush is run to get data out of the CPU caches | |
2906 | * then i915_dev_set_domain calls i915_gem_flush to | |
2907 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
2908 | * 5. Unmapped from GTT | |
2909 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
2910 | * flush_domains and invalidate_domains end up both zero | |
2911 | * so no flushing/invalidating happens | |
2912 | * 6. Freed | |
2913 | * yay, done | |
2914 | * | |
2915 | * Case 2: The shared render buffer | |
2916 | * | |
2917 | * 1. Allocated | |
2918 | * 2. Mapped to GTT | |
2919 | * 3. Read/written by GPU | |
2920 | * 4. set_domain to (CPU,CPU) | |
2921 | * 5. Read/written by CPU | |
2922 | * 6. Read/written by GPU | |
2923 | * | |
2924 | * 1. Allocated | |
2925 | * Same as last example, (CPU, CPU) | |
2926 | * 2. Mapped to GTT | |
2927 | * Nothing changes (assertions find that it is not in the GPU) | |
2928 | * 3. Read/written by GPU | |
2929 | * execbuffer calls set_domain (RENDER, RENDER) | |
2930 | * flush_domains gets CPU | |
2931 | * invalidate_domains gets GPU | |
2932 | * clflush (obj) | |
2933 | * MI_FLUSH and drm_agp_chipset_flush | |
2934 | * 4. set_domain (CPU, CPU) | |
2935 | * flush_domains gets GPU | |
2936 | * invalidate_domains gets CPU | |
2937 | * wait_rendering (obj) to make sure all drawing is complete. | |
2938 | * This will include an MI_FLUSH to get the data from GPU | |
2939 | * to memory | |
2940 | * clflush (obj) to invalidate the CPU cache | |
2941 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
2942 | * 5. Read/written by CPU | |
2943 | * cache lines are loaded and dirtied | |
2944 | * 6. Read written by GPU | |
2945 | * Same as last GPU access | |
2946 | * | |
2947 | * Case 3: The constant buffer | |
2948 | * | |
2949 | * 1. Allocated | |
2950 | * 2. Written by CPU | |
2951 | * 3. Read by GPU | |
2952 | * 4. Updated (written) by CPU again | |
2953 | * 5. Read by GPU | |
2954 | * | |
2955 | * 1. Allocated | |
2956 | * (CPU, CPU) | |
2957 | * 2. Written by CPU | |
2958 | * (CPU, CPU) | |
2959 | * 3. Read by GPU | |
2960 | * (CPU+RENDER, 0) | |
2961 | * flush_domains = CPU | |
2962 | * invalidate_domains = RENDER | |
2963 | * clflush (obj) | |
2964 | * MI_FLUSH | |
2965 | * drm_agp_chipset_flush | |
2966 | * 4. Updated (written) by CPU again | |
2967 | * (CPU, CPU) | |
2968 | * flush_domains = 0 (no previous write domain) | |
2969 | * invalidate_domains = 0 (no new read domains) | |
2970 | * 5. Read by GPU | |
2971 | * (CPU+RENDER, 0) | |
2972 | * flush_domains = CPU | |
2973 | * invalidate_domains = RENDER | |
2974 | * clflush (obj) | |
2975 | * MI_FLUSH | |
2976 | * drm_agp_chipset_flush | |
2977 | */ | |
c0d90829 | 2978 | static void |
8b0e378a | 2979 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
2980 | { |
2981 | struct drm_device *dev = obj->dev; | |
88f356b7 | 2982 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2983 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2984 | uint32_t invalidate_domains = 0; |
2985 | uint32_t flush_domains = 0; | |
1c5d22f7 | 2986 | uint32_t old_read_domains; |
e47c68e9 | 2987 | |
8b0e378a EA |
2988 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
2989 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 2990 | |
652c393a JB |
2991 | intel_mark_busy(dev, obj); |
2992 | ||
673a394b EA |
2993 | #if WATCH_BUF |
2994 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", | |
2995 | __func__, obj, | |
8b0e378a EA |
2996 | obj->read_domains, obj->pending_read_domains, |
2997 | obj->write_domain, obj->pending_write_domain); | |
673a394b EA |
2998 | #endif |
2999 | /* | |
3000 | * If the object isn't moving to a new write domain, | |
3001 | * let the object stay in multiple read domains | |
3002 | */ | |
8b0e378a EA |
3003 | if (obj->pending_write_domain == 0) |
3004 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3005 | else |
3006 | obj_priv->dirty = 1; | |
3007 | ||
3008 | /* | |
3009 | * Flush the current write domain if | |
3010 | * the new read domains don't match. Invalidate | |
3011 | * any read domains which differ from the old | |
3012 | * write domain | |
3013 | */ | |
8b0e378a EA |
3014 | if (obj->write_domain && |
3015 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3016 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3017 | invalidate_domains |= |
3018 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3019 | } |
3020 | /* | |
3021 | * Invalidate any read caches which may have | |
3022 | * stale data. That is, any new read domains. | |
3023 | */ | |
8b0e378a | 3024 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
673a394b EA |
3025 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
3026 | #if WATCH_BUF | |
3027 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", | |
3028 | __func__, flush_domains, invalidate_domains); | |
3029 | #endif | |
673a394b EA |
3030 | i915_gem_clflush_object(obj); |
3031 | } | |
3032 | ||
1c5d22f7 CW |
3033 | old_read_domains = obj->read_domains; |
3034 | ||
efbeed96 EA |
3035 | /* The actual obj->write_domain will be updated with |
3036 | * pending_write_domain after we emit the accumulated flush for all | |
3037 | * of our domain changes in execbuffers (which clears objects' | |
3038 | * write_domains). So if we have a current write domain that we | |
3039 | * aren't changing, set pending_write_domain to that. | |
3040 | */ | |
3041 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3042 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3043 | obj->read_domains = obj->pending_read_domains; |
673a394b | 3044 | |
88f356b7 CW |
3045 | if (flush_domains & I915_GEM_GPU_DOMAINS) { |
3046 | if (obj_priv->ring == &dev_priv->render_ring) | |
3047 | dev_priv->flush_rings |= FLUSH_RENDER_RING; | |
3048 | else if (obj_priv->ring == &dev_priv->bsd_ring) | |
3049 | dev_priv->flush_rings |= FLUSH_BSD_RING; | |
3050 | } | |
3051 | ||
673a394b EA |
3052 | dev->invalidate_domains |= invalidate_domains; |
3053 | dev->flush_domains |= flush_domains; | |
3054 | #if WATCH_BUF | |
3055 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", | |
3056 | __func__, | |
3057 | obj->read_domains, obj->write_domain, | |
3058 | dev->invalidate_domains, dev->flush_domains); | |
3059 | #endif | |
1c5d22f7 CW |
3060 | |
3061 | trace_i915_gem_object_change_domain(obj, | |
3062 | old_read_domains, | |
3063 | obj->write_domain); | |
673a394b EA |
3064 | } |
3065 | ||
3066 | /** | |
e47c68e9 | 3067 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3068 | * |
e47c68e9 EA |
3069 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3070 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3071 | */ |
e47c68e9 EA |
3072 | static void |
3073 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3074 | { |
23010e43 | 3075 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3076 | |
e47c68e9 EA |
3077 | if (!obj_priv->page_cpu_valid) |
3078 | return; | |
3079 | ||
3080 | /* If we're partially in the CPU read domain, finish moving it in. | |
3081 | */ | |
3082 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3083 | int i; | |
3084 | ||
3085 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3086 | if (obj_priv->page_cpu_valid[i]) | |
3087 | continue; | |
856fa198 | 3088 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3089 | } |
e47c68e9 EA |
3090 | } |
3091 | ||
3092 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3093 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3094 | */ | |
9a298b2a | 3095 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3096 | obj_priv->page_cpu_valid = NULL; |
3097 | } | |
3098 | ||
3099 | /** | |
3100 | * Set the CPU read domain on a range of the object. | |
3101 | * | |
3102 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3103 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3104 | * pages have been flushed, and will be respected by | |
3105 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3106 | * of the whole object. | |
3107 | * | |
3108 | * This function returns when the move is complete, including waiting on | |
3109 | * flushes to occur. | |
3110 | */ | |
3111 | static int | |
3112 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3113 | uint64_t offset, uint64_t size) | |
3114 | { | |
23010e43 | 3115 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3116 | uint32_t old_read_domains; |
e47c68e9 | 3117 | int i, ret; |
673a394b | 3118 | |
e47c68e9 EA |
3119 | if (offset == 0 && size == obj->size) |
3120 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3121 | |
2dafb1e0 CW |
3122 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3123 | if (ret) | |
3124 | return ret; | |
3125 | ||
e47c68e9 | 3126 | /* Wait on any GPU rendering and flushing to occur. */ |
e35a41de | 3127 | ret = i915_gem_object_wait_rendering(obj, true); |
e47c68e9 | 3128 | if (ret != 0) |
6a47baa6 | 3129 | return ret; |
e47c68e9 EA |
3130 | i915_gem_object_flush_gtt_write_domain(obj); |
3131 | ||
3132 | /* If we're already fully in the CPU read domain, we're done. */ | |
3133 | if (obj_priv->page_cpu_valid == NULL && | |
3134 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3135 | return 0; | |
673a394b | 3136 | |
e47c68e9 EA |
3137 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3138 | * newly adding I915_GEM_DOMAIN_CPU | |
3139 | */ | |
673a394b | 3140 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3141 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3142 | GFP_KERNEL); | |
e47c68e9 EA |
3143 | if (obj_priv->page_cpu_valid == NULL) |
3144 | return -ENOMEM; | |
3145 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3146 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3147 | |
3148 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3149 | * perspective. | |
3150 | */ | |
e47c68e9 EA |
3151 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3152 | i++) { | |
673a394b EA |
3153 | if (obj_priv->page_cpu_valid[i]) |
3154 | continue; | |
3155 | ||
856fa198 | 3156 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3157 | |
3158 | obj_priv->page_cpu_valid[i] = 1; | |
3159 | } | |
3160 | ||
e47c68e9 EA |
3161 | /* It should now be out of any other write domains, and we can update |
3162 | * the domain values for our changes. | |
3163 | */ | |
3164 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3165 | ||
1c5d22f7 | 3166 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3167 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3168 | ||
1c5d22f7 CW |
3169 | trace_i915_gem_object_change_domain(obj, |
3170 | old_read_domains, | |
3171 | obj->write_domain); | |
3172 | ||
673a394b EA |
3173 | return 0; |
3174 | } | |
3175 | ||
673a394b EA |
3176 | /** |
3177 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3178 | */ | |
3179 | static int | |
3180 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3181 | struct drm_file *file_priv, | |
76446cac | 3182 | struct drm_i915_gem_exec_object2 *entry, |
40a5f0de | 3183 | struct drm_i915_gem_relocation_entry *relocs) |
673a394b EA |
3184 | { |
3185 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3186 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 3187 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3188 | int i, ret; |
0839ccb8 | 3189 | void __iomem *reloc_page; |
76446cac JB |
3190 | bool need_fence; |
3191 | ||
3192 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3193 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3194 | ||
3195 | /* Check fence reg constraints and rebind if necessary */ | |
808b24d6 CW |
3196 | if (need_fence && |
3197 | !i915_gem_object_fence_offset_ok(obj, | |
3198 | obj_priv->tiling_mode)) { | |
3199 | ret = i915_gem_object_unbind(obj); | |
3200 | if (ret) | |
3201 | return ret; | |
3202 | } | |
673a394b EA |
3203 | |
3204 | /* Choose the GTT offset for our buffer and put it there. */ | |
3205 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3206 | if (ret) | |
3207 | return ret; | |
3208 | ||
76446cac JB |
3209 | /* |
3210 | * Pre-965 chips need a fence register set up in order to | |
3211 | * properly handle blits to/from tiled surfaces. | |
3212 | */ | |
3213 | if (need_fence) { | |
3214 | ret = i915_gem_object_get_fence_reg(obj); | |
3215 | if (ret != 0) { | |
76446cac JB |
3216 | i915_gem_object_unpin(obj); |
3217 | return ret; | |
3218 | } | |
3219 | } | |
3220 | ||
673a394b EA |
3221 | entry->offset = obj_priv->gtt_offset; |
3222 | ||
673a394b EA |
3223 | /* Apply the relocations, using the GTT aperture to avoid cache |
3224 | * flushing requirements. | |
3225 | */ | |
3226 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 3227 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
3228 | struct drm_gem_object *target_obj; |
3229 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
3230 | uint32_t reloc_val, reloc_offset; |
3231 | uint32_t __iomem *reloc_entry; | |
673a394b | 3232 | |
673a394b | 3233 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 3234 | reloc->target_handle); |
673a394b EA |
3235 | if (target_obj == NULL) { |
3236 | i915_gem_object_unpin(obj); | |
bf79cb91 | 3237 | return -ENOENT; |
673a394b | 3238 | } |
23010e43 | 3239 | target_obj_priv = to_intel_bo(target_obj); |
673a394b | 3240 | |
8542a0bb CW |
3241 | #if WATCH_RELOC |
3242 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3243 | "read %08x write %08x gtt %08x " | |
3244 | "presumed %08x delta %08x\n", | |
3245 | __func__, | |
3246 | obj, | |
3247 | (int) reloc->offset, | |
3248 | (int) reloc->target_handle, | |
3249 | (int) reloc->read_domains, | |
3250 | (int) reloc->write_domain, | |
3251 | (int) target_obj_priv->gtt_offset, | |
3252 | (int) reloc->presumed_offset, | |
3253 | reloc->delta); | |
3254 | #endif | |
3255 | ||
673a394b EA |
3256 | /* The target buffer should have appeared before us in the |
3257 | * exec_object list, so it should have a GTT space bound by now. | |
3258 | */ | |
3259 | if (target_obj_priv->gtt_space == NULL) { | |
3260 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 3261 | reloc->target_handle); |
673a394b EA |
3262 | drm_gem_object_unreference(target_obj); |
3263 | i915_gem_object_unpin(obj); | |
3264 | return -EINVAL; | |
3265 | } | |
3266 | ||
8542a0bb | 3267 | /* Validate that the target is in a valid r/w GPU domain */ |
16edd550 DV |
3268 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
3269 | DRM_ERROR("reloc with multiple write domains: " | |
3270 | "obj %p target %d offset %d " | |
3271 | "read %08x write %08x", | |
3272 | obj, reloc->target_handle, | |
3273 | (int) reloc->offset, | |
3274 | reloc->read_domains, | |
3275 | reloc->write_domain); | |
3276 | return -EINVAL; | |
3277 | } | |
40a5f0de EA |
3278 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3279 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3280 | DRM_ERROR("reloc with read/write CPU domains: " |
3281 | "obj %p target %d offset %d " | |
3282 | "read %08x write %08x", | |
40a5f0de EA |
3283 | obj, reloc->target_handle, |
3284 | (int) reloc->offset, | |
3285 | reloc->read_domains, | |
3286 | reloc->write_domain); | |
491152b8 CW |
3287 | drm_gem_object_unreference(target_obj); |
3288 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3289 | return -EINVAL; |
3290 | } | |
40a5f0de EA |
3291 | if (reloc->write_domain && target_obj->pending_write_domain && |
3292 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3293 | DRM_ERROR("Write domain conflict: " |
3294 | "obj %p target %d offset %d " | |
3295 | "new %08x old %08x\n", | |
40a5f0de EA |
3296 | obj, reloc->target_handle, |
3297 | (int) reloc->offset, | |
3298 | reloc->write_domain, | |
673a394b EA |
3299 | target_obj->pending_write_domain); |
3300 | drm_gem_object_unreference(target_obj); | |
3301 | i915_gem_object_unpin(obj); | |
3302 | return -EINVAL; | |
3303 | } | |
3304 | ||
40a5f0de EA |
3305 | target_obj->pending_read_domains |= reloc->read_domains; |
3306 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3307 | |
3308 | /* If the relocation already has the right value in it, no | |
3309 | * more work needs to be done. | |
3310 | */ | |
40a5f0de | 3311 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3312 | drm_gem_object_unreference(target_obj); |
3313 | continue; | |
3314 | } | |
3315 | ||
8542a0bb CW |
3316 | /* Check that the relocation address is valid... */ |
3317 | if (reloc->offset > obj->size - 4) { | |
3318 | DRM_ERROR("Relocation beyond object bounds: " | |
3319 | "obj %p target %d offset %d size %d.\n", | |
3320 | obj, reloc->target_handle, | |
3321 | (int) reloc->offset, (int) obj->size); | |
3322 | drm_gem_object_unreference(target_obj); | |
3323 | i915_gem_object_unpin(obj); | |
3324 | return -EINVAL; | |
3325 | } | |
3326 | if (reloc->offset & 3) { | |
3327 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3328 | "obj %p target %d offset %d.\n", | |
3329 | obj, reloc->target_handle, | |
3330 | (int) reloc->offset); | |
3331 | drm_gem_object_unreference(target_obj); | |
3332 | i915_gem_object_unpin(obj); | |
3333 | return -EINVAL; | |
3334 | } | |
3335 | ||
3336 | /* and points to somewhere within the target object. */ | |
3337 | if (reloc->delta >= target_obj->size) { | |
3338 | DRM_ERROR("Relocation beyond target object bounds: " | |
3339 | "obj %p target %d delta %d size %d.\n", | |
3340 | obj, reloc->target_handle, | |
3341 | (int) reloc->delta, (int) target_obj->size); | |
3342 | drm_gem_object_unreference(target_obj); | |
3343 | i915_gem_object_unpin(obj); | |
3344 | return -EINVAL; | |
3345 | } | |
3346 | ||
2ef7eeaa EA |
3347 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3348 | if (ret != 0) { | |
3349 | drm_gem_object_unreference(target_obj); | |
3350 | i915_gem_object_unpin(obj); | |
3351 | return -EINVAL; | |
673a394b EA |
3352 | } |
3353 | ||
3354 | /* Map the page containing the relocation we're going to | |
3355 | * perform. | |
3356 | */ | |
40a5f0de | 3357 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3358 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3359 | (reloc_offset & | |
fca3ec01 CW |
3360 | ~(PAGE_SIZE - 1)), |
3361 | KM_USER0); | |
3043c60c | 3362 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3363 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3364 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b EA |
3365 | |
3366 | #if WATCH_BUF | |
3367 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", | |
40a5f0de | 3368 | obj, (unsigned int) reloc->offset, |
673a394b EA |
3369 | readl(reloc_entry), reloc_val); |
3370 | #endif | |
3371 | writel(reloc_val, reloc_entry); | |
fca3ec01 | 3372 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
673a394b | 3373 | |
40a5f0de EA |
3374 | /* The updated presumed offset for this entry will be |
3375 | * copied back out to the user. | |
673a394b | 3376 | */ |
40a5f0de | 3377 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3378 | |
3379 | drm_gem_object_unreference(target_obj); | |
3380 | } | |
3381 | ||
673a394b EA |
3382 | #if WATCH_BUF |
3383 | if (0) | |
3384 | i915_gem_dump_object(obj, 128, __func__, ~0); | |
3385 | #endif | |
3386 | return 0; | |
3387 | } | |
3388 | ||
673a394b EA |
3389 | /* Throttle our rendering by waiting until the ring has completed our requests |
3390 | * emitted over 20 msec ago. | |
3391 | * | |
b962442e EA |
3392 | * Note that if we were to use the current jiffies each time around the loop, |
3393 | * we wouldn't escape the function with any frames outstanding if the time to | |
3394 | * render a frame was over 20ms. | |
3395 | * | |
673a394b EA |
3396 | * This should get us reasonable parallelism between CPU and GPU but also |
3397 | * relatively low latency when blocking on a particular request to finish. | |
3398 | */ | |
3399 | static int | |
3400 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) | |
3401 | { | |
3402 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
3403 | int ret = 0; | |
b962442e | 3404 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
673a394b EA |
3405 | |
3406 | mutex_lock(&dev->struct_mutex); | |
b962442e EA |
3407 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
3408 | struct drm_i915_gem_request *request; | |
3409 | ||
3410 | request = list_first_entry(&i915_file_priv->mm.request_list, | |
3411 | struct drm_i915_gem_request, | |
3412 | client_list); | |
3413 | ||
3414 | if (time_after_eq(request->emitted_jiffies, recent_enough)) | |
3415 | break; | |
3416 | ||
852835f3 | 3417 | ret = i915_wait_request(dev, request->seqno, request->ring); |
b962442e EA |
3418 | if (ret != 0) |
3419 | break; | |
3420 | } | |
673a394b | 3421 | mutex_unlock(&dev->struct_mutex); |
b962442e | 3422 | |
673a394b EA |
3423 | return ret; |
3424 | } | |
3425 | ||
40a5f0de | 3426 | static int |
76446cac | 3427 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3428 | uint32_t buffer_count, |
3429 | struct drm_i915_gem_relocation_entry **relocs) | |
3430 | { | |
3431 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3432 | int ret; | |
3433 | ||
3434 | *relocs = NULL; | |
3435 | for (i = 0; i < buffer_count; i++) { | |
3436 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3437 | return -EINVAL; | |
3438 | reloc_count += exec_list[i].relocation_count; | |
3439 | } | |
3440 | ||
8e7d2b2c | 3441 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
76446cac JB |
3442 | if (*relocs == NULL) { |
3443 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); | |
40a5f0de | 3444 | return -ENOMEM; |
76446cac | 3445 | } |
40a5f0de EA |
3446 | |
3447 | for (i = 0; i < buffer_count; i++) { | |
3448 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3449 | ||
3450 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3451 | ||
3452 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3453 | user_relocs, | |
3454 | exec_list[i].relocation_count * | |
3455 | sizeof(**relocs)); | |
3456 | if (ret != 0) { | |
8e7d2b2c | 3457 | drm_free_large(*relocs); |
40a5f0de | 3458 | *relocs = NULL; |
2bc43b5c | 3459 | return -EFAULT; |
40a5f0de EA |
3460 | } |
3461 | ||
3462 | reloc_index += exec_list[i].relocation_count; | |
3463 | } | |
3464 | ||
2bc43b5c | 3465 | return 0; |
40a5f0de EA |
3466 | } |
3467 | ||
3468 | static int | |
76446cac | 3469 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3470 | uint32_t buffer_count, |
3471 | struct drm_i915_gem_relocation_entry *relocs) | |
3472 | { | |
3473 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3474 | int ret = 0; |
40a5f0de | 3475 | |
93533c29 CW |
3476 | if (relocs == NULL) |
3477 | return 0; | |
3478 | ||
40a5f0de EA |
3479 | for (i = 0; i < buffer_count; i++) { |
3480 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3481 | int unwritten; |
40a5f0de EA |
3482 | |
3483 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3484 | ||
2bc43b5c FM |
3485 | unwritten = copy_to_user(user_relocs, |
3486 | &relocs[reloc_count], | |
3487 | exec_list[i].relocation_count * | |
3488 | sizeof(*relocs)); | |
3489 | ||
3490 | if (unwritten) { | |
3491 | ret = -EFAULT; | |
3492 | goto err; | |
40a5f0de EA |
3493 | } |
3494 | ||
3495 | reloc_count += exec_list[i].relocation_count; | |
3496 | } | |
3497 | ||
2bc43b5c | 3498 | err: |
8e7d2b2c | 3499 | drm_free_large(relocs); |
40a5f0de EA |
3500 | |
3501 | return ret; | |
3502 | } | |
3503 | ||
83d60795 | 3504 | static int |
76446cac | 3505 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
83d60795 CW |
3506 | uint64_t exec_offset) |
3507 | { | |
3508 | uint32_t exec_start, exec_len; | |
3509 | ||
3510 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3511 | exec_len = (uint32_t) exec->batch_len; | |
3512 | ||
3513 | if ((exec_start | exec_len) & 0x7) | |
3514 | return -EINVAL; | |
3515 | ||
3516 | if (!exec_start) | |
3517 | return -EINVAL; | |
3518 | ||
3519 | return 0; | |
3520 | } | |
3521 | ||
6b95a207 KH |
3522 | static int |
3523 | i915_gem_wait_for_pending_flip(struct drm_device *dev, | |
3524 | struct drm_gem_object **object_list, | |
3525 | int count) | |
3526 | { | |
3527 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3528 | struct drm_i915_gem_object *obj_priv; | |
3529 | DEFINE_WAIT(wait); | |
3530 | int i, ret = 0; | |
3531 | ||
3532 | for (;;) { | |
3533 | prepare_to_wait(&dev_priv->pending_flip_queue, | |
3534 | &wait, TASK_INTERRUPTIBLE); | |
3535 | for (i = 0; i < count; i++) { | |
23010e43 | 3536 | obj_priv = to_intel_bo(object_list[i]); |
6b95a207 KH |
3537 | if (atomic_read(&obj_priv->pending_flip) > 0) |
3538 | break; | |
3539 | } | |
3540 | if (i == count) | |
3541 | break; | |
3542 | ||
3543 | if (!signal_pending(current)) { | |
3544 | mutex_unlock(&dev->struct_mutex); | |
3545 | schedule(); | |
3546 | mutex_lock(&dev->struct_mutex); | |
3547 | continue; | |
3548 | } | |
3549 | ret = -ERESTARTSYS; | |
3550 | break; | |
3551 | } | |
3552 | finish_wait(&dev_priv->pending_flip_queue, &wait); | |
3553 | ||
3554 | return ret; | |
3555 | } | |
3556 | ||
43b27f40 | 3557 | |
673a394b | 3558 | int |
76446cac JB |
3559 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
3560 | struct drm_file *file_priv, | |
3561 | struct drm_i915_gem_execbuffer2 *args, | |
3562 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3563 | { |
3564 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3565 | struct drm_gem_object **object_list = NULL; |
3566 | struct drm_gem_object *batch_obj; | |
b70d11da | 3567 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3568 | struct drm_clip_rect *cliprects = NULL; |
93533c29 | 3569 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
76446cac | 3570 | int ret = 0, ret2, i, pinned = 0; |
673a394b | 3571 | uint64_t exec_offset; |
40a5f0de | 3572 | uint32_t seqno, flush_domains, reloc_index; |
6b95a207 | 3573 | int pin_tries, flips; |
673a394b | 3574 | |
852835f3 ZN |
3575 | struct intel_ring_buffer *ring = NULL; |
3576 | ||
673a394b EA |
3577 | #if WATCH_EXEC |
3578 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3579 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3580 | #endif | |
d1b851fc ZN |
3581 | if (args->flags & I915_EXEC_BSD) { |
3582 | if (!HAS_BSD(dev)) { | |
3583 | DRM_ERROR("execbuf with wrong flag\n"); | |
3584 | return -EINVAL; | |
3585 | } | |
3586 | ring = &dev_priv->bsd_ring; | |
3587 | } else { | |
3588 | ring = &dev_priv->render_ring; | |
3589 | } | |
3590 | ||
4f481ed2 EA |
3591 | if (args->buffer_count < 1) { |
3592 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3593 | return -EINVAL; | |
3594 | } | |
c8e0f93a | 3595 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3596 | if (object_list == NULL) { |
3597 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3598 | args->buffer_count); |
3599 | ret = -ENOMEM; | |
3600 | goto pre_mutex_err; | |
3601 | } | |
673a394b | 3602 | |
201361a5 | 3603 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3604 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3605 | GFP_KERNEL); | |
a40e8d31 OA |
3606 | if (cliprects == NULL) { |
3607 | ret = -ENOMEM; | |
201361a5 | 3608 | goto pre_mutex_err; |
a40e8d31 | 3609 | } |
201361a5 EA |
3610 | |
3611 | ret = copy_from_user(cliprects, | |
3612 | (struct drm_clip_rect __user *) | |
3613 | (uintptr_t) args->cliprects_ptr, | |
3614 | sizeof(*cliprects) * args->num_cliprects); | |
3615 | if (ret != 0) { | |
3616 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3617 | args->num_cliprects, ret); | |
c877cdce | 3618 | ret = -EFAULT; |
201361a5 EA |
3619 | goto pre_mutex_err; |
3620 | } | |
3621 | } | |
3622 | ||
40a5f0de EA |
3623 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3624 | &relocs); | |
3625 | if (ret != 0) | |
3626 | goto pre_mutex_err; | |
3627 | ||
673a394b EA |
3628 | mutex_lock(&dev->struct_mutex); |
3629 | ||
3630 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3631 | ||
ba1234d1 | 3632 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3633 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3634 | ret = -EIO; |
3635 | goto pre_mutex_err; | |
673a394b EA |
3636 | } |
3637 | ||
3638 | if (dev_priv->mm.suspended) { | |
673a394b | 3639 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3640 | ret = -EBUSY; |
3641 | goto pre_mutex_err; | |
673a394b EA |
3642 | } |
3643 | ||
ac94a962 | 3644 | /* Look up object handles */ |
6b95a207 | 3645 | flips = 0; |
673a394b EA |
3646 | for (i = 0; i < args->buffer_count; i++) { |
3647 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3648 | exec_list[i].handle); | |
3649 | if (object_list[i] == NULL) { | |
3650 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3651 | exec_list[i].handle, i); | |
0ce907f8 CW |
3652 | /* prevent error path from reading uninitialized data */ |
3653 | args->buffer_count = i + 1; | |
bf79cb91 | 3654 | ret = -ENOENT; |
673a394b EA |
3655 | goto err; |
3656 | } | |
b70d11da | 3657 | |
23010e43 | 3658 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3659 | if (obj_priv->in_execbuffer) { |
3660 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3661 | object_list[i]); | |
0ce907f8 CW |
3662 | /* prevent error path from reading uninitialized data */ |
3663 | args->buffer_count = i + 1; | |
bf79cb91 | 3664 | ret = -EINVAL; |
b70d11da KH |
3665 | goto err; |
3666 | } | |
3667 | obj_priv->in_execbuffer = true; | |
6b95a207 KH |
3668 | flips += atomic_read(&obj_priv->pending_flip); |
3669 | } | |
3670 | ||
3671 | if (flips > 0) { | |
3672 | ret = i915_gem_wait_for_pending_flip(dev, object_list, | |
3673 | args->buffer_count); | |
3674 | if (ret) | |
3675 | goto err; | |
ac94a962 | 3676 | } |
673a394b | 3677 | |
ac94a962 KP |
3678 | /* Pin and relocate */ |
3679 | for (pin_tries = 0; ; pin_tries++) { | |
3680 | ret = 0; | |
40a5f0de EA |
3681 | reloc_index = 0; |
3682 | ||
ac94a962 KP |
3683 | for (i = 0; i < args->buffer_count; i++) { |
3684 | object_list[i]->pending_read_domains = 0; | |
3685 | object_list[i]->pending_write_domain = 0; | |
3686 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3687 | file_priv, | |
40a5f0de EA |
3688 | &exec_list[i], |
3689 | &relocs[reloc_index]); | |
ac94a962 KP |
3690 | if (ret) |
3691 | break; | |
3692 | pinned = i + 1; | |
40a5f0de | 3693 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3694 | } |
3695 | /* success */ | |
3696 | if (ret == 0) | |
3697 | break; | |
3698 | ||
3699 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3700 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3701 | if (ret != -ERESTARTSYS) { |
3702 | unsigned long long total_size = 0; | |
3d1cc470 CW |
3703 | int num_fences = 0; |
3704 | for (i = 0; i < args->buffer_count; i++) { | |
43b27f40 | 3705 | obj_priv = to_intel_bo(object_list[i]); |
3d1cc470 | 3706 | |
07f73f69 | 3707 | total_size += object_list[i]->size; |
3d1cc470 CW |
3708 | num_fences += |
3709 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && | |
3710 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3711 | } | |
3712 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", | |
07f73f69 | 3713 | pinned+1, args->buffer_count, |
3d1cc470 CW |
3714 | total_size, num_fences, |
3715 | ret); | |
07f73f69 CW |
3716 | DRM_ERROR("%d objects [%d pinned], " |
3717 | "%d object bytes [%d pinned], " | |
3718 | "%d/%d gtt bytes\n", | |
3719 | atomic_read(&dev->object_count), | |
3720 | atomic_read(&dev->pin_count), | |
3721 | atomic_read(&dev->object_memory), | |
3722 | atomic_read(&dev->pin_memory), | |
3723 | atomic_read(&dev->gtt_memory), | |
3724 | dev->gtt_total); | |
3725 | } | |
673a394b EA |
3726 | goto err; |
3727 | } | |
ac94a962 KP |
3728 | |
3729 | /* unpin all of our buffers */ | |
3730 | for (i = 0; i < pinned; i++) | |
3731 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3732 | pinned = 0; |
ac94a962 KP |
3733 | |
3734 | /* evict everyone we can from the aperture */ | |
3735 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3736 | if (ret && ret != -ENOSPC) |
ac94a962 | 3737 | goto err; |
673a394b EA |
3738 | } |
3739 | ||
3740 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3741 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3742 | if (batch_obj->pending_write_domain) { |
3743 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3744 | ret = -EINVAL; | |
3745 | goto err; | |
3746 | } | |
3747 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3748 | |
83d60795 CW |
3749 | /* Sanity check the batch buffer, prior to moving objects */ |
3750 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3751 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3752 | if (ret != 0) { | |
3753 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3754 | goto err; | |
3755 | } | |
3756 | ||
673a394b EA |
3757 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3758 | ||
646f0f6e KP |
3759 | /* Zero the global flush/invalidate flags. These |
3760 | * will be modified as new domains are computed | |
3761 | * for each object | |
3762 | */ | |
3763 | dev->invalidate_domains = 0; | |
3764 | dev->flush_domains = 0; | |
88f356b7 | 3765 | dev_priv->flush_rings = 0; |
646f0f6e | 3766 | |
673a394b EA |
3767 | for (i = 0; i < args->buffer_count; i++) { |
3768 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3769 | |
646f0f6e | 3770 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3771 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3772 | } |
3773 | ||
3774 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3775 | ||
646f0f6e KP |
3776 | if (dev->invalidate_domains | dev->flush_domains) { |
3777 | #if WATCH_EXEC | |
3778 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3779 | __func__, | |
3780 | dev->invalidate_domains, | |
3781 | dev->flush_domains); | |
3782 | #endif | |
3783 | i915_gem_flush(dev, | |
3784 | dev->invalidate_domains, | |
3785 | dev->flush_domains); | |
88f356b7 | 3786 | if (dev_priv->flush_rings & FLUSH_RENDER_RING) |
8bff917c | 3787 | (void)i915_add_request(dev, file_priv, 0, |
88f356b7 CW |
3788 | &dev_priv->render_ring); |
3789 | if (dev_priv->flush_rings & FLUSH_BSD_RING) | |
8bff917c | 3790 | (void)i915_add_request(dev, file_priv, 0, |
88f356b7 | 3791 | &dev_priv->bsd_ring); |
646f0f6e | 3792 | } |
673a394b | 3793 | |
efbeed96 EA |
3794 | for (i = 0; i < args->buffer_count; i++) { |
3795 | struct drm_gem_object *obj = object_list[i]; | |
23010e43 | 3796 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3797 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3798 | |
3799 | obj->write_domain = obj->pending_write_domain; | |
99fcb766 DV |
3800 | if (obj->write_domain) |
3801 | list_move_tail(&obj_priv->gpu_write_list, | |
3802 | &dev_priv->mm.gpu_write_list); | |
3803 | else | |
3804 | list_del_init(&obj_priv->gpu_write_list); | |
3805 | ||
1c5d22f7 CW |
3806 | trace_i915_gem_object_change_domain(obj, |
3807 | obj->read_domains, | |
3808 | old_write_domain); | |
efbeed96 EA |
3809 | } |
3810 | ||
673a394b EA |
3811 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3812 | ||
3813 | #if WATCH_COHERENCY | |
3814 | for (i = 0; i < args->buffer_count; i++) { | |
3815 | i915_gem_object_check_coherency(object_list[i], | |
3816 | exec_list[i].handle); | |
3817 | } | |
3818 | #endif | |
3819 | ||
673a394b | 3820 | #if WATCH_EXEC |
6911a9b8 | 3821 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3822 | args->batch_len, |
3823 | __func__, | |
3824 | ~0); | |
3825 | #endif | |
3826 | ||
673a394b | 3827 | /* Exec the batchbuffer */ |
852835f3 ZN |
3828 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
3829 | cliprects, exec_offset); | |
673a394b EA |
3830 | if (ret) { |
3831 | DRM_ERROR("dispatch failed %d\n", ret); | |
3832 | goto err; | |
3833 | } | |
3834 | ||
3835 | /* | |
3836 | * Ensure that the commands in the batch buffer are | |
3837 | * finished before the interrupt fires | |
3838 | */ | |
852835f3 | 3839 | flush_domains = i915_retire_commands(dev, ring); |
673a394b EA |
3840 | |
3841 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3842 | ||
3843 | /* | |
3844 | * Get a seqno representing the execution of the current buffer, | |
3845 | * which we can wait on. We would like to mitigate these interrupts, | |
3846 | * likely by only creating seqnos occasionally (so that we have | |
3847 | * *some* interrupts representing completion of buffers that we can | |
3848 | * wait on when trying to clear up gtt space). | |
3849 | */ | |
852835f3 | 3850 | seqno = i915_add_request(dev, file_priv, flush_domains, ring); |
673a394b | 3851 | BUG_ON(seqno == 0); |
673a394b EA |
3852 | for (i = 0; i < args->buffer_count; i++) { |
3853 | struct drm_gem_object *obj = object_list[i]; | |
852835f3 | 3854 | obj_priv = to_intel_bo(obj); |
673a394b | 3855 | |
852835f3 | 3856 | i915_gem_object_move_to_active(obj, seqno, ring); |
673a394b EA |
3857 | #if WATCH_LRU |
3858 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); | |
3859 | #endif | |
3860 | } | |
3861 | #if WATCH_LRU | |
3862 | i915_dump_lru(dev, __func__); | |
3863 | #endif | |
3864 | ||
3865 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3866 | ||
673a394b | 3867 | err: |
aad87dff JL |
3868 | for (i = 0; i < pinned; i++) |
3869 | i915_gem_object_unpin(object_list[i]); | |
3870 | ||
b70d11da KH |
3871 | for (i = 0; i < args->buffer_count; i++) { |
3872 | if (object_list[i]) { | |
23010e43 | 3873 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3874 | obj_priv->in_execbuffer = false; |
3875 | } | |
aad87dff | 3876 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3877 | } |
673a394b | 3878 | |
673a394b EA |
3879 | mutex_unlock(&dev->struct_mutex); |
3880 | ||
93533c29 | 3881 | pre_mutex_err: |
40a5f0de EA |
3882 | /* Copy the updated relocations out regardless of current error |
3883 | * state. Failure to update the relocs would mean that the next | |
3884 | * time userland calls execbuf, it would do so with presumed offset | |
3885 | * state that didn't match the actual object state. | |
3886 | */ | |
3887 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3888 | relocs); | |
3889 | if (ret2 != 0) { | |
3890 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3891 | ||
3892 | if (ret == 0) | |
3893 | ret = ret2; | |
3894 | } | |
3895 | ||
8e7d2b2c | 3896 | drm_free_large(object_list); |
9a298b2a | 3897 | kfree(cliprects); |
673a394b EA |
3898 | |
3899 | return ret; | |
3900 | } | |
3901 | ||
76446cac JB |
3902 | /* |
3903 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3904 | * list array and passes it to the real function. | |
3905 | */ | |
3906 | int | |
3907 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3908 | struct drm_file *file_priv) | |
3909 | { | |
3910 | struct drm_i915_gem_execbuffer *args = data; | |
3911 | struct drm_i915_gem_execbuffer2 exec2; | |
3912 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3913 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3914 | int ret, i; | |
3915 | ||
3916 | #if WATCH_EXEC | |
3917 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3918 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3919 | #endif | |
3920 | ||
3921 | if (args->buffer_count < 1) { | |
3922 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3923 | return -EINVAL; | |
3924 | } | |
3925 | ||
3926 | /* Copy in the exec list from userland */ | |
3927 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3928 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3929 | if (exec_list == NULL || exec2_list == NULL) { | |
3930 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3931 | args->buffer_count); | |
3932 | drm_free_large(exec_list); | |
3933 | drm_free_large(exec2_list); | |
3934 | return -ENOMEM; | |
3935 | } | |
3936 | ret = copy_from_user(exec_list, | |
3937 | (struct drm_i915_relocation_entry __user *) | |
3938 | (uintptr_t) args->buffers_ptr, | |
3939 | sizeof(*exec_list) * args->buffer_count); | |
3940 | if (ret != 0) { | |
3941 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3942 | args->buffer_count, ret); | |
3943 | drm_free_large(exec_list); | |
3944 | drm_free_large(exec2_list); | |
3945 | return -EFAULT; | |
3946 | } | |
3947 | ||
3948 | for (i = 0; i < args->buffer_count; i++) { | |
3949 | exec2_list[i].handle = exec_list[i].handle; | |
3950 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3951 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3952 | exec2_list[i].alignment = exec_list[i].alignment; | |
3953 | exec2_list[i].offset = exec_list[i].offset; | |
3954 | if (!IS_I965G(dev)) | |
3955 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
3956 | else | |
3957 | exec2_list[i].flags = 0; | |
3958 | } | |
3959 | ||
3960 | exec2.buffers_ptr = args->buffers_ptr; | |
3961 | exec2.buffer_count = args->buffer_count; | |
3962 | exec2.batch_start_offset = args->batch_start_offset; | |
3963 | exec2.batch_len = args->batch_len; | |
3964 | exec2.DR1 = args->DR1; | |
3965 | exec2.DR4 = args->DR4; | |
3966 | exec2.num_cliprects = args->num_cliprects; | |
3967 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 3968 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
3969 | |
3970 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
3971 | if (!ret) { | |
3972 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3973 | for (i = 0; i < args->buffer_count; i++) | |
3974 | exec_list[i].offset = exec2_list[i].offset; | |
3975 | /* ... and back out to userspace */ | |
3976 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3977 | (uintptr_t) args->buffers_ptr, | |
3978 | exec_list, | |
3979 | sizeof(*exec_list) * args->buffer_count); | |
3980 | if (ret) { | |
3981 | ret = -EFAULT; | |
3982 | DRM_ERROR("failed to copy %d exec entries " | |
3983 | "back to user (%d)\n", | |
3984 | args->buffer_count, ret); | |
3985 | } | |
76446cac JB |
3986 | } |
3987 | ||
3988 | drm_free_large(exec_list); | |
3989 | drm_free_large(exec2_list); | |
3990 | return ret; | |
3991 | } | |
3992 | ||
3993 | int | |
3994 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
3995 | struct drm_file *file_priv) | |
3996 | { | |
3997 | struct drm_i915_gem_execbuffer2 *args = data; | |
3998 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3999 | int ret; | |
4000 | ||
4001 | #if WATCH_EXEC | |
4002 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4003 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4004 | #endif | |
4005 | ||
4006 | if (args->buffer_count < 1) { | |
4007 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4008 | return -EINVAL; | |
4009 | } | |
4010 | ||
4011 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4012 | if (exec2_list == NULL) { | |
4013 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4014 | args->buffer_count); | |
4015 | return -ENOMEM; | |
4016 | } | |
4017 | ret = copy_from_user(exec2_list, | |
4018 | (struct drm_i915_relocation_entry __user *) | |
4019 | (uintptr_t) args->buffers_ptr, | |
4020 | sizeof(*exec2_list) * args->buffer_count); | |
4021 | if (ret != 0) { | |
4022 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4023 | args->buffer_count, ret); | |
4024 | drm_free_large(exec2_list); | |
4025 | return -EFAULT; | |
4026 | } | |
4027 | ||
4028 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4029 | if (!ret) { | |
4030 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4031 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4032 | (uintptr_t) args->buffers_ptr, | |
4033 | exec2_list, | |
4034 | sizeof(*exec2_list) * args->buffer_count); | |
4035 | if (ret) { | |
4036 | ret = -EFAULT; | |
4037 | DRM_ERROR("failed to copy %d exec entries " | |
4038 | "back to user (%d)\n", | |
4039 | args->buffer_count, ret); | |
4040 | } | |
4041 | } | |
4042 | ||
4043 | drm_free_large(exec2_list); | |
4044 | return ret; | |
4045 | } | |
4046 | ||
673a394b EA |
4047 | int |
4048 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
4049 | { | |
4050 | struct drm_device *dev = obj->dev; | |
23010e43 | 4051 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4052 | int ret; |
4053 | ||
778c3544 DV |
4054 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
4055 | ||
673a394b | 4056 | i915_verify_inactive(dev, __FILE__, __LINE__); |
ac0c6b5a CW |
4057 | |
4058 | if (obj_priv->gtt_space != NULL) { | |
4059 | if (alignment == 0) | |
4060 | alignment = i915_gem_get_gtt_alignment(obj); | |
4061 | if (obj_priv->gtt_offset & (alignment - 1)) { | |
ae7d49d8 CW |
4062 | WARN(obj_priv->pin_count, |
4063 | "bo is already pinned with incorrect alignment:" | |
4064 | " offset=%x, req.alignment=%x\n", | |
4065 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4066 | ret = i915_gem_object_unbind(obj); |
4067 | if (ret) | |
4068 | return ret; | |
4069 | } | |
4070 | } | |
4071 | ||
673a394b EA |
4072 | if (obj_priv->gtt_space == NULL) { |
4073 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 4074 | if (ret) |
673a394b | 4075 | return ret; |
22c344e9 | 4076 | } |
76446cac | 4077 | |
673a394b EA |
4078 | obj_priv->pin_count++; |
4079 | ||
4080 | /* If the object is not active and not pending a flush, | |
4081 | * remove it from the inactive list | |
4082 | */ | |
4083 | if (obj_priv->pin_count == 1) { | |
4084 | atomic_inc(&dev->pin_count); | |
4085 | atomic_add(obj->size, &dev->pin_memory); | |
4086 | if (!obj_priv->active && | |
bf1a1092 | 4087 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
673a394b EA |
4088 | list_del_init(&obj_priv->list); |
4089 | } | |
4090 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4091 | ||
4092 | return 0; | |
4093 | } | |
4094 | ||
4095 | void | |
4096 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4097 | { | |
4098 | struct drm_device *dev = obj->dev; | |
4099 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4100 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4101 | |
4102 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4103 | obj_priv->pin_count--; | |
4104 | BUG_ON(obj_priv->pin_count < 0); | |
4105 | BUG_ON(obj_priv->gtt_space == NULL); | |
4106 | ||
4107 | /* If the object is no longer pinned, and is | |
4108 | * neither active nor being flushed, then stick it on | |
4109 | * the inactive list | |
4110 | */ | |
4111 | if (obj_priv->pin_count == 0) { | |
4112 | if (!obj_priv->active && | |
21d509e3 | 4113 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
673a394b EA |
4114 | list_move_tail(&obj_priv->list, |
4115 | &dev_priv->mm.inactive_list); | |
4116 | atomic_dec(&dev->pin_count); | |
4117 | atomic_sub(obj->size, &dev->pin_memory); | |
4118 | } | |
4119 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4120 | } | |
4121 | ||
4122 | int | |
4123 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4124 | struct drm_file *file_priv) | |
4125 | { | |
4126 | struct drm_i915_gem_pin *args = data; | |
4127 | struct drm_gem_object *obj; | |
4128 | struct drm_i915_gem_object *obj_priv; | |
4129 | int ret; | |
4130 | ||
4131 | mutex_lock(&dev->struct_mutex); | |
4132 | ||
4133 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4134 | if (obj == NULL) { | |
4135 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
4136 | args->handle); | |
4137 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 4138 | return -ENOENT; |
673a394b | 4139 | } |
23010e43 | 4140 | obj_priv = to_intel_bo(obj); |
673a394b | 4141 | |
bb6baf76 CW |
4142 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4143 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
4144 | drm_gem_object_unreference(obj); |
4145 | mutex_unlock(&dev->struct_mutex); | |
4146 | return -EINVAL; | |
4147 | } | |
4148 | ||
79e53945 JB |
4149 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4150 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4151 | args->handle); | |
96dec61d | 4152 | drm_gem_object_unreference(obj); |
673a394b | 4153 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
4154 | return -EINVAL; |
4155 | } | |
4156 | ||
4157 | obj_priv->user_pin_count++; | |
4158 | obj_priv->pin_filp = file_priv; | |
4159 | if (obj_priv->user_pin_count == 1) { | |
4160 | ret = i915_gem_object_pin(obj, args->alignment); | |
4161 | if (ret != 0) { | |
4162 | drm_gem_object_unreference(obj); | |
4163 | mutex_unlock(&dev->struct_mutex); | |
4164 | return ret; | |
4165 | } | |
673a394b EA |
4166 | } |
4167 | ||
4168 | /* XXX - flush the CPU caches for pinned objects | |
4169 | * as the X server doesn't manage domains yet | |
4170 | */ | |
e47c68e9 | 4171 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
4172 | args->offset = obj_priv->gtt_offset; |
4173 | drm_gem_object_unreference(obj); | |
4174 | mutex_unlock(&dev->struct_mutex); | |
4175 | ||
4176 | return 0; | |
4177 | } | |
4178 | ||
4179 | int | |
4180 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4181 | struct drm_file *file_priv) | |
4182 | { | |
4183 | struct drm_i915_gem_pin *args = data; | |
4184 | struct drm_gem_object *obj; | |
79e53945 | 4185 | struct drm_i915_gem_object *obj_priv; |
673a394b EA |
4186 | |
4187 | mutex_lock(&dev->struct_mutex); | |
4188 | ||
4189 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4190 | if (obj == NULL) { | |
4191 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
4192 | args->handle); | |
4193 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 4194 | return -ENOENT; |
673a394b EA |
4195 | } |
4196 | ||
23010e43 | 4197 | obj_priv = to_intel_bo(obj); |
79e53945 JB |
4198 | if (obj_priv->pin_filp != file_priv) { |
4199 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4200 | args->handle); | |
4201 | drm_gem_object_unreference(obj); | |
4202 | mutex_unlock(&dev->struct_mutex); | |
4203 | return -EINVAL; | |
4204 | } | |
4205 | obj_priv->user_pin_count--; | |
4206 | if (obj_priv->user_pin_count == 0) { | |
4207 | obj_priv->pin_filp = NULL; | |
4208 | i915_gem_object_unpin(obj); | |
4209 | } | |
673a394b EA |
4210 | |
4211 | drm_gem_object_unreference(obj); | |
4212 | mutex_unlock(&dev->struct_mutex); | |
4213 | return 0; | |
4214 | } | |
4215 | ||
4216 | int | |
4217 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4218 | struct drm_file *file_priv) | |
4219 | { | |
4220 | struct drm_i915_gem_busy *args = data; | |
4221 | struct drm_gem_object *obj; | |
4222 | struct drm_i915_gem_object *obj_priv; | |
4223 | ||
673a394b EA |
4224 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4225 | if (obj == NULL) { | |
4226 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4227 | args->handle); | |
bf79cb91 | 4228 | return -ENOENT; |
673a394b EA |
4229 | } |
4230 | ||
b1ce786c | 4231 | mutex_lock(&dev->struct_mutex); |
d1b851fc | 4232 | |
0be555b6 CW |
4233 | /* Count all active objects as busy, even if they are currently not used |
4234 | * by the gpu. Users of this interface expect objects to eventually | |
4235 | * become non-busy without any further actions, therefore emit any | |
4236 | * necessary flushes here. | |
c4de0a5d | 4237 | */ |
0be555b6 CW |
4238 | obj_priv = to_intel_bo(obj); |
4239 | args->busy = obj_priv->active; | |
4240 | if (args->busy) { | |
4241 | /* Unconditionally flush objects, even when the gpu still uses this | |
4242 | * object. Userspace calling this function indicates that it wants to | |
4243 | * use this buffer rather sooner than later, so issuing the required | |
4244 | * flush earlier is beneficial. | |
4245 | */ | |
4246 | if (obj->write_domain) { | |
4247 | i915_gem_flush(dev, 0, obj->write_domain); | |
4248 | (void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring); | |
4249 | } | |
4250 | ||
4251 | /* Update the active list for the hardware's current position. | |
4252 | * Otherwise this only updates on a delayed timer or when irqs | |
4253 | * are actually unmasked, and our working set ends up being | |
4254 | * larger than required. | |
4255 | */ | |
4256 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4257 | ||
4258 | args->busy = obj_priv->active; | |
4259 | } | |
673a394b EA |
4260 | |
4261 | drm_gem_object_unreference(obj); | |
4262 | mutex_unlock(&dev->struct_mutex); | |
4263 | return 0; | |
4264 | } | |
4265 | ||
4266 | int | |
4267 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4268 | struct drm_file *file_priv) | |
4269 | { | |
4270 | return i915_gem_ring_throttle(dev, file_priv); | |
4271 | } | |
4272 | ||
3ef94daa CW |
4273 | int |
4274 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4275 | struct drm_file *file_priv) | |
4276 | { | |
4277 | struct drm_i915_gem_madvise *args = data; | |
4278 | struct drm_gem_object *obj; | |
4279 | struct drm_i915_gem_object *obj_priv; | |
4280 | ||
4281 | switch (args->madv) { | |
4282 | case I915_MADV_DONTNEED: | |
4283 | case I915_MADV_WILLNEED: | |
4284 | break; | |
4285 | default: | |
4286 | return -EINVAL; | |
4287 | } | |
4288 | ||
4289 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4290 | if (obj == NULL) { | |
4291 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4292 | args->handle); | |
bf79cb91 | 4293 | return -ENOENT; |
3ef94daa CW |
4294 | } |
4295 | ||
4296 | mutex_lock(&dev->struct_mutex); | |
23010e43 | 4297 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4298 | |
4299 | if (obj_priv->pin_count) { | |
4300 | drm_gem_object_unreference(obj); | |
4301 | mutex_unlock(&dev->struct_mutex); | |
4302 | ||
4303 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4304 | return -EINVAL; | |
4305 | } | |
4306 | ||
bb6baf76 CW |
4307 | if (obj_priv->madv != __I915_MADV_PURGED) |
4308 | obj_priv->madv = args->madv; | |
3ef94daa | 4309 | |
2d7ef395 CW |
4310 | /* if the object is no longer bound, discard its backing storage */ |
4311 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4312 | obj_priv->gtt_space == NULL) | |
4313 | i915_gem_object_truncate(obj); | |
4314 | ||
bb6baf76 CW |
4315 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4316 | ||
3ef94daa CW |
4317 | drm_gem_object_unreference(obj); |
4318 | mutex_unlock(&dev->struct_mutex); | |
4319 | ||
4320 | return 0; | |
4321 | } | |
4322 | ||
ac52bc56 DV |
4323 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4324 | size_t size) | |
4325 | { | |
c397b908 | 4326 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4327 | |
c397b908 DV |
4328 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4329 | if (obj == NULL) | |
4330 | return NULL; | |
673a394b | 4331 | |
c397b908 DV |
4332 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4333 | kfree(obj); | |
4334 | return NULL; | |
4335 | } | |
673a394b | 4336 | |
c397b908 DV |
4337 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4338 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4339 | |
c397b908 | 4340 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4341 | obj->base.driver_private = NULL; |
c397b908 DV |
4342 | obj->fence_reg = I915_FENCE_REG_NONE; |
4343 | INIT_LIST_HEAD(&obj->list); | |
4344 | INIT_LIST_HEAD(&obj->gpu_write_list); | |
c397b908 | 4345 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4346 | |
c397b908 DV |
4347 | trace_i915_gem_object_create(&obj->base); |
4348 | ||
4349 | return &obj->base; | |
4350 | } | |
4351 | ||
4352 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4353 | { | |
4354 | BUG(); | |
de151cf6 | 4355 | |
673a394b EA |
4356 | return 0; |
4357 | } | |
4358 | ||
be72615b | 4359 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4360 | { |
de151cf6 | 4361 | struct drm_device *dev = obj->dev; |
be72615b | 4362 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4363 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4364 | int ret; |
673a394b | 4365 | |
be72615b CW |
4366 | ret = i915_gem_object_unbind(obj); |
4367 | if (ret == -ERESTARTSYS) { | |
4368 | list_move(&obj_priv->list, | |
4369 | &dev_priv->mm.deferred_free_list); | |
4370 | return; | |
4371 | } | |
673a394b | 4372 | |
7e616158 CW |
4373 | if (obj_priv->mmap_offset) |
4374 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4375 | |
c397b908 DV |
4376 | drm_gem_object_release(obj); |
4377 | ||
9a298b2a | 4378 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4379 | kfree(obj_priv->bit_17); |
c397b908 | 4380 | kfree(obj_priv); |
673a394b EA |
4381 | } |
4382 | ||
be72615b CW |
4383 | void i915_gem_free_object(struct drm_gem_object *obj) |
4384 | { | |
4385 | struct drm_device *dev = obj->dev; | |
4386 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4387 | ||
4388 | trace_i915_gem_object_destroy(obj); | |
4389 | ||
4390 | while (obj_priv->pin_count > 0) | |
4391 | i915_gem_object_unpin(obj); | |
4392 | ||
4393 | if (obj_priv->phys_obj) | |
4394 | i915_gem_detach_phys_object(dev, obj); | |
4395 | ||
4396 | i915_gem_free_object_tail(obj); | |
4397 | } | |
4398 | ||
29105ccc CW |
4399 | int |
4400 | i915_gem_idle(struct drm_device *dev) | |
4401 | { | |
4402 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4403 | int ret; | |
28dfe52a | 4404 | |
29105ccc | 4405 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4406 | |
8187a2b7 | 4407 | if (dev_priv->mm.suspended || |
d1b851fc ZN |
4408 | (dev_priv->render_ring.gem_object == NULL) || |
4409 | (HAS_BSD(dev) && | |
4410 | dev_priv->bsd_ring.gem_object == NULL)) { | |
29105ccc CW |
4411 | mutex_unlock(&dev->struct_mutex); |
4412 | return 0; | |
28dfe52a EA |
4413 | } |
4414 | ||
29105ccc | 4415 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4416 | if (ret) { |
4417 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4418 | return ret; |
6dbe2772 | 4419 | } |
673a394b | 4420 | |
29105ccc CW |
4421 | /* Under UMS, be paranoid and evict. */ |
4422 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4423 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4424 | if (ret) { |
4425 | mutex_unlock(&dev->struct_mutex); | |
4426 | return ret; | |
4427 | } | |
4428 | } | |
4429 | ||
4430 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4431 | * We need to replace this with a semaphore, or something. | |
4432 | * And not confound mm.suspended! | |
4433 | */ | |
4434 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4435 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4436 | |
4437 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4438 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4439 | |
6dbe2772 KP |
4440 | mutex_unlock(&dev->struct_mutex); |
4441 | ||
29105ccc CW |
4442 | /* Cancel the retire work handler, which should be idle now. */ |
4443 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4444 | ||
673a394b EA |
4445 | return 0; |
4446 | } | |
4447 | ||
e552eb70 JB |
4448 | /* |
4449 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4450 | * over cache flushing. | |
4451 | */ | |
8187a2b7 | 4452 | static int |
e552eb70 JB |
4453 | i915_gem_init_pipe_control(struct drm_device *dev) |
4454 | { | |
4455 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4456 | struct drm_gem_object *obj; | |
4457 | struct drm_i915_gem_object *obj_priv; | |
4458 | int ret; | |
4459 | ||
34dc4d44 | 4460 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4461 | if (obj == NULL) { |
4462 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4463 | ret = -ENOMEM; | |
4464 | goto err; | |
4465 | } | |
4466 | obj_priv = to_intel_bo(obj); | |
4467 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4468 | ||
4469 | ret = i915_gem_object_pin(obj, 4096); | |
4470 | if (ret) | |
4471 | goto err_unref; | |
4472 | ||
4473 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4474 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4475 | if (dev_priv->seqno_page == NULL) | |
4476 | goto err_unpin; | |
4477 | ||
4478 | dev_priv->seqno_obj = obj; | |
4479 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4480 | ||
4481 | return 0; | |
4482 | ||
4483 | err_unpin: | |
4484 | i915_gem_object_unpin(obj); | |
4485 | err_unref: | |
4486 | drm_gem_object_unreference(obj); | |
4487 | err: | |
4488 | return ret; | |
4489 | } | |
4490 | ||
8187a2b7 ZN |
4491 | |
4492 | static void | |
e552eb70 JB |
4493 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4494 | { | |
4495 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4496 | struct drm_gem_object *obj; | |
4497 | struct drm_i915_gem_object *obj_priv; | |
4498 | ||
4499 | obj = dev_priv->seqno_obj; | |
4500 | obj_priv = to_intel_bo(obj); | |
4501 | kunmap(obj_priv->pages[0]); | |
4502 | i915_gem_object_unpin(obj); | |
4503 | drm_gem_object_unreference(obj); | |
4504 | dev_priv->seqno_obj = NULL; | |
4505 | ||
4506 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4507 | } |
4508 | ||
8187a2b7 ZN |
4509 | int |
4510 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4511 | { | |
4512 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4513 | int ret; | |
68f95ba9 | 4514 | |
8187a2b7 | 4515 | dev_priv->render_ring = render_ring; |
68f95ba9 | 4516 | |
8187a2b7 ZN |
4517 | if (!I915_NEED_GFX_HWS(dev)) { |
4518 | dev_priv->render_ring.status_page.page_addr | |
4519 | = dev_priv->status_page_dmah->vaddr; | |
4520 | memset(dev_priv->render_ring.status_page.page_addr, | |
4521 | 0, PAGE_SIZE); | |
4522 | } | |
68f95ba9 | 4523 | |
8187a2b7 ZN |
4524 | if (HAS_PIPE_CONTROL(dev)) { |
4525 | ret = i915_gem_init_pipe_control(dev); | |
4526 | if (ret) | |
4527 | return ret; | |
4528 | } | |
68f95ba9 | 4529 | |
8187a2b7 | 4530 | ret = intel_init_ring_buffer(dev, &dev_priv->render_ring); |
68f95ba9 CW |
4531 | if (ret) |
4532 | goto cleanup_pipe_control; | |
4533 | ||
4534 | if (HAS_BSD(dev)) { | |
d1b851fc ZN |
4535 | dev_priv->bsd_ring = bsd_ring; |
4536 | ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
68f95ba9 CW |
4537 | if (ret) |
4538 | goto cleanup_render_ring; | |
d1b851fc | 4539 | } |
68f95ba9 | 4540 | |
6f392d54 CW |
4541 | dev_priv->next_seqno = 1; |
4542 | ||
68f95ba9 CW |
4543 | return 0; |
4544 | ||
4545 | cleanup_render_ring: | |
4546 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
4547 | cleanup_pipe_control: | |
4548 | if (HAS_PIPE_CONTROL(dev)) | |
4549 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4550 | return ret; |
4551 | } | |
4552 | ||
4553 | void | |
4554 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4555 | { | |
4556 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4557 | ||
4558 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4559 | if (HAS_BSD(dev)) |
4560 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
8187a2b7 ZN |
4561 | if (HAS_PIPE_CONTROL(dev)) |
4562 | i915_gem_cleanup_pipe_control(dev); | |
4563 | } | |
4564 | ||
673a394b EA |
4565 | int |
4566 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4567 | struct drm_file *file_priv) | |
4568 | { | |
4569 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4570 | int ret; | |
4571 | ||
79e53945 JB |
4572 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4573 | return 0; | |
4574 | ||
ba1234d1 | 4575 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4576 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4577 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4578 | } |
4579 | ||
673a394b | 4580 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4581 | dev_priv->mm.suspended = 0; |
4582 | ||
4583 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4584 | if (ret != 0) { |
4585 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4586 | return ret; |
d816f6ac | 4587 | } |
9bb2d6f9 | 4588 | |
5e118f41 | 4589 | spin_lock(&dev_priv->mm.active_list_lock); |
852835f3 | 4590 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
d1b851fc | 4591 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
5e118f41 CW |
4592 | spin_unlock(&dev_priv->mm.active_list_lock); |
4593 | ||
673a394b EA |
4594 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4595 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4596 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
d1b851fc | 4597 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
673a394b | 4598 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4599 | |
5f35308b CW |
4600 | ret = drm_irq_install(dev); |
4601 | if (ret) | |
4602 | goto cleanup_ringbuffer; | |
dbb19d30 | 4603 | |
673a394b | 4604 | return 0; |
5f35308b CW |
4605 | |
4606 | cleanup_ringbuffer: | |
4607 | mutex_lock(&dev->struct_mutex); | |
4608 | i915_gem_cleanup_ringbuffer(dev); | |
4609 | dev_priv->mm.suspended = 1; | |
4610 | mutex_unlock(&dev->struct_mutex); | |
4611 | ||
4612 | return ret; | |
673a394b EA |
4613 | } |
4614 | ||
4615 | int | |
4616 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4617 | struct drm_file *file_priv) | |
4618 | { | |
79e53945 JB |
4619 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4620 | return 0; | |
4621 | ||
dbb19d30 | 4622 | drm_irq_uninstall(dev); |
e6890f6f | 4623 | return i915_gem_idle(dev); |
673a394b EA |
4624 | } |
4625 | ||
4626 | void | |
4627 | i915_gem_lastclose(struct drm_device *dev) | |
4628 | { | |
4629 | int ret; | |
673a394b | 4630 | |
e806b495 EA |
4631 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4632 | return; | |
4633 | ||
6dbe2772 KP |
4634 | ret = i915_gem_idle(dev); |
4635 | if (ret) | |
4636 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4637 | } |
4638 | ||
4639 | void | |
4640 | i915_gem_load(struct drm_device *dev) | |
4641 | { | |
b5aa8a0f | 4642 | int i; |
673a394b EA |
4643 | drm_i915_private_t *dev_priv = dev->dev_private; |
4644 | ||
5e118f41 | 4645 | spin_lock_init(&dev_priv->mm.active_list_lock); |
673a394b | 4646 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
99fcb766 | 4647 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
673a394b | 4648 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
a09ba7fa | 4649 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4650 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
852835f3 ZN |
4651 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
4652 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); | |
d1b851fc ZN |
4653 | if (HAS_BSD(dev)) { |
4654 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); | |
4655 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); | |
4656 | } | |
007cc8ac DV |
4657 | for (i = 0; i < 16; i++) |
4658 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4659 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4660 | i915_gem_retire_work_handler); | |
31169714 CW |
4661 | spin_lock(&shrink_list_lock); |
4662 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4663 | spin_unlock(&shrink_list_lock); | |
4664 | ||
94400120 DA |
4665 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4666 | if (IS_GEN3(dev)) { | |
4667 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4668 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4669 | /* arb state is a masked write, so set bit + bit in mask */ | |
4670 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4671 | I915_WRITE(MI_ARB_STATE, tmp); | |
4672 | } | |
4673 | } | |
4674 | ||
de151cf6 | 4675 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4676 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4677 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4678 | |
0f973f27 | 4679 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4680 | dev_priv->num_fence_regs = 16; |
4681 | else | |
4682 | dev_priv->num_fence_regs = 8; | |
4683 | ||
b5aa8a0f GH |
4684 | /* Initialize fence registers to zero */ |
4685 | if (IS_I965G(dev)) { | |
4686 | for (i = 0; i < 16; i++) | |
4687 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
4688 | } else { | |
4689 | for (i = 0; i < 8; i++) | |
4690 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4691 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4692 | for (i = 0; i < 8; i++) | |
4693 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
4694 | } | |
673a394b | 4695 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4696 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4697 | } |
71acb5eb DA |
4698 | |
4699 | /* | |
4700 | * Create a physically contiguous memory object for this object | |
4701 | * e.g. for cursor + overlay regs | |
4702 | */ | |
4703 | int i915_gem_init_phys_object(struct drm_device *dev, | |
6eeefaf3 | 4704 | int id, int size, int align) |
71acb5eb DA |
4705 | { |
4706 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4707 | struct drm_i915_gem_phys_object *phys_obj; | |
4708 | int ret; | |
4709 | ||
4710 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4711 | return 0; | |
4712 | ||
9a298b2a | 4713 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4714 | if (!phys_obj) |
4715 | return -ENOMEM; | |
4716 | ||
4717 | phys_obj->id = id; | |
4718 | ||
6eeefaf3 | 4719 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4720 | if (!phys_obj->handle) { |
4721 | ret = -ENOMEM; | |
4722 | goto kfree_obj; | |
4723 | } | |
4724 | #ifdef CONFIG_X86 | |
4725 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4726 | #endif | |
4727 | ||
4728 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4729 | ||
4730 | return 0; | |
4731 | kfree_obj: | |
9a298b2a | 4732 | kfree(phys_obj); |
71acb5eb DA |
4733 | return ret; |
4734 | } | |
4735 | ||
4736 | void i915_gem_free_phys_object(struct drm_device *dev, int id) | |
4737 | { | |
4738 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4739 | struct drm_i915_gem_phys_object *phys_obj; | |
4740 | ||
4741 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4742 | return; | |
4743 | ||
4744 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4745 | if (phys_obj->cur_obj) { | |
4746 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4747 | } | |
4748 | ||
4749 | #ifdef CONFIG_X86 | |
4750 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4751 | #endif | |
4752 | drm_pci_free(dev, phys_obj->handle); | |
4753 | kfree(phys_obj); | |
4754 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4755 | } | |
4756 | ||
4757 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4758 | { | |
4759 | int i; | |
4760 | ||
260883c8 | 4761 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4762 | i915_gem_free_phys_object(dev, i); |
4763 | } | |
4764 | ||
4765 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4766 | struct drm_gem_object *obj) | |
4767 | { | |
4768 | struct drm_i915_gem_object *obj_priv; | |
4769 | int i; | |
4770 | int ret; | |
4771 | int page_count; | |
4772 | ||
23010e43 | 4773 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4774 | if (!obj_priv->phys_obj) |
4775 | return; | |
4776 | ||
4bdadb97 | 4777 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4778 | if (ret) |
4779 | goto out; | |
4780 | ||
4781 | page_count = obj->size / PAGE_SIZE; | |
4782 | ||
4783 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4784 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4785 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4786 | ||
4787 | memcpy(dst, src, PAGE_SIZE); | |
4788 | kunmap_atomic(dst, KM_USER0); | |
4789 | } | |
856fa198 | 4790 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4791 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4792 | |
4793 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4794 | out: |
4795 | obj_priv->phys_obj->cur_obj = NULL; | |
4796 | obj_priv->phys_obj = NULL; | |
4797 | } | |
4798 | ||
4799 | int | |
4800 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4801 | struct drm_gem_object *obj, |
4802 | int id, | |
4803 | int align) | |
71acb5eb DA |
4804 | { |
4805 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4806 | struct drm_i915_gem_object *obj_priv; | |
4807 | int ret = 0; | |
4808 | int page_count; | |
4809 | int i; | |
4810 | ||
4811 | if (id > I915_MAX_PHYS_OBJECT) | |
4812 | return -EINVAL; | |
4813 | ||
23010e43 | 4814 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4815 | |
4816 | if (obj_priv->phys_obj) { | |
4817 | if (obj_priv->phys_obj->id == id) | |
4818 | return 0; | |
4819 | i915_gem_detach_phys_object(dev, obj); | |
4820 | } | |
4821 | ||
71acb5eb DA |
4822 | /* create a new object */ |
4823 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4824 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4825 | obj->size, align); |
71acb5eb | 4826 | if (ret) { |
aeb565df | 4827 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4828 | goto out; |
4829 | } | |
4830 | } | |
4831 | ||
4832 | /* bind to the object */ | |
4833 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4834 | obj_priv->phys_obj->cur_obj = obj; | |
4835 | ||
4bdadb97 | 4836 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4837 | if (ret) { |
4838 | DRM_ERROR("failed to get page list\n"); | |
4839 | goto out; | |
4840 | } | |
4841 | ||
4842 | page_count = obj->size / PAGE_SIZE; | |
4843 | ||
4844 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4845 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4846 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4847 | ||
4848 | memcpy(dst, src, PAGE_SIZE); | |
4849 | kunmap_atomic(src, KM_USER0); | |
4850 | } | |
4851 | ||
d78b47b9 CW |
4852 | i915_gem_object_put_pages(obj); |
4853 | ||
71acb5eb DA |
4854 | return 0; |
4855 | out: | |
4856 | return ret; | |
4857 | } | |
4858 | ||
4859 | static int | |
4860 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4861 | struct drm_i915_gem_pwrite *args, | |
4862 | struct drm_file *file_priv) | |
4863 | { | |
23010e43 | 4864 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4865 | void *obj_addr; |
4866 | int ret; | |
4867 | char __user *user_data; | |
4868 | ||
4869 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4870 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4871 | ||
44d98a61 | 4872 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4873 | ret = copy_from_user(obj_addr, user_data, args->size); |
4874 | if (ret) | |
4875 | return -EFAULT; | |
4876 | ||
4877 | drm_agp_chipset_flush(dev); | |
4878 | return 0; | |
4879 | } | |
b962442e EA |
4880 | |
4881 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) | |
4882 | { | |
4883 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
4884 | ||
4885 | /* Clean up our request list when the client is going away, so that | |
4886 | * later retire_requests won't dereference our soon-to-be-gone | |
4887 | * file_priv. | |
4888 | */ | |
4889 | mutex_lock(&dev->struct_mutex); | |
4890 | while (!list_empty(&i915_file_priv->mm.request_list)) | |
4891 | list_del_init(i915_file_priv->mm.request_list.next); | |
4892 | mutex_unlock(&dev->struct_mutex); | |
4893 | } | |
31169714 | 4894 | |
1637ef41 CW |
4895 | static int |
4896 | i915_gpu_is_active(struct drm_device *dev) | |
4897 | { | |
4898 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4899 | int lists_empty; | |
4900 | ||
4901 | spin_lock(&dev_priv->mm.active_list_lock); | |
4902 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && | |
852835f3 | 4903 | list_empty(&dev_priv->render_ring.active_list); |
d1b851fc ZN |
4904 | if (HAS_BSD(dev)) |
4905 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); | |
1637ef41 CW |
4906 | spin_unlock(&dev_priv->mm.active_list_lock); |
4907 | ||
4908 | return !lists_empty; | |
4909 | } | |
4910 | ||
31169714 | 4911 | static int |
7f8275d0 | 4912 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
4913 | { |
4914 | drm_i915_private_t *dev_priv, *next_dev; | |
4915 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4916 | int cnt = 0; | |
4917 | int would_deadlock = 1; | |
4918 | ||
4919 | /* "fast-path" to count number of available objects */ | |
4920 | if (nr_to_scan == 0) { | |
4921 | spin_lock(&shrink_list_lock); | |
4922 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4923 | struct drm_device *dev = dev_priv->dev; | |
4924 | ||
4925 | if (mutex_trylock(&dev->struct_mutex)) { | |
4926 | list_for_each_entry(obj_priv, | |
4927 | &dev_priv->mm.inactive_list, | |
4928 | list) | |
4929 | cnt++; | |
4930 | mutex_unlock(&dev->struct_mutex); | |
4931 | } | |
4932 | } | |
4933 | spin_unlock(&shrink_list_lock); | |
4934 | ||
4935 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4936 | } | |
4937 | ||
4938 | spin_lock(&shrink_list_lock); | |
4939 | ||
1637ef41 | 4940 | rescan: |
31169714 CW |
4941 | /* first scan for clean buffers */ |
4942 | list_for_each_entry_safe(dev_priv, next_dev, | |
4943 | &shrink_list, mm.shrink_list) { | |
4944 | struct drm_device *dev = dev_priv->dev; | |
4945 | ||
4946 | if (! mutex_trylock(&dev->struct_mutex)) | |
4947 | continue; | |
4948 | ||
4949 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 4950 | i915_gem_retire_requests(dev); |
31169714 CW |
4951 | |
4952 | list_for_each_entry_safe(obj_priv, next_obj, | |
4953 | &dev_priv->mm.inactive_list, | |
4954 | list) { | |
4955 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
a8089e84 | 4956 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4957 | if (--nr_to_scan <= 0) |
4958 | break; | |
4959 | } | |
4960 | } | |
4961 | ||
4962 | spin_lock(&shrink_list_lock); | |
4963 | mutex_unlock(&dev->struct_mutex); | |
4964 | ||
963b4836 CW |
4965 | would_deadlock = 0; |
4966 | ||
31169714 CW |
4967 | if (nr_to_scan <= 0) |
4968 | break; | |
4969 | } | |
4970 | ||
4971 | /* second pass, evict/count anything still on the inactive list */ | |
4972 | list_for_each_entry_safe(dev_priv, next_dev, | |
4973 | &shrink_list, mm.shrink_list) { | |
4974 | struct drm_device *dev = dev_priv->dev; | |
4975 | ||
4976 | if (! mutex_trylock(&dev->struct_mutex)) | |
4977 | continue; | |
4978 | ||
4979 | spin_unlock(&shrink_list_lock); | |
4980 | ||
4981 | list_for_each_entry_safe(obj_priv, next_obj, | |
4982 | &dev_priv->mm.inactive_list, | |
4983 | list) { | |
4984 | if (nr_to_scan > 0) { | |
a8089e84 | 4985 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4986 | nr_to_scan--; |
4987 | } else | |
4988 | cnt++; | |
4989 | } | |
4990 | ||
4991 | spin_lock(&shrink_list_lock); | |
4992 | mutex_unlock(&dev->struct_mutex); | |
4993 | ||
4994 | would_deadlock = 0; | |
4995 | } | |
4996 | ||
1637ef41 CW |
4997 | if (nr_to_scan) { |
4998 | int active = 0; | |
4999 | ||
5000 | /* | |
5001 | * We are desperate for pages, so as a last resort, wait | |
5002 | * for the GPU to finish and discard whatever we can. | |
5003 | * This has a dramatic impact to reduce the number of | |
5004 | * OOM-killer events whilst running the GPU aggressively. | |
5005 | */ | |
5006 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5007 | struct drm_device *dev = dev_priv->dev; | |
5008 | ||
5009 | if (!mutex_trylock(&dev->struct_mutex)) | |
5010 | continue; | |
5011 | ||
5012 | spin_unlock(&shrink_list_lock); | |
5013 | ||
5014 | if (i915_gpu_is_active(dev)) { | |
5015 | i915_gpu_idle(dev); | |
5016 | active++; | |
5017 | } | |
5018 | ||
5019 | spin_lock(&shrink_list_lock); | |
5020 | mutex_unlock(&dev->struct_mutex); | |
5021 | } | |
5022 | ||
5023 | if (active) | |
5024 | goto rescan; | |
5025 | } | |
5026 | ||
31169714 CW |
5027 | spin_unlock(&shrink_list_lock); |
5028 | ||
5029 | if (would_deadlock) | |
5030 | return -1; | |
5031 | else if (cnt > 0) | |
5032 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5033 | else | |
5034 | return 0; | |
5035 | } | |
5036 | ||
5037 | static struct shrinker shrinker = { | |
5038 | .shrink = i915_gem_shrink, | |
5039 | .seeks = DEFAULT_SEEKS, | |
5040 | }; | |
5041 | ||
5042 | __init void | |
5043 | i915_gem_shrinker_init(void) | |
5044 | { | |
5045 | register_shrinker(&shrinker); | |
5046 | } | |
5047 | ||
5048 | __exit void | |
5049 | i915_gem_shrinker_exit(void) | |
5050 | { | |
5051 | unregister_shrinker(&shrinker); | |
5052 | } |