Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
0ccdacf6 | 35 | #include "intel_mocs.h" |
5949eac4 | 36 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
673a394b | 38 | #include <linux/swap.h> |
79e53945 | 39 | #include <linux/pci.h> |
1286ff73 | 40 | #include <linux/dma-buf.h> |
673a394b | 41 | |
05394f39 | 42 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 43 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
c8725f3d | 44 | static void |
b4716185 CW |
45 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
46 | static void | |
47 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); | |
61050808 | 48 | |
c76ce038 CW |
49 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
50 | enum i915_cache_level level) | |
51 | { | |
52 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
53 | } | |
54 | ||
2c22569b CW |
55 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
56 | { | |
57 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
58 | return true; | |
59 | ||
60 | return obj->pin_display; | |
61 | } | |
62 | ||
73aa808f CW |
63 | /* some bookkeeping */ |
64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
65 | size_t size) | |
66 | { | |
c20e8355 | 67 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
68 | dev_priv->mm.object_count++; |
69 | dev_priv->mm.object_memory += size; | |
c20e8355 | 70 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
71 | } |
72 | ||
73 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
74 | size_t size) | |
75 | { | |
c20e8355 | 76 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
77 | dev_priv->mm.object_count--; |
78 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 79 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
80 | } |
81 | ||
21dd3734 | 82 | static int |
33196ded | 83 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 84 | { |
30dbf0c0 CW |
85 | int ret; |
86 | ||
d98c52cf | 87 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
88 | return 0; |
89 | ||
0a6759c6 DV |
90 | /* |
91 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
92 | * userspace. If it takes that long something really bad is going on and | |
93 | * we should simply try to bail out and fail as gracefully as possible. | |
94 | */ | |
1f83fee0 | 95 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 96 | !i915_reset_in_progress(error), |
1f83fee0 | 97 | 10*HZ); |
0a6759c6 DV |
98 | if (ret == 0) { |
99 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
100 | return -EIO; | |
101 | } else if (ret < 0) { | |
30dbf0c0 | 102 | return ret; |
d98c52cf CW |
103 | } else { |
104 | return 0; | |
0a6759c6 | 105 | } |
30dbf0c0 CW |
106 | } |
107 | ||
54cf91dc | 108 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 109 | { |
33196ded | 110 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
111 | int ret; |
112 | ||
33196ded | 113 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
114 | if (ret) |
115 | return ret; | |
116 | ||
117 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
118 | if (ret) | |
119 | return ret; | |
120 | ||
23bc5982 | 121 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
122 | return 0; |
123 | } | |
30dbf0c0 | 124 | |
5a125c3c EA |
125 | int |
126 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 127 | struct drm_file *file) |
5a125c3c | 128 | { |
72e96d64 | 129 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 130 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 131 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 132 | struct i915_vma *vma; |
6299f992 | 133 | size_t pinned; |
5a125c3c | 134 | |
6299f992 | 135 | pinned = 0; |
73aa808f | 136 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 137 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
ca1543be TU |
138 | if (vma->pin_count) |
139 | pinned += vma->node.size; | |
1c7f4bca | 140 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
ca1543be TU |
141 | if (vma->pin_count) |
142 | pinned += vma->node.size; | |
73aa808f | 143 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 144 | |
72e96d64 | 145 | args->aper_size = ggtt->base.total; |
0206e353 | 146 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 147 | |
5a125c3c EA |
148 | return 0; |
149 | } | |
150 | ||
6a2c4232 CW |
151 | static int |
152 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 153 | { |
6a2c4232 CW |
154 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
155 | char *vaddr = obj->phys_handle->vaddr; | |
156 | struct sg_table *st; | |
157 | struct scatterlist *sg; | |
158 | int i; | |
00731155 | 159 | |
6a2c4232 CW |
160 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
161 | return -EINVAL; | |
162 | ||
163 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
164 | struct page *page; | |
165 | char *src; | |
166 | ||
167 | page = shmem_read_mapping_page(mapping, i); | |
168 | if (IS_ERR(page)) | |
169 | return PTR_ERR(page); | |
170 | ||
171 | src = kmap_atomic(page); | |
172 | memcpy(vaddr, src, PAGE_SIZE); | |
173 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
174 | kunmap_atomic(src); | |
175 | ||
09cbfeaf | 176 | put_page(page); |
6a2c4232 CW |
177 | vaddr += PAGE_SIZE; |
178 | } | |
179 | ||
180 | i915_gem_chipset_flush(obj->base.dev); | |
181 | ||
182 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
183 | if (st == NULL) | |
184 | return -ENOMEM; | |
185 | ||
186 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
187 | kfree(st); | |
188 | return -ENOMEM; | |
189 | } | |
190 | ||
191 | sg = st->sgl; | |
192 | sg->offset = 0; | |
193 | sg->length = obj->base.size; | |
00731155 | 194 | |
6a2c4232 CW |
195 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
196 | sg_dma_len(sg) = obj->base.size; | |
197 | ||
198 | obj->pages = st; | |
6a2c4232 CW |
199 | return 0; |
200 | } | |
201 | ||
202 | static void | |
203 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
204 | { | |
205 | int ret; | |
206 | ||
207 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 208 | |
6a2c4232 | 209 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 210 | if (WARN_ON(ret)) { |
6a2c4232 CW |
211 | /* In the event of a disaster, abandon all caches and |
212 | * hope for the best. | |
213 | */ | |
6a2c4232 CW |
214 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
215 | } | |
216 | ||
217 | if (obj->madv == I915_MADV_DONTNEED) | |
218 | obj->dirty = 0; | |
219 | ||
220 | if (obj->dirty) { | |
00731155 | 221 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 222 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
223 | int i; |
224 | ||
225 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
226 | struct page *page; |
227 | char *dst; | |
228 | ||
229 | page = shmem_read_mapping_page(mapping, i); | |
230 | if (IS_ERR(page)) | |
231 | continue; | |
232 | ||
233 | dst = kmap_atomic(page); | |
234 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
235 | memcpy(dst, vaddr, PAGE_SIZE); | |
236 | kunmap_atomic(dst); | |
237 | ||
238 | set_page_dirty(page); | |
239 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 240 | mark_page_accessed(page); |
09cbfeaf | 241 | put_page(page); |
00731155 CW |
242 | vaddr += PAGE_SIZE; |
243 | } | |
6a2c4232 | 244 | obj->dirty = 0; |
00731155 CW |
245 | } |
246 | ||
6a2c4232 CW |
247 | sg_free_table(obj->pages); |
248 | kfree(obj->pages); | |
6a2c4232 CW |
249 | } |
250 | ||
251 | static void | |
252 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
253 | { | |
254 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
255 | } | |
256 | ||
257 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
258 | .get_pages = i915_gem_object_get_pages_phys, | |
259 | .put_pages = i915_gem_object_put_pages_phys, | |
260 | .release = i915_gem_object_release_phys, | |
261 | }; | |
262 | ||
263 | static int | |
264 | drop_pages(struct drm_i915_gem_object *obj) | |
265 | { | |
266 | struct i915_vma *vma, *next; | |
267 | int ret; | |
268 | ||
269 | drm_gem_object_reference(&obj->base); | |
1c7f4bca | 270 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) |
6a2c4232 CW |
271 | if (i915_vma_unbind(vma)) |
272 | break; | |
273 | ||
274 | ret = i915_gem_object_put_pages(obj); | |
275 | drm_gem_object_unreference(&obj->base); | |
276 | ||
277 | return ret; | |
00731155 CW |
278 | } |
279 | ||
280 | int | |
281 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
282 | int align) | |
283 | { | |
284 | drm_dma_handle_t *phys; | |
6a2c4232 | 285 | int ret; |
00731155 CW |
286 | |
287 | if (obj->phys_handle) { | |
288 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
289 | return -EBUSY; | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | if (obj->madv != I915_MADV_WILLNEED) | |
295 | return -EFAULT; | |
296 | ||
297 | if (obj->base.filp == NULL) | |
298 | return -EINVAL; | |
299 | ||
6a2c4232 CW |
300 | ret = drop_pages(obj); |
301 | if (ret) | |
302 | return ret; | |
303 | ||
00731155 CW |
304 | /* create a new object */ |
305 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
306 | if (!phys) | |
307 | return -ENOMEM; | |
308 | ||
00731155 | 309 | obj->phys_handle = phys; |
6a2c4232 CW |
310 | obj->ops = &i915_gem_phys_ops; |
311 | ||
312 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
313 | } |
314 | ||
315 | static int | |
316 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
317 | struct drm_i915_gem_pwrite *args, | |
318 | struct drm_file *file_priv) | |
319 | { | |
320 | struct drm_device *dev = obj->base.dev; | |
321 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
322 | char __user *user_data = to_user_ptr(args->data_ptr); | |
063e4e6b | 323 | int ret = 0; |
6a2c4232 CW |
324 | |
325 | /* We manually control the domain here and pretend that it | |
326 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
327 | */ | |
328 | ret = i915_gem_object_wait_rendering(obj, false); | |
329 | if (ret) | |
330 | return ret; | |
00731155 | 331 | |
77a0d1ca | 332 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
333 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
334 | unsigned long unwritten; | |
335 | ||
336 | /* The physical object once assigned is fixed for the lifetime | |
337 | * of the obj, so we can safely drop the lock and continue | |
338 | * to access vaddr. | |
339 | */ | |
340 | mutex_unlock(&dev->struct_mutex); | |
341 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
342 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
343 | if (unwritten) { |
344 | ret = -EFAULT; | |
345 | goto out; | |
346 | } | |
00731155 CW |
347 | } |
348 | ||
6a2c4232 | 349 | drm_clflush_virt_range(vaddr, args->size); |
00731155 | 350 | i915_gem_chipset_flush(dev); |
063e4e6b PZ |
351 | |
352 | out: | |
de152b62 | 353 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 354 | return ret; |
00731155 CW |
355 | } |
356 | ||
42dcedd4 CW |
357 | void *i915_gem_object_alloc(struct drm_device *dev) |
358 | { | |
359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
efab6d8d | 360 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
361 | } |
362 | ||
363 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
364 | { | |
365 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
efab6d8d | 366 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
367 | } |
368 | ||
ff72145b DA |
369 | static int |
370 | i915_gem_create(struct drm_file *file, | |
371 | struct drm_device *dev, | |
372 | uint64_t size, | |
373 | uint32_t *handle_p) | |
673a394b | 374 | { |
05394f39 | 375 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
376 | int ret; |
377 | u32 handle; | |
673a394b | 378 | |
ff72145b | 379 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
380 | if (size == 0) |
381 | return -EINVAL; | |
673a394b EA |
382 | |
383 | /* Allocate the new object */ | |
ff72145b | 384 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
385 | if (obj == NULL) |
386 | return -ENOMEM; | |
387 | ||
05394f39 | 388 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 389 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
390 | drm_gem_object_unreference_unlocked(&obj->base); |
391 | if (ret) | |
392 | return ret; | |
202f2fef | 393 | |
ff72145b | 394 | *handle_p = handle; |
673a394b EA |
395 | return 0; |
396 | } | |
397 | ||
ff72145b DA |
398 | int |
399 | i915_gem_dumb_create(struct drm_file *file, | |
400 | struct drm_device *dev, | |
401 | struct drm_mode_create_dumb *args) | |
402 | { | |
403 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 404 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
405 | args->size = args->pitch * args->height; |
406 | return i915_gem_create(file, dev, | |
da6b51d0 | 407 | args->size, &args->handle); |
ff72145b DA |
408 | } |
409 | ||
ff72145b DA |
410 | /** |
411 | * Creates a new mm object and returns a handle to it. | |
412 | */ | |
413 | int | |
414 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
415 | struct drm_file *file) | |
416 | { | |
417 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 418 | |
ff72145b | 419 | return i915_gem_create(file, dev, |
da6b51d0 | 420 | args->size, &args->handle); |
ff72145b DA |
421 | } |
422 | ||
8461d226 DV |
423 | static inline int |
424 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
425 | const char *gpu_vaddr, int gpu_offset, | |
426 | int length) | |
427 | { | |
428 | int ret, cpu_offset = 0; | |
429 | ||
430 | while (length > 0) { | |
431 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
432 | int this_length = min(cacheline_end - gpu_offset, length); | |
433 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
434 | ||
435 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
436 | gpu_vaddr + swizzled_gpu_offset, | |
437 | this_length); | |
438 | if (ret) | |
439 | return ret + length; | |
440 | ||
441 | cpu_offset += this_length; | |
442 | gpu_offset += this_length; | |
443 | length -= this_length; | |
444 | } | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
8c59967c | 449 | static inline int |
4f0c7cfb BW |
450 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
451 | const char __user *cpu_vaddr, | |
8c59967c DV |
452 | int length) |
453 | { | |
454 | int ret, cpu_offset = 0; | |
455 | ||
456 | while (length > 0) { | |
457 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
458 | int this_length = min(cacheline_end - gpu_offset, length); | |
459 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
460 | ||
461 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
462 | cpu_vaddr + cpu_offset, | |
463 | this_length); | |
464 | if (ret) | |
465 | return ret + length; | |
466 | ||
467 | cpu_offset += this_length; | |
468 | gpu_offset += this_length; | |
469 | length -= this_length; | |
470 | } | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
4c914c0c BV |
475 | /* |
476 | * Pins the specified object's pages and synchronizes the object with | |
477 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
478 | * flush the object from the CPU cache. | |
479 | */ | |
480 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
481 | int *needs_clflush) | |
482 | { | |
483 | int ret; | |
484 | ||
485 | *needs_clflush = 0; | |
486 | ||
1db6e2e7 | 487 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
4c914c0c BV |
488 | return -EINVAL; |
489 | ||
490 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
491 | /* If we're not in the cpu read domain, set ourself into the gtt | |
492 | * read domain and manually flush cachelines (if required). This | |
493 | * optimizes for the case when the gpu will dirty the data | |
494 | * anyway again before the next pread happens. */ | |
495 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
496 | obj->cache_level); | |
497 | ret = i915_gem_object_wait_rendering(obj, true); | |
498 | if (ret) | |
499 | return ret; | |
500 | } | |
501 | ||
502 | ret = i915_gem_object_get_pages(obj); | |
503 | if (ret) | |
504 | return ret; | |
505 | ||
506 | i915_gem_object_pin_pages(obj); | |
507 | ||
508 | return ret; | |
509 | } | |
510 | ||
d174bd64 DV |
511 | /* Per-page copy function for the shmem pread fastpath. |
512 | * Flushes invalid cachelines before reading the target if | |
513 | * needs_clflush is set. */ | |
eb01459f | 514 | static int |
d174bd64 DV |
515 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
516 | char __user *user_data, | |
517 | bool page_do_bit17_swizzling, bool needs_clflush) | |
518 | { | |
519 | char *vaddr; | |
520 | int ret; | |
521 | ||
e7e58eb5 | 522 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
523 | return -EINVAL; |
524 | ||
525 | vaddr = kmap_atomic(page); | |
526 | if (needs_clflush) | |
527 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
528 | page_length); | |
529 | ret = __copy_to_user_inatomic(user_data, | |
530 | vaddr + shmem_page_offset, | |
531 | page_length); | |
532 | kunmap_atomic(vaddr); | |
533 | ||
f60d7f0c | 534 | return ret ? -EFAULT : 0; |
d174bd64 DV |
535 | } |
536 | ||
23c18c71 DV |
537 | static void |
538 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
539 | bool swizzled) | |
540 | { | |
e7e58eb5 | 541 | if (unlikely(swizzled)) { |
23c18c71 DV |
542 | unsigned long start = (unsigned long) addr; |
543 | unsigned long end = (unsigned long) addr + length; | |
544 | ||
545 | /* For swizzling simply ensure that we always flush both | |
546 | * channels. Lame, but simple and it works. Swizzled | |
547 | * pwrite/pread is far from a hotpath - current userspace | |
548 | * doesn't use it at all. */ | |
549 | start = round_down(start, 128); | |
550 | end = round_up(end, 128); | |
551 | ||
552 | drm_clflush_virt_range((void *)start, end - start); | |
553 | } else { | |
554 | drm_clflush_virt_range(addr, length); | |
555 | } | |
556 | ||
557 | } | |
558 | ||
d174bd64 DV |
559 | /* Only difference to the fast-path function is that this can handle bit17 |
560 | * and uses non-atomic copy and kmap functions. */ | |
561 | static int | |
562 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
563 | char __user *user_data, | |
564 | bool page_do_bit17_swizzling, bool needs_clflush) | |
565 | { | |
566 | char *vaddr; | |
567 | int ret; | |
568 | ||
569 | vaddr = kmap(page); | |
570 | if (needs_clflush) | |
23c18c71 DV |
571 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
572 | page_length, | |
573 | page_do_bit17_swizzling); | |
d174bd64 DV |
574 | |
575 | if (page_do_bit17_swizzling) | |
576 | ret = __copy_to_user_swizzled(user_data, | |
577 | vaddr, shmem_page_offset, | |
578 | page_length); | |
579 | else | |
580 | ret = __copy_to_user(user_data, | |
581 | vaddr + shmem_page_offset, | |
582 | page_length); | |
583 | kunmap(page); | |
584 | ||
f60d7f0c | 585 | return ret ? - EFAULT : 0; |
d174bd64 DV |
586 | } |
587 | ||
eb01459f | 588 | static int |
dbf7bff0 DV |
589 | i915_gem_shmem_pread(struct drm_device *dev, |
590 | struct drm_i915_gem_object *obj, | |
591 | struct drm_i915_gem_pread *args, | |
592 | struct drm_file *file) | |
eb01459f | 593 | { |
8461d226 | 594 | char __user *user_data; |
eb01459f | 595 | ssize_t remain; |
8461d226 | 596 | loff_t offset; |
eb2c0c81 | 597 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 598 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 599 | int prefaulted = 0; |
8489731c | 600 | int needs_clflush = 0; |
67d5a50c | 601 | struct sg_page_iter sg_iter; |
eb01459f | 602 | |
2bb4629a | 603 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
604 | remain = args->size; |
605 | ||
8461d226 | 606 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 607 | |
4c914c0c | 608 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
609 | if (ret) |
610 | return ret; | |
611 | ||
8461d226 | 612 | offset = args->offset; |
eb01459f | 613 | |
67d5a50c ID |
614 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
615 | offset >> PAGE_SHIFT) { | |
2db76d7c | 616 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
617 | |
618 | if (remain <= 0) | |
619 | break; | |
620 | ||
eb01459f EA |
621 | /* Operation in this page |
622 | * | |
eb01459f | 623 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
624 | * page_length = bytes to copy for this page |
625 | */ | |
c8cbbb8b | 626 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
627 | page_length = remain; |
628 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
629 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 630 | |
8461d226 DV |
631 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
632 | (page_to_phys(page) & (1 << 17)) != 0; | |
633 | ||
d174bd64 DV |
634 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
635 | user_data, page_do_bit17_swizzling, | |
636 | needs_clflush); | |
637 | if (ret == 0) | |
638 | goto next_page; | |
dbf7bff0 | 639 | |
dbf7bff0 DV |
640 | mutex_unlock(&dev->struct_mutex); |
641 | ||
d330a953 | 642 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 643 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
644 | /* Userspace is tricking us, but we've already clobbered |
645 | * its pages with the prefault and promised to write the | |
646 | * data up to the first fault. Hence ignore any errors | |
647 | * and just continue. */ | |
648 | (void)ret; | |
649 | prefaulted = 1; | |
650 | } | |
eb01459f | 651 | |
d174bd64 DV |
652 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
653 | user_data, page_do_bit17_swizzling, | |
654 | needs_clflush); | |
eb01459f | 655 | |
dbf7bff0 | 656 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 657 | |
f60d7f0c | 658 | if (ret) |
8461d226 | 659 | goto out; |
8461d226 | 660 | |
17793c9a | 661 | next_page: |
eb01459f | 662 | remain -= page_length; |
8461d226 | 663 | user_data += page_length; |
eb01459f EA |
664 | offset += page_length; |
665 | } | |
666 | ||
4f27b75d | 667 | out: |
f60d7f0c CW |
668 | i915_gem_object_unpin_pages(obj); |
669 | ||
eb01459f EA |
670 | return ret; |
671 | } | |
672 | ||
673a394b EA |
673 | /** |
674 | * Reads data from the object referenced by handle. | |
675 | * | |
676 | * On error, the contents of *data are undefined. | |
677 | */ | |
678 | int | |
679 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 680 | struct drm_file *file) |
673a394b EA |
681 | { |
682 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 683 | struct drm_i915_gem_object *obj; |
35b62a89 | 684 | int ret = 0; |
673a394b | 685 | |
51311d0a CW |
686 | if (args->size == 0) |
687 | return 0; | |
688 | ||
689 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 690 | to_user_ptr(args->data_ptr), |
51311d0a CW |
691 | args->size)) |
692 | return -EFAULT; | |
693 | ||
4f27b75d | 694 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 695 | if (ret) |
4f27b75d | 696 | return ret; |
673a394b | 697 | |
05394f39 | 698 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 699 | if (&obj->base == NULL) { |
1d7cfea1 CW |
700 | ret = -ENOENT; |
701 | goto unlock; | |
4f27b75d | 702 | } |
673a394b | 703 | |
7dcd2499 | 704 | /* Bounds check source. */ |
05394f39 CW |
705 | if (args->offset > obj->base.size || |
706 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 707 | ret = -EINVAL; |
35b62a89 | 708 | goto out; |
ce9d419d CW |
709 | } |
710 | ||
1286ff73 DV |
711 | /* prime objects have no backing filp to GEM pread/pwrite |
712 | * pages from. | |
713 | */ | |
714 | if (!obj->base.filp) { | |
715 | ret = -EINVAL; | |
716 | goto out; | |
717 | } | |
718 | ||
db53a302 CW |
719 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
720 | ||
dbf7bff0 | 721 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 722 | |
35b62a89 | 723 | out: |
05394f39 | 724 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 725 | unlock: |
4f27b75d | 726 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 727 | return ret; |
673a394b EA |
728 | } |
729 | ||
0839ccb8 KP |
730 | /* This is the fast write path which cannot handle |
731 | * page faults in the source data | |
9b7530cc | 732 | */ |
0839ccb8 KP |
733 | |
734 | static inline int | |
735 | fast_user_write(struct io_mapping *mapping, | |
736 | loff_t page_base, int page_offset, | |
737 | char __user *user_data, | |
738 | int length) | |
9b7530cc | 739 | { |
4f0c7cfb BW |
740 | void __iomem *vaddr_atomic; |
741 | void *vaddr; | |
0839ccb8 | 742 | unsigned long unwritten; |
9b7530cc | 743 | |
3e4d3af5 | 744 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
745 | /* We can use the cpu mem copy function because this is X86. */ |
746 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
747 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 748 | user_data, length); |
3e4d3af5 | 749 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 750 | return unwritten; |
0839ccb8 KP |
751 | } |
752 | ||
3de09aa3 EA |
753 | /** |
754 | * This is the fast pwrite path, where we copy the data directly from the | |
755 | * user into the GTT, uncached. | |
756 | */ | |
673a394b | 757 | static int |
05394f39 CW |
758 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
759 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 760 | struct drm_i915_gem_pwrite *args, |
05394f39 | 761 | struct drm_file *file) |
673a394b | 762 | { |
72e96d64 JL |
763 | struct drm_i915_private *dev_priv = to_i915(dev); |
764 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
673a394b | 765 | ssize_t remain; |
0839ccb8 | 766 | loff_t offset, page_base; |
673a394b | 767 | char __user *user_data; |
935aaa69 DV |
768 | int page_offset, page_length, ret; |
769 | ||
1ec9e26d | 770 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
771 | if (ret) |
772 | goto out; | |
773 | ||
774 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
775 | if (ret) | |
776 | goto out_unpin; | |
777 | ||
778 | ret = i915_gem_object_put_fence(obj); | |
779 | if (ret) | |
780 | goto out_unpin; | |
673a394b | 781 | |
2bb4629a | 782 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 783 | remain = args->size; |
673a394b | 784 | |
f343c5f6 | 785 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b | 786 | |
77a0d1ca | 787 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
063e4e6b | 788 | |
673a394b EA |
789 | while (remain > 0) { |
790 | /* Operation in this page | |
791 | * | |
0839ccb8 KP |
792 | * page_base = page offset within aperture |
793 | * page_offset = offset within page | |
794 | * page_length = bytes to copy for this page | |
673a394b | 795 | */ |
c8cbbb8b CW |
796 | page_base = offset & PAGE_MASK; |
797 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
798 | page_length = remain; |
799 | if ((page_offset + remain) > PAGE_SIZE) | |
800 | page_length = PAGE_SIZE - page_offset; | |
801 | ||
0839ccb8 | 802 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
803 | * source page isn't available. Return the error and we'll |
804 | * retry in the slow path. | |
0839ccb8 | 805 | */ |
72e96d64 | 806 | if (fast_user_write(ggtt->mappable, page_base, |
935aaa69 DV |
807 | page_offset, user_data, page_length)) { |
808 | ret = -EFAULT; | |
063e4e6b | 809 | goto out_flush; |
935aaa69 | 810 | } |
673a394b | 811 | |
0839ccb8 KP |
812 | remain -= page_length; |
813 | user_data += page_length; | |
814 | offset += page_length; | |
673a394b | 815 | } |
673a394b | 816 | |
063e4e6b | 817 | out_flush: |
de152b62 | 818 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 819 | out_unpin: |
d7f46fc4 | 820 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 821 | out: |
3de09aa3 | 822 | return ret; |
673a394b EA |
823 | } |
824 | ||
d174bd64 DV |
825 | /* Per-page copy function for the shmem pwrite fastpath. |
826 | * Flushes invalid cachelines before writing to the target if | |
827 | * needs_clflush_before is set and flushes out any written cachelines after | |
828 | * writing if needs_clflush is set. */ | |
3043c60c | 829 | static int |
d174bd64 DV |
830 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
831 | char __user *user_data, | |
832 | bool page_do_bit17_swizzling, | |
833 | bool needs_clflush_before, | |
834 | bool needs_clflush_after) | |
673a394b | 835 | { |
d174bd64 | 836 | char *vaddr; |
673a394b | 837 | int ret; |
3de09aa3 | 838 | |
e7e58eb5 | 839 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 840 | return -EINVAL; |
3de09aa3 | 841 | |
d174bd64 DV |
842 | vaddr = kmap_atomic(page); |
843 | if (needs_clflush_before) | |
844 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
845 | page_length); | |
c2831a94 CW |
846 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
847 | user_data, page_length); | |
d174bd64 DV |
848 | if (needs_clflush_after) |
849 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
850 | page_length); | |
851 | kunmap_atomic(vaddr); | |
3de09aa3 | 852 | |
755d2218 | 853 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
854 | } |
855 | ||
d174bd64 DV |
856 | /* Only difference to the fast-path function is that this can handle bit17 |
857 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 858 | static int |
d174bd64 DV |
859 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
860 | char __user *user_data, | |
861 | bool page_do_bit17_swizzling, | |
862 | bool needs_clflush_before, | |
863 | bool needs_clflush_after) | |
673a394b | 864 | { |
d174bd64 DV |
865 | char *vaddr; |
866 | int ret; | |
e5281ccd | 867 | |
d174bd64 | 868 | vaddr = kmap(page); |
e7e58eb5 | 869 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
870 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
871 | page_length, | |
872 | page_do_bit17_swizzling); | |
d174bd64 DV |
873 | if (page_do_bit17_swizzling) |
874 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
875 | user_data, |
876 | page_length); | |
d174bd64 DV |
877 | else |
878 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
879 | user_data, | |
880 | page_length); | |
881 | if (needs_clflush_after) | |
23c18c71 DV |
882 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
883 | page_length, | |
884 | page_do_bit17_swizzling); | |
d174bd64 | 885 | kunmap(page); |
40123c1f | 886 | |
755d2218 | 887 | return ret ? -EFAULT : 0; |
40123c1f EA |
888 | } |
889 | ||
40123c1f | 890 | static int |
e244a443 DV |
891 | i915_gem_shmem_pwrite(struct drm_device *dev, |
892 | struct drm_i915_gem_object *obj, | |
893 | struct drm_i915_gem_pwrite *args, | |
894 | struct drm_file *file) | |
40123c1f | 895 | { |
40123c1f | 896 | ssize_t remain; |
8c59967c DV |
897 | loff_t offset; |
898 | char __user *user_data; | |
eb2c0c81 | 899 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 900 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 901 | int hit_slowpath = 0; |
58642885 DV |
902 | int needs_clflush_after = 0; |
903 | int needs_clflush_before = 0; | |
67d5a50c | 904 | struct sg_page_iter sg_iter; |
40123c1f | 905 | |
2bb4629a | 906 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
907 | remain = args->size; |
908 | ||
8c59967c | 909 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 910 | |
58642885 DV |
911 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
912 | /* If we're not in the cpu write domain, set ourself into the gtt | |
913 | * write domain and manually flush cachelines (if required). This | |
914 | * optimizes for the case when the gpu will use the data | |
915 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 916 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
917 | ret = i915_gem_object_wait_rendering(obj, false); |
918 | if (ret) | |
919 | return ret; | |
58642885 | 920 | } |
c76ce038 CW |
921 | /* Same trick applies to invalidate partially written cachelines read |
922 | * before writing. */ | |
923 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
924 | needs_clflush_before = | |
925 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 926 | |
755d2218 CW |
927 | ret = i915_gem_object_get_pages(obj); |
928 | if (ret) | |
929 | return ret; | |
930 | ||
77a0d1ca | 931 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 932 | |
755d2218 CW |
933 | i915_gem_object_pin_pages(obj); |
934 | ||
673a394b | 935 | offset = args->offset; |
05394f39 | 936 | obj->dirty = 1; |
673a394b | 937 | |
67d5a50c ID |
938 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
939 | offset >> PAGE_SHIFT) { | |
2db76d7c | 940 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 941 | int partial_cacheline_write; |
e5281ccd | 942 | |
9da3da66 CW |
943 | if (remain <= 0) |
944 | break; | |
945 | ||
40123c1f EA |
946 | /* Operation in this page |
947 | * | |
40123c1f | 948 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
949 | * page_length = bytes to copy for this page |
950 | */ | |
c8cbbb8b | 951 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
952 | |
953 | page_length = remain; | |
954 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
955 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 956 | |
58642885 DV |
957 | /* If we don't overwrite a cacheline completely we need to be |
958 | * careful to have up-to-date data by first clflushing. Don't | |
959 | * overcomplicate things and flush the entire patch. */ | |
960 | partial_cacheline_write = needs_clflush_before && | |
961 | ((shmem_page_offset | page_length) | |
962 | & (boot_cpu_data.x86_clflush_size - 1)); | |
963 | ||
8c59967c DV |
964 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
965 | (page_to_phys(page) & (1 << 17)) != 0; | |
966 | ||
d174bd64 DV |
967 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
968 | user_data, page_do_bit17_swizzling, | |
969 | partial_cacheline_write, | |
970 | needs_clflush_after); | |
971 | if (ret == 0) | |
972 | goto next_page; | |
e244a443 DV |
973 | |
974 | hit_slowpath = 1; | |
e244a443 | 975 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
976 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
977 | user_data, page_do_bit17_swizzling, | |
978 | partial_cacheline_write, | |
979 | needs_clflush_after); | |
40123c1f | 980 | |
e244a443 | 981 | mutex_lock(&dev->struct_mutex); |
755d2218 | 982 | |
755d2218 | 983 | if (ret) |
8c59967c | 984 | goto out; |
8c59967c | 985 | |
17793c9a | 986 | next_page: |
40123c1f | 987 | remain -= page_length; |
8c59967c | 988 | user_data += page_length; |
40123c1f | 989 | offset += page_length; |
673a394b EA |
990 | } |
991 | ||
fbd5a26d | 992 | out: |
755d2218 CW |
993 | i915_gem_object_unpin_pages(obj); |
994 | ||
e244a443 | 995 | if (hit_slowpath) { |
8dcf015e DV |
996 | /* |
997 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
998 | * cachelines in-line while writing and the object moved | |
999 | * out of the cpu write domain while we've dropped the lock. | |
1000 | */ | |
1001 | if (!needs_clflush_after && | |
1002 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1003 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1004 | needs_clflush_after = true; |
e244a443 | 1005 | } |
8c59967c | 1006 | } |
673a394b | 1007 | |
58642885 | 1008 | if (needs_clflush_after) |
e76e9aeb | 1009 | i915_gem_chipset_flush(dev); |
ed75a55b VS |
1010 | else |
1011 | obj->cache_dirty = true; | |
58642885 | 1012 | |
de152b62 | 1013 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1014 | return ret; |
673a394b EA |
1015 | } |
1016 | ||
1017 | /** | |
1018 | * Writes data to the object referenced by handle. | |
1019 | * | |
1020 | * On error, the contents of the buffer that were to be modified are undefined. | |
1021 | */ | |
1022 | int | |
1023 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1024 | struct drm_file *file) |
673a394b | 1025 | { |
5d77d9c5 | 1026 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1027 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1028 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1029 | int ret; |
1030 | ||
1031 | if (args->size == 0) | |
1032 | return 0; | |
1033 | ||
1034 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1035 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1036 | args->size)) |
1037 | return -EFAULT; | |
1038 | ||
d330a953 | 1039 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1040 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1041 | args->size); | |
1042 | if (ret) | |
1043 | return -EFAULT; | |
1044 | } | |
673a394b | 1045 | |
5d77d9c5 ID |
1046 | intel_runtime_pm_get(dev_priv); |
1047 | ||
fbd5a26d | 1048 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1049 | if (ret) |
5d77d9c5 | 1050 | goto put_rpm; |
1d7cfea1 | 1051 | |
05394f39 | 1052 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1053 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1054 | ret = -ENOENT; |
1055 | goto unlock; | |
fbd5a26d | 1056 | } |
673a394b | 1057 | |
7dcd2499 | 1058 | /* Bounds check destination. */ |
05394f39 CW |
1059 | if (args->offset > obj->base.size || |
1060 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1061 | ret = -EINVAL; |
35b62a89 | 1062 | goto out; |
ce9d419d CW |
1063 | } |
1064 | ||
1286ff73 DV |
1065 | /* prime objects have no backing filp to GEM pread/pwrite |
1066 | * pages from. | |
1067 | */ | |
1068 | if (!obj->base.filp) { | |
1069 | ret = -EINVAL; | |
1070 | goto out; | |
1071 | } | |
1072 | ||
db53a302 CW |
1073 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1074 | ||
935aaa69 | 1075 | ret = -EFAULT; |
673a394b EA |
1076 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1077 | * it would end up going through the fenced access, and we'll get | |
1078 | * different detiling behavior between reading and writing. | |
1079 | * pread/pwrite currently are reading and writing from the CPU | |
1080 | * perspective, requiring manual detiling by the client. | |
1081 | */ | |
2c22569b CW |
1082 | if (obj->tiling_mode == I915_TILING_NONE && |
1083 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1084 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1085 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1086 | /* Note that the gtt paths might fail with non-page-backed user |
1087 | * pointers (e.g. gtt mappings when moving data between | |
1088 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1089 | } |
673a394b | 1090 | |
6a2c4232 CW |
1091 | if (ret == -EFAULT || ret == -ENOSPC) { |
1092 | if (obj->phys_handle) | |
1093 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1094 | else | |
1095 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1096 | } | |
5c0480f2 | 1097 | |
35b62a89 | 1098 | out: |
05394f39 | 1099 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1100 | unlock: |
fbd5a26d | 1101 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1102 | put_rpm: |
1103 | intel_runtime_pm_put(dev_priv); | |
1104 | ||
673a394b EA |
1105 | return ret; |
1106 | } | |
1107 | ||
f4457ae7 CW |
1108 | static int |
1109 | i915_gem_check_wedge(unsigned reset_counter, bool interruptible) | |
b361237b | 1110 | { |
f4457ae7 CW |
1111 | if (__i915_terminally_wedged(reset_counter)) |
1112 | return -EIO; | |
d98c52cf | 1113 | |
f4457ae7 | 1114 | if (__i915_reset_in_progress(reset_counter)) { |
b361237b CW |
1115 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1116 | * -EIO unconditionally for these. */ | |
1117 | if (!interruptible) | |
1118 | return -EIO; | |
1119 | ||
d98c52cf | 1120 | return -EAGAIN; |
b361237b CW |
1121 | } |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
094f9a54 CW |
1126 | static void fake_irq(unsigned long data) |
1127 | { | |
1128 | wake_up_process((struct task_struct *)data); | |
1129 | } | |
1130 | ||
1131 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
0bc40be8 | 1132 | struct intel_engine_cs *engine) |
094f9a54 | 1133 | { |
0bc40be8 | 1134 | return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings); |
094f9a54 CW |
1135 | } |
1136 | ||
ca5b721e CW |
1137 | static unsigned long local_clock_us(unsigned *cpu) |
1138 | { | |
1139 | unsigned long t; | |
1140 | ||
1141 | /* Cheaply and approximately convert from nanoseconds to microseconds. | |
1142 | * The result and subsequent calculations are also defined in the same | |
1143 | * approximate microseconds units. The principal source of timing | |
1144 | * error here is from the simple truncation. | |
1145 | * | |
1146 | * Note that local_clock() is only defined wrt to the current CPU; | |
1147 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1148 | * blocking preemption for the entire busywait, we can detect the CPU | |
1149 | * switch and use that as indicator of system load and a reason to | |
1150 | * stop busywaiting, see busywait_stop(). | |
1151 | */ | |
1152 | *cpu = get_cpu(); | |
1153 | t = local_clock() >> 10; | |
1154 | put_cpu(); | |
1155 | ||
1156 | return t; | |
1157 | } | |
1158 | ||
1159 | static bool busywait_stop(unsigned long timeout, unsigned cpu) | |
1160 | { | |
1161 | unsigned this_cpu; | |
1162 | ||
1163 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1164 | return true; | |
1165 | ||
1166 | return this_cpu != cpu; | |
1167 | } | |
1168 | ||
91b0c352 | 1169 | static int __i915_spin_request(struct drm_i915_gem_request *req, int state) |
b29c19b6 | 1170 | { |
2def4ad9 | 1171 | unsigned long timeout; |
ca5b721e CW |
1172 | unsigned cpu; |
1173 | ||
1174 | /* When waiting for high frequency requests, e.g. during synchronous | |
1175 | * rendering split between the CPU and GPU, the finite amount of time | |
1176 | * required to set up the irq and wait upon it limits the response | |
1177 | * rate. By busywaiting on the request completion for a short while we | |
1178 | * can service the high frequency waits as quick as possible. However, | |
1179 | * if it is a slow request, we want to sleep as quickly as possible. | |
1180 | * The tradeoff between waiting and sleeping is roughly the time it | |
1181 | * takes to sleep on a request, on the order of a microsecond. | |
1182 | */ | |
2def4ad9 | 1183 | |
4a570db5 | 1184 | if (req->engine->irq_refcount) |
2def4ad9 CW |
1185 | return -EBUSY; |
1186 | ||
821485dc CW |
1187 | /* Only spin if we know the GPU is processing this request */ |
1188 | if (!i915_gem_request_started(req, true)) | |
1189 | return -EAGAIN; | |
1190 | ||
ca5b721e | 1191 | timeout = local_clock_us(&cpu) + 5; |
2def4ad9 | 1192 | while (!need_resched()) { |
eed29a5b | 1193 | if (i915_gem_request_completed(req, true)) |
2def4ad9 CW |
1194 | return 0; |
1195 | ||
91b0c352 CW |
1196 | if (signal_pending_state(state, current)) |
1197 | break; | |
1198 | ||
ca5b721e | 1199 | if (busywait_stop(timeout, cpu)) |
2def4ad9 | 1200 | break; |
b29c19b6 | 1201 | |
2def4ad9 CW |
1202 | cpu_relax_lowlatency(); |
1203 | } | |
821485dc | 1204 | |
eed29a5b | 1205 | if (i915_gem_request_completed(req, false)) |
2def4ad9 CW |
1206 | return 0; |
1207 | ||
1208 | return -EAGAIN; | |
b29c19b6 CW |
1209 | } |
1210 | ||
b361237b | 1211 | /** |
9c654818 JH |
1212 | * __i915_wait_request - wait until execution of request has finished |
1213 | * @req: duh! | |
b361237b CW |
1214 | * @interruptible: do an interruptible wait (normally yes) |
1215 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1216 | * | |
f69061be DV |
1217 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1218 | * values have been read by the caller in an smp safe manner. Where read-side | |
1219 | * locks are involved, it is sufficient to read the reset_counter before | |
1220 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1221 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1222 | * inserted. | |
1223 | * | |
9c654818 | 1224 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1225 | * errno with remaining time filled in timeout argument. |
1226 | */ | |
9c654818 | 1227 | int __i915_wait_request(struct drm_i915_gem_request *req, |
b29c19b6 | 1228 | bool interruptible, |
5ed0bdf2 | 1229 | s64 *timeout, |
2e1b8730 | 1230 | struct intel_rps_client *rps) |
b361237b | 1231 | { |
666796da | 1232 | struct intel_engine_cs *engine = i915_gem_request_get_engine(req); |
e2f80391 | 1233 | struct drm_device *dev = engine->dev; |
3e31c6c0 | 1234 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 | 1235 | const bool irq_test_in_progress = |
666796da | 1236 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine); |
91b0c352 | 1237 | int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; |
094f9a54 | 1238 | DEFINE_WAIT(wait); |
47e9766d | 1239 | unsigned long timeout_expire; |
e0313db0 | 1240 | s64 before = 0; /* Only to silence a compiler warning. */ |
b361237b CW |
1241 | int ret; |
1242 | ||
9df7575f | 1243 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1244 | |
b4716185 CW |
1245 | if (list_empty(&req->list)) |
1246 | return 0; | |
1247 | ||
1b5a433a | 1248 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1249 | return 0; |
1250 | ||
bb6d1984 CW |
1251 | timeout_expire = 0; |
1252 | if (timeout) { | |
1253 | if (WARN_ON(*timeout < 0)) | |
1254 | return -EINVAL; | |
1255 | ||
1256 | if (*timeout == 0) | |
1257 | return -ETIME; | |
1258 | ||
1259 | timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout); | |
e0313db0 TU |
1260 | |
1261 | /* | |
1262 | * Record current time in case interrupted by signal, or wedged. | |
1263 | */ | |
1264 | before = ktime_get_raw_ns(); | |
bb6d1984 | 1265 | } |
b361237b | 1266 | |
2e1b8730 | 1267 | if (INTEL_INFO(dev_priv)->gen >= 6) |
e61b9958 | 1268 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
b361237b | 1269 | |
74328ee5 | 1270 | trace_i915_gem_request_wait_begin(req); |
2def4ad9 CW |
1271 | |
1272 | /* Optimistic spin for the next jiffie before touching IRQs */ | |
91b0c352 | 1273 | ret = __i915_spin_request(req, state); |
2def4ad9 CW |
1274 | if (ret == 0) |
1275 | goto out; | |
1276 | ||
e2f80391 | 1277 | if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) { |
2def4ad9 CW |
1278 | ret = -ENODEV; |
1279 | goto out; | |
1280 | } | |
1281 | ||
094f9a54 CW |
1282 | for (;;) { |
1283 | struct timer_list timer; | |
b361237b | 1284 | |
e2f80391 | 1285 | prepare_to_wait(&engine->irq_queue, &wait, state); |
b361237b | 1286 | |
f69061be | 1287 | /* We need to check whether any gpu reset happened in between |
f4457ae7 CW |
1288 | * the request being submitted and now. If a reset has occurred, |
1289 | * the request is effectively complete (we either are in the | |
1290 | * process of or have discarded the rendering and completely | |
1291 | * reset the GPU. The results of the request are lost and we | |
1292 | * are free to continue on with the original operation. | |
1293 | */ | |
299259a3 | 1294 | if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) { |
f4457ae7 | 1295 | ret = 0; |
094f9a54 CW |
1296 | break; |
1297 | } | |
f69061be | 1298 | |
1b5a433a | 1299 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1300 | ret = 0; |
1301 | break; | |
1302 | } | |
b361237b | 1303 | |
91b0c352 | 1304 | if (signal_pending_state(state, current)) { |
094f9a54 CW |
1305 | ret = -ERESTARTSYS; |
1306 | break; | |
1307 | } | |
1308 | ||
47e9766d | 1309 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1310 | ret = -ETIME; |
1311 | break; | |
1312 | } | |
1313 | ||
1314 | timer.function = NULL; | |
e2f80391 | 1315 | if (timeout || missed_irq(dev_priv, engine)) { |
47e9766d MK |
1316 | unsigned long expire; |
1317 | ||
094f9a54 | 1318 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
e2f80391 | 1319 | expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1320 | mod_timer(&timer, expire); |
1321 | } | |
1322 | ||
5035c275 | 1323 | io_schedule(); |
094f9a54 | 1324 | |
094f9a54 CW |
1325 | if (timer.function) { |
1326 | del_singleshot_timer_sync(&timer); | |
1327 | destroy_timer_on_stack(&timer); | |
1328 | } | |
1329 | } | |
168c3f21 | 1330 | if (!irq_test_in_progress) |
e2f80391 | 1331 | engine->irq_put(engine); |
094f9a54 | 1332 | |
e2f80391 | 1333 | finish_wait(&engine->irq_queue, &wait); |
b361237b | 1334 | |
2def4ad9 | 1335 | out: |
2def4ad9 CW |
1336 | trace_i915_gem_request_wait_end(req); |
1337 | ||
b361237b | 1338 | if (timeout) { |
e0313db0 | 1339 | s64 tres = *timeout - (ktime_get_raw_ns() - before); |
5ed0bdf2 TG |
1340 | |
1341 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1342 | |
1343 | /* | |
1344 | * Apparently ktime isn't accurate enough and occasionally has a | |
1345 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1346 | * things up to make the test happy. We allow up to 1 jiffy. | |
1347 | * | |
1348 | * This is a regrssion from the timespec->ktime conversion. | |
1349 | */ | |
1350 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1351 | *timeout = 0; | |
b361237b CW |
1352 | } |
1353 | ||
094f9a54 | 1354 | return ret; |
b361237b CW |
1355 | } |
1356 | ||
fcfa423c JH |
1357 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
1358 | struct drm_file *file) | |
1359 | { | |
fcfa423c JH |
1360 | struct drm_i915_file_private *file_priv; |
1361 | ||
1362 | WARN_ON(!req || !file || req->file_priv); | |
1363 | ||
1364 | if (!req || !file) | |
1365 | return -EINVAL; | |
1366 | ||
1367 | if (req->file_priv) | |
1368 | return -EINVAL; | |
1369 | ||
fcfa423c JH |
1370 | file_priv = file->driver_priv; |
1371 | ||
1372 | spin_lock(&file_priv->mm.lock); | |
1373 | req->file_priv = file_priv; | |
1374 | list_add_tail(&req->client_list, &file_priv->mm.request_list); | |
1375 | spin_unlock(&file_priv->mm.lock); | |
1376 | ||
1377 | req->pid = get_pid(task_pid(current)); | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
b4716185 CW |
1382 | static inline void |
1383 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
1384 | { | |
1385 | struct drm_i915_file_private *file_priv = request->file_priv; | |
1386 | ||
1387 | if (!file_priv) | |
1388 | return; | |
1389 | ||
1390 | spin_lock(&file_priv->mm.lock); | |
1391 | list_del(&request->client_list); | |
1392 | request->file_priv = NULL; | |
1393 | spin_unlock(&file_priv->mm.lock); | |
fcfa423c JH |
1394 | |
1395 | put_pid(request->pid); | |
1396 | request->pid = NULL; | |
b4716185 CW |
1397 | } |
1398 | ||
1399 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) | |
1400 | { | |
1401 | trace_i915_gem_request_retire(request); | |
1402 | ||
1403 | /* We know the GPU must have read the request to have | |
1404 | * sent us the seqno + interrupt, so use the position | |
1405 | * of tail of the request to update the last known position | |
1406 | * of the GPU head. | |
1407 | * | |
1408 | * Note this requires that we are always called in request | |
1409 | * completion order. | |
1410 | */ | |
1411 | request->ringbuf->last_retired_head = request->postfix; | |
1412 | ||
1413 | list_del_init(&request->list); | |
1414 | i915_gem_request_remove_from_client(request); | |
1415 | ||
b4716185 CW |
1416 | i915_gem_request_unreference(request); |
1417 | } | |
1418 | ||
1419 | static void | |
1420 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) | |
1421 | { | |
4a570db5 | 1422 | struct intel_engine_cs *engine = req->engine; |
b4716185 CW |
1423 | struct drm_i915_gem_request *tmp; |
1424 | ||
1425 | lockdep_assert_held(&engine->dev->struct_mutex); | |
1426 | ||
1427 | if (list_empty(&req->list)) | |
1428 | return; | |
1429 | ||
1430 | do { | |
1431 | tmp = list_first_entry(&engine->request_list, | |
1432 | typeof(*tmp), list); | |
1433 | ||
1434 | i915_gem_request_retire(tmp); | |
1435 | } while (tmp != req); | |
1436 | ||
1437 | WARN_ON(i915_verify_lists(engine->dev)); | |
1438 | } | |
1439 | ||
b361237b | 1440 | /** |
a4b3a571 | 1441 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1442 | * request and object lists appropriately for that event. |
1443 | */ | |
1444 | int | |
a4b3a571 | 1445 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1446 | { |
a4b3a571 DV |
1447 | struct drm_device *dev; |
1448 | struct drm_i915_private *dev_priv; | |
1449 | bool interruptible; | |
b361237b CW |
1450 | int ret; |
1451 | ||
a4b3a571 DV |
1452 | BUG_ON(req == NULL); |
1453 | ||
4a570db5 | 1454 | dev = req->engine->dev; |
a4b3a571 DV |
1455 | dev_priv = dev->dev_private; |
1456 | interruptible = dev_priv->mm.interruptible; | |
1457 | ||
b361237b | 1458 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1459 | |
299259a3 | 1460 | ret = __i915_wait_request(req, interruptible, NULL, NULL); |
b4716185 CW |
1461 | if (ret) |
1462 | return ret; | |
d26e3af8 | 1463 | |
b4716185 | 1464 | __i915_gem_request_retire__upto(req); |
d26e3af8 CW |
1465 | return 0; |
1466 | } | |
1467 | ||
b361237b CW |
1468 | /** |
1469 | * Ensures that all rendering to the object has completed and the object is | |
1470 | * safe to unbind from the GTT or access from the CPU. | |
1471 | */ | |
2e2f351d | 1472 | int |
b361237b CW |
1473 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1474 | bool readonly) | |
1475 | { | |
b4716185 | 1476 | int ret, i; |
b361237b | 1477 | |
b4716185 | 1478 | if (!obj->active) |
b361237b CW |
1479 | return 0; |
1480 | ||
b4716185 CW |
1481 | if (readonly) { |
1482 | if (obj->last_write_req != NULL) { | |
1483 | ret = i915_wait_request(obj->last_write_req); | |
1484 | if (ret) | |
1485 | return ret; | |
b361237b | 1486 | |
4a570db5 | 1487 | i = obj->last_write_req->engine->id; |
b4716185 CW |
1488 | if (obj->last_read_req[i] == obj->last_write_req) |
1489 | i915_gem_object_retire__read(obj, i); | |
1490 | else | |
1491 | i915_gem_object_retire__write(obj); | |
1492 | } | |
1493 | } else { | |
666796da | 1494 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1495 | if (obj->last_read_req[i] == NULL) |
1496 | continue; | |
1497 | ||
1498 | ret = i915_wait_request(obj->last_read_req[i]); | |
1499 | if (ret) | |
1500 | return ret; | |
1501 | ||
1502 | i915_gem_object_retire__read(obj, i); | |
1503 | } | |
d501b1d2 | 1504 | GEM_BUG_ON(obj->active); |
b4716185 CW |
1505 | } |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
1510 | static void | |
1511 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, | |
1512 | struct drm_i915_gem_request *req) | |
1513 | { | |
4a570db5 | 1514 | int ring = req->engine->id; |
b4716185 CW |
1515 | |
1516 | if (obj->last_read_req[ring] == req) | |
1517 | i915_gem_object_retire__read(obj, ring); | |
1518 | else if (obj->last_write_req == req) | |
1519 | i915_gem_object_retire__write(obj); | |
1520 | ||
1521 | __i915_gem_request_retire__upto(req); | |
b361237b CW |
1522 | } |
1523 | ||
3236f57a CW |
1524 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1525 | * as the object state may change during this call. | |
1526 | */ | |
1527 | static __must_check int | |
1528 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
2e1b8730 | 1529 | struct intel_rps_client *rps, |
3236f57a CW |
1530 | bool readonly) |
1531 | { | |
1532 | struct drm_device *dev = obj->base.dev; | |
1533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
666796da | 1534 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
b4716185 | 1535 | int ret, i, n = 0; |
3236f57a CW |
1536 | |
1537 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1538 | BUG_ON(!dev_priv->mm.interruptible); | |
1539 | ||
b4716185 | 1540 | if (!obj->active) |
3236f57a CW |
1541 | return 0; |
1542 | ||
b4716185 CW |
1543 | if (readonly) { |
1544 | struct drm_i915_gem_request *req; | |
1545 | ||
1546 | req = obj->last_write_req; | |
1547 | if (req == NULL) | |
1548 | return 0; | |
1549 | ||
b4716185 CW |
1550 | requests[n++] = i915_gem_request_reference(req); |
1551 | } else { | |
666796da | 1552 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1553 | struct drm_i915_gem_request *req; |
1554 | ||
1555 | req = obj->last_read_req[i]; | |
1556 | if (req == NULL) | |
1557 | continue; | |
1558 | ||
b4716185 CW |
1559 | requests[n++] = i915_gem_request_reference(req); |
1560 | } | |
1561 | } | |
1562 | ||
3236f57a | 1563 | mutex_unlock(&dev->struct_mutex); |
299259a3 | 1564 | ret = 0; |
b4716185 | 1565 | for (i = 0; ret == 0 && i < n; i++) |
299259a3 | 1566 | ret = __i915_wait_request(requests[i], true, NULL, rps); |
3236f57a CW |
1567 | mutex_lock(&dev->struct_mutex); |
1568 | ||
b4716185 CW |
1569 | for (i = 0; i < n; i++) { |
1570 | if (ret == 0) | |
1571 | i915_gem_object_retire_request(obj, requests[i]); | |
1572 | i915_gem_request_unreference(requests[i]); | |
1573 | } | |
1574 | ||
1575 | return ret; | |
3236f57a CW |
1576 | } |
1577 | ||
2e1b8730 CW |
1578 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
1579 | { | |
1580 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1581 | return &fpriv->rps; | |
1582 | } | |
1583 | ||
673a394b | 1584 | /** |
2ef7eeaa EA |
1585 | * Called when user space prepares to use an object with the CPU, either |
1586 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1587 | */ |
1588 | int | |
1589 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1590 | struct drm_file *file) |
673a394b EA |
1591 | { |
1592 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1593 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1594 | uint32_t read_domains = args->read_domains; |
1595 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1596 | int ret; |
1597 | ||
2ef7eeaa | 1598 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1599 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1600 | return -EINVAL; |
1601 | ||
21d509e3 | 1602 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1603 | return -EINVAL; |
1604 | ||
1605 | /* Having something in the write domain implies it's in the read | |
1606 | * domain, and only that read domain. Enforce that in the request. | |
1607 | */ | |
1608 | if (write_domain != 0 && read_domains != write_domain) | |
1609 | return -EINVAL; | |
1610 | ||
76c1dec1 | 1611 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1612 | if (ret) |
76c1dec1 | 1613 | return ret; |
1d7cfea1 | 1614 | |
05394f39 | 1615 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1616 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1617 | ret = -ENOENT; |
1618 | goto unlock; | |
76c1dec1 | 1619 | } |
673a394b | 1620 | |
3236f57a CW |
1621 | /* Try to flush the object off the GPU without holding the lock. |
1622 | * We will repeat the flush holding the lock in the normal manner | |
1623 | * to catch cases where we are gazumped. | |
1624 | */ | |
6e4930f6 | 1625 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
2e1b8730 | 1626 | to_rps_client(file), |
6e4930f6 | 1627 | !write_domain); |
3236f57a CW |
1628 | if (ret) |
1629 | goto unref; | |
1630 | ||
43566ded | 1631 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1632 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1633 | else |
e47c68e9 | 1634 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1635 | |
031b698a DV |
1636 | if (write_domain != 0) |
1637 | intel_fb_obj_invalidate(obj, | |
1638 | write_domain == I915_GEM_DOMAIN_GTT ? | |
1639 | ORIGIN_GTT : ORIGIN_CPU); | |
1640 | ||
3236f57a | 1641 | unref: |
05394f39 | 1642 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1643 | unlock: |
673a394b EA |
1644 | mutex_unlock(&dev->struct_mutex); |
1645 | return ret; | |
1646 | } | |
1647 | ||
1648 | /** | |
1649 | * Called when user space has done writes to this buffer | |
1650 | */ | |
1651 | int | |
1652 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1653 | struct drm_file *file) |
673a394b EA |
1654 | { |
1655 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1656 | struct drm_i915_gem_object *obj; |
673a394b EA |
1657 | int ret = 0; |
1658 | ||
76c1dec1 | 1659 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1660 | if (ret) |
76c1dec1 | 1661 | return ret; |
1d7cfea1 | 1662 | |
05394f39 | 1663 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1664 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1665 | ret = -ENOENT; |
1666 | goto unlock; | |
673a394b EA |
1667 | } |
1668 | ||
673a394b | 1669 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1670 | if (obj->pin_display) |
e62b59e4 | 1671 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1672 | |
05394f39 | 1673 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1674 | unlock: |
673a394b EA |
1675 | mutex_unlock(&dev->struct_mutex); |
1676 | return ret; | |
1677 | } | |
1678 | ||
1679 | /** | |
1680 | * Maps the contents of an object, returning the address it is mapped | |
1681 | * into. | |
1682 | * | |
1683 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1684 | * imply a ref on the object itself. | |
34367381 DV |
1685 | * |
1686 | * IMPORTANT: | |
1687 | * | |
1688 | * DRM driver writers who look a this function as an example for how to do GEM | |
1689 | * mmap support, please don't implement mmap support like here. The modern way | |
1690 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1691 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1692 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1693 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1694 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1695 | */ |
1696 | int | |
1697 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1698 | struct drm_file *file) |
673a394b EA |
1699 | { |
1700 | struct drm_i915_gem_mmap *args = data; | |
1701 | struct drm_gem_object *obj; | |
673a394b EA |
1702 | unsigned long addr; |
1703 | ||
1816f923 AG |
1704 | if (args->flags & ~(I915_MMAP_WC)) |
1705 | return -EINVAL; | |
1706 | ||
1707 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) | |
1708 | return -ENODEV; | |
1709 | ||
05394f39 | 1710 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1711 | if (obj == NULL) |
bf79cb91 | 1712 | return -ENOENT; |
673a394b | 1713 | |
1286ff73 DV |
1714 | /* prime objects have no backing filp to GEM mmap |
1715 | * pages from. | |
1716 | */ | |
1717 | if (!obj->filp) { | |
1718 | drm_gem_object_unreference_unlocked(obj); | |
1719 | return -EINVAL; | |
1720 | } | |
1721 | ||
6be5ceb0 | 1722 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1723 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1724 | args->offset); | |
1816f923 AG |
1725 | if (args->flags & I915_MMAP_WC) { |
1726 | struct mm_struct *mm = current->mm; | |
1727 | struct vm_area_struct *vma; | |
1728 | ||
1729 | down_write(&mm->mmap_sem); | |
1730 | vma = find_vma(mm, addr); | |
1731 | if (vma) | |
1732 | vma->vm_page_prot = | |
1733 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1734 | else | |
1735 | addr = -ENOMEM; | |
1736 | up_write(&mm->mmap_sem); | |
1737 | } | |
bc9025bd | 1738 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1739 | if (IS_ERR((void *)addr)) |
1740 | return addr; | |
1741 | ||
1742 | args->addr_ptr = (uint64_t) addr; | |
1743 | ||
1744 | return 0; | |
1745 | } | |
1746 | ||
de151cf6 JB |
1747 | /** |
1748 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
1749 | * @vma: VMA in question |
1750 | * @vmf: fault info | |
de151cf6 JB |
1751 | * |
1752 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1753 | * from userspace. The fault handler takes care of binding the object to | |
1754 | * the GTT (if needed), allocating and programming a fence register (again, | |
1755 | * only if needed based on whether the old reg is still valid or the object | |
1756 | * is tiled) and inserting a new PTE into the faulting process. | |
1757 | * | |
1758 | * Note that the faulting process may involve evicting existing objects | |
1759 | * from the GTT and/or fence registers to make room. So performance may | |
1760 | * suffer if the GTT working set is large or there are few fence registers | |
1761 | * left. | |
1762 | */ | |
1763 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1764 | { | |
05394f39 CW |
1765 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1766 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
1767 | struct drm_i915_private *dev_priv = to_i915(dev); |
1768 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
c5ad54cf | 1769 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
de151cf6 JB |
1770 | pgoff_t page_offset; |
1771 | unsigned long pfn; | |
1772 | int ret = 0; | |
0f973f27 | 1773 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1774 | |
f65c9168 PZ |
1775 | intel_runtime_pm_get(dev_priv); |
1776 | ||
de151cf6 JB |
1777 | /* We don't use vmf->pgoff since that has the fake offset */ |
1778 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1779 | PAGE_SHIFT; | |
1780 | ||
d9bc7e9f CW |
1781 | ret = i915_mutex_lock_interruptible(dev); |
1782 | if (ret) | |
1783 | goto out; | |
a00b10c3 | 1784 | |
db53a302 CW |
1785 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1786 | ||
6e4930f6 CW |
1787 | /* Try to flush the object off the GPU first without holding the lock. |
1788 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1789 | * repeat the flush holding the lock in the normal manner to catch cases | |
1790 | * where we are gazumped. | |
1791 | */ | |
1792 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1793 | if (ret) | |
1794 | goto unlock; | |
1795 | ||
eb119bd6 CW |
1796 | /* Access to snoopable pages through the GTT is incoherent. */ |
1797 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1798 | ret = -EFAULT; |
eb119bd6 CW |
1799 | goto unlock; |
1800 | } | |
1801 | ||
c5ad54cf | 1802 | /* Use a partial view if the object is bigger than the aperture. */ |
72e96d64 | 1803 | if (obj->base.size >= ggtt->mappable_end && |
e7ded2d7 | 1804 | obj->tiling_mode == I915_TILING_NONE) { |
c5ad54cf | 1805 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1806 | |
c5ad54cf JL |
1807 | memset(&view, 0, sizeof(view)); |
1808 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1809 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1810 | view.params.partial.size = | |
1811 | min_t(unsigned int, | |
1812 | chunk_size, | |
1813 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1814 | view.params.partial.offset); | |
1815 | } | |
1816 | ||
1817 | /* Now pin it into the GTT if needed */ | |
1818 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); | |
c9839303 CW |
1819 | if (ret) |
1820 | goto unlock; | |
4a684a41 | 1821 | |
c9839303 CW |
1822 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1823 | if (ret) | |
1824 | goto unpin; | |
74898d7e | 1825 | |
06d98131 | 1826 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1827 | if (ret) |
c9839303 | 1828 | goto unpin; |
7d1c4804 | 1829 | |
b90b91d8 | 1830 | /* Finally, remap it using the new GTT offset */ |
72e96d64 | 1831 | pfn = ggtt->mappable_base + |
c5ad54cf | 1832 | i915_gem_obj_ggtt_offset_view(obj, &view); |
f343c5f6 | 1833 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1834 | |
c5ad54cf JL |
1835 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1836 | /* Overriding existing pages in partial view does not cause | |
1837 | * us any trouble as TLBs are still valid because the fault | |
1838 | * is due to userspace losing part of the mapping or never | |
1839 | * having accessed it before (at this partials' range). | |
1840 | */ | |
1841 | unsigned long base = vma->vm_start + | |
1842 | (view.params.partial.offset << PAGE_SHIFT); | |
1843 | unsigned int i; | |
b90b91d8 | 1844 | |
c5ad54cf JL |
1845 | for (i = 0; i < view.params.partial.size; i++) { |
1846 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1847 | if (ret) |
1848 | break; | |
1849 | } | |
1850 | ||
1851 | obj->fault_mappable = true; | |
c5ad54cf JL |
1852 | } else { |
1853 | if (!obj->fault_mappable) { | |
1854 | unsigned long size = min_t(unsigned long, | |
1855 | vma->vm_end - vma->vm_start, | |
1856 | obj->base.size); | |
1857 | int i; | |
1858 | ||
1859 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1860 | ret = vm_insert_pfn(vma, | |
1861 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1862 | pfn + i); | |
1863 | if (ret) | |
1864 | break; | |
1865 | } | |
1866 | ||
1867 | obj->fault_mappable = true; | |
1868 | } else | |
1869 | ret = vm_insert_pfn(vma, | |
1870 | (unsigned long)vmf->virtual_address, | |
1871 | pfn + page_offset); | |
1872 | } | |
c9839303 | 1873 | unpin: |
c5ad54cf | 1874 | i915_gem_object_ggtt_unpin_view(obj, &view); |
c715089f | 1875 | unlock: |
de151cf6 | 1876 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1877 | out: |
de151cf6 | 1878 | switch (ret) { |
d9bc7e9f | 1879 | case -EIO: |
2232f031 DV |
1880 | /* |
1881 | * We eat errors when the gpu is terminally wedged to avoid | |
1882 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1883 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1884 | * and so needs to be reported. | |
1885 | */ | |
1886 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1887 | ret = VM_FAULT_SIGBUS; |
1888 | break; | |
1889 | } | |
045e769a | 1890 | case -EAGAIN: |
571c608d DV |
1891 | /* |
1892 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1893 | * handler to reset everything when re-faulting in | |
1894 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1895 | */ |
c715089f CW |
1896 | case 0: |
1897 | case -ERESTARTSYS: | |
bed636ab | 1898 | case -EINTR: |
e79e0fe3 DR |
1899 | case -EBUSY: |
1900 | /* | |
1901 | * EBUSY is ok: this just means that another thread | |
1902 | * already did the job. | |
1903 | */ | |
f65c9168 PZ |
1904 | ret = VM_FAULT_NOPAGE; |
1905 | break; | |
de151cf6 | 1906 | case -ENOMEM: |
f65c9168 PZ |
1907 | ret = VM_FAULT_OOM; |
1908 | break; | |
a7c2e1aa | 1909 | case -ENOSPC: |
45d67817 | 1910 | case -EFAULT: |
f65c9168 PZ |
1911 | ret = VM_FAULT_SIGBUS; |
1912 | break; | |
de151cf6 | 1913 | default: |
a7c2e1aa | 1914 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1915 | ret = VM_FAULT_SIGBUS; |
1916 | break; | |
de151cf6 | 1917 | } |
f65c9168 PZ |
1918 | |
1919 | intel_runtime_pm_put(dev_priv); | |
1920 | return ret; | |
de151cf6 JB |
1921 | } |
1922 | ||
901782b2 CW |
1923 | /** |
1924 | * i915_gem_release_mmap - remove physical page mappings | |
1925 | * @obj: obj in question | |
1926 | * | |
af901ca1 | 1927 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1928 | * relinquish ownership of the pages back to the system. |
1929 | * | |
1930 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1931 | * object through the GTT and then lose the fence register due to | |
1932 | * resource pressure. Similarly if the object has been moved out of the | |
1933 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1934 | * mapping will then trigger a page fault on the next user access, allowing | |
1935 | * fixup by i915_gem_fault(). | |
1936 | */ | |
d05ca301 | 1937 | void |
05394f39 | 1938 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1939 | { |
349f2ccf CW |
1940 | /* Serialisation between user GTT access and our code depends upon |
1941 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1942 | * pagefault then has to wait until we release the mutex. | |
1943 | */ | |
1944 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
1945 | ||
6299f992 CW |
1946 | if (!obj->fault_mappable) |
1947 | return; | |
901782b2 | 1948 | |
6796cb16 DH |
1949 | drm_vma_node_unmap(&obj->base.vma_node, |
1950 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1951 | |
1952 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1953 | * memory transactions from userspace before we return. The TLB | |
1954 | * flushing implied above by changing the PTE above *should* be | |
1955 | * sufficient, an extra barrier here just provides us with a bit | |
1956 | * of paranoid documentation about our requirement to serialise | |
1957 | * memory writes before touching registers / GSM. | |
1958 | */ | |
1959 | wmb(); | |
1960 | ||
6299f992 | 1961 | obj->fault_mappable = false; |
901782b2 CW |
1962 | } |
1963 | ||
eedd10f4 CW |
1964 | void |
1965 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1966 | { | |
1967 | struct drm_i915_gem_object *obj; | |
1968 | ||
1969 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1970 | i915_gem_release_mmap(obj); | |
1971 | } | |
1972 | ||
0fa87796 | 1973 | uint32_t |
e28f8711 | 1974 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1975 | { |
e28f8711 | 1976 | uint32_t gtt_size; |
92b88aeb CW |
1977 | |
1978 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1979 | tiling_mode == I915_TILING_NONE) |
1980 | return size; | |
92b88aeb CW |
1981 | |
1982 | /* Previous chips need a power-of-two fence region when tiling */ | |
1983 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1984 | gtt_size = 1024*1024; |
92b88aeb | 1985 | else |
e28f8711 | 1986 | gtt_size = 512*1024; |
92b88aeb | 1987 | |
e28f8711 CW |
1988 | while (gtt_size < size) |
1989 | gtt_size <<= 1; | |
92b88aeb | 1990 | |
e28f8711 | 1991 | return gtt_size; |
92b88aeb CW |
1992 | } |
1993 | ||
de151cf6 JB |
1994 | /** |
1995 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1996 | * @obj: object to check | |
1997 | * | |
1998 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1999 | * potential fence register mapping. |
de151cf6 | 2000 | */ |
d865110c ID |
2001 | uint32_t |
2002 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
2003 | int tiling_mode, bool fenced) | |
de151cf6 | 2004 | { |
de151cf6 JB |
2005 | /* |
2006 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2007 | * if a fence register is needed for the object. | |
2008 | */ | |
d865110c | 2009 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 2010 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2011 | return 4096; |
2012 | ||
a00b10c3 CW |
2013 | /* |
2014 | * Previous chips need to be aligned to the size of the smallest | |
2015 | * fence register that can contain the object. | |
2016 | */ | |
e28f8711 | 2017 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
2018 | } |
2019 | ||
d8cb5086 CW |
2020 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2021 | { | |
2022 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2023 | int ret; | |
2024 | ||
0de23977 | 2025 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
2026 | return 0; |
2027 | ||
da494d7c DV |
2028 | dev_priv->mm.shrinker_no_lock_stealing = true; |
2029 | ||
d8cb5086 CW |
2030 | ret = drm_gem_create_mmap_offset(&obj->base); |
2031 | if (ret != -ENOSPC) | |
da494d7c | 2032 | goto out; |
d8cb5086 CW |
2033 | |
2034 | /* Badly fragmented mmap space? The only way we can recover | |
2035 | * space is by destroying unwanted objects. We can't randomly release | |
2036 | * mmap_offsets as userspace expects them to be persistent for the | |
2037 | * lifetime of the objects. The closest we can is to release the | |
2038 | * offsets on purgeable objects by truncating it and marking it purged, | |
2039 | * which prevents userspace from ever using that object again. | |
2040 | */ | |
21ab4e74 CW |
2041 | i915_gem_shrink(dev_priv, |
2042 | obj->base.size >> PAGE_SHIFT, | |
2043 | I915_SHRINK_BOUND | | |
2044 | I915_SHRINK_UNBOUND | | |
2045 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
2046 | ret = drm_gem_create_mmap_offset(&obj->base); |
2047 | if (ret != -ENOSPC) | |
da494d7c | 2048 | goto out; |
d8cb5086 CW |
2049 | |
2050 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
2051 | ret = drm_gem_create_mmap_offset(&obj->base); |
2052 | out: | |
2053 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
2054 | ||
2055 | return ret; | |
d8cb5086 CW |
2056 | } |
2057 | ||
2058 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2059 | { | |
d8cb5086 CW |
2060 | drm_gem_free_mmap_offset(&obj->base); |
2061 | } | |
2062 | ||
da6b51d0 | 2063 | int |
ff72145b DA |
2064 | i915_gem_mmap_gtt(struct drm_file *file, |
2065 | struct drm_device *dev, | |
da6b51d0 | 2066 | uint32_t handle, |
ff72145b | 2067 | uint64_t *offset) |
de151cf6 | 2068 | { |
05394f39 | 2069 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2070 | int ret; |
2071 | ||
76c1dec1 | 2072 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 2073 | if (ret) |
76c1dec1 | 2074 | return ret; |
de151cf6 | 2075 | |
ff72145b | 2076 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 2077 | if (&obj->base == NULL) { |
1d7cfea1 CW |
2078 | ret = -ENOENT; |
2079 | goto unlock; | |
2080 | } | |
de151cf6 | 2081 | |
05394f39 | 2082 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2083 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 2084 | ret = -EFAULT; |
1d7cfea1 | 2085 | goto out; |
ab18282d CW |
2086 | } |
2087 | ||
d8cb5086 CW |
2088 | ret = i915_gem_object_create_mmap_offset(obj); |
2089 | if (ret) | |
2090 | goto out; | |
de151cf6 | 2091 | |
0de23977 | 2092 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 2093 | |
1d7cfea1 | 2094 | out: |
05394f39 | 2095 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 2096 | unlock: |
de151cf6 | 2097 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 2098 | return ret; |
de151cf6 JB |
2099 | } |
2100 | ||
ff72145b DA |
2101 | /** |
2102 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2103 | * @dev: DRM device | |
2104 | * @data: GTT mapping ioctl data | |
2105 | * @file: GEM object info | |
2106 | * | |
2107 | * Simply returns the fake offset to userspace so it can mmap it. | |
2108 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2109 | * up so we can get faults in the handler above. | |
2110 | * | |
2111 | * The fault handler will take care of binding the object into the GTT | |
2112 | * (since it may have been evicted to make room for something), allocating | |
2113 | * a fence register, and mapping the appropriate aperture address into | |
2114 | * userspace. | |
2115 | */ | |
2116 | int | |
2117 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2118 | struct drm_file *file) | |
2119 | { | |
2120 | struct drm_i915_gem_mmap_gtt *args = data; | |
2121 | ||
da6b51d0 | 2122 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2123 | } |
2124 | ||
225067ee DV |
2125 | /* Immediately discard the backing storage */ |
2126 | static void | |
2127 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2128 | { |
4d6294bf | 2129 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2130 | |
4d6294bf CW |
2131 | if (obj->base.filp == NULL) |
2132 | return; | |
e5281ccd | 2133 | |
225067ee DV |
2134 | /* Our goal here is to return as much of the memory as |
2135 | * is possible back to the system as we are called from OOM. | |
2136 | * To do this we must instruct the shmfs to drop all of its | |
2137 | * backing pages, *now*. | |
2138 | */ | |
5537252b | 2139 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2140 | obj->madv = __I915_MADV_PURGED; |
2141 | } | |
e5281ccd | 2142 | |
5537252b CW |
2143 | /* Try to discard unwanted pages */ |
2144 | static void | |
2145 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2146 | { |
5537252b CW |
2147 | struct address_space *mapping; |
2148 | ||
2149 | switch (obj->madv) { | |
2150 | case I915_MADV_DONTNEED: | |
2151 | i915_gem_object_truncate(obj); | |
2152 | case __I915_MADV_PURGED: | |
2153 | return; | |
2154 | } | |
2155 | ||
2156 | if (obj->base.filp == NULL) | |
2157 | return; | |
2158 | ||
2159 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2160 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2161 | } |
2162 | ||
5cdf5881 | 2163 | static void |
05394f39 | 2164 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2165 | { |
90797e6d ID |
2166 | struct sg_page_iter sg_iter; |
2167 | int ret; | |
1286ff73 | 2168 | |
05394f39 | 2169 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2170 | |
6c085a72 | 2171 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2172 | if (WARN_ON(ret)) { |
6c085a72 CW |
2173 | /* In the event of a disaster, abandon all caches and |
2174 | * hope for the best. | |
2175 | */ | |
2c22569b | 2176 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2177 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2178 | } | |
2179 | ||
e2273302 ID |
2180 | i915_gem_gtt_finish_object(obj); |
2181 | ||
6dacfd2f | 2182 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2183 | i915_gem_object_save_bit_17_swizzle(obj); |
2184 | ||
05394f39 CW |
2185 | if (obj->madv == I915_MADV_DONTNEED) |
2186 | obj->dirty = 0; | |
3ef94daa | 2187 | |
90797e6d | 2188 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 2189 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 2190 | |
05394f39 | 2191 | if (obj->dirty) |
9da3da66 | 2192 | set_page_dirty(page); |
3ef94daa | 2193 | |
05394f39 | 2194 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2195 | mark_page_accessed(page); |
3ef94daa | 2196 | |
09cbfeaf | 2197 | put_page(page); |
3ef94daa | 2198 | } |
05394f39 | 2199 | obj->dirty = 0; |
673a394b | 2200 | |
9da3da66 CW |
2201 | sg_free_table(obj->pages); |
2202 | kfree(obj->pages); | |
37e680a1 | 2203 | } |
6c085a72 | 2204 | |
dd624afd | 2205 | int |
37e680a1 CW |
2206 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2207 | { | |
2208 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2209 | ||
2f745ad3 | 2210 | if (obj->pages == NULL) |
37e680a1 CW |
2211 | return 0; |
2212 | ||
a5570178 CW |
2213 | if (obj->pages_pin_count) |
2214 | return -EBUSY; | |
2215 | ||
9843877d | 2216 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2217 | |
a2165e31 CW |
2218 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2219 | * array, hence protect them from being reaped by removing them from gtt | |
2220 | * lists early. */ | |
35c20a60 | 2221 | list_del(&obj->global_list); |
a2165e31 | 2222 | |
0a798eb9 | 2223 | if (obj->mapping) { |
fb8621d3 CW |
2224 | if (is_vmalloc_addr(obj->mapping)) |
2225 | vunmap(obj->mapping); | |
2226 | else | |
2227 | kunmap(kmap_to_page(obj->mapping)); | |
0a798eb9 CW |
2228 | obj->mapping = NULL; |
2229 | } | |
2230 | ||
37e680a1 | 2231 | ops->put_pages(obj); |
05394f39 | 2232 | obj->pages = NULL; |
37e680a1 | 2233 | |
5537252b | 2234 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2235 | |
2236 | return 0; | |
2237 | } | |
2238 | ||
37e680a1 | 2239 | static int |
6c085a72 | 2240 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2241 | { |
6c085a72 | 2242 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2243 | int page_count, i; |
2244 | struct address_space *mapping; | |
9da3da66 CW |
2245 | struct sg_table *st; |
2246 | struct scatterlist *sg; | |
90797e6d | 2247 | struct sg_page_iter sg_iter; |
e5281ccd | 2248 | struct page *page; |
90797e6d | 2249 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2250 | int ret; |
6c085a72 | 2251 | gfp_t gfp; |
e5281ccd | 2252 | |
6c085a72 CW |
2253 | /* Assert that the object is not currently in any GPU domain. As it |
2254 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2255 | * a GPU cache | |
2256 | */ | |
2257 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2258 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2259 | ||
9da3da66 CW |
2260 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2261 | if (st == NULL) | |
2262 | return -ENOMEM; | |
2263 | ||
05394f39 | 2264 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2265 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2266 | kfree(st); |
e5281ccd | 2267 | return -ENOMEM; |
9da3da66 | 2268 | } |
e5281ccd | 2269 | |
9da3da66 CW |
2270 | /* Get the list of pages out of our struct file. They'll be pinned |
2271 | * at this point until we release them. | |
2272 | * | |
2273 | * Fail silently without starting the shrinker | |
2274 | */ | |
496ad9aa | 2275 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2276 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2277 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2278 | sg = st->sgl; |
2279 | st->nents = 0; | |
2280 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2281 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2282 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2283 | i915_gem_shrink(dev_priv, |
2284 | page_count, | |
2285 | I915_SHRINK_BOUND | | |
2286 | I915_SHRINK_UNBOUND | | |
2287 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2288 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2289 | } | |
2290 | if (IS_ERR(page)) { | |
2291 | /* We've tried hard to allocate the memory by reaping | |
2292 | * our own buffer, now let the real VM do its job and | |
2293 | * go down in flames if truly OOM. | |
2294 | */ | |
6c085a72 | 2295 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2296 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2297 | if (IS_ERR(page)) { |
2298 | ret = PTR_ERR(page); | |
6c085a72 | 2299 | goto err_pages; |
e2273302 | 2300 | } |
6c085a72 | 2301 | } |
426729dc KRW |
2302 | #ifdef CONFIG_SWIOTLB |
2303 | if (swiotlb_nr_tbl()) { | |
2304 | st->nents++; | |
2305 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2306 | sg = sg_next(sg); | |
2307 | continue; | |
2308 | } | |
2309 | #endif | |
90797e6d ID |
2310 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2311 | if (i) | |
2312 | sg = sg_next(sg); | |
2313 | st->nents++; | |
2314 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2315 | } else { | |
2316 | sg->length += PAGE_SIZE; | |
2317 | } | |
2318 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2319 | |
2320 | /* Check that the i965g/gm workaround works. */ | |
2321 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2322 | } |
426729dc KRW |
2323 | #ifdef CONFIG_SWIOTLB |
2324 | if (!swiotlb_nr_tbl()) | |
2325 | #endif | |
2326 | sg_mark_end(sg); | |
74ce6b6c CW |
2327 | obj->pages = st; |
2328 | ||
e2273302 ID |
2329 | ret = i915_gem_gtt_prepare_object(obj); |
2330 | if (ret) | |
2331 | goto err_pages; | |
2332 | ||
6dacfd2f | 2333 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2334 | i915_gem_object_do_bit_17_swizzle(obj); |
2335 | ||
656bfa3a DV |
2336 | if (obj->tiling_mode != I915_TILING_NONE && |
2337 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2338 | i915_gem_object_pin_pages(obj); | |
2339 | ||
e5281ccd CW |
2340 | return 0; |
2341 | ||
2342 | err_pages: | |
90797e6d ID |
2343 | sg_mark_end(sg); |
2344 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
09cbfeaf | 2345 | put_page(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2346 | sg_free_table(st); |
2347 | kfree(st); | |
0820baf3 CW |
2348 | |
2349 | /* shmemfs first checks if there is enough memory to allocate the page | |
2350 | * and reports ENOSPC should there be insufficient, along with the usual | |
2351 | * ENOMEM for a genuine allocation failure. | |
2352 | * | |
2353 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2354 | * space and so want to translate the error from shmemfs back to our | |
2355 | * usual understanding of ENOMEM. | |
2356 | */ | |
e2273302 ID |
2357 | if (ret == -ENOSPC) |
2358 | ret = -ENOMEM; | |
2359 | ||
2360 | return ret; | |
673a394b EA |
2361 | } |
2362 | ||
37e680a1 CW |
2363 | /* Ensure that the associated pages are gathered from the backing storage |
2364 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2365 | * multiple times before they are released by a single call to | |
2366 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2367 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2368 | * or as the object is itself released. | |
2369 | */ | |
2370 | int | |
2371 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2372 | { | |
2373 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2374 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2375 | int ret; | |
2376 | ||
2f745ad3 | 2377 | if (obj->pages) |
37e680a1 CW |
2378 | return 0; |
2379 | ||
43e28f09 | 2380 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2381 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2382 | return -EFAULT; |
43e28f09 CW |
2383 | } |
2384 | ||
a5570178 CW |
2385 | BUG_ON(obj->pages_pin_count); |
2386 | ||
37e680a1 CW |
2387 | ret = ops->get_pages(obj); |
2388 | if (ret) | |
2389 | return ret; | |
2390 | ||
35c20a60 | 2391 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2392 | |
2393 | obj->get_page.sg = obj->pages->sgl; | |
2394 | obj->get_page.last = 0; | |
2395 | ||
37e680a1 | 2396 | return 0; |
673a394b EA |
2397 | } |
2398 | ||
0a798eb9 CW |
2399 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
2400 | { | |
2401 | int ret; | |
2402 | ||
2403 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
2404 | ||
2405 | ret = i915_gem_object_get_pages(obj); | |
2406 | if (ret) | |
2407 | return ERR_PTR(ret); | |
2408 | ||
2409 | i915_gem_object_pin_pages(obj); | |
2410 | ||
2411 | if (obj->mapping == NULL) { | |
0a798eb9 | 2412 | struct page **pages; |
0a798eb9 | 2413 | |
fb8621d3 CW |
2414 | pages = NULL; |
2415 | if (obj->base.size == PAGE_SIZE) | |
2416 | obj->mapping = kmap(sg_page(obj->pages->sgl)); | |
2417 | else | |
2418 | pages = drm_malloc_gfp(obj->base.size >> PAGE_SHIFT, | |
2419 | sizeof(*pages), | |
2420 | GFP_TEMPORARY); | |
0a798eb9 | 2421 | if (pages != NULL) { |
fb8621d3 CW |
2422 | struct sg_page_iter sg_iter; |
2423 | int n; | |
2424 | ||
0a798eb9 CW |
2425 | n = 0; |
2426 | for_each_sg_page(obj->pages->sgl, &sg_iter, | |
2427 | obj->pages->nents, 0) | |
2428 | pages[n++] = sg_page_iter_page(&sg_iter); | |
2429 | ||
2430 | obj->mapping = vmap(pages, n, 0, PAGE_KERNEL); | |
2431 | drm_free_large(pages); | |
2432 | } | |
2433 | if (obj->mapping == NULL) { | |
2434 | i915_gem_object_unpin_pages(obj); | |
2435 | return ERR_PTR(-ENOMEM); | |
2436 | } | |
2437 | } | |
2438 | ||
2439 | return obj->mapping; | |
2440 | } | |
2441 | ||
b4716185 | 2442 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2443 | struct drm_i915_gem_request *req) |
673a394b | 2444 | { |
b4716185 | 2445 | struct drm_i915_gem_object *obj = vma->obj; |
e2f80391 | 2446 | struct intel_engine_cs *engine; |
b2af0376 | 2447 | |
666796da | 2448 | engine = i915_gem_request_get_engine(req); |
673a394b EA |
2449 | |
2450 | /* Add a reference if we're newly entering the active list. */ | |
b4716185 | 2451 | if (obj->active == 0) |
05394f39 | 2452 | drm_gem_object_reference(&obj->base); |
666796da | 2453 | obj->active |= intel_engine_flag(engine); |
e35a41de | 2454 | |
117897f4 | 2455 | list_move_tail(&obj->engine_list[engine->id], &engine->active_list); |
e2f80391 | 2456 | i915_gem_request_assign(&obj->last_read_req[engine->id], req); |
caea7476 | 2457 | |
1c7f4bca | 2458 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
caea7476 CW |
2459 | } |
2460 | ||
b4716185 CW |
2461 | static void |
2462 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) | |
e2d05a8b | 2463 | { |
d501b1d2 CW |
2464 | GEM_BUG_ON(obj->last_write_req == NULL); |
2465 | GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine))); | |
b4716185 CW |
2466 | |
2467 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
de152b62 | 2468 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2469 | } |
2470 | ||
caea7476 | 2471 | static void |
b4716185 | 2472 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
ce44b0ea | 2473 | { |
feb822cf | 2474 | struct i915_vma *vma; |
ce44b0ea | 2475 | |
d501b1d2 CW |
2476 | GEM_BUG_ON(obj->last_read_req[ring] == NULL); |
2477 | GEM_BUG_ON(!(obj->active & (1 << ring))); | |
b4716185 | 2478 | |
117897f4 | 2479 | list_del_init(&obj->engine_list[ring]); |
b4716185 CW |
2480 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
2481 | ||
4a570db5 | 2482 | if (obj->last_write_req && obj->last_write_req->engine->id == ring) |
b4716185 CW |
2483 | i915_gem_object_retire__write(obj); |
2484 | ||
2485 | obj->active &= ~(1 << ring); | |
2486 | if (obj->active) | |
2487 | return; | |
caea7476 | 2488 | |
6c246959 CW |
2489 | /* Bump our place on the bound list to keep it roughly in LRU order |
2490 | * so that we don't steal from recently used but inactive objects | |
2491 | * (unless we are forced to ofc!) | |
2492 | */ | |
2493 | list_move_tail(&obj->global_list, | |
2494 | &to_i915(obj->base.dev)->mm.bound_list); | |
2495 | ||
1c7f4bca CW |
2496 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
2497 | if (!list_empty(&vma->vm_link)) | |
2498 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
feb822cf | 2499 | } |
caea7476 | 2500 | |
97b2a6a1 | 2501 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 | 2502 | drm_gem_object_unreference(&obj->base); |
c8725f3d CW |
2503 | } |
2504 | ||
9d773091 | 2505 | static int |
fca26bb4 | 2506 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2507 | { |
9d773091 | 2508 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2509 | struct intel_engine_cs *engine; |
29dcb570 | 2510 | int ret; |
53d227f2 | 2511 | |
107f27a5 | 2512 | /* Carefully retire all requests without writing to the rings */ |
b4ac5afc | 2513 | for_each_engine(engine, dev_priv) { |
666796da | 2514 | ret = intel_engine_idle(engine); |
107f27a5 CW |
2515 | if (ret) |
2516 | return ret; | |
9d773091 | 2517 | } |
9d773091 | 2518 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2519 | |
2520 | /* Finally reset hw state */ | |
29dcb570 | 2521 | for_each_engine(engine, dev_priv) |
e2f80391 | 2522 | intel_ring_init_seqno(engine, seqno); |
498d2ac1 | 2523 | |
9d773091 | 2524 | return 0; |
53d227f2 DV |
2525 | } |
2526 | ||
fca26bb4 MK |
2527 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2528 | { | |
2529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2530 | int ret; | |
2531 | ||
2532 | if (seqno == 0) | |
2533 | return -EINVAL; | |
2534 | ||
2535 | /* HWS page needs to be set less than what we | |
2536 | * will inject to ring | |
2537 | */ | |
2538 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2539 | if (ret) | |
2540 | return ret; | |
2541 | ||
2542 | /* Carefully set the last_seqno value so that wrap | |
2543 | * detection still works | |
2544 | */ | |
2545 | dev_priv->next_seqno = seqno; | |
2546 | dev_priv->last_seqno = seqno - 1; | |
2547 | if (dev_priv->last_seqno == 0) | |
2548 | dev_priv->last_seqno--; | |
2549 | ||
2550 | return 0; | |
2551 | } | |
2552 | ||
9d773091 CW |
2553 | int |
2554 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2555 | { |
9d773091 CW |
2556 | struct drm_i915_private *dev_priv = dev->dev_private; |
2557 | ||
2558 | /* reserve 0 for non-seqno */ | |
2559 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2560 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2561 | if (ret) |
2562 | return ret; | |
53d227f2 | 2563 | |
9d773091 CW |
2564 | dev_priv->next_seqno = 1; |
2565 | } | |
53d227f2 | 2566 | |
f72b3435 | 2567 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2568 | return 0; |
53d227f2 DV |
2569 | } |
2570 | ||
bf7dc5b7 JH |
2571 | /* |
2572 | * NB: This function is not allowed to fail. Doing so would mean the the | |
2573 | * request is not being tracked for completion but the work itself is | |
2574 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
2575 | */ | |
75289874 | 2576 | void __i915_add_request(struct drm_i915_gem_request *request, |
5b4a60c2 JH |
2577 | struct drm_i915_gem_object *obj, |
2578 | bool flush_caches) | |
673a394b | 2579 | { |
e2f80391 | 2580 | struct intel_engine_cs *engine; |
75289874 | 2581 | struct drm_i915_private *dev_priv; |
48e29f55 | 2582 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2583 | u32 request_start; |
3cce469c CW |
2584 | int ret; |
2585 | ||
48e29f55 | 2586 | if (WARN_ON(request == NULL)) |
bf7dc5b7 | 2587 | return; |
48e29f55 | 2588 | |
4a570db5 | 2589 | engine = request->engine; |
39dabecd | 2590 | dev_priv = request->i915; |
75289874 JH |
2591 | ringbuf = request->ringbuf; |
2592 | ||
29b1b415 JH |
2593 | /* |
2594 | * To ensure that this call will not fail, space for its emissions | |
2595 | * should already have been reserved in the ring buffer. Let the ring | |
2596 | * know that it is time to use that space up. | |
2597 | */ | |
2598 | intel_ring_reserved_space_use(ringbuf); | |
2599 | ||
48e29f55 | 2600 | request_start = intel_ring_get_tail(ringbuf); |
cc889e0f DV |
2601 | /* |
2602 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2603 | * after having emitted the batchbuffer command. Hence we need to fix | |
2604 | * things up similar to emitting the lazy request. The difference here | |
2605 | * is that the flush _must_ happen before the next request, no matter | |
2606 | * what. | |
2607 | */ | |
5b4a60c2 JH |
2608 | if (flush_caches) { |
2609 | if (i915.enable_execlists) | |
4866d729 | 2610 | ret = logical_ring_flush_all_caches(request); |
5b4a60c2 | 2611 | else |
4866d729 | 2612 | ret = intel_ring_flush_all_caches(request); |
5b4a60c2 JH |
2613 | /* Not allowed to fail! */ |
2614 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); | |
2615 | } | |
cc889e0f | 2616 | |
7c90b7de CW |
2617 | trace_i915_gem_request_add(request); |
2618 | ||
2619 | request->head = request_start; | |
2620 | ||
2621 | /* Whilst this request exists, batch_obj will be on the | |
2622 | * active_list, and so will hold the active reference. Only when this | |
2623 | * request is retired will the the batch_obj be moved onto the | |
2624 | * inactive_list and lose its active reference. Hence we do not need | |
2625 | * to explicitly hold another reference here. | |
2626 | */ | |
2627 | request->batch_obj = obj; | |
2628 | ||
2629 | /* Seal the request and mark it as pending execution. Note that | |
2630 | * we may inspect this state, without holding any locks, during | |
2631 | * hangcheck. Hence we apply the barrier to ensure that we do not | |
2632 | * see a more recent value in the hws than we are tracking. | |
2633 | */ | |
2634 | request->emitted_jiffies = jiffies; | |
2635 | request->previous_seqno = engine->last_submitted_seqno; | |
2636 | smp_store_mb(engine->last_submitted_seqno, request->seqno); | |
2637 | list_add_tail(&request->list, &engine->request_list); | |
2638 | ||
a71d8d94 CW |
2639 | /* Record the position of the start of the request so that |
2640 | * should we detect the updated seqno part-way through the | |
2641 | * GPU processing the request, we never over-estimate the | |
2642 | * position of the head. | |
2643 | */ | |
6d3d8274 | 2644 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2645 | |
bf7dc5b7 | 2646 | if (i915.enable_execlists) |
e2f80391 | 2647 | ret = engine->emit_request(request); |
bf7dc5b7 | 2648 | else { |
e2f80391 | 2649 | ret = engine->add_request(request); |
53292cdb MT |
2650 | |
2651 | request->tail = intel_ring_get_tail(ringbuf); | |
48e29f55 | 2652 | } |
bf7dc5b7 JH |
2653 | /* Not allowed to fail! */ |
2654 | WARN(ret, "emit|add_request failed: %d!\n", ret); | |
673a394b | 2655 | |
e2f80391 | 2656 | i915_queue_hangcheck(engine->dev); |
10cd45b6 | 2657 | |
87255483 DV |
2658 | queue_delayed_work(dev_priv->wq, |
2659 | &dev_priv->mm.retire_work, | |
2660 | round_jiffies_up_relative(HZ)); | |
2661 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2662 | |
29b1b415 JH |
2663 | /* Sanity check that the reserved size was large enough. */ |
2664 | intel_ring_reserved_space_end(ringbuf); | |
673a394b EA |
2665 | } |
2666 | ||
939fd762 | 2667 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2668 | const struct intel_context *ctx) |
be62acb4 | 2669 | { |
44e2c070 | 2670 | unsigned long elapsed; |
be62acb4 | 2671 | |
44e2c070 MK |
2672 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2673 | ||
2674 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2675 | return true; |
2676 | ||
676fa572 CW |
2677 | if (ctx->hang_stats.ban_period_seconds && |
2678 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
ccc7bed0 | 2679 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2680 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2681 | return true; |
88b4aa87 MK |
2682 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2683 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2684 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2685 | return true; |
3fac8978 | 2686 | } |
be62acb4 MK |
2687 | } |
2688 | ||
2689 | return false; | |
2690 | } | |
2691 | ||
939fd762 | 2692 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2693 | struct intel_context *ctx, |
b6b0fac0 | 2694 | const bool guilty) |
aa60c664 | 2695 | { |
44e2c070 MK |
2696 | struct i915_ctx_hang_stats *hs; |
2697 | ||
2698 | if (WARN_ON(!ctx)) | |
2699 | return; | |
aa60c664 | 2700 | |
44e2c070 MK |
2701 | hs = &ctx->hang_stats; |
2702 | ||
2703 | if (guilty) { | |
939fd762 | 2704 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2705 | hs->batch_active++; |
2706 | hs->guilty_ts = get_seconds(); | |
2707 | } else { | |
2708 | hs->batch_pending++; | |
aa60c664 MK |
2709 | } |
2710 | } | |
2711 | ||
abfe262a JH |
2712 | void i915_gem_request_free(struct kref *req_ref) |
2713 | { | |
2714 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2715 | typeof(*req), ref); | |
2716 | struct intel_context *ctx = req->ctx; | |
2717 | ||
fcfa423c JH |
2718 | if (req->file_priv) |
2719 | i915_gem_request_remove_from_client(req); | |
2720 | ||
0794aed3 | 2721 | if (ctx) { |
e28e404c | 2722 | if (i915.enable_execlists && ctx != req->i915->kernel_context) |
4a570db5 | 2723 | intel_lr_context_unpin(ctx, req->engine); |
abfe262a | 2724 | |
dcb4c12a OM |
2725 | i915_gem_context_unreference(ctx); |
2726 | } | |
abfe262a | 2727 | |
efab6d8d | 2728 | kmem_cache_free(req->i915->requests, req); |
0e50e96b MK |
2729 | } |
2730 | ||
26827088 | 2731 | static inline int |
0bc40be8 | 2732 | __i915_gem_request_alloc(struct intel_engine_cs *engine, |
26827088 DG |
2733 | struct intel_context *ctx, |
2734 | struct drm_i915_gem_request **req_out) | |
6689cb2b | 2735 | { |
0bc40be8 | 2736 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
299259a3 | 2737 | unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
eed29a5b | 2738 | struct drm_i915_gem_request *req; |
6689cb2b | 2739 | int ret; |
6689cb2b | 2740 | |
217e46b5 JH |
2741 | if (!req_out) |
2742 | return -EINVAL; | |
2743 | ||
bccca494 | 2744 | *req_out = NULL; |
6689cb2b | 2745 | |
f4457ae7 CW |
2746 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
2747 | * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex | |
2748 | * and restart. | |
2749 | */ | |
2750 | ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible); | |
299259a3 CW |
2751 | if (ret) |
2752 | return ret; | |
2753 | ||
eed29a5b DV |
2754 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
2755 | if (req == NULL) | |
6689cb2b JH |
2756 | return -ENOMEM; |
2757 | ||
0bc40be8 | 2758 | ret = i915_gem_get_seqno(engine->dev, &req->seqno); |
9a0c1e27 CW |
2759 | if (ret) |
2760 | goto err; | |
6689cb2b | 2761 | |
40e895ce JH |
2762 | kref_init(&req->ref); |
2763 | req->i915 = dev_priv; | |
4a570db5 | 2764 | req->engine = engine; |
299259a3 | 2765 | req->reset_counter = reset_counter; |
40e895ce JH |
2766 | req->ctx = ctx; |
2767 | i915_gem_context_reference(req->ctx); | |
6689cb2b JH |
2768 | |
2769 | if (i915.enable_execlists) | |
40e895ce | 2770 | ret = intel_logical_ring_alloc_request_extras(req); |
6689cb2b | 2771 | else |
eed29a5b | 2772 | ret = intel_ring_alloc_request_extras(req); |
40e895ce JH |
2773 | if (ret) { |
2774 | i915_gem_context_unreference(req->ctx); | |
9a0c1e27 | 2775 | goto err; |
40e895ce | 2776 | } |
6689cb2b | 2777 | |
29b1b415 JH |
2778 | /* |
2779 | * Reserve space in the ring buffer for all the commands required to | |
2780 | * eventually emit this request. This is to guarantee that the | |
2781 | * i915_add_request() call can't fail. Note that the reserve may need | |
2782 | * to be redone if the request is not actually submitted straight | |
2783 | * away, e.g. because a GPU scheduler has deferred it. | |
29b1b415 | 2784 | */ |
ccd98fe4 JH |
2785 | if (i915.enable_execlists) |
2786 | ret = intel_logical_ring_reserve_space(req); | |
2787 | else | |
2788 | ret = intel_ring_reserve_space(req); | |
2789 | if (ret) { | |
2790 | /* | |
2791 | * At this point, the request is fully allocated even if not | |
2792 | * fully prepared. Thus it can be cleaned up using the proper | |
2793 | * free code. | |
2794 | */ | |
aa9b7810 CW |
2795 | intel_ring_reserved_space_cancel(req->ringbuf); |
2796 | i915_gem_request_unreference(req); | |
ccd98fe4 JH |
2797 | return ret; |
2798 | } | |
29b1b415 | 2799 | |
bccca494 | 2800 | *req_out = req; |
6689cb2b | 2801 | return 0; |
9a0c1e27 CW |
2802 | |
2803 | err: | |
2804 | kmem_cache_free(dev_priv->requests, req); | |
2805 | return ret; | |
0e50e96b MK |
2806 | } |
2807 | ||
26827088 DG |
2808 | /** |
2809 | * i915_gem_request_alloc - allocate a request structure | |
2810 | * | |
2811 | * @engine: engine that we wish to issue the request on. | |
2812 | * @ctx: context that the request will be associated with. | |
2813 | * This can be NULL if the request is not directly related to | |
2814 | * any specific user context, in which case this function will | |
2815 | * choose an appropriate context to use. | |
2816 | * | |
2817 | * Returns a pointer to the allocated request if successful, | |
2818 | * or an error code if not. | |
2819 | */ | |
2820 | struct drm_i915_gem_request * | |
2821 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
2822 | struct intel_context *ctx) | |
2823 | { | |
2824 | struct drm_i915_gem_request *req; | |
2825 | int err; | |
2826 | ||
2827 | if (ctx == NULL) | |
ed54c1a1 | 2828 | ctx = to_i915(engine->dev)->kernel_context; |
26827088 DG |
2829 | err = __i915_gem_request_alloc(engine, ctx, &req); |
2830 | return err ? ERR_PTR(err) : req; | |
2831 | } | |
2832 | ||
8d9fc7fd | 2833 | struct drm_i915_gem_request * |
0bc40be8 | 2834 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2835 | { |
4db080f9 CW |
2836 | struct drm_i915_gem_request *request; |
2837 | ||
0bc40be8 | 2838 | list_for_each_entry(request, &engine->request_list, list) { |
1b5a433a | 2839 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2840 | continue; |
aa60c664 | 2841 | |
b6b0fac0 | 2842 | return request; |
4db080f9 | 2843 | } |
b6b0fac0 MK |
2844 | |
2845 | return NULL; | |
2846 | } | |
2847 | ||
666796da | 2848 | static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv, |
0bc40be8 | 2849 | struct intel_engine_cs *engine) |
b6b0fac0 MK |
2850 | { |
2851 | struct drm_i915_gem_request *request; | |
2852 | bool ring_hung; | |
2853 | ||
0bc40be8 | 2854 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
2855 | |
2856 | if (request == NULL) | |
2857 | return; | |
2858 | ||
0bc40be8 | 2859 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 2860 | |
939fd762 | 2861 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 | 2862 | |
0bc40be8 | 2863 | list_for_each_entry_continue(request, &engine->request_list, list) |
939fd762 | 2864 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2865 | } |
aa60c664 | 2866 | |
666796da | 2867 | static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv, |
0bc40be8 | 2868 | struct intel_engine_cs *engine) |
4db080f9 | 2869 | { |
608c1a52 CW |
2870 | struct intel_ringbuffer *buffer; |
2871 | ||
0bc40be8 | 2872 | while (!list_empty(&engine->active_list)) { |
05394f39 | 2873 | struct drm_i915_gem_object *obj; |
9375e446 | 2874 | |
0bc40be8 | 2875 | obj = list_first_entry(&engine->active_list, |
05394f39 | 2876 | struct drm_i915_gem_object, |
117897f4 | 2877 | engine_list[engine->id]); |
9375e446 | 2878 | |
0bc40be8 | 2879 | i915_gem_object_retire__read(obj, engine->id); |
673a394b | 2880 | } |
1d62beea | 2881 | |
dcb4c12a OM |
2882 | /* |
2883 | * Clear the execlists queue up before freeing the requests, as those | |
2884 | * are the ones that keep the context and ringbuffer backing objects | |
2885 | * pinned in place. | |
2886 | */ | |
dcb4c12a | 2887 | |
7de1691a | 2888 | if (i915.enable_execlists) { |
27af5eea TU |
2889 | /* Ensure irq handler finishes or is cancelled. */ |
2890 | tasklet_kill(&engine->irq_tasklet); | |
1197b4f2 | 2891 | |
27af5eea | 2892 | spin_lock_bh(&engine->execlist_lock); |
c5baa566 | 2893 | /* list_splice_tail_init checks for empty lists */ |
0bc40be8 TU |
2894 | list_splice_tail_init(&engine->execlist_queue, |
2895 | &engine->execlist_retired_req_list); | |
27af5eea | 2896 | spin_unlock_bh(&engine->execlist_lock); |
1197b4f2 | 2897 | |
0bc40be8 | 2898 | intel_execlists_retire_requests(engine); |
dcb4c12a OM |
2899 | } |
2900 | ||
1d62beea BW |
2901 | /* |
2902 | * We must free the requests after all the corresponding objects have | |
2903 | * been moved off active lists. Which is the same order as the normal | |
2904 | * retire_requests function does. This is important if object hold | |
2905 | * implicit references on things like e.g. ppgtt address spaces through | |
2906 | * the request. | |
2907 | */ | |
0bc40be8 | 2908 | while (!list_empty(&engine->request_list)) { |
1d62beea BW |
2909 | struct drm_i915_gem_request *request; |
2910 | ||
0bc40be8 | 2911 | request = list_first_entry(&engine->request_list, |
1d62beea BW |
2912 | struct drm_i915_gem_request, |
2913 | list); | |
2914 | ||
b4716185 | 2915 | i915_gem_request_retire(request); |
1d62beea | 2916 | } |
608c1a52 CW |
2917 | |
2918 | /* Having flushed all requests from all queues, we know that all | |
2919 | * ringbuffers must now be empty. However, since we do not reclaim | |
2920 | * all space when retiring the request (to prevent HEADs colliding | |
2921 | * with rapid ringbuffer wraparound) the amount of available space | |
2922 | * upon reset is less than when we start. Do one more pass over | |
2923 | * all the ringbuffers to reset last_retired_head. | |
2924 | */ | |
0bc40be8 | 2925 | list_for_each_entry(buffer, &engine->buffers, link) { |
608c1a52 CW |
2926 | buffer->last_retired_head = buffer->tail; |
2927 | intel_ring_update_space(buffer); | |
2928 | } | |
2ed53a94 CW |
2929 | |
2930 | intel_ring_init_seqno(engine, engine->last_submitted_seqno); | |
673a394b EA |
2931 | } |
2932 | ||
069efc1d | 2933 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2934 | { |
77f01230 | 2935 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2936 | struct intel_engine_cs *engine; |
673a394b | 2937 | |
4db080f9 CW |
2938 | /* |
2939 | * Before we free the objects from the requests, we need to inspect | |
2940 | * them for finding the guilty party. As the requests only borrow | |
2941 | * their reference to the objects, the inspection must be done first. | |
2942 | */ | |
b4ac5afc | 2943 | for_each_engine(engine, dev_priv) |
666796da | 2944 | i915_gem_reset_engine_status(dev_priv, engine); |
4db080f9 | 2945 | |
b4ac5afc | 2946 | for_each_engine(engine, dev_priv) |
666796da | 2947 | i915_gem_reset_engine_cleanup(dev_priv, engine); |
dfaae392 | 2948 | |
acce9ffa BW |
2949 | i915_gem_context_reset(dev); |
2950 | ||
19b2dbde | 2951 | i915_gem_restore_fences(dev); |
b4716185 CW |
2952 | |
2953 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2954 | } |
2955 | ||
2956 | /** | |
2957 | * This function clears the request list as sequence numbers are passed. | |
2958 | */ | |
1cf0ba14 | 2959 | void |
0bc40be8 | 2960 | i915_gem_retire_requests_ring(struct intel_engine_cs *engine) |
673a394b | 2961 | { |
0bc40be8 | 2962 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b | 2963 | |
832a3aad CW |
2964 | /* Retire requests first as we use it above for the early return. |
2965 | * If we retire requests last, we may use a later seqno and so clear | |
2966 | * the requests lists without clearing the active list, leading to | |
2967 | * confusion. | |
e9103038 | 2968 | */ |
0bc40be8 | 2969 | while (!list_empty(&engine->request_list)) { |
673a394b | 2970 | struct drm_i915_gem_request *request; |
673a394b | 2971 | |
0bc40be8 | 2972 | request = list_first_entry(&engine->request_list, |
673a394b EA |
2973 | struct drm_i915_gem_request, |
2974 | list); | |
673a394b | 2975 | |
1b5a433a | 2976 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
2977 | break; |
2978 | ||
b4716185 | 2979 | i915_gem_request_retire(request); |
b84d5f0c | 2980 | } |
673a394b | 2981 | |
832a3aad CW |
2982 | /* Move any buffers on the active list that are no longer referenced |
2983 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2984 | * before we free the context associated with the requests. | |
2985 | */ | |
0bc40be8 | 2986 | while (!list_empty(&engine->active_list)) { |
832a3aad CW |
2987 | struct drm_i915_gem_object *obj; |
2988 | ||
0bc40be8 TU |
2989 | obj = list_first_entry(&engine->active_list, |
2990 | struct drm_i915_gem_object, | |
117897f4 | 2991 | engine_list[engine->id]); |
832a3aad | 2992 | |
0bc40be8 | 2993 | if (!list_empty(&obj->last_read_req[engine->id]->list)) |
832a3aad CW |
2994 | break; |
2995 | ||
0bc40be8 | 2996 | i915_gem_object_retire__read(obj, engine->id); |
832a3aad CW |
2997 | } |
2998 | ||
0bc40be8 TU |
2999 | if (unlikely(engine->trace_irq_req && |
3000 | i915_gem_request_completed(engine->trace_irq_req, true))) { | |
3001 | engine->irq_put(engine); | |
3002 | i915_gem_request_assign(&engine->trace_irq_req, NULL); | |
9d34e5db | 3003 | } |
23bc5982 | 3004 | |
0bc40be8 | 3005 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b EA |
3006 | } |
3007 | ||
b29c19b6 | 3008 | bool |
b09a1fec CW |
3009 | i915_gem_retire_requests(struct drm_device *dev) |
3010 | { | |
3e31c6c0 | 3011 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 3012 | struct intel_engine_cs *engine; |
b29c19b6 | 3013 | bool idle = true; |
b09a1fec | 3014 | |
b4ac5afc | 3015 | for_each_engine(engine, dev_priv) { |
e2f80391 TU |
3016 | i915_gem_retire_requests_ring(engine); |
3017 | idle &= list_empty(&engine->request_list); | |
c86ee3a9 | 3018 | if (i915.enable_execlists) { |
27af5eea | 3019 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 3020 | idle &= list_empty(&engine->execlist_queue); |
27af5eea | 3021 | spin_unlock_bh(&engine->execlist_lock); |
c86ee3a9 | 3022 | |
e2f80391 | 3023 | intel_execlists_retire_requests(engine); |
c86ee3a9 | 3024 | } |
b29c19b6 CW |
3025 | } |
3026 | ||
3027 | if (idle) | |
3028 | mod_delayed_work(dev_priv->wq, | |
3029 | &dev_priv->mm.idle_work, | |
3030 | msecs_to_jiffies(100)); | |
3031 | ||
3032 | return idle; | |
b09a1fec CW |
3033 | } |
3034 | ||
75ef9da2 | 3035 | static void |
673a394b EA |
3036 | i915_gem_retire_work_handler(struct work_struct *work) |
3037 | { | |
b29c19b6 CW |
3038 | struct drm_i915_private *dev_priv = |
3039 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
3040 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 3041 | bool idle; |
673a394b | 3042 | |
891b48cf | 3043 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
3044 | idle = false; |
3045 | if (mutex_trylock(&dev->struct_mutex)) { | |
3046 | idle = i915_gem_retire_requests(dev); | |
3047 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3048 | } |
b29c19b6 | 3049 | if (!idle) |
bcb45086 CW |
3050 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
3051 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 3052 | } |
0a58705b | 3053 | |
b29c19b6 CW |
3054 | static void |
3055 | i915_gem_idle_work_handler(struct work_struct *work) | |
3056 | { | |
3057 | struct drm_i915_private *dev_priv = | |
3058 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
35c94185 | 3059 | struct drm_device *dev = dev_priv->dev; |
b4ac5afc | 3060 | struct intel_engine_cs *engine; |
b29c19b6 | 3061 | |
b4ac5afc DG |
3062 | for_each_engine(engine, dev_priv) |
3063 | if (!list_empty(&engine->request_list)) | |
423795cb | 3064 | return; |
35c94185 | 3065 | |
30ecad77 | 3066 | /* we probably should sync with hangcheck here, using cancel_work_sync. |
b4ac5afc | 3067 | * Also locking seems to be fubar here, engine->request_list is protected |
30ecad77 DV |
3068 | * by dev->struct_mutex. */ |
3069 | ||
35c94185 CW |
3070 | intel_mark_idle(dev); |
3071 | ||
3072 | if (mutex_trylock(&dev->struct_mutex)) { | |
b4ac5afc | 3073 | for_each_engine(engine, dev_priv) |
e2f80391 | 3074 | i915_gem_batch_pool_fini(&engine->batch_pool); |
b29c19b6 | 3075 | |
35c94185 CW |
3076 | mutex_unlock(&dev->struct_mutex); |
3077 | } | |
673a394b EA |
3078 | } |
3079 | ||
30dfebf3 DV |
3080 | /** |
3081 | * Ensures that an object will eventually get non-busy by flushing any required | |
3082 | * write domains, emitting any outstanding lazy request and retiring and | |
3083 | * completed requests. | |
3084 | */ | |
3085 | static int | |
3086 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
3087 | { | |
a5ac0f90 | 3088 | int i; |
b4716185 CW |
3089 | |
3090 | if (!obj->active) | |
3091 | return 0; | |
30dfebf3 | 3092 | |
666796da | 3093 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 | 3094 | struct drm_i915_gem_request *req; |
41c52415 | 3095 | |
b4716185 CW |
3096 | req = obj->last_read_req[i]; |
3097 | if (req == NULL) | |
3098 | continue; | |
3099 | ||
3100 | if (list_empty(&req->list)) | |
3101 | goto retire; | |
3102 | ||
b4716185 CW |
3103 | if (i915_gem_request_completed(req, true)) { |
3104 | __i915_gem_request_retire__upto(req); | |
3105 | retire: | |
3106 | i915_gem_object_retire__read(obj, i); | |
3107 | } | |
30dfebf3 DV |
3108 | } |
3109 | ||
3110 | return 0; | |
3111 | } | |
3112 | ||
23ba4fd0 BW |
3113 | /** |
3114 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
3115 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
3116 | * | |
3117 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3118 | * the timeout parameter. | |
3119 | * -ETIME: object is still busy after timeout | |
3120 | * -ERESTARTSYS: signal interrupted the wait | |
3121 | * -ENONENT: object doesn't exist | |
3122 | * Also possible, but rare: | |
3123 | * -EAGAIN: GPU wedged | |
3124 | * -ENOMEM: damn | |
3125 | * -ENODEV: Internal IRQ fail | |
3126 | * -E?: The add request failed | |
3127 | * | |
3128 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3129 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3130 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3131 | * without holding struct_mutex the object may become re-busied before this | |
3132 | * function completes. A similar but shorter * race condition exists in the busy | |
3133 | * ioctl | |
3134 | */ | |
3135 | int | |
3136 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3137 | { | |
3138 | struct drm_i915_gem_wait *args = data; | |
3139 | struct drm_i915_gem_object *obj; | |
666796da | 3140 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 CW |
3141 | int i, n = 0; |
3142 | int ret; | |
23ba4fd0 | 3143 | |
11b5d511 DV |
3144 | if (args->flags != 0) |
3145 | return -EINVAL; | |
3146 | ||
23ba4fd0 BW |
3147 | ret = i915_mutex_lock_interruptible(dev); |
3148 | if (ret) | |
3149 | return ret; | |
3150 | ||
3151 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
3152 | if (&obj->base == NULL) { | |
3153 | mutex_unlock(&dev->struct_mutex); | |
3154 | return -ENOENT; | |
3155 | } | |
3156 | ||
30dfebf3 DV |
3157 | /* Need to make sure the object gets inactive eventually. */ |
3158 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
3159 | if (ret) |
3160 | goto out; | |
3161 | ||
b4716185 | 3162 | if (!obj->active) |
97b2a6a1 | 3163 | goto out; |
23ba4fd0 | 3164 | |
23ba4fd0 | 3165 | /* Do this after OLR check to make sure we make forward progress polling |
762e4583 | 3166 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
23ba4fd0 | 3167 | */ |
762e4583 | 3168 | if (args->timeout_ns == 0) { |
23ba4fd0 BW |
3169 | ret = -ETIME; |
3170 | goto out; | |
3171 | } | |
3172 | ||
3173 | drm_gem_object_unreference(&obj->base); | |
b4716185 | 3174 | |
666796da | 3175 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
3176 | if (obj->last_read_req[i] == NULL) |
3177 | continue; | |
3178 | ||
3179 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); | |
3180 | } | |
3181 | ||
23ba4fd0 BW |
3182 | mutex_unlock(&dev->struct_mutex); |
3183 | ||
b4716185 CW |
3184 | for (i = 0; i < n; i++) { |
3185 | if (ret == 0) | |
299259a3 | 3186 | ret = __i915_wait_request(req[i], true, |
b4716185 | 3187 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
b6aa0873 | 3188 | to_rps_client(file)); |
b4716185 CW |
3189 | i915_gem_request_unreference__unlocked(req[i]); |
3190 | } | |
ff865885 | 3191 | return ret; |
23ba4fd0 BW |
3192 | |
3193 | out: | |
3194 | drm_gem_object_unreference(&obj->base); | |
3195 | mutex_unlock(&dev->struct_mutex); | |
3196 | return ret; | |
3197 | } | |
3198 | ||
b4716185 CW |
3199 | static int |
3200 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3201 | struct intel_engine_cs *to, | |
91af127f JH |
3202 | struct drm_i915_gem_request *from_req, |
3203 | struct drm_i915_gem_request **to_req) | |
b4716185 CW |
3204 | { |
3205 | struct intel_engine_cs *from; | |
3206 | int ret; | |
3207 | ||
666796da | 3208 | from = i915_gem_request_get_engine(from_req); |
b4716185 CW |
3209 | if (to == from) |
3210 | return 0; | |
3211 | ||
91af127f | 3212 | if (i915_gem_request_completed(from_req, true)) |
b4716185 CW |
3213 | return 0; |
3214 | ||
b4716185 | 3215 | if (!i915_semaphore_is_enabled(obj->base.dev)) { |
a6f766f3 | 3216 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
91af127f | 3217 | ret = __i915_wait_request(from_req, |
a6f766f3 CW |
3218 | i915->mm.interruptible, |
3219 | NULL, | |
3220 | &i915->rps.semaphores); | |
b4716185 CW |
3221 | if (ret) |
3222 | return ret; | |
3223 | ||
91af127f | 3224 | i915_gem_object_retire_request(obj, from_req); |
b4716185 CW |
3225 | } else { |
3226 | int idx = intel_ring_sync_index(from, to); | |
91af127f JH |
3227 | u32 seqno = i915_gem_request_get_seqno(from_req); |
3228 | ||
3229 | WARN_ON(!to_req); | |
b4716185 CW |
3230 | |
3231 | if (seqno <= from->semaphore.sync_seqno[idx]) | |
3232 | return 0; | |
3233 | ||
91af127f | 3234 | if (*to_req == NULL) { |
26827088 DG |
3235 | struct drm_i915_gem_request *req; |
3236 | ||
3237 | req = i915_gem_request_alloc(to, NULL); | |
3238 | if (IS_ERR(req)) | |
3239 | return PTR_ERR(req); | |
3240 | ||
3241 | *to_req = req; | |
91af127f JH |
3242 | } |
3243 | ||
599d924c JH |
3244 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
3245 | ret = to->semaphore.sync_to(*to_req, from, seqno); | |
b4716185 CW |
3246 | if (ret) |
3247 | return ret; | |
3248 | ||
3249 | /* We use last_read_req because sync_to() | |
3250 | * might have just caused seqno wrap under | |
3251 | * the radar. | |
3252 | */ | |
3253 | from->semaphore.sync_seqno[idx] = | |
3254 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); | |
3255 | } | |
3256 | ||
3257 | return 0; | |
3258 | } | |
3259 | ||
5816d648 BW |
3260 | /** |
3261 | * i915_gem_object_sync - sync an object to a ring. | |
3262 | * | |
3263 | * @obj: object which may be in use on another ring. | |
3264 | * @to: ring we wish to use the object on. May be NULL. | |
91af127f JH |
3265 | * @to_req: request we wish to use the object for. See below. |
3266 | * This will be allocated and returned if a request is | |
3267 | * required but not passed in. | |
5816d648 BW |
3268 | * |
3269 | * This code is meant to abstract object synchronization with the GPU. | |
3270 | * Calling with NULL implies synchronizing the object with the CPU | |
b4716185 | 3271 | * rather than a particular GPU ring. Conceptually we serialise writes |
91af127f | 3272 | * between engines inside the GPU. We only allow one engine to write |
b4716185 CW |
3273 | * into a buffer at any time, but multiple readers. To ensure each has |
3274 | * a coherent view of memory, we must: | |
3275 | * | |
3276 | * - If there is an outstanding write request to the object, the new | |
3277 | * request must wait for it to complete (either CPU or in hw, requests | |
3278 | * on the same ring will be naturally ordered). | |
3279 | * | |
3280 | * - If we are a write request (pending_write_domain is set), the new | |
3281 | * request must wait for outstanding read requests to complete. | |
5816d648 | 3282 | * |
91af127f JH |
3283 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
3284 | * rings to_req must be non-NULL. However, a request does not have to be | |
3285 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a | |
3286 | * request will be allocated automatically and returned through *to_req. Note | |
3287 | * that it is not guaranteed that commands will be emitted (because the system | |
3288 | * might already be idle). Hence there is no need to create a request that | |
3289 | * might never have any work submitted. Note further that if a request is | |
3290 | * returned in *to_req, it is the responsibility of the caller to submit | |
3291 | * that request (after potentially adding more work to it). | |
3292 | * | |
5816d648 BW |
3293 | * Returns 0 if successful, else propagates up the lower layer error. |
3294 | */ | |
2911a35b BW |
3295 | int |
3296 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
91af127f JH |
3297 | struct intel_engine_cs *to, |
3298 | struct drm_i915_gem_request **to_req) | |
2911a35b | 3299 | { |
b4716185 | 3300 | const bool readonly = obj->base.pending_write_domain == 0; |
666796da | 3301 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 | 3302 | int ret, i, n; |
41c52415 | 3303 | |
b4716185 | 3304 | if (!obj->active) |
2911a35b BW |
3305 | return 0; |
3306 | ||
b4716185 CW |
3307 | if (to == NULL) |
3308 | return i915_gem_object_wait_rendering(obj, readonly); | |
2911a35b | 3309 | |
b4716185 CW |
3310 | n = 0; |
3311 | if (readonly) { | |
3312 | if (obj->last_write_req) | |
3313 | req[n++] = obj->last_write_req; | |
3314 | } else { | |
666796da | 3315 | for (i = 0; i < I915_NUM_ENGINES; i++) |
b4716185 CW |
3316 | if (obj->last_read_req[i]) |
3317 | req[n++] = obj->last_read_req[i]; | |
3318 | } | |
3319 | for (i = 0; i < n; i++) { | |
91af127f | 3320 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
b4716185 CW |
3321 | if (ret) |
3322 | return ret; | |
3323 | } | |
2911a35b | 3324 | |
b4716185 | 3325 | return 0; |
2911a35b BW |
3326 | } |
3327 | ||
b5ffc9bc CW |
3328 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3329 | { | |
3330 | u32 old_write_domain, old_read_domains; | |
3331 | ||
b5ffc9bc CW |
3332 | /* Force a pagefault for domain tracking on next user access */ |
3333 | i915_gem_release_mmap(obj); | |
3334 | ||
b97c3d9c KP |
3335 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3336 | return; | |
3337 | ||
b5ffc9bc CW |
3338 | old_read_domains = obj->base.read_domains; |
3339 | old_write_domain = obj->base.write_domain; | |
3340 | ||
3341 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3342 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3343 | ||
3344 | trace_i915_gem_object_change_domain(obj, | |
3345 | old_read_domains, | |
3346 | old_write_domain); | |
3347 | } | |
3348 | ||
e9f24d5f | 3349 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
673a394b | 3350 | { |
07fe0b12 | 3351 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3352 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3353 | int ret; |
673a394b | 3354 | |
1c7f4bca | 3355 | if (list_empty(&vma->obj_link)) |
673a394b EA |
3356 | return 0; |
3357 | ||
0ff501cb DV |
3358 | if (!drm_mm_node_allocated(&vma->node)) { |
3359 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3360 | return 0; |
3361 | } | |
433544bd | 3362 | |
d7f46fc4 | 3363 | if (vma->pin_count) |
31d8d651 | 3364 | return -EBUSY; |
673a394b | 3365 | |
c4670ad0 CW |
3366 | BUG_ON(obj->pages == NULL); |
3367 | ||
e9f24d5f TU |
3368 | if (wait) { |
3369 | ret = i915_gem_object_wait_rendering(obj, false); | |
3370 | if (ret) | |
3371 | return ret; | |
3372 | } | |
a8198eea | 3373 | |
596c5923 | 3374 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
8b1bc9b4 | 3375 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3376 | |
8b1bc9b4 DV |
3377 | /* release the fence reg _after_ flushing */ |
3378 | ret = i915_gem_object_put_fence(obj); | |
3379 | if (ret) | |
3380 | return ret; | |
3381 | } | |
96b47b65 | 3382 | |
07fe0b12 | 3383 | trace_i915_vma_unbind(vma); |
db53a302 | 3384 | |
777dc5bb | 3385 | vma->vm->unbind_vma(vma); |
5e562f1d | 3386 | vma->bound = 0; |
6f65e29a | 3387 | |
1c7f4bca | 3388 | list_del_init(&vma->vm_link); |
596c5923 | 3389 | if (vma->is_ggtt) { |
fe14d5f4 TU |
3390 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
3391 | obj->map_and_fenceable = false; | |
3392 | } else if (vma->ggtt_view.pages) { | |
3393 | sg_free_table(vma->ggtt_view.pages); | |
3394 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 3395 | } |
016a65a3 | 3396 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 3397 | } |
673a394b | 3398 | |
2f633156 BW |
3399 | drm_mm_remove_node(&vma->node); |
3400 | i915_gem_vma_destroy(vma); | |
3401 | ||
3402 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3403 | * no more VMAs exist. */ |
e2273302 | 3404 | if (list_empty(&obj->vma_list)) |
2f633156 | 3405 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
673a394b | 3406 | |
70903c3b CW |
3407 | /* And finally now the object is completely decoupled from this vma, |
3408 | * we can drop its hold on the backing storage and allow it to be | |
3409 | * reaped by the shrinker. | |
3410 | */ | |
3411 | i915_gem_object_unpin_pages(obj); | |
3412 | ||
88241785 | 3413 | return 0; |
54cf91dc CW |
3414 | } |
3415 | ||
e9f24d5f TU |
3416 | int i915_vma_unbind(struct i915_vma *vma) |
3417 | { | |
3418 | return __i915_vma_unbind(vma, true); | |
3419 | } | |
3420 | ||
3421 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) | |
3422 | { | |
3423 | return __i915_vma_unbind(vma, false); | |
3424 | } | |
3425 | ||
b2da9fe5 | 3426 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3427 | { |
3e31c6c0 | 3428 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 3429 | struct intel_engine_cs *engine; |
b4ac5afc | 3430 | int ret; |
4df2faf4 | 3431 | |
4df2faf4 | 3432 | /* Flush everything onto the inactive list. */ |
b4ac5afc | 3433 | for_each_engine(engine, dev_priv) { |
ecdb5fd8 | 3434 | if (!i915.enable_execlists) { |
73cfa865 JH |
3435 | struct drm_i915_gem_request *req; |
3436 | ||
e2f80391 | 3437 | req = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
3438 | if (IS_ERR(req)) |
3439 | return PTR_ERR(req); | |
73cfa865 | 3440 | |
ba01cc93 | 3441 | ret = i915_switch_context(req); |
75289874 | 3442 | i915_add_request_no_flush(req); |
aa9b7810 CW |
3443 | if (ret) |
3444 | return ret; | |
ecdb5fd8 | 3445 | } |
b6c7488d | 3446 | |
666796da | 3447 | ret = intel_engine_idle(engine); |
1ec14ad3 CW |
3448 | if (ret) |
3449 | return ret; | |
3450 | } | |
4df2faf4 | 3451 | |
b4716185 | 3452 | WARN_ON(i915_verify_lists(dev)); |
8a1a49f9 | 3453 | return 0; |
4df2faf4 DV |
3454 | } |
3455 | ||
4144f9b5 | 3456 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3457 | unsigned long cache_level) |
3458 | { | |
4144f9b5 | 3459 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3460 | struct drm_mm_node *other; |
3461 | ||
4144f9b5 CW |
3462 | /* |
3463 | * On some machines we have to be careful when putting differing types | |
3464 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3465 | * domains and dying. During vm initialisation, we decide whether or not | |
3466 | * these constraints apply and set the drm_mm.color_adjust | |
3467 | * appropriately. | |
42d6ab48 | 3468 | */ |
4144f9b5 | 3469 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3470 | return true; |
3471 | ||
c6cfb325 | 3472 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3473 | return true; |
3474 | ||
3475 | if (list_empty(>t_space->node_list)) | |
3476 | return true; | |
3477 | ||
3478 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3479 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3480 | return false; | |
3481 | ||
3482 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3483 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3484 | return false; | |
3485 | ||
3486 | return true; | |
3487 | } | |
3488 | ||
673a394b | 3489 | /** |
91e6711e JL |
3490 | * Finds free space in the GTT aperture and binds the object or a view of it |
3491 | * there. | |
673a394b | 3492 | */ |
262de145 | 3493 | static struct i915_vma * |
07fe0b12 BW |
3494 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3495 | struct i915_address_space *vm, | |
ec7adb6e | 3496 | const struct i915_ggtt_view *ggtt_view, |
07fe0b12 | 3497 | unsigned alignment, |
ec7adb6e | 3498 | uint64_t flags) |
673a394b | 3499 | { |
05394f39 | 3500 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
3501 | struct drm_i915_private *dev_priv = to_i915(dev); |
3502 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
65bd342f | 3503 | u32 fence_alignment, unfenced_alignment; |
101b506a MT |
3504 | u32 search_flag, alloc_flag; |
3505 | u64 start, end; | |
65bd342f | 3506 | u64 size, fence_size; |
2f633156 | 3507 | struct i915_vma *vma; |
07f73f69 | 3508 | int ret; |
673a394b | 3509 | |
91e6711e JL |
3510 | if (i915_is_ggtt(vm)) { |
3511 | u32 view_size; | |
3512 | ||
3513 | if (WARN_ON(!ggtt_view)) | |
3514 | return ERR_PTR(-EINVAL); | |
ec7adb6e | 3515 | |
91e6711e JL |
3516 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
3517 | ||
3518 | fence_size = i915_gem_get_gtt_size(dev, | |
3519 | view_size, | |
3520 | obj->tiling_mode); | |
3521 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3522 | view_size, | |
3523 | obj->tiling_mode, | |
3524 | true); | |
3525 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, | |
3526 | view_size, | |
3527 | obj->tiling_mode, | |
3528 | false); | |
3529 | size = flags & PIN_MAPPABLE ? fence_size : view_size; | |
3530 | } else { | |
3531 | fence_size = i915_gem_get_gtt_size(dev, | |
3532 | obj->base.size, | |
3533 | obj->tiling_mode); | |
3534 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3535 | obj->base.size, | |
3536 | obj->tiling_mode, | |
3537 | true); | |
3538 | unfenced_alignment = | |
3539 | i915_gem_get_gtt_alignment(dev, | |
3540 | obj->base.size, | |
3541 | obj->tiling_mode, | |
3542 | false); | |
3543 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; | |
3544 | } | |
a00b10c3 | 3545 | |
101b506a MT |
3546 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
3547 | end = vm->total; | |
3548 | if (flags & PIN_MAPPABLE) | |
72e96d64 | 3549 | end = min_t(u64, end, ggtt->mappable_end); |
101b506a | 3550 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3551 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3552 | |
673a394b | 3553 | if (alignment == 0) |
1ec9e26d | 3554 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3555 | unfenced_alignment; |
1ec9e26d | 3556 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
91e6711e JL |
3557 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
3558 | ggtt_view ? ggtt_view->type : 0, | |
3559 | alignment); | |
262de145 | 3560 | return ERR_PTR(-EINVAL); |
673a394b EA |
3561 | } |
3562 | ||
91e6711e JL |
3563 | /* If binding the object/GGTT view requires more space than the entire |
3564 | * aperture has, reject it early before evicting everything in a vain | |
3565 | * attempt to find space. | |
654fc607 | 3566 | */ |
91e6711e | 3567 | if (size > end) { |
65bd342f | 3568 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
91e6711e JL |
3569 | ggtt_view ? ggtt_view->type : 0, |
3570 | size, | |
1ec9e26d | 3571 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3572 | end); |
262de145 | 3573 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3574 | } |
3575 | ||
37e680a1 | 3576 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3577 | if (ret) |
262de145 | 3578 | return ERR_PTR(ret); |
6c085a72 | 3579 | |
fbdda6fb CW |
3580 | i915_gem_object_pin_pages(obj); |
3581 | ||
ec7adb6e JL |
3582 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
3583 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3584 | ||
262de145 | 3585 | if (IS_ERR(vma)) |
bc6bc15b | 3586 | goto err_unpin; |
2f633156 | 3587 | |
506a8e87 CW |
3588 | if (flags & PIN_OFFSET_FIXED) { |
3589 | uint64_t offset = flags & PIN_OFFSET_MASK; | |
3590 | ||
3591 | if (offset & (alignment - 1) || offset + size > end) { | |
3592 | ret = -EINVAL; | |
3593 | goto err_free_vma; | |
3594 | } | |
3595 | vma->node.start = offset; | |
3596 | vma->node.size = size; | |
3597 | vma->node.color = obj->cache_level; | |
3598 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3599 | if (ret) { | |
3600 | ret = i915_gem_evict_for_vma(vma); | |
3601 | if (ret == 0) | |
3602 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3603 | } | |
3604 | if (ret) | |
3605 | goto err_free_vma; | |
101b506a | 3606 | } else { |
506a8e87 CW |
3607 | if (flags & PIN_HIGH) { |
3608 | search_flag = DRM_MM_SEARCH_BELOW; | |
3609 | alloc_flag = DRM_MM_CREATE_TOP; | |
3610 | } else { | |
3611 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3612 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3613 | } | |
101b506a | 3614 | |
0a9ae0d7 | 3615 | search_free: |
506a8e87 CW |
3616 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3617 | size, alignment, | |
3618 | obj->cache_level, | |
3619 | start, end, | |
3620 | search_flag, | |
3621 | alloc_flag); | |
3622 | if (ret) { | |
3623 | ret = i915_gem_evict_something(dev, vm, size, alignment, | |
3624 | obj->cache_level, | |
3625 | start, end, | |
3626 | flags); | |
3627 | if (ret == 0) | |
3628 | goto search_free; | |
9731129c | 3629 | |
506a8e87 CW |
3630 | goto err_free_vma; |
3631 | } | |
673a394b | 3632 | } |
4144f9b5 | 3633 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3634 | ret = -EINVAL; |
bc6bc15b | 3635 | goto err_remove_node; |
673a394b EA |
3636 | } |
3637 | ||
fe14d5f4 | 3638 | trace_i915_vma_bind(vma, flags); |
0875546c | 3639 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
fe14d5f4 | 3640 | if (ret) |
e2273302 | 3641 | goto err_remove_node; |
fe14d5f4 | 3642 | |
35c20a60 | 3643 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
1c7f4bca | 3644 | list_add_tail(&vma->vm_link, &vm->inactive_list); |
bf1a1092 | 3645 | |
262de145 | 3646 | return vma; |
2f633156 | 3647 | |
bc6bc15b | 3648 | err_remove_node: |
6286ef9b | 3649 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3650 | err_free_vma: |
2f633156 | 3651 | i915_gem_vma_destroy(vma); |
262de145 | 3652 | vma = ERR_PTR(ret); |
bc6bc15b | 3653 | err_unpin: |
2f633156 | 3654 | i915_gem_object_unpin_pages(obj); |
262de145 | 3655 | return vma; |
673a394b EA |
3656 | } |
3657 | ||
000433b6 | 3658 | bool |
2c22569b CW |
3659 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3660 | bool force) | |
673a394b | 3661 | { |
673a394b EA |
3662 | /* If we don't have a page list set up, then we're not pinned |
3663 | * to GPU, and we can ignore the cache flush because it'll happen | |
3664 | * again at bind time. | |
3665 | */ | |
05394f39 | 3666 | if (obj->pages == NULL) |
000433b6 | 3667 | return false; |
673a394b | 3668 | |
769ce464 ID |
3669 | /* |
3670 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3671 | * marked as wc by the system, or the system is cache-coherent. | |
3672 | */ | |
6a2c4232 | 3673 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3674 | return false; |
769ce464 | 3675 | |
9c23f7fc CW |
3676 | /* If the GPU is snooping the contents of the CPU cache, |
3677 | * we do not need to manually clear the CPU cache lines. However, | |
3678 | * the caches are only snooped when the render cache is | |
3679 | * flushed/invalidated. As we always have to emit invalidations | |
3680 | * and flushes when moving into and out of the RENDER domain, correct | |
3681 | * snooping behaviour occurs naturally as the result of our domain | |
3682 | * tracking. | |
3683 | */ | |
0f71979a CW |
3684 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3685 | obj->cache_dirty = true; | |
000433b6 | 3686 | return false; |
0f71979a | 3687 | } |
9c23f7fc | 3688 | |
1c5d22f7 | 3689 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3690 | drm_clflush_sg(obj->pages); |
0f71979a | 3691 | obj->cache_dirty = false; |
000433b6 CW |
3692 | |
3693 | return true; | |
e47c68e9 EA |
3694 | } |
3695 | ||
3696 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3697 | static void | |
05394f39 | 3698 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3699 | { |
1c5d22f7 CW |
3700 | uint32_t old_write_domain; |
3701 | ||
05394f39 | 3702 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3703 | return; |
3704 | ||
63256ec5 | 3705 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3706 | * to it immediately go to main memory as far as we know, so there's |
3707 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3708 | * |
3709 | * However, we do have to enforce the order so that all writes through | |
3710 | * the GTT land before any writes to the device, such as updates to | |
3711 | * the GATT itself. | |
e47c68e9 | 3712 | */ |
63256ec5 CW |
3713 | wmb(); |
3714 | ||
05394f39 CW |
3715 | old_write_domain = obj->base.write_domain; |
3716 | obj->base.write_domain = 0; | |
1c5d22f7 | 3717 | |
de152b62 | 3718 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3719 | |
1c5d22f7 | 3720 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3721 | obj->base.read_domains, |
1c5d22f7 | 3722 | old_write_domain); |
e47c68e9 EA |
3723 | } |
3724 | ||
3725 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3726 | static void | |
e62b59e4 | 3727 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3728 | { |
1c5d22f7 | 3729 | uint32_t old_write_domain; |
e47c68e9 | 3730 | |
05394f39 | 3731 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3732 | return; |
3733 | ||
e62b59e4 | 3734 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
000433b6 CW |
3735 | i915_gem_chipset_flush(obj->base.dev); |
3736 | ||
05394f39 CW |
3737 | old_write_domain = obj->base.write_domain; |
3738 | obj->base.write_domain = 0; | |
1c5d22f7 | 3739 | |
de152b62 | 3740 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3741 | |
1c5d22f7 | 3742 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3743 | obj->base.read_domains, |
1c5d22f7 | 3744 | old_write_domain); |
e47c68e9 EA |
3745 | } |
3746 | ||
2ef7eeaa EA |
3747 | /** |
3748 | * Moves a single object to the GTT read, and possibly write domain. | |
3749 | * | |
3750 | * This function returns when the move is complete, including waiting on | |
3751 | * flushes to occur. | |
3752 | */ | |
79e53945 | 3753 | int |
2021746e | 3754 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3755 | { |
72e96d64 JL |
3756 | struct drm_device *dev = obj->base.dev; |
3757 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3758 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1c5d22f7 | 3759 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3760 | struct i915_vma *vma; |
e47c68e9 | 3761 | int ret; |
2ef7eeaa | 3762 | |
8d7e3de1 CW |
3763 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3764 | return 0; | |
3765 | ||
0201f1ec | 3766 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3767 | if (ret) |
3768 | return ret; | |
3769 | ||
43566ded CW |
3770 | /* Flush and acquire obj->pages so that we are coherent through |
3771 | * direct access in memory with previous cached writes through | |
3772 | * shmemfs and that our cache domain tracking remains valid. | |
3773 | * For example, if the obj->filp was moved to swap without us | |
3774 | * being notified and releasing the pages, we would mistakenly | |
3775 | * continue to assume that the obj remained out of the CPU cached | |
3776 | * domain. | |
3777 | */ | |
3778 | ret = i915_gem_object_get_pages(obj); | |
3779 | if (ret) | |
3780 | return ret; | |
3781 | ||
e62b59e4 | 3782 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3783 | |
d0a57789 CW |
3784 | /* Serialise direct access to this object with the barriers for |
3785 | * coherent writes from the GPU, by effectively invalidating the | |
3786 | * GTT domain upon first access. | |
3787 | */ | |
3788 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3789 | mb(); | |
3790 | ||
05394f39 CW |
3791 | old_write_domain = obj->base.write_domain; |
3792 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3793 | |
e47c68e9 EA |
3794 | /* It should now be out of any other write domains, and we can update |
3795 | * the domain values for our changes. | |
3796 | */ | |
05394f39 CW |
3797 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3798 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3799 | if (write) { |
05394f39 CW |
3800 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3801 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3802 | obj->dirty = 1; | |
2ef7eeaa EA |
3803 | } |
3804 | ||
1c5d22f7 CW |
3805 | trace_i915_gem_object_change_domain(obj, |
3806 | old_read_domains, | |
3807 | old_write_domain); | |
3808 | ||
8325a09d | 3809 | /* And bump the LRU for this access */ |
43566ded CW |
3810 | vma = i915_gem_obj_to_ggtt(obj); |
3811 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
1c7f4bca | 3812 | list_move_tail(&vma->vm_link, |
72e96d64 | 3813 | &ggtt->base.inactive_list); |
8325a09d | 3814 | |
e47c68e9 EA |
3815 | return 0; |
3816 | } | |
3817 | ||
ef55f92a CW |
3818 | /** |
3819 | * Changes the cache-level of an object across all VMA. | |
3820 | * | |
3821 | * After this function returns, the object will be in the new cache-level | |
3822 | * across all GTT and the contents of the backing storage will be coherent, | |
3823 | * with respect to the new cache-level. In order to keep the backing storage | |
3824 | * coherent for all users, we only allow a single cache level to be set | |
3825 | * globally on the object and prevent it from being changed whilst the | |
3826 | * hardware is reading from the object. That is if the object is currently | |
3827 | * on the scanout it will be set to uncached (or equivalent display | |
3828 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3829 | * that all direct access to the scanout remains coherent. | |
3830 | */ | |
e4ffd173 CW |
3831 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3832 | enum i915_cache_level cache_level) | |
3833 | { | |
7bddb01f | 3834 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3835 | struct i915_vma *vma, *next; |
ef55f92a | 3836 | bool bound = false; |
ed75a55b | 3837 | int ret = 0; |
e4ffd173 CW |
3838 | |
3839 | if (obj->cache_level == cache_level) | |
ed75a55b | 3840 | goto out; |
e4ffd173 | 3841 | |
ef55f92a CW |
3842 | /* Inspect the list of currently bound VMA and unbind any that would |
3843 | * be invalid given the new cache-level. This is principally to | |
3844 | * catch the issue of the CS prefetch crossing page boundaries and | |
3845 | * reading an invalid PTE on older architectures. | |
3846 | */ | |
1c7f4bca | 3847 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
ef55f92a CW |
3848 | if (!drm_mm_node_allocated(&vma->node)) |
3849 | continue; | |
3850 | ||
3851 | if (vma->pin_count) { | |
3852 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3853 | return -EBUSY; | |
3854 | } | |
3855 | ||
4144f9b5 | 3856 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3857 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3858 | if (ret) |
3859 | return ret; | |
ef55f92a CW |
3860 | } else |
3861 | bound = true; | |
42d6ab48 CW |
3862 | } |
3863 | ||
ef55f92a CW |
3864 | /* We can reuse the existing drm_mm nodes but need to change the |
3865 | * cache-level on the PTE. We could simply unbind them all and | |
3866 | * rebind with the correct cache-level on next use. However since | |
3867 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3868 | * rewrite the PTE in the belief that doing so tramples upon less | |
3869 | * state and so involves less work. | |
3870 | */ | |
3871 | if (bound) { | |
3872 | /* Before we change the PTE, the GPU must not be accessing it. | |
3873 | * If we wait upon the object, we know that all the bound | |
3874 | * VMA are no longer active. | |
3875 | */ | |
2e2f351d | 3876 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3877 | if (ret) |
3878 | return ret; | |
3879 | ||
ef55f92a CW |
3880 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
3881 | /* Access to snoopable pages through the GTT is | |
3882 | * incoherent and on some machines causes a hard | |
3883 | * lockup. Relinquish the CPU mmaping to force | |
3884 | * userspace to refault in the pages and we can | |
3885 | * then double check if the GTT mapping is still | |
3886 | * valid for that pointer access. | |
3887 | */ | |
3888 | i915_gem_release_mmap(obj); | |
3889 | ||
3890 | /* As we no longer need a fence for GTT access, | |
3891 | * we can relinquish it now (and so prevent having | |
3892 | * to steal a fence from someone else on the next | |
3893 | * fence request). Note GPU activity would have | |
3894 | * dropped the fence as all snoopable access is | |
3895 | * supposed to be linear. | |
3896 | */ | |
e4ffd173 CW |
3897 | ret = i915_gem_object_put_fence(obj); |
3898 | if (ret) | |
3899 | return ret; | |
ef55f92a CW |
3900 | } else { |
3901 | /* We either have incoherent backing store and | |
3902 | * so no GTT access or the architecture is fully | |
3903 | * coherent. In such cases, existing GTT mmaps | |
3904 | * ignore the cache bit in the PTE and we can | |
3905 | * rewrite it without confusing the GPU or having | |
3906 | * to force userspace to fault back in its mmaps. | |
3907 | */ | |
e4ffd173 CW |
3908 | } |
3909 | ||
1c7f4bca | 3910 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3911 | if (!drm_mm_node_allocated(&vma->node)) |
3912 | continue; | |
3913 | ||
3914 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3915 | if (ret) | |
3916 | return ret; | |
3917 | } | |
e4ffd173 CW |
3918 | } |
3919 | ||
1c7f4bca | 3920 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3921 | vma->node.color = cache_level; |
3922 | obj->cache_level = cache_level; | |
3923 | ||
ed75a55b | 3924 | out: |
ef55f92a CW |
3925 | /* Flush the dirty CPU caches to the backing storage so that the |
3926 | * object is now coherent at its new cache level (with respect | |
3927 | * to the access domain). | |
3928 | */ | |
0f71979a CW |
3929 | if (obj->cache_dirty && |
3930 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
3931 | cpu_write_needs_clflush(obj)) { | |
3932 | if (i915_gem_clflush_object(obj, true)) | |
3933 | i915_gem_chipset_flush(obj->base.dev); | |
e4ffd173 CW |
3934 | } |
3935 | ||
e4ffd173 CW |
3936 | return 0; |
3937 | } | |
3938 | ||
199adf40 BW |
3939 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3940 | struct drm_file *file) | |
e6994aee | 3941 | { |
199adf40 | 3942 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3943 | struct drm_i915_gem_object *obj; |
e6994aee CW |
3944 | |
3945 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
432be69d CW |
3946 | if (&obj->base == NULL) |
3947 | return -ENOENT; | |
e6994aee | 3948 | |
651d794f CW |
3949 | switch (obj->cache_level) { |
3950 | case I915_CACHE_LLC: | |
3951 | case I915_CACHE_L3_LLC: | |
3952 | args->caching = I915_CACHING_CACHED; | |
3953 | break; | |
3954 | ||
4257d3ba CW |
3955 | case I915_CACHE_WT: |
3956 | args->caching = I915_CACHING_DISPLAY; | |
3957 | break; | |
3958 | ||
651d794f CW |
3959 | default: |
3960 | args->caching = I915_CACHING_NONE; | |
3961 | break; | |
3962 | } | |
e6994aee | 3963 | |
432be69d CW |
3964 | drm_gem_object_unreference_unlocked(&obj->base); |
3965 | return 0; | |
e6994aee CW |
3966 | } |
3967 | ||
199adf40 BW |
3968 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3969 | struct drm_file *file) | |
e6994aee | 3970 | { |
fd0fe6ac | 3971 | struct drm_i915_private *dev_priv = dev->dev_private; |
199adf40 | 3972 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3973 | struct drm_i915_gem_object *obj; |
3974 | enum i915_cache_level level; | |
3975 | int ret; | |
3976 | ||
199adf40 BW |
3977 | switch (args->caching) { |
3978 | case I915_CACHING_NONE: | |
e6994aee CW |
3979 | level = I915_CACHE_NONE; |
3980 | break; | |
199adf40 | 3981 | case I915_CACHING_CACHED: |
e5756c10 ID |
3982 | /* |
3983 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3984 | * snooped mapping may leave stale data in a corresponding CPU | |
3985 | * cacheline, whereas normally such cachelines would get | |
3986 | * invalidated. | |
3987 | */ | |
ca377809 | 3988 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
3989 | return -ENODEV; |
3990 | ||
e6994aee CW |
3991 | level = I915_CACHE_LLC; |
3992 | break; | |
4257d3ba CW |
3993 | case I915_CACHING_DISPLAY: |
3994 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3995 | break; | |
e6994aee CW |
3996 | default: |
3997 | return -EINVAL; | |
3998 | } | |
3999 | ||
fd0fe6ac ID |
4000 | intel_runtime_pm_get(dev_priv); |
4001 | ||
3bc2913e BW |
4002 | ret = i915_mutex_lock_interruptible(dev); |
4003 | if (ret) | |
fd0fe6ac | 4004 | goto rpm_put; |
3bc2913e | 4005 | |
e6994aee CW |
4006 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
4007 | if (&obj->base == NULL) { | |
4008 | ret = -ENOENT; | |
4009 | goto unlock; | |
4010 | } | |
4011 | ||
4012 | ret = i915_gem_object_set_cache_level(obj, level); | |
4013 | ||
4014 | drm_gem_object_unreference(&obj->base); | |
4015 | unlock: | |
4016 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
4017 | rpm_put: |
4018 | intel_runtime_pm_put(dev_priv); | |
4019 | ||
e6994aee CW |
4020 | return ret; |
4021 | } | |
4022 | ||
b9241ea3 | 4023 | /* |
2da3b9b9 CW |
4024 | * Prepare buffer for display plane (scanout, cursors, etc). |
4025 | * Can be called from an uninterruptible phase (modesetting) and allows | |
4026 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
4027 | */ |
4028 | int | |
2da3b9b9 CW |
4029 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
4030 | u32 alignment, | |
e6617330 | 4031 | const struct i915_ggtt_view *view) |
b9241ea3 | 4032 | { |
2da3b9b9 | 4033 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
4034 | int ret; |
4035 | ||
cc98b413 CW |
4036 | /* Mark the pin_display early so that we account for the |
4037 | * display coherency whilst setting up the cache domains. | |
4038 | */ | |
8a0c39b1 | 4039 | obj->pin_display++; |
cc98b413 | 4040 | |
a7ef0640 EA |
4041 | /* The display engine is not coherent with the LLC cache on gen6. As |
4042 | * a result, we make sure that the pinning that is about to occur is | |
4043 | * done with uncached PTEs. This is lowest common denominator for all | |
4044 | * chipsets. | |
4045 | * | |
4046 | * However for gen6+, we could do better by using the GFDT bit instead | |
4047 | * of uncaching, which would allow us to flush all the LLC-cached data | |
4048 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
4049 | */ | |
651d794f CW |
4050 | ret = i915_gem_object_set_cache_level(obj, |
4051 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 4052 | if (ret) |
cc98b413 | 4053 | goto err_unpin_display; |
a7ef0640 | 4054 | |
2da3b9b9 CW |
4055 | /* As the user may map the buffer once pinned in the display plane |
4056 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
4057 | * always use map_and_fenceable for all scanout buffers. | |
4058 | */ | |
50470bb0 TU |
4059 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
4060 | view->type == I915_GGTT_VIEW_NORMAL ? | |
4061 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 4062 | if (ret) |
cc98b413 | 4063 | goto err_unpin_display; |
2da3b9b9 | 4064 | |
e62b59e4 | 4065 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 4066 | |
2da3b9b9 | 4067 | old_write_domain = obj->base.write_domain; |
05394f39 | 4068 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
4069 | |
4070 | /* It should now be out of any other write domains, and we can update | |
4071 | * the domain values for our changes. | |
4072 | */ | |
e5f1d962 | 4073 | obj->base.write_domain = 0; |
05394f39 | 4074 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
4075 | |
4076 | trace_i915_gem_object_change_domain(obj, | |
4077 | old_read_domains, | |
2da3b9b9 | 4078 | old_write_domain); |
b9241ea3 ZW |
4079 | |
4080 | return 0; | |
cc98b413 CW |
4081 | |
4082 | err_unpin_display: | |
8a0c39b1 | 4083 | obj->pin_display--; |
cc98b413 CW |
4084 | return ret; |
4085 | } | |
4086 | ||
4087 | void | |
e6617330 TU |
4088 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
4089 | const struct i915_ggtt_view *view) | |
cc98b413 | 4090 | { |
8a0c39b1 TU |
4091 | if (WARN_ON(obj->pin_display == 0)) |
4092 | return; | |
4093 | ||
e6617330 TU |
4094 | i915_gem_object_ggtt_unpin_view(obj, view); |
4095 | ||
8a0c39b1 | 4096 | obj->pin_display--; |
b9241ea3 ZW |
4097 | } |
4098 | ||
e47c68e9 EA |
4099 | /** |
4100 | * Moves a single object to the CPU read, and possibly write domain. | |
4101 | * | |
4102 | * This function returns when the move is complete, including waiting on | |
4103 | * flushes to occur. | |
4104 | */ | |
dabdfe02 | 4105 | int |
919926ae | 4106 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4107 | { |
1c5d22f7 | 4108 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4109 | int ret; |
4110 | ||
8d7e3de1 CW |
4111 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4112 | return 0; | |
4113 | ||
0201f1ec | 4114 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4115 | if (ret) |
4116 | return ret; | |
4117 | ||
e47c68e9 | 4118 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4119 | |
05394f39 CW |
4120 | old_write_domain = obj->base.write_domain; |
4121 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4122 | |
e47c68e9 | 4123 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4124 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4125 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4126 | |
05394f39 | 4127 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4128 | } |
4129 | ||
4130 | /* It should now be out of any other write domains, and we can update | |
4131 | * the domain values for our changes. | |
4132 | */ | |
05394f39 | 4133 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4134 | |
4135 | /* If we're writing through the CPU, then the GPU read domains will | |
4136 | * need to be invalidated at next use. | |
4137 | */ | |
4138 | if (write) { | |
05394f39 CW |
4139 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4140 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4141 | } |
2ef7eeaa | 4142 | |
1c5d22f7 CW |
4143 | trace_i915_gem_object_change_domain(obj, |
4144 | old_read_domains, | |
4145 | old_write_domain); | |
4146 | ||
2ef7eeaa EA |
4147 | return 0; |
4148 | } | |
4149 | ||
673a394b EA |
4150 | /* Throttle our rendering by waiting until the ring has completed our requests |
4151 | * emitted over 20 msec ago. | |
4152 | * | |
b962442e EA |
4153 | * Note that if we were to use the current jiffies each time around the loop, |
4154 | * we wouldn't escape the function with any frames outstanding if the time to | |
4155 | * render a frame was over 20ms. | |
4156 | * | |
673a394b EA |
4157 | * This should get us reasonable parallelism between CPU and GPU but also |
4158 | * relatively low latency when blocking on a particular request to finish. | |
4159 | */ | |
40a5f0de | 4160 | static int |
f787a5f5 | 4161 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4162 | { |
f787a5f5 CW |
4163 | struct drm_i915_private *dev_priv = dev->dev_private; |
4164 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
d0bc54f2 | 4165 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 4166 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 4167 | int ret; |
93533c29 | 4168 | |
308887aa DV |
4169 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4170 | if (ret) | |
4171 | return ret; | |
4172 | ||
f4457ae7 CW |
4173 | /* ABI: return -EIO if already wedged */ |
4174 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
4175 | return -EIO; | |
e110e8d6 | 4176 | |
1c25595f | 4177 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4178 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4179 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4180 | break; | |
40a5f0de | 4181 | |
fcfa423c JH |
4182 | /* |
4183 | * Note that the request might not have been submitted yet. | |
4184 | * In which case emitted_jiffies will be zero. | |
4185 | */ | |
4186 | if (!request->emitted_jiffies) | |
4187 | continue; | |
4188 | ||
54fb2411 | 4189 | target = request; |
b962442e | 4190 | } |
ff865885 JH |
4191 | if (target) |
4192 | i915_gem_request_reference(target); | |
1c25595f | 4193 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4194 | |
54fb2411 | 4195 | if (target == NULL) |
f787a5f5 | 4196 | return 0; |
2bc43b5c | 4197 | |
299259a3 | 4198 | ret = __i915_wait_request(target, true, NULL, NULL); |
f787a5f5 CW |
4199 | if (ret == 0) |
4200 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4201 | |
41037f9f | 4202 | i915_gem_request_unreference__unlocked(target); |
ff865885 | 4203 | |
40a5f0de EA |
4204 | return ret; |
4205 | } | |
4206 | ||
d23db88c CW |
4207 | static bool |
4208 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4209 | { | |
4210 | struct drm_i915_gem_object *obj = vma->obj; | |
4211 | ||
4212 | if (alignment && | |
4213 | vma->node.start & (alignment - 1)) | |
4214 | return true; | |
4215 | ||
4216 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4217 | return true; | |
4218 | ||
4219 | if (flags & PIN_OFFSET_BIAS && | |
4220 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4221 | return true; | |
4222 | ||
506a8e87 CW |
4223 | if (flags & PIN_OFFSET_FIXED && |
4224 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
4225 | return true; | |
4226 | ||
d23db88c CW |
4227 | return false; |
4228 | } | |
4229 | ||
d0710abb CW |
4230 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
4231 | { | |
4232 | struct drm_i915_gem_object *obj = vma->obj; | |
4233 | bool mappable, fenceable; | |
4234 | u32 fence_size, fence_alignment; | |
4235 | ||
4236 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4237 | obj->base.size, | |
4238 | obj->tiling_mode); | |
4239 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4240 | obj->base.size, | |
4241 | obj->tiling_mode, | |
4242 | true); | |
4243 | ||
4244 | fenceable = (vma->node.size == fence_size && | |
4245 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4246 | ||
4247 | mappable = (vma->node.start + fence_size <= | |
62106b4f | 4248 | to_i915(obj->base.dev)->ggtt.mappable_end); |
d0710abb CW |
4249 | |
4250 | obj->map_and_fenceable = mappable && fenceable; | |
4251 | } | |
4252 | ||
ec7adb6e JL |
4253 | static int |
4254 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
4255 | struct i915_address_space *vm, | |
4256 | const struct i915_ggtt_view *ggtt_view, | |
4257 | uint32_t alignment, | |
4258 | uint64_t flags) | |
673a394b | 4259 | { |
6e7186af | 4260 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4261 | struct i915_vma *vma; |
ef79e17c | 4262 | unsigned bound; |
673a394b EA |
4263 | int ret; |
4264 | ||
6e7186af BW |
4265 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4266 | return -ENODEV; | |
4267 | ||
bf3d149b | 4268 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4269 | return -EINVAL; |
07fe0b12 | 4270 | |
c826c449 CW |
4271 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4272 | return -EINVAL; | |
4273 | ||
ec7adb6e JL |
4274 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
4275 | return -EINVAL; | |
4276 | ||
4277 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
4278 | i915_gem_obj_to_vma(obj, vm); | |
4279 | ||
07fe0b12 | 4280 | if (vma) { |
d7f46fc4 BW |
4281 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4282 | return -EBUSY; | |
4283 | ||
d23db88c | 4284 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4285 | WARN(vma->pin_count, |
ec7adb6e | 4286 | "bo is already pinned in %s with incorrect alignment:" |
088e0df4 | 4287 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4288 | " obj->map_and_fenceable=%d\n", |
ec7adb6e | 4289 | ggtt_view ? "ggtt" : "ppgtt", |
088e0df4 MT |
4290 | upper_32_bits(vma->node.start), |
4291 | lower_32_bits(vma->node.start), | |
fe14d5f4 | 4292 | alignment, |
d23db88c | 4293 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4294 | obj->map_and_fenceable); |
07fe0b12 | 4295 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4296 | if (ret) |
4297 | return ret; | |
8ea99c92 DV |
4298 | |
4299 | vma = NULL; | |
ac0c6b5a CW |
4300 | } |
4301 | } | |
4302 | ||
ef79e17c | 4303 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4304 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
ec7adb6e JL |
4305 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
4306 | flags); | |
262de145 DV |
4307 | if (IS_ERR(vma)) |
4308 | return PTR_ERR(vma); | |
0875546c DV |
4309 | } else { |
4310 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
fe14d5f4 TU |
4311 | if (ret) |
4312 | return ret; | |
4313 | } | |
74898d7e | 4314 | |
91e6711e JL |
4315 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
4316 | (bound ^ vma->bound) & GLOBAL_BIND) { | |
d0710abb | 4317 | __i915_vma_set_map_and_fenceable(vma); |
91e6711e JL |
4318 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
4319 | } | |
ef79e17c | 4320 | |
8ea99c92 | 4321 | vma->pin_count++; |
673a394b EA |
4322 | return 0; |
4323 | } | |
4324 | ||
ec7adb6e JL |
4325 | int |
4326 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
4327 | struct i915_address_space *vm, | |
4328 | uint32_t alignment, | |
4329 | uint64_t flags) | |
4330 | { | |
4331 | return i915_gem_object_do_pin(obj, vm, | |
4332 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
4333 | alignment, flags); | |
4334 | } | |
4335 | ||
4336 | int | |
4337 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
4338 | const struct i915_ggtt_view *view, | |
4339 | uint32_t alignment, | |
4340 | uint64_t flags) | |
4341 | { | |
72e96d64 JL |
4342 | struct drm_device *dev = obj->base.dev; |
4343 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4344 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
4345 | ||
ade7daa1 | 4346 | BUG_ON(!view); |
ec7adb6e | 4347 | |
72e96d64 | 4348 | return i915_gem_object_do_pin(obj, &ggtt->base, view, |
6fafab76 | 4349 | alignment, flags | PIN_GLOBAL); |
ec7adb6e JL |
4350 | } |
4351 | ||
673a394b | 4352 | void |
e6617330 TU |
4353 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
4354 | const struct i915_ggtt_view *view) | |
673a394b | 4355 | { |
e6617330 | 4356 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 4357 | |
d7f46fc4 | 4358 | BUG_ON(!vma); |
e6617330 | 4359 | WARN_ON(vma->pin_count == 0); |
9abc4648 | 4360 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 4361 | |
30154650 | 4362 | --vma->pin_count; |
673a394b EA |
4363 | } |
4364 | ||
673a394b EA |
4365 | int |
4366 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4367 | struct drm_file *file) |
673a394b EA |
4368 | { |
4369 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4370 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4371 | int ret; |
4372 | ||
76c1dec1 | 4373 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4374 | if (ret) |
76c1dec1 | 4375 | return ret; |
673a394b | 4376 | |
05394f39 | 4377 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4378 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4379 | ret = -ENOENT; |
4380 | goto unlock; | |
673a394b | 4381 | } |
d1b851fc | 4382 | |
0be555b6 CW |
4383 | /* Count all active objects as busy, even if they are currently not used |
4384 | * by the gpu. Users of this interface expect objects to eventually | |
4385 | * become non-busy without any further actions, therefore emit any | |
4386 | * necessary flushes here. | |
c4de0a5d | 4387 | */ |
30dfebf3 | 4388 | ret = i915_gem_object_flush_active(obj); |
b4716185 CW |
4389 | if (ret) |
4390 | goto unref; | |
0be555b6 | 4391 | |
426960be CW |
4392 | args->busy = 0; |
4393 | if (obj->active) { | |
4394 | int i; | |
4395 | ||
666796da | 4396 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
426960be CW |
4397 | struct drm_i915_gem_request *req; |
4398 | ||
4399 | req = obj->last_read_req[i]; | |
4400 | if (req) | |
4a570db5 | 4401 | args->busy |= 1 << (16 + req->engine->exec_id); |
426960be CW |
4402 | } |
4403 | if (obj->last_write_req) | |
4a570db5 | 4404 | args->busy |= obj->last_write_req->engine->exec_id; |
426960be | 4405 | } |
673a394b | 4406 | |
b4716185 | 4407 | unref: |
05394f39 | 4408 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4409 | unlock: |
673a394b | 4410 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4411 | return ret; |
673a394b EA |
4412 | } |
4413 | ||
4414 | int | |
4415 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4416 | struct drm_file *file_priv) | |
4417 | { | |
0206e353 | 4418 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4419 | } |
4420 | ||
3ef94daa CW |
4421 | int |
4422 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4423 | struct drm_file *file_priv) | |
4424 | { | |
656bfa3a | 4425 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4426 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4427 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4428 | int ret; |
3ef94daa CW |
4429 | |
4430 | switch (args->madv) { | |
4431 | case I915_MADV_DONTNEED: | |
4432 | case I915_MADV_WILLNEED: | |
4433 | break; | |
4434 | default: | |
4435 | return -EINVAL; | |
4436 | } | |
4437 | ||
1d7cfea1 CW |
4438 | ret = i915_mutex_lock_interruptible(dev); |
4439 | if (ret) | |
4440 | return ret; | |
4441 | ||
05394f39 | 4442 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4443 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4444 | ret = -ENOENT; |
4445 | goto unlock; | |
3ef94daa | 4446 | } |
3ef94daa | 4447 | |
d7f46fc4 | 4448 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4449 | ret = -EINVAL; |
4450 | goto out; | |
3ef94daa CW |
4451 | } |
4452 | ||
656bfa3a DV |
4453 | if (obj->pages && |
4454 | obj->tiling_mode != I915_TILING_NONE && | |
4455 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4456 | if (obj->madv == I915_MADV_WILLNEED) | |
4457 | i915_gem_object_unpin_pages(obj); | |
4458 | if (args->madv == I915_MADV_WILLNEED) | |
4459 | i915_gem_object_pin_pages(obj); | |
4460 | } | |
4461 | ||
05394f39 CW |
4462 | if (obj->madv != __I915_MADV_PURGED) |
4463 | obj->madv = args->madv; | |
3ef94daa | 4464 | |
6c085a72 | 4465 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4466 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4467 | i915_gem_object_truncate(obj); |
4468 | ||
05394f39 | 4469 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4470 | |
1d7cfea1 | 4471 | out: |
05394f39 | 4472 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4473 | unlock: |
3ef94daa | 4474 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4475 | return ret; |
3ef94daa CW |
4476 | } |
4477 | ||
37e680a1 CW |
4478 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4479 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4480 | { |
b4716185 CW |
4481 | int i; |
4482 | ||
35c20a60 | 4483 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 4484 | for (i = 0; i < I915_NUM_ENGINES; i++) |
117897f4 | 4485 | INIT_LIST_HEAD(&obj->engine_list[i]); |
b25cb2f8 | 4486 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4487 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4488 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4489 | |
37e680a1 CW |
4490 | obj->ops = ops; |
4491 | ||
0327d6ba CW |
4492 | obj->fence_reg = I915_FENCE_REG_NONE; |
4493 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4494 | |
4495 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4496 | } | |
4497 | ||
37e680a1 | 4498 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 4499 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
4500 | .get_pages = i915_gem_object_get_pages_gtt, |
4501 | .put_pages = i915_gem_object_put_pages_gtt, | |
4502 | }; | |
4503 | ||
05394f39 CW |
4504 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4505 | size_t size) | |
ac52bc56 | 4506 | { |
c397b908 | 4507 | struct drm_i915_gem_object *obj; |
5949eac4 | 4508 | struct address_space *mapping; |
1a240d4d | 4509 | gfp_t mask; |
ac52bc56 | 4510 | |
42dcedd4 | 4511 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4512 | if (obj == NULL) |
4513 | return NULL; | |
673a394b | 4514 | |
c397b908 | 4515 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4516 | i915_gem_object_free(obj); |
c397b908 DV |
4517 | return NULL; |
4518 | } | |
673a394b | 4519 | |
bed1ea95 CW |
4520 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4521 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4522 | /* 965gm cannot relocate objects above 4GiB. */ | |
4523 | mask &= ~__GFP_HIGHMEM; | |
4524 | mask |= __GFP_DMA32; | |
4525 | } | |
4526 | ||
496ad9aa | 4527 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4528 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4529 | |
37e680a1 | 4530 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4531 | |
c397b908 DV |
4532 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4533 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4534 | |
3d29b842 ED |
4535 | if (HAS_LLC(dev)) { |
4536 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4537 | * cache) for about a 10% performance improvement |
4538 | * compared to uncached. Graphics requests other than | |
4539 | * display scanout are coherent with the CPU in | |
4540 | * accessing this cache. This means in this mode we | |
4541 | * don't need to clflush on the CPU side, and on the | |
4542 | * GPU side we only need to flush internal caches to | |
4543 | * get data visible to the CPU. | |
4544 | * | |
4545 | * However, we maintain the display planes as UC, and so | |
4546 | * need to rebind when first used as such. | |
4547 | */ | |
4548 | obj->cache_level = I915_CACHE_LLC; | |
4549 | } else | |
4550 | obj->cache_level = I915_CACHE_NONE; | |
4551 | ||
d861e338 DV |
4552 | trace_i915_gem_object_create(obj); |
4553 | ||
05394f39 | 4554 | return obj; |
c397b908 DV |
4555 | } |
4556 | ||
340fbd8c CW |
4557 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4558 | { | |
4559 | /* If we are the last user of the backing storage (be it shmemfs | |
4560 | * pages or stolen etc), we know that the pages are going to be | |
4561 | * immediately released. In this case, we can then skip copying | |
4562 | * back the contents from the GPU. | |
4563 | */ | |
4564 | ||
4565 | if (obj->madv != I915_MADV_WILLNEED) | |
4566 | return false; | |
4567 | ||
4568 | if (obj->base.filp == NULL) | |
4569 | return true; | |
4570 | ||
4571 | /* At first glance, this looks racy, but then again so would be | |
4572 | * userspace racing mmap against close. However, the first external | |
4573 | * reference to the filp can only be obtained through the | |
4574 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4575 | * acquiring such a reference whilst we are in the middle of | |
4576 | * freeing the object. | |
4577 | */ | |
4578 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4579 | } | |
4580 | ||
1488fc08 | 4581 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4582 | { |
1488fc08 | 4583 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4584 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4585 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4586 | struct i915_vma *vma, *next; |
673a394b | 4587 | |
f65c9168 PZ |
4588 | intel_runtime_pm_get(dev_priv); |
4589 | ||
26e12f89 CW |
4590 | trace_i915_gem_object_destroy(obj); |
4591 | ||
1c7f4bca | 4592 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
4593 | int ret; |
4594 | ||
4595 | vma->pin_count = 0; | |
4596 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4597 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4598 | bool was_interruptible; | |
1488fc08 | 4599 | |
07fe0b12 BW |
4600 | was_interruptible = dev_priv->mm.interruptible; |
4601 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4602 | |
07fe0b12 | 4603 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4604 | |
07fe0b12 BW |
4605 | dev_priv->mm.interruptible = was_interruptible; |
4606 | } | |
1488fc08 CW |
4607 | } |
4608 | ||
1d64ae71 BW |
4609 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4610 | * before progressing. */ | |
4611 | if (obj->stolen) | |
4612 | i915_gem_object_unpin_pages(obj); | |
4613 | ||
a071fa00 DV |
4614 | WARN_ON(obj->frontbuffer_bits); |
4615 | ||
656bfa3a DV |
4616 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4617 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4618 | obj->tiling_mode != I915_TILING_NONE) | |
4619 | i915_gem_object_unpin_pages(obj); | |
4620 | ||
401c29f6 BW |
4621 | if (WARN_ON(obj->pages_pin_count)) |
4622 | obj->pages_pin_count = 0; | |
340fbd8c | 4623 | if (discard_backing_storage(obj)) |
5537252b | 4624 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4625 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4626 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4627 | |
9da3da66 CW |
4628 | BUG_ON(obj->pages); |
4629 | ||
2f745ad3 CW |
4630 | if (obj->base.import_attach) |
4631 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4632 | |
5cc9ed4b CW |
4633 | if (obj->ops->release) |
4634 | obj->ops->release(obj); | |
4635 | ||
05394f39 CW |
4636 | drm_gem_object_release(&obj->base); |
4637 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4638 | |
05394f39 | 4639 | kfree(obj->bit_17); |
42dcedd4 | 4640 | i915_gem_object_free(obj); |
f65c9168 PZ |
4641 | |
4642 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4643 | } |
4644 | ||
ec7adb6e JL |
4645 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4646 | struct i915_address_space *vm) | |
e656a6cb DV |
4647 | { |
4648 | struct i915_vma *vma; | |
1c7f4bca | 4649 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
1b683729 TU |
4650 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4651 | vma->vm == vm) | |
e656a6cb | 4652 | return vma; |
ec7adb6e JL |
4653 | } |
4654 | return NULL; | |
4655 | } | |
4656 | ||
4657 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4658 | const struct i915_ggtt_view *view) | |
4659 | { | |
72e96d64 JL |
4660 | struct drm_device *dev = obj->base.dev; |
4661 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4662 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ec7adb6e | 4663 | struct i915_vma *vma; |
e656a6cb | 4664 | |
ade7daa1 | 4665 | BUG_ON(!view); |
ec7adb6e | 4666 | |
1c7f4bca | 4667 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
72e96d64 | 4668 | if (vma->vm == &ggtt->base && |
9abc4648 | 4669 | i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e | 4670 | return vma; |
e656a6cb DV |
4671 | return NULL; |
4672 | } | |
4673 | ||
2f633156 BW |
4674 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4675 | { | |
4676 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4677 | |
4678 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4679 | if (!list_empty(&vma->exec_list)) | |
4680 | return; | |
4681 | ||
596c5923 CW |
4682 | if (!vma->is_ggtt) |
4683 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); | |
b9d06dd9 | 4684 | |
1c7f4bca | 4685 | list_del(&vma->obj_link); |
b93dab6e | 4686 | |
e20d2ab7 | 4687 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
2f633156 BW |
4688 | } |
4689 | ||
e3efda49 | 4690 | static void |
117897f4 | 4691 | i915_gem_stop_engines(struct drm_device *dev) |
e3efda49 CW |
4692 | { |
4693 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 4694 | struct intel_engine_cs *engine; |
e3efda49 | 4695 | |
b4ac5afc | 4696 | for_each_engine(engine, dev_priv) |
117897f4 | 4697 | dev_priv->gt.stop_engine(engine); |
e3efda49 CW |
4698 | } |
4699 | ||
29105ccc | 4700 | int |
45c5f202 | 4701 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4702 | { |
3e31c6c0 | 4703 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4704 | int ret = 0; |
28dfe52a | 4705 | |
45c5f202 | 4706 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4707 | ret = i915_gpu_idle(dev); |
f7403347 | 4708 | if (ret) |
45c5f202 | 4709 | goto err; |
f7403347 | 4710 | |
b2da9fe5 | 4711 | i915_gem_retire_requests(dev); |
673a394b | 4712 | |
117897f4 | 4713 | i915_gem_stop_engines(dev); |
45c5f202 CW |
4714 | mutex_unlock(&dev->struct_mutex); |
4715 | ||
737b1506 | 4716 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
29105ccc | 4717 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4718 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4719 | |
bdcf120b CW |
4720 | /* Assert that we sucessfully flushed all the work and |
4721 | * reset the GPU back to its idle, low power state. | |
4722 | */ | |
4723 | WARN_ON(dev_priv->mm.busy); | |
4724 | ||
673a394b | 4725 | return 0; |
45c5f202 CW |
4726 | |
4727 | err: | |
4728 | mutex_unlock(&dev->struct_mutex); | |
4729 | return ret; | |
673a394b EA |
4730 | } |
4731 | ||
6909a666 | 4732 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) |
b9524a1e | 4733 | { |
4a570db5 | 4734 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 4735 | struct drm_device *dev = engine->dev; |
3e31c6c0 | 4736 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4737 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
c3787e2e | 4738 | int i, ret; |
b9524a1e | 4739 | |
040d2baa | 4740 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4741 | return 0; |
b9524a1e | 4742 | |
5fb9de1a | 4743 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); |
c3787e2e BW |
4744 | if (ret) |
4745 | return ret; | |
b9524a1e | 4746 | |
c3787e2e BW |
4747 | /* |
4748 | * Note: We do not worry about the concurrent register cacheline hang | |
4749 | * here because no other code should access these registers other than | |
4750 | * at initialization time. | |
4751 | */ | |
6fa1c5f1 | 4752 | for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { |
e2f80391 TU |
4753 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); |
4754 | intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); | |
4755 | intel_ring_emit(engine, remap_info[i]); | |
b9524a1e BW |
4756 | } |
4757 | ||
e2f80391 | 4758 | intel_ring_advance(engine); |
b9524a1e | 4759 | |
c3787e2e | 4760 | return ret; |
b9524a1e BW |
4761 | } |
4762 | ||
f691e2f4 DV |
4763 | void i915_gem_init_swizzling(struct drm_device *dev) |
4764 | { | |
3e31c6c0 | 4765 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4766 | |
11782b02 | 4767 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4768 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4769 | return; | |
4770 | ||
4771 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4772 | DISP_TILE_SURFACE_SWIZZLING); | |
4773 | ||
11782b02 DV |
4774 | if (IS_GEN5(dev)) |
4775 | return; | |
4776 | ||
f691e2f4 DV |
4777 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4778 | if (IS_GEN6(dev)) | |
6b26c86d | 4779 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4780 | else if (IS_GEN7(dev)) |
6b26c86d | 4781 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4782 | else if (IS_GEN8(dev)) |
4783 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4784 | else |
4785 | BUG(); | |
f691e2f4 | 4786 | } |
e21af88d | 4787 | |
81e7f200 VS |
4788 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4789 | { | |
4790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4791 | ||
4792 | I915_WRITE(RING_CTL(base), 0); | |
4793 | I915_WRITE(RING_HEAD(base), 0); | |
4794 | I915_WRITE(RING_TAIL(base), 0); | |
4795 | I915_WRITE(RING_START(base), 0); | |
4796 | } | |
4797 | ||
4798 | static void init_unused_rings(struct drm_device *dev) | |
4799 | { | |
4800 | if (IS_I830(dev)) { | |
4801 | init_unused_ring(dev, PRB1_BASE); | |
4802 | init_unused_ring(dev, SRB0_BASE); | |
4803 | init_unused_ring(dev, SRB1_BASE); | |
4804 | init_unused_ring(dev, SRB2_BASE); | |
4805 | init_unused_ring(dev, SRB3_BASE); | |
4806 | } else if (IS_GEN2(dev)) { | |
4807 | init_unused_ring(dev, SRB0_BASE); | |
4808 | init_unused_ring(dev, SRB1_BASE); | |
4809 | } else if (IS_GEN3(dev)) { | |
4810 | init_unused_ring(dev, PRB1_BASE); | |
4811 | init_unused_ring(dev, PRB2_BASE); | |
4812 | } | |
4813 | } | |
4814 | ||
117897f4 | 4815 | int i915_gem_init_engines(struct drm_device *dev) |
8187a2b7 | 4816 | { |
4fc7c971 | 4817 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4818 | int ret; |
68f95ba9 | 4819 | |
5c1143bb | 4820 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4821 | if (ret) |
b6913e4b | 4822 | return ret; |
68f95ba9 CW |
4823 | |
4824 | if (HAS_BSD(dev)) { | |
5c1143bb | 4825 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4826 | if (ret) |
4827 | goto cleanup_render_ring; | |
d1b851fc | 4828 | } |
68f95ba9 | 4829 | |
d39398f5 | 4830 | if (HAS_BLT(dev)) { |
549f7365 CW |
4831 | ret = intel_init_blt_ring_buffer(dev); |
4832 | if (ret) | |
4833 | goto cleanup_bsd_ring; | |
4834 | } | |
4835 | ||
9a8a2213 BW |
4836 | if (HAS_VEBOX(dev)) { |
4837 | ret = intel_init_vebox_ring_buffer(dev); | |
4838 | if (ret) | |
4839 | goto cleanup_blt_ring; | |
4840 | } | |
4841 | ||
845f74a7 ZY |
4842 | if (HAS_BSD2(dev)) { |
4843 | ret = intel_init_bsd2_ring_buffer(dev); | |
4844 | if (ret) | |
4845 | goto cleanup_vebox_ring; | |
4846 | } | |
9a8a2213 | 4847 | |
4fc7c971 BW |
4848 | return 0; |
4849 | ||
9a8a2213 | 4850 | cleanup_vebox_ring: |
117897f4 | 4851 | intel_cleanup_engine(&dev_priv->engine[VECS]); |
4fc7c971 | 4852 | cleanup_blt_ring: |
117897f4 | 4853 | intel_cleanup_engine(&dev_priv->engine[BCS]); |
4fc7c971 | 4854 | cleanup_bsd_ring: |
117897f4 | 4855 | intel_cleanup_engine(&dev_priv->engine[VCS]); |
4fc7c971 | 4856 | cleanup_render_ring: |
117897f4 | 4857 | intel_cleanup_engine(&dev_priv->engine[RCS]); |
4fc7c971 BW |
4858 | |
4859 | return ret; | |
4860 | } | |
4861 | ||
4862 | int | |
4863 | i915_gem_init_hw(struct drm_device *dev) | |
4864 | { | |
3e31c6c0 | 4865 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 4866 | struct intel_engine_cs *engine; |
b4ac5afc | 4867 | int ret, j; |
4fc7c971 BW |
4868 | |
4869 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4870 | return -EIO; | |
4871 | ||
5e4f5189 CW |
4872 | /* Double layer security blanket, see i915_gem_init() */ |
4873 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4874 | ||
3accaf7e | 4875 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4876 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4877 | |
0bf21347 VS |
4878 | if (IS_HASWELL(dev)) |
4879 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4880 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4881 | |
88a2b2a3 | 4882 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4883 | if (IS_IVYBRIDGE(dev)) { |
4884 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4885 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4886 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4887 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4888 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4889 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4890 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4891 | } | |
88a2b2a3 BW |
4892 | } |
4893 | ||
4fc7c971 BW |
4894 | i915_gem_init_swizzling(dev); |
4895 | ||
d5abdfda DV |
4896 | /* |
4897 | * At least 830 can leave some of the unused rings | |
4898 | * "active" (ie. head != tail) after resume which | |
4899 | * will prevent c3 entry. Makes sure all unused rings | |
4900 | * are totally idle. | |
4901 | */ | |
4902 | init_unused_rings(dev); | |
4903 | ||
ed54c1a1 | 4904 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4905 | |
4ad2fd88 JH |
4906 | ret = i915_ppgtt_init_hw(dev); |
4907 | if (ret) { | |
4908 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4909 | goto out; | |
4910 | } | |
4911 | ||
4912 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4913 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4914 | ret = engine->init_hw(engine); |
35a57ffb | 4915 | if (ret) |
5e4f5189 | 4916 | goto out; |
35a57ffb | 4917 | } |
99433931 | 4918 | |
0ccdacf6 PA |
4919 | intel_mocs_init_l3cc_table(dev); |
4920 | ||
33a732f4 | 4921 | /* We can't enable contexts until all firmware is loaded */ |
87bcdd2e JB |
4922 | if (HAS_GUC_UCODE(dev)) { |
4923 | ret = intel_guc_ucode_load(dev); | |
4924 | if (ret) { | |
9f9e539f DV |
4925 | DRM_ERROR("Failed to initialize GuC, error %d\n", ret); |
4926 | ret = -EIO; | |
4927 | goto out; | |
87bcdd2e | 4928 | } |
33a732f4 AD |
4929 | } |
4930 | ||
e84fe803 NH |
4931 | /* |
4932 | * Increment the next seqno by 0x100 so we have a visible break | |
4933 | * on re-initialisation | |
4934 | */ | |
4935 | ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100); | |
4936 | if (ret) | |
4937 | goto out; | |
4938 | ||
4ad2fd88 | 4939 | /* Now it is safe to go back round and do everything else: */ |
b4ac5afc | 4940 | for_each_engine(engine, dev_priv) { |
dc4be607 JH |
4941 | struct drm_i915_gem_request *req; |
4942 | ||
e2f80391 | 4943 | req = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
4944 | if (IS_ERR(req)) { |
4945 | ret = PTR_ERR(req); | |
aa9b7810 | 4946 | break; |
dc4be607 JH |
4947 | } |
4948 | ||
e2f80391 | 4949 | if (engine->id == RCS) { |
aa9b7810 CW |
4950 | for (j = 0; j < NUM_L3_SLICES(dev); j++) { |
4951 | ret = i915_gem_l3_remap(req, j); | |
4952 | if (ret) | |
4953 | goto err_request; | |
4954 | } | |
4ad2fd88 | 4955 | } |
c3787e2e | 4956 | |
b3dd6b96 | 4957 | ret = i915_ppgtt_init_ring(req); |
aa9b7810 CW |
4958 | if (ret) |
4959 | goto err_request; | |
82460d97 | 4960 | |
b3dd6b96 | 4961 | ret = i915_gem_context_enable(req); |
aa9b7810 CW |
4962 | if (ret) |
4963 | goto err_request; | |
4964 | ||
4965 | err_request: | |
4966 | i915_add_request_no_flush(req); | |
4967 | if (ret) { | |
4968 | DRM_ERROR("Failed to enable %s, error=%d\n", | |
b4ac5afc | 4969 | engine->name, ret); |
117897f4 | 4970 | i915_gem_cleanup_engines(dev); |
aa9b7810 | 4971 | break; |
90638cc1 | 4972 | } |
b7c36d25 | 4973 | } |
e21af88d | 4974 | |
5e4f5189 CW |
4975 | out: |
4976 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4977 | return ret; |
8187a2b7 ZN |
4978 | } |
4979 | ||
1070a42b CW |
4980 | int i915_gem_init(struct drm_device *dev) |
4981 | { | |
4982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4983 | int ret; |
4984 | ||
127f1003 OM |
4985 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4986 | i915.enable_execlists); | |
4987 | ||
1070a42b | 4988 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4989 | |
a83014d3 | 4990 | if (!i915.enable_execlists) { |
f3dc74c0 | 4991 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
117897f4 TU |
4992 | dev_priv->gt.init_engines = i915_gem_init_engines; |
4993 | dev_priv->gt.cleanup_engine = intel_cleanup_engine; | |
4994 | dev_priv->gt.stop_engine = intel_stop_engine; | |
454afebd | 4995 | } else { |
f3dc74c0 | 4996 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
117897f4 TU |
4997 | dev_priv->gt.init_engines = intel_logical_rings_init; |
4998 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; | |
4999 | dev_priv->gt.stop_engine = intel_logical_ring_stop; | |
a83014d3 OM |
5000 | } |
5001 | ||
5e4f5189 CW |
5002 | /* This is just a security blanket to placate dragons. |
5003 | * On some systems, we very sporadically observe that the first TLBs | |
5004 | * used by the CS may be stale, despite us poking the TLB reset. If | |
5005 | * we hold the forcewake during initialisation these problems | |
5006 | * just magically go away. | |
5007 | */ | |
5008 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
5009 | ||
6c5566a8 | 5010 | ret = i915_gem_init_userptr(dev); |
7bcc3777 JN |
5011 | if (ret) |
5012 | goto out_unlock; | |
6c5566a8 | 5013 | |
d85489d3 | 5014 | i915_gem_init_ggtt(dev); |
d62b4892 | 5015 | |
2fa48d8d | 5016 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
5017 | if (ret) |
5018 | goto out_unlock; | |
2fa48d8d | 5019 | |
117897f4 | 5020 | ret = dev_priv->gt.init_engines(dev); |
35a57ffb | 5021 | if (ret) |
7bcc3777 | 5022 | goto out_unlock; |
2fa48d8d | 5023 | |
1070a42b | 5024 | ret = i915_gem_init_hw(dev); |
60990320 CW |
5025 | if (ret == -EIO) { |
5026 | /* Allow ring initialisation to fail by marking the GPU as | |
5027 | * wedged. But we only want to do this where the GPU is angry, | |
5028 | * for all other failure, such as an allocation failure, bail. | |
5029 | */ | |
5030 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 5031 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 5032 | ret = 0; |
1070a42b | 5033 | } |
7bcc3777 JN |
5034 | |
5035 | out_unlock: | |
5e4f5189 | 5036 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 5037 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 5038 | |
60990320 | 5039 | return ret; |
1070a42b CW |
5040 | } |
5041 | ||
8187a2b7 | 5042 | void |
117897f4 | 5043 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 5044 | { |
3e31c6c0 | 5045 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 5046 | struct intel_engine_cs *engine; |
8187a2b7 | 5047 | |
b4ac5afc | 5048 | for_each_engine(engine, dev_priv) |
117897f4 | 5049 | dev_priv->gt.cleanup_engine(engine); |
a647828a | 5050 | |
ee4b6faf MK |
5051 | if (i915.enable_execlists) |
5052 | /* | |
5053 | * Neither the BIOS, ourselves or any other kernel | |
5054 | * expects the system to be in execlists mode on startup, | |
5055 | * so we need to reset the GPU back to legacy mode. | |
5056 | */ | |
5057 | intel_gpu_reset(dev, ALL_ENGINES); | |
8187a2b7 ZN |
5058 | } |
5059 | ||
64193406 | 5060 | static void |
666796da | 5061 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 5062 | { |
0bc40be8 TU |
5063 | INIT_LIST_HEAD(&engine->active_list); |
5064 | INIT_LIST_HEAD(&engine->request_list); | |
64193406 CW |
5065 | } |
5066 | ||
40ae4e16 ID |
5067 | void |
5068 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
5069 | { | |
5070 | struct drm_device *dev = dev_priv->dev; | |
5071 | ||
5072 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
5073 | !IS_CHERRYVIEW(dev_priv)) | |
5074 | dev_priv->num_fence_regs = 32; | |
5075 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
5076 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
5077 | dev_priv->num_fence_regs = 16; | |
5078 | else | |
5079 | dev_priv->num_fence_regs = 8; | |
5080 | ||
5081 | if (intel_vgpu_active(dev)) | |
5082 | dev_priv->num_fence_regs = | |
5083 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
5084 | ||
5085 | /* Initialize fence registers to zero */ | |
5086 | i915_gem_restore_fences(dev); | |
5087 | ||
5088 | i915_gem_detect_bit_6_swizzle(dev); | |
5089 | } | |
5090 | ||
673a394b | 5091 | void |
d64aa096 | 5092 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 5093 | { |
3e31c6c0 | 5094 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
5095 | int i; |
5096 | ||
efab6d8d | 5097 | dev_priv->objects = |
42dcedd4 CW |
5098 | kmem_cache_create("i915_gem_object", |
5099 | sizeof(struct drm_i915_gem_object), 0, | |
5100 | SLAB_HWCACHE_ALIGN, | |
5101 | NULL); | |
e20d2ab7 CW |
5102 | dev_priv->vmas = |
5103 | kmem_cache_create("i915_gem_vma", | |
5104 | sizeof(struct i915_vma), 0, | |
5105 | SLAB_HWCACHE_ALIGN, | |
5106 | NULL); | |
efab6d8d CW |
5107 | dev_priv->requests = |
5108 | kmem_cache_create("i915_gem_request", | |
5109 | sizeof(struct drm_i915_gem_request), 0, | |
5110 | SLAB_HWCACHE_ALIGN, | |
5111 | NULL); | |
673a394b | 5112 | |
fc8c067e | 5113 | INIT_LIST_HEAD(&dev_priv->vm_list); |
a33afea5 | 5114 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
5115 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
5116 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 5117 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
5118 | for (i = 0; i < I915_NUM_ENGINES; i++) |
5119 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 5120 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 5121 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
5122 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
5123 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
5124 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
5125 | i915_gem_idle_work_handler); | |
1f83fee0 | 5126 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 5127 | |
72bfa19c CW |
5128 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
5129 | ||
e84fe803 NH |
5130 | /* |
5131 | * Set initial sequence number for requests. | |
5132 | * Using this number allows the wraparound to happen early, | |
5133 | * catching any obvious problems. | |
5134 | */ | |
5135 | dev_priv->next_seqno = ((u32)~0 - 0x1100); | |
5136 | dev_priv->last_seqno = ((u32)~0 - 0x1101); | |
5137 | ||
19b2dbde | 5138 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 5139 | |
6b95a207 | 5140 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 5141 | |
ce453d81 CW |
5142 | dev_priv->mm.interruptible = true; |
5143 | ||
f99d7069 | 5144 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 5145 | } |
71acb5eb | 5146 | |
d64aa096 ID |
5147 | void i915_gem_load_cleanup(struct drm_device *dev) |
5148 | { | |
5149 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5150 | ||
5151 | kmem_cache_destroy(dev_priv->requests); | |
5152 | kmem_cache_destroy(dev_priv->vmas); | |
5153 | kmem_cache_destroy(dev_priv->objects); | |
5154 | } | |
5155 | ||
f787a5f5 | 5156 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5157 | { |
f787a5f5 | 5158 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
5159 | |
5160 | /* Clean up our request list when the client is going away, so that | |
5161 | * later retire_requests won't dereference our soon-to-be-gone | |
5162 | * file_priv. | |
5163 | */ | |
1c25595f | 5164 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5165 | while (!list_empty(&file_priv->mm.request_list)) { |
5166 | struct drm_i915_gem_request *request; | |
5167 | ||
5168 | request = list_first_entry(&file_priv->mm.request_list, | |
5169 | struct drm_i915_gem_request, | |
5170 | client_list); | |
5171 | list_del(&request->client_list); | |
5172 | request->file_priv = NULL; | |
5173 | } | |
1c25595f | 5174 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 5175 | |
2e1b8730 | 5176 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 5177 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 5178 | list_del(&file_priv->rps.link); |
8d3afd7d | 5179 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 5180 | } |
b29c19b6 CW |
5181 | } |
5182 | ||
5183 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5184 | { | |
5185 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5186 | int ret; |
b29c19b6 CW |
5187 | |
5188 | DRM_DEBUG_DRIVER("\n"); | |
5189 | ||
5190 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5191 | if (!file_priv) | |
5192 | return -ENOMEM; | |
5193 | ||
5194 | file->driver_priv = file_priv; | |
5195 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5196 | file_priv->file = file; |
2e1b8730 | 5197 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
5198 | |
5199 | spin_lock_init(&file_priv->mm.lock); | |
5200 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5201 | |
de1add36 TU |
5202 | file_priv->bsd_ring = -1; |
5203 | ||
e422b888 BW |
5204 | ret = i915_gem_context_open(dev, file); |
5205 | if (ret) | |
5206 | kfree(file_priv); | |
b29c19b6 | 5207 | |
e422b888 | 5208 | return ret; |
b29c19b6 CW |
5209 | } |
5210 | ||
b680c37a DV |
5211 | /** |
5212 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5213 | * @old: current GEM buffer for the frontbuffer slots |
5214 | * @new: new GEM buffer for the frontbuffer slots | |
5215 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5216 | * |
5217 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5218 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5219 | */ | |
a071fa00 DV |
5220 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5221 | struct drm_i915_gem_object *new, | |
5222 | unsigned frontbuffer_bits) | |
5223 | { | |
5224 | if (old) { | |
5225 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5226 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5227 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5228 | } | |
5229 | ||
5230 | if (new) { | |
5231 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5232 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5233 | new->frontbuffer_bits |= frontbuffer_bits; | |
5234 | } | |
5235 | } | |
5236 | ||
a70a3148 | 5237 | /* All the new VM stuff */ |
088e0df4 MT |
5238 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
5239 | struct i915_address_space *vm) | |
a70a3148 BW |
5240 | { |
5241 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5242 | struct i915_vma *vma; | |
5243 | ||
896ab1a5 | 5244 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5245 | |
1c7f4bca | 5246 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5247 | if (vma->is_ggtt && |
ec7adb6e JL |
5248 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5249 | continue; | |
5250 | if (vma->vm == vm) | |
a70a3148 | 5251 | return vma->node.start; |
a70a3148 | 5252 | } |
ec7adb6e | 5253 | |
f25748ea DV |
5254 | WARN(1, "%s vma for this object not found.\n", |
5255 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5256 | return -1; |
5257 | } | |
5258 | ||
088e0df4 MT |
5259 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
5260 | const struct i915_ggtt_view *view) | |
a70a3148 | 5261 | { |
72e96d64 JL |
5262 | struct drm_i915_private *dev_priv = to_i915(o->base.dev); |
5263 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
a70a3148 BW |
5264 | struct i915_vma *vma; |
5265 | ||
1c7f4bca | 5266 | list_for_each_entry(vma, &o->vma_list, obj_link) |
72e96d64 | 5267 | if (vma->vm == &ggtt->base && |
9abc4648 | 5268 | i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e JL |
5269 | return vma->node.start; |
5270 | ||
5678ad73 | 5271 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
5272 | return -1; |
5273 | } | |
5274 | ||
5275 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5276 | struct i915_address_space *vm) | |
5277 | { | |
5278 | struct i915_vma *vma; | |
5279 | ||
1c7f4bca | 5280 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5281 | if (vma->is_ggtt && |
ec7adb6e JL |
5282 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5283 | continue; | |
5284 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
5285 | return true; | |
5286 | } | |
5287 | ||
5288 | return false; | |
5289 | } | |
5290 | ||
5291 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5292 | const struct i915_ggtt_view *view) |
ec7adb6e | 5293 | { |
72e96d64 JL |
5294 | struct drm_i915_private *dev_priv = to_i915(o->base.dev); |
5295 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ec7adb6e JL |
5296 | struct i915_vma *vma; |
5297 | ||
1c7f4bca | 5298 | list_for_each_entry(vma, &o->vma_list, obj_link) |
72e96d64 | 5299 | if (vma->vm == &ggtt->base && |
9abc4648 | 5300 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 5301 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5302 | return true; |
5303 | ||
5304 | return false; | |
5305 | } | |
5306 | ||
5307 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5308 | { | |
5a1d5eb0 | 5309 | struct i915_vma *vma; |
a70a3148 | 5310 | |
1c7f4bca | 5311 | list_for_each_entry(vma, &o->vma_list, obj_link) |
5a1d5eb0 | 5312 | if (drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5313 | return true; |
5314 | ||
5315 | return false; | |
5316 | } | |
5317 | ||
5318 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5319 | struct i915_address_space *vm) | |
5320 | { | |
5321 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5322 | struct i915_vma *vma; | |
5323 | ||
896ab1a5 | 5324 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5325 | |
5326 | BUG_ON(list_empty(&o->vma_list)); | |
5327 | ||
1c7f4bca | 5328 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5329 | if (vma->is_ggtt && |
ec7adb6e JL |
5330 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5331 | continue; | |
a70a3148 BW |
5332 | if (vma->vm == vm) |
5333 | return vma->node.size; | |
ec7adb6e | 5334 | } |
a70a3148 BW |
5335 | return 0; |
5336 | } | |
5337 | ||
ec7adb6e | 5338 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
5339 | { |
5340 | struct i915_vma *vma; | |
1c7f4bca | 5341 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
ec7adb6e JL |
5342 | if (vma->pin_count > 0) |
5343 | return true; | |
a6631ae1 | 5344 | |
ec7adb6e | 5345 | return false; |
5c2abbea | 5346 | } |
ea70299d | 5347 | |
033908ae DG |
5348 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
5349 | struct page * | |
5350 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
5351 | { | |
5352 | struct page *page; | |
5353 | ||
5354 | /* Only default objects have per-page dirty tracking */ | |
de472664 | 5355 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
033908ae DG |
5356 | return NULL; |
5357 | ||
5358 | page = i915_gem_object_get_page(obj, n); | |
5359 | set_page_dirty(page); | |
5360 | return page; | |
5361 | } | |
5362 | ||
ea70299d DG |
5363 | /* Allocate a new GEM object and fill it with the supplied data */ |
5364 | struct drm_i915_gem_object * | |
5365 | i915_gem_object_create_from_data(struct drm_device *dev, | |
5366 | const void *data, size_t size) | |
5367 | { | |
5368 | struct drm_i915_gem_object *obj; | |
5369 | struct sg_table *sg; | |
5370 | size_t bytes; | |
5371 | int ret; | |
5372 | ||
5373 | obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE)); | |
5374 | if (IS_ERR_OR_NULL(obj)) | |
5375 | return obj; | |
5376 | ||
5377 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
5378 | if (ret) | |
5379 | goto fail; | |
5380 | ||
5381 | ret = i915_gem_object_get_pages(obj); | |
5382 | if (ret) | |
5383 | goto fail; | |
5384 | ||
5385 | i915_gem_object_pin_pages(obj); | |
5386 | sg = obj->pages; | |
5387 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 5388 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
5389 | i915_gem_object_unpin_pages(obj); |
5390 | ||
5391 | if (WARN_ON(bytes != size)) { | |
5392 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
5393 | ret = -EFAULT; | |
5394 | goto fail; | |
5395 | } | |
5396 | ||
5397 | return obj; | |
5398 | ||
5399 | fail: | |
5400 | drm_gem_object_unreference(&obj->base); | |
5401 | return ERR_PTR(ret); | |
5402 | } |