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drm/i915: Update write_domains on active list after flush.
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
673a394b 34#include <linux/swap.h>
79e53945 35#include <linux/pci.h>
673a394b 36
28dfe52a
EA		 37#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38
e47c68e9
EA		 39static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 42static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 int write);
44static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
47static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 48static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 49static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 unsigned alignment);
de151cf6 51static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 52static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 53static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 54static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
673a394b 57
31169714
CW		 58static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
79e53945
JB		 61int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
673a394b
EA		 63{
64 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 65
79e53945
JB		 66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 69 return -EINVAL;
70 }
71
79e53945
JB		 72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
673a394b 74
79e53945
JB		 75 dev->gtt_total = (uint32_t) (end - start);
76
77 return 0;
78}
673a394b 79
79e53945
JB		 80int
81i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
83{
84 struct drm_i915_gem_init *args = data;
85 int ret;
86
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 89 mutex_unlock(&dev->struct_mutex);
90
79e53945 91 return ret;
673a394b
EA		 92}
93
5a125c3c
EA		 94int
95i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
97{
5a125c3c 98 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 99
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
102
103 args->aper_size = dev->gtt_total;
2678d9d6
KP		 104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
5a125c3c
EA		 106
107 return 0;
108}
109
673a394b
EA		 110
111/**
112 * Creates a new mm object and returns a handle to it.
113 */
114int
115i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
117{
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
a1a2d1d3
PP		 120 int ret;
121 u32 handle;
673a394b
EA		 122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
134
135 if (ret)
136 return ret;
137
138 args->handle = handle;
139
140 return 0;
141}
142
eb01459f
EA		 143static inline int
144fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
146 char __user *data,
147 int length)
148{
149 char __iomem *vaddr;
2bc43b5c 150 int unwritten;
eb01459f
EA		 151
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 if (vaddr == NULL)
154 return -ENOMEM;
2bc43b5c 155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 156 kunmap_atomic(vaddr, KM_USER0);
157
2bc43b5c
FM		 158 if (unwritten)
159 return -EFAULT;
160
161 return 0;
eb01459f
EA		 162}
163
280b713b
EA		 164static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165{
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
171}
172
40123c1f
EA		 173static inline int
174slow_shmem_copy(struct page *dst_page,
175 int dst_offset,
176 struct page *src_page,
177 int src_offset,
178 int length)
179{
180 char *dst_vaddr, *src_vaddr;
181
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
184 return -ENOMEM;
185
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
189 return -ENOMEM;
190 }
191
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
196
197 return 0;
198}
199
280b713b
EA		 200static inline int
201slow_shmem_bit17_copy(struct page *gpu_page,
202 int gpu_offset,
203 struct page *cpu_page,
204 int cpu_offset,
205 int length,
206 int is_read)
207{
208 char *gpu_vaddr, *cpu_vaddr;
209
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 if (is_read)
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
215 else
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
218 }
219
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
222 return -ENOMEM;
223
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
227 return -ENOMEM;
228 }
229
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 */
233 while (length > 0) {
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238 if (is_read) {
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
241 this_length);
242 } else {
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
245 this_length);
246 }
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
250 }
251
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
254
255 return 0;
256}
257
eb01459f
EA		 258/**
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 */
263static int
264i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
267{
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
269 ssize_t remain;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
273 int ret;
274
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 remain = args->size;
277
278 mutex_lock(&dev->struct_mutex);
279
4bdadb97 280 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 281 if (ret != 0)
282 goto fail_unlock;
283
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285 args->size);
286 if (ret != 0)
287 goto fail_put_pages;
288
289 obj_priv = obj->driver_private;
290 offset = args->offset;
291
292 while (remain > 0) {
293 /* Operation in this page
294 *
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
298 */
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
304
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
308 if (ret)
309 goto fail_put_pages;
310
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
314 }
315
316fail_put_pages:
317 i915_gem_object_put_pages(obj);
318fail_unlock:
319 mutex_unlock(&dev->struct_mutex);
320
321 return ret;
322}
323
07f73f69
CW		 324static int
325i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
326{
327 int ret;
328
4bdadb97 329 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 330
331 /* If we've insufficient memory to map in the pages, attempt
332 * to make some space by throwing out some old buffers.
333 */
334 if (ret == -ENOMEM) {
335 struct drm_device *dev = obj->dev;
07f73f69
CW		 336
337 ret = i915_gem_evict_something(dev, obj->size);
338 if (ret)
339 return ret;
340
4bdadb97 341 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 342 }
343
344 return ret;
345}
346
eb01459f
EA		 347/**
348 * This is the fallback shmem pread path, which allocates temporary storage
349 * in kernel space to copy_to_user into outside of the struct_mutex, so we
350 * can copy out of the object's backing pages while holding the struct mutex
351 * and not take page faults.
352 */
353static int
354i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
355 struct drm_i915_gem_pread *args,
356 struct drm_file *file_priv)
357{
358 struct drm_i915_gem_object *obj_priv = obj->driver_private;
359 struct mm_struct *mm = current->mm;
360 struct page **user_pages;
361 ssize_t remain;
362 loff_t offset, pinned_pages, i;
363 loff_t first_data_page, last_data_page, num_pages;
364 int shmem_page_index, shmem_page_offset;
365 int data_page_index, data_page_offset;
366 int page_length;
367 int ret;
368 uint64_t data_ptr = args->data_ptr;
280b713b 369 int do_bit17_swizzling;
eb01459f
EA		 370
371 remain = args->size;
372
373 /* Pin the user pages containing the data. We can't fault while
374 * holding the struct mutex, yet we want to hold it while
375 * dereferencing the user data.
376 */
377 first_data_page = data_ptr / PAGE_SIZE;
378 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
379 num_pages = last_data_page - first_data_page + 1;
380
8e7d2b2c 381 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 382 if (user_pages == NULL)
383 return -ENOMEM;
384
385 down_read(&mm->mmap_sem);
386 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 387 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 388 up_read(&mm->mmap_sem);
389 if (pinned_pages < num_pages) {
390 ret = -EFAULT;
391 goto fail_put_user_pages;
392 }
393
280b713b
EA		 394 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
395
eb01459f
EA		 396 mutex_lock(&dev->struct_mutex);
397
07f73f69
CW		 398 ret = i915_gem_object_get_pages_or_evict(obj);
399 if (ret)
eb01459f
EA		 400 goto fail_unlock;
401
402 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
403 args->size);
404 if (ret != 0)
405 goto fail_put_pages;
406
407 obj_priv = obj->driver_private;
408 offset = args->offset;
409
410 while (remain > 0) {
411 /* Operation in this page
412 *
413 * shmem_page_index = page number within shmem file
414 * shmem_page_offset = offset within page in shmem file
415 * data_page_index = page number in get_user_pages return
416 * data_page_offset = offset with data_page_index page.
417 * page_length = bytes to copy for this page
418 */
419 shmem_page_index = offset / PAGE_SIZE;
420 shmem_page_offset = offset & ~PAGE_MASK;
421 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
422 data_page_offset = data_ptr & ~PAGE_MASK;
423
424 page_length = remain;
425 if ((shmem_page_offset + page_length) > PAGE_SIZE)
426 page_length = PAGE_SIZE - shmem_page_offset;
427 if ((data_page_offset + page_length) > PAGE_SIZE)
428 page_length = PAGE_SIZE - data_page_offset;
429
280b713b
EA		 430 if (do_bit17_swizzling) {
431 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
432 shmem_page_offset,
433 user_pages[data_page_index],
434 data_page_offset,
435 page_length,
436 1);
437 } else {
438 ret = slow_shmem_copy(user_pages[data_page_index],
439 data_page_offset,
440 obj_priv->pages[shmem_page_index],
441 shmem_page_offset,
442 page_length);
443 }
eb01459f
EA		 444 if (ret)
445 goto fail_put_pages;
446
447 remain -= page_length;
448 data_ptr += page_length;
449 offset += page_length;
450 }
451
452fail_put_pages:
453 i915_gem_object_put_pages(obj);
454fail_unlock:
455 mutex_unlock(&dev->struct_mutex);
456fail_put_user_pages:
457 for (i = 0; i < pinned_pages; i++) {
458 SetPageDirty(user_pages[i]);
459 page_cache_release(user_pages[i]);
460 }
8e7d2b2c 461 drm_free_large(user_pages);
eb01459f
EA		 462
463 return ret;
464}
465
673a394b
EA		 466/**
467 * Reads data from the object referenced by handle.
468 *
469 * On error, the contents of *data are undefined.
470 */
471int
472i915_gem_pread_ioctl(struct drm_device *dev, void *data,
473 struct drm_file *file_priv)
474{
475 struct drm_i915_gem_pread *args = data;
476 struct drm_gem_object *obj;
477 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 478 int ret;
479
480 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
481 if (obj == NULL)
482 return -EBADF;
483 obj_priv = obj->driver_private;
484
485 /* Bounds check source.
486 *
487 * XXX: This could use review for overflow issues...
488 */
489 if (args->offset > obj->size || args->size > obj->size ||
490 args->offset + args->size > obj->size) {
491 drm_gem_object_unreference(obj);
492 return -EINVAL;
493 }
494
280b713b 495 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 496 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 497 } else {
498 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
499 if (ret != 0)
500 ret = i915_gem_shmem_pread_slow(dev, obj, args,
501 file_priv);
502 }
673a394b
EA		 503
504 drm_gem_object_unreference(obj);
673a394b 505
eb01459f 506 return ret;
673a394b
EA		 507}
508
0839ccb8
KP		 509/* This is the fast write path which cannot handle
510 * page faults in the source data
9b7530cc 511 */
0839ccb8
KP		 512
513static inline int
514fast_user_write(struct io_mapping *mapping,
515 loff_t page_base, int page_offset,
516 char __user *user_data,
517 int length)
9b7530cc 518{
9b7530cc 519 char *vaddr_atomic;
0839ccb8 520 unsigned long unwritten;
9b7530cc 521
0839ccb8
KP		 522 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
523 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
524 user_data, length);
525 io_mapping_unmap_atomic(vaddr_atomic);
526 if (unwritten)
527 return -EFAULT;
528 return 0;
529}
530
531/* Here's the write path which can sleep for
532 * page faults
533 */
534
535static inline int
3de09aa3
EA		 536slow_kernel_write(struct io_mapping *mapping,
537 loff_t gtt_base, int gtt_offset,
538 struct page *user_page, int user_offset,
539 int length)
0839ccb8 540{
3de09aa3 541 char *src_vaddr, *dst_vaddr;
0839ccb8
KP		 542 unsigned long unwritten;
543
3de09aa3
EA		 544 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
545 src_vaddr = kmap_atomic(user_page, KM_USER1);
546 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
547 src_vaddr + user_offset,
548 length);
549 kunmap_atomic(src_vaddr, KM_USER1);
550 io_mapping_unmap_atomic(dst_vaddr);
0839ccb8
KP		 551 if (unwritten)
552 return -EFAULT;
9b7530cc 553 return 0;
9b7530cc
LT		 554}
555
40123c1f
EA		 556static inline int
557fast_shmem_write(struct page **pages,
558 loff_t page_base, int page_offset,
559 char __user *data,
560 int length)
561{
562 char __iomem *vaddr;
d0088775 563 unsigned long unwritten;
40123c1f
EA		 564
565 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
566 if (vaddr == NULL)
567 return -ENOMEM;
d0088775 568 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 569 kunmap_atomic(vaddr, KM_USER0);
570
d0088775
DA		 571 if (unwritten)
572 return -EFAULT;
40123c1f
EA		 573 return 0;
574}
575
3de09aa3
EA		 576/**
577 * This is the fast pwrite path, where we copy the data directly from the
578 * user into the GTT, uncached.
579 */
673a394b 580static int
3de09aa3
EA		 581i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
582 struct drm_i915_gem_pwrite *args,
583 struct drm_file *file_priv)
673a394b
EA		 584{
585 struct drm_i915_gem_object *obj_priv = obj->driver_private;
0839ccb8 586 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 587 ssize_t remain;
0839ccb8 588 loff_t offset, page_base;
673a394b 589 char __user *user_data;
0839ccb8
KP		 590 int page_offset, page_length;
591 int ret;
673a394b
EA		 592
593 user_data = (char __user *) (uintptr_t) args->data_ptr;
594 remain = args->size;
595 if (!access_ok(VERIFY_READ, user_data, remain))
596 return -EFAULT;
597
598
599 mutex_lock(&dev->struct_mutex);
600 ret = i915_gem_object_pin(obj, 0);
601 if (ret) {
602 mutex_unlock(&dev->struct_mutex);
603 return ret;
604 }
2ef7eeaa 605 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 606 if (ret)
607 goto fail;
608
609 obj_priv = obj->driver_private;
610 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 611
612 while (remain > 0) {
613 /* Operation in this page
614 *
0839ccb8
KP		 615 * page_base = page offset within aperture
616 * page_offset = offset within page
617 * page_length = bytes to copy for this page
673a394b 618 */
0839ccb8
KP		 619 page_base = (offset & ~(PAGE_SIZE-1));
620 page_offset = offset & (PAGE_SIZE-1);
621 page_length = remain;
622 if ((page_offset + remain) > PAGE_SIZE)
623 page_length = PAGE_SIZE - page_offset;
624
625 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
626 page_offset, user_data, page_length);
627
628 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 629 * source page isn't available. Return the error and we'll
630 * retry in the slow path.
0839ccb8 631 */
3de09aa3
EA		 632 if (ret)
633 goto fail;
673a394b 634
0839ccb8
KP		 635 remain -= page_length;
636 user_data += page_length;
637 offset += page_length;
673a394b 638 }
673a394b
EA		 639
640fail:
641 i915_gem_object_unpin(obj);
642 mutex_unlock(&dev->struct_mutex);
643
644 return ret;
645}
646
3de09aa3
EA		 647/**
648 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
649 * the memory and maps it using kmap_atomic for copying.
650 *
651 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
652 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
653 */
3043c60c 654static int
3de09aa3
EA		 655i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
656 struct drm_i915_gem_pwrite *args,
657 struct drm_file *file_priv)
673a394b 658{
3de09aa3
EA		 659 struct drm_i915_gem_object *obj_priv = obj->driver_private;
660 drm_i915_private_t *dev_priv = dev->dev_private;
661 ssize_t remain;
662 loff_t gtt_page_base, offset;
663 loff_t first_data_page, last_data_page, num_pages;
664 loff_t pinned_pages, i;
665 struct page **user_pages;
666 struct mm_struct *mm = current->mm;
667 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 668 int ret;
3de09aa3
EA		 669 uint64_t data_ptr = args->data_ptr;
670
671 remain = args->size;
672
673 /* Pin the user pages containing the data. We can't fault while
674 * holding the struct mutex, and all of the pwrite implementations
675 * want to hold it while dereferencing the user data.
676 */
677 first_data_page = data_ptr / PAGE_SIZE;
678 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
679 num_pages = last_data_page - first_data_page + 1;
680
8e7d2b2c 681 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 682 if (user_pages == NULL)
683 return -ENOMEM;
684
685 down_read(&mm->mmap_sem);
686 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
687 num_pages, 0, 0, user_pages, NULL);
688 up_read(&mm->mmap_sem);
689 if (pinned_pages < num_pages) {
690 ret = -EFAULT;
691 goto out_unpin_pages;
692 }
673a394b
EA		 693
694 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 695 ret = i915_gem_object_pin(obj, 0);
696 if (ret)
697 goto out_unlock;
698
699 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
700 if (ret)
701 goto out_unpin_object;
702
703 obj_priv = obj->driver_private;
704 offset = obj_priv->gtt_offset + args->offset;
705
706 while (remain > 0) {
707 /* Operation in this page
708 *
709 * gtt_page_base = page offset within aperture
710 * gtt_page_offset = offset within page in aperture
711 * data_page_index = page number in get_user_pages return
712 * data_page_offset = offset with data_page_index page.
713 * page_length = bytes to copy for this page
714 */
715 gtt_page_base = offset & PAGE_MASK;
716 gtt_page_offset = offset & ~PAGE_MASK;
717 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
718 data_page_offset = data_ptr & ~PAGE_MASK;
719
720 page_length = remain;
721 if ((gtt_page_offset + page_length) > PAGE_SIZE)
722 page_length = PAGE_SIZE - gtt_page_offset;
723 if ((data_page_offset + page_length) > PAGE_SIZE)
724 page_length = PAGE_SIZE - data_page_offset;
725
726 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
727 gtt_page_base, gtt_page_offset,
728 user_pages[data_page_index],
729 data_page_offset,
730 page_length);
731
732 /* If we get a fault while copying data, then (presumably) our
733 * source page isn't available. Return the error and we'll
734 * retry in the slow path.
735 */
736 if (ret)
737 goto out_unpin_object;
738
739 remain -= page_length;
740 offset += page_length;
741 data_ptr += page_length;
742 }
743
744out_unpin_object:
745 i915_gem_object_unpin(obj);
746out_unlock:
747 mutex_unlock(&dev->struct_mutex);
748out_unpin_pages:
749 for (i = 0; i < pinned_pages; i++)
750 page_cache_release(user_pages[i]);
8e7d2b2c 751 drm_free_large(user_pages);
3de09aa3
EA		 752
753 return ret;
754}
755
40123c1f
EA		 756/**
757 * This is the fast shmem pwrite path, which attempts to directly
758 * copy_from_user into the kmapped pages backing the object.
759 */
3043c60c 760static int
40123c1f
EA		 761i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
762 struct drm_i915_gem_pwrite *args,
763 struct drm_file *file_priv)
673a394b 764{
40123c1f
EA		 765 struct drm_i915_gem_object *obj_priv = obj->driver_private;
766 ssize_t remain;
767 loff_t offset, page_base;
768 char __user *user_data;
769 int page_offset, page_length;
673a394b 770 int ret;
40123c1f
EA		 771
772 user_data = (char __user *) (uintptr_t) args->data_ptr;
773 remain = args->size;
673a394b
EA		 774
775 mutex_lock(&dev->struct_mutex);
776
4bdadb97 777 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 778 if (ret != 0)
779 goto fail_unlock;
673a394b 780
e47c68e9 781 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 782 if (ret != 0)
783 goto fail_put_pages;
784
785 obj_priv = obj->driver_private;
786 offset = args->offset;
787 obj_priv->dirty = 1;
788
789 while (remain > 0) {
790 /* Operation in this page
791 *
792 * page_base = page offset within aperture
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
795 */
796 page_base = (offset & ~(PAGE_SIZE-1));
797 page_offset = offset & (PAGE_SIZE-1);
798 page_length = remain;
799 if ((page_offset + remain) > PAGE_SIZE)
800 page_length = PAGE_SIZE - page_offset;
801
802 ret = fast_shmem_write(obj_priv->pages,
803 page_base, page_offset,
804 user_data, page_length);
805 if (ret)
806 goto fail_put_pages;
807
808 remain -= page_length;
809 user_data += page_length;
810 offset += page_length;
811 }
812
813fail_put_pages:
814 i915_gem_object_put_pages(obj);
815fail_unlock:
816 mutex_unlock(&dev->struct_mutex);
817
818 return ret;
819}
820
821/**
822 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
823 * the memory and maps it using kmap_atomic for copying.
824 *
825 * This avoids taking mmap_sem for faulting on the user's address while the
826 * struct_mutex is held.
827 */
828static int
829i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
830 struct drm_i915_gem_pwrite *args,
831 struct drm_file *file_priv)
832{
833 struct drm_i915_gem_object *obj_priv = obj->driver_private;
834 struct mm_struct *mm = current->mm;
835 struct page **user_pages;
836 ssize_t remain;
837 loff_t offset, pinned_pages, i;
838 loff_t first_data_page, last_data_page, num_pages;
839 int shmem_page_index, shmem_page_offset;
840 int data_page_index, data_page_offset;
841 int page_length;
842 int ret;
843 uint64_t data_ptr = args->data_ptr;
280b713b 844 int do_bit17_swizzling;
40123c1f
EA		 845
846 remain = args->size;
847
848 /* Pin the user pages containing the data. We can't fault while
849 * holding the struct mutex, and all of the pwrite implementations
850 * want to hold it while dereferencing the user data.
851 */
852 first_data_page = data_ptr / PAGE_SIZE;
853 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
854 num_pages = last_data_page - first_data_page + 1;
855
8e7d2b2c 856 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 857 if (user_pages == NULL)
858 return -ENOMEM;
859
860 down_read(&mm->mmap_sem);
861 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
862 num_pages, 0, 0, user_pages, NULL);
863 up_read(&mm->mmap_sem);
864 if (pinned_pages < num_pages) {
865 ret = -EFAULT;
866 goto fail_put_user_pages;
673a394b
EA		 867 }
868
280b713b
EA		 869 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
870
40123c1f
EA		 871 mutex_lock(&dev->struct_mutex);
872
07f73f69
CW		 873 ret = i915_gem_object_get_pages_or_evict(obj);
874 if (ret)
40123c1f
EA		 875 goto fail_unlock;
876
877 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
878 if (ret != 0)
879 goto fail_put_pages;
880
881 obj_priv = obj->driver_private;
673a394b 882 offset = args->offset;
40123c1f 883 obj_priv->dirty = 1;
673a394b 884
40123c1f
EA		 885 while (remain > 0) {
886 /* Operation in this page
887 *
888 * shmem_page_index = page number within shmem file
889 * shmem_page_offset = offset within page in shmem file
890 * data_page_index = page number in get_user_pages return
891 * data_page_offset = offset with data_page_index page.
892 * page_length = bytes to copy for this page
893 */
894 shmem_page_index = offset / PAGE_SIZE;
895 shmem_page_offset = offset & ~PAGE_MASK;
896 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
897 data_page_offset = data_ptr & ~PAGE_MASK;
898
899 page_length = remain;
900 if ((shmem_page_offset + page_length) > PAGE_SIZE)
901 page_length = PAGE_SIZE - shmem_page_offset;
902 if ((data_page_offset + page_length) > PAGE_SIZE)
903 page_length = PAGE_SIZE - data_page_offset;
904
280b713b
EA		 905 if (do_bit17_swizzling) {
906 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
907 shmem_page_offset,
908 user_pages[data_page_index],
909 data_page_offset,
910 page_length,
911 0);
912 } else {
913 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
914 shmem_page_offset,
915 user_pages[data_page_index],
916 data_page_offset,
917 page_length);
918 }
40123c1f
EA		 919 if (ret)
920 goto fail_put_pages;
921
922 remain -= page_length;
923 data_ptr += page_length;
924 offset += page_length;
673a394b
EA		 925 }
926
40123c1f
EA		 927fail_put_pages:
928 i915_gem_object_put_pages(obj);
929fail_unlock:
673a394b 930 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 931fail_put_user_pages:
932 for (i = 0; i < pinned_pages; i++)
933 page_cache_release(user_pages[i]);
8e7d2b2c 934 drm_free_large(user_pages);
673a394b 935
40123c1f 936 return ret;
673a394b
EA		 937}
938
939/**
940 * Writes data to the object referenced by handle.
941 *
942 * On error, the contents of the buffer that were to be modified are undefined.
943 */
944int
945i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
946 struct drm_file *file_priv)
947{
948 struct drm_i915_gem_pwrite *args = data;
949 struct drm_gem_object *obj;
950 struct drm_i915_gem_object *obj_priv;
951 int ret = 0;
952
953 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
954 if (obj == NULL)
955 return -EBADF;
956 obj_priv = obj->driver_private;
957
958 /* Bounds check destination.
959 *
960 * XXX: This could use review for overflow issues...
961 */
962 if (args->offset > obj->size || args->size > obj->size ||
963 args->offset + args->size > obj->size) {
964 drm_gem_object_unreference(obj);
965 return -EINVAL;
966 }
967
968 /* We can only do the GTT pwrite on untiled buffers, as otherwise
969 * it would end up going through the fenced access, and we'll get
970 * different detiling behavior between reading and writing.
971 * pread/pwrite currently are reading and writing from the CPU
972 * perspective, requiring manual detiling by the client.
973 */
71acb5eb
DA		 974 if (obj_priv->phys_obj)
975 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
976 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
3de09aa3
EA		 977 dev->gtt_total != 0) {
978 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
979 if (ret == -EFAULT) {
980 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
981 file_priv);
982 }
280b713b
EA		 983 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
984 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 985 } else {
986 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
987 if (ret == -EFAULT) {
988 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
989 file_priv);
990 }
991 }
673a394b
EA		 992
993#if WATCH_PWRITE
994 if (ret)
995 DRM_INFO("pwrite failed %d\n", ret);
996#endif
997
998 drm_gem_object_unreference(obj);
999
1000 return ret;
1001}
1002
1003/**
2ef7eeaa
EA		 1004 * Called when user space prepares to use an object with the CPU, either
1005 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1006 */
1007int
1008i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv)
1010{
a09ba7fa 1011 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1012 struct drm_i915_gem_set_domain *args = data;
1013 struct drm_gem_object *obj;
652c393a 1014 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1015 uint32_t read_domains = args->read_domains;
1016 uint32_t write_domain = args->write_domain;
673a394b
EA		 1017 int ret;
1018
1019 if (!(dev->driver->driver_features & DRIVER_GEM))
1020 return -ENODEV;
1021
2ef7eeaa 1022 /* Only handle setting domains to types used by the CPU. */
21d509e3 1023 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1024 return -EINVAL;
1025
21d509e3 1026 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1027 return -EINVAL;
1028
1029 /* Having something in the write domain implies it's in the read
1030 * domain, and only that read domain. Enforce that in the request.
1031 */
1032 if (write_domain != 0 && read_domains != write_domain)
1033 return -EINVAL;
1034
673a394b
EA		 1035 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1036 if (obj == NULL)
1037 return -EBADF;
652c393a 1038 obj_priv = obj->driver_private;
673a394b
EA		 1039
1040 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1041
1042 intel_mark_busy(dev, obj);
1043
673a394b 1044#if WATCH_BUF
cfd43c02 1045 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1046 obj, obj->size, read_domains, write_domain);
673a394b 1047#endif
2ef7eeaa
EA		 1048 if (read_domains & I915_GEM_DOMAIN_GTT) {
1049 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1050
a09ba7fa
EA		 1051 /* Update the LRU on the fence for the CPU access that's
1052 * about to occur.
1053 */
1054 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1055 list_move_tail(&obj_priv->fence_list,
1056 &dev_priv->mm.fence_list);
1057 }
1058
02354392
EA		 1059 /* Silently promote "you're not bound, there was nothing to do"
1060 * to success, since the client was just asking us to
1061 * make sure everything was done.
1062 */
1063 if (ret == -EINVAL)
1064 ret = 0;
2ef7eeaa 1065 } else {
e47c68e9 1066 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1067 }
1068
673a394b
EA		 1069 drm_gem_object_unreference(obj);
1070 mutex_unlock(&dev->struct_mutex);
1071 return ret;
1072}
1073
1074/**
1075 * Called when user space has done writes to this buffer
1076 */
1077int
1078i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv)
1080{
1081 struct drm_i915_gem_sw_finish *args = data;
1082 struct drm_gem_object *obj;
1083 struct drm_i915_gem_object *obj_priv;
1084 int ret = 0;
1085
1086 if (!(dev->driver->driver_features & DRIVER_GEM))
1087 return -ENODEV;
1088
1089 mutex_lock(&dev->struct_mutex);
1090 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091 if (obj == NULL) {
1092 mutex_unlock(&dev->struct_mutex);
1093 return -EBADF;
1094 }
1095
1096#if WATCH_BUF
cfd43c02 1097 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1098 __func__, args->handle, obj, obj->size);
1099#endif
1100 obj_priv = obj->driver_private;
1101
1102 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1103 if (obj_priv->pin_count)
1104 i915_gem_object_flush_cpu_write_domain(obj);
1105
673a394b
EA		 1106 drm_gem_object_unreference(obj);
1107 mutex_unlock(&dev->struct_mutex);
1108 return ret;
1109}
1110
1111/**
1112 * Maps the contents of an object, returning the address it is mapped
1113 * into.
1114 *
1115 * While the mapping holds a reference on the contents of the object, it doesn't
1116 * imply a ref on the object itself.
1117 */
1118int
1119i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv)
1121{
1122 struct drm_i915_gem_mmap *args = data;
1123 struct drm_gem_object *obj;
1124 loff_t offset;
1125 unsigned long addr;
1126
1127 if (!(dev->driver->driver_features & DRIVER_GEM))
1128 return -ENODEV;
1129
1130 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1131 if (obj == NULL)
1132 return -EBADF;
1133
1134 offset = args->offset;
1135
1136 down_write(&current->mm->mmap_sem);
1137 addr = do_mmap(obj->filp, 0, args->size,
1138 PROT_READ | PROT_WRITE, MAP_SHARED,
1139 args->offset);
1140 up_write(&current->mm->mmap_sem);
1141 mutex_lock(&dev->struct_mutex);
1142 drm_gem_object_unreference(obj);
1143 mutex_unlock(&dev->struct_mutex);
1144 if (IS_ERR((void *)addr))
1145 return addr;
1146
1147 args->addr_ptr = (uint64_t) addr;
1148
1149 return 0;
1150}
1151
de151cf6
JB		 1152/**
1153 * i915_gem_fault - fault a page into the GTT
1154 * vma: VMA in question
1155 * vmf: fault info
1156 *
1157 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1158 * from userspace. The fault handler takes care of binding the object to
1159 * the GTT (if needed), allocating and programming a fence register (again,
1160 * only if needed based on whether the old reg is still valid or the object
1161 * is tiled) and inserting a new PTE into the faulting process.
1162 *
1163 * Note that the faulting process may involve evicting existing objects
1164 * from the GTT and/or fence registers to make room. So performance may
1165 * suffer if the GTT working set is large or there are few fence registers
1166 * left.
1167 */
1168int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1169{
1170 struct drm_gem_object *obj = vma->vm_private_data;
1171 struct drm_device *dev = obj->dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1174 pgoff_t page_offset;
1175 unsigned long pfn;
1176 int ret = 0;
0f973f27 1177 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1178
1179 /* We don't use vmf->pgoff since that has the fake offset */
1180 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1181 PAGE_SHIFT;
1182
1183 /* Now bind it into the GTT if needed */
1184 mutex_lock(&dev->struct_mutex);
1185 if (!obj_priv->gtt_space) {
e67b8ce1 1186 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1187 if (ret)
1188 goto unlock;
07f4f3e8 1189
14b60391 1190 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1191
1192 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1193 if (ret)
1194 goto unlock;
de151cf6
JB		 1195 }
1196
1197 /* Need a new fence register? */
a09ba7fa 1198 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1199 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1200 if (ret)
1201 goto unlock;
d9ddcb96 1202 }
de151cf6
JB		 1203
1204 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1205 page_offset;
1206
1207 /* Finally, remap it using the new GTT offset */
1208 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1209unlock:
de151cf6
JB		 1210 mutex_unlock(&dev->struct_mutex);
1211
1212 switch (ret) {
c715089f
CW		 1213 case 0:
1214 case -ERESTARTSYS:
1215 return VM_FAULT_NOPAGE;
de151cf6
JB		 1216 case -ENOMEM:
1217 case -EAGAIN:
1218 return VM_FAULT_OOM;
de151cf6 1219 default:
c715089f 1220 return VM_FAULT_SIGBUS;
de151cf6
JB		 1221 }
1222}
1223
1224/**
1225 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1226 * @obj: obj in question
1227 *
1228 * GEM memory mapping works by handing back to userspace a fake mmap offset
1229 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1230 * up the object based on the offset and sets up the various memory mapping
1231 * structures.
1232 *
1233 * This routine allocates and attaches a fake offset for @obj.
1234 */
1235static int
1236i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1237{
1238 struct drm_device *dev = obj->dev;
1239 struct drm_gem_mm *mm = dev->mm_private;
1240 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1241 struct drm_map_list *list;
f77d390c 1242 struct drm_local_map *map;
de151cf6
JB		 1243 int ret = 0;
1244
1245 /* Set the object up for mmap'ing */
1246 list = &obj->map_list;
9a298b2a 1247 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1248 if (!list->map)
1249 return -ENOMEM;
1250
1251 map = list->map;
1252 map->type = _DRM_GEM;
1253 map->size = obj->size;
1254 map->handle = obj;
1255
1256 /* Get a DRM GEM mmap offset allocated... */
1257 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1258 obj->size / PAGE_SIZE, 0, 0);
1259 if (!list->file_offset_node) {
1260 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1261 ret = -ENOMEM;
1262 goto out_free_list;
1263 }
1264
1265 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1266 obj->size / PAGE_SIZE, 0);
1267 if (!list->file_offset_node) {
1268 ret = -ENOMEM;
1269 goto out_free_list;
1270 }
1271
1272 list->hash.key = list->file_offset_node->start;
1273 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1274 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1275 ret = -ENOMEM;
de151cf6
JB		 1276 goto out_free_mm;
1277 }
1278
1279 /* By now we should be all set, any drm_mmap request on the offset
1280 * below will get to our mmap & fault handler */
1281 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1282
1283 return 0;
1284
1285out_free_mm:
1286 drm_mm_put_block(list->file_offset_node);
1287out_free_list:
9a298b2a 1288 kfree(list->map);
de151cf6
JB		 1289
1290 return ret;
1291}
1292
901782b2
CW		 1293/**
1294 * i915_gem_release_mmap - remove physical page mappings
1295 * @obj: obj in question
1296 *
af901ca1 1297 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1298 * relinquish ownership of the pages back to the system.
1299 *
1300 * It is vital that we remove the page mapping if we have mapped a tiled
1301 * object through the GTT and then lose the fence register due to
1302 * resource pressure. Similarly if the object has been moved out of the
1303 * aperture, than pages mapped into userspace must be revoked. Removing the
1304 * mapping will then trigger a page fault on the next user access, allowing
1305 * fixup by i915_gem_fault().
1306 */
d05ca301 1307void
901782b2
CW		 1308i915_gem_release_mmap(struct drm_gem_object *obj)
1309{
1310 struct drm_device *dev = obj->dev;
1311 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1312
1313 if (dev->dev_mapping)
1314 unmap_mapping_range(dev->dev_mapping,
1315 obj_priv->mmap_offset, obj->size, 1);
1316}
1317
ab00b3e5
JB		 1318static void
1319i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1320{
1321 struct drm_device *dev = obj->dev;
1322 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1323 struct drm_gem_mm *mm = dev->mm_private;
1324 struct drm_map_list *list;
1325
1326 list = &obj->map_list;
1327 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1328
1329 if (list->file_offset_node) {
1330 drm_mm_put_block(list->file_offset_node);
1331 list->file_offset_node = NULL;
1332 }
1333
1334 if (list->map) {
9a298b2a 1335 kfree(list->map);
ab00b3e5
JB		 1336 list->map = NULL;
1337 }
1338
1339 obj_priv->mmap_offset = 0;
1340}
1341
de151cf6
JB		 1342/**
1343 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1344 * @obj: object to check
1345 *
1346 * Return the required GTT alignment for an object, taking into account
1347 * potential fence register mapping if needed.
1348 */
1349static uint32_t
1350i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1351{
1352 struct drm_device *dev = obj->dev;
1353 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1354 int start, i;
1355
1356 /*
1357 * Minimum alignment is 4k (GTT page size), but might be greater
1358 * if a fence register is needed for the object.
1359 */
1360 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361 return 4096;
1362
1363 /*
1364 * Previous chips need to be aligned to the size of the smallest
1365 * fence register that can contain the object.
1366 */
1367 if (IS_I9XX(dev))
1368 start = 1024*1024;
1369 else
1370 start = 512*1024;
1371
1372 for (i = start; i < obj->size; i <<= 1)
1373 ;
1374
1375 return i;
1376}
1377
1378/**
1379 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1380 * @dev: DRM device
1381 * @data: GTT mapping ioctl data
1382 * @file_priv: GEM object info
1383 *
1384 * Simply returns the fake offset to userspace so it can mmap it.
1385 * The mmap call will end up in drm_gem_mmap(), which will set things
1386 * up so we can get faults in the handler above.
1387 *
1388 * The fault handler will take care of binding the object into the GTT
1389 * (since it may have been evicted to make room for something), allocating
1390 * a fence register, and mapping the appropriate aperture address into
1391 * userspace.
1392 */
1393int
1394i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1395 struct drm_file *file_priv)
1396{
1397 struct drm_i915_gem_mmap_gtt *args = data;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 struct drm_gem_object *obj;
1400 struct drm_i915_gem_object *obj_priv;
1401 int ret;
1402
1403 if (!(dev->driver->driver_features & DRIVER_GEM))
1404 return -ENODEV;
1405
1406 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407 if (obj == NULL)
1408 return -EBADF;
1409
1410 mutex_lock(&dev->struct_mutex);
1411
1412 obj_priv = obj->driver_private;
1413
ab18282d
CW		 1414 if (obj_priv->madv != I915_MADV_WILLNEED) {
1415 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1416 drm_gem_object_unreference(obj);
1417 mutex_unlock(&dev->struct_mutex);
1418 return -EINVAL;
1419 }
1420
1421
de151cf6
JB		 1422 if (!obj_priv->mmap_offset) {
1423 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1424 if (ret) {
1425 drm_gem_object_unreference(obj);
1426 mutex_unlock(&dev->struct_mutex);
de151cf6 1427 return ret;
13af1062 1428 }
de151cf6
JB		 1429 }
1430
1431 args->offset = obj_priv->mmap_offset;
1432
de151cf6
JB		 1433 /*
1434 * Pull it into the GTT so that we have a page list (makes the
1435 * initial fault faster and any subsequent flushing possible).
1436 */
1437 if (!obj_priv->agp_mem) {
e67b8ce1 1438 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1439 if (ret) {
1440 drm_gem_object_unreference(obj);
1441 mutex_unlock(&dev->struct_mutex);
1442 return ret;
1443 }
14b60391 1444 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1445 }
1446
1447 drm_gem_object_unreference(obj);
1448 mutex_unlock(&dev->struct_mutex);
1449
1450 return 0;
1451}
1452
6911a9b8 1453void
856fa198 1454i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b
EA		 1455{
1456 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457 int page_count = obj->size / PAGE_SIZE;
1458 int i;
1459
856fa198 1460 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1461 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1462
856fa198
EA		 1463 if (--obj_priv->pages_refcount != 0)
1464 return;
673a394b 1465
280b713b
EA		 1466 if (obj_priv->tiling_mode != I915_TILING_NONE)
1467 i915_gem_object_save_bit_17_swizzle(obj);
1468
3ef94daa 1469 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1470 obj_priv->dirty = 0;
3ef94daa
CW		 1471
1472 for (i = 0; i < page_count; i++) {
1473 if (obj_priv->pages[i] == NULL)
1474 break;
1475
1476 if (obj_priv->dirty)
1477 set_page_dirty(obj_priv->pages[i]);
1478
1479 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1480 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1481
1482 page_cache_release(obj_priv->pages[i]);
1483 }
673a394b
EA		 1484 obj_priv->dirty = 0;
1485
8e7d2b2c 1486 drm_free_large(obj_priv->pages);
856fa198 1487 obj_priv->pages = NULL;
673a394b
EA		 1488}
1489
1490static void
ce44b0ea 1491i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
673a394b
EA		 1492{
1493 struct drm_device *dev = obj->dev;
1494 drm_i915_private_t *dev_priv = dev->dev_private;
1495 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1496
1497 /* Add a reference if we're newly entering the active list. */
1498 if (!obj_priv->active) {
1499 drm_gem_object_reference(obj);
1500 obj_priv->active = 1;
1501 }
1502 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1503 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1504 list_move_tail(&obj_priv->list,
1505 &dev_priv->mm.active_list);
5e118f41 1506 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1507 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1508}
1509
ce44b0ea
EA		 1510static void
1511i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1512{
1513 struct drm_device *dev = obj->dev;
1514 drm_i915_private_t *dev_priv = dev->dev_private;
1515 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1516
1517 BUG_ON(!obj_priv->active);
1518 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1519 obj_priv->last_rendering_seqno = 0;
1520}
673a394b 1521
963b4836
CW		 1522/* Immediately discard the backing storage */
1523static void
1524i915_gem_object_truncate(struct drm_gem_object *obj)
1525{
bb6baf76
CW		 1526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1527 struct inode *inode;
963b4836 1528
bb6baf76
CW		 1529 inode = obj->filp->f_path.dentry->d_inode;
1530 if (inode->i_op->truncate)
1531 inode->i_op->truncate (inode);
1532
1533 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1534}
1535
1536static inline int
1537i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1538{
1539 return obj_priv->madv == I915_MADV_DONTNEED;
1540}
1541
673a394b
EA		 1542static void
1543i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1544{
1545 struct drm_device *dev = obj->dev;
1546 drm_i915_private_t *dev_priv = dev->dev_private;
1547 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1548
1549 i915_verify_inactive(dev, __FILE__, __LINE__);
1550 if (obj_priv->pin_count != 0)
1551 list_del_init(&obj_priv->list);
1552 else
1553 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1554
99fcb766
DV		 1555 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1556
ce44b0ea 1557 obj_priv->last_rendering_seqno = 0;
673a394b
EA		 1558 if (obj_priv->active) {
1559 obj_priv->active = 0;
1560 drm_gem_object_unreference(obj);
1561 }
1562 i915_verify_inactive(dev, __FILE__, __LINE__);
1563}
1564
1565/**
1566 * Creates a new sequence number, emitting a write of it to the status page
1567 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1568 *
1569 * Must be called with struct_lock held.
1570 *
1571 * Returned sequence numbers are nonzero on success.
1572 */
5a5a0c64 1573uint32_t
b962442e
EA		 1574i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1575 uint32_t flush_domains)
673a394b
EA		 1576{
1577 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1578 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1579 struct drm_i915_gem_request *request;
1580 uint32_t seqno;
1581 int was_empty;
1582 RING_LOCALS;
1583
b962442e
EA		 1584 if (file_priv != NULL)
1585 i915_file_priv = file_priv->driver_priv;
1586
9a298b2a 1587 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1588 if (request == NULL)
1589 return 0;
1590
1591 /* Grab the seqno we're going to make this request be, and bump the
1592 * next (skipping 0 so it can be the reserved no-seqno value).
1593 */
1594 seqno = dev_priv->mm.next_gem_seqno;
1595 dev_priv->mm.next_gem_seqno++;
1596 if (dev_priv->mm.next_gem_seqno == 0)
1597 dev_priv->mm.next_gem_seqno++;
1598
1599 BEGIN_LP_RING(4);
1600 OUT_RING(MI_STORE_DWORD_INDEX);
1601 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1602 OUT_RING(seqno);
1603
1604 OUT_RING(MI_USER_INTERRUPT);
1605 ADVANCE_LP_RING();
1606
44d98a61 1607 DRM_DEBUG_DRIVER("%d\n", seqno);
673a394b
EA		 1608
1609 request->seqno = seqno;
1610 request->emitted_jiffies = jiffies;
673a394b
EA		 1611 was_empty = list_empty(&dev_priv->mm.request_list);
1612 list_add_tail(&request->list, &dev_priv->mm.request_list);
b962442e
EA		 1613 if (i915_file_priv) {
1614 list_add_tail(&request->client_list,
1615 &i915_file_priv->mm.request_list);
1616 } else {
1617 INIT_LIST_HEAD(&request->client_list);
1618 }
673a394b 1619
ce44b0ea
EA		 1620 /* Associate any objects on the flushing list matching the write
1621 * domain we're flushing with our flush.
1622 */
1623 if (flush_domains != 0) {
1624 struct drm_i915_gem_object *obj_priv, *next;
1625
1626 list_for_each_entry_safe(obj_priv, next,
99fcb766
DV		 1627 &dev_priv->mm.gpu_write_list,
1628 gpu_write_list) {
ce44b0ea
EA		 1629 struct drm_gem_object *obj = obj_priv->obj;
1630
1631 if ((obj->write_domain & flush_domains) ==
1632 obj->write_domain) {
1c5d22f7
CW		 1633 uint32_t old_write_domain = obj->write_domain;
1634
ce44b0ea 1635 obj->write_domain = 0;
99fcb766 1636 list_del_init(&obj_priv->gpu_write_list);
ce44b0ea 1637 i915_gem_object_move_to_active(obj, seqno);
1c5d22f7
CW		 1638
1639 trace_i915_gem_object_change_domain(obj,
1640 obj->read_domains,
1641 old_write_domain);
ce44b0ea
EA		 1642 }
1643 }
1644
1645 }
1646
f65d9421
BG		 1647 if (!dev_priv->mm.suspended) {
1648 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1649 if (was_empty)
1650 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1651 }
673a394b
EA		 1652 return seqno;
1653}
1654
1655/**
1656 * Command execution barrier
1657 *
1658 * Ensures that all commands in the ring are finished
1659 * before signalling the CPU
1660 */
3043c60c 1661static uint32_t
673a394b
EA		 1662i915_retire_commands(struct drm_device *dev)
1663{
1664 drm_i915_private_t *dev_priv = dev->dev_private;
1665 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1666 uint32_t flush_domains = 0;
1667 RING_LOCALS;
1668
1669 /* The sampler always gets flushed on i965 (sigh) */
1670 if (IS_I965G(dev))
1671 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1672 BEGIN_LP_RING(2);
1673 OUT_RING(cmd);
1674 OUT_RING(0); /* noop */
1675 ADVANCE_LP_RING();
1676 return flush_domains;
1677}
1678
1679/**
1680 * Moves buffers associated only with the given active seqno from the active
1681 * to inactive list, potentially freeing them.
1682 */
1683static void
1684i915_gem_retire_request(struct drm_device *dev,
1685 struct drm_i915_gem_request *request)
1686{
1687 drm_i915_private_t *dev_priv = dev->dev_private;
1688
1c5d22f7
CW		 1689 trace_i915_gem_request_retire(dev, request->seqno);
1690
673a394b
EA		 1691 /* Move any buffers on the active list that are no longer referenced
1692 * by the ringbuffer to the flushing/inactive lists as appropriate.
1693 */
5e118f41 1694 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1695 while (!list_empty(&dev_priv->mm.active_list)) {
1696 struct drm_gem_object *obj;
1697 struct drm_i915_gem_object *obj_priv;
1698
1699 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1700 struct drm_i915_gem_object,
1701 list);
1702 obj = obj_priv->obj;
1703
1704 /* If the seqno being retired doesn't match the oldest in the
1705 * list, then the oldest in the list must still be newer than
1706 * this seqno.
1707 */
1708 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1709 goto out;
de151cf6 1710
673a394b
EA		 1711#if WATCH_LRU
1712 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1713 __func__, request->seqno, obj);
1714#endif
1715
ce44b0ea
EA		 1716 if (obj->write_domain != 0)
1717 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1718 else {
1719 /* Take a reference on the object so it won't be
1720 * freed while the spinlock is held. The list
1721 * protection for this spinlock is safe when breaking
1722 * the lock like this since the next thing we do
1723 * is just get the head of the list again.
1724 */
1725 drm_gem_object_reference(obj);
673a394b 1726 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1727 spin_unlock(&dev_priv->mm.active_list_lock);
1728 drm_gem_object_unreference(obj);
1729 spin_lock(&dev_priv->mm.active_list_lock);
1730 }
673a394b 1731 }
5e118f41
CW		 1732out:
1733 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1734}
1735
1736/**
1737 * Returns true if seq1 is later than seq2.
1738 */
22be1724 1739bool
673a394b
EA		 1740i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1741{
1742 return (int32_t)(seq1 - seq2) >= 0;
1743}
1744
1745uint32_t
1746i915_get_gem_seqno(struct drm_device *dev)
1747{
1748 drm_i915_private_t *dev_priv = dev->dev_private;
1749
1750 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1751}
1752
1753/**
1754 * This function clears the request list as sequence numbers are passed.
1755 */
1756void
1757i915_gem_retire_requests(struct drm_device *dev)
1758{
1759 drm_i915_private_t *dev_priv = dev->dev_private;
1760 uint32_t seqno;
1761
9d34e5db 1762 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
6c0594a3
KW		 1763 return;
1764
673a394b
EA		 1765 seqno = i915_get_gem_seqno(dev);
1766
1767 while (!list_empty(&dev_priv->mm.request_list)) {
1768 struct drm_i915_gem_request *request;
1769 uint32_t retiring_seqno;
1770
1771 request = list_first_entry(&dev_priv->mm.request_list,
1772 struct drm_i915_gem_request,
1773 list);
1774 retiring_seqno = request->seqno;
1775
1776 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1777 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1778 i915_gem_retire_request(dev, request);
1779
1780 list_del(&request->list);
b962442e 1781 list_del(&request->client_list);
9a298b2a 1782 kfree(request);
673a394b
EA		 1783 } else
1784 break;
1785 }
9d34e5db
CW		 1786
1787 if (unlikely (dev_priv->trace_irq_seqno &&
1788 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1789 i915_user_irq_put(dev);
1790 dev_priv->trace_irq_seqno = 0;
1791 }
673a394b
EA		 1792}
1793
1794void
1795i915_gem_retire_work_handler(struct work_struct *work)
1796{
1797 drm_i915_private_t *dev_priv;
1798 struct drm_device *dev;
1799
1800 dev_priv = container_of(work, drm_i915_private_t,
1801 mm.retire_work.work);
1802 dev = dev_priv->dev;
1803
1804 mutex_lock(&dev->struct_mutex);
1805 i915_gem_retire_requests(dev);
6dbe2772
KP		 1806 if (!dev_priv->mm.suspended &&
1807 !list_empty(&dev_priv->mm.request_list))
9c9fe1f8 1808 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1809 mutex_unlock(&dev->struct_mutex);
1810}
1811
5a5a0c64 1812int
48764bf4 1813i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
673a394b
EA		 1814{
1815 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1816 u32 ier;
673a394b
EA		 1817 int ret = 0;
1818
1819 BUG_ON(seqno == 0);
1820
ba1234d1 1821 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1822 return -EIO;
1823
673a394b 1824 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
f2b115e6 1825 if (IS_IRONLAKE(dev))
036a4a7d
ZW		 1826 ier = I915_READ(DEIER) | I915_READ(GTIER);
1827 else
1828 ier = I915_READ(IER);
802c7eb6
JB		 1829 if (!ier) {
1830 DRM_ERROR("something (likely vbetool) disabled "
1831 "interrupts, re-enabling\n");
1832 i915_driver_irq_preinstall(dev);
1833 i915_driver_irq_postinstall(dev);
1834 }
1835
1c5d22f7
CW		 1836 trace_i915_gem_request_wait_begin(dev, seqno);
1837
673a394b
EA		 1838 dev_priv->mm.waiting_gem_seqno = seqno;
1839 i915_user_irq_get(dev);
48764bf4
DV		 1840 if (interruptible)
1841 ret = wait_event_interruptible(dev_priv->irq_queue,
1842 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1843 atomic_read(&dev_priv->mm.wedged));
1844 else
1845 wait_event(dev_priv->irq_queue,
1846 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1847 atomic_read(&dev_priv->mm.wedged));
1848
673a394b
EA		 1849 i915_user_irq_put(dev);
1850 dev_priv->mm.waiting_gem_seqno = 0;
1c5d22f7
CW		 1851
1852 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1853 }
ba1234d1 1854 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1855 ret = -EIO;
1856
1857 if (ret && ret != -ERESTARTSYS)
1858 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1859 __func__, ret, seqno, i915_get_gem_seqno(dev));
1860
1861 /* Directly dispatch request retiring. While we have the work queue
1862 * to handle this, the waiter on a request often wants an associated
1863 * buffer to have made it to the inactive list, and we would need
1864 * a separate wait queue to handle that.
1865 */
1866 if (ret == 0)
1867 i915_gem_retire_requests(dev);
1868
1869 return ret;
1870}
1871
48764bf4
DV		 1872/**
1873 * Waits for a sequence number to be signaled, and cleans up the
1874 * request and object lists appropriately for that event.
1875 */
1876static int
1877i915_wait_request(struct drm_device *dev, uint32_t seqno)
1878{
1879 return i915_do_wait_request(dev, seqno, 1);
1880}
1881
673a394b
EA		 1882static void
1883i915_gem_flush(struct drm_device *dev,
1884 uint32_t invalidate_domains,
1885 uint32_t flush_domains)
1886{
1887 drm_i915_private_t *dev_priv = dev->dev_private;
1888 uint32_t cmd;
1889 RING_LOCALS;
1890
1891#if WATCH_EXEC
1892 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1893 invalidate_domains, flush_domains);
1894#endif
1c5d22f7
CW		 1895 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1896 invalidate_domains, flush_domains);
673a394b
EA		 1897
1898 if (flush_domains & I915_GEM_DOMAIN_CPU)
1899 drm_agp_chipset_flush(dev);
1900
21d509e3 1901 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
673a394b
EA		 1902 /*
1903 * read/write caches:
1904 *
1905 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1906 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1907 * also flushed at 2d versus 3d pipeline switches.
1908 *
1909 * read-only caches:
1910 *
1911 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1912 * MI_READ_FLUSH is set, and is always flushed on 965.
1913 *
1914 * I915_GEM_DOMAIN_COMMAND may not exist?
1915 *
1916 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1917 * invalidated when MI_EXE_FLUSH is set.
1918 *
1919 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1920 * invalidated with every MI_FLUSH.
1921 *
1922 * TLBs:
1923 *
1924 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1925 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1926 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1927 * are flushed at any MI_FLUSH.
1928 */
1929
1930 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1931 if ((invalidate_domains|flush_domains) &
1932 I915_GEM_DOMAIN_RENDER)
1933 cmd &= ~MI_NO_WRITE_FLUSH;
1934 if (!IS_I965G(dev)) {
1935 /*
1936 * On the 965, the sampler cache always gets flushed
1937 * and this bit is reserved.
1938 */
1939 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1940 cmd |= MI_READ_FLUSH;
1941 }
1942 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1943 cmd |= MI_EXE_FLUSH;
1944
1945#if WATCH_EXEC
1946 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1947#endif
1948 BEGIN_LP_RING(2);
1949 OUT_RING(cmd);
48764bf4 1950 OUT_RING(MI_NOOP);
673a394b
EA		 1951 ADVANCE_LP_RING();
1952 }
1953}
1954
1955/**
1956 * Ensures that all rendering to the object has completed and the object is
1957 * safe to unbind from the GTT or access from the CPU.
1958 */
1959static int
1960i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1961{
1962 struct drm_device *dev = obj->dev;
1963 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1964 int ret;
1965
e47c68e9
EA		 1966 /* This function only exists to support waiting for existing rendering,
1967 * not for emitting required flushes.
673a394b 1968 */
e47c68e9 1969 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1970
1971 /* If there is rendering queued on the buffer being evicted, wait for
1972 * it.
1973 */
1974 if (obj_priv->active) {
1975#if WATCH_BUF
1976 DRM_INFO("%s: object %p wait for seqno %08x\n",
1977 __func__, obj, obj_priv->last_rendering_seqno);
1978#endif
1979 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1980 if (ret != 0)
1981 return ret;
1982 }
1983
1984 return 0;
1985}
1986
1987/**
1988 * Unbinds an object from the GTT aperture.
1989 */
0f973f27 1990int
673a394b
EA		 1991i915_gem_object_unbind(struct drm_gem_object *obj)
1992{
1993 struct drm_device *dev = obj->dev;
1994 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1995 int ret = 0;
1996
1997#if WATCH_BUF
1998 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1999 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2000#endif
2001 if (obj_priv->gtt_space == NULL)
2002 return 0;
2003
2004 if (obj_priv->pin_count != 0) {
2005 DRM_ERROR("Attempting to unbind pinned buffer\n");
2006 return -EINVAL;
2007 }
2008
5323fd04
EA		 2009 /* blow away mappings if mapped through GTT */
2010 i915_gem_release_mmap(obj);
2011
673a394b
EA		 2012 /* Move the object to the CPU domain to ensure that
2013 * any possible CPU writes while it's not in the GTT
2014 * are flushed when we go to remap it. This will
2015 * also ensure that all pending GPU writes are finished
2016 * before we unbind.
2017 */
e47c68e9 2018 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 2019 if (ret) {
e47c68e9
EA		 2020 if (ret != -ERESTARTSYS)
2021 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 2022 return ret;
2023 }
2024
5323fd04
EA		 2025 BUG_ON(obj_priv->active);
2026
96b47b65
DV		 2027 /* release the fence reg _after_ flushing */
2028 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2029 i915_gem_clear_fence_reg(obj);
2030
673a394b
EA		 2031 if (obj_priv->agp_mem != NULL) {
2032 drm_unbind_agp(obj_priv->agp_mem);
2033 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2034 obj_priv->agp_mem = NULL;
2035 }
2036
856fa198 2037 i915_gem_object_put_pages(obj);
a32808c0 2038 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 2039
2040 if (obj_priv->gtt_space) {
2041 atomic_dec(&dev->gtt_count);
2042 atomic_sub(obj->size, &dev->gtt_memory);
2043
2044 drm_mm_put_block(obj_priv->gtt_space);
2045 obj_priv->gtt_space = NULL;
2046 }
2047
2048 /* Remove ourselves from the LRU list if present. */
2049 if (!list_empty(&obj_priv->list))
2050 list_del_init(&obj_priv->list);
2051
963b4836
CW		 2052 if (i915_gem_object_is_purgeable(obj_priv))
2053 i915_gem_object_truncate(obj);
2054
1c5d22f7
CW		 2055 trace_i915_gem_object_unbind(obj);
2056
673a394b
EA		 2057 return 0;
2058}
2059
07f73f69
CW		 2060static struct drm_gem_object *
2061i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2062{
2063 drm_i915_private_t *dev_priv = dev->dev_private;
2064 struct drm_i915_gem_object *obj_priv;
2065 struct drm_gem_object *best = NULL;
2066 struct drm_gem_object *first = NULL;
2067
2068 /* Try to find the smallest clean object */
2069 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2070 struct drm_gem_object *obj = obj_priv->obj;
2071 if (obj->size >= min_size) {
963b4836
CW		 2072 if ((!obj_priv->dirty ||
2073 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2074 (!best || obj->size < best->size)) {
2075 best = obj;
2076 if (best->size == min_size)
2077 return best;
2078 }
2079 if (!first)
2080 first = obj;
2081 }
2082 }
2083
2084 return best ? best : first;
2085}
2086
673a394b 2087static int
07f73f69
CW		 2088i915_gem_evict_everything(struct drm_device *dev)
2089{
2090 drm_i915_private_t *dev_priv = dev->dev_private;
07f73f69 2091 int ret;
99fcb766 2092 uint32_t seqno;
07f73f69
CW		 2093 bool lists_empty;
2094
07f73f69
CW		 2095 spin_lock(&dev_priv->mm.active_list_lock);
2096 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2097 list_empty(&dev_priv->mm.flushing_list) &&
2098 list_empty(&dev_priv->mm.active_list));
2099 spin_unlock(&dev_priv->mm.active_list_lock);
2100
9731129c 2101 if (lists_empty)
07f73f69 2102 return -ENOSPC;
07f73f69
CW		 2103
2104 /* Flush everything (on to the inactive lists) and evict */
2105 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2106 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2107 if (seqno == 0)
2108 return -ENOMEM;
2109
2110 ret = i915_wait_request(dev, seqno);
2111 if (ret)
2112 return ret;
2113
99fcb766
DV		 2114 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2115
ab5ee576 2116 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2117 if (ret)
2118 return ret;
2119
2120 spin_lock(&dev_priv->mm.active_list_lock);
2121 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2122 list_empty(&dev_priv->mm.flushing_list) &&
2123 list_empty(&dev_priv->mm.active_list));
2124 spin_unlock(&dev_priv->mm.active_list_lock);
2125 BUG_ON(!lists_empty);
2126
2127 return 0;
2128}
2129
673a394b 2130static int
07f73f69 2131i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2132{
2133 drm_i915_private_t *dev_priv = dev->dev_private;
2134 struct drm_gem_object *obj;
07f73f69 2135 int ret;
673a394b
EA		 2136
2137 for (;;) {
07f73f69
CW		 2138 i915_gem_retire_requests(dev);
2139
673a394b
EA		 2140 /* If there's an inactive buffer available now, grab it
2141 * and be done.
2142 */
07f73f69
CW		 2143 obj = i915_gem_find_inactive_object(dev, min_size);
2144 if (obj) {
2145 struct drm_i915_gem_object *obj_priv;
2146
673a394b
EA		 2147#if WATCH_LRU
2148 DRM_INFO("%s: evicting %p\n", __func__, obj);
2149#endif
07f73f69
CW		 2150 obj_priv = obj->driver_private;
2151 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2152 BUG_ON(obj_priv->active);
2153
2154 /* Wait on the rendering and unbind the buffer. */
07f73f69 2155 return i915_gem_object_unbind(obj);
673a394b
EA		 2156 }
2157
2158 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2159 * things, wait for the next to finish and hopefully leave us
2160 * a buffer to evict.
673a394b
EA		 2161 */
2162 if (!list_empty(&dev_priv->mm.request_list)) {
2163 struct drm_i915_gem_request *request;
2164
2165 request = list_first_entry(&dev_priv->mm.request_list,
2166 struct drm_i915_gem_request,
2167 list);
2168
2169 ret = i915_wait_request(dev, request->seqno);
2170 if (ret)
07f73f69 2171 return ret;
673a394b 2172
07f73f69 2173 continue;
673a394b
EA		 2174 }
2175
2176 /* If we didn't have anything on the request list but there
2177 * are buffers awaiting a flush, emit one and try again.
2178 * When we wait on it, those buffers waiting for that flush
2179 * will get moved to inactive.
2180 */
2181 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2182 struct drm_i915_gem_object *obj_priv;
673a394b 2183
9a1e2582
CW		 2184 /* Find an object that we can immediately reuse */
2185 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2186 obj = obj_priv->obj;
2187 if (obj->size >= min_size)
2188 break;
673a394b 2189
9a1e2582
CW		 2190 obj = NULL;
2191 }
673a394b 2192
9a1e2582
CW		 2193 if (obj != NULL) {
2194 uint32_t seqno;
673a394b 2195
9a1e2582
CW		 2196 i915_gem_flush(dev,
2197 obj->write_domain,
2198 obj->write_domain);
2199 seqno = i915_add_request(dev, NULL, obj->write_domain);
2200 if (seqno == 0)
2201 return -ENOMEM;
ac94a962 2202
9a1e2582
CW		 2203 ret = i915_wait_request(dev, seqno);
2204 if (ret)
2205 return ret;
2206
2207 continue;
2208 }
673a394b
EA		 2209 }
2210
07f73f69
CW		 2211 /* If we didn't do any of the above, there's no single buffer
2212 * large enough to swap out for the new one, so just evict
2213 * everything and start again. (This should be rare.)
673a394b 2214 */
9731129c 2215 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2216 return i915_gem_evict_from_inactive_list(dev);
9731129c 2217 else
07f73f69 2218 return i915_gem_evict_everything(dev);
ac94a962 2219 }
ac94a962
KP		 2220}
2221
6911a9b8 2222int
4bdadb97
CW		 2223i915_gem_object_get_pages(struct drm_gem_object *obj,
2224 gfp_t gfpmask)
673a394b
EA		 2225{
2226 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2227 int page_count, i;
2228 struct address_space *mapping;
2229 struct inode *inode;
2230 struct page *page;
2231 int ret;
2232
856fa198 2233 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2234 return 0;
2235
2236 /* Get the list of pages out of our struct file. They'll be pinned
2237 * at this point until we release them.
2238 */
2239 page_count = obj->size / PAGE_SIZE;
856fa198 2240 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2241 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2242 if (obj_priv->pages == NULL) {
856fa198 2243 obj_priv->pages_refcount--;
673a394b
EA		 2244 return -ENOMEM;
2245 }
2246
2247 inode = obj->filp->f_path.dentry->d_inode;
2248 mapping = inode->i_mapping;
2249 for (i = 0; i < page_count; i++) {
4bdadb97
CW		 2250 page = read_cache_page_gfp(mapping, i,
2251 mapping_gfp_mask (mapping) |
2252 __GFP_COLD |
2253 gfpmask);
673a394b
EA		 2254 if (IS_ERR(page)) {
2255 ret = PTR_ERR(page);
856fa198 2256 i915_gem_object_put_pages(obj);
673a394b
EA		 2257 return ret;
2258 }
856fa198 2259 obj_priv->pages[i] = page;
673a394b 2260 }
280b713b
EA		 2261
2262 if (obj_priv->tiling_mode != I915_TILING_NONE)
2263 i915_gem_object_do_bit_17_swizzle(obj);
2264
673a394b
EA		 2265 return 0;
2266}
2267
de151cf6
JB		 2268static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2269{
2270 struct drm_gem_object *obj = reg->obj;
2271 struct drm_device *dev = obj->dev;
2272 drm_i915_private_t *dev_priv = dev->dev_private;
2273 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2274 int regnum = obj_priv->fence_reg;
2275 uint64_t val;
2276
2277 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2278 0xfffff000) << 32;
2279 val |= obj_priv->gtt_offset & 0xfffff000;
2280 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2281 if (obj_priv->tiling_mode == I915_TILING_Y)
2282 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2283 val |= I965_FENCE_REG_VALID;
2284
2285 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2286}
2287
2288static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2289{
2290 struct drm_gem_object *obj = reg->obj;
2291 struct drm_device *dev = obj->dev;
2292 drm_i915_private_t *dev_priv = dev->dev_private;
2293 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2294 int regnum = obj_priv->fence_reg;
0f973f27 2295 int tile_width;
dc529a4f 2296 uint32_t fence_reg, val;
de151cf6
JB		 2297 uint32_t pitch_val;
2298
2299 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2300 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2301 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2302 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2303 return;
2304 }
2305
0f973f27
JB		 2306 if (obj_priv->tiling_mode == I915_TILING_Y &&
2307 HAS_128_BYTE_Y_TILING(dev))
2308 tile_width = 128;
de151cf6 2309 else
0f973f27
JB		 2310 tile_width = 512;
2311
2312 /* Note: pitch better be a power of two tile widths */
2313 pitch_val = obj_priv->stride / tile_width;
2314 pitch_val = ffs(pitch_val) - 1;
de151cf6
JB		 2315
2316 val = obj_priv->gtt_offset;
2317 if (obj_priv->tiling_mode == I915_TILING_Y)
2318 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2319 val |= I915_FENCE_SIZE_BITS(obj->size);
2320 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2321 val |= I830_FENCE_REG_VALID;
2322
dc529a4f
EA		 2323 if (regnum < 8)
2324 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2325 else
2326 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2327 I915_WRITE(fence_reg, val);
de151cf6
JB		 2328}
2329
2330static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2331{
2332 struct drm_gem_object *obj = reg->obj;
2333 struct drm_device *dev = obj->dev;
2334 drm_i915_private_t *dev_priv = dev->dev_private;
2335 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2336 int regnum = obj_priv->fence_reg;
2337 uint32_t val;
2338 uint32_t pitch_val;
8d7773a3 2339 uint32_t fence_size_bits;
de151cf6 2340
8d7773a3 2341 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2342 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2343 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2344 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2345 return;
2346 }
2347
e76a16de
EA		 2348 pitch_val = obj_priv->stride / 128;
2349 pitch_val = ffs(pitch_val) - 1;
2350 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2351
de151cf6
JB		 2352 val = obj_priv->gtt_offset;
2353 if (obj_priv->tiling_mode == I915_TILING_Y)
2354 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2355 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2356 WARN_ON(fence_size_bits & ~0x00000f00);
2357 val |= fence_size_bits;
de151cf6
JB		 2358 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2359 val |= I830_FENCE_REG_VALID;
2360
2361 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2362}
2363
2364/**
2365 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2366 * @obj: object to map through a fence reg
2367 *
2368 * When mapping objects through the GTT, userspace wants to be able to write
2369 * to them without having to worry about swizzling if the object is tiled.
2370 *
2371 * This function walks the fence regs looking for a free one for @obj,
2372 * stealing one if it can't find any.
2373 *
2374 * It then sets up the reg based on the object's properties: address, pitch
2375 * and tiling format.
2376 */
8c4b8c3f
CW		 2377int
2378i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2379{
2380 struct drm_device *dev = obj->dev;
79e53945 2381 struct drm_i915_private *dev_priv = dev->dev_private;
de151cf6
JB		 2382 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2383 struct drm_i915_fence_reg *reg = NULL;
fc7170ba
CW		 2384 struct drm_i915_gem_object *old_obj_priv = NULL;
2385 int i, ret, avail;
de151cf6 2386
a09ba7fa
EA		 2387 /* Just update our place in the LRU if our fence is getting used. */
2388 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2389 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2390 return 0;
2391 }
2392
de151cf6
JB		 2393 switch (obj_priv->tiling_mode) {
2394 case I915_TILING_NONE:
2395 WARN(1, "allocating a fence for non-tiled object?\n");
2396 break;
2397 case I915_TILING_X:
0f973f27
JB		 2398 if (!obj_priv->stride)
2399 return -EINVAL;
2400 WARN((obj_priv->stride & (512 - 1)),
2401 "object 0x%08x is X tiled but has non-512B pitch\n",
2402 obj_priv->gtt_offset);
de151cf6
JB		 2403 break;
2404 case I915_TILING_Y:
0f973f27
JB		 2405 if (!obj_priv->stride)
2406 return -EINVAL;
2407 WARN((obj_priv->stride & (128 - 1)),
2408 "object 0x%08x is Y tiled but has non-128B pitch\n",
2409 obj_priv->gtt_offset);
de151cf6
JB		 2410 break;
2411 }
2412
2413 /* First try to find a free reg */
fc7170ba 2414 avail = 0;
de151cf6
JB		 2415 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2416 reg = &dev_priv->fence_regs[i];
2417 if (!reg->obj)
2418 break;
fc7170ba
CW		 2419
2420 old_obj_priv = reg->obj->driver_private;
2421 if (!old_obj_priv->pin_count)
2422 avail++;
de151cf6
JB		 2423 }
2424
2425 /* None available, try to steal one or wait for a user to finish */
2426 if (i == dev_priv->num_fence_regs) {
a09ba7fa 2427 struct drm_gem_object *old_obj = NULL;
de151cf6 2428
fc7170ba 2429 if (avail == 0)
2939e1f5 2430 return -ENOSPC;
fc7170ba 2431
a09ba7fa
EA		 2432 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2433 fence_list) {
2434 old_obj = old_obj_priv->obj;
d7619c4b 2435
d7619c4b
CW		 2436 if (old_obj_priv->pin_count)
2437 continue;
2438
a09ba7fa
EA		 2439 /* Take a reference, as otherwise the wait_rendering
2440 * below may cause the object to get freed out from
2441 * under us.
2442 */
2443 drm_gem_object_reference(old_obj);
2444
d7619c4b
CW		 2445 /* i915 uses fences for GPU access to tiled buffers */
2446 if (IS_I965G(dev) || !old_obj_priv->active)
de151cf6 2447 break;
d7619c4b 2448
a09ba7fa
EA		 2449 /* This brings the object to the head of the LRU if it
2450 * had been written to. The only way this should
2451 * result in us waiting longer than the expected
2452 * optimal amount of time is if there was a
2453 * fence-using buffer later that was read-only.
2454 */
2455 i915_gem_object_flush_gpu_write_domain(old_obj);
2456 ret = i915_gem_object_wait_rendering(old_obj);
58c2fb64
CW		 2457 if (ret != 0) {
2458 drm_gem_object_unreference(old_obj);
d7619c4b 2459 return ret;
58c2fb64
CW		 2460 }
2461
a09ba7fa 2462 break;
de151cf6
JB		 2463 }
2464
2465 /*
2466 * Zap this virtual mapping so we can set up a fence again
2467 * for this object next time we need it.
2468 */
58c2fb64
CW		 2469 i915_gem_release_mmap(old_obj);
2470
a09ba7fa 2471 i = old_obj_priv->fence_reg;
58c2fb64
CW		 2472 reg = &dev_priv->fence_regs[i];
2473
de151cf6 2474 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2475 list_del_init(&old_obj_priv->fence_list);
58c2fb64 2476
a09ba7fa 2477 drm_gem_object_unreference(old_obj);
de151cf6
JB		 2478 }
2479
2480 obj_priv->fence_reg = i;
a09ba7fa
EA		 2481 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2482
de151cf6
JB		 2483 reg->obj = obj;
2484
2485 if (IS_I965G(dev))
2486 i965_write_fence_reg(reg);
2487 else if (IS_I9XX(dev))
2488 i915_write_fence_reg(reg);
2489 else
2490 i830_write_fence_reg(reg);
d9ddcb96 2491
1c5d22f7
CW		 2492 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2493
d9ddcb96 2494 return 0;
de151cf6
JB		 2495}
2496
2497/**
2498 * i915_gem_clear_fence_reg - clear out fence register info
2499 * @obj: object to clear
2500 *
2501 * Zeroes out the fence register itself and clears out the associated
2502 * data structures in dev_priv and obj_priv.
2503 */
2504static void
2505i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2506{
2507 struct drm_device *dev = obj->dev;
79e53945 2508 drm_i915_private_t *dev_priv = dev->dev_private;
de151cf6
JB		 2509 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2510
2511 if (IS_I965G(dev))
2512 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
dc529a4f
EA		 2513 else {
2514 uint32_t fence_reg;
2515
2516 if (obj_priv->fence_reg < 8)
2517 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2518 else
2519 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2520 8) * 4;
2521
2522 I915_WRITE(fence_reg, 0);
2523 }
de151cf6
JB		 2524
2525 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2526 obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2527 list_del_init(&obj_priv->fence_list);
de151cf6
JB		 2528}
2529
52dc7d32
CW		 2530/**
2531 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2532 * to the buffer to finish, and then resets the fence register.
2533 * @obj: tiled object holding a fence register.
2534 *
2535 * Zeroes out the fence register itself and clears out the associated
2536 * data structures in dev_priv and obj_priv.
2537 */
2538int
2539i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2540{
2541 struct drm_device *dev = obj->dev;
2542 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2543
2544 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2545 return 0;
2546
2547 /* On the i915, GPU access to tiled buffers is via a fence,
2548 * therefore we must wait for any outstanding access to complete
2549 * before clearing the fence.
2550 */
2551 if (!IS_I965G(dev)) {
2552 int ret;
2553
2554 i915_gem_object_flush_gpu_write_domain(obj);
2555 i915_gem_object_flush_gtt_write_domain(obj);
2556 ret = i915_gem_object_wait_rendering(obj);
2557 if (ret != 0)
2558 return ret;
2559 }
2560
2561 i915_gem_clear_fence_reg (obj);
2562
2563 return 0;
2564}
2565
673a394b
EA		 2566/**
2567 * Finds free space in the GTT aperture and binds the object there.
2568 */
2569static int
2570i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2571{
2572 struct drm_device *dev = obj->dev;
2573 drm_i915_private_t *dev_priv = dev->dev_private;
2574 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2575 struct drm_mm_node *free_space;
4bdadb97 2576 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2577 int ret;
673a394b 2578
bb6baf76 2579 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2580 DRM_ERROR("Attempting to bind a purgeable object\n");
2581 return -EINVAL;
2582 }
2583
673a394b 2584 if (alignment == 0)
0f973f27 2585 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2586 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2587 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2588 return -EINVAL;
2589 }
2590
2591 search_free:
2592 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2593 obj->size, alignment, 0);
2594 if (free_space != NULL) {
2595 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2596 alignment);
2597 if (obj_priv->gtt_space != NULL) {
2598 obj_priv->gtt_space->private = obj;
2599 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2600 }
2601 }
2602 if (obj_priv->gtt_space == NULL) {
2603 /* If the gtt is empty and we're still having trouble
2604 * fitting our object in, we're out of memory.
2605 */
2606#if WATCH_LRU
2607 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2608#endif
07f73f69 2609 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2610 if (ret)
673a394b 2611 return ret;
9731129c 2612
673a394b
EA		 2613 goto search_free;
2614 }
2615
2616#if WATCH_BUF
cfd43c02 2617 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2618 obj->size, obj_priv->gtt_offset);
2619#endif
4bdadb97 2620 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2621 if (ret) {
2622 drm_mm_put_block(obj_priv->gtt_space);
2623 obj_priv->gtt_space = NULL;
07f73f69
CW		 2624
2625 if (ret == -ENOMEM) {
2626 /* first try to clear up some space from the GTT */
2627 ret = i915_gem_evict_something(dev, obj->size);
2628 if (ret) {
07f73f69 2629 /* now try to shrink everyone else */
4bdadb97
CW		 2630 if (gfpmask) {
2631 gfpmask = 0;
2632 goto search_free;
07f73f69
CW		 2633 }
2634
2635 return ret;
2636 }
2637
2638 goto search_free;
2639 }
2640
673a394b
EA		 2641 return ret;
2642 }
2643
673a394b
EA		 2644 /* Create an AGP memory structure pointing at our pages, and bind it
2645 * into the GTT.
2646 */
2647 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2648 obj_priv->pages,
07f73f69 2649 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2650 obj_priv->gtt_offset,
2651 obj_priv->agp_type);
673a394b 2652 if (obj_priv->agp_mem == NULL) {
856fa198 2653 i915_gem_object_put_pages(obj);
673a394b
EA		 2654 drm_mm_put_block(obj_priv->gtt_space);
2655 obj_priv->gtt_space = NULL;
07f73f69
CW		 2656
2657 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2658 if (ret)
07f73f69 2659 return ret;
07f73f69
CW		 2660
2661 goto search_free;
673a394b
EA		 2662 }
2663 atomic_inc(&dev->gtt_count);
2664 atomic_add(obj->size, &dev->gtt_memory);
2665
2666 /* Assert that the object is not currently in any GPU domain. As it
2667 * wasn't in the GTT, there shouldn't be any way it could have been in
2668 * a GPU cache
2669 */
21d509e3
CW		 2670 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2671 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2672
1c5d22f7
CW		 2673 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2674
673a394b
EA		 2675 return 0;
2676}
2677
2678void
2679i915_gem_clflush_object(struct drm_gem_object *obj)
2680{
2681 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2682
2683 /* If we don't have a page list set up, then we're not pinned
2684 * to GPU, and we can ignore the cache flush because it'll happen
2685 * again at bind time.
2686 */
856fa198 2687 if (obj_priv->pages == NULL)
673a394b
EA		 2688 return;
2689
1c5d22f7 2690 trace_i915_gem_object_clflush(obj);
cfa16a0d 2691
856fa198 2692 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2693}
2694
e47c68e9
EA		 2695/** Flushes any GPU write domain for the object if it's dirty. */
2696static void
2697i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2698{
2699 struct drm_device *dev = obj->dev;
2700 uint32_t seqno;
1c5d22f7 2701 uint32_t old_write_domain;
e47c68e9
EA		 2702
2703 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2704 return;
2705
2706 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2707 old_write_domain = obj->write_domain;
e47c68e9 2708 i915_gem_flush(dev, 0, obj->write_domain);
b962442e 2709 seqno = i915_add_request(dev, NULL, obj->write_domain);
99fcb766 2710 BUG_ON(obj->write_domain);
e47c68e9 2711 i915_gem_object_move_to_active(obj, seqno);
1c5d22f7
CW		 2712
2713 trace_i915_gem_object_change_domain(obj,
2714 obj->read_domains,
2715 old_write_domain);
e47c68e9
EA		 2716}
2717
2718/** Flushes the GTT write domain for the object if it's dirty. */
2719static void
2720i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2721{
1c5d22f7
CW		 2722 uint32_t old_write_domain;
2723
e47c68e9
EA		 2724 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2725 return;
2726
2727 /* No actual flushing is required for the GTT write domain. Writes
2728 * to it immediately go to main memory as far as we know, so there's
2729 * no chipset flush. It also doesn't land in render cache.
2730 */
1c5d22f7 2731 old_write_domain = obj->write_domain;
e47c68e9 2732 obj->write_domain = 0;
1c5d22f7
CW		 2733
2734 trace_i915_gem_object_change_domain(obj,
2735 obj->read_domains,
2736 old_write_domain);
e47c68e9
EA		 2737}
2738
2739/** Flushes the CPU write domain for the object if it's dirty. */
2740static void
2741i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2742{
2743 struct drm_device *dev = obj->dev;
1c5d22f7 2744 uint32_t old_write_domain;
e47c68e9
EA		 2745
2746 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2747 return;
2748
2749 i915_gem_clflush_object(obj);
2750 drm_agp_chipset_flush(dev);
1c5d22f7 2751 old_write_domain = obj->write_domain;
e47c68e9 2752 obj->write_domain = 0;
1c5d22f7
CW		 2753
2754 trace_i915_gem_object_change_domain(obj,
2755 obj->read_domains,
2756 old_write_domain);
e47c68e9
EA		 2757}
2758
6b95a207
KH		 2759void
2760i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2761{
2762 switch (obj->write_domain) {
2763 case I915_GEM_DOMAIN_GTT:
2764 i915_gem_object_flush_gtt_write_domain(obj);
2765 break;
2766 case I915_GEM_DOMAIN_CPU:
2767 i915_gem_object_flush_cpu_write_domain(obj);
2768 break;
2769 default:
2770 i915_gem_object_flush_gpu_write_domain(obj);
2771 break;
2772 }
2773}
2774
2ef7eeaa
EA		 2775/**
2776 * Moves a single object to the GTT read, and possibly write domain.
2777 *
2778 * This function returns when the move is complete, including waiting on
2779 * flushes to occur.
2780 */
79e53945 2781int
2ef7eeaa
EA		 2782i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2783{
2ef7eeaa 2784 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1c5d22f7 2785 uint32_t old_write_domain, old_read_domains;
e47c68e9 2786 int ret;
2ef7eeaa 2787
02354392
EA		 2788 /* Not valid to be called on unbound objects. */
2789 if (obj_priv->gtt_space == NULL)
2790 return -EINVAL;
2791
e47c68e9
EA		 2792 i915_gem_object_flush_gpu_write_domain(obj);
2793 /* Wait on any GPU rendering and flushing to occur. */
2794 ret = i915_gem_object_wait_rendering(obj);
2795 if (ret != 0)
2796 return ret;
2797
1c5d22f7
CW		 2798 old_write_domain = obj->write_domain;
2799 old_read_domains = obj->read_domains;
2800
e47c68e9
EA		 2801 /* If we're writing through the GTT domain, then CPU and GPU caches
2802 * will need to be invalidated at next use.
2ef7eeaa 2803 */
e47c68e9
EA		 2804 if (write)
2805 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2806
e47c68e9 2807 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2808
e47c68e9
EA		 2809 /* It should now be out of any other write domains, and we can update
2810 * the domain values for our changes.
2811 */
2812 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2813 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2814 if (write) {
2815 obj->write_domain = I915_GEM_DOMAIN_GTT;
2816 obj_priv->dirty = 1;
2ef7eeaa
EA		 2817 }
2818
1c5d22f7
CW		 2819 trace_i915_gem_object_change_domain(obj,
2820 old_read_domains,
2821 old_write_domain);
2822
e47c68e9
EA		 2823 return 0;
2824}
2825
b9241ea3
ZW		 2826/*
2827 * Prepare buffer for display plane. Use uninterruptible for possible flush
2828 * wait, as in modesetting process we're not supposed to be interrupted.
2829 */
2830int
2831i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2832{
2833 struct drm_device *dev = obj->dev;
2834 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2835 uint32_t old_write_domain, old_read_domains;
2836 int ret;
2837
2838 /* Not valid to be called on unbound objects. */
2839 if (obj_priv->gtt_space == NULL)
2840 return -EINVAL;
2841
2842 i915_gem_object_flush_gpu_write_domain(obj);
2843
2844 /* Wait on any GPU rendering and flushing to occur. */
2845 if (obj_priv->active) {
2846#if WATCH_BUF
2847 DRM_INFO("%s: object %p wait for seqno %08x\n",
2848 __func__, obj, obj_priv->last_rendering_seqno);
2849#endif
2850 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2851 if (ret != 0)
2852 return ret;
2853 }
2854
2855 old_write_domain = obj->write_domain;
2856 old_read_domains = obj->read_domains;
2857
2858 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2859
2860 i915_gem_object_flush_cpu_write_domain(obj);
2861
2862 /* It should now be out of any other write domains, and we can update
2863 * the domain values for our changes.
2864 */
2865 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2866 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2867 obj->write_domain = I915_GEM_DOMAIN_GTT;
2868 obj_priv->dirty = 1;
2869
2870 trace_i915_gem_object_change_domain(obj,
2871 old_read_domains,
2872 old_write_domain);
2873
2874 return 0;
2875}
2876
e47c68e9
EA		 2877/**
2878 * Moves a single object to the CPU read, and possibly write domain.
2879 *
2880 * This function returns when the move is complete, including waiting on
2881 * flushes to occur.
2882 */
2883static int
2884i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2885{
1c5d22f7 2886 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2887 int ret;
2888
2889 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2890 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2891 ret = i915_gem_object_wait_rendering(obj);
2892 if (ret != 0)
2893 return ret;
2ef7eeaa 2894
e47c68e9 2895 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2896
e47c68e9
EA		 2897 /* If we have a partially-valid cache of the object in the CPU,
2898 * finish invalidating it and free the per-page flags.
2ef7eeaa 2899 */
e47c68e9 2900 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2901
1c5d22f7
CW		 2902 old_write_domain = obj->write_domain;
2903 old_read_domains = obj->read_domains;
2904
e47c68e9
EA		 2905 /* Flush the CPU cache if it's still invalid. */
2906 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2907 i915_gem_clflush_object(obj);
2ef7eeaa 2908
e47c68e9 2909 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2910 }
2911
2912 /* It should now be out of any other write domains, and we can update
2913 * the domain values for our changes.
2914 */
e47c68e9
EA		 2915 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2916
2917 /* If we're writing through the CPU, then the GPU read domains will
2918 * need to be invalidated at next use.
2919 */
2920 if (write) {
2921 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2922 obj->write_domain = I915_GEM_DOMAIN_CPU;
2923 }
2ef7eeaa 2924
1c5d22f7
CW		 2925 trace_i915_gem_object_change_domain(obj,
2926 old_read_domains,
2927 old_write_domain);
2928
2ef7eeaa
EA		 2929 return 0;
2930}
2931
673a394b
EA		 2932/*
2933 * Set the next domain for the specified object. This
2934 * may not actually perform the necessary flushing/invaliding though,
2935 * as that may want to be batched with other set_domain operations
2936 *
2937 * This is (we hope) the only really tricky part of gem. The goal
2938 * is fairly simple -- track which caches hold bits of the object
2939 * and make sure they remain coherent. A few concrete examples may
2940 * help to explain how it works. For shorthand, we use the notation
2941 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2942 * a pair of read and write domain masks.
2943 *
2944 * Case 1: the batch buffer
2945 *
2946 * 1. Allocated
2947 * 2. Written by CPU
2948 * 3. Mapped to GTT
2949 * 4. Read by GPU
2950 * 5. Unmapped from GTT
2951 * 6. Freed
2952 *
2953 * Let's take these a step at a time
2954 *
2955 * 1. Allocated
2956 * Pages allocated from the kernel may still have
2957 * cache contents, so we set them to (CPU, CPU) always.
2958 * 2. Written by CPU (using pwrite)
2959 * The pwrite function calls set_domain (CPU, CPU) and
2960 * this function does nothing (as nothing changes)
2961 * 3. Mapped by GTT
2962 * This function asserts that the object is not
2963 * currently in any GPU-based read or write domains
2964 * 4. Read by GPU
2965 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2966 * As write_domain is zero, this function adds in the
2967 * current read domains (CPU+COMMAND, 0).
2968 * flush_domains is set to CPU.
2969 * invalidate_domains is set to COMMAND
2970 * clflush is run to get data out of the CPU caches
2971 * then i915_dev_set_domain calls i915_gem_flush to
2972 * emit an MI_FLUSH and drm_agp_chipset_flush
2973 * 5. Unmapped from GTT
2974 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2975 * flush_domains and invalidate_domains end up both zero
2976 * so no flushing/invalidating happens
2977 * 6. Freed
2978 * yay, done
2979 *
2980 * Case 2: The shared render buffer
2981 *
2982 * 1. Allocated
2983 * 2. Mapped to GTT
2984 * 3. Read/written by GPU
2985 * 4. set_domain to (CPU,CPU)
2986 * 5. Read/written by CPU
2987 * 6. Read/written by GPU
2988 *
2989 * 1. Allocated
2990 * Same as last example, (CPU, CPU)
2991 * 2. Mapped to GTT
2992 * Nothing changes (assertions find that it is not in the GPU)
2993 * 3. Read/written by GPU
2994 * execbuffer calls set_domain (RENDER, RENDER)
2995 * flush_domains gets CPU
2996 * invalidate_domains gets GPU
2997 * clflush (obj)
2998 * MI_FLUSH and drm_agp_chipset_flush
2999 * 4. set_domain (CPU, CPU)
3000 * flush_domains gets GPU
3001 * invalidate_domains gets CPU
3002 * wait_rendering (obj) to make sure all drawing is complete.
3003 * This will include an MI_FLUSH to get the data from GPU
3004 * to memory
3005 * clflush (obj) to invalidate the CPU cache
3006 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3007 * 5. Read/written by CPU
3008 * cache lines are loaded and dirtied
3009 * 6. Read written by GPU
3010 * Same as last GPU access
3011 *
3012 * Case 3: The constant buffer
3013 *
3014 * 1. Allocated
3015 * 2. Written by CPU
3016 * 3. Read by GPU
3017 * 4. Updated (written) by CPU again
3018 * 5. Read by GPU
3019 *
3020 * 1. Allocated
3021 * (CPU, CPU)
3022 * 2. Written by CPU
3023 * (CPU, CPU)
3024 * 3. Read by GPU
3025 * (CPU+RENDER, 0)
3026 * flush_domains = CPU
3027 * invalidate_domains = RENDER
3028 * clflush (obj)
3029 * MI_FLUSH
3030 * drm_agp_chipset_flush
3031 * 4. Updated (written) by CPU again
3032 * (CPU, CPU)
3033 * flush_domains = 0 (no previous write domain)
3034 * invalidate_domains = 0 (no new read domains)
3035 * 5. Read by GPU
3036 * (CPU+RENDER, 0)
3037 * flush_domains = CPU
3038 * invalidate_domains = RENDER
3039 * clflush (obj)
3040 * MI_FLUSH
3041 * drm_agp_chipset_flush
3042 */
c0d90829 3043static void
8b0e378a 3044i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3045{
3046 struct drm_device *dev = obj->dev;
3047 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3048 uint32_t invalidate_domains = 0;
3049 uint32_t flush_domains = 0;
1c5d22f7 3050 uint32_t old_read_domains;
e47c68e9 3051
8b0e378a
EA		 3052 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3053 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3054
652c393a
JB		 3055 intel_mark_busy(dev, obj);
3056
673a394b
EA		 3057#if WATCH_BUF
3058 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3059 __func__, obj,
8b0e378a
EA		 3060 obj->read_domains, obj->pending_read_domains,
3061 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 3062#endif
3063 /*
3064 * If the object isn't moving to a new write domain,
3065 * let the object stay in multiple read domains
3066 */
8b0e378a
EA		 3067 if (obj->pending_write_domain == 0)
3068 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3069 else
3070 obj_priv->dirty = 1;
3071
3072 /*
3073 * Flush the current write domain if
3074 * the new read domains don't match. Invalidate
3075 * any read domains which differ from the old
3076 * write domain
3077 */
8b0e378a
EA		 3078 if (obj->write_domain &&
3079 obj->write_domain != obj->pending_read_domains) {
673a394b 3080 flush_domains |= obj->write_domain;
8b0e378a
EA		 3081 invalidate_domains |=
3082 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3083 }
3084 /*
3085 * Invalidate any read caches which may have
3086 * stale data. That is, any new read domains.
3087 */
8b0e378a 3088 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3089 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3090#if WATCH_BUF
3091 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3092 __func__, flush_domains, invalidate_domains);
3093#endif
673a394b
EA		 3094 i915_gem_clflush_object(obj);
3095 }
3096
1c5d22f7
CW		 3097 old_read_domains = obj->read_domains;
3098
efbeed96
EA		 3099 /* The actual obj->write_domain will be updated with
3100 * pending_write_domain after we emit the accumulated flush for all
3101 * of our domain changes in execbuffers (which clears objects'
3102 * write_domains). So if we have a current write domain that we
3103 * aren't changing, set pending_write_domain to that.
3104 */
3105 if (flush_domains == 0 && obj->pending_write_domain == 0)
3106 obj->pending_write_domain = obj->write_domain;
8b0e378a 3107 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3108
3109 dev->invalidate_domains |= invalidate_domains;
3110 dev->flush_domains |= flush_domains;
3111#if WATCH_BUF
3112 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3113 __func__,
3114 obj->read_domains, obj->write_domain,
3115 dev->invalidate_domains, dev->flush_domains);
3116#endif
1c5d22f7
CW		 3117
3118 trace_i915_gem_object_change_domain(obj,
3119 old_read_domains,
3120 obj->write_domain);
673a394b
EA		 3121}
3122
3123/**
e47c68e9 3124 * Moves the object from a partially CPU read to a full one.
673a394b 3125 *
e47c68e9
EA		 3126 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3127 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3128 */
e47c68e9
EA		 3129static void
3130i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b
EA		 3131{
3132 struct drm_i915_gem_object *obj_priv = obj->driver_private;
673a394b 3133
e47c68e9
EA		 3134 if (!obj_priv->page_cpu_valid)
3135 return;
3136
3137 /* If we're partially in the CPU read domain, finish moving it in.
3138 */
3139 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3140 int i;
3141
3142 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3143 if (obj_priv->page_cpu_valid[i])
3144 continue;
856fa198 3145 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3146 }
e47c68e9
EA		 3147 }
3148
3149 /* Free the page_cpu_valid mappings which are now stale, whether
3150 * or not we've got I915_GEM_DOMAIN_CPU.
3151 */
9a298b2a 3152 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3153 obj_priv->page_cpu_valid = NULL;
3154}
3155
3156/**
3157 * Set the CPU read domain on a range of the object.
3158 *
3159 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3160 * not entirely valid. The page_cpu_valid member of the object flags which
3161 * pages have been flushed, and will be respected by
3162 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3163 * of the whole object.
3164 *
3165 * This function returns when the move is complete, including waiting on
3166 * flushes to occur.
3167 */
3168static int
3169i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3170 uint64_t offset, uint64_t size)
3171{
3172 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1c5d22f7 3173 uint32_t old_read_domains;
e47c68e9 3174 int i, ret;
673a394b 3175
e47c68e9
EA		 3176 if (offset == 0 && size == obj->size)
3177 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3178
e47c68e9
EA		 3179 i915_gem_object_flush_gpu_write_domain(obj);
3180 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3181 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3182 if (ret != 0)
6a47baa6 3183 return ret;
e47c68e9
EA		 3184 i915_gem_object_flush_gtt_write_domain(obj);
3185
3186 /* If we're already fully in the CPU read domain, we're done. */
3187 if (obj_priv->page_cpu_valid == NULL &&
3188 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3189 return 0;
673a394b 3190
e47c68e9
EA		 3191 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3192 * newly adding I915_GEM_DOMAIN_CPU
3193 */
673a394b 3194 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3195 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3196 GFP_KERNEL);
e47c68e9
EA		 3197 if (obj_priv->page_cpu_valid == NULL)
3198 return -ENOMEM;
3199 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3200 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3201
3202 /* Flush the cache on any pages that are still invalid from the CPU's
3203 * perspective.
3204 */
e47c68e9
EA		 3205 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3206 i++) {
673a394b
EA		 3207 if (obj_priv->page_cpu_valid[i])
3208 continue;
3209
856fa198 3210 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3211
3212 obj_priv->page_cpu_valid[i] = 1;
3213 }
3214
e47c68e9
EA		 3215 /* It should now be out of any other write domains, and we can update
3216 * the domain values for our changes.
3217 */
3218 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3219
1c5d22f7 3220 old_read_domains = obj->read_domains;
e47c68e9
EA		 3221 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3222
1c5d22f7
CW		 3223 trace_i915_gem_object_change_domain(obj,
3224 old_read_domains,
3225 obj->write_domain);
3226
673a394b
EA		 3227 return 0;
3228}
3229
673a394b
EA		 3230/**
3231 * Pin an object to the GTT and evaluate the relocations landing in it.
3232 */
3233static int
3234i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3235 struct drm_file *file_priv,
76446cac 3236 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3237 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3238{
3239 struct drm_device *dev = obj->dev;
0839ccb8 3240 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3241 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3242 int i, ret;
0839ccb8 3243 void __iomem *reloc_page;
76446cac
JB		 3244 bool need_fence;
3245
3246 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3247 obj_priv->tiling_mode != I915_TILING_NONE;
3248
3249 /* Check fence reg constraints and rebind if necessary */
3250 if (need_fence && !i915_obj_fenceable(dev, obj))
3251 i915_gem_object_unbind(obj);
673a394b
EA		 3252
3253 /* Choose the GTT offset for our buffer and put it there. */
3254 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3255 if (ret)
3256 return ret;
3257
76446cac
JB		 3258 /*
3259 * Pre-965 chips need a fence register set up in order to
3260 * properly handle blits to/from tiled surfaces.
3261 */
3262 if (need_fence) {
3263 ret = i915_gem_object_get_fence_reg(obj);
3264 if (ret != 0) {
3265 if (ret != -EBUSY && ret != -ERESTARTSYS)
3266 DRM_ERROR("Failure to install fence: %d\n",
3267 ret);
3268 i915_gem_object_unpin(obj);
3269 return ret;
3270 }
3271 }
3272
673a394b
EA		 3273 entry->offset = obj_priv->gtt_offset;
3274
673a394b
EA		 3275 /* Apply the relocations, using the GTT aperture to avoid cache
3276 * flushing requirements.
3277 */
3278 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3279 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3280 struct drm_gem_object *target_obj;
3281 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3282 uint32_t reloc_val, reloc_offset;
3283 uint32_t __iomem *reloc_entry;
673a394b 3284
673a394b 3285 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3286 reloc->target_handle);
673a394b
EA		 3287 if (target_obj == NULL) {
3288 i915_gem_object_unpin(obj);
3289 return -EBADF;
3290 }
3291 target_obj_priv = target_obj->driver_private;
3292
8542a0bb
CW		 3293#if WATCH_RELOC
3294 DRM_INFO("%s: obj %p offset %08x target %d "
3295 "read %08x write %08x gtt %08x "
3296 "presumed %08x delta %08x\n",
3297 __func__,
3298 obj,
3299 (int) reloc->offset,
3300 (int) reloc->target_handle,
3301 (int) reloc->read_domains,
3302 (int) reloc->write_domain,
3303 (int) target_obj_priv->gtt_offset,
3304 (int) reloc->presumed_offset,
3305 reloc->delta);
3306#endif
3307
673a394b
EA		 3308 /* The target buffer should have appeared before us in the
3309 * exec_object list, so it should have a GTT space bound by now.
3310 */
3311 if (target_obj_priv->gtt_space == NULL) {
3312 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3313 reloc->target_handle);
673a394b
EA		 3314 drm_gem_object_unreference(target_obj);
3315 i915_gem_object_unpin(obj);
3316 return -EINVAL;
3317 }
3318
8542a0bb 3319 /* Validate that the target is in a valid r/w GPU domain */
40a5f0de
EA		 3320 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3321 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3322 DRM_ERROR("reloc with read/write CPU domains: "
3323 "obj %p target %d offset %d "
3324 "read %08x write %08x",
40a5f0de
EA		 3325 obj, reloc->target_handle,
3326 (int) reloc->offset,
3327 reloc->read_domains,
3328 reloc->write_domain);
491152b8
CW		 3329 drm_gem_object_unreference(target_obj);
3330 i915_gem_object_unpin(obj);
e47c68e9
EA		 3331 return -EINVAL;
3332 }
40a5f0de
EA		 3333 if (reloc->write_domain && target_obj->pending_write_domain &&
3334 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3335 DRM_ERROR("Write domain conflict: "
3336 "obj %p target %d offset %d "
3337 "new %08x old %08x\n",
40a5f0de
EA		 3338 obj, reloc->target_handle,
3339 (int) reloc->offset,
3340 reloc->write_domain,
673a394b
EA		 3341 target_obj->pending_write_domain);
3342 drm_gem_object_unreference(target_obj);
3343 i915_gem_object_unpin(obj);
3344 return -EINVAL;
3345 }
3346
40a5f0de
EA		 3347 target_obj->pending_read_domains |= reloc->read_domains;
3348 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3349
3350 /* If the relocation already has the right value in it, no
3351 * more work needs to be done.
3352 */
40a5f0de 3353 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3354 drm_gem_object_unreference(target_obj);
3355 continue;
3356 }
3357
8542a0bb
CW		 3358 /* Check that the relocation address is valid... */
3359 if (reloc->offset > obj->size - 4) {
3360 DRM_ERROR("Relocation beyond object bounds: "
3361 "obj %p target %d offset %d size %d.\n",
3362 obj, reloc->target_handle,
3363 (int) reloc->offset, (int) obj->size);
3364 drm_gem_object_unreference(target_obj);
3365 i915_gem_object_unpin(obj);
3366 return -EINVAL;
3367 }
3368 if (reloc->offset & 3) {
3369 DRM_ERROR("Relocation not 4-byte aligned: "
3370 "obj %p target %d offset %d.\n",
3371 obj, reloc->target_handle,
3372 (int) reloc->offset);
3373 drm_gem_object_unreference(target_obj);
3374 i915_gem_object_unpin(obj);
3375 return -EINVAL;
3376 }
3377
3378 /* and points to somewhere within the target object. */
3379 if (reloc->delta >= target_obj->size) {
3380 DRM_ERROR("Relocation beyond target object bounds: "
3381 "obj %p target %d delta %d size %d.\n",
3382 obj, reloc->target_handle,
3383 (int) reloc->delta, (int) target_obj->size);
3384 drm_gem_object_unreference(target_obj);
3385 i915_gem_object_unpin(obj);
3386 return -EINVAL;
3387 }
3388
2ef7eeaa
EA		 3389 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3390 if (ret != 0) {
3391 drm_gem_object_unreference(target_obj);
3392 i915_gem_object_unpin(obj);
3393 return -EINVAL;
673a394b
EA		 3394 }
3395
3396 /* Map the page containing the relocation we're going to
3397 * perform.
3398 */
40a5f0de 3399 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3400 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3401 (reloc_offset &
3402 ~(PAGE_SIZE - 1)));
3043c60c 3403 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3404 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3405 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3406
3407#if WATCH_BUF
3408 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3409 obj, (unsigned int) reloc->offset,
673a394b
EA		 3410 readl(reloc_entry), reloc_val);
3411#endif
3412 writel(reloc_val, reloc_entry);
0839ccb8 3413 io_mapping_unmap_atomic(reloc_page);
673a394b 3414
40a5f0de
EA		 3415 /* The updated presumed offset for this entry will be
3416 * copied back out to the user.
673a394b 3417 */
40a5f0de 3418 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3419
3420 drm_gem_object_unreference(target_obj);
3421 }
3422
673a394b
EA		 3423#if WATCH_BUF
3424 if (0)
3425 i915_gem_dump_object(obj, 128, __func__, ~0);
3426#endif
3427 return 0;
3428}
3429
3430/** Dispatch a batchbuffer to the ring
3431 */
3432static int
3433i915_dispatch_gem_execbuffer(struct drm_device *dev,
76446cac 3434 struct drm_i915_gem_execbuffer2 *exec,
201361a5 3435 struct drm_clip_rect *cliprects,
673a394b
EA		 3436 uint64_t exec_offset)
3437{
3438 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3439 int nbox = exec->num_cliprects;
3440 int i = 0, count;
83d60795 3441 uint32_t exec_start, exec_len;
673a394b
EA		 3442 RING_LOCALS;
3443
3444 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3445 exec_len = (uint32_t) exec->batch_len;
3446
8f0dc5bf 3447 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
1c5d22f7 3448
673a394b
EA		 3449 count = nbox ? nbox : 1;
3450
3451 for (i = 0; i < count; i++) {
3452 if (i < nbox) {
201361a5 3453 int ret = i915_emit_box(dev, cliprects, i,
673a394b
EA		 3454 exec->DR1, exec->DR4);
3455 if (ret)
3456 return ret;
3457 }
3458
3459 if (IS_I830(dev) || IS_845G(dev)) {
3460 BEGIN_LP_RING(4);
3461 OUT_RING(MI_BATCH_BUFFER);
3462 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3463 OUT_RING(exec_start + exec_len - 4);
3464 OUT_RING(0);
3465 ADVANCE_LP_RING();
3466 } else {
3467 BEGIN_LP_RING(2);
3468 if (IS_I965G(dev)) {
3469 OUT_RING(MI_BATCH_BUFFER_START |
3470 (2 << 6) |
3471 MI_BATCH_NON_SECURE_I965);
3472 OUT_RING(exec_start);
3473 } else {
3474 OUT_RING(MI_BATCH_BUFFER_START |
3475 (2 << 6));
3476 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3477 }
3478 ADVANCE_LP_RING();
3479 }
3480 }
3481
3482 /* XXX breadcrumb */
3483 return 0;
3484}
3485
3486/* Throttle our rendering by waiting until the ring has completed our requests
3487 * emitted over 20 msec ago.
3488 *
b962442e
EA		 3489 * Note that if we were to use the current jiffies each time around the loop,
3490 * we wouldn't escape the function with any frames outstanding if the time to
3491 * render a frame was over 20ms.
3492 *
673a394b
EA		 3493 * This should get us reasonable parallelism between CPU and GPU but also
3494 * relatively low latency when blocking on a particular request to finish.
3495 */
3496static int
3497i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3498{
3499 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3500 int ret = 0;
b962442e 3501 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3502
3503 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3504 while (!list_empty(&i915_file_priv->mm.request_list)) {
3505 struct drm_i915_gem_request *request;
3506
3507 request = list_first_entry(&i915_file_priv->mm.request_list,
3508 struct drm_i915_gem_request,
3509 client_list);
3510
3511 if (time_after_eq(request->emitted_jiffies, recent_enough))
3512 break;
3513
3514 ret = i915_wait_request(dev, request->seqno);
3515 if (ret != 0)
3516 break;
3517 }
673a394b 3518 mutex_unlock(&dev->struct_mutex);
b962442e 3519
673a394b
EA		 3520 return ret;
3521}
3522
40a5f0de 3523static int
76446cac 3524i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3525 uint32_t buffer_count,
3526 struct drm_i915_gem_relocation_entry **relocs)
3527{
3528 uint32_t reloc_count = 0, reloc_index = 0, i;
3529 int ret;
3530
3531 *relocs = NULL;
3532 for (i = 0; i < buffer_count; i++) {
3533 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3534 return -EINVAL;
3535 reloc_count += exec_list[i].relocation_count;
3536 }
3537
8e7d2b2c 3538 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3539 if (*relocs == NULL) {
3540 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3541 return -ENOMEM;
76446cac 3542 }
40a5f0de
EA		 3543
3544 for (i = 0; i < buffer_count; i++) {
3545 struct drm_i915_gem_relocation_entry __user *user_relocs;
3546
3547 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3548
3549 ret = copy_from_user(&(*relocs)[reloc_index],
3550 user_relocs,
3551 exec_list[i].relocation_count *
3552 sizeof(**relocs));
3553 if (ret != 0) {
8e7d2b2c 3554 drm_free_large(*relocs);
40a5f0de 3555 *relocs = NULL;
2bc43b5c 3556 return -EFAULT;
40a5f0de
EA		 3557 }
3558
3559 reloc_index += exec_list[i].relocation_count;
3560 }
3561
2bc43b5c 3562 return 0;
40a5f0de
EA		 3563}
3564
3565static int
76446cac 3566i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3567 uint32_t buffer_count,
3568 struct drm_i915_gem_relocation_entry *relocs)
3569{
3570 uint32_t reloc_count = 0, i;
2bc43b5c 3571 int ret = 0;
40a5f0de 3572
93533c29
CW		 3573 if (relocs == NULL)
3574 return 0;
3575
40a5f0de
EA		 3576 for (i = 0; i < buffer_count; i++) {
3577 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3578 int unwritten;
40a5f0de
EA		 3579
3580 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3581
2bc43b5c
FM		 3582 unwritten = copy_to_user(user_relocs,
3583 &relocs[reloc_count],
3584 exec_list[i].relocation_count *
3585 sizeof(*relocs));
3586
3587 if (unwritten) {
3588 ret = -EFAULT;
3589 goto err;
40a5f0de
EA		 3590 }
3591
3592 reloc_count += exec_list[i].relocation_count;
3593 }
3594
2bc43b5c 3595err:
8e7d2b2c 3596 drm_free_large(relocs);
40a5f0de
EA		 3597
3598 return ret;
3599}
3600
83d60795 3601static int
76446cac 3602i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3603 uint64_t exec_offset)
3604{
3605 uint32_t exec_start, exec_len;
3606
3607 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3608 exec_len = (uint32_t) exec->batch_len;
3609
3610 if ((exec_start | exec_len) & 0x7)
3611 return -EINVAL;
3612
3613 if (!exec_start)
3614 return -EINVAL;
3615
3616 return 0;
3617}
3618
6b95a207
KH		 3619static int
3620i915_gem_wait_for_pending_flip(struct drm_device *dev,
3621 struct drm_gem_object **object_list,
3622 int count)
3623{
3624 drm_i915_private_t *dev_priv = dev->dev_private;
3625 struct drm_i915_gem_object *obj_priv;
3626 DEFINE_WAIT(wait);
3627 int i, ret = 0;
3628
3629 for (;;) {
3630 prepare_to_wait(&dev_priv->pending_flip_queue,
3631 &wait, TASK_INTERRUPTIBLE);
3632 for (i = 0; i < count; i++) {
3633 obj_priv = object_list[i]->driver_private;
3634 if (atomic_read(&obj_priv->pending_flip) > 0)
3635 break;
3636 }
3637 if (i == count)
3638 break;
3639
3640 if (!signal_pending(current)) {
3641 mutex_unlock(&dev->struct_mutex);
3642 schedule();
3643 mutex_lock(&dev->struct_mutex);
3644 continue;
3645 }
3646 ret = -ERESTARTSYS;
3647 break;
3648 }
3649 finish_wait(&dev_priv->pending_flip_queue, &wait);
3650
3651 return ret;
3652}
3653
673a394b 3654int
76446cac
JB		 3655i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3656 struct drm_file *file_priv,
3657 struct drm_i915_gem_execbuffer2 *args,
3658 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3659{
3660 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3661 struct drm_gem_object **object_list = NULL;
3662 struct drm_gem_object *batch_obj;
b70d11da 3663 struct drm_i915_gem_object *obj_priv;
201361a5 3664 struct drm_clip_rect *cliprects = NULL;
93533c29 3665 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3666 int ret = 0, ret2, i, pinned = 0;
673a394b 3667 uint64_t exec_offset;
40a5f0de 3668 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3669 int pin_tries, flips;
673a394b
EA		 3670
3671#if WATCH_EXEC
3672 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3673 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3674#endif
3675
4f481ed2
EA		 3676 if (args->buffer_count < 1) {
3677 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3678 return -EINVAL;
3679 }
c8e0f93a 3680 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3681 if (object_list == NULL) {
3682 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3683 args->buffer_count);
3684 ret = -ENOMEM;
3685 goto pre_mutex_err;
3686 }
673a394b 3687
201361a5 3688 if (args->num_cliprects != 0) {
9a298b2a
EA		 3689 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3690 GFP_KERNEL);
201361a5
EA		 3691 if (cliprects == NULL)
3692 goto pre_mutex_err;
3693
3694 ret = copy_from_user(cliprects,
3695 (struct drm_clip_rect __user *)
3696 (uintptr_t) args->cliprects_ptr,
3697 sizeof(*cliprects) * args->num_cliprects);
3698 if (ret != 0) {
3699 DRM_ERROR("copy %d cliprects failed: %d\n",
3700 args->num_cliprects, ret);
3701 goto pre_mutex_err;
3702 }
3703 }
3704
40a5f0de
EA		 3705 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3706 &relocs);
3707 if (ret != 0)
3708 goto pre_mutex_err;
3709
673a394b
EA		 3710 mutex_lock(&dev->struct_mutex);
3711
3712 i915_verify_inactive(dev, __FILE__, __LINE__);
3713
ba1234d1 3714 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3715 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3716 ret = -EIO;
3717 goto pre_mutex_err;
673a394b
EA		 3718 }
3719
3720 if (dev_priv->mm.suspended) {
673a394b 3721 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3722 ret = -EBUSY;
3723 goto pre_mutex_err;
673a394b
EA		 3724 }
3725
ac94a962 3726 /* Look up object handles */
6b95a207 3727 flips = 0;
673a394b
EA		 3728 for (i = 0; i < args->buffer_count; i++) {
3729 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3730 exec_list[i].handle);
3731 if (object_list[i] == NULL) {
3732 DRM_ERROR("Invalid object handle %d at index %d\n",
3733 exec_list[i].handle, i);
0ce907f8
CW		 3734 /* prevent error path from reading uninitialized data */
3735 args->buffer_count = i + 1;
673a394b
EA		 3736 ret = -EBADF;
3737 goto err;
3738 }
b70d11da
KH		 3739
3740 obj_priv = object_list[i]->driver_private;
3741 if (obj_priv->in_execbuffer) {
3742 DRM_ERROR("Object %p appears more than once in object list\n",
3743 object_list[i]);
0ce907f8
CW		 3744 /* prevent error path from reading uninitialized data */
3745 args->buffer_count = i + 1;
b70d11da
KH		 3746 ret = -EBADF;
3747 goto err;
3748 }
3749 obj_priv->in_execbuffer = true;
6b95a207
KH		 3750 flips += atomic_read(&obj_priv->pending_flip);
3751 }
3752
3753 if (flips > 0) {
3754 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3755 args->buffer_count);
3756 if (ret)
3757 goto err;
ac94a962 3758 }
673a394b 3759
ac94a962
KP		 3760 /* Pin and relocate */
3761 for (pin_tries = 0; ; pin_tries++) {
3762 ret = 0;
40a5f0de
EA		 3763 reloc_index = 0;
3764
ac94a962
KP		 3765 for (i = 0; i < args->buffer_count; i++) {
3766 object_list[i]->pending_read_domains = 0;
3767 object_list[i]->pending_write_domain = 0;
3768 ret = i915_gem_object_pin_and_relocate(object_list[i],
3769 file_priv,
40a5f0de
EA		 3770 &exec_list[i],
3771 &relocs[reloc_index]);
ac94a962
KP		 3772 if (ret)
3773 break;
3774 pinned = i + 1;
40a5f0de 3775 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3776 }
3777 /* success */
3778 if (ret == 0)
3779 break;
3780
3781 /* error other than GTT full, or we've already tried again */
2939e1f5 3782 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3783 if (ret != -ERESTARTSYS) {
3784 unsigned long long total_size = 0;
3785 for (i = 0; i < args->buffer_count; i++)
3786 total_size += object_list[i]->size;
3787 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3788 pinned+1, args->buffer_count,
3789 total_size, ret);
3790 DRM_ERROR("%d objects [%d pinned], "
3791 "%d object bytes [%d pinned], "
3792 "%d/%d gtt bytes\n",
3793 atomic_read(&dev->object_count),
3794 atomic_read(&dev->pin_count),
3795 atomic_read(&dev->object_memory),
3796 atomic_read(&dev->pin_memory),
3797 atomic_read(&dev->gtt_memory),
3798 dev->gtt_total);
3799 }
673a394b
EA		 3800 goto err;
3801 }
ac94a962
KP		 3802
3803 /* unpin all of our buffers */
3804 for (i = 0; i < pinned; i++)
3805 i915_gem_object_unpin(object_list[i]);
b1177636 3806 pinned = 0;
ac94a962
KP		 3807
3808 /* evict everyone we can from the aperture */
3809 ret = i915_gem_evict_everything(dev);
07f73f69 3810 if (ret && ret != -ENOSPC)
ac94a962 3811 goto err;
673a394b
EA		 3812 }
3813
3814 /* Set the pending read domains for the batch buffer to COMMAND */
3815 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3816 if (batch_obj->pending_write_domain) {
3817 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3818 ret = -EINVAL;
3819 goto err;
3820 }
3821 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3822
83d60795
CW		 3823 /* Sanity check the batch buffer, prior to moving objects */
3824 exec_offset = exec_list[args->buffer_count - 1].offset;
3825 ret = i915_gem_check_execbuffer (args, exec_offset);
3826 if (ret != 0) {
3827 DRM_ERROR("execbuf with invalid offset/length\n");
3828 goto err;
3829 }
3830
673a394b
EA		 3831 i915_verify_inactive(dev, __FILE__, __LINE__);
3832
646f0f6e
KP		 3833 /* Zero the global flush/invalidate flags. These
3834 * will be modified as new domains are computed
3835 * for each object
3836 */
3837 dev->invalidate_domains = 0;
3838 dev->flush_domains = 0;
3839
673a394b
EA		 3840 for (i = 0; i < args->buffer_count; i++) {
3841 struct drm_gem_object *obj = object_list[i];
673a394b 3842
646f0f6e 3843 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3844 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3845 }
3846
3847 i915_verify_inactive(dev, __FILE__, __LINE__);
3848
646f0f6e
KP		 3849 if (dev->invalidate_domains | dev->flush_domains) {
3850#if WATCH_EXEC
3851 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3852 __func__,
3853 dev->invalidate_domains,
3854 dev->flush_domains);
3855#endif
3856 i915_gem_flush(dev,
3857 dev->invalidate_domains,
3858 dev->flush_domains);
99fcb766 3859 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
b962442e
EA		 3860 (void)i915_add_request(dev, file_priv,
3861 dev->flush_domains);
646f0f6e 3862 }
673a394b 3863
efbeed96
EA		 3864 for (i = 0; i < args->buffer_count; i++) {
3865 struct drm_gem_object *obj = object_list[i];
99fcb766 3866 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1c5d22f7 3867 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3868
3869 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3870 if (obj->write_domain)
3871 list_move_tail(&obj_priv->gpu_write_list,
3872 &dev_priv->mm.gpu_write_list);
3873 else
3874 list_del_init(&obj_priv->gpu_write_list);
3875
1c5d22f7
CW		 3876 trace_i915_gem_object_change_domain(obj,
3877 obj->read_domains,
3878 old_write_domain);
efbeed96
EA		 3879 }
3880
673a394b
EA		 3881 i915_verify_inactive(dev, __FILE__, __LINE__);
3882
3883#if WATCH_COHERENCY
3884 for (i = 0; i < args->buffer_count; i++) {
3885 i915_gem_object_check_coherency(object_list[i],
3886 exec_list[i].handle);
3887 }
3888#endif
3889
673a394b 3890#if WATCH_EXEC
6911a9b8 3891 i915_gem_dump_object(batch_obj,
673a394b
EA		 3892 args->batch_len,
3893 __func__,
3894 ~0);
3895#endif
3896
673a394b 3897 /* Exec the batchbuffer */
201361a5 3898 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
673a394b
EA		 3899 if (ret) {
3900 DRM_ERROR("dispatch failed %d\n", ret);
3901 goto err;
3902 }
3903
3904 /*
3905 * Ensure that the commands in the batch buffer are
3906 * finished before the interrupt fires
3907 */
3908 flush_domains = i915_retire_commands(dev);
3909
3910 i915_verify_inactive(dev, __FILE__, __LINE__);
3911
3912 /*
3913 * Get a seqno representing the execution of the current buffer,
3914 * which we can wait on. We would like to mitigate these interrupts,
3915 * likely by only creating seqnos occasionally (so that we have
3916 * *some* interrupts representing completion of buffers that we can
3917 * wait on when trying to clear up gtt space).
3918 */
b962442e 3919 seqno = i915_add_request(dev, file_priv, flush_domains);
673a394b 3920 BUG_ON(seqno == 0);
673a394b
EA		 3921 for (i = 0; i < args->buffer_count; i++) {
3922 struct drm_gem_object *obj = object_list[i];
673a394b 3923
ce44b0ea 3924 i915_gem_object_move_to_active(obj, seqno);
673a394b
EA		 3925#if WATCH_LRU
3926 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3927#endif
3928 }
3929#if WATCH_LRU
3930 i915_dump_lru(dev, __func__);
3931#endif
3932
3933 i915_verify_inactive(dev, __FILE__, __LINE__);
3934
673a394b 3935err:
aad87dff
JL		 3936 for (i = 0; i < pinned; i++)
3937 i915_gem_object_unpin(object_list[i]);
3938
b70d11da
KH		 3939 for (i = 0; i < args->buffer_count; i++) {
3940 if (object_list[i]) {
3941 obj_priv = object_list[i]->driver_private;
3942 obj_priv->in_execbuffer = false;
3943 }
aad87dff 3944 drm_gem_object_unreference(object_list[i]);
b70d11da 3945 }
673a394b 3946
673a394b
EA		 3947 mutex_unlock(&dev->struct_mutex);
3948
93533c29 3949pre_mutex_err:
40a5f0de
EA		 3950 /* Copy the updated relocations out regardless of current error
3951 * state. Failure to update the relocs would mean that the next
3952 * time userland calls execbuf, it would do so with presumed offset
3953 * state that didn't match the actual object state.
3954 */
3955 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3956 relocs);
3957 if (ret2 != 0) {
3958 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3959
3960 if (ret == 0)
3961 ret = ret2;
3962 }
3963
8e7d2b2c 3964 drm_free_large(object_list);
9a298b2a 3965 kfree(cliprects);
673a394b
EA		 3966
3967 return ret;
3968}
3969
76446cac
JB		 3970/*
3971 * Legacy execbuffer just creates an exec2 list from the original exec object
3972 * list array and passes it to the real function.
3973 */
3974int
3975i915_gem_execbuffer(struct drm_device *dev, void *data,
3976 struct drm_file *file_priv)
3977{
3978 struct drm_i915_gem_execbuffer *args = data;
3979 struct drm_i915_gem_execbuffer2 exec2;
3980 struct drm_i915_gem_exec_object *exec_list = NULL;
3981 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3982 int ret, i;
3983
3984#if WATCH_EXEC
3985 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3986 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3987#endif
3988
3989 if (args->buffer_count < 1) {
3990 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3991 return -EINVAL;
3992 }
3993
3994 /* Copy in the exec list from userland */
3995 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3996 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3997 if (exec_list == NULL || exec2_list == NULL) {
3998 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3999 args->buffer_count);
4000 drm_free_large(exec_list);
4001 drm_free_large(exec2_list);
4002 return -ENOMEM;
4003 }
4004 ret = copy_from_user(exec_list,
4005 (struct drm_i915_relocation_entry __user *)
4006 (uintptr_t) args->buffers_ptr,
4007 sizeof(*exec_list) * args->buffer_count);
4008 if (ret != 0) {
4009 DRM_ERROR("copy %d exec entries failed %d\n",
4010 args->buffer_count, ret);
4011 drm_free_large(exec_list);
4012 drm_free_large(exec2_list);
4013 return -EFAULT;
4014 }
4015
4016 for (i = 0; i < args->buffer_count; i++) {
4017 exec2_list[i].handle = exec_list[i].handle;
4018 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4019 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4020 exec2_list[i].alignment = exec_list[i].alignment;
4021 exec2_list[i].offset = exec_list[i].offset;
4022 if (!IS_I965G(dev))
4023 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4024 else
4025 exec2_list[i].flags = 0;
4026 }
4027
4028 exec2.buffers_ptr = args->buffers_ptr;
4029 exec2.buffer_count = args->buffer_count;
4030 exec2.batch_start_offset = args->batch_start_offset;
4031 exec2.batch_len = args->batch_len;
4032 exec2.DR1 = args->DR1;
4033 exec2.DR4 = args->DR4;
4034 exec2.num_cliprects = args->num_cliprects;
4035 exec2.cliprects_ptr = args->cliprects_ptr;
4036 exec2.flags = 0;
4037
4038 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4039 if (!ret) {
4040 /* Copy the new buffer offsets back to the user's exec list. */
4041 for (i = 0; i < args->buffer_count; i++)
4042 exec_list[i].offset = exec2_list[i].offset;
4043 /* ... and back out to userspace */
4044 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4045 (uintptr_t) args->buffers_ptr,
4046 exec_list,
4047 sizeof(*exec_list) * args->buffer_count);
4048 if (ret) {
4049 ret = -EFAULT;
4050 DRM_ERROR("failed to copy %d exec entries "
4051 "back to user (%d)\n",
4052 args->buffer_count, ret);
4053 }
76446cac
JB		 4054 }
4055
4056 drm_free_large(exec_list);
4057 drm_free_large(exec2_list);
4058 return ret;
4059}
4060
4061int
4062i915_gem_execbuffer2(struct drm_device *dev, void *data,
4063 struct drm_file *file_priv)
4064{
4065 struct drm_i915_gem_execbuffer2 *args = data;
4066 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4067 int ret;
4068
4069#if WATCH_EXEC
4070 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4071 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4072#endif
4073
4074 if (args->buffer_count < 1) {
4075 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4076 return -EINVAL;
4077 }
4078
4079 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4080 if (exec2_list == NULL) {
4081 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4082 args->buffer_count);
4083 return -ENOMEM;
4084 }
4085 ret = copy_from_user(exec2_list,
4086 (struct drm_i915_relocation_entry __user *)
4087 (uintptr_t) args->buffers_ptr,
4088 sizeof(*exec2_list) * args->buffer_count);
4089 if (ret != 0) {
4090 DRM_ERROR("copy %d exec entries failed %d\n",
4091 args->buffer_count, ret);
4092 drm_free_large(exec2_list);
4093 return -EFAULT;
4094 }
4095
4096 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4097 if (!ret) {
4098 /* Copy the new buffer offsets back to the user's exec list. */
4099 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4100 (uintptr_t) args->buffers_ptr,
4101 exec2_list,
4102 sizeof(*exec2_list) * args->buffer_count);
4103 if (ret) {
4104 ret = -EFAULT;
4105 DRM_ERROR("failed to copy %d exec entries "
4106 "back to user (%d)\n",
4107 args->buffer_count, ret);
4108 }
4109 }
4110
4111 drm_free_large(exec2_list);
4112 return ret;
4113}
4114
673a394b
EA		 4115int
4116i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4117{
4118 struct drm_device *dev = obj->dev;
4119 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4120 int ret;
4121
4122 i915_verify_inactive(dev, __FILE__, __LINE__);
4123 if (obj_priv->gtt_space == NULL) {
4124 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4125 if (ret)
673a394b 4126 return ret;
22c344e9 4127 }
76446cac 4128
673a394b
EA		 4129 obj_priv->pin_count++;
4130
4131 /* If the object is not active and not pending a flush,
4132 * remove it from the inactive list
4133 */
4134 if (obj_priv->pin_count == 1) {
4135 atomic_inc(&dev->pin_count);
4136 atomic_add(obj->size, &dev->pin_memory);
4137 if (!obj_priv->active &&
21d509e3 4138 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 4139 !list_empty(&obj_priv->list))
4140 list_del_init(&obj_priv->list);
4141 }
4142 i915_verify_inactive(dev, __FILE__, __LINE__);
4143
4144 return 0;
4145}
4146
4147void
4148i915_gem_object_unpin(struct drm_gem_object *obj)
4149{
4150 struct drm_device *dev = obj->dev;
4151 drm_i915_private_t *dev_priv = dev->dev_private;
4152 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4153
4154 i915_verify_inactive(dev, __FILE__, __LINE__);
4155 obj_priv->pin_count--;
4156 BUG_ON(obj_priv->pin_count < 0);
4157 BUG_ON(obj_priv->gtt_space == NULL);
4158
4159 /* If the object is no longer pinned, and is
4160 * neither active nor being flushed, then stick it on
4161 * the inactive list
4162 */
4163 if (obj_priv->pin_count == 0) {
4164 if (!obj_priv->active &&
21d509e3 4165 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4166 list_move_tail(&obj_priv->list,
4167 &dev_priv->mm.inactive_list);
4168 atomic_dec(&dev->pin_count);
4169 atomic_sub(obj->size, &dev->pin_memory);
4170 }
4171 i915_verify_inactive(dev, __FILE__, __LINE__);
4172}
4173
4174int
4175i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4176 struct drm_file *file_priv)
4177{
4178 struct drm_i915_gem_pin *args = data;
4179 struct drm_gem_object *obj;
4180 struct drm_i915_gem_object *obj_priv;
4181 int ret;
4182
4183 mutex_lock(&dev->struct_mutex);
4184
4185 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4186 if (obj == NULL) {
4187 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4188 args->handle);
4189 mutex_unlock(&dev->struct_mutex);
4190 return -EBADF;
4191 }
4192 obj_priv = obj->driver_private;
4193
bb6baf76
CW		 4194 if (obj_priv->madv != I915_MADV_WILLNEED) {
4195 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4196 drm_gem_object_unreference(obj);
4197 mutex_unlock(&dev->struct_mutex);
4198 return -EINVAL;
4199 }
4200
79e53945
JB		 4201 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4202 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4203 args->handle);
96dec61d 4204 drm_gem_object_unreference(obj);
673a394b 4205 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4206 return -EINVAL;
4207 }
4208
4209 obj_priv->user_pin_count++;
4210 obj_priv->pin_filp = file_priv;
4211 if (obj_priv->user_pin_count == 1) {
4212 ret = i915_gem_object_pin(obj, args->alignment);
4213 if (ret != 0) {
4214 drm_gem_object_unreference(obj);
4215 mutex_unlock(&dev->struct_mutex);
4216 return ret;
4217 }
673a394b
EA		 4218 }
4219
4220 /* XXX - flush the CPU caches for pinned objects
4221 * as the X server doesn't manage domains yet
4222 */
e47c68e9 4223 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4224 args->offset = obj_priv->gtt_offset;
4225 drm_gem_object_unreference(obj);
4226 mutex_unlock(&dev->struct_mutex);
4227
4228 return 0;
4229}
4230
4231int
4232i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4233 struct drm_file *file_priv)
4234{
4235 struct drm_i915_gem_pin *args = data;
4236 struct drm_gem_object *obj;
79e53945 4237 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4238
4239 mutex_lock(&dev->struct_mutex);
4240
4241 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4242 if (obj == NULL) {
4243 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4244 args->handle);
4245 mutex_unlock(&dev->struct_mutex);
4246 return -EBADF;
4247 }
4248
79e53945
JB		 4249 obj_priv = obj->driver_private;
4250 if (obj_priv->pin_filp != file_priv) {
4251 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4252 args->handle);
4253 drm_gem_object_unreference(obj);
4254 mutex_unlock(&dev->struct_mutex);
4255 return -EINVAL;
4256 }
4257 obj_priv->user_pin_count--;
4258 if (obj_priv->user_pin_count == 0) {
4259 obj_priv->pin_filp = NULL;
4260 i915_gem_object_unpin(obj);
4261 }
673a394b
EA		 4262
4263 drm_gem_object_unreference(obj);
4264 mutex_unlock(&dev->struct_mutex);
4265 return 0;
4266}
4267
4268int
4269i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4270 struct drm_file *file_priv)
4271{
4272 struct drm_i915_gem_busy *args = data;
4273 struct drm_gem_object *obj;
4274 struct drm_i915_gem_object *obj_priv;
4275
673a394b
EA		 4276 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4277 if (obj == NULL) {
4278 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4279 args->handle);
673a394b
EA		 4280 return -EBADF;
4281 }
4282
b1ce786c 4283 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4284 /* Update the active list for the hardware's current position.
4285 * Otherwise this only updates on a delayed timer or when irqs are
4286 * actually unmasked, and our working set ends up being larger than
4287 * required.
4288 */
4289 i915_gem_retire_requests(dev);
4290
673a394b 4291 obj_priv = obj->driver_private;
c4de0a5d
EA		 4292 /* Don't count being on the flushing list against the object being
4293 * done. Otherwise, a buffer left on the flushing list but not getting
4294 * flushed (because nobody's flushing that domain) won't ever return
4295 * unbusy and get reused by libdrm's bo cache. The other expected
4296 * consumer of this interface, OpenGL's occlusion queries, also specs
4297 * that the objects get unbusy "eventually" without any interference.
4298 */
4299 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4300
4301 drm_gem_object_unreference(obj);
4302 mutex_unlock(&dev->struct_mutex);
4303 return 0;
4304}
4305
4306int
4307i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4308 struct drm_file *file_priv)
4309{
4310 return i915_gem_ring_throttle(dev, file_priv);
4311}
4312
3ef94daa
CW		 4313int
4314i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4315 struct drm_file *file_priv)
4316{
4317 struct drm_i915_gem_madvise *args = data;
4318 struct drm_gem_object *obj;
4319 struct drm_i915_gem_object *obj_priv;
4320
4321 switch (args->madv) {
4322 case I915_MADV_DONTNEED:
4323 case I915_MADV_WILLNEED:
4324 break;
4325 default:
4326 return -EINVAL;
4327 }
4328
4329 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4330 if (obj == NULL) {
4331 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4332 args->handle);
4333 return -EBADF;
4334 }
4335
4336 mutex_lock(&dev->struct_mutex);
4337 obj_priv = obj->driver_private;
4338
4339 if (obj_priv->pin_count) {
4340 drm_gem_object_unreference(obj);
4341 mutex_unlock(&dev->struct_mutex);
4342
4343 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4344 return -EINVAL;
4345 }
4346
bb6baf76
CW		 4347 if (obj_priv->madv != __I915_MADV_PURGED)
4348 obj_priv->madv = args->madv;
3ef94daa 4349
2d7ef395
CW		 4350 /* if the object is no longer bound, discard its backing storage */
4351 if (i915_gem_object_is_purgeable(obj_priv) &&
4352 obj_priv->gtt_space == NULL)
4353 i915_gem_object_truncate(obj);
4354
bb6baf76
CW		 4355 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4356
3ef94daa
CW		 4357 drm_gem_object_unreference(obj);
4358 mutex_unlock(&dev->struct_mutex);
4359
4360 return 0;
4361}
4362
673a394b
EA		 4363int i915_gem_init_object(struct drm_gem_object *obj)
4364{
4365 struct drm_i915_gem_object *obj_priv;
4366
9a298b2a 4367 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
673a394b
EA		 4368 if (obj_priv == NULL)
4369 return -ENOMEM;
4370
4371 /*
4372 * We've just allocated pages from the kernel,
4373 * so they've just been written by the CPU with
4374 * zeros. They'll need to be clflushed before we
4375 * use them with the GPU.
4376 */
4377 obj->write_domain = I915_GEM_DOMAIN_CPU;
4378 obj->read_domains = I915_GEM_DOMAIN_CPU;
4379
ba1eb1d8
KP		 4380 obj_priv->agp_type = AGP_USER_MEMORY;
4381
673a394b
EA		 4382 obj->driver_private = obj_priv;
4383 obj_priv->obj = obj;
de151cf6 4384 obj_priv->fence_reg = I915_FENCE_REG_NONE;
673a394b 4385 INIT_LIST_HEAD(&obj_priv->list);
99fcb766 4386 INIT_LIST_HEAD(&obj_priv->gpu_write_list);
a09ba7fa 4387 INIT_LIST_HEAD(&obj_priv->fence_list);
3ef94daa 4388 obj_priv->madv = I915_MADV_WILLNEED;
de151cf6 4389
1c5d22f7 4390 trace_i915_gem_object_create(obj);
de151cf6 4391
673a394b
EA		 4392 return 0;
4393}
4394
4395void i915_gem_free_object(struct drm_gem_object *obj)
4396{
de151cf6 4397 struct drm_device *dev = obj->dev;
673a394b
EA		 4398 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4399
1c5d22f7
CW		 4400 trace_i915_gem_object_destroy(obj);
4401
673a394b
EA		 4402 while (obj_priv->pin_count > 0)
4403 i915_gem_object_unpin(obj);
4404
71acb5eb
DA		 4405 if (obj_priv->phys_obj)
4406 i915_gem_detach_phys_object(dev, obj);
4407
673a394b
EA		 4408 i915_gem_object_unbind(obj);
4409
7e616158
CW		 4410 if (obj_priv->mmap_offset)
4411 i915_gem_free_mmap_offset(obj);
de151cf6 4412
9a298b2a 4413 kfree(obj_priv->page_cpu_valid);
280b713b 4414 kfree(obj_priv->bit_17);
9a298b2a 4415 kfree(obj->driver_private);
673a394b
EA		 4416}
4417
ab5ee576 4418/** Unbinds all inactive objects. */
673a394b 4419static int
ab5ee576 4420i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4421{
ab5ee576 4422 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4423
ab5ee576
CW		 4424 while (!list_empty(&dev_priv->mm.inactive_list)) {
4425 struct drm_gem_object *obj;
4426 int ret;
673a394b 4427
ab5ee576
CW		 4428 obj = list_first_entry(&dev_priv->mm.inactive_list,
4429 struct drm_i915_gem_object,
4430 list)->obj;
673a394b
EA		 4431
4432 ret = i915_gem_object_unbind(obj);
4433 if (ret != 0) {
ab5ee576 4434 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4435 return ret;
4436 }
4437 }
4438
673a394b
EA		 4439 return 0;
4440}
4441
5669fcac 4442int
673a394b
EA		 4443i915_gem_idle(struct drm_device *dev)
4444{
4445 drm_i915_private_t *dev_priv = dev->dev_private;
4446 uint32_t seqno, cur_seqno, last_seqno;
4447 int stuck, ret;
4448
6dbe2772
KP		 4449 mutex_lock(&dev->struct_mutex);
4450
4451 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4452 mutex_unlock(&dev->struct_mutex);
673a394b 4453 return 0;
6dbe2772 4454 }
673a394b
EA		 4455
4456 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4457 * We need to replace this with a semaphore, or something.
4458 */
4459 dev_priv->mm.suspended = 1;
f65d9421 4460 del_timer(&dev_priv->hangcheck_timer);
673a394b 4461
6dbe2772
KP		 4462 /* Cancel the retire work handler, wait for it to finish if running
4463 */
4464 mutex_unlock(&dev->struct_mutex);
4465 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4466 mutex_lock(&dev->struct_mutex);
4467
673a394b
EA		 4468 i915_kernel_lost_context(dev);
4469
4470 /* Flush the GPU along with all non-CPU write domains
4471 */
21d509e3
CW		 4472 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4473 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
673a394b
EA		 4474
4475 if (seqno == 0) {
4476 mutex_unlock(&dev->struct_mutex);
4477 return -ENOMEM;
4478 }
4479
4480 dev_priv->mm.waiting_gem_seqno = seqno;
4481 last_seqno = 0;
4482 stuck = 0;
4483 for (;;) {
4484 cur_seqno = i915_get_gem_seqno(dev);
4485 if (i915_seqno_passed(cur_seqno, seqno))
4486 break;
4487 if (last_seqno == cur_seqno) {
4488 if (stuck++ > 100) {
4489 DRM_ERROR("hardware wedged\n");
ba1234d1 4490 atomic_set(&dev_priv->mm.wedged, 1);
673a394b
EA		 4491 DRM_WAKEUP(&dev_priv->irq_queue);
4492 break;
4493 }
4494 }
4495 msleep(10);
4496 last_seqno = cur_seqno;
4497 }
4498 dev_priv->mm.waiting_gem_seqno = 0;
4499
4500 i915_gem_retire_requests(dev);
4501
5e118f41 4502 spin_lock(&dev_priv->mm.active_list_lock);
ba1234d1 4503 if (!atomic_read(&dev_priv->mm.wedged)) {
28dfe52a
EA		 4504 /* Active and flushing should now be empty as we've
4505 * waited for a sequence higher than any pending execbuffer
4506 */
4507 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4508 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4509 /* Request should now be empty as we've also waited
4510 * for the last request in the list
4511 */
4512 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4513 }
673a394b 4514
28dfe52a
EA		 4515 /* Empty the active and flushing lists to inactive. If there's
4516 * anything left at this point, it means that we're wedged and
4517 * nothing good's going to happen by leaving them there. So strip
4518 * the GPU domains and just stuff them onto inactive.
673a394b 4519 */
28dfe52a 4520 while (!list_empty(&dev_priv->mm.active_list)) {
1c5d22f7
CW		 4521 struct drm_gem_object *obj;
4522 uint32_t old_write_domain;
673a394b 4523
1c5d22f7
CW		 4524 obj = list_first_entry(&dev_priv->mm.active_list,
4525 struct drm_i915_gem_object,
4526 list)->obj;
4527 old_write_domain = obj->write_domain;
4528 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4529 i915_gem_object_move_to_inactive(obj);
4530
4531 trace_i915_gem_object_change_domain(obj,
4532 obj->read_domains,
4533 old_write_domain);
28dfe52a 4534 }
5e118f41 4535 spin_unlock(&dev_priv->mm.active_list_lock);
28dfe52a
EA		 4536
4537 while (!list_empty(&dev_priv->mm.flushing_list)) {
1c5d22f7
CW		 4538 struct drm_gem_object *obj;
4539 uint32_t old_write_domain;
28dfe52a 4540
1c5d22f7
CW		 4541 obj = list_first_entry(&dev_priv->mm.flushing_list,
4542 struct drm_i915_gem_object,
4543 list)->obj;
4544 old_write_domain = obj->write_domain;
4545 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4546 i915_gem_object_move_to_inactive(obj);
4547
4548 trace_i915_gem_object_change_domain(obj,
4549 obj->read_domains,
4550 old_write_domain);
28dfe52a
EA		 4551 }
4552
4553
4554 /* Move all inactive buffers out of the GTT. */
ab5ee576 4555 ret = i915_gem_evict_from_inactive_list(dev);
28dfe52a 4556 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
6dbe2772
KP		 4557 if (ret) {
4558 mutex_unlock(&dev->struct_mutex);
673a394b 4559 return ret;
6dbe2772 4560 }
673a394b 4561
6dbe2772
KP		 4562 i915_gem_cleanup_ringbuffer(dev);
4563 mutex_unlock(&dev->struct_mutex);
4564
673a394b
EA		 4565 return 0;
4566}
4567
4568static int
4569i915_gem_init_hws(struct drm_device *dev)
4570{
4571 drm_i915_private_t *dev_priv = dev->dev_private;
4572 struct drm_gem_object *obj;
4573 struct drm_i915_gem_object *obj_priv;
4574 int ret;
4575
4576 /* If we need a physical address for the status page, it's already
4577 * initialized at driver load time.
4578 */
4579 if (!I915_NEED_GFX_HWS(dev))
4580 return 0;
4581
4582 obj = drm_gem_object_alloc(dev, 4096);
4583 if (obj == NULL) {
4584 DRM_ERROR("Failed to allocate status page\n");
4585 return -ENOMEM;
4586 }
4587 obj_priv = obj->driver_private;
ba1eb1d8 4588 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
673a394b
EA		 4589
4590 ret = i915_gem_object_pin(obj, 4096);
4591 if (ret != 0) {
4592 drm_gem_object_unreference(obj);
4593 return ret;
4594 }
4595
4596 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
673a394b 4597
856fa198 4598 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
ba1eb1d8 4599 if (dev_priv->hw_status_page == NULL) {
673a394b
EA		 4600 DRM_ERROR("Failed to map status page.\n");
4601 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3eb2ee77 4602 i915_gem_object_unpin(obj);
673a394b
EA		 4603 drm_gem_object_unreference(obj);
4604 return -EINVAL;
4605 }
4606 dev_priv->hws_obj = obj;
673a394b
EA		 4607 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4608 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
ba1eb1d8 4609 I915_READ(HWS_PGA); /* posting read */
44d98a61 4610 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
673a394b
EA		 4611
4612 return 0;
4613}
4614
85a7bb98
CW		 4615static void
4616i915_gem_cleanup_hws(struct drm_device *dev)
4617{
4618 drm_i915_private_t *dev_priv = dev->dev_private;
bab2d1f6
CW		 4619 struct drm_gem_object *obj;
4620 struct drm_i915_gem_object *obj_priv;
85a7bb98
CW		 4621
4622 if (dev_priv->hws_obj == NULL)
4623 return;
4624
bab2d1f6
CW		 4625 obj = dev_priv->hws_obj;
4626 obj_priv = obj->driver_private;
4627
856fa198 4628 kunmap(obj_priv->pages[0]);
85a7bb98
CW		 4629 i915_gem_object_unpin(obj);
4630 drm_gem_object_unreference(obj);
4631 dev_priv->hws_obj = NULL;
bab2d1f6 4632
85a7bb98
CW		 4633 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4634 dev_priv->hw_status_page = NULL;
4635
4636 /* Write high address into HWS_PGA when disabling. */
4637 I915_WRITE(HWS_PGA, 0x1ffff000);
4638}
4639
79e53945 4640int
673a394b
EA		 4641i915_gem_init_ringbuffer(struct drm_device *dev)
4642{
4643 drm_i915_private_t *dev_priv = dev->dev_private;
4644 struct drm_gem_object *obj;
4645 struct drm_i915_gem_object *obj_priv;
79e53945 4646 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
673a394b 4647 int ret;
50aa253d 4648 u32 head;
673a394b
EA		 4649
4650 ret = i915_gem_init_hws(dev);
4651 if (ret != 0)
4652 return ret;
4653
4654 obj = drm_gem_object_alloc(dev, 128 * 1024);
4655 if (obj == NULL) {
4656 DRM_ERROR("Failed to allocate ringbuffer\n");
85a7bb98 4657 i915_gem_cleanup_hws(dev);
673a394b
EA		 4658 return -ENOMEM;
4659 }
4660 obj_priv = obj->driver_private;
4661
4662 ret = i915_gem_object_pin(obj, 4096);
4663 if (ret != 0) {
4664 drm_gem_object_unreference(obj);
85a7bb98 4665 i915_gem_cleanup_hws(dev);
673a394b
EA		 4666 return ret;
4667 }
4668
4669 /* Set up the kernel mapping for the ring. */
79e53945 4670 ring->Size = obj->size;
673a394b 4671
79e53945
JB		 4672 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4673 ring->map.size = obj->size;
4674 ring->map.type = 0;
4675 ring->map.flags = 0;
4676 ring->map.mtrr = 0;
673a394b 4677
79e53945
JB		 4678 drm_core_ioremap_wc(&ring->map, dev);
4679 if (ring->map.handle == NULL) {
673a394b
EA		 4680 DRM_ERROR("Failed to map ringbuffer.\n");
4681 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
47ed185a 4682 i915_gem_object_unpin(obj);
673a394b 4683 drm_gem_object_unreference(obj);
85a7bb98 4684 i915_gem_cleanup_hws(dev);
673a394b
EA		 4685 return -EINVAL;
4686 }
79e53945
JB		 4687 ring->ring_obj = obj;
4688 ring->virtual_start = ring->map.handle;
673a394b
EA		 4689
4690 /* Stop the ring if it's running. */
4691 I915_WRITE(PRB0_CTL, 0);
673a394b 4692 I915_WRITE(PRB0_TAIL, 0);
50aa253d 4693 I915_WRITE(PRB0_HEAD, 0);
673a394b
EA		 4694
4695 /* Initialize the ring. */
4696 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
50aa253d
KP		 4697 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4698
4699 /* G45 ring initialization fails to reset head to zero */
4700 if (head != 0) {
4701 DRM_ERROR("Ring head not reset to zero "
4702 "ctl %08x head %08x tail %08x start %08x\n",
4703 I915_READ(PRB0_CTL),
4704 I915_READ(PRB0_HEAD),
4705 I915_READ(PRB0_TAIL),
4706 I915_READ(PRB0_START));
4707 I915_WRITE(PRB0_HEAD, 0);
4708
4709 DRM_ERROR("Ring head forced to zero "
4710 "ctl %08x head %08x tail %08x start %08x\n",
4711 I915_READ(PRB0_CTL),
4712 I915_READ(PRB0_HEAD),
4713 I915_READ(PRB0_TAIL),
4714 I915_READ(PRB0_START));
4715 }
4716
673a394b
EA		 4717 I915_WRITE(PRB0_CTL,
4718 ((obj->size - 4096) & RING_NR_PAGES) |
4719 RING_NO_REPORT |
4720 RING_VALID);
4721
50aa253d
KP		 4722 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4723
4724 /* If the head is still not zero, the ring is dead */
4725 if (head != 0) {
4726 DRM_ERROR("Ring initialization failed "
4727 "ctl %08x head %08x tail %08x start %08x\n",
4728 I915_READ(PRB0_CTL),
4729 I915_READ(PRB0_HEAD),
4730 I915_READ(PRB0_TAIL),
4731 I915_READ(PRB0_START));
4732 return -EIO;
4733 }
4734
673a394b 4735 /* Update our cache of the ring state */
79e53945
JB		 4736 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4737 i915_kernel_lost_context(dev);
4738 else {
4739 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4740 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4741 ring->space = ring->head - (ring->tail + 8);
4742 if (ring->space < 0)
4743 ring->space += ring->Size;
4744 }
673a394b
EA		 4745
4746 return 0;
4747}
4748
79e53945 4749void
673a394b
EA		 4750i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4751{
4752 drm_i915_private_t *dev_priv = dev->dev_private;
4753
4754 if (dev_priv->ring.ring_obj == NULL)
4755 return;
4756
4757 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4758
4759 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4760 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4761 dev_priv->ring.ring_obj = NULL;
4762 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4763
85a7bb98 4764 i915_gem_cleanup_hws(dev);
673a394b
EA		 4765}
4766
4767int
4768i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4769 struct drm_file *file_priv)
4770{
4771 drm_i915_private_t *dev_priv = dev->dev_private;
4772 int ret;
4773
79e53945
JB		 4774 if (drm_core_check_feature(dev, DRIVER_MODESET))
4775 return 0;
4776
ba1234d1 4777 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4778 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4779 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4780 }
4781
673a394b 4782 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4783 dev_priv->mm.suspended = 0;
4784
4785 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4786 if (ret != 0) {
4787 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4788 return ret;
d816f6ac 4789 }
9bb2d6f9 4790
5e118f41 4791 spin_lock(&dev_priv->mm.active_list_lock);
673a394b 4792 BUG_ON(!list_empty(&dev_priv->mm.active_list));
5e118f41
CW		 4793 spin_unlock(&dev_priv->mm.active_list_lock);
4794
673a394b
EA		 4795 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4796 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4797 BUG_ON(!list_empty(&dev_priv->mm.request_list));
673a394b 4798 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4799
4800 drm_irq_install(dev);
4801
673a394b
EA		 4802 return 0;
4803}
4804
4805int
4806i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4807 struct drm_file *file_priv)
4808{
79e53945
JB		 4809 if (drm_core_check_feature(dev, DRIVER_MODESET))
4810 return 0;
4811
dbb19d30 4812 drm_irq_uninstall(dev);
e6890f6f 4813 return i915_gem_idle(dev);
673a394b
EA		 4814}
4815
4816void
4817i915_gem_lastclose(struct drm_device *dev)
4818{
4819 int ret;
673a394b 4820
e806b495
EA		 4821 if (drm_core_check_feature(dev, DRIVER_MODESET))
4822 return;
4823
6dbe2772
KP		 4824 ret = i915_gem_idle(dev);
4825 if (ret)
4826 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4827}
4828
4829void
4830i915_gem_load(struct drm_device *dev)
4831{
b5aa8a0f 4832 int i;
673a394b
EA		 4833 drm_i915_private_t *dev_priv = dev->dev_private;
4834
5e118f41 4835 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b
EA		 4836 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4837 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4838 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b
EA		 4839 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4840 INIT_LIST_HEAD(&dev_priv->mm.request_list);
a09ba7fa 4841 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
673a394b
EA		 4842 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4843 i915_gem_retire_work_handler);
4844 dev_priv->mm.next_gem_seqno = 1;
4845
31169714
CW		 4846 spin_lock(&shrink_list_lock);
4847 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4848 spin_unlock(&shrink_list_lock);
4849
de151cf6
JB		 4850 /* Old X drivers will take 0-2 for front, back, depth buffers */
4851 dev_priv->fence_reg_start = 3;
4852
0f973f27 4853 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4854 dev_priv->num_fence_regs = 16;
4855 else
4856 dev_priv->num_fence_regs = 8;
4857
b5aa8a0f
GH		 4858 /* Initialize fence registers to zero */
4859 if (IS_I965G(dev)) {
4860 for (i = 0; i < 16; i++)
4861 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4862 } else {
4863 for (i = 0; i < 8; i++)
4864 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4865 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4866 for (i = 0; i < 8; i++)
4867 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4868 }
673a394b 4869 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4870 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4871}
71acb5eb
DA		 4872
4873/*
4874 * Create a physically contiguous memory object for this object
4875 * e.g. for cursor + overlay regs
4876 */
4877int i915_gem_init_phys_object(struct drm_device *dev,
4878 int id, int size)
4879{
4880 drm_i915_private_t *dev_priv = dev->dev_private;
4881 struct drm_i915_gem_phys_object *phys_obj;
4882 int ret;
4883
4884 if (dev_priv->mm.phys_objs[id - 1] || !size)
4885 return 0;
4886
9a298b2a 4887 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4888 if (!phys_obj)
4889 return -ENOMEM;
4890
4891 phys_obj->id = id;
4892
e6be8d9d 4893 phys_obj->handle = drm_pci_alloc(dev, size, 0);
71acb5eb
DA		 4894 if (!phys_obj->handle) {
4895 ret = -ENOMEM;
4896 goto kfree_obj;
4897 }
4898#ifdef CONFIG_X86
4899 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4900#endif
4901
4902 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4903
4904 return 0;
4905kfree_obj:
9a298b2a 4906 kfree(phys_obj);
71acb5eb
DA		 4907 return ret;
4908}
4909
4910void i915_gem_free_phys_object(struct drm_device *dev, int id)
4911{
4912 drm_i915_private_t *dev_priv = dev->dev_private;
4913 struct drm_i915_gem_phys_object *phys_obj;
4914
4915 if (!dev_priv->mm.phys_objs[id - 1])
4916 return;
4917
4918 phys_obj = dev_priv->mm.phys_objs[id - 1];
4919 if (phys_obj->cur_obj) {
4920 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4921 }
4922
4923#ifdef CONFIG_X86
4924 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4925#endif
4926 drm_pci_free(dev, phys_obj->handle);
4927 kfree(phys_obj);
4928 dev_priv->mm.phys_objs[id - 1] = NULL;
4929}
4930
4931void i915_gem_free_all_phys_object(struct drm_device *dev)
4932{
4933 int i;
4934
260883c8 4935 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4936 i915_gem_free_phys_object(dev, i);
4937}
4938
4939void i915_gem_detach_phys_object(struct drm_device *dev,
4940 struct drm_gem_object *obj)
4941{
4942 struct drm_i915_gem_object *obj_priv;
4943 int i;
4944 int ret;
4945 int page_count;
4946
4947 obj_priv = obj->driver_private;
4948 if (!obj_priv->phys_obj)
4949 return;
4950
4bdadb97 4951 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4952 if (ret)
4953 goto out;
4954
4955 page_count = obj->size / PAGE_SIZE;
4956
4957 for (i = 0; i < page_count; i++) {
856fa198 4958 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4959 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4960
4961 memcpy(dst, src, PAGE_SIZE);
4962 kunmap_atomic(dst, KM_USER0);
4963 }
856fa198 4964 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4965 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4966
4967 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4968out:
4969 obj_priv->phys_obj->cur_obj = NULL;
4970 obj_priv->phys_obj = NULL;
4971}
4972
4973int
4974i915_gem_attach_phys_object(struct drm_device *dev,
4975 struct drm_gem_object *obj, int id)
4976{
4977 drm_i915_private_t *dev_priv = dev->dev_private;
4978 struct drm_i915_gem_object *obj_priv;
4979 int ret = 0;
4980 int page_count;
4981 int i;
4982
4983 if (id > I915_MAX_PHYS_OBJECT)
4984 return -EINVAL;
4985
4986 obj_priv = obj->driver_private;
4987
4988 if (obj_priv->phys_obj) {
4989 if (obj_priv->phys_obj->id == id)
4990 return 0;
4991 i915_gem_detach_phys_object(dev, obj);
4992 }
4993
4994
4995 /* create a new object */
4996 if (!dev_priv->mm.phys_objs[id - 1]) {
4997 ret = i915_gem_init_phys_object(dev, id,
4998 obj->size);
4999 if (ret) {
aeb565df 5000 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 5001 goto out;
5002 }
5003 }
5004
5005 /* bind to the object */
5006 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
5007 obj_priv->phys_obj->cur_obj = obj;
5008
4bdadb97 5009 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 5010 if (ret) {
5011 DRM_ERROR("failed to get page list\n");
5012 goto out;
5013 }
5014
5015 page_count = obj->size / PAGE_SIZE;
5016
5017 for (i = 0; i < page_count; i++) {
856fa198 5018 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 5019 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5020
5021 memcpy(dst, src, PAGE_SIZE);
5022 kunmap_atomic(src, KM_USER0);
5023 }
5024
d78b47b9
CW		 5025 i915_gem_object_put_pages(obj);
5026
71acb5eb
DA		 5027 return 0;
5028out:
5029 return ret;
5030}
5031
5032static int
5033i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5034 struct drm_i915_gem_pwrite *args,
5035 struct drm_file *file_priv)
5036{
5037 struct drm_i915_gem_object *obj_priv = obj->driver_private;
5038 void *obj_addr;
5039 int ret;
5040 char __user *user_data;
5041
5042 user_data = (char __user *) (uintptr_t) args->data_ptr;
5043 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5044
44d98a61 5045 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 5046 ret = copy_from_user(obj_addr, user_data, args->size);
5047 if (ret)
5048 return -EFAULT;
5049
5050 drm_agp_chipset_flush(dev);
5051 return 0;
5052}
b962442e
EA		 5053
5054void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5055{
5056 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5057
5058 /* Clean up our request list when the client is going away, so that
5059 * later retire_requests won't dereference our soon-to-be-gone
5060 * file_priv.
5061 */
5062 mutex_lock(&dev->struct_mutex);
5063 while (!list_empty(&i915_file_priv->mm.request_list))
5064 list_del_init(i915_file_priv->mm.request_list.next);
5065 mutex_unlock(&dev->struct_mutex);
5066}
31169714 5067
31169714
CW		 5068static int
5069i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5070{
5071 drm_i915_private_t *dev_priv, *next_dev;
5072 struct drm_i915_gem_object *obj_priv, *next_obj;
5073 int cnt = 0;
5074 int would_deadlock = 1;
5075
5076 /* "fast-path" to count number of available objects */
5077 if (nr_to_scan == 0) {
5078 spin_lock(&shrink_list_lock);
5079 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5080 struct drm_device *dev = dev_priv->dev;
5081
5082 if (mutex_trylock(&dev->struct_mutex)) {
5083 list_for_each_entry(obj_priv,
5084 &dev_priv->mm.inactive_list,
5085 list)
5086 cnt++;
5087 mutex_unlock(&dev->struct_mutex);
5088 }
5089 }
5090 spin_unlock(&shrink_list_lock);
5091
5092 return (cnt / 100) * sysctl_vfs_cache_pressure;
5093 }
5094
5095 spin_lock(&shrink_list_lock);
5096
5097 /* first scan for clean buffers */
5098 list_for_each_entry_safe(dev_priv, next_dev,
5099 &shrink_list, mm.shrink_list) {
5100 struct drm_device *dev = dev_priv->dev;
5101
5102 if (! mutex_trylock(&dev->struct_mutex))
5103 continue;
5104
5105 spin_unlock(&shrink_list_lock);
5106
5107 i915_gem_retire_requests(dev);
5108
5109 list_for_each_entry_safe(obj_priv, next_obj,
5110 &dev_priv->mm.inactive_list,
5111 list) {
5112 if (i915_gem_object_is_purgeable(obj_priv)) {
963b4836 5113 i915_gem_object_unbind(obj_priv->obj);
31169714
CW		 5114 if (--nr_to_scan <= 0)
5115 break;
5116 }
5117 }
5118
5119 spin_lock(&shrink_list_lock);
5120 mutex_unlock(&dev->struct_mutex);
5121
963b4836
CW		 5122 would_deadlock = 0;
5123
31169714
CW		 5124 if (nr_to_scan <= 0)
5125 break;
5126 }
5127
5128 /* second pass, evict/count anything still on the inactive list */
5129 list_for_each_entry_safe(dev_priv, next_dev,
5130 &shrink_list, mm.shrink_list) {
5131 struct drm_device *dev = dev_priv->dev;
5132
5133 if (! mutex_trylock(&dev->struct_mutex))
5134 continue;
5135
5136 spin_unlock(&shrink_list_lock);
5137
5138 list_for_each_entry_safe(obj_priv, next_obj,
5139 &dev_priv->mm.inactive_list,
5140 list) {
5141 if (nr_to_scan > 0) {
963b4836 5142 i915_gem_object_unbind(obj_priv->obj);
31169714
CW		 5143 nr_to_scan--;
5144 } else
5145 cnt++;
5146 }
5147
5148 spin_lock(&shrink_list_lock);
5149 mutex_unlock(&dev->struct_mutex);
5150
5151 would_deadlock = 0;
5152 }
5153
5154 spin_unlock(&shrink_list_lock);
5155
5156 if (would_deadlock)
5157 return -1;
5158 else if (cnt > 0)
5159 return (cnt / 100) * sysctl_vfs_cache_pressure;
5160 else
5161 return 0;
5162}
5163
5164static struct shrinker shrinker = {
5165 .shrink = i915_gem_shrink,
5166 .seeks = DEFAULT_SEEKS,
5167};
5168
5169__init void
5170i915_gem_shrinker_init(void)
5171{
5172 register_shrinker(&shrinker);
5173}
5174
5175__exit void
5176i915_gem_shrinker_exit(void)
5177{
5178 unregister_shrinker(&shrinker);
5179}
Linux kernel - Deliverables
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