Commit | Line | Data |
---|---|---|
673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
c13d87ea | 32 | #include "i915_gem_dmabuf.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
5d723d7a | 36 | #include "intel_frontbuffer.h" |
0ccdacf6 | 37 | #include "intel_mocs.h" |
c13d87ea | 38 | #include <linux/reservation.h> |
5949eac4 | 39 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
673a394b | 41 | #include <linux/swap.h> |
79e53945 | 42 | #include <linux/pci.h> |
1286ff73 | 43 | #include <linux/dma-buf.h> |
673a394b | 44 | |
05394f39 | 45 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 46 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 47 | |
c76ce038 CW |
48 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
49 | enum i915_cache_level level) | |
50 | { | |
51 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
52 | } | |
53 | ||
2c22569b CW |
54 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
55 | { | |
b50a5371 AS |
56 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
57 | return false; | |
58 | ||
2c22569b CW |
59 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
60 | return true; | |
61 | ||
62 | return obj->pin_display; | |
63 | } | |
64 | ||
4f1959ee AS |
65 | static int |
66 | insert_mappable_node(struct drm_i915_private *i915, | |
67 | struct drm_mm_node *node, u32 size) | |
68 | { | |
69 | memset(node, 0, sizeof(*node)); | |
70 | return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node, | |
71 | size, 0, 0, 0, | |
72 | i915->ggtt.mappable_end, | |
73 | DRM_MM_SEARCH_DEFAULT, | |
74 | DRM_MM_CREATE_DEFAULT); | |
75 | } | |
76 | ||
77 | static void | |
78 | remove_mappable_node(struct drm_mm_node *node) | |
79 | { | |
80 | drm_mm_remove_node(node); | |
81 | } | |
82 | ||
73aa808f CW |
83 | /* some bookkeeping */ |
84 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
85 | size_t size) | |
86 | { | |
c20e8355 | 87 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
88 | dev_priv->mm.object_count++; |
89 | dev_priv->mm.object_memory += size; | |
c20e8355 | 90 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | } |
92 | ||
93 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count--; |
98 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
21dd3734 | 102 | static int |
33196ded | 103 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 104 | { |
30dbf0c0 CW |
105 | int ret; |
106 | ||
d98c52cf | 107 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
108 | return 0; |
109 | ||
0a6759c6 DV |
110 | /* |
111 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
112 | * userspace. If it takes that long something really bad is going on and | |
113 | * we should simply try to bail out and fail as gracefully as possible. | |
114 | */ | |
1f83fee0 | 115 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 116 | !i915_reset_in_progress(error), |
1f83fee0 | 117 | 10*HZ); |
0a6759c6 DV |
118 | if (ret == 0) { |
119 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
120 | return -EIO; | |
121 | } else if (ret < 0) { | |
30dbf0c0 | 122 | return ret; |
d98c52cf CW |
123 | } else { |
124 | return 0; | |
0a6759c6 | 125 | } |
30dbf0c0 CW |
126 | } |
127 | ||
54cf91dc | 128 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 129 | { |
fac5e23e | 130 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
131 | int ret; |
132 | ||
33196ded | 133 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
134 | if (ret) |
135 | return ret; | |
136 | ||
137 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
138 | if (ret) | |
139 | return ret; | |
140 | ||
76c1dec1 CW |
141 | return 0; |
142 | } | |
30dbf0c0 | 143 | |
5a125c3c EA |
144 | int |
145 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 146 | struct drm_file *file) |
5a125c3c | 147 | { |
72e96d64 | 148 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 149 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 150 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 151 | struct i915_vma *vma; |
6299f992 | 152 | size_t pinned; |
5a125c3c | 153 | |
6299f992 | 154 | pinned = 0; |
73aa808f | 155 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 156 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 157 | if (i915_vma_is_pinned(vma)) |
ca1543be | 158 | pinned += vma->node.size; |
1c7f4bca | 159 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 160 | if (i915_vma_is_pinned(vma)) |
ca1543be | 161 | pinned += vma->node.size; |
73aa808f | 162 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 163 | |
72e96d64 | 164 | args->aper_size = ggtt->base.total; |
0206e353 | 165 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 166 | |
5a125c3c EA |
167 | return 0; |
168 | } | |
169 | ||
6a2c4232 CW |
170 | static int |
171 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 172 | { |
93c76a3d | 173 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 CW |
174 | char *vaddr = obj->phys_handle->vaddr; |
175 | struct sg_table *st; | |
176 | struct scatterlist *sg; | |
177 | int i; | |
00731155 | 178 | |
6a2c4232 CW |
179 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
180 | return -EINVAL; | |
181 | ||
182 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
183 | struct page *page; | |
184 | char *src; | |
185 | ||
186 | page = shmem_read_mapping_page(mapping, i); | |
187 | if (IS_ERR(page)) | |
188 | return PTR_ERR(page); | |
189 | ||
190 | src = kmap_atomic(page); | |
191 | memcpy(vaddr, src, PAGE_SIZE); | |
192 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
193 | kunmap_atomic(src); | |
194 | ||
09cbfeaf | 195 | put_page(page); |
6a2c4232 CW |
196 | vaddr += PAGE_SIZE; |
197 | } | |
198 | ||
c033666a | 199 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
200 | |
201 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
202 | if (st == NULL) | |
203 | return -ENOMEM; | |
204 | ||
205 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
206 | kfree(st); | |
207 | return -ENOMEM; | |
208 | } | |
209 | ||
210 | sg = st->sgl; | |
211 | sg->offset = 0; | |
212 | sg->length = obj->base.size; | |
00731155 | 213 | |
6a2c4232 CW |
214 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
215 | sg_dma_len(sg) = obj->base.size; | |
216 | ||
217 | obj->pages = st; | |
6a2c4232 CW |
218 | return 0; |
219 | } | |
220 | ||
221 | static void | |
222 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
223 | { | |
224 | int ret; | |
225 | ||
226 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 227 | |
6a2c4232 | 228 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 229 | if (WARN_ON(ret)) { |
6a2c4232 CW |
230 | /* In the event of a disaster, abandon all caches and |
231 | * hope for the best. | |
232 | */ | |
6a2c4232 CW |
233 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
234 | } | |
235 | ||
236 | if (obj->madv == I915_MADV_DONTNEED) | |
237 | obj->dirty = 0; | |
238 | ||
239 | if (obj->dirty) { | |
93c76a3d | 240 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 241 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
242 | int i; |
243 | ||
244 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
245 | struct page *page; |
246 | char *dst; | |
247 | ||
248 | page = shmem_read_mapping_page(mapping, i); | |
249 | if (IS_ERR(page)) | |
250 | continue; | |
251 | ||
252 | dst = kmap_atomic(page); | |
253 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
254 | memcpy(dst, vaddr, PAGE_SIZE); | |
255 | kunmap_atomic(dst); | |
256 | ||
257 | set_page_dirty(page); | |
258 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 259 | mark_page_accessed(page); |
09cbfeaf | 260 | put_page(page); |
00731155 CW |
261 | vaddr += PAGE_SIZE; |
262 | } | |
6a2c4232 | 263 | obj->dirty = 0; |
00731155 CW |
264 | } |
265 | ||
6a2c4232 CW |
266 | sg_free_table(obj->pages); |
267 | kfree(obj->pages); | |
6a2c4232 CW |
268 | } |
269 | ||
270 | static void | |
271 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
272 | { | |
273 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
274 | } | |
275 | ||
276 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
277 | .get_pages = i915_gem_object_get_pages_phys, | |
278 | .put_pages = i915_gem_object_put_pages_phys, | |
279 | .release = i915_gem_object_release_phys, | |
280 | }; | |
281 | ||
35a9611c | 282 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
283 | { |
284 | struct i915_vma *vma; | |
285 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
286 | int ret; |
287 | ||
288 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 289 | |
02bef8f9 CW |
290 | /* Closed vma are removed from the obj->vma_list - but they may |
291 | * still have an active binding on the object. To remove those we | |
292 | * must wait for all rendering to complete to the object (as unbinding | |
293 | * must anyway), and retire the requests. | |
aa653a68 | 294 | */ |
02bef8f9 CW |
295 | ret = i915_gem_object_wait_rendering(obj, false); |
296 | if (ret) | |
297 | return ret; | |
298 | ||
299 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
300 | ||
aa653a68 CW |
301 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
302 | struct i915_vma, | |
303 | obj_link))) { | |
304 | list_move_tail(&vma->obj_link, &still_in_list); | |
305 | ret = i915_vma_unbind(vma); | |
306 | if (ret) | |
307 | break; | |
308 | } | |
309 | list_splice(&still_in_list, &obj->vma_list); | |
310 | ||
311 | return ret; | |
312 | } | |
313 | ||
00e60f26 CW |
314 | /** |
315 | * Ensures that all rendering to the object has completed and the object is | |
316 | * safe to unbind from the GTT or access from the CPU. | |
317 | * @obj: i915 gem object | |
318 | * @readonly: waiting for just read access or read-write access | |
319 | */ | |
320 | int | |
321 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
322 | bool readonly) | |
323 | { | |
324 | struct reservation_object *resv; | |
325 | struct i915_gem_active *active; | |
326 | unsigned long active_mask; | |
327 | int idx; | |
328 | ||
329 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
330 | ||
331 | if (!readonly) { | |
332 | active = obj->last_read; | |
333 | active_mask = i915_gem_object_get_active(obj); | |
334 | } else { | |
335 | active_mask = 1; | |
336 | active = &obj->last_write; | |
337 | } | |
338 | ||
339 | for_each_active(active_mask, idx) { | |
340 | int ret; | |
341 | ||
342 | ret = i915_gem_active_wait(&active[idx], | |
343 | &obj->base.dev->struct_mutex); | |
344 | if (ret) | |
345 | return ret; | |
346 | } | |
347 | ||
348 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
349 | if (resv) { | |
350 | long err; | |
351 | ||
352 | err = reservation_object_wait_timeout_rcu(resv, !readonly, true, | |
353 | MAX_SCHEDULE_TIMEOUT); | |
354 | if (err < 0) | |
355 | return err; | |
356 | } | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
b8f9096d CW |
361 | /* A nonblocking variant of the above wait. Must be called prior to |
362 | * acquiring the mutex for the object, as the object state may change | |
363 | * during this call. A reference must be held by the caller for the object. | |
00e60f26 CW |
364 | */ |
365 | static __must_check int | |
b8f9096d CW |
366 | __unsafe_wait_rendering(struct drm_i915_gem_object *obj, |
367 | struct intel_rps_client *rps, | |
368 | bool readonly) | |
00e60f26 | 369 | { |
00e60f26 CW |
370 | struct i915_gem_active *active; |
371 | unsigned long active_mask; | |
b8f9096d | 372 | int idx; |
00e60f26 | 373 | |
b8f9096d | 374 | active_mask = __I915_BO_ACTIVE(obj); |
00e60f26 CW |
375 | if (!active_mask) |
376 | return 0; | |
377 | ||
378 | if (!readonly) { | |
379 | active = obj->last_read; | |
380 | } else { | |
381 | active_mask = 1; | |
382 | active = &obj->last_write; | |
383 | } | |
384 | ||
b8f9096d CW |
385 | for_each_active(active_mask, idx) { |
386 | int ret; | |
00e60f26 | 387 | |
b8f9096d CW |
388 | ret = i915_gem_active_wait_unlocked(&active[idx], |
389 | true, NULL, rps); | |
390 | if (ret) | |
391 | return ret; | |
00e60f26 CW |
392 | } |
393 | ||
b8f9096d | 394 | return 0; |
00e60f26 CW |
395 | } |
396 | ||
397 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
398 | { | |
399 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
400 | ||
401 | return &fpriv->rps; | |
402 | } | |
403 | ||
00731155 CW |
404 | int |
405 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
406 | int align) | |
407 | { | |
408 | drm_dma_handle_t *phys; | |
6a2c4232 | 409 | int ret; |
00731155 CW |
410 | |
411 | if (obj->phys_handle) { | |
412 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
413 | return -EBUSY; | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
418 | if (obj->madv != I915_MADV_WILLNEED) | |
419 | return -EFAULT; | |
420 | ||
421 | if (obj->base.filp == NULL) | |
422 | return -EINVAL; | |
423 | ||
4717ca9e CW |
424 | ret = i915_gem_object_unbind(obj); |
425 | if (ret) | |
426 | return ret; | |
427 | ||
428 | ret = i915_gem_object_put_pages(obj); | |
6a2c4232 CW |
429 | if (ret) |
430 | return ret; | |
431 | ||
00731155 CW |
432 | /* create a new object */ |
433 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
434 | if (!phys) | |
435 | return -ENOMEM; | |
436 | ||
00731155 | 437 | obj->phys_handle = phys; |
6a2c4232 CW |
438 | obj->ops = &i915_gem_phys_ops; |
439 | ||
440 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
441 | } |
442 | ||
443 | static int | |
444 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
445 | struct drm_i915_gem_pwrite *args, | |
446 | struct drm_file *file_priv) | |
447 | { | |
448 | struct drm_device *dev = obj->base.dev; | |
449 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 450 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
063e4e6b | 451 | int ret = 0; |
6a2c4232 CW |
452 | |
453 | /* We manually control the domain here and pretend that it | |
454 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
455 | */ | |
456 | ret = i915_gem_object_wait_rendering(obj, false); | |
457 | if (ret) | |
458 | return ret; | |
00731155 | 459 | |
77a0d1ca | 460 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
461 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
462 | unsigned long unwritten; | |
463 | ||
464 | /* The physical object once assigned is fixed for the lifetime | |
465 | * of the obj, so we can safely drop the lock and continue | |
466 | * to access vaddr. | |
467 | */ | |
468 | mutex_unlock(&dev->struct_mutex); | |
469 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
470 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
471 | if (unwritten) { |
472 | ret = -EFAULT; | |
473 | goto out; | |
474 | } | |
00731155 CW |
475 | } |
476 | ||
6a2c4232 | 477 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 478 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
479 | |
480 | out: | |
de152b62 | 481 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 482 | return ret; |
00731155 CW |
483 | } |
484 | ||
42dcedd4 CW |
485 | void *i915_gem_object_alloc(struct drm_device *dev) |
486 | { | |
fac5e23e | 487 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 488 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
489 | } |
490 | ||
491 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
492 | { | |
fac5e23e | 493 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 494 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
495 | } |
496 | ||
ff72145b DA |
497 | static int |
498 | i915_gem_create(struct drm_file *file, | |
499 | struct drm_device *dev, | |
500 | uint64_t size, | |
501 | uint32_t *handle_p) | |
673a394b | 502 | { |
05394f39 | 503 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
504 | int ret; |
505 | u32 handle; | |
673a394b | 506 | |
ff72145b | 507 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
508 | if (size == 0) |
509 | return -EINVAL; | |
673a394b EA |
510 | |
511 | /* Allocate the new object */ | |
d37cd8a8 | 512 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
513 | if (IS_ERR(obj)) |
514 | return PTR_ERR(obj); | |
673a394b | 515 | |
05394f39 | 516 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 517 | /* drop reference from allocate - handle holds it now */ |
34911fd3 | 518 | i915_gem_object_put_unlocked(obj); |
d861e338 DV |
519 | if (ret) |
520 | return ret; | |
202f2fef | 521 | |
ff72145b | 522 | *handle_p = handle; |
673a394b EA |
523 | return 0; |
524 | } | |
525 | ||
ff72145b DA |
526 | int |
527 | i915_gem_dumb_create(struct drm_file *file, | |
528 | struct drm_device *dev, | |
529 | struct drm_mode_create_dumb *args) | |
530 | { | |
531 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 532 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
533 | args->size = args->pitch * args->height; |
534 | return i915_gem_create(file, dev, | |
da6b51d0 | 535 | args->size, &args->handle); |
ff72145b DA |
536 | } |
537 | ||
ff72145b DA |
538 | /** |
539 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
540 | * @dev: drm device pointer |
541 | * @data: ioctl data blob | |
542 | * @file: drm file pointer | |
ff72145b DA |
543 | */ |
544 | int | |
545 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
546 | struct drm_file *file) | |
547 | { | |
548 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 549 | |
ff72145b | 550 | return i915_gem_create(file, dev, |
da6b51d0 | 551 | args->size, &args->handle); |
ff72145b DA |
552 | } |
553 | ||
8461d226 DV |
554 | static inline int |
555 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
556 | const char *gpu_vaddr, int gpu_offset, | |
557 | int length) | |
558 | { | |
559 | int ret, cpu_offset = 0; | |
560 | ||
561 | while (length > 0) { | |
562 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
563 | int this_length = min(cacheline_end - gpu_offset, length); | |
564 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
565 | ||
566 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
567 | gpu_vaddr + swizzled_gpu_offset, | |
568 | this_length); | |
569 | if (ret) | |
570 | return ret + length; | |
571 | ||
572 | cpu_offset += this_length; | |
573 | gpu_offset += this_length; | |
574 | length -= this_length; | |
575 | } | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
8c59967c | 580 | static inline int |
4f0c7cfb BW |
581 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
582 | const char __user *cpu_vaddr, | |
8c59967c DV |
583 | int length) |
584 | { | |
585 | int ret, cpu_offset = 0; | |
586 | ||
587 | while (length > 0) { | |
588 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
589 | int this_length = min(cacheline_end - gpu_offset, length); | |
590 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
591 | ||
592 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
593 | cpu_vaddr + cpu_offset, | |
594 | this_length); | |
595 | if (ret) | |
596 | return ret + length; | |
597 | ||
598 | cpu_offset += this_length; | |
599 | gpu_offset += this_length; | |
600 | length -= this_length; | |
601 | } | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
4c914c0c BV |
606 | /* |
607 | * Pins the specified object's pages and synchronizes the object with | |
608 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
609 | * flush the object from the CPU cache. | |
610 | */ | |
611 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 612 | unsigned int *needs_clflush) |
4c914c0c BV |
613 | { |
614 | int ret; | |
615 | ||
616 | *needs_clflush = 0; | |
617 | ||
43394c7d CW |
618 | if (!i915_gem_object_has_struct_page(obj)) |
619 | return -ENODEV; | |
4c914c0c | 620 | |
c13d87ea CW |
621 | ret = i915_gem_object_wait_rendering(obj, true); |
622 | if (ret) | |
623 | return ret; | |
624 | ||
9764951e CW |
625 | ret = i915_gem_object_get_pages(obj); |
626 | if (ret) | |
627 | return ret; | |
628 | ||
629 | i915_gem_object_pin_pages(obj); | |
630 | ||
a314d5cb CW |
631 | i915_gem_object_flush_gtt_write_domain(obj); |
632 | ||
43394c7d CW |
633 | /* If we're not in the cpu read domain, set ourself into the gtt |
634 | * read domain and manually flush cachelines (if required). This | |
635 | * optimizes for the case when the gpu will dirty the data | |
636 | * anyway again before the next pread happens. | |
637 | */ | |
638 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
4c914c0c BV |
639 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
640 | obj->cache_level); | |
43394c7d | 641 | |
43394c7d CW |
642 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
643 | ret = i915_gem_object_set_to_cpu_domain(obj, false); | |
9764951e CW |
644 | if (ret) |
645 | goto err_unpin; | |
646 | ||
43394c7d | 647 | *needs_clflush = 0; |
4c914c0c BV |
648 | } |
649 | ||
9764951e | 650 | /* return with the pages pinned */ |
43394c7d | 651 | return 0; |
9764951e CW |
652 | |
653 | err_unpin: | |
654 | i915_gem_object_unpin_pages(obj); | |
655 | return ret; | |
43394c7d CW |
656 | } |
657 | ||
658 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
659 | unsigned int *needs_clflush) | |
660 | { | |
661 | int ret; | |
662 | ||
663 | *needs_clflush = 0; | |
664 | if (!i915_gem_object_has_struct_page(obj)) | |
665 | return -ENODEV; | |
666 | ||
667 | ret = i915_gem_object_wait_rendering(obj, false); | |
668 | if (ret) | |
669 | return ret; | |
670 | ||
9764951e CW |
671 | ret = i915_gem_object_get_pages(obj); |
672 | if (ret) | |
673 | return ret; | |
674 | ||
675 | i915_gem_object_pin_pages(obj); | |
676 | ||
a314d5cb CW |
677 | i915_gem_object_flush_gtt_write_domain(obj); |
678 | ||
43394c7d CW |
679 | /* If we're not in the cpu write domain, set ourself into the |
680 | * gtt write domain and manually flush cachelines (as required). | |
681 | * This optimizes for the case when the gpu will use the data | |
682 | * right away and we therefore have to clflush anyway. | |
683 | */ | |
684 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
685 | *needs_clflush |= cpu_write_needs_clflush(obj) << 1; | |
686 | ||
687 | /* Same trick applies to invalidate partially written cachelines read | |
688 | * before writing. | |
689 | */ | |
690 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
691 | *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev, | |
692 | obj->cache_level); | |
693 | ||
43394c7d CW |
694 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
695 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
9764951e CW |
696 | if (ret) |
697 | goto err_unpin; | |
698 | ||
43394c7d CW |
699 | *needs_clflush = 0; |
700 | } | |
701 | ||
702 | if ((*needs_clflush & CLFLUSH_AFTER) == 0) | |
703 | obj->cache_dirty = true; | |
704 | ||
705 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
706 | obj->dirty = 1; | |
9764951e | 707 | /* return with the pages pinned */ |
43394c7d | 708 | return 0; |
9764951e CW |
709 | |
710 | err_unpin: | |
711 | i915_gem_object_unpin_pages(obj); | |
712 | return ret; | |
4c914c0c BV |
713 | } |
714 | ||
d174bd64 DV |
715 | /* Per-page copy function for the shmem pread fastpath. |
716 | * Flushes invalid cachelines before reading the target if | |
717 | * needs_clflush is set. */ | |
eb01459f | 718 | static int |
d174bd64 DV |
719 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
720 | char __user *user_data, | |
721 | bool page_do_bit17_swizzling, bool needs_clflush) | |
722 | { | |
723 | char *vaddr; | |
724 | int ret; | |
725 | ||
e7e58eb5 | 726 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
727 | return -EINVAL; |
728 | ||
729 | vaddr = kmap_atomic(page); | |
730 | if (needs_clflush) | |
731 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
732 | page_length); | |
733 | ret = __copy_to_user_inatomic(user_data, | |
734 | vaddr + shmem_page_offset, | |
735 | page_length); | |
736 | kunmap_atomic(vaddr); | |
737 | ||
f60d7f0c | 738 | return ret ? -EFAULT : 0; |
d174bd64 DV |
739 | } |
740 | ||
23c18c71 DV |
741 | static void |
742 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
743 | bool swizzled) | |
744 | { | |
e7e58eb5 | 745 | if (unlikely(swizzled)) { |
23c18c71 DV |
746 | unsigned long start = (unsigned long) addr; |
747 | unsigned long end = (unsigned long) addr + length; | |
748 | ||
749 | /* For swizzling simply ensure that we always flush both | |
750 | * channels. Lame, but simple and it works. Swizzled | |
751 | * pwrite/pread is far from a hotpath - current userspace | |
752 | * doesn't use it at all. */ | |
753 | start = round_down(start, 128); | |
754 | end = round_up(end, 128); | |
755 | ||
756 | drm_clflush_virt_range((void *)start, end - start); | |
757 | } else { | |
758 | drm_clflush_virt_range(addr, length); | |
759 | } | |
760 | ||
761 | } | |
762 | ||
d174bd64 DV |
763 | /* Only difference to the fast-path function is that this can handle bit17 |
764 | * and uses non-atomic copy and kmap functions. */ | |
765 | static int | |
766 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
767 | char __user *user_data, | |
768 | bool page_do_bit17_swizzling, bool needs_clflush) | |
769 | { | |
770 | char *vaddr; | |
771 | int ret; | |
772 | ||
773 | vaddr = kmap(page); | |
774 | if (needs_clflush) | |
23c18c71 DV |
775 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
776 | page_length, | |
777 | page_do_bit17_swizzling); | |
d174bd64 DV |
778 | |
779 | if (page_do_bit17_swizzling) | |
780 | ret = __copy_to_user_swizzled(user_data, | |
781 | vaddr, shmem_page_offset, | |
782 | page_length); | |
783 | else | |
784 | ret = __copy_to_user(user_data, | |
785 | vaddr + shmem_page_offset, | |
786 | page_length); | |
787 | kunmap(page); | |
788 | ||
f60d7f0c | 789 | return ret ? - EFAULT : 0; |
d174bd64 DV |
790 | } |
791 | ||
b50a5371 AS |
792 | static inline unsigned long |
793 | slow_user_access(struct io_mapping *mapping, | |
794 | uint64_t page_base, int page_offset, | |
795 | char __user *user_data, | |
796 | unsigned long length, bool pwrite) | |
797 | { | |
798 | void __iomem *ioaddr; | |
799 | void *vaddr; | |
800 | uint64_t unwritten; | |
801 | ||
802 | ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE); | |
803 | /* We can use the cpu mem copy function because this is X86. */ | |
804 | vaddr = (void __force *)ioaddr + page_offset; | |
805 | if (pwrite) | |
806 | unwritten = __copy_from_user(vaddr, user_data, length); | |
807 | else | |
808 | unwritten = __copy_to_user(user_data, vaddr, length); | |
809 | ||
810 | io_mapping_unmap(ioaddr); | |
811 | return unwritten; | |
812 | } | |
813 | ||
814 | static int | |
815 | i915_gem_gtt_pread(struct drm_device *dev, | |
816 | struct drm_i915_gem_object *obj, uint64_t size, | |
817 | uint64_t data_offset, uint64_t data_ptr) | |
818 | { | |
fac5e23e | 819 | struct drm_i915_private *dev_priv = to_i915(dev); |
b50a5371 | 820 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
058d88c4 | 821 | struct i915_vma *vma; |
b50a5371 AS |
822 | struct drm_mm_node node; |
823 | char __user *user_data; | |
824 | uint64_t remain; | |
825 | uint64_t offset; | |
826 | int ret; | |
827 | ||
058d88c4 | 828 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); |
18034584 CW |
829 | if (!IS_ERR(vma)) { |
830 | node.start = i915_ggtt_offset(vma); | |
831 | node.allocated = false; | |
832 | ret = i915_gem_object_put_fence(obj); | |
833 | if (ret) { | |
834 | i915_vma_unpin(vma); | |
835 | vma = ERR_PTR(ret); | |
836 | } | |
837 | } | |
058d88c4 | 838 | if (IS_ERR(vma)) { |
b50a5371 AS |
839 | ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE); |
840 | if (ret) | |
841 | goto out; | |
842 | ||
843 | ret = i915_gem_object_get_pages(obj); | |
844 | if (ret) { | |
845 | remove_mappable_node(&node); | |
846 | goto out; | |
847 | } | |
848 | ||
849 | i915_gem_object_pin_pages(obj); | |
b50a5371 AS |
850 | } |
851 | ||
852 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
853 | if (ret) | |
854 | goto out_unpin; | |
855 | ||
856 | user_data = u64_to_user_ptr(data_ptr); | |
857 | remain = size; | |
858 | offset = data_offset; | |
859 | ||
860 | mutex_unlock(&dev->struct_mutex); | |
861 | if (likely(!i915.prefault_disable)) { | |
862 | ret = fault_in_multipages_writeable(user_data, remain); | |
863 | if (ret) { | |
864 | mutex_lock(&dev->struct_mutex); | |
865 | goto out_unpin; | |
866 | } | |
867 | } | |
868 | ||
869 | while (remain > 0) { | |
870 | /* Operation in this page | |
871 | * | |
872 | * page_base = page offset within aperture | |
873 | * page_offset = offset within page | |
874 | * page_length = bytes to copy for this page | |
875 | */ | |
876 | u32 page_base = node.start; | |
877 | unsigned page_offset = offset_in_page(offset); | |
878 | unsigned page_length = PAGE_SIZE - page_offset; | |
879 | page_length = remain < page_length ? remain : page_length; | |
880 | if (node.allocated) { | |
881 | wmb(); | |
882 | ggtt->base.insert_page(&ggtt->base, | |
883 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
884 | node.start, | |
885 | I915_CACHE_NONE, 0); | |
886 | wmb(); | |
887 | } else { | |
888 | page_base += offset & PAGE_MASK; | |
889 | } | |
890 | /* This is a slow read/write as it tries to read from | |
891 | * and write to user memory which may result into page | |
892 | * faults, and so we cannot perform this under struct_mutex. | |
893 | */ | |
894 | if (slow_user_access(ggtt->mappable, page_base, | |
895 | page_offset, user_data, | |
896 | page_length, false)) { | |
897 | ret = -EFAULT; | |
898 | break; | |
899 | } | |
900 | ||
901 | remain -= page_length; | |
902 | user_data += page_length; | |
903 | offset += page_length; | |
904 | } | |
905 | ||
906 | mutex_lock(&dev->struct_mutex); | |
907 | if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
908 | /* The user has modified the object whilst we tried | |
909 | * reading from it, and we now have no idea what domain | |
910 | * the pages should be in. As we have just been touching | |
911 | * them directly, flush everything back to the GTT | |
912 | * domain. | |
913 | */ | |
914 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
915 | } | |
916 | ||
917 | out_unpin: | |
918 | if (node.allocated) { | |
919 | wmb(); | |
920 | ggtt->base.clear_range(&ggtt->base, | |
921 | node.start, node.size, | |
922 | true); | |
923 | i915_gem_object_unpin_pages(obj); | |
924 | remove_mappable_node(&node); | |
925 | } else { | |
058d88c4 | 926 | i915_vma_unpin(vma); |
b50a5371 AS |
927 | } |
928 | out: | |
929 | return ret; | |
930 | } | |
931 | ||
eb01459f | 932 | static int |
dbf7bff0 DV |
933 | i915_gem_shmem_pread(struct drm_device *dev, |
934 | struct drm_i915_gem_object *obj, | |
935 | struct drm_i915_gem_pread *args, | |
936 | struct drm_file *file) | |
eb01459f | 937 | { |
8461d226 | 938 | char __user *user_data; |
eb01459f | 939 | ssize_t remain; |
8461d226 | 940 | loff_t offset; |
eb2c0c81 | 941 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 942 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 943 | int prefaulted = 0; |
8489731c | 944 | int needs_clflush = 0; |
67d5a50c | 945 | struct sg_page_iter sg_iter; |
eb01459f | 946 | |
4c914c0c | 947 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
948 | if (ret) |
949 | return ret; | |
950 | ||
43394c7d CW |
951 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
952 | user_data = u64_to_user_ptr(args->data_ptr); | |
8461d226 | 953 | offset = args->offset; |
43394c7d | 954 | remain = args->size; |
eb01459f | 955 | |
67d5a50c ID |
956 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
957 | offset >> PAGE_SHIFT) { | |
2db76d7c | 958 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
959 | |
960 | if (remain <= 0) | |
961 | break; | |
962 | ||
eb01459f EA |
963 | /* Operation in this page |
964 | * | |
eb01459f | 965 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
966 | * page_length = bytes to copy for this page |
967 | */ | |
c8cbbb8b | 968 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
969 | page_length = remain; |
970 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
971 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 972 | |
8461d226 DV |
973 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
974 | (page_to_phys(page) & (1 << 17)) != 0; | |
975 | ||
d174bd64 DV |
976 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
977 | user_data, page_do_bit17_swizzling, | |
978 | needs_clflush); | |
979 | if (ret == 0) | |
980 | goto next_page; | |
dbf7bff0 | 981 | |
dbf7bff0 DV |
982 | mutex_unlock(&dev->struct_mutex); |
983 | ||
d330a953 | 984 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 985 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
986 | /* Userspace is tricking us, but we've already clobbered |
987 | * its pages with the prefault and promised to write the | |
988 | * data up to the first fault. Hence ignore any errors | |
989 | * and just continue. */ | |
990 | (void)ret; | |
991 | prefaulted = 1; | |
992 | } | |
eb01459f | 993 | |
d174bd64 DV |
994 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
995 | user_data, page_do_bit17_swizzling, | |
996 | needs_clflush); | |
eb01459f | 997 | |
dbf7bff0 | 998 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 999 | |
f60d7f0c | 1000 | if (ret) |
8461d226 | 1001 | goto out; |
8461d226 | 1002 | |
17793c9a | 1003 | next_page: |
eb01459f | 1004 | remain -= page_length; |
8461d226 | 1005 | user_data += page_length; |
eb01459f EA |
1006 | offset += page_length; |
1007 | } | |
1008 | ||
4f27b75d | 1009 | out: |
43394c7d | 1010 | i915_gem_obj_finish_shmem_access(obj); |
f60d7f0c | 1011 | |
eb01459f EA |
1012 | return ret; |
1013 | } | |
1014 | ||
673a394b EA |
1015 | /** |
1016 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1017 | * @dev: drm device pointer |
1018 | * @data: ioctl data blob | |
1019 | * @file: drm file pointer | |
673a394b EA |
1020 | * |
1021 | * On error, the contents of *data are undefined. | |
1022 | */ | |
1023 | int | |
1024 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1025 | struct drm_file *file) |
673a394b EA |
1026 | { |
1027 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1028 | struct drm_i915_gem_object *obj; |
35b62a89 | 1029 | int ret = 0; |
673a394b | 1030 | |
51311d0a CW |
1031 | if (args->size == 0) |
1032 | return 0; | |
1033 | ||
1034 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1035 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1036 | args->size)) |
1037 | return -EFAULT; | |
1038 | ||
03ac0642 | 1039 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1040 | if (!obj) |
1041 | return -ENOENT; | |
673a394b | 1042 | |
7dcd2499 | 1043 | /* Bounds check source. */ |
05394f39 CW |
1044 | if (args->offset > obj->base.size || |
1045 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1046 | ret = -EINVAL; |
258a5ede | 1047 | goto err; |
ce9d419d CW |
1048 | } |
1049 | ||
db53a302 CW |
1050 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1051 | ||
258a5ede CW |
1052 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), true); |
1053 | if (ret) | |
1054 | goto err; | |
1055 | ||
1056 | ret = i915_mutex_lock_interruptible(dev); | |
1057 | if (ret) | |
1058 | goto err; | |
1059 | ||
dbf7bff0 | 1060 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 1061 | |
b50a5371 | 1062 | /* pread for non shmem backed objects */ |
1dd5b6f2 CW |
1063 | if (ret == -EFAULT || ret == -ENODEV) { |
1064 | intel_runtime_pm_get(to_i915(dev)); | |
b50a5371 AS |
1065 | ret = i915_gem_gtt_pread(dev, obj, args->size, |
1066 | args->offset, args->data_ptr); | |
1dd5b6f2 CW |
1067 | intel_runtime_pm_put(to_i915(dev)); |
1068 | } | |
b50a5371 | 1069 | |
f8c417cd | 1070 | i915_gem_object_put(obj); |
4f27b75d | 1071 | mutex_unlock(&dev->struct_mutex); |
258a5ede CW |
1072 | |
1073 | return ret; | |
1074 | ||
1075 | err: | |
1076 | i915_gem_object_put_unlocked(obj); | |
eb01459f | 1077 | return ret; |
673a394b EA |
1078 | } |
1079 | ||
0839ccb8 KP |
1080 | /* This is the fast write path which cannot handle |
1081 | * page faults in the source data | |
9b7530cc | 1082 | */ |
0839ccb8 KP |
1083 | |
1084 | static inline int | |
1085 | fast_user_write(struct io_mapping *mapping, | |
1086 | loff_t page_base, int page_offset, | |
1087 | char __user *user_data, | |
1088 | int length) | |
9b7530cc | 1089 | { |
4f0c7cfb BW |
1090 | void __iomem *vaddr_atomic; |
1091 | void *vaddr; | |
0839ccb8 | 1092 | unsigned long unwritten; |
9b7530cc | 1093 | |
3e4d3af5 | 1094 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
1095 | /* We can use the cpu mem copy function because this is X86. */ |
1096 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
1097 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 1098 | user_data, length); |
3e4d3af5 | 1099 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 1100 | return unwritten; |
0839ccb8 KP |
1101 | } |
1102 | ||
3de09aa3 EA |
1103 | /** |
1104 | * This is the fast pwrite path, where we copy the data directly from the | |
1105 | * user into the GTT, uncached. | |
62f90b38 | 1106 | * @i915: i915 device private data |
14bb2c11 TU |
1107 | * @obj: i915 gem object |
1108 | * @args: pwrite arguments structure | |
1109 | * @file: drm file pointer | |
3de09aa3 | 1110 | */ |
673a394b | 1111 | static int |
4f1959ee | 1112 | i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915, |
05394f39 | 1113 | struct drm_i915_gem_object *obj, |
3de09aa3 | 1114 | struct drm_i915_gem_pwrite *args, |
05394f39 | 1115 | struct drm_file *file) |
673a394b | 1116 | { |
4f1959ee | 1117 | struct i915_ggtt *ggtt = &i915->ggtt; |
b50a5371 | 1118 | struct drm_device *dev = obj->base.dev; |
058d88c4 | 1119 | struct i915_vma *vma; |
4f1959ee AS |
1120 | struct drm_mm_node node; |
1121 | uint64_t remain, offset; | |
673a394b | 1122 | char __user *user_data; |
4f1959ee | 1123 | int ret; |
b50a5371 AS |
1124 | bool hit_slow_path = false; |
1125 | ||
3e510a8e | 1126 | if (i915_gem_object_is_tiled(obj)) |
b50a5371 | 1127 | return -EFAULT; |
935aaa69 | 1128 | |
058d88c4 | 1129 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1130 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1131 | if (!IS_ERR(vma)) { |
1132 | node.start = i915_ggtt_offset(vma); | |
1133 | node.allocated = false; | |
1134 | ret = i915_gem_object_put_fence(obj); | |
1135 | if (ret) { | |
1136 | i915_vma_unpin(vma); | |
1137 | vma = ERR_PTR(ret); | |
1138 | } | |
1139 | } | |
058d88c4 | 1140 | if (IS_ERR(vma)) { |
4f1959ee AS |
1141 | ret = insert_mappable_node(i915, &node, PAGE_SIZE); |
1142 | if (ret) | |
1143 | goto out; | |
1144 | ||
1145 | ret = i915_gem_object_get_pages(obj); | |
1146 | if (ret) { | |
1147 | remove_mappable_node(&node); | |
1148 | goto out; | |
1149 | } | |
1150 | ||
1151 | i915_gem_object_pin_pages(obj); | |
4f1959ee | 1152 | } |
935aaa69 DV |
1153 | |
1154 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1155 | if (ret) | |
1156 | goto out_unpin; | |
1157 | ||
b19482d7 | 1158 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
4f1959ee | 1159 | obj->dirty = true; |
063e4e6b | 1160 | |
4f1959ee AS |
1161 | user_data = u64_to_user_ptr(args->data_ptr); |
1162 | offset = args->offset; | |
1163 | remain = args->size; | |
1164 | while (remain) { | |
673a394b EA |
1165 | /* Operation in this page |
1166 | * | |
0839ccb8 KP |
1167 | * page_base = page offset within aperture |
1168 | * page_offset = offset within page | |
1169 | * page_length = bytes to copy for this page | |
673a394b | 1170 | */ |
4f1959ee AS |
1171 | u32 page_base = node.start; |
1172 | unsigned page_offset = offset_in_page(offset); | |
1173 | unsigned page_length = PAGE_SIZE - page_offset; | |
1174 | page_length = remain < page_length ? remain : page_length; | |
1175 | if (node.allocated) { | |
1176 | wmb(); /* flush the write before we modify the GGTT */ | |
1177 | ggtt->base.insert_page(&ggtt->base, | |
1178 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1179 | node.start, I915_CACHE_NONE, 0); | |
1180 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1181 | } else { | |
1182 | page_base += offset & PAGE_MASK; | |
1183 | } | |
0839ccb8 | 1184 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1185 | * source page isn't available. Return the error and we'll |
1186 | * retry in the slow path. | |
b50a5371 AS |
1187 | * If the object is non-shmem backed, we retry again with the |
1188 | * path that handles page fault. | |
0839ccb8 | 1189 | */ |
72e96d64 | 1190 | if (fast_user_write(ggtt->mappable, page_base, |
935aaa69 | 1191 | page_offset, user_data, page_length)) { |
b50a5371 AS |
1192 | hit_slow_path = true; |
1193 | mutex_unlock(&dev->struct_mutex); | |
1194 | if (slow_user_access(ggtt->mappable, | |
1195 | page_base, | |
1196 | page_offset, user_data, | |
1197 | page_length, true)) { | |
1198 | ret = -EFAULT; | |
1199 | mutex_lock(&dev->struct_mutex); | |
1200 | goto out_flush; | |
1201 | } | |
1202 | ||
1203 | mutex_lock(&dev->struct_mutex); | |
935aaa69 | 1204 | } |
673a394b | 1205 | |
0839ccb8 KP |
1206 | remain -= page_length; |
1207 | user_data += page_length; | |
1208 | offset += page_length; | |
673a394b | 1209 | } |
673a394b | 1210 | |
063e4e6b | 1211 | out_flush: |
b50a5371 AS |
1212 | if (hit_slow_path) { |
1213 | if (ret == 0 && | |
1214 | (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
1215 | /* The user has modified the object whilst we tried | |
1216 | * reading from it, and we now have no idea what domain | |
1217 | * the pages should be in. As we have just been touching | |
1218 | * them directly, flush everything back to the GTT | |
1219 | * domain. | |
1220 | */ | |
1221 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1222 | } | |
1223 | } | |
1224 | ||
b19482d7 | 1225 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
935aaa69 | 1226 | out_unpin: |
4f1959ee AS |
1227 | if (node.allocated) { |
1228 | wmb(); | |
1229 | ggtt->base.clear_range(&ggtt->base, | |
1230 | node.start, node.size, | |
1231 | true); | |
1232 | i915_gem_object_unpin_pages(obj); | |
1233 | remove_mappable_node(&node); | |
1234 | } else { | |
058d88c4 | 1235 | i915_vma_unpin(vma); |
4f1959ee | 1236 | } |
935aaa69 | 1237 | out: |
3de09aa3 | 1238 | return ret; |
673a394b EA |
1239 | } |
1240 | ||
d174bd64 DV |
1241 | /* Per-page copy function for the shmem pwrite fastpath. |
1242 | * Flushes invalid cachelines before writing to the target if | |
1243 | * needs_clflush_before is set and flushes out any written cachelines after | |
1244 | * writing if needs_clflush is set. */ | |
3043c60c | 1245 | static int |
d174bd64 DV |
1246 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
1247 | char __user *user_data, | |
1248 | bool page_do_bit17_swizzling, | |
1249 | bool needs_clflush_before, | |
1250 | bool needs_clflush_after) | |
673a394b | 1251 | { |
d174bd64 | 1252 | char *vaddr; |
673a394b | 1253 | int ret; |
3de09aa3 | 1254 | |
e7e58eb5 | 1255 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 1256 | return -EINVAL; |
3de09aa3 | 1257 | |
d174bd64 DV |
1258 | vaddr = kmap_atomic(page); |
1259 | if (needs_clflush_before) | |
1260 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1261 | page_length); | |
c2831a94 CW |
1262 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
1263 | user_data, page_length); | |
d174bd64 DV |
1264 | if (needs_clflush_after) |
1265 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1266 | page_length); | |
1267 | kunmap_atomic(vaddr); | |
3de09aa3 | 1268 | |
755d2218 | 1269 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
1270 | } |
1271 | ||
d174bd64 DV |
1272 | /* Only difference to the fast-path function is that this can handle bit17 |
1273 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 1274 | static int |
d174bd64 DV |
1275 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
1276 | char __user *user_data, | |
1277 | bool page_do_bit17_swizzling, | |
1278 | bool needs_clflush_before, | |
1279 | bool needs_clflush_after) | |
673a394b | 1280 | { |
d174bd64 DV |
1281 | char *vaddr; |
1282 | int ret; | |
e5281ccd | 1283 | |
d174bd64 | 1284 | vaddr = kmap(page); |
e7e58eb5 | 1285 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
1286 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1287 | page_length, | |
1288 | page_do_bit17_swizzling); | |
d174bd64 DV |
1289 | if (page_do_bit17_swizzling) |
1290 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
1291 | user_data, |
1292 | page_length); | |
d174bd64 DV |
1293 | else |
1294 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
1295 | user_data, | |
1296 | page_length); | |
1297 | if (needs_clflush_after) | |
23c18c71 DV |
1298 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1299 | page_length, | |
1300 | page_do_bit17_swizzling); | |
d174bd64 | 1301 | kunmap(page); |
40123c1f | 1302 | |
755d2218 | 1303 | return ret ? -EFAULT : 0; |
40123c1f EA |
1304 | } |
1305 | ||
40123c1f | 1306 | static int |
e244a443 DV |
1307 | i915_gem_shmem_pwrite(struct drm_device *dev, |
1308 | struct drm_i915_gem_object *obj, | |
1309 | struct drm_i915_gem_pwrite *args, | |
1310 | struct drm_file *file) | |
40123c1f | 1311 | { |
40123c1f | 1312 | ssize_t remain; |
8c59967c DV |
1313 | loff_t offset; |
1314 | char __user *user_data; | |
eb2c0c81 | 1315 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 1316 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 1317 | int hit_slowpath = 0; |
43394c7d | 1318 | unsigned int needs_clflush; |
67d5a50c | 1319 | struct sg_page_iter sg_iter; |
40123c1f | 1320 | |
43394c7d | 1321 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
755d2218 CW |
1322 | if (ret) |
1323 | return ret; | |
1324 | ||
43394c7d CW |
1325 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
1326 | user_data = u64_to_user_ptr(args->data_ptr); | |
673a394b | 1327 | offset = args->offset; |
43394c7d | 1328 | remain = args->size; |
673a394b | 1329 | |
67d5a50c ID |
1330 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
1331 | offset >> PAGE_SHIFT) { | |
2db76d7c | 1332 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 1333 | int partial_cacheline_write; |
e5281ccd | 1334 | |
9da3da66 CW |
1335 | if (remain <= 0) |
1336 | break; | |
1337 | ||
40123c1f EA |
1338 | /* Operation in this page |
1339 | * | |
40123c1f | 1340 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
1341 | * page_length = bytes to copy for this page |
1342 | */ | |
c8cbbb8b | 1343 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
1344 | |
1345 | page_length = remain; | |
1346 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1347 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 1348 | |
58642885 DV |
1349 | /* If we don't overwrite a cacheline completely we need to be |
1350 | * careful to have up-to-date data by first clflushing. Don't | |
1351 | * overcomplicate things and flush the entire patch. */ | |
43394c7d | 1352 | partial_cacheline_write = needs_clflush & CLFLUSH_BEFORE && |
58642885 DV |
1353 | ((shmem_page_offset | page_length) |
1354 | & (boot_cpu_data.x86_clflush_size - 1)); | |
1355 | ||
8c59967c DV |
1356 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
1357 | (page_to_phys(page) & (1 << 17)) != 0; | |
1358 | ||
d174bd64 DV |
1359 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
1360 | user_data, page_do_bit17_swizzling, | |
1361 | partial_cacheline_write, | |
43394c7d | 1362 | needs_clflush & CLFLUSH_AFTER); |
d174bd64 DV |
1363 | if (ret == 0) |
1364 | goto next_page; | |
e244a443 DV |
1365 | |
1366 | hit_slowpath = 1; | |
e244a443 | 1367 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1368 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1369 | user_data, page_do_bit17_swizzling, | |
1370 | partial_cacheline_write, | |
43394c7d | 1371 | needs_clflush & CLFLUSH_AFTER); |
40123c1f | 1372 | |
e244a443 | 1373 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1374 | |
755d2218 | 1375 | if (ret) |
8c59967c | 1376 | goto out; |
8c59967c | 1377 | |
17793c9a | 1378 | next_page: |
40123c1f | 1379 | remain -= page_length; |
8c59967c | 1380 | user_data += page_length; |
40123c1f | 1381 | offset += page_length; |
673a394b EA |
1382 | } |
1383 | ||
fbd5a26d | 1384 | out: |
43394c7d | 1385 | i915_gem_obj_finish_shmem_access(obj); |
755d2218 | 1386 | |
e244a443 | 1387 | if (hit_slowpath) { |
8dcf015e DV |
1388 | /* |
1389 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1390 | * cachelines in-line while writing and the object moved | |
1391 | * out of the cpu write domain while we've dropped the lock. | |
1392 | */ | |
43394c7d | 1393 | if (!(needs_clflush & CLFLUSH_AFTER) && |
8dcf015e | 1394 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
000433b6 | 1395 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
43394c7d | 1396 | needs_clflush |= CLFLUSH_AFTER; |
e244a443 | 1397 | } |
8c59967c | 1398 | } |
673a394b | 1399 | |
43394c7d | 1400 | if (needs_clflush & CLFLUSH_AFTER) |
c033666a | 1401 | i915_gem_chipset_flush(to_i915(dev)); |
58642885 | 1402 | |
de152b62 | 1403 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1404 | return ret; |
673a394b EA |
1405 | } |
1406 | ||
1407 | /** | |
1408 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1409 | * @dev: drm device |
1410 | * @data: ioctl data blob | |
1411 | * @file: drm file | |
673a394b EA |
1412 | * |
1413 | * On error, the contents of the buffer that were to be modified are undefined. | |
1414 | */ | |
1415 | int | |
1416 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1417 | struct drm_file *file) |
673a394b | 1418 | { |
fac5e23e | 1419 | struct drm_i915_private *dev_priv = to_i915(dev); |
673a394b | 1420 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1421 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1422 | int ret; |
1423 | ||
1424 | if (args->size == 0) | |
1425 | return 0; | |
1426 | ||
1427 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1428 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1429 | args->size)) |
1430 | return -EFAULT; | |
1431 | ||
d330a953 | 1432 | if (likely(!i915.prefault_disable)) { |
3ed605bc | 1433 | ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr), |
0b74b508 XZ |
1434 | args->size); |
1435 | if (ret) | |
1436 | return -EFAULT; | |
1437 | } | |
673a394b | 1438 | |
03ac0642 | 1439 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1440 | if (!obj) |
1441 | return -ENOENT; | |
673a394b | 1442 | |
7dcd2499 | 1443 | /* Bounds check destination. */ |
05394f39 CW |
1444 | if (args->offset > obj->base.size || |
1445 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1446 | ret = -EINVAL; |
258a5ede | 1447 | goto err; |
ce9d419d CW |
1448 | } |
1449 | ||
db53a302 CW |
1450 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1451 | ||
258a5ede CW |
1452 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), false); |
1453 | if (ret) | |
1454 | goto err; | |
1455 | ||
1456 | intel_runtime_pm_get(dev_priv); | |
1457 | ||
1458 | ret = i915_mutex_lock_interruptible(dev); | |
1459 | if (ret) | |
1460 | goto err_rpm; | |
1461 | ||
935aaa69 | 1462 | ret = -EFAULT; |
673a394b EA |
1463 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1464 | * it would end up going through the fenced access, and we'll get | |
1465 | * different detiling behavior between reading and writing. | |
1466 | * pread/pwrite currently are reading and writing from the CPU | |
1467 | * perspective, requiring manual detiling by the client. | |
1468 | */ | |
6eae0059 CW |
1469 | if (!i915_gem_object_has_struct_page(obj) || |
1470 | cpu_write_needs_clflush(obj)) { | |
4f1959ee | 1471 | ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file); |
935aaa69 DV |
1472 | /* Note that the gtt paths might fail with non-page-backed user |
1473 | * pointers (e.g. gtt mappings when moving data between | |
1474 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1475 | } |
673a394b | 1476 | |
d1054ee4 | 1477 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1478 | if (obj->phys_handle) |
1479 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1480 | else |
43394c7d | 1481 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
6a2c4232 | 1482 | } |
5c0480f2 | 1483 | |
f8c417cd | 1484 | i915_gem_object_put(obj); |
fbd5a26d | 1485 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1486 | intel_runtime_pm_put(dev_priv); |
1487 | ||
673a394b | 1488 | return ret; |
258a5ede CW |
1489 | |
1490 | err_rpm: | |
1491 | intel_runtime_pm_put(dev_priv); | |
1492 | err: | |
1493 | i915_gem_object_put_unlocked(obj); | |
1494 | return ret; | |
673a394b EA |
1495 | } |
1496 | ||
d243ad82 | 1497 | static inline enum fb_op_origin |
aeecc969 CW |
1498 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) |
1499 | { | |
1500 | return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ? | |
1501 | ORIGIN_GTT : ORIGIN_CPU; | |
1502 | } | |
1503 | ||
673a394b | 1504 | /** |
2ef7eeaa EA |
1505 | * Called when user space prepares to use an object with the CPU, either |
1506 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1507 | * @dev: drm device |
1508 | * @data: ioctl data blob | |
1509 | * @file: drm file | |
673a394b EA |
1510 | */ |
1511 | int | |
1512 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1513 | struct drm_file *file) |
673a394b EA |
1514 | { |
1515 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1516 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1517 | uint32_t read_domains = args->read_domains; |
1518 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1519 | int ret; |
1520 | ||
2ef7eeaa | 1521 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1522 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1523 | return -EINVAL; |
1524 | ||
1525 | /* Having something in the write domain implies it's in the read | |
1526 | * domain, and only that read domain. Enforce that in the request. | |
1527 | */ | |
1528 | if (write_domain != 0 && read_domains != write_domain) | |
1529 | return -EINVAL; | |
1530 | ||
03ac0642 | 1531 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1532 | if (!obj) |
1533 | return -ENOENT; | |
673a394b | 1534 | |
3236f57a CW |
1535 | /* Try to flush the object off the GPU without holding the lock. |
1536 | * We will repeat the flush holding the lock in the normal manner | |
1537 | * to catch cases where we are gazumped. | |
1538 | */ | |
b8f9096d CW |
1539 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), !write_domain); |
1540 | if (ret) | |
1541 | goto err; | |
1542 | ||
1543 | ret = i915_mutex_lock_interruptible(dev); | |
3236f57a | 1544 | if (ret) |
b8f9096d | 1545 | goto err; |
3236f57a | 1546 | |
43566ded | 1547 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1548 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1549 | else |
e47c68e9 | 1550 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1551 | |
031b698a | 1552 | if (write_domain != 0) |
aeecc969 | 1553 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); |
031b698a | 1554 | |
f8c417cd | 1555 | i915_gem_object_put(obj); |
673a394b EA |
1556 | mutex_unlock(&dev->struct_mutex); |
1557 | return ret; | |
b8f9096d CW |
1558 | |
1559 | err: | |
1560 | i915_gem_object_put_unlocked(obj); | |
1561 | return ret; | |
673a394b EA |
1562 | } |
1563 | ||
1564 | /** | |
1565 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1566 | * @dev: drm device |
1567 | * @data: ioctl data blob | |
1568 | * @file: drm file | |
673a394b EA |
1569 | */ |
1570 | int | |
1571 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1572 | struct drm_file *file) |
673a394b EA |
1573 | { |
1574 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1575 | struct drm_i915_gem_object *obj; |
c21724cc | 1576 | int err = 0; |
1d7cfea1 | 1577 | |
03ac0642 | 1578 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1579 | if (!obj) |
1580 | return -ENOENT; | |
673a394b | 1581 | |
673a394b | 1582 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1583 | if (READ_ONCE(obj->pin_display)) { |
1584 | err = i915_mutex_lock_interruptible(dev); | |
1585 | if (!err) { | |
1586 | i915_gem_object_flush_cpu_write_domain(obj); | |
1587 | mutex_unlock(&dev->struct_mutex); | |
1588 | } | |
1589 | } | |
e47c68e9 | 1590 | |
c21724cc CW |
1591 | i915_gem_object_put_unlocked(obj); |
1592 | return err; | |
673a394b EA |
1593 | } |
1594 | ||
1595 | /** | |
14bb2c11 TU |
1596 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1597 | * it is mapped to. | |
1598 | * @dev: drm device | |
1599 | * @data: ioctl data blob | |
1600 | * @file: drm file | |
673a394b EA |
1601 | * |
1602 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1603 | * imply a ref on the object itself. | |
34367381 DV |
1604 | * |
1605 | * IMPORTANT: | |
1606 | * | |
1607 | * DRM driver writers who look a this function as an example for how to do GEM | |
1608 | * mmap support, please don't implement mmap support like here. The modern way | |
1609 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1610 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1611 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1612 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1613 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1614 | */ |
1615 | int | |
1616 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1617 | struct drm_file *file) |
673a394b EA |
1618 | { |
1619 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1620 | struct drm_i915_gem_object *obj; |
673a394b EA |
1621 | unsigned long addr; |
1622 | ||
1816f923 AG |
1623 | if (args->flags & ~(I915_MMAP_WC)) |
1624 | return -EINVAL; | |
1625 | ||
568a58e5 | 1626 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1627 | return -ENODEV; |
1628 | ||
03ac0642 CW |
1629 | obj = i915_gem_object_lookup(file, args->handle); |
1630 | if (!obj) | |
bf79cb91 | 1631 | return -ENOENT; |
673a394b | 1632 | |
1286ff73 DV |
1633 | /* prime objects have no backing filp to GEM mmap |
1634 | * pages from. | |
1635 | */ | |
03ac0642 | 1636 | if (!obj->base.filp) { |
34911fd3 | 1637 | i915_gem_object_put_unlocked(obj); |
1286ff73 DV |
1638 | return -EINVAL; |
1639 | } | |
1640 | ||
03ac0642 | 1641 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1642 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1643 | args->offset); | |
1816f923 AG |
1644 | if (args->flags & I915_MMAP_WC) { |
1645 | struct mm_struct *mm = current->mm; | |
1646 | struct vm_area_struct *vma; | |
1647 | ||
80a89a5e | 1648 | if (down_write_killable(&mm->mmap_sem)) { |
34911fd3 | 1649 | i915_gem_object_put_unlocked(obj); |
80a89a5e MH |
1650 | return -EINTR; |
1651 | } | |
1816f923 AG |
1652 | vma = find_vma(mm, addr); |
1653 | if (vma) | |
1654 | vma->vm_page_prot = | |
1655 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1656 | else | |
1657 | addr = -ENOMEM; | |
1658 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1659 | |
1660 | /* This may race, but that's ok, it only gets set */ | |
03ac0642 | 1661 | WRITE_ONCE(obj->has_wc_mmap, true); |
1816f923 | 1662 | } |
34911fd3 | 1663 | i915_gem_object_put_unlocked(obj); |
673a394b EA |
1664 | if (IS_ERR((void *)addr)) |
1665 | return addr; | |
1666 | ||
1667 | args->addr_ptr = (uint64_t) addr; | |
1668 | ||
1669 | return 0; | |
1670 | } | |
1671 | ||
de151cf6 JB |
1672 | /** |
1673 | * i915_gem_fault - fault a page into the GTT | |
058d88c4 | 1674 | * @area: CPU VMA in question |
d9072a3e | 1675 | * @vmf: fault info |
de151cf6 JB |
1676 | * |
1677 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1678 | * from userspace. The fault handler takes care of binding the object to | |
1679 | * the GTT (if needed), allocating and programming a fence register (again, | |
1680 | * only if needed based on whether the old reg is still valid or the object | |
1681 | * is tiled) and inserting a new PTE into the faulting process. | |
1682 | * | |
1683 | * Note that the faulting process may involve evicting existing objects | |
1684 | * from the GTT and/or fence registers to make room. So performance may | |
1685 | * suffer if the GTT working set is large or there are few fence registers | |
1686 | * left. | |
1687 | */ | |
058d88c4 | 1688 | int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) |
de151cf6 | 1689 | { |
058d88c4 | 1690 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1691 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1692 | struct drm_i915_private *dev_priv = to_i915(dev); |
1693 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
c5ad54cf | 1694 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
b8f9096d | 1695 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1696 | struct i915_vma *vma; |
de151cf6 JB |
1697 | pgoff_t page_offset; |
1698 | unsigned long pfn; | |
b8f9096d | 1699 | int ret; |
f65c9168 | 1700 | |
de151cf6 | 1701 | /* We don't use vmf->pgoff since that has the fake offset */ |
058d88c4 | 1702 | page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >> |
de151cf6 JB |
1703 | PAGE_SHIFT; |
1704 | ||
db53a302 CW |
1705 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1706 | ||
6e4930f6 | 1707 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1708 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1709 | * repeat the flush holding the lock in the normal manner to catch cases |
1710 | * where we are gazumped. | |
1711 | */ | |
b8f9096d | 1712 | ret = __unsafe_wait_rendering(obj, NULL, !write); |
6e4930f6 | 1713 | if (ret) |
b8f9096d CW |
1714 | goto err; |
1715 | ||
1716 | intel_runtime_pm_get(dev_priv); | |
1717 | ||
1718 | ret = i915_mutex_lock_interruptible(dev); | |
1719 | if (ret) | |
1720 | goto err_rpm; | |
6e4930f6 | 1721 | |
eb119bd6 CW |
1722 | /* Access to snoopable pages through the GTT is incoherent. */ |
1723 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1724 | ret = -EFAULT; |
b8f9096d | 1725 | goto err_unlock; |
eb119bd6 CW |
1726 | } |
1727 | ||
c5ad54cf | 1728 | /* Use a partial view if the object is bigger than the aperture. */ |
72e96d64 | 1729 | if (obj->base.size >= ggtt->mappable_end && |
3e510a8e | 1730 | !i915_gem_object_is_tiled(obj)) { |
c5ad54cf | 1731 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1732 | |
c5ad54cf JL |
1733 | memset(&view, 0, sizeof(view)); |
1734 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1735 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1736 | view.params.partial.size = | |
1737 | min_t(unsigned int, | |
1738 | chunk_size, | |
058d88c4 | 1739 | (area->vm_end - area->vm_start) / PAGE_SIZE - |
c5ad54cf JL |
1740 | view.params.partial.offset); |
1741 | } | |
1742 | ||
1743 | /* Now pin it into the GTT if needed */ | |
058d88c4 CW |
1744 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1745 | if (IS_ERR(vma)) { | |
1746 | ret = PTR_ERR(vma); | |
b8f9096d | 1747 | goto err_unlock; |
058d88c4 | 1748 | } |
4a684a41 | 1749 | |
c9839303 CW |
1750 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1751 | if (ret) | |
b8f9096d | 1752 | goto err_unpin; |
74898d7e | 1753 | |
06d98131 | 1754 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1755 | if (ret) |
b8f9096d | 1756 | goto err_unpin; |
7d1c4804 | 1757 | |
b90b91d8 | 1758 | /* Finally, remap it using the new GTT offset */ |
bde13ebd | 1759 | pfn = ggtt->mappable_base + i915_ggtt_offset(vma); |
f343c5f6 | 1760 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1761 | |
c5ad54cf JL |
1762 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1763 | /* Overriding existing pages in partial view does not cause | |
1764 | * us any trouble as TLBs are still valid because the fault | |
1765 | * is due to userspace losing part of the mapping or never | |
1766 | * having accessed it before (at this partials' range). | |
1767 | */ | |
058d88c4 | 1768 | unsigned long base = area->vm_start + |
c5ad54cf JL |
1769 | (view.params.partial.offset << PAGE_SHIFT); |
1770 | unsigned int i; | |
b90b91d8 | 1771 | |
c5ad54cf | 1772 | for (i = 0; i < view.params.partial.size; i++) { |
058d88c4 CW |
1773 | ret = vm_insert_pfn(area, |
1774 | base + i * PAGE_SIZE, | |
1775 | pfn + i); | |
b90b91d8 CW |
1776 | if (ret) |
1777 | break; | |
1778 | } | |
1779 | ||
1780 | obj->fault_mappable = true; | |
c5ad54cf JL |
1781 | } else { |
1782 | if (!obj->fault_mappable) { | |
058d88c4 CW |
1783 | unsigned long size = |
1784 | min_t(unsigned long, | |
1785 | area->vm_end - area->vm_start, | |
1786 | obj->base.size) >> PAGE_SHIFT; | |
1787 | unsigned long base = area->vm_start; | |
c5ad54cf JL |
1788 | int i; |
1789 | ||
058d88c4 CW |
1790 | for (i = 0; i < size; i++) { |
1791 | ret = vm_insert_pfn(area, | |
1792 | base + i * PAGE_SIZE, | |
c5ad54cf JL |
1793 | pfn + i); |
1794 | if (ret) | |
1795 | break; | |
1796 | } | |
1797 | ||
1798 | obj->fault_mappable = true; | |
1799 | } else | |
058d88c4 | 1800 | ret = vm_insert_pfn(area, |
c5ad54cf JL |
1801 | (unsigned long)vmf->virtual_address, |
1802 | pfn + page_offset); | |
1803 | } | |
b8f9096d | 1804 | err_unpin: |
058d88c4 | 1805 | __i915_vma_unpin(vma); |
b8f9096d | 1806 | err_unlock: |
de151cf6 | 1807 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1808 | err_rpm: |
1809 | intel_runtime_pm_put(dev_priv); | |
1810 | err: | |
de151cf6 | 1811 | switch (ret) { |
d9bc7e9f | 1812 | case -EIO: |
2232f031 DV |
1813 | /* |
1814 | * We eat errors when the gpu is terminally wedged to avoid | |
1815 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1816 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1817 | * and so needs to be reported. | |
1818 | */ | |
1819 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1820 | ret = VM_FAULT_SIGBUS; |
1821 | break; | |
1822 | } | |
045e769a | 1823 | case -EAGAIN: |
571c608d DV |
1824 | /* |
1825 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1826 | * handler to reset everything when re-faulting in | |
1827 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1828 | */ |
c715089f CW |
1829 | case 0: |
1830 | case -ERESTARTSYS: | |
bed636ab | 1831 | case -EINTR: |
e79e0fe3 DR |
1832 | case -EBUSY: |
1833 | /* | |
1834 | * EBUSY is ok: this just means that another thread | |
1835 | * already did the job. | |
1836 | */ | |
f65c9168 PZ |
1837 | ret = VM_FAULT_NOPAGE; |
1838 | break; | |
de151cf6 | 1839 | case -ENOMEM: |
f65c9168 PZ |
1840 | ret = VM_FAULT_OOM; |
1841 | break; | |
a7c2e1aa | 1842 | case -ENOSPC: |
45d67817 | 1843 | case -EFAULT: |
f65c9168 PZ |
1844 | ret = VM_FAULT_SIGBUS; |
1845 | break; | |
de151cf6 | 1846 | default: |
a7c2e1aa | 1847 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1848 | ret = VM_FAULT_SIGBUS; |
1849 | break; | |
de151cf6 | 1850 | } |
f65c9168 | 1851 | return ret; |
de151cf6 JB |
1852 | } |
1853 | ||
901782b2 CW |
1854 | /** |
1855 | * i915_gem_release_mmap - remove physical page mappings | |
1856 | * @obj: obj in question | |
1857 | * | |
af901ca1 | 1858 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1859 | * relinquish ownership of the pages back to the system. |
1860 | * | |
1861 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1862 | * object through the GTT and then lose the fence register due to | |
1863 | * resource pressure. Similarly if the object has been moved out of the | |
1864 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1865 | * mapping will then trigger a page fault on the next user access, allowing | |
1866 | * fixup by i915_gem_fault(). | |
1867 | */ | |
d05ca301 | 1868 | void |
05394f39 | 1869 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1870 | { |
349f2ccf CW |
1871 | /* Serialisation between user GTT access and our code depends upon |
1872 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1873 | * pagefault then has to wait until we release the mutex. | |
1874 | */ | |
1875 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
1876 | ||
6299f992 CW |
1877 | if (!obj->fault_mappable) |
1878 | return; | |
901782b2 | 1879 | |
6796cb16 DH |
1880 | drm_vma_node_unmap(&obj->base.vma_node, |
1881 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1882 | |
1883 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1884 | * memory transactions from userspace before we return. The TLB | |
1885 | * flushing implied above by changing the PTE above *should* be | |
1886 | * sufficient, an extra barrier here just provides us with a bit | |
1887 | * of paranoid documentation about our requirement to serialise | |
1888 | * memory writes before touching registers / GSM. | |
1889 | */ | |
1890 | wmb(); | |
1891 | ||
6299f992 | 1892 | obj->fault_mappable = false; |
901782b2 CW |
1893 | } |
1894 | ||
eedd10f4 CW |
1895 | void |
1896 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1897 | { | |
1898 | struct drm_i915_gem_object *obj; | |
1899 | ||
1900 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1901 | i915_gem_release_mmap(obj); | |
1902 | } | |
1903 | ||
ad1a7d20 CW |
1904 | /** |
1905 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 1906 | * @dev_priv: i915 device |
ad1a7d20 CW |
1907 | * @size: object size |
1908 | * @tiling_mode: tiling mode | |
1909 | * | |
1910 | * Return the required global GTT size for an object, taking into account | |
1911 | * potential fence register mapping. | |
1912 | */ | |
a9f1481f CW |
1913 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
1914 | u64 size, int tiling_mode) | |
92b88aeb | 1915 | { |
ad1a7d20 | 1916 | u64 ggtt_size; |
92b88aeb | 1917 | |
ad1a7d20 CW |
1918 | GEM_BUG_ON(size == 0); |
1919 | ||
a9f1481f | 1920 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
1921 | tiling_mode == I915_TILING_NONE) |
1922 | return size; | |
92b88aeb CW |
1923 | |
1924 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 1925 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 1926 | ggtt_size = 1024*1024; |
92b88aeb | 1927 | else |
ad1a7d20 | 1928 | ggtt_size = 512*1024; |
92b88aeb | 1929 | |
ad1a7d20 CW |
1930 | while (ggtt_size < size) |
1931 | ggtt_size <<= 1; | |
92b88aeb | 1932 | |
ad1a7d20 | 1933 | return ggtt_size; |
92b88aeb CW |
1934 | } |
1935 | ||
de151cf6 | 1936 | /** |
ad1a7d20 | 1937 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 1938 | * @dev_priv: i915 device |
14bb2c11 TU |
1939 | * @size: object size |
1940 | * @tiling_mode: tiling mode | |
ad1a7d20 | 1941 | * @fenced: is fenced alignment required or not |
de151cf6 | 1942 | * |
ad1a7d20 | 1943 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 1944 | * potential fence register mapping. |
de151cf6 | 1945 | */ |
a9f1481f | 1946 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 1947 | int tiling_mode, bool fenced) |
de151cf6 | 1948 | { |
ad1a7d20 CW |
1949 | GEM_BUG_ON(size == 0); |
1950 | ||
de151cf6 JB |
1951 | /* |
1952 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1953 | * if a fence register is needed for the object. | |
1954 | */ | |
a9f1481f | 1955 | if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) || |
e28f8711 | 1956 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1957 | return 4096; |
1958 | ||
a00b10c3 CW |
1959 | /* |
1960 | * Previous chips need to be aligned to the size of the smallest | |
1961 | * fence register that can contain the object. | |
1962 | */ | |
a9f1481f | 1963 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
1964 | } |
1965 | ||
d8cb5086 CW |
1966 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1967 | { | |
fac5e23e | 1968 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 1969 | int err; |
da494d7c | 1970 | |
f3f6184c CW |
1971 | err = drm_gem_create_mmap_offset(&obj->base); |
1972 | if (!err) | |
1973 | return 0; | |
d8cb5086 | 1974 | |
f3f6184c CW |
1975 | /* We can idle the GPU locklessly to flush stale objects, but in order |
1976 | * to claim that space for ourselves, we need to take the big | |
1977 | * struct_mutex to free the requests+objects and allocate our slot. | |
d8cb5086 | 1978 | */ |
f3f6184c CW |
1979 | err = i915_gem_wait_for_idle(dev_priv, true); |
1980 | if (err) | |
1981 | return err; | |
1982 | ||
1983 | err = i915_mutex_lock_interruptible(&dev_priv->drm); | |
1984 | if (!err) { | |
1985 | i915_gem_retire_requests(dev_priv); | |
1986 | err = drm_gem_create_mmap_offset(&obj->base); | |
1987 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1988 | } | |
da494d7c | 1989 | |
f3f6184c | 1990 | return err; |
d8cb5086 CW |
1991 | } |
1992 | ||
1993 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1994 | { | |
d8cb5086 CW |
1995 | drm_gem_free_mmap_offset(&obj->base); |
1996 | } | |
1997 | ||
da6b51d0 | 1998 | int |
ff72145b DA |
1999 | i915_gem_mmap_gtt(struct drm_file *file, |
2000 | struct drm_device *dev, | |
da6b51d0 | 2001 | uint32_t handle, |
ff72145b | 2002 | uint64_t *offset) |
de151cf6 | 2003 | { |
05394f39 | 2004 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2005 | int ret; |
2006 | ||
03ac0642 | 2007 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2008 | if (!obj) |
2009 | return -ENOENT; | |
ab18282d | 2010 | |
d8cb5086 | 2011 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2012 | if (ret == 0) |
2013 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2014 | |
f3f6184c | 2015 | i915_gem_object_put_unlocked(obj); |
1d7cfea1 | 2016 | return ret; |
de151cf6 JB |
2017 | } |
2018 | ||
ff72145b DA |
2019 | /** |
2020 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2021 | * @dev: DRM device | |
2022 | * @data: GTT mapping ioctl data | |
2023 | * @file: GEM object info | |
2024 | * | |
2025 | * Simply returns the fake offset to userspace so it can mmap it. | |
2026 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2027 | * up so we can get faults in the handler above. | |
2028 | * | |
2029 | * The fault handler will take care of binding the object into the GTT | |
2030 | * (since it may have been evicted to make room for something), allocating | |
2031 | * a fence register, and mapping the appropriate aperture address into | |
2032 | * userspace. | |
2033 | */ | |
2034 | int | |
2035 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2036 | struct drm_file *file) | |
2037 | { | |
2038 | struct drm_i915_gem_mmap_gtt *args = data; | |
2039 | ||
da6b51d0 | 2040 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2041 | } |
2042 | ||
225067ee DV |
2043 | /* Immediately discard the backing storage */ |
2044 | static void | |
2045 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2046 | { |
4d6294bf | 2047 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2048 | |
4d6294bf CW |
2049 | if (obj->base.filp == NULL) |
2050 | return; | |
e5281ccd | 2051 | |
225067ee DV |
2052 | /* Our goal here is to return as much of the memory as |
2053 | * is possible back to the system as we are called from OOM. | |
2054 | * To do this we must instruct the shmfs to drop all of its | |
2055 | * backing pages, *now*. | |
2056 | */ | |
5537252b | 2057 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2058 | obj->madv = __I915_MADV_PURGED; |
2059 | } | |
e5281ccd | 2060 | |
5537252b CW |
2061 | /* Try to discard unwanted pages */ |
2062 | static void | |
2063 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2064 | { |
5537252b CW |
2065 | struct address_space *mapping; |
2066 | ||
2067 | switch (obj->madv) { | |
2068 | case I915_MADV_DONTNEED: | |
2069 | i915_gem_object_truncate(obj); | |
2070 | case __I915_MADV_PURGED: | |
2071 | return; | |
2072 | } | |
2073 | ||
2074 | if (obj->base.filp == NULL) | |
2075 | return; | |
2076 | ||
93c76a3d | 2077 | mapping = obj->base.filp->f_mapping, |
5537252b | 2078 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2079 | } |
2080 | ||
5cdf5881 | 2081 | static void |
05394f39 | 2082 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2083 | { |
85d1225e DG |
2084 | struct sgt_iter sgt_iter; |
2085 | struct page *page; | |
90797e6d | 2086 | int ret; |
1286ff73 | 2087 | |
05394f39 | 2088 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2089 | |
6c085a72 | 2090 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2091 | if (WARN_ON(ret)) { |
6c085a72 CW |
2092 | /* In the event of a disaster, abandon all caches and |
2093 | * hope for the best. | |
2094 | */ | |
2c22569b | 2095 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2096 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2097 | } | |
2098 | ||
e2273302 ID |
2099 | i915_gem_gtt_finish_object(obj); |
2100 | ||
6dacfd2f | 2101 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2102 | i915_gem_object_save_bit_17_swizzle(obj); |
2103 | ||
05394f39 CW |
2104 | if (obj->madv == I915_MADV_DONTNEED) |
2105 | obj->dirty = 0; | |
3ef94daa | 2106 | |
85d1225e | 2107 | for_each_sgt_page(page, sgt_iter, obj->pages) { |
05394f39 | 2108 | if (obj->dirty) |
9da3da66 | 2109 | set_page_dirty(page); |
3ef94daa | 2110 | |
05394f39 | 2111 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2112 | mark_page_accessed(page); |
3ef94daa | 2113 | |
09cbfeaf | 2114 | put_page(page); |
3ef94daa | 2115 | } |
05394f39 | 2116 | obj->dirty = 0; |
673a394b | 2117 | |
9da3da66 CW |
2118 | sg_free_table(obj->pages); |
2119 | kfree(obj->pages); | |
37e680a1 | 2120 | } |
6c085a72 | 2121 | |
dd624afd | 2122 | int |
37e680a1 CW |
2123 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2124 | { | |
2125 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2126 | ||
2f745ad3 | 2127 | if (obj->pages == NULL) |
37e680a1 CW |
2128 | return 0; |
2129 | ||
a5570178 CW |
2130 | if (obj->pages_pin_count) |
2131 | return -EBUSY; | |
2132 | ||
15717de2 | 2133 | GEM_BUG_ON(obj->bind_count); |
3e123027 | 2134 | |
a2165e31 CW |
2135 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2136 | * array, hence protect them from being reaped by removing them from gtt | |
2137 | * lists early. */ | |
35c20a60 | 2138 | list_del(&obj->global_list); |
a2165e31 | 2139 | |
0a798eb9 | 2140 | if (obj->mapping) { |
4b30cb23 CW |
2141 | void *ptr; |
2142 | ||
2143 | ptr = ptr_mask_bits(obj->mapping); | |
2144 | if (is_vmalloc_addr(ptr)) | |
2145 | vunmap(ptr); | |
fb8621d3 | 2146 | else |
4b30cb23 CW |
2147 | kunmap(kmap_to_page(ptr)); |
2148 | ||
0a798eb9 CW |
2149 | obj->mapping = NULL; |
2150 | } | |
2151 | ||
37e680a1 | 2152 | ops->put_pages(obj); |
05394f39 | 2153 | obj->pages = NULL; |
37e680a1 | 2154 | |
5537252b | 2155 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2156 | |
2157 | return 0; | |
2158 | } | |
2159 | ||
37e680a1 | 2160 | static int |
6c085a72 | 2161 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2162 | { |
fac5e23e | 2163 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2164 | int page_count, i; |
2165 | struct address_space *mapping; | |
9da3da66 CW |
2166 | struct sg_table *st; |
2167 | struct scatterlist *sg; | |
85d1225e | 2168 | struct sgt_iter sgt_iter; |
e5281ccd | 2169 | struct page *page; |
90797e6d | 2170 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2171 | int ret; |
6c085a72 | 2172 | gfp_t gfp; |
e5281ccd | 2173 | |
6c085a72 CW |
2174 | /* Assert that the object is not currently in any GPU domain. As it |
2175 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2176 | * a GPU cache | |
2177 | */ | |
2178 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2179 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2180 | ||
9da3da66 CW |
2181 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2182 | if (st == NULL) | |
2183 | return -ENOMEM; | |
2184 | ||
05394f39 | 2185 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2186 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2187 | kfree(st); |
e5281ccd | 2188 | return -ENOMEM; |
9da3da66 | 2189 | } |
e5281ccd | 2190 | |
9da3da66 CW |
2191 | /* Get the list of pages out of our struct file. They'll be pinned |
2192 | * at this point until we release them. | |
2193 | * | |
2194 | * Fail silently without starting the shrinker | |
2195 | */ | |
93c76a3d | 2196 | mapping = obj->base.filp->f_mapping; |
c62d2555 | 2197 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2198 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2199 | sg = st->sgl; |
2200 | st->nents = 0; | |
2201 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2202 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2203 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2204 | i915_gem_shrink(dev_priv, |
2205 | page_count, | |
2206 | I915_SHRINK_BOUND | | |
2207 | I915_SHRINK_UNBOUND | | |
2208 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2209 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2210 | } | |
2211 | if (IS_ERR(page)) { | |
2212 | /* We've tried hard to allocate the memory by reaping | |
2213 | * our own buffer, now let the real VM do its job and | |
2214 | * go down in flames if truly OOM. | |
2215 | */ | |
6c085a72 | 2216 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2217 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2218 | if (IS_ERR(page)) { |
2219 | ret = PTR_ERR(page); | |
6c085a72 | 2220 | goto err_pages; |
e2273302 | 2221 | } |
6c085a72 | 2222 | } |
426729dc KRW |
2223 | #ifdef CONFIG_SWIOTLB |
2224 | if (swiotlb_nr_tbl()) { | |
2225 | st->nents++; | |
2226 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2227 | sg = sg_next(sg); | |
2228 | continue; | |
2229 | } | |
2230 | #endif | |
90797e6d ID |
2231 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2232 | if (i) | |
2233 | sg = sg_next(sg); | |
2234 | st->nents++; | |
2235 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2236 | } else { | |
2237 | sg->length += PAGE_SIZE; | |
2238 | } | |
2239 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2240 | |
2241 | /* Check that the i965g/gm workaround works. */ | |
2242 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2243 | } |
426729dc KRW |
2244 | #ifdef CONFIG_SWIOTLB |
2245 | if (!swiotlb_nr_tbl()) | |
2246 | #endif | |
2247 | sg_mark_end(sg); | |
74ce6b6c CW |
2248 | obj->pages = st; |
2249 | ||
e2273302 ID |
2250 | ret = i915_gem_gtt_prepare_object(obj); |
2251 | if (ret) | |
2252 | goto err_pages; | |
2253 | ||
6dacfd2f | 2254 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2255 | i915_gem_object_do_bit_17_swizzle(obj); |
2256 | ||
3e510a8e | 2257 | if (i915_gem_object_is_tiled(obj) && |
656bfa3a DV |
2258 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
2259 | i915_gem_object_pin_pages(obj); | |
2260 | ||
e5281ccd CW |
2261 | return 0; |
2262 | ||
2263 | err_pages: | |
90797e6d | 2264 | sg_mark_end(sg); |
85d1225e DG |
2265 | for_each_sgt_page(page, sgt_iter, st) |
2266 | put_page(page); | |
9da3da66 CW |
2267 | sg_free_table(st); |
2268 | kfree(st); | |
0820baf3 CW |
2269 | |
2270 | /* shmemfs first checks if there is enough memory to allocate the page | |
2271 | * and reports ENOSPC should there be insufficient, along with the usual | |
2272 | * ENOMEM for a genuine allocation failure. | |
2273 | * | |
2274 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2275 | * space and so want to translate the error from shmemfs back to our | |
2276 | * usual understanding of ENOMEM. | |
2277 | */ | |
e2273302 ID |
2278 | if (ret == -ENOSPC) |
2279 | ret = -ENOMEM; | |
2280 | ||
2281 | return ret; | |
673a394b EA |
2282 | } |
2283 | ||
37e680a1 CW |
2284 | /* Ensure that the associated pages are gathered from the backing storage |
2285 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2286 | * multiple times before they are released by a single call to | |
2287 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2288 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2289 | * or as the object is itself released. | |
2290 | */ | |
2291 | int | |
2292 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2293 | { | |
fac5e23e | 2294 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
37e680a1 CW |
2295 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
2296 | int ret; | |
2297 | ||
2f745ad3 | 2298 | if (obj->pages) |
37e680a1 CW |
2299 | return 0; |
2300 | ||
43e28f09 | 2301 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2302 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2303 | return -EFAULT; |
43e28f09 CW |
2304 | } |
2305 | ||
a5570178 CW |
2306 | BUG_ON(obj->pages_pin_count); |
2307 | ||
37e680a1 CW |
2308 | ret = ops->get_pages(obj); |
2309 | if (ret) | |
2310 | return ret; | |
2311 | ||
35c20a60 | 2312 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2313 | |
2314 | obj->get_page.sg = obj->pages->sgl; | |
2315 | obj->get_page.last = 0; | |
2316 | ||
37e680a1 | 2317 | return 0; |
673a394b EA |
2318 | } |
2319 | ||
dd6034c6 | 2320 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2321 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2322 | enum i915_map_type type) | |
dd6034c6 DG |
2323 | { |
2324 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
2325 | struct sg_table *sgt = obj->pages; | |
85d1225e DG |
2326 | struct sgt_iter sgt_iter; |
2327 | struct page *page; | |
b338fa47 DG |
2328 | struct page *stack_pages[32]; |
2329 | struct page **pages = stack_pages; | |
dd6034c6 | 2330 | unsigned long i = 0; |
d31d7cb1 | 2331 | pgprot_t pgprot; |
dd6034c6 DG |
2332 | void *addr; |
2333 | ||
2334 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2335 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2336 | return kmap(sg_page(sgt->sgl)); |
2337 | ||
b338fa47 DG |
2338 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2339 | /* Too big for stack -- allocate temporary array instead */ | |
2340 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2341 | if (!pages) | |
2342 | return NULL; | |
2343 | } | |
dd6034c6 | 2344 | |
85d1225e DG |
2345 | for_each_sgt_page(page, sgt_iter, sgt) |
2346 | pages[i++] = page; | |
dd6034c6 DG |
2347 | |
2348 | /* Check that we have the expected number of pages */ | |
2349 | GEM_BUG_ON(i != n_pages); | |
2350 | ||
d31d7cb1 CW |
2351 | switch (type) { |
2352 | case I915_MAP_WB: | |
2353 | pgprot = PAGE_KERNEL; | |
2354 | break; | |
2355 | case I915_MAP_WC: | |
2356 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2357 | break; | |
2358 | } | |
2359 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2360 | |
b338fa47 DG |
2361 | if (pages != stack_pages) |
2362 | drm_free_large(pages); | |
dd6034c6 DG |
2363 | |
2364 | return addr; | |
2365 | } | |
2366 | ||
2367 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2368 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2369 | enum i915_map_type type) | |
0a798eb9 | 2370 | { |
d31d7cb1 CW |
2371 | enum i915_map_type has_type; |
2372 | bool pinned; | |
2373 | void *ptr; | |
0a798eb9 CW |
2374 | int ret; |
2375 | ||
2376 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
d31d7cb1 | 2377 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 CW |
2378 | |
2379 | ret = i915_gem_object_get_pages(obj); | |
2380 | if (ret) | |
2381 | return ERR_PTR(ret); | |
2382 | ||
2383 | i915_gem_object_pin_pages(obj); | |
d31d7cb1 | 2384 | pinned = obj->pages_pin_count > 1; |
0a798eb9 | 2385 | |
d31d7cb1 CW |
2386 | ptr = ptr_unpack_bits(obj->mapping, has_type); |
2387 | if (ptr && has_type != type) { | |
2388 | if (pinned) { | |
2389 | ret = -EBUSY; | |
2390 | goto err; | |
0a798eb9 | 2391 | } |
d31d7cb1 CW |
2392 | |
2393 | if (is_vmalloc_addr(ptr)) | |
2394 | vunmap(ptr); | |
2395 | else | |
2396 | kunmap(kmap_to_page(ptr)); | |
2397 | ||
2398 | ptr = obj->mapping = NULL; | |
0a798eb9 CW |
2399 | } |
2400 | ||
d31d7cb1 CW |
2401 | if (!ptr) { |
2402 | ptr = i915_gem_object_map(obj, type); | |
2403 | if (!ptr) { | |
2404 | ret = -ENOMEM; | |
2405 | goto err; | |
2406 | } | |
2407 | ||
2408 | obj->mapping = ptr_pack_bits(ptr, type); | |
2409 | } | |
2410 | ||
2411 | return ptr; | |
2412 | ||
2413 | err: | |
2414 | i915_gem_object_unpin_pages(obj); | |
2415 | return ERR_PTR(ret); | |
0a798eb9 CW |
2416 | } |
2417 | ||
b4716185 | 2418 | static void |
fa545cbf CW |
2419 | i915_gem_object_retire__write(struct i915_gem_active *active, |
2420 | struct drm_i915_gem_request *request) | |
e2d05a8b | 2421 | { |
fa545cbf CW |
2422 | struct drm_i915_gem_object *obj = |
2423 | container_of(active, struct drm_i915_gem_object, last_write); | |
b4716185 | 2424 | |
de152b62 | 2425 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2426 | } |
2427 | ||
caea7476 | 2428 | static void |
fa545cbf CW |
2429 | i915_gem_object_retire__read(struct i915_gem_active *active, |
2430 | struct drm_i915_gem_request *request) | |
ce44b0ea | 2431 | { |
fa545cbf CW |
2432 | int idx = request->engine->id; |
2433 | struct drm_i915_gem_object *obj = | |
2434 | container_of(active, struct drm_i915_gem_object, last_read[idx]); | |
ce44b0ea | 2435 | |
573adb39 | 2436 | GEM_BUG_ON(!i915_gem_object_has_active_engine(obj, idx)); |
b4716185 | 2437 | |
573adb39 CW |
2438 | i915_gem_object_clear_active(obj, idx); |
2439 | if (i915_gem_object_is_active(obj)) | |
b4716185 | 2440 | return; |
caea7476 | 2441 | |
6c246959 CW |
2442 | /* Bump our place on the bound list to keep it roughly in LRU order |
2443 | * so that we don't steal from recently used but inactive objects | |
2444 | * (unless we are forced to ofc!) | |
2445 | */ | |
b0decaf7 CW |
2446 | if (obj->bind_count) |
2447 | list_move_tail(&obj->global_list, | |
2448 | &request->i915->mm.bound_list); | |
caea7476 | 2449 | |
f8c417cd | 2450 | i915_gem_object_put(obj); |
c8725f3d CW |
2451 | } |
2452 | ||
7b4d3a16 | 2453 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2454 | { |
44e2c070 | 2455 | unsigned long elapsed; |
be62acb4 | 2456 | |
44e2c070 | 2457 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2458 | return true; |
2459 | ||
7b4d3a16 | 2460 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2461 | if (ctx->hang_stats.ban_period_seconds && |
2462 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2463 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2464 | return true; | |
be62acb4 MK |
2465 | } |
2466 | ||
2467 | return false; | |
2468 | } | |
2469 | ||
7b4d3a16 | 2470 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2471 | const bool guilty) |
aa60c664 | 2472 | { |
7b4d3a16 | 2473 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2474 | |
2475 | if (guilty) { | |
7b4d3a16 | 2476 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2477 | hs->batch_active++; |
2478 | hs->guilty_ts = get_seconds(); | |
2479 | } else { | |
2480 | hs->batch_pending++; | |
aa60c664 MK |
2481 | } |
2482 | } | |
2483 | ||
8d9fc7fd | 2484 | struct drm_i915_gem_request * |
0bc40be8 | 2485 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2486 | { |
4db080f9 CW |
2487 | struct drm_i915_gem_request *request; |
2488 | ||
f69a02c9 CW |
2489 | /* We are called by the error capture and reset at a random |
2490 | * point in time. In particular, note that neither is crucially | |
2491 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2492 | * assume that no more writes can happen (we waited long enough for | |
2493 | * all writes that were in transaction to be flushed) - adding an | |
2494 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2495 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2496 | */ | |
efdf7c06 | 2497 | list_for_each_entry(request, &engine->request_list, link) { |
f69a02c9 | 2498 | if (i915_gem_request_completed(request)) |
4db080f9 | 2499 | continue; |
aa60c664 | 2500 | |
b6b0fac0 | 2501 | return request; |
4db080f9 | 2502 | } |
b6b0fac0 MK |
2503 | |
2504 | return NULL; | |
2505 | } | |
2506 | ||
7b4d3a16 | 2507 | static void i915_gem_reset_engine_status(struct intel_engine_cs *engine) |
b6b0fac0 MK |
2508 | { |
2509 | struct drm_i915_gem_request *request; | |
2510 | bool ring_hung; | |
2511 | ||
0bc40be8 | 2512 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
2513 | if (request == NULL) |
2514 | return; | |
2515 | ||
0bc40be8 | 2516 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 2517 | |
7b4d3a16 | 2518 | i915_set_reset_status(request->ctx, ring_hung); |
efdf7c06 | 2519 | list_for_each_entry_continue(request, &engine->request_list, link) |
7b4d3a16 | 2520 | i915_set_reset_status(request->ctx, false); |
4db080f9 | 2521 | } |
aa60c664 | 2522 | |
7b4d3a16 | 2523 | static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine) |
4db080f9 | 2524 | { |
dcff85c8 | 2525 | struct drm_i915_gem_request *request; |
7e37f889 | 2526 | struct intel_ring *ring; |
608c1a52 | 2527 | |
c4b0930b CW |
2528 | /* Mark all pending requests as complete so that any concurrent |
2529 | * (lockless) lookup doesn't try and wait upon the request as we | |
2530 | * reset it. | |
2531 | */ | |
87b723a1 | 2532 | intel_engine_init_seqno(engine, engine->last_submitted_seqno); |
c4b0930b | 2533 | |
dcb4c12a OM |
2534 | /* |
2535 | * Clear the execlists queue up before freeing the requests, as those | |
2536 | * are the ones that keep the context and ringbuffer backing objects | |
2537 | * pinned in place. | |
2538 | */ | |
dcb4c12a | 2539 | |
7de1691a | 2540 | if (i915.enable_execlists) { |
27af5eea TU |
2541 | /* Ensure irq handler finishes or is cancelled. */ |
2542 | tasklet_kill(&engine->irq_tasklet); | |
1197b4f2 | 2543 | |
e39d42fa | 2544 | intel_execlists_cancel_requests(engine); |
dcb4c12a OM |
2545 | } |
2546 | ||
1d62beea BW |
2547 | /* |
2548 | * We must free the requests after all the corresponding objects have | |
2549 | * been moved off active lists. Which is the same order as the normal | |
2550 | * retire_requests function does. This is important if object hold | |
2551 | * implicit references on things like e.g. ppgtt address spaces through | |
2552 | * the request. | |
2553 | */ | |
87b723a1 CW |
2554 | request = i915_gem_active_raw(&engine->last_request, |
2555 | &engine->i915->drm.struct_mutex); | |
dcff85c8 | 2556 | if (request) |
05235c53 | 2557 | i915_gem_request_retire_upto(request); |
dcff85c8 | 2558 | GEM_BUG_ON(intel_engine_is_active(engine)); |
608c1a52 CW |
2559 | |
2560 | /* Having flushed all requests from all queues, we know that all | |
2561 | * ringbuffers must now be empty. However, since we do not reclaim | |
2562 | * all space when retiring the request (to prevent HEADs colliding | |
2563 | * with rapid ringbuffer wraparound) the amount of available space | |
2564 | * upon reset is less than when we start. Do one more pass over | |
2565 | * all the ringbuffers to reset last_retired_head. | |
2566 | */ | |
7e37f889 CW |
2567 | list_for_each_entry(ring, &engine->buffers, link) { |
2568 | ring->last_retired_head = ring->tail; | |
2569 | intel_ring_update_space(ring); | |
608c1a52 | 2570 | } |
2ed53a94 | 2571 | |
b913b33c | 2572 | engine->i915->gt.active_engines &= ~intel_engine_flag(engine); |
673a394b EA |
2573 | } |
2574 | ||
069efc1d | 2575 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2576 | { |
fac5e23e | 2577 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2578 | struct intel_engine_cs *engine; |
673a394b | 2579 | |
4db080f9 CW |
2580 | /* |
2581 | * Before we free the objects from the requests, we need to inspect | |
2582 | * them for finding the guilty party. As the requests only borrow | |
2583 | * their reference to the objects, the inspection must be done first. | |
2584 | */ | |
b4ac5afc | 2585 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2586 | i915_gem_reset_engine_status(engine); |
4db080f9 | 2587 | |
b4ac5afc | 2588 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2589 | i915_gem_reset_engine_cleanup(engine); |
b913b33c | 2590 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); |
dfaae392 | 2591 | |
acce9ffa BW |
2592 | i915_gem_context_reset(dev); |
2593 | ||
19b2dbde | 2594 | i915_gem_restore_fences(dev); |
673a394b EA |
2595 | } |
2596 | ||
75ef9da2 | 2597 | static void |
673a394b EA |
2598 | i915_gem_retire_work_handler(struct work_struct *work) |
2599 | { | |
b29c19b6 | 2600 | struct drm_i915_private *dev_priv = |
67d97da3 | 2601 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2602 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2603 | |
891b48cf | 2604 | /* Come back later if the device is busy... */ |
b29c19b6 | 2605 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2606 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2607 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2608 | } |
67d97da3 CW |
2609 | |
2610 | /* Keep the retire handler running until we are finally idle. | |
2611 | * We do not need to do this test under locking as in the worst-case | |
2612 | * we queue the retire worker once too often. | |
2613 | */ | |
c9615613 CW |
2614 | if (READ_ONCE(dev_priv->gt.awake)) { |
2615 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2616 | queue_delayed_work(dev_priv->wq, |
2617 | &dev_priv->gt.retire_work, | |
bcb45086 | 2618 | round_jiffies_up_relative(HZ)); |
c9615613 | 2619 | } |
b29c19b6 | 2620 | } |
0a58705b | 2621 | |
b29c19b6 CW |
2622 | static void |
2623 | i915_gem_idle_work_handler(struct work_struct *work) | |
2624 | { | |
2625 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2626 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2627 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2628 | struct intel_engine_cs *engine; |
67d97da3 CW |
2629 | bool rearm_hangcheck; |
2630 | ||
2631 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2632 | return; | |
2633 | ||
2634 | if (READ_ONCE(dev_priv->gt.active_engines)) | |
2635 | return; | |
2636 | ||
2637 | rearm_hangcheck = | |
2638 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2639 | ||
2640 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2641 | /* Currently busy, come back later */ | |
2642 | mod_delayed_work(dev_priv->wq, | |
2643 | &dev_priv->gt.idle_work, | |
2644 | msecs_to_jiffies(50)); | |
2645 | goto out_rearm; | |
2646 | } | |
2647 | ||
2648 | if (dev_priv->gt.active_engines) | |
2649 | goto out_unlock; | |
b29c19b6 | 2650 | |
b4ac5afc | 2651 | for_each_engine(engine, dev_priv) |
67d97da3 | 2652 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2653 | |
67d97da3 CW |
2654 | GEM_BUG_ON(!dev_priv->gt.awake); |
2655 | dev_priv->gt.awake = false; | |
2656 | rearm_hangcheck = false; | |
30ecad77 | 2657 | |
67d97da3 CW |
2658 | if (INTEL_GEN(dev_priv) >= 6) |
2659 | gen6_rps_idle(dev_priv); | |
2660 | intel_runtime_pm_put(dev_priv); | |
2661 | out_unlock: | |
2662 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2663 | |
67d97da3 CW |
2664 | out_rearm: |
2665 | if (rearm_hangcheck) { | |
2666 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2667 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2668 | } |
673a394b EA |
2669 | } |
2670 | ||
b1f788c6 CW |
2671 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2672 | { | |
2673 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2674 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2675 | struct i915_vma *vma, *vn; | |
2676 | ||
2677 | mutex_lock(&obj->base.dev->struct_mutex); | |
2678 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2679 | if (vma->vm->file == fpriv) | |
2680 | i915_vma_close(vma); | |
2681 | mutex_unlock(&obj->base.dev->struct_mutex); | |
2682 | } | |
2683 | ||
23ba4fd0 BW |
2684 | /** |
2685 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2686 | * @dev: drm device pointer |
2687 | * @data: ioctl data blob | |
2688 | * @file: drm file pointer | |
23ba4fd0 BW |
2689 | * |
2690 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2691 | * the timeout parameter. | |
2692 | * -ETIME: object is still busy after timeout | |
2693 | * -ERESTARTSYS: signal interrupted the wait | |
2694 | * -ENONENT: object doesn't exist | |
2695 | * Also possible, but rare: | |
2696 | * -EAGAIN: GPU wedged | |
2697 | * -ENOMEM: damn | |
2698 | * -ENODEV: Internal IRQ fail | |
2699 | * -E?: The add request failed | |
2700 | * | |
2701 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2702 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2703 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2704 | * without holding struct_mutex the object may become re-busied before this | |
2705 | * function completes. A similar but shorter * race condition exists in the busy | |
2706 | * ioctl | |
2707 | */ | |
2708 | int | |
2709 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2710 | { | |
2711 | struct drm_i915_gem_wait *args = data; | |
033d549b | 2712 | struct intel_rps_client *rps = to_rps_client(file); |
23ba4fd0 | 2713 | struct drm_i915_gem_object *obj; |
033d549b CW |
2714 | unsigned long active; |
2715 | int idx, ret = 0; | |
23ba4fd0 | 2716 | |
11b5d511 DV |
2717 | if (args->flags != 0) |
2718 | return -EINVAL; | |
2719 | ||
03ac0642 | 2720 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 2721 | if (!obj) |
23ba4fd0 | 2722 | return -ENOENT; |
23ba4fd0 | 2723 | |
033d549b CW |
2724 | active = __I915_BO_ACTIVE(obj); |
2725 | for_each_active(active, idx) { | |
2726 | s64 *timeout = args->timeout_ns >= 0 ? &args->timeout_ns : NULL; | |
2727 | ret = i915_gem_active_wait_unlocked(&obj->last_read[idx], true, | |
2728 | timeout, rps); | |
2729 | if (ret) | |
2730 | break; | |
b4716185 CW |
2731 | } |
2732 | ||
033d549b | 2733 | i915_gem_object_put_unlocked(obj); |
ff865885 | 2734 | return ret; |
23ba4fd0 BW |
2735 | } |
2736 | ||
b4716185 | 2737 | static int |
fa545cbf | 2738 | __i915_gem_object_sync(struct drm_i915_gem_request *to, |
8e637178 | 2739 | struct drm_i915_gem_request *from) |
b4716185 | 2740 | { |
b4716185 CW |
2741 | int ret; |
2742 | ||
8e637178 | 2743 | if (to->engine == from->engine) |
b4716185 CW |
2744 | return 0; |
2745 | ||
39df9190 | 2746 | if (!i915.semaphores) { |
776f3236 CW |
2747 | ret = i915_wait_request(from, |
2748 | from->i915->mm.interruptible, | |
2749 | NULL, | |
2750 | NO_WAITBOOST); | |
b4716185 CW |
2751 | if (ret) |
2752 | return ret; | |
b4716185 | 2753 | } else { |
8e637178 | 2754 | int idx = intel_engine_sync_index(from->engine, to->engine); |
ddf07be7 | 2755 | if (from->fence.seqno <= from->engine->semaphore.sync_seqno[idx]) |
b4716185 CW |
2756 | return 0; |
2757 | ||
8e637178 | 2758 | trace_i915_gem_ring_sync_to(to, from); |
ddf07be7 | 2759 | ret = to->engine->semaphore.sync_to(to, from); |
b4716185 CW |
2760 | if (ret) |
2761 | return ret; | |
2762 | ||
ddf07be7 | 2763 | from->engine->semaphore.sync_seqno[idx] = from->fence.seqno; |
b4716185 CW |
2764 | } |
2765 | ||
2766 | return 0; | |
2767 | } | |
2768 | ||
5816d648 BW |
2769 | /** |
2770 | * i915_gem_object_sync - sync an object to a ring. | |
2771 | * | |
2772 | * @obj: object which may be in use on another ring. | |
8e637178 | 2773 | * @to: request we are wishing to use |
5816d648 BW |
2774 | * |
2775 | * This code is meant to abstract object synchronization with the GPU. | |
8e637178 CW |
2776 | * Conceptually we serialise writes between engines inside the GPU. |
2777 | * We only allow one engine to write into a buffer at any time, but | |
2778 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
b4716185 CW |
2779 | * |
2780 | * - If there is an outstanding write request to the object, the new | |
2781 | * request must wait for it to complete (either CPU or in hw, requests | |
2782 | * on the same ring will be naturally ordered). | |
2783 | * | |
2784 | * - If we are a write request (pending_write_domain is set), the new | |
2785 | * request must wait for outstanding read requests to complete. | |
5816d648 BW |
2786 | * |
2787 | * Returns 0 if successful, else propagates up the lower layer error. | |
2788 | */ | |
2911a35b BW |
2789 | int |
2790 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
8e637178 | 2791 | struct drm_i915_gem_request *to) |
2911a35b | 2792 | { |
8cac6f6c CW |
2793 | struct i915_gem_active *active; |
2794 | unsigned long active_mask; | |
2795 | int idx; | |
41c52415 | 2796 | |
8cac6f6c | 2797 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
2911a35b | 2798 | |
573adb39 | 2799 | active_mask = i915_gem_object_get_active(obj); |
8cac6f6c CW |
2800 | if (!active_mask) |
2801 | return 0; | |
27c01aae | 2802 | |
8cac6f6c CW |
2803 | if (obj->base.pending_write_domain) { |
2804 | active = obj->last_read; | |
b4716185 | 2805 | } else { |
8cac6f6c CW |
2806 | active_mask = 1; |
2807 | active = &obj->last_write; | |
b4716185 | 2808 | } |
8cac6f6c CW |
2809 | |
2810 | for_each_active(active_mask, idx) { | |
2811 | struct drm_i915_gem_request *request; | |
2812 | int ret; | |
2813 | ||
2814 | request = i915_gem_active_peek(&active[idx], | |
2815 | &obj->base.dev->struct_mutex); | |
2816 | if (!request) | |
2817 | continue; | |
2818 | ||
fa545cbf | 2819 | ret = __i915_gem_object_sync(to, request); |
b4716185 CW |
2820 | if (ret) |
2821 | return ret; | |
2822 | } | |
2911a35b | 2823 | |
b4716185 | 2824 | return 0; |
2911a35b BW |
2825 | } |
2826 | ||
b5ffc9bc CW |
2827 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2828 | { | |
2829 | u32 old_write_domain, old_read_domains; | |
2830 | ||
b5ffc9bc CW |
2831 | /* Force a pagefault for domain tracking on next user access */ |
2832 | i915_gem_release_mmap(obj); | |
2833 | ||
b97c3d9c KP |
2834 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2835 | return; | |
2836 | ||
b5ffc9bc CW |
2837 | old_read_domains = obj->base.read_domains; |
2838 | old_write_domain = obj->base.write_domain; | |
2839 | ||
2840 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2841 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2842 | ||
2843 | trace_i915_gem_object_change_domain(obj, | |
2844 | old_read_domains, | |
2845 | old_write_domain); | |
2846 | } | |
2847 | ||
8ef8561f CW |
2848 | static void __i915_vma_iounmap(struct i915_vma *vma) |
2849 | { | |
20dfbde4 | 2850 | GEM_BUG_ON(i915_vma_is_pinned(vma)); |
8ef8561f CW |
2851 | |
2852 | if (vma->iomap == NULL) | |
2853 | return; | |
2854 | ||
2855 | io_mapping_unmap(vma->iomap); | |
2856 | vma->iomap = NULL; | |
2857 | } | |
2858 | ||
df0e9a28 | 2859 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2860 | { |
07fe0b12 | 2861 | struct drm_i915_gem_object *obj = vma->obj; |
b0decaf7 | 2862 | unsigned long active; |
43e28f09 | 2863 | int ret; |
673a394b | 2864 | |
b0decaf7 CW |
2865 | /* First wait upon any activity as retiring the request may |
2866 | * have side-effects such as unpinning or even unbinding this vma. | |
2867 | */ | |
2868 | active = i915_vma_get_active(vma); | |
df0e9a28 | 2869 | if (active) { |
b0decaf7 CW |
2870 | int idx; |
2871 | ||
b1f788c6 CW |
2872 | /* When a closed VMA is retired, it is unbound - eek. |
2873 | * In order to prevent it from being recursively closed, | |
2874 | * take a pin on the vma so that the second unbind is | |
2875 | * aborted. | |
2876 | */ | |
20dfbde4 | 2877 | __i915_vma_pin(vma); |
b1f788c6 | 2878 | |
b0decaf7 CW |
2879 | for_each_active(active, idx) { |
2880 | ret = i915_gem_active_retire(&vma->last_read[idx], | |
2881 | &vma->vm->dev->struct_mutex); | |
2882 | if (ret) | |
b1f788c6 | 2883 | break; |
b0decaf7 CW |
2884 | } |
2885 | ||
20dfbde4 | 2886 | __i915_vma_unpin(vma); |
b1f788c6 CW |
2887 | if (ret) |
2888 | return ret; | |
2889 | ||
b0decaf7 CW |
2890 | GEM_BUG_ON(i915_vma_is_active(vma)); |
2891 | } | |
2892 | ||
20dfbde4 | 2893 | if (i915_vma_is_pinned(vma)) |
b0decaf7 CW |
2894 | return -EBUSY; |
2895 | ||
b1f788c6 CW |
2896 | if (!drm_mm_node_allocated(&vma->node)) |
2897 | goto destroy; | |
433544bd | 2898 | |
15717de2 CW |
2899 | GEM_BUG_ON(obj->bind_count == 0); |
2900 | GEM_BUG_ON(!obj->pages); | |
c4670ad0 | 2901 | |
3272db53 CW |
2902 | if (i915_vma_is_ggtt(vma) && |
2903 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
8b1bc9b4 | 2904 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2905 | |
8b1bc9b4 DV |
2906 | /* release the fence reg _after_ flushing */ |
2907 | ret = i915_gem_object_put_fence(obj); | |
2908 | if (ret) | |
2909 | return ret; | |
8ef8561f CW |
2910 | |
2911 | __i915_vma_iounmap(vma); | |
8b1bc9b4 | 2912 | } |
96b47b65 | 2913 | |
50e046b6 CW |
2914 | if (likely(!vma->vm->closed)) { |
2915 | trace_i915_vma_unbind(vma); | |
2916 | vma->vm->unbind_vma(vma); | |
2917 | } | |
3272db53 | 2918 | vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); |
6f65e29a | 2919 | |
50e046b6 CW |
2920 | drm_mm_remove_node(&vma->node); |
2921 | list_move_tail(&vma->vm_link, &vma->vm->unbound_list); | |
2922 | ||
3272db53 | 2923 | if (i915_vma_is_ggtt(vma)) { |
fe14d5f4 TU |
2924 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
2925 | obj->map_and_fenceable = false; | |
247177dd CW |
2926 | } else if (vma->pages) { |
2927 | sg_free_table(vma->pages); | |
2928 | kfree(vma->pages); | |
fe14d5f4 TU |
2929 | } |
2930 | } | |
247177dd | 2931 | vma->pages = NULL; |
673a394b | 2932 | |
2f633156 | 2933 | /* Since the unbound list is global, only move to that list if |
b93dab6e | 2934 | * no more VMAs exist. */ |
15717de2 CW |
2935 | if (--obj->bind_count == 0) |
2936 | list_move_tail(&obj->global_list, | |
2937 | &to_i915(obj->base.dev)->mm.unbound_list); | |
673a394b | 2938 | |
70903c3b CW |
2939 | /* And finally now the object is completely decoupled from this vma, |
2940 | * we can drop its hold on the backing storage and allow it to be | |
2941 | * reaped by the shrinker. | |
2942 | */ | |
2943 | i915_gem_object_unpin_pages(obj); | |
2944 | ||
b1f788c6 | 2945 | destroy: |
3272db53 | 2946 | if (unlikely(i915_vma_is_closed(vma))) |
b1f788c6 CW |
2947 | i915_vma_destroy(vma); |
2948 | ||
88241785 | 2949 | return 0; |
54cf91dc CW |
2950 | } |
2951 | ||
dcff85c8 CW |
2952 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
2953 | bool interruptible) | |
4df2faf4 | 2954 | { |
e2f80391 | 2955 | struct intel_engine_cs *engine; |
b4ac5afc | 2956 | int ret; |
4df2faf4 | 2957 | |
b4ac5afc | 2958 | for_each_engine(engine, dev_priv) { |
62e63007 CW |
2959 | if (engine->last_context == NULL) |
2960 | continue; | |
2961 | ||
dcff85c8 | 2962 | ret = intel_engine_idle(engine, interruptible); |
1ec14ad3 CW |
2963 | if (ret) |
2964 | return ret; | |
2965 | } | |
4df2faf4 | 2966 | |
8a1a49f9 | 2967 | return 0; |
4df2faf4 DV |
2968 | } |
2969 | ||
4144f9b5 | 2970 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
2971 | unsigned long cache_level) |
2972 | { | |
4144f9b5 | 2973 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
2974 | struct drm_mm_node *other; |
2975 | ||
4144f9b5 CW |
2976 | /* |
2977 | * On some machines we have to be careful when putting differing types | |
2978 | * of snoopable memory together to avoid the prefetcher crossing memory | |
2979 | * domains and dying. During vm initialisation, we decide whether or not | |
2980 | * these constraints apply and set the drm_mm.color_adjust | |
2981 | * appropriately. | |
42d6ab48 | 2982 | */ |
4144f9b5 | 2983 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
2984 | return true; |
2985 | ||
c6cfb325 | 2986 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
2987 | return true; |
2988 | ||
2989 | if (list_empty(>t_space->node_list)) | |
2990 | return true; | |
2991 | ||
2992 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2993 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2994 | return false; | |
2995 | ||
2996 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2997 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2998 | return false; | |
2999 | ||
3000 | return true; | |
3001 | } | |
3002 | ||
673a394b | 3003 | /** |
59bfa124 CW |
3004 | * i915_vma_insert - finds a slot for the vma in its address space |
3005 | * @vma: the vma | |
91b2db6f | 3006 | * @size: requested size in bytes (can be larger than the VMA) |
59bfa124 | 3007 | * @alignment: required alignment |
14bb2c11 | 3008 | * @flags: mask of PIN_* flags to use |
59bfa124 CW |
3009 | * |
3010 | * First we try to allocate some free space that meets the requirements for | |
3011 | * the VMA. Failiing that, if the flags permit, it will evict an old VMA, | |
3012 | * preferrably the oldest idle entry to make room for the new VMA. | |
3013 | * | |
3014 | * Returns: | |
3015 | * 0 on success, negative error code otherwise. | |
673a394b | 3016 | */ |
59bfa124 CW |
3017 | static int |
3018 | i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) | |
673a394b | 3019 | { |
59bfa124 CW |
3020 | struct drm_i915_private *dev_priv = to_i915(vma->vm->dev); |
3021 | struct drm_i915_gem_object *obj = vma->obj; | |
de180033 CW |
3022 | u64 start, end; |
3023 | u64 min_alignment; | |
07f73f69 | 3024 | int ret; |
673a394b | 3025 | |
3272db53 | 3026 | GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); |
59bfa124 | 3027 | GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); |
de180033 CW |
3028 | |
3029 | size = max(size, vma->size); | |
3030 | if (flags & PIN_MAPPABLE) | |
3e510a8e CW |
3031 | size = i915_gem_get_ggtt_size(dev_priv, size, |
3032 | i915_gem_object_get_tiling(obj)); | |
de180033 CW |
3033 | |
3034 | min_alignment = | |
3e510a8e CW |
3035 | i915_gem_get_ggtt_alignment(dev_priv, size, |
3036 | i915_gem_object_get_tiling(obj), | |
de180033 CW |
3037 | flags & PIN_MAPPABLE); |
3038 | if (alignment == 0) | |
3039 | alignment = min_alignment; | |
3040 | if (alignment & (min_alignment - 1)) { | |
3041 | DRM_DEBUG("Invalid object alignment requested %llu, minimum %llu\n", | |
3042 | alignment, min_alignment); | |
59bfa124 | 3043 | return -EINVAL; |
91e6711e | 3044 | } |
a00b10c3 | 3045 | |
101b506a | 3046 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
de180033 CW |
3047 | |
3048 | end = vma->vm->total; | |
101b506a | 3049 | if (flags & PIN_MAPPABLE) |
91b2db6f | 3050 | end = min_t(u64, end, dev_priv->ggtt.mappable_end); |
101b506a | 3051 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3052 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3053 | |
91e6711e JL |
3054 | /* If binding the object/GGTT view requires more space than the entire |
3055 | * aperture has, reject it early before evicting everything in a vain | |
3056 | * attempt to find space. | |
654fc607 | 3057 | */ |
91e6711e | 3058 | if (size > end) { |
de180033 | 3059 | DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n", |
91b2db6f | 3060 | size, obj->base.size, |
1ec9e26d | 3061 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3062 | end); |
59bfa124 | 3063 | return -E2BIG; |
654fc607 CW |
3064 | } |
3065 | ||
37e680a1 | 3066 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3067 | if (ret) |
59bfa124 | 3068 | return ret; |
6c085a72 | 3069 | |
fbdda6fb CW |
3070 | i915_gem_object_pin_pages(obj); |
3071 | ||
506a8e87 | 3072 | if (flags & PIN_OFFSET_FIXED) { |
59bfa124 | 3073 | u64 offset = flags & PIN_OFFSET_MASK; |
de180033 | 3074 | if (offset & (alignment - 1) || offset > end - size) { |
506a8e87 | 3075 | ret = -EINVAL; |
de180033 | 3076 | goto err_unpin; |
506a8e87 | 3077 | } |
de180033 | 3078 | |
506a8e87 CW |
3079 | vma->node.start = offset; |
3080 | vma->node.size = size; | |
3081 | vma->node.color = obj->cache_level; | |
de180033 | 3082 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
506a8e87 CW |
3083 | if (ret) { |
3084 | ret = i915_gem_evict_for_vma(vma); | |
3085 | if (ret == 0) | |
de180033 CW |
3086 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
3087 | if (ret) | |
3088 | goto err_unpin; | |
506a8e87 | 3089 | } |
101b506a | 3090 | } else { |
de180033 CW |
3091 | u32 search_flag, alloc_flag; |
3092 | ||
506a8e87 CW |
3093 | if (flags & PIN_HIGH) { |
3094 | search_flag = DRM_MM_SEARCH_BELOW; | |
3095 | alloc_flag = DRM_MM_CREATE_TOP; | |
3096 | } else { | |
3097 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3098 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3099 | } | |
101b506a | 3100 | |
954c4691 CW |
3101 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, |
3102 | * so we know that we always have a minimum alignment of 4096. | |
3103 | * The drm_mm range manager is optimised to return results | |
3104 | * with zero alignment, so where possible use the optimal | |
3105 | * path. | |
3106 | */ | |
3107 | if (alignment <= 4096) | |
3108 | alignment = 0; | |
3109 | ||
0a9ae0d7 | 3110 | search_free: |
de180033 CW |
3111 | ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm, |
3112 | &vma->node, | |
506a8e87 CW |
3113 | size, alignment, |
3114 | obj->cache_level, | |
3115 | start, end, | |
3116 | search_flag, | |
3117 | alloc_flag); | |
3118 | if (ret) { | |
de180033 | 3119 | ret = i915_gem_evict_something(vma->vm, size, alignment, |
506a8e87 CW |
3120 | obj->cache_level, |
3121 | start, end, | |
3122 | flags); | |
3123 | if (ret == 0) | |
3124 | goto search_free; | |
9731129c | 3125 | |
de180033 | 3126 | goto err_unpin; |
506a8e87 | 3127 | } |
673a394b | 3128 | } |
37508589 | 3129 | GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level)); |
673a394b | 3130 | |
35c20a60 | 3131 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
de180033 | 3132 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
15717de2 | 3133 | obj->bind_count++; |
bf1a1092 | 3134 | |
59bfa124 | 3135 | return 0; |
2f633156 | 3136 | |
bc6bc15b | 3137 | err_unpin: |
2f633156 | 3138 | i915_gem_object_unpin_pages(obj); |
59bfa124 | 3139 | return ret; |
673a394b EA |
3140 | } |
3141 | ||
000433b6 | 3142 | bool |
2c22569b CW |
3143 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3144 | bool force) | |
673a394b | 3145 | { |
673a394b EA |
3146 | /* If we don't have a page list set up, then we're not pinned |
3147 | * to GPU, and we can ignore the cache flush because it'll happen | |
3148 | * again at bind time. | |
3149 | */ | |
05394f39 | 3150 | if (obj->pages == NULL) |
000433b6 | 3151 | return false; |
673a394b | 3152 | |
769ce464 ID |
3153 | /* |
3154 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3155 | * marked as wc by the system, or the system is cache-coherent. | |
3156 | */ | |
6a2c4232 | 3157 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3158 | return false; |
769ce464 | 3159 | |
9c23f7fc CW |
3160 | /* If the GPU is snooping the contents of the CPU cache, |
3161 | * we do not need to manually clear the CPU cache lines. However, | |
3162 | * the caches are only snooped when the render cache is | |
3163 | * flushed/invalidated. As we always have to emit invalidations | |
3164 | * and flushes when moving into and out of the RENDER domain, correct | |
3165 | * snooping behaviour occurs naturally as the result of our domain | |
3166 | * tracking. | |
3167 | */ | |
0f71979a CW |
3168 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3169 | obj->cache_dirty = true; | |
000433b6 | 3170 | return false; |
0f71979a | 3171 | } |
9c23f7fc | 3172 | |
1c5d22f7 | 3173 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3174 | drm_clflush_sg(obj->pages); |
0f71979a | 3175 | obj->cache_dirty = false; |
000433b6 CW |
3176 | |
3177 | return true; | |
e47c68e9 EA |
3178 | } |
3179 | ||
3180 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3181 | static void | |
05394f39 | 3182 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3183 | { |
3b5724d7 | 3184 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
1c5d22f7 | 3185 | |
05394f39 | 3186 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3187 | return; |
3188 | ||
63256ec5 | 3189 | /* No actual flushing is required for the GTT write domain. Writes |
3b5724d7 | 3190 | * to it "immediately" go to main memory as far as we know, so there's |
e47c68e9 | 3191 | * no chipset flush. It also doesn't land in render cache. |
63256ec5 CW |
3192 | * |
3193 | * However, we do have to enforce the order so that all writes through | |
3194 | * the GTT land before any writes to the device, such as updates to | |
3195 | * the GATT itself. | |
3b5724d7 CW |
3196 | * |
3197 | * We also have to wait a bit for the writes to land from the GTT. | |
3198 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
3199 | * timing. This issue has only been observed when switching quickly | |
3200 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
3201 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
3202 | * system agents we cannot reproduce this behaviour). | |
e47c68e9 | 3203 | */ |
63256ec5 | 3204 | wmb(); |
3b5724d7 CW |
3205 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) |
3206 | POSTING_READ(RING_ACTHD(dev_priv->engine[RCS].mmio_base)); | |
63256ec5 | 3207 | |
d243ad82 | 3208 | intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); |
f99d7069 | 3209 | |
b0dc465f | 3210 | obj->base.write_domain = 0; |
1c5d22f7 | 3211 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3212 | obj->base.read_domains, |
b0dc465f | 3213 | I915_GEM_DOMAIN_GTT); |
e47c68e9 EA |
3214 | } |
3215 | ||
3216 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3217 | static void | |
e62b59e4 | 3218 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3219 | { |
05394f39 | 3220 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3221 | return; |
3222 | ||
e62b59e4 | 3223 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 3224 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 3225 | |
de152b62 | 3226 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3227 | |
b0dc465f | 3228 | obj->base.write_domain = 0; |
1c5d22f7 | 3229 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3230 | obj->base.read_domains, |
b0dc465f | 3231 | I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3232 | } |
3233 | ||
2ef7eeaa EA |
3234 | /** |
3235 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3236 | * @obj: object to act on |
3237 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3238 | * |
3239 | * This function returns when the move is complete, including waiting on | |
3240 | * flushes to occur. | |
3241 | */ | |
79e53945 | 3242 | int |
2021746e | 3243 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3244 | { |
1c5d22f7 | 3245 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3246 | struct i915_vma *vma; |
e47c68e9 | 3247 | int ret; |
2ef7eeaa | 3248 | |
0201f1ec | 3249 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3250 | if (ret) |
3251 | return ret; | |
3252 | ||
c13d87ea CW |
3253 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3254 | return 0; | |
3255 | ||
43566ded CW |
3256 | /* Flush and acquire obj->pages so that we are coherent through |
3257 | * direct access in memory with previous cached writes through | |
3258 | * shmemfs and that our cache domain tracking remains valid. | |
3259 | * For example, if the obj->filp was moved to swap without us | |
3260 | * being notified and releasing the pages, we would mistakenly | |
3261 | * continue to assume that the obj remained out of the CPU cached | |
3262 | * domain. | |
3263 | */ | |
3264 | ret = i915_gem_object_get_pages(obj); | |
3265 | if (ret) | |
3266 | return ret; | |
3267 | ||
e62b59e4 | 3268 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3269 | |
d0a57789 CW |
3270 | /* Serialise direct access to this object with the barriers for |
3271 | * coherent writes from the GPU, by effectively invalidating the | |
3272 | * GTT domain upon first access. | |
3273 | */ | |
3274 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3275 | mb(); | |
3276 | ||
05394f39 CW |
3277 | old_write_domain = obj->base.write_domain; |
3278 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3279 | |
e47c68e9 EA |
3280 | /* It should now be out of any other write domains, and we can update |
3281 | * the domain values for our changes. | |
3282 | */ | |
05394f39 CW |
3283 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3284 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3285 | if (write) { |
05394f39 CW |
3286 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3287 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3288 | obj->dirty = 1; | |
2ef7eeaa EA |
3289 | } |
3290 | ||
1c5d22f7 CW |
3291 | trace_i915_gem_object_change_domain(obj, |
3292 | old_read_domains, | |
3293 | old_write_domain); | |
3294 | ||
8325a09d | 3295 | /* And bump the LRU for this access */ |
058d88c4 | 3296 | vma = i915_gem_object_to_ggtt(obj, NULL); |
b0decaf7 CW |
3297 | if (vma && |
3298 | drm_mm_node_allocated(&vma->node) && | |
3299 | !i915_vma_is_active(vma)) | |
3300 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
8325a09d | 3301 | |
e47c68e9 EA |
3302 | return 0; |
3303 | } | |
3304 | ||
ef55f92a CW |
3305 | /** |
3306 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3307 | * @obj: object to act on |
3308 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3309 | * |
3310 | * After this function returns, the object will be in the new cache-level | |
3311 | * across all GTT and the contents of the backing storage will be coherent, | |
3312 | * with respect to the new cache-level. In order to keep the backing storage | |
3313 | * coherent for all users, we only allow a single cache level to be set | |
3314 | * globally on the object and prevent it from being changed whilst the | |
3315 | * hardware is reading from the object. That is if the object is currently | |
3316 | * on the scanout it will be set to uncached (or equivalent display | |
3317 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3318 | * that all direct access to the scanout remains coherent. | |
3319 | */ | |
e4ffd173 CW |
3320 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3321 | enum i915_cache_level cache_level) | |
3322 | { | |
aa653a68 | 3323 | struct i915_vma *vma; |
ed75a55b | 3324 | int ret = 0; |
e4ffd173 CW |
3325 | |
3326 | if (obj->cache_level == cache_level) | |
ed75a55b | 3327 | goto out; |
e4ffd173 | 3328 | |
ef55f92a CW |
3329 | /* Inspect the list of currently bound VMA and unbind any that would |
3330 | * be invalid given the new cache-level. This is principally to | |
3331 | * catch the issue of the CS prefetch crossing page boundaries and | |
3332 | * reading an invalid PTE on older architectures. | |
3333 | */ | |
aa653a68 CW |
3334 | restart: |
3335 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3336 | if (!drm_mm_node_allocated(&vma->node)) |
3337 | continue; | |
3338 | ||
20dfbde4 | 3339 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3340 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3341 | return -EBUSY; | |
3342 | } | |
3343 | ||
aa653a68 CW |
3344 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3345 | continue; | |
3346 | ||
3347 | ret = i915_vma_unbind(vma); | |
3348 | if (ret) | |
3349 | return ret; | |
3350 | ||
3351 | /* As unbinding may affect other elements in the | |
3352 | * obj->vma_list (due to side-effects from retiring | |
3353 | * an active vma), play safe and restart the iterator. | |
3354 | */ | |
3355 | goto restart; | |
42d6ab48 CW |
3356 | } |
3357 | ||
ef55f92a CW |
3358 | /* We can reuse the existing drm_mm nodes but need to change the |
3359 | * cache-level on the PTE. We could simply unbind them all and | |
3360 | * rebind with the correct cache-level on next use. However since | |
3361 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3362 | * rewrite the PTE in the belief that doing so tramples upon less | |
3363 | * state and so involves less work. | |
3364 | */ | |
15717de2 | 3365 | if (obj->bind_count) { |
ef55f92a CW |
3366 | /* Before we change the PTE, the GPU must not be accessing it. |
3367 | * If we wait upon the object, we know that all the bound | |
3368 | * VMA are no longer active. | |
3369 | */ | |
2e2f351d | 3370 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3371 | if (ret) |
3372 | return ret; | |
3373 | ||
aa653a68 | 3374 | if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) { |
ef55f92a CW |
3375 | /* Access to snoopable pages through the GTT is |
3376 | * incoherent and on some machines causes a hard | |
3377 | * lockup. Relinquish the CPU mmaping to force | |
3378 | * userspace to refault in the pages and we can | |
3379 | * then double check if the GTT mapping is still | |
3380 | * valid for that pointer access. | |
3381 | */ | |
3382 | i915_gem_release_mmap(obj); | |
3383 | ||
3384 | /* As we no longer need a fence for GTT access, | |
3385 | * we can relinquish it now (and so prevent having | |
3386 | * to steal a fence from someone else on the next | |
3387 | * fence request). Note GPU activity would have | |
3388 | * dropped the fence as all snoopable access is | |
3389 | * supposed to be linear. | |
3390 | */ | |
e4ffd173 CW |
3391 | ret = i915_gem_object_put_fence(obj); |
3392 | if (ret) | |
3393 | return ret; | |
ef55f92a CW |
3394 | } else { |
3395 | /* We either have incoherent backing store and | |
3396 | * so no GTT access or the architecture is fully | |
3397 | * coherent. In such cases, existing GTT mmaps | |
3398 | * ignore the cache bit in the PTE and we can | |
3399 | * rewrite it without confusing the GPU or having | |
3400 | * to force userspace to fault back in its mmaps. | |
3401 | */ | |
e4ffd173 CW |
3402 | } |
3403 | ||
1c7f4bca | 3404 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3405 | if (!drm_mm_node_allocated(&vma->node)) |
3406 | continue; | |
3407 | ||
3408 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3409 | if (ret) | |
3410 | return ret; | |
3411 | } | |
e4ffd173 CW |
3412 | } |
3413 | ||
1c7f4bca | 3414 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3415 | vma->node.color = cache_level; |
3416 | obj->cache_level = cache_level; | |
3417 | ||
ed75a55b | 3418 | out: |
ef55f92a CW |
3419 | /* Flush the dirty CPU caches to the backing storage so that the |
3420 | * object is now coherent at its new cache level (with respect | |
3421 | * to the access domain). | |
3422 | */ | |
b50a5371 | 3423 | if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { |
0f71979a | 3424 | if (i915_gem_clflush_object(obj, true)) |
c033666a | 3425 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
3426 | } |
3427 | ||
e4ffd173 CW |
3428 | return 0; |
3429 | } | |
3430 | ||
199adf40 BW |
3431 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3432 | struct drm_file *file) | |
e6994aee | 3433 | { |
199adf40 | 3434 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3435 | struct drm_i915_gem_object *obj; |
e6994aee | 3436 | |
03ac0642 CW |
3437 | obj = i915_gem_object_lookup(file, args->handle); |
3438 | if (!obj) | |
432be69d | 3439 | return -ENOENT; |
e6994aee | 3440 | |
651d794f CW |
3441 | switch (obj->cache_level) { |
3442 | case I915_CACHE_LLC: | |
3443 | case I915_CACHE_L3_LLC: | |
3444 | args->caching = I915_CACHING_CACHED; | |
3445 | break; | |
3446 | ||
4257d3ba CW |
3447 | case I915_CACHE_WT: |
3448 | args->caching = I915_CACHING_DISPLAY; | |
3449 | break; | |
3450 | ||
651d794f CW |
3451 | default: |
3452 | args->caching = I915_CACHING_NONE; | |
3453 | break; | |
3454 | } | |
e6994aee | 3455 | |
34911fd3 | 3456 | i915_gem_object_put_unlocked(obj); |
432be69d | 3457 | return 0; |
e6994aee CW |
3458 | } |
3459 | ||
199adf40 BW |
3460 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3461 | struct drm_file *file) | |
e6994aee | 3462 | { |
fac5e23e | 3463 | struct drm_i915_private *dev_priv = to_i915(dev); |
199adf40 | 3464 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3465 | struct drm_i915_gem_object *obj; |
3466 | enum i915_cache_level level; | |
3467 | int ret; | |
3468 | ||
199adf40 BW |
3469 | switch (args->caching) { |
3470 | case I915_CACHING_NONE: | |
e6994aee CW |
3471 | level = I915_CACHE_NONE; |
3472 | break; | |
199adf40 | 3473 | case I915_CACHING_CACHED: |
e5756c10 ID |
3474 | /* |
3475 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3476 | * snooped mapping may leave stale data in a corresponding CPU | |
3477 | * cacheline, whereas normally such cachelines would get | |
3478 | * invalidated. | |
3479 | */ | |
ca377809 | 3480 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
3481 | return -ENODEV; |
3482 | ||
e6994aee CW |
3483 | level = I915_CACHE_LLC; |
3484 | break; | |
4257d3ba CW |
3485 | case I915_CACHING_DISPLAY: |
3486 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3487 | break; | |
e6994aee CW |
3488 | default: |
3489 | return -EINVAL; | |
3490 | } | |
3491 | ||
fd0fe6ac ID |
3492 | intel_runtime_pm_get(dev_priv); |
3493 | ||
3bc2913e BW |
3494 | ret = i915_mutex_lock_interruptible(dev); |
3495 | if (ret) | |
fd0fe6ac | 3496 | goto rpm_put; |
3bc2913e | 3497 | |
03ac0642 CW |
3498 | obj = i915_gem_object_lookup(file, args->handle); |
3499 | if (!obj) { | |
e6994aee CW |
3500 | ret = -ENOENT; |
3501 | goto unlock; | |
3502 | } | |
3503 | ||
3504 | ret = i915_gem_object_set_cache_level(obj, level); | |
3505 | ||
f8c417cd | 3506 | i915_gem_object_put(obj); |
e6994aee CW |
3507 | unlock: |
3508 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
3509 | rpm_put: |
3510 | intel_runtime_pm_put(dev_priv); | |
3511 | ||
e6994aee CW |
3512 | return ret; |
3513 | } | |
3514 | ||
b9241ea3 | 3515 | /* |
2da3b9b9 CW |
3516 | * Prepare buffer for display plane (scanout, cursors, etc). |
3517 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3518 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3519 | */ |
058d88c4 | 3520 | struct i915_vma * |
2da3b9b9 CW |
3521 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3522 | u32 alignment, | |
e6617330 | 3523 | const struct i915_ggtt_view *view) |
b9241ea3 | 3524 | { |
058d88c4 | 3525 | struct i915_vma *vma; |
2da3b9b9 | 3526 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3527 | int ret; |
3528 | ||
cc98b413 CW |
3529 | /* Mark the pin_display early so that we account for the |
3530 | * display coherency whilst setting up the cache domains. | |
3531 | */ | |
8a0c39b1 | 3532 | obj->pin_display++; |
cc98b413 | 3533 | |
a7ef0640 EA |
3534 | /* The display engine is not coherent with the LLC cache on gen6. As |
3535 | * a result, we make sure that the pinning that is about to occur is | |
3536 | * done with uncached PTEs. This is lowest common denominator for all | |
3537 | * chipsets. | |
3538 | * | |
3539 | * However for gen6+, we could do better by using the GFDT bit instead | |
3540 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3541 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3542 | */ | |
651d794f CW |
3543 | ret = i915_gem_object_set_cache_level(obj, |
3544 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3545 | if (ret) { |
3546 | vma = ERR_PTR(ret); | |
cc98b413 | 3547 | goto err_unpin_display; |
058d88c4 | 3548 | } |
a7ef0640 | 3549 | |
2da3b9b9 CW |
3550 | /* As the user may map the buffer once pinned in the display plane |
3551 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3552 | * always use map_and_fenceable for all scanout buffers. | |
3553 | */ | |
058d88c4 | 3554 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
50470bb0 TU |
3555 | view->type == I915_GGTT_VIEW_NORMAL ? |
3556 | PIN_MAPPABLE : 0); | |
058d88c4 | 3557 | if (IS_ERR(vma)) |
cc98b413 | 3558 | goto err_unpin_display; |
2da3b9b9 | 3559 | |
058d88c4 CW |
3560 | WARN_ON(obj->pin_display > i915_vma_pin_count(vma)); |
3561 | ||
e62b59e4 | 3562 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3563 | |
2da3b9b9 | 3564 | old_write_domain = obj->base.write_domain; |
05394f39 | 3565 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3566 | |
3567 | /* It should now be out of any other write domains, and we can update | |
3568 | * the domain values for our changes. | |
3569 | */ | |
e5f1d962 | 3570 | obj->base.write_domain = 0; |
05394f39 | 3571 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3572 | |
3573 | trace_i915_gem_object_change_domain(obj, | |
3574 | old_read_domains, | |
2da3b9b9 | 3575 | old_write_domain); |
b9241ea3 | 3576 | |
058d88c4 | 3577 | return vma; |
cc98b413 CW |
3578 | |
3579 | err_unpin_display: | |
8a0c39b1 | 3580 | obj->pin_display--; |
058d88c4 | 3581 | return vma; |
cc98b413 CW |
3582 | } |
3583 | ||
3584 | void | |
058d88c4 | 3585 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3586 | { |
058d88c4 | 3587 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3588 | return; |
3589 | ||
058d88c4 | 3590 | vma->obj->pin_display--; |
e6617330 | 3591 | |
058d88c4 CW |
3592 | i915_vma_unpin(vma); |
3593 | WARN_ON(vma->obj->pin_display > i915_vma_pin_count(vma)); | |
b9241ea3 ZW |
3594 | } |
3595 | ||
e47c68e9 EA |
3596 | /** |
3597 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3598 | * @obj: object to act on |
3599 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3600 | * |
3601 | * This function returns when the move is complete, including waiting on | |
3602 | * flushes to occur. | |
3603 | */ | |
dabdfe02 | 3604 | int |
919926ae | 3605 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3606 | { |
1c5d22f7 | 3607 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3608 | int ret; |
3609 | ||
0201f1ec | 3610 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3611 | if (ret) |
3612 | return ret; | |
3613 | ||
c13d87ea CW |
3614 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3615 | return 0; | |
3616 | ||
e47c68e9 | 3617 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3618 | |
05394f39 CW |
3619 | old_write_domain = obj->base.write_domain; |
3620 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3621 | |
e47c68e9 | 3622 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3623 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3624 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3625 | |
05394f39 | 3626 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3627 | } |
3628 | ||
3629 | /* It should now be out of any other write domains, and we can update | |
3630 | * the domain values for our changes. | |
3631 | */ | |
05394f39 | 3632 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3633 | |
3634 | /* If we're writing through the CPU, then the GPU read domains will | |
3635 | * need to be invalidated at next use. | |
3636 | */ | |
3637 | if (write) { | |
05394f39 CW |
3638 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3639 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3640 | } |
2ef7eeaa | 3641 | |
1c5d22f7 CW |
3642 | trace_i915_gem_object_change_domain(obj, |
3643 | old_read_domains, | |
3644 | old_write_domain); | |
3645 | ||
2ef7eeaa EA |
3646 | return 0; |
3647 | } | |
3648 | ||
673a394b EA |
3649 | /* Throttle our rendering by waiting until the ring has completed our requests |
3650 | * emitted over 20 msec ago. | |
3651 | * | |
b962442e EA |
3652 | * Note that if we were to use the current jiffies each time around the loop, |
3653 | * we wouldn't escape the function with any frames outstanding if the time to | |
3654 | * render a frame was over 20ms. | |
3655 | * | |
673a394b EA |
3656 | * This should get us reasonable parallelism between CPU and GPU but also |
3657 | * relatively low latency when blocking on a particular request to finish. | |
3658 | */ | |
40a5f0de | 3659 | static int |
f787a5f5 | 3660 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3661 | { |
fac5e23e | 3662 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3663 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3664 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3665 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 3666 | int ret; |
93533c29 | 3667 | |
308887aa DV |
3668 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3669 | if (ret) | |
3670 | return ret; | |
3671 | ||
f4457ae7 CW |
3672 | /* ABI: return -EIO if already wedged */ |
3673 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3674 | return -EIO; | |
e110e8d6 | 3675 | |
1c25595f | 3676 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3677 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3678 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3679 | break; | |
40a5f0de | 3680 | |
fcfa423c JH |
3681 | /* |
3682 | * Note that the request might not have been submitted yet. | |
3683 | * In which case emitted_jiffies will be zero. | |
3684 | */ | |
3685 | if (!request->emitted_jiffies) | |
3686 | continue; | |
3687 | ||
54fb2411 | 3688 | target = request; |
b962442e | 3689 | } |
ff865885 | 3690 | if (target) |
e8a261ea | 3691 | i915_gem_request_get(target); |
1c25595f | 3692 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3693 | |
54fb2411 | 3694 | if (target == NULL) |
f787a5f5 | 3695 | return 0; |
2bc43b5c | 3696 | |
776f3236 | 3697 | ret = i915_wait_request(target, true, NULL, NULL); |
e8a261ea | 3698 | i915_gem_request_put(target); |
ff865885 | 3699 | |
40a5f0de EA |
3700 | return ret; |
3701 | } | |
3702 | ||
d23db88c | 3703 | static bool |
91b2db6f | 3704 | i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) |
d23db88c CW |
3705 | { |
3706 | struct drm_i915_gem_object *obj = vma->obj; | |
3707 | ||
59bfa124 CW |
3708 | if (!drm_mm_node_allocated(&vma->node)) |
3709 | return false; | |
3710 | ||
91b2db6f CW |
3711 | if (vma->node.size < size) |
3712 | return true; | |
3713 | ||
3714 | if (alignment && vma->node.start & (alignment - 1)) | |
d23db88c CW |
3715 | return true; |
3716 | ||
3717 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
3718 | return true; | |
3719 | ||
3720 | if (flags & PIN_OFFSET_BIAS && | |
3721 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
3722 | return true; | |
3723 | ||
506a8e87 CW |
3724 | if (flags & PIN_OFFSET_FIXED && |
3725 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
3726 | return true; | |
3727 | ||
d23db88c CW |
3728 | return false; |
3729 | } | |
3730 | ||
d0710abb CW |
3731 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
3732 | { | |
3733 | struct drm_i915_gem_object *obj = vma->obj; | |
a9f1481f | 3734 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d0710abb CW |
3735 | bool mappable, fenceable; |
3736 | u32 fence_size, fence_alignment; | |
3737 | ||
a9f1481f | 3738 | fence_size = i915_gem_get_ggtt_size(dev_priv, |
ad1a7d20 | 3739 | obj->base.size, |
3e510a8e | 3740 | i915_gem_object_get_tiling(obj)); |
a9f1481f | 3741 | fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, |
ad1a7d20 | 3742 | obj->base.size, |
3e510a8e | 3743 | i915_gem_object_get_tiling(obj), |
ad1a7d20 | 3744 | true); |
d0710abb CW |
3745 | |
3746 | fenceable = (vma->node.size == fence_size && | |
3747 | (vma->node.start & (fence_alignment - 1)) == 0); | |
3748 | ||
3749 | mappable = (vma->node.start + fence_size <= | |
a9f1481f | 3750 | dev_priv->ggtt.mappable_end); |
d0710abb CW |
3751 | |
3752 | obj->map_and_fenceable = mappable && fenceable; | |
3753 | } | |
3754 | ||
305bc234 CW |
3755 | int __i915_vma_do_pin(struct i915_vma *vma, |
3756 | u64 size, u64 alignment, u64 flags) | |
673a394b | 3757 | { |
305bc234 | 3758 | unsigned int bound = vma->flags; |
673a394b EA |
3759 | int ret; |
3760 | ||
59bfa124 | 3761 | GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0); |
3272db53 | 3762 | GEM_BUG_ON((flags & PIN_GLOBAL) && !i915_vma_is_ggtt(vma)); |
d7f46fc4 | 3763 | |
305bc234 CW |
3764 | if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) { |
3765 | ret = -EBUSY; | |
3766 | goto err; | |
3767 | } | |
ac0c6b5a | 3768 | |
de895082 | 3769 | if ((bound & I915_VMA_BIND_MASK) == 0) { |
59bfa124 CW |
3770 | ret = i915_vma_insert(vma, size, alignment, flags); |
3771 | if (ret) | |
3772 | goto err; | |
fe14d5f4 | 3773 | } |
74898d7e | 3774 | |
59bfa124 | 3775 | ret = i915_vma_bind(vma, vma->obj->cache_level, flags); |
3b16525c | 3776 | if (ret) |
59bfa124 | 3777 | goto err; |
3b16525c | 3778 | |
3272db53 | 3779 | if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND) |
d0710abb | 3780 | __i915_vma_set_map_and_fenceable(vma); |
ef79e17c | 3781 | |
3b16525c | 3782 | GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags)); |
673a394b | 3783 | return 0; |
673a394b | 3784 | |
59bfa124 CW |
3785 | err: |
3786 | __i915_vma_unpin(vma); | |
3787 | return ret; | |
ec7adb6e JL |
3788 | } |
3789 | ||
058d88c4 | 3790 | struct i915_vma * |
ec7adb6e JL |
3791 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3792 | const struct i915_ggtt_view *view, | |
91b2db6f | 3793 | u64 size, |
2ffffd0f CW |
3794 | u64 alignment, |
3795 | u64 flags) | |
ec7adb6e | 3796 | { |
058d88c4 | 3797 | struct i915_address_space *vm = &to_i915(obj->base.dev)->ggtt.base; |
59bfa124 CW |
3798 | struct i915_vma *vma; |
3799 | int ret; | |
72e96d64 | 3800 | |
058d88c4 | 3801 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view); |
59bfa124 | 3802 | if (IS_ERR(vma)) |
058d88c4 | 3803 | return vma; |
59bfa124 CW |
3804 | |
3805 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3806 | if (flags & PIN_NONBLOCK && | |
3807 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 3808 | return ERR_PTR(-ENOSPC); |
59bfa124 CW |
3809 | |
3810 | WARN(i915_vma_is_pinned(vma), | |
3811 | "bo is already pinned in ggtt with incorrect alignment:" | |
bde13ebd | 3812 | " offset=%08x, req.alignment=%llx, req.map_and_fenceable=%d," |
59bfa124 | 3813 | " obj->map_and_fenceable=%d\n", |
bde13ebd | 3814 | i915_ggtt_offset(vma), |
59bfa124 CW |
3815 | alignment, |
3816 | !!(flags & PIN_MAPPABLE), | |
3817 | obj->map_and_fenceable); | |
3818 | ret = i915_vma_unbind(vma); | |
3819 | if (ret) | |
058d88c4 | 3820 | return ERR_PTR(ret); |
59bfa124 CW |
3821 | } |
3822 | ||
058d88c4 CW |
3823 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
3824 | if (ret) | |
3825 | return ERR_PTR(ret); | |
ec7adb6e | 3826 | |
058d88c4 | 3827 | return vma; |
673a394b EA |
3828 | } |
3829 | ||
edf6b76f | 3830 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
3831 | { |
3832 | /* Note that we could alias engines in the execbuf API, but | |
3833 | * that would be very unwise as it prevents userspace from | |
3834 | * fine control over engine selection. Ahem. | |
3835 | * | |
3836 | * This should be something like EXEC_MAX_ENGINE instead of | |
3837 | * I915_NUM_ENGINES. | |
3838 | */ | |
3839 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3840 | return 0x10000 << id; | |
3841 | } | |
3842 | ||
3843 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3844 | { | |
70cb472c CW |
3845 | /* The uABI guarantees an active writer is also amongst the read |
3846 | * engines. This would be true if we accessed the activity tracking | |
3847 | * under the lock, but as we perform the lookup of the object and | |
3848 | * its activity locklessly we can not guarantee that the last_write | |
3849 | * being active implies that we have set the same engine flag from | |
3850 | * last_read - hence we always set both read and write busy for | |
3851 | * last_write. | |
3852 | */ | |
3853 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
3854 | } |
3855 | ||
edf6b76f | 3856 | static __always_inline unsigned int |
3fdc13c7 CW |
3857 | __busy_set_if_active(const struct i915_gem_active *active, |
3858 | unsigned int (*flag)(unsigned int id)) | |
3859 | { | |
1255501d | 3860 | struct drm_i915_gem_request *request; |
3fdc13c7 | 3861 | |
1255501d CW |
3862 | request = rcu_dereference(active->request); |
3863 | if (!request || i915_gem_request_completed(request)) | |
3864 | return 0; | |
3fdc13c7 | 3865 | |
1255501d CW |
3866 | /* This is racy. See __i915_gem_active_get_rcu() for an in detail |
3867 | * discussion of how to handle the race correctly, but for reporting | |
3868 | * the busy state we err on the side of potentially reporting the | |
3869 | * wrong engine as being busy (but we guarantee that the result | |
3870 | * is at least self-consistent). | |
3871 | * | |
3872 | * As we use SLAB_DESTROY_BY_RCU, the request may be reallocated | |
3873 | * whilst we are inspecting it, even under the RCU read lock as we are. | |
3874 | * This means that there is a small window for the engine and/or the | |
3875 | * seqno to have been overwritten. The seqno will always be in the | |
3876 | * future compared to the intended, and so we know that if that | |
3877 | * seqno is idle (on whatever engine) our request is idle and the | |
3878 | * return 0 above is correct. | |
3879 | * | |
3880 | * The issue is that if the engine is switched, it is just as likely | |
3881 | * to report that it is busy (but since the switch happened, we know | |
3882 | * the request should be idle). So there is a small chance that a busy | |
3883 | * result is actually the wrong engine. | |
3884 | * | |
3885 | * So why don't we care? | |
3886 | * | |
3887 | * For starters, the busy ioctl is a heuristic that is by definition | |
3888 | * racy. Even with perfect serialisation in the driver, the hardware | |
3889 | * state is constantly advancing - the state we report to the user | |
3890 | * is stale. | |
3891 | * | |
3892 | * The critical information for the busy-ioctl is whether the object | |
3893 | * is idle as userspace relies on that to detect whether its next | |
3894 | * access will stall, or if it has missed submitting commands to | |
3895 | * the hardware allowing the GPU to stall. We never generate a | |
3896 | * false-positive for idleness, thus busy-ioctl is reliable at the | |
3897 | * most fundamental level, and we maintain the guarantee that a | |
3898 | * busy object left to itself will eventually become idle (and stay | |
3899 | * idle!). | |
3900 | * | |
3901 | * We allow ourselves the leeway of potentially misreporting the busy | |
3902 | * state because that is an optimisation heuristic that is constantly | |
3903 | * in flux. Being quickly able to detect the busy/idle state is much | |
3904 | * more important than accurate logging of exactly which engines were | |
3905 | * busy. | |
3906 | * | |
3907 | * For accuracy in reporting the engine, we could use | |
3908 | * | |
3909 | * result = 0; | |
3910 | * request = __i915_gem_active_get_rcu(active); | |
3911 | * if (request) { | |
3912 | * if (!i915_gem_request_completed(request)) | |
3913 | * result = flag(request->engine->exec_id); | |
3914 | * i915_gem_request_put(request); | |
3915 | * } | |
3916 | * | |
3917 | * but that still remains susceptible to both hardware and userspace | |
3918 | * races. So we accept making the result of that race slightly worse, | |
3919 | * given the rarity of the race and its low impact on the result. | |
3920 | */ | |
3921 | return flag(READ_ONCE(request->engine->exec_id)); | |
3fdc13c7 CW |
3922 | } |
3923 | ||
edf6b76f | 3924 | static __always_inline unsigned int |
3fdc13c7 CW |
3925 | busy_check_reader(const struct i915_gem_active *active) |
3926 | { | |
3927 | return __busy_set_if_active(active, __busy_read_flag); | |
3928 | } | |
3929 | ||
edf6b76f | 3930 | static __always_inline unsigned int |
3fdc13c7 CW |
3931 | busy_check_writer(const struct i915_gem_active *active) |
3932 | { | |
3933 | return __busy_set_if_active(active, __busy_write_id); | |
3934 | } | |
3935 | ||
673a394b EA |
3936 | int |
3937 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3938 | struct drm_file *file) |
673a394b EA |
3939 | { |
3940 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3941 | struct drm_i915_gem_object *obj; |
3fdc13c7 | 3942 | unsigned long active; |
673a394b | 3943 | |
03ac0642 | 3944 | obj = i915_gem_object_lookup(file, args->handle); |
3fdc13c7 CW |
3945 | if (!obj) |
3946 | return -ENOENT; | |
d1b851fc | 3947 | |
426960be | 3948 | args->busy = 0; |
3fdc13c7 CW |
3949 | active = __I915_BO_ACTIVE(obj); |
3950 | if (active) { | |
3951 | int idx; | |
426960be | 3952 | |
3fdc13c7 CW |
3953 | /* Yes, the lookups are intentionally racy. |
3954 | * | |
3955 | * First, we cannot simply rely on __I915_BO_ACTIVE. We have | |
3956 | * to regard the value as stale and as our ABI guarantees | |
3957 | * forward progress, we confirm the status of each active | |
3958 | * request with the hardware. | |
3959 | * | |
3960 | * Even though we guard the pointer lookup by RCU, that only | |
3961 | * guarantees that the pointer and its contents remain | |
3962 | * dereferencable and does *not* mean that the request we | |
3963 | * have is the same as the one being tracked by the object. | |
3964 | * | |
3965 | * Consider that we lookup the request just as it is being | |
3966 | * retired and freed. We take a local copy of the pointer, | |
3967 | * but before we add its engine into the busy set, the other | |
3968 | * thread reallocates it and assigns it to a task on another | |
1255501d CW |
3969 | * engine with a fresh and incomplete seqno. Guarding against |
3970 | * that requires careful serialisation and reference counting, | |
3971 | * i.e. using __i915_gem_active_get_request_rcu(). We don't, | |
3972 | * instead we expect that if the result is busy, which engines | |
3973 | * are busy is not completely reliable - we only guarantee | |
3974 | * that the object was busy. | |
3fdc13c7 CW |
3975 | */ |
3976 | rcu_read_lock(); | |
3977 | ||
3978 | for_each_active(active, idx) | |
3979 | args->busy |= busy_check_reader(&obj->last_read[idx]); | |
3980 | ||
3981 | /* For ABI sanity, we only care that the write engine is in | |
70cb472c CW |
3982 | * the set of read engines. This should be ensured by the |
3983 | * ordering of setting last_read/last_write in | |
3984 | * i915_vma_move_to_active(), and then in reverse in retire. | |
3985 | * However, for good measure, we always report the last_write | |
3986 | * request as a busy read as well as being a busy write. | |
3fdc13c7 CW |
3987 | * |
3988 | * We don't care that the set of active read/write engines | |
3989 | * may change during construction of the result, as it is | |
3990 | * equally liable to change before userspace can inspect | |
3991 | * the result. | |
3992 | */ | |
3993 | args->busy |= busy_check_writer(&obj->last_write); | |
3994 | ||
3995 | rcu_read_unlock(); | |
426960be | 3996 | } |
673a394b | 3997 | |
3fdc13c7 CW |
3998 | i915_gem_object_put_unlocked(obj); |
3999 | return 0; | |
673a394b EA |
4000 | } |
4001 | ||
4002 | int | |
4003 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4004 | struct drm_file *file_priv) | |
4005 | { | |
0206e353 | 4006 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4007 | } |
4008 | ||
3ef94daa CW |
4009 | int |
4010 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4011 | struct drm_file *file_priv) | |
4012 | { | |
fac5e23e | 4013 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4014 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4015 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4016 | int ret; |
3ef94daa CW |
4017 | |
4018 | switch (args->madv) { | |
4019 | case I915_MADV_DONTNEED: | |
4020 | case I915_MADV_WILLNEED: | |
4021 | break; | |
4022 | default: | |
4023 | return -EINVAL; | |
4024 | } | |
4025 | ||
1d7cfea1 CW |
4026 | ret = i915_mutex_lock_interruptible(dev); |
4027 | if (ret) | |
4028 | return ret; | |
4029 | ||
03ac0642 CW |
4030 | obj = i915_gem_object_lookup(file_priv, args->handle); |
4031 | if (!obj) { | |
1d7cfea1 CW |
4032 | ret = -ENOENT; |
4033 | goto unlock; | |
3ef94daa | 4034 | } |
3ef94daa | 4035 | |
656bfa3a | 4036 | if (obj->pages && |
3e510a8e | 4037 | i915_gem_object_is_tiled(obj) && |
656bfa3a DV |
4038 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
4039 | if (obj->madv == I915_MADV_WILLNEED) | |
4040 | i915_gem_object_unpin_pages(obj); | |
4041 | if (args->madv == I915_MADV_WILLNEED) | |
4042 | i915_gem_object_pin_pages(obj); | |
4043 | } | |
4044 | ||
05394f39 CW |
4045 | if (obj->madv != __I915_MADV_PURGED) |
4046 | obj->madv = args->madv; | |
3ef94daa | 4047 | |
6c085a72 | 4048 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4049 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4050 | i915_gem_object_truncate(obj); |
4051 | ||
05394f39 | 4052 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4053 | |
f8c417cd | 4054 | i915_gem_object_put(obj); |
1d7cfea1 | 4055 | unlock: |
3ef94daa | 4056 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4057 | return ret; |
3ef94daa CW |
4058 | } |
4059 | ||
37e680a1 CW |
4060 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4061 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4062 | { |
b4716185 CW |
4063 | int i; |
4064 | ||
35c20a60 | 4065 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 4066 | for (i = 0; i < I915_NUM_ENGINES; i++) |
fa545cbf CW |
4067 | init_request_active(&obj->last_read[i], |
4068 | i915_gem_object_retire__read); | |
4069 | init_request_active(&obj->last_write, | |
4070 | i915_gem_object_retire__write); | |
4071 | init_request_active(&obj->last_fence, NULL); | |
b25cb2f8 | 4072 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4073 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4074 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4075 | |
37e680a1 CW |
4076 | obj->ops = ops; |
4077 | ||
0327d6ba CW |
4078 | obj->fence_reg = I915_FENCE_REG_NONE; |
4079 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba | 4080 | |
f19ec8cb | 4081 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4082 | } |
4083 | ||
37e680a1 | 4084 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 4085 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
4086 | .get_pages = i915_gem_object_get_pages_gtt, |
4087 | .put_pages = i915_gem_object_put_pages_gtt, | |
4088 | }; | |
4089 | ||
d37cd8a8 | 4090 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 4091 | size_t size) |
ac52bc56 | 4092 | { |
c397b908 | 4093 | struct drm_i915_gem_object *obj; |
5949eac4 | 4094 | struct address_space *mapping; |
1a240d4d | 4095 | gfp_t mask; |
fe3db79b | 4096 | int ret; |
ac52bc56 | 4097 | |
42dcedd4 | 4098 | obj = i915_gem_object_alloc(dev); |
c397b908 | 4099 | if (obj == NULL) |
fe3db79b | 4100 | return ERR_PTR(-ENOMEM); |
673a394b | 4101 | |
fe3db79b CW |
4102 | ret = drm_gem_object_init(dev, &obj->base, size); |
4103 | if (ret) | |
4104 | goto fail; | |
673a394b | 4105 | |
bed1ea95 CW |
4106 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4107 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4108 | /* 965gm cannot relocate objects above 4GiB. */ | |
4109 | mask &= ~__GFP_HIGHMEM; | |
4110 | mask |= __GFP_DMA32; | |
4111 | } | |
4112 | ||
93c76a3d | 4113 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4114 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4115 | |
37e680a1 | 4116 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4117 | |
c397b908 DV |
4118 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4119 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4120 | |
3d29b842 ED |
4121 | if (HAS_LLC(dev)) { |
4122 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4123 | * cache) for about a 10% performance improvement |
4124 | * compared to uncached. Graphics requests other than | |
4125 | * display scanout are coherent with the CPU in | |
4126 | * accessing this cache. This means in this mode we | |
4127 | * don't need to clflush on the CPU side, and on the | |
4128 | * GPU side we only need to flush internal caches to | |
4129 | * get data visible to the CPU. | |
4130 | * | |
4131 | * However, we maintain the display planes as UC, and so | |
4132 | * need to rebind when first used as such. | |
4133 | */ | |
4134 | obj->cache_level = I915_CACHE_LLC; | |
4135 | } else | |
4136 | obj->cache_level = I915_CACHE_NONE; | |
4137 | ||
d861e338 DV |
4138 | trace_i915_gem_object_create(obj); |
4139 | ||
05394f39 | 4140 | return obj; |
fe3db79b CW |
4141 | |
4142 | fail: | |
4143 | i915_gem_object_free(obj); | |
4144 | ||
4145 | return ERR_PTR(ret); | |
c397b908 DV |
4146 | } |
4147 | ||
340fbd8c CW |
4148 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4149 | { | |
4150 | /* If we are the last user of the backing storage (be it shmemfs | |
4151 | * pages or stolen etc), we know that the pages are going to be | |
4152 | * immediately released. In this case, we can then skip copying | |
4153 | * back the contents from the GPU. | |
4154 | */ | |
4155 | ||
4156 | if (obj->madv != I915_MADV_WILLNEED) | |
4157 | return false; | |
4158 | ||
4159 | if (obj->base.filp == NULL) | |
4160 | return true; | |
4161 | ||
4162 | /* At first glance, this looks racy, but then again so would be | |
4163 | * userspace racing mmap against close. However, the first external | |
4164 | * reference to the filp can only be obtained through the | |
4165 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4166 | * acquiring such a reference whilst we are in the middle of | |
4167 | * freeing the object. | |
4168 | */ | |
4169 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4170 | } | |
4171 | ||
1488fc08 | 4172 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4173 | { |
1488fc08 | 4174 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4175 | struct drm_device *dev = obj->base.dev; |
fac5e23e | 4176 | struct drm_i915_private *dev_priv = to_i915(dev); |
07fe0b12 | 4177 | struct i915_vma *vma, *next; |
673a394b | 4178 | |
f65c9168 PZ |
4179 | intel_runtime_pm_get(dev_priv); |
4180 | ||
26e12f89 CW |
4181 | trace_i915_gem_object_destroy(obj); |
4182 | ||
b1f788c6 CW |
4183 | /* All file-owned VMA should have been released by this point through |
4184 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4185 | * However, the object may also be bound into the global GTT (e.g. | |
4186 | * older GPUs without per-process support, or for direct access through | |
4187 | * the GTT either for the user or for scanout). Those VMA still need to | |
4188 | * unbound now. | |
4189 | */ | |
1c7f4bca | 4190 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
3272db53 | 4191 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); |
b1f788c6 | 4192 | GEM_BUG_ON(i915_vma_is_active(vma)); |
3272db53 | 4193 | vma->flags &= ~I915_VMA_PIN_MASK; |
b1f788c6 | 4194 | i915_vma_close(vma); |
1488fc08 | 4195 | } |
15717de2 | 4196 | GEM_BUG_ON(obj->bind_count); |
1488fc08 | 4197 | |
1d64ae71 BW |
4198 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4199 | * before progressing. */ | |
4200 | if (obj->stolen) | |
4201 | i915_gem_object_unpin_pages(obj); | |
4202 | ||
faf5bf0a | 4203 | WARN_ON(atomic_read(&obj->frontbuffer_bits)); |
a071fa00 | 4204 | |
656bfa3a DV |
4205 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4206 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
3e510a8e | 4207 | i915_gem_object_is_tiled(obj)) |
656bfa3a DV |
4208 | i915_gem_object_unpin_pages(obj); |
4209 | ||
401c29f6 BW |
4210 | if (WARN_ON(obj->pages_pin_count)) |
4211 | obj->pages_pin_count = 0; | |
340fbd8c | 4212 | if (discard_backing_storage(obj)) |
5537252b | 4213 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4214 | i915_gem_object_put_pages(obj); |
de151cf6 | 4215 | |
9da3da66 CW |
4216 | BUG_ON(obj->pages); |
4217 | ||
2f745ad3 CW |
4218 | if (obj->base.import_attach) |
4219 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4220 | |
5cc9ed4b CW |
4221 | if (obj->ops->release) |
4222 | obj->ops->release(obj); | |
4223 | ||
05394f39 CW |
4224 | drm_gem_object_release(&obj->base); |
4225 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4226 | |
05394f39 | 4227 | kfree(obj->bit_17); |
42dcedd4 | 4228 | i915_gem_object_free(obj); |
f65c9168 PZ |
4229 | |
4230 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4231 | } |
4232 | ||
dcff85c8 | 4233 | int i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4234 | { |
fac5e23e | 4235 | struct drm_i915_private *dev_priv = to_i915(dev); |
dcff85c8 | 4236 | int ret; |
28dfe52a | 4237 | |
54b4f68f CW |
4238 | intel_suspend_gt_powersave(dev_priv); |
4239 | ||
45c5f202 | 4240 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4241 | |
4242 | /* We have to flush all the executing contexts to main memory so | |
4243 | * that they can saved in the hibernation image. To ensure the last | |
4244 | * context image is coherent, we have to switch away from it. That | |
4245 | * leaves the dev_priv->kernel_context still active when | |
4246 | * we actually suspend, and its image in memory may not match the GPU | |
4247 | * state. Fortunately, the kernel_context is disposable and we do | |
4248 | * not rely on its state. | |
4249 | */ | |
4250 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4251 | if (ret) | |
4252 | goto err; | |
4253 | ||
dcff85c8 | 4254 | ret = i915_gem_wait_for_idle(dev_priv, true); |
f7403347 | 4255 | if (ret) |
45c5f202 | 4256 | goto err; |
f7403347 | 4257 | |
c033666a | 4258 | i915_gem_retire_requests(dev_priv); |
673a394b | 4259 | |
b2e862d0 | 4260 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4261 | mutex_unlock(&dev->struct_mutex); |
4262 | ||
737b1506 | 4263 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4264 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4265 | flush_delayed_work(&dev_priv->gt.idle_work); | |
29105ccc | 4266 | |
bdcf120b CW |
4267 | /* Assert that we sucessfully flushed all the work and |
4268 | * reset the GPU back to its idle, low power state. | |
4269 | */ | |
67d97da3 | 4270 | WARN_ON(dev_priv->gt.awake); |
bdcf120b | 4271 | |
673a394b | 4272 | return 0; |
45c5f202 CW |
4273 | |
4274 | err: | |
4275 | mutex_unlock(&dev->struct_mutex); | |
4276 | return ret; | |
673a394b EA |
4277 | } |
4278 | ||
5ab57c70 CW |
4279 | void i915_gem_resume(struct drm_device *dev) |
4280 | { | |
4281 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4282 | ||
4283 | mutex_lock(&dev->struct_mutex); | |
4284 | i915_gem_restore_gtt_mappings(dev); | |
4285 | ||
4286 | /* As we didn't flush the kernel context before suspend, we cannot | |
4287 | * guarantee that the context image is complete. So let's just reset | |
4288 | * it and start again. | |
4289 | */ | |
4290 | if (i915.enable_execlists) | |
4291 | intel_lr_context_reset(dev_priv, dev_priv->kernel_context); | |
4292 | ||
4293 | mutex_unlock(&dev->struct_mutex); | |
4294 | } | |
4295 | ||
f691e2f4 DV |
4296 | void i915_gem_init_swizzling(struct drm_device *dev) |
4297 | { | |
fac5e23e | 4298 | struct drm_i915_private *dev_priv = to_i915(dev); |
f691e2f4 | 4299 | |
11782b02 | 4300 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4301 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4302 | return; | |
4303 | ||
4304 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4305 | DISP_TILE_SURFACE_SWIZZLING); | |
4306 | ||
11782b02 DV |
4307 | if (IS_GEN5(dev)) |
4308 | return; | |
4309 | ||
f691e2f4 DV |
4310 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4311 | if (IS_GEN6(dev)) | |
6b26c86d | 4312 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4313 | else if (IS_GEN7(dev)) |
6b26c86d | 4314 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4315 | else if (IS_GEN8(dev)) |
4316 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4317 | else |
4318 | BUG(); | |
f691e2f4 | 4319 | } |
e21af88d | 4320 | |
81e7f200 VS |
4321 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4322 | { | |
fac5e23e | 4323 | struct drm_i915_private *dev_priv = to_i915(dev); |
81e7f200 VS |
4324 | |
4325 | I915_WRITE(RING_CTL(base), 0); | |
4326 | I915_WRITE(RING_HEAD(base), 0); | |
4327 | I915_WRITE(RING_TAIL(base), 0); | |
4328 | I915_WRITE(RING_START(base), 0); | |
4329 | } | |
4330 | ||
4331 | static void init_unused_rings(struct drm_device *dev) | |
4332 | { | |
4333 | if (IS_I830(dev)) { | |
4334 | init_unused_ring(dev, PRB1_BASE); | |
4335 | init_unused_ring(dev, SRB0_BASE); | |
4336 | init_unused_ring(dev, SRB1_BASE); | |
4337 | init_unused_ring(dev, SRB2_BASE); | |
4338 | init_unused_ring(dev, SRB3_BASE); | |
4339 | } else if (IS_GEN2(dev)) { | |
4340 | init_unused_ring(dev, SRB0_BASE); | |
4341 | init_unused_ring(dev, SRB1_BASE); | |
4342 | } else if (IS_GEN3(dev)) { | |
4343 | init_unused_ring(dev, PRB1_BASE); | |
4344 | init_unused_ring(dev, PRB2_BASE); | |
4345 | } | |
4346 | } | |
4347 | ||
4fc7c971 BW |
4348 | int |
4349 | i915_gem_init_hw(struct drm_device *dev) | |
4350 | { | |
fac5e23e | 4351 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4352 | struct intel_engine_cs *engine; |
d200cda6 | 4353 | int ret; |
4fc7c971 | 4354 | |
5e4f5189 CW |
4355 | /* Double layer security blanket, see i915_gem_init() */ |
4356 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4357 | ||
3accaf7e | 4358 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4359 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4360 | |
0bf21347 VS |
4361 | if (IS_HASWELL(dev)) |
4362 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4363 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4364 | |
88a2b2a3 | 4365 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4366 | if (IS_IVYBRIDGE(dev)) { |
4367 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4368 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4369 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4370 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4371 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4372 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4373 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4374 | } | |
88a2b2a3 BW |
4375 | } |
4376 | ||
4fc7c971 BW |
4377 | i915_gem_init_swizzling(dev); |
4378 | ||
d5abdfda DV |
4379 | /* |
4380 | * At least 830 can leave some of the unused rings | |
4381 | * "active" (ie. head != tail) after resume which | |
4382 | * will prevent c3 entry. Makes sure all unused rings | |
4383 | * are totally idle. | |
4384 | */ | |
4385 | init_unused_rings(dev); | |
4386 | ||
ed54c1a1 | 4387 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4388 | |
4ad2fd88 JH |
4389 | ret = i915_ppgtt_init_hw(dev); |
4390 | if (ret) { | |
4391 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4392 | goto out; | |
4393 | } | |
4394 | ||
4395 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4396 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4397 | ret = engine->init_hw(engine); |
35a57ffb | 4398 | if (ret) |
5e4f5189 | 4399 | goto out; |
35a57ffb | 4400 | } |
99433931 | 4401 | |
0ccdacf6 PA |
4402 | intel_mocs_init_l3cc_table(dev); |
4403 | ||
33a732f4 | 4404 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
4405 | ret = intel_guc_setup(dev); |
4406 | if (ret) | |
4407 | goto out; | |
33a732f4 | 4408 | |
5e4f5189 CW |
4409 | out: |
4410 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4411 | return ret; |
8187a2b7 ZN |
4412 | } |
4413 | ||
39df9190 CW |
4414 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4415 | { | |
4416 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4417 | return false; | |
4418 | ||
4419 | /* TODO: make semaphores and Execlists play nicely together */ | |
4420 | if (i915.enable_execlists) | |
4421 | return false; | |
4422 | ||
4423 | if (value >= 0) | |
4424 | return value; | |
4425 | ||
4426 | #ifdef CONFIG_INTEL_IOMMU | |
4427 | /* Enable semaphores on SNB when IO remapping is off */ | |
4428 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4429 | return false; | |
4430 | #endif | |
4431 | ||
4432 | return true; | |
4433 | } | |
4434 | ||
1070a42b CW |
4435 | int i915_gem_init(struct drm_device *dev) |
4436 | { | |
fac5e23e | 4437 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
4438 | int ret; |
4439 | ||
1070a42b | 4440 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4441 | |
a83014d3 | 4442 | if (!i915.enable_execlists) { |
7e37f889 | 4443 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4444 | } else { |
117897f4 | 4445 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4446 | } |
4447 | ||
5e4f5189 CW |
4448 | /* This is just a security blanket to placate dragons. |
4449 | * On some systems, we very sporadically observe that the first TLBs | |
4450 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4451 | * we hold the forcewake during initialisation these problems | |
4452 | * just magically go away. | |
4453 | */ | |
4454 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4455 | ||
72778cb2 | 4456 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4457 | |
4458 | ret = i915_gem_init_ggtt(dev_priv); | |
4459 | if (ret) | |
4460 | goto out_unlock; | |
d62b4892 | 4461 | |
2fa48d8d | 4462 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4463 | if (ret) |
4464 | goto out_unlock; | |
2fa48d8d | 4465 | |
8b3e2d36 | 4466 | ret = intel_engines_init(dev); |
35a57ffb | 4467 | if (ret) |
7bcc3777 | 4468 | goto out_unlock; |
2fa48d8d | 4469 | |
1070a42b | 4470 | ret = i915_gem_init_hw(dev); |
60990320 | 4471 | if (ret == -EIO) { |
7e21d648 | 4472 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4473 | * wedged. But we only want to do this where the GPU is angry, |
4474 | * for all other failure, such as an allocation failure, bail. | |
4475 | */ | |
4476 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 4477 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 4478 | ret = 0; |
1070a42b | 4479 | } |
7bcc3777 JN |
4480 | |
4481 | out_unlock: | |
5e4f5189 | 4482 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4483 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4484 | |
60990320 | 4485 | return ret; |
1070a42b CW |
4486 | } |
4487 | ||
8187a2b7 | 4488 | void |
117897f4 | 4489 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4490 | { |
fac5e23e | 4491 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4492 | struct intel_engine_cs *engine; |
8187a2b7 | 4493 | |
b4ac5afc | 4494 | for_each_engine(engine, dev_priv) |
117897f4 | 4495 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4496 | } |
4497 | ||
64193406 | 4498 | static void |
666796da | 4499 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 4500 | { |
0bc40be8 | 4501 | INIT_LIST_HEAD(&engine->request_list); |
64193406 CW |
4502 | } |
4503 | ||
40ae4e16 ID |
4504 | void |
4505 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4506 | { | |
91c8a326 | 4507 | struct drm_device *dev = &dev_priv->drm; |
40ae4e16 ID |
4508 | |
4509 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4510 | !IS_CHERRYVIEW(dev_priv)) | |
4511 | dev_priv->num_fence_regs = 32; | |
4512 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4513 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4514 | dev_priv->num_fence_regs = 16; | |
4515 | else | |
4516 | dev_priv->num_fence_regs = 8; | |
4517 | ||
c033666a | 4518 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4519 | dev_priv->num_fence_regs = |
4520 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4521 | ||
4522 | /* Initialize fence registers to zero */ | |
4523 | i915_gem_restore_fences(dev); | |
4524 | ||
4525 | i915_gem_detect_bit_6_swizzle(dev); | |
4526 | } | |
4527 | ||
673a394b | 4528 | void |
d64aa096 | 4529 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 4530 | { |
fac5e23e | 4531 | struct drm_i915_private *dev_priv = to_i915(dev); |
42dcedd4 CW |
4532 | int i; |
4533 | ||
efab6d8d | 4534 | dev_priv->objects = |
42dcedd4 CW |
4535 | kmem_cache_create("i915_gem_object", |
4536 | sizeof(struct drm_i915_gem_object), 0, | |
4537 | SLAB_HWCACHE_ALIGN, | |
4538 | NULL); | |
e20d2ab7 CW |
4539 | dev_priv->vmas = |
4540 | kmem_cache_create("i915_gem_vma", | |
4541 | sizeof(struct i915_vma), 0, | |
4542 | SLAB_HWCACHE_ALIGN, | |
4543 | NULL); | |
efab6d8d CW |
4544 | dev_priv->requests = |
4545 | kmem_cache_create("i915_gem_request", | |
4546 | sizeof(struct drm_i915_gem_request), 0, | |
0eafec6d CW |
4547 | SLAB_HWCACHE_ALIGN | |
4548 | SLAB_RECLAIM_ACCOUNT | | |
4549 | SLAB_DESTROY_BY_RCU, | |
efab6d8d | 4550 | NULL); |
673a394b | 4551 | |
a33afea5 | 4552 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4553 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4554 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4555 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
4556 | for (i = 0; i < I915_NUM_ENGINES; i++) |
4557 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 4558 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4559 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
67d97da3 | 4560 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4561 | i915_gem_retire_work_handler); |
67d97da3 | 4562 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4563 | i915_gem_idle_work_handler); |
1f15b76f | 4564 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4565 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4566 | |
72bfa19c CW |
4567 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4568 | ||
19b2dbde | 4569 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 4570 | |
6b95a207 | 4571 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4572 | |
ce453d81 CW |
4573 | dev_priv->mm.interruptible = true; |
4574 | ||
b5add959 | 4575 | spin_lock_init(&dev_priv->fb_tracking.lock); |
673a394b | 4576 | } |
71acb5eb | 4577 | |
d64aa096 ID |
4578 | void i915_gem_load_cleanup(struct drm_device *dev) |
4579 | { | |
4580 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4581 | ||
4582 | kmem_cache_destroy(dev_priv->requests); | |
4583 | kmem_cache_destroy(dev_priv->vmas); | |
4584 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4585 | |
4586 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4587 | rcu_barrier(); | |
d64aa096 ID |
4588 | } |
4589 | ||
461fb99c CW |
4590 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4591 | { | |
4592 | struct drm_i915_gem_object *obj; | |
4593 | ||
4594 | /* Called just before we write the hibernation image. | |
4595 | * | |
4596 | * We need to update the domain tracking to reflect that the CPU | |
4597 | * will be accessing all the pages to create and restore from the | |
4598 | * hibernation, and so upon restoration those pages will be in the | |
4599 | * CPU domain. | |
4600 | * | |
4601 | * To make sure the hibernation image contains the latest state, | |
4602 | * we update that state just before writing out the image. | |
4603 | */ | |
4604 | ||
4605 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
4606 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4607 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4608 | } | |
4609 | ||
4610 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4611 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4612 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4613 | } | |
4614 | ||
4615 | return 0; | |
4616 | } | |
4617 | ||
f787a5f5 | 4618 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4619 | { |
f787a5f5 | 4620 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4621 | struct drm_i915_gem_request *request; |
b962442e EA |
4622 | |
4623 | /* Clean up our request list when the client is going away, so that | |
4624 | * later retire_requests won't dereference our soon-to-be-gone | |
4625 | * file_priv. | |
4626 | */ | |
1c25595f | 4627 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4628 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4629 | request->file_priv = NULL; |
1c25595f | 4630 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4631 | |
2e1b8730 | 4632 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4633 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4634 | list_del(&file_priv->rps.link); |
8d3afd7d | 4635 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4636 | } |
b29c19b6 CW |
4637 | } |
4638 | ||
4639 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4640 | { | |
4641 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4642 | int ret; |
b29c19b6 CW |
4643 | |
4644 | DRM_DEBUG_DRIVER("\n"); | |
4645 | ||
4646 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4647 | if (!file_priv) | |
4648 | return -ENOMEM; | |
4649 | ||
4650 | file->driver_priv = file_priv; | |
f19ec8cb | 4651 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4652 | file_priv->file = file; |
2e1b8730 | 4653 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4654 | |
4655 | spin_lock_init(&file_priv->mm.lock); | |
4656 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4657 | |
c80ff16e | 4658 | file_priv->bsd_engine = -1; |
de1add36 | 4659 | |
e422b888 BW |
4660 | ret = i915_gem_context_open(dev, file); |
4661 | if (ret) | |
4662 | kfree(file_priv); | |
b29c19b6 | 4663 | |
e422b888 | 4664 | return ret; |
b29c19b6 CW |
4665 | } |
4666 | ||
b680c37a DV |
4667 | /** |
4668 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4669 | * @old: current GEM buffer for the frontbuffer slots |
4670 | * @new: new GEM buffer for the frontbuffer slots | |
4671 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4672 | * |
4673 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4674 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4675 | */ | |
a071fa00 DV |
4676 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4677 | struct drm_i915_gem_object *new, | |
4678 | unsigned frontbuffer_bits) | |
4679 | { | |
faf5bf0a CW |
4680 | /* Control of individual bits within the mask are guarded by |
4681 | * the owning plane->mutex, i.e. we can never see concurrent | |
4682 | * manipulation of individual bits. But since the bitfield as a whole | |
4683 | * is updated using RMW, we need to use atomics in order to update | |
4684 | * the bits. | |
4685 | */ | |
4686 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4687 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4688 | ||
a071fa00 | 4689 | if (old) { |
faf5bf0a CW |
4690 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4691 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4692 | } |
4693 | ||
4694 | if (new) { | |
faf5bf0a CW |
4695 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4696 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4697 | } |
4698 | } | |
4699 | ||
033908ae DG |
4700 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
4701 | struct page * | |
4702 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
4703 | { | |
4704 | struct page *page; | |
4705 | ||
4706 | /* Only default objects have per-page dirty tracking */ | |
b9bcd14a | 4707 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
033908ae DG |
4708 | return NULL; |
4709 | ||
4710 | page = i915_gem_object_get_page(obj, n); | |
4711 | set_page_dirty(page); | |
4712 | return page; | |
4713 | } | |
4714 | ||
ea70299d DG |
4715 | /* Allocate a new GEM object and fill it with the supplied data */ |
4716 | struct drm_i915_gem_object * | |
4717 | i915_gem_object_create_from_data(struct drm_device *dev, | |
4718 | const void *data, size_t size) | |
4719 | { | |
4720 | struct drm_i915_gem_object *obj; | |
4721 | struct sg_table *sg; | |
4722 | size_t bytes; | |
4723 | int ret; | |
4724 | ||
d37cd8a8 | 4725 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 4726 | if (IS_ERR(obj)) |
ea70299d DG |
4727 | return obj; |
4728 | ||
4729 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4730 | if (ret) | |
4731 | goto fail; | |
4732 | ||
4733 | ret = i915_gem_object_get_pages(obj); | |
4734 | if (ret) | |
4735 | goto fail; | |
4736 | ||
4737 | i915_gem_object_pin_pages(obj); | |
4738 | sg = obj->pages; | |
4739 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 4740 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
4741 | i915_gem_object_unpin_pages(obj); |
4742 | ||
4743 | if (WARN_ON(bytes != size)) { | |
4744 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4745 | ret = -EFAULT; | |
4746 | goto fail; | |
4747 | } | |
4748 | ||
4749 | return obj; | |
4750 | ||
4751 | fail: | |
f8c417cd | 4752 | i915_gem_object_put(obj); |
ea70299d DG |
4753 | return ERR_PTR(ret); |
4754 | } |