Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
42 | unsigned alignment, | |
86a1ee26 CW |
43 | bool map_and_fenceable, |
44 | bool nonblocking); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
6c085a72 CW |
58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 61 | |
61050808 CW |
62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
63 | { | |
64 | if (obj->tiling_mode) | |
65 | i915_gem_release_mmap(obj); | |
66 | ||
67 | /* As we do not have an associated fence register, we will force | |
68 | * a tiling change if we ever need to acquire one. | |
69 | */ | |
5d82e3e6 | 70 | obj->fence_dirty = false; |
61050808 CW |
71 | obj->fence_reg = I915_FENCE_REG_NONE; |
72 | } | |
73 | ||
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
c20e8355 | 78 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
79 | dev_priv->mm.object_count++; |
80 | dev_priv->mm.object_memory += size; | |
c20e8355 | 81 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
82 | } |
83 | ||
84 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
85 | size_t size) | |
86 | { | |
c20e8355 | 87 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
88 | dev_priv->mm.object_count--; |
89 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 90 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | } |
92 | ||
21dd3734 | 93 | static int |
33196ded | 94 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 95 | { |
30dbf0c0 CW |
96 | int ret; |
97 | ||
7abb690a DV |
98 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
99 | i915_terminally_wedged(error)) | |
1f83fee0 | 100 | if (EXIT_COND) |
30dbf0c0 CW |
101 | return 0; |
102 | ||
0a6759c6 DV |
103 | /* |
104 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
105 | * userspace. If it takes that long something really bad is going on and | |
106 | * we should simply try to bail out and fail as gracefully as possible. | |
107 | */ | |
1f83fee0 DV |
108 | ret = wait_event_interruptible_timeout(error->reset_queue, |
109 | EXIT_COND, | |
110 | 10*HZ); | |
0a6759c6 DV |
111 | if (ret == 0) { |
112 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
113 | return -EIO; | |
114 | } else if (ret < 0) { | |
30dbf0c0 | 115 | return ret; |
0a6759c6 | 116 | } |
1f83fee0 | 117 | #undef EXIT_COND |
30dbf0c0 | 118 | |
21dd3734 | 119 | return 0; |
30dbf0c0 CW |
120 | } |
121 | ||
54cf91dc | 122 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 123 | { |
33196ded | 124 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
125 | int ret; |
126 | ||
33196ded | 127 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
128 | if (ret) |
129 | return ret; | |
130 | ||
131 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
132 | if (ret) | |
133 | return ret; | |
134 | ||
23bc5982 | 135 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
136 | return 0; |
137 | } | |
30dbf0c0 | 138 | |
7d1c4804 | 139 | static inline bool |
05394f39 | 140 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 141 | { |
f343c5f6 | 142 | return i915_gem_obj_ggtt_bound(obj) && !obj->active; |
7d1c4804 CW |
143 | } |
144 | ||
79e53945 JB |
145 | int |
146 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 147 | struct drm_file *file) |
79e53945 | 148 | { |
93d18799 | 149 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 150 | struct drm_i915_gem_init *args = data; |
2021746e | 151 | |
7bb6fb8d DV |
152 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
153 | return -ENODEV; | |
154 | ||
2021746e CW |
155 | if (args->gtt_start >= args->gtt_end || |
156 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
157 | return -EINVAL; | |
79e53945 | 158 | |
f534bc0b DV |
159 | /* GEM with user mode setting was never supported on ilk and later. */ |
160 | if (INTEL_INFO(dev)->gen >= 5) | |
161 | return -ENODEV; | |
162 | ||
79e53945 | 163 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
164 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
165 | args->gtt_end); | |
93d18799 | 166 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
167 | mutex_unlock(&dev->struct_mutex); |
168 | ||
2021746e | 169 | return 0; |
673a394b EA |
170 | } |
171 | ||
5a125c3c EA |
172 | int |
173 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 174 | struct drm_file *file) |
5a125c3c | 175 | { |
73aa808f | 176 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 177 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
178 | struct drm_i915_gem_object *obj; |
179 | size_t pinned; | |
5a125c3c | 180 | |
6299f992 | 181 | pinned = 0; |
73aa808f | 182 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 183 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
1b50247a | 184 | if (obj->pin_count) |
f343c5f6 | 185 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 186 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 187 | |
853ba5d2 | 188 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 189 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 190 | |
5a125c3c EA |
191 | return 0; |
192 | } | |
193 | ||
42dcedd4 CW |
194 | void *i915_gem_object_alloc(struct drm_device *dev) |
195 | { | |
196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
197 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); | |
198 | } | |
199 | ||
200 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
201 | { | |
202 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
203 | kmem_cache_free(dev_priv->slab, obj); | |
204 | } | |
205 | ||
ff72145b DA |
206 | static int |
207 | i915_gem_create(struct drm_file *file, | |
208 | struct drm_device *dev, | |
209 | uint64_t size, | |
210 | uint32_t *handle_p) | |
673a394b | 211 | { |
05394f39 | 212 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
213 | int ret; |
214 | u32 handle; | |
673a394b | 215 | |
ff72145b | 216 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
217 | if (size == 0) |
218 | return -EINVAL; | |
673a394b EA |
219 | |
220 | /* Allocate the new object */ | |
ff72145b | 221 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
222 | if (obj == NULL) |
223 | return -ENOMEM; | |
224 | ||
05394f39 | 225 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 226 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
227 | drm_gem_object_unreference_unlocked(&obj->base); |
228 | if (ret) | |
229 | return ret; | |
202f2fef | 230 | |
ff72145b | 231 | *handle_p = handle; |
673a394b EA |
232 | return 0; |
233 | } | |
234 | ||
ff72145b DA |
235 | int |
236 | i915_gem_dumb_create(struct drm_file *file, | |
237 | struct drm_device *dev, | |
238 | struct drm_mode_create_dumb *args) | |
239 | { | |
240 | /* have to work out size/pitch and return them */ | |
ed0291fd | 241 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
242 | args->size = args->pitch * args->height; |
243 | return i915_gem_create(file, dev, | |
244 | args->size, &args->handle); | |
245 | } | |
246 | ||
247 | int i915_gem_dumb_destroy(struct drm_file *file, | |
248 | struct drm_device *dev, | |
249 | uint32_t handle) | |
250 | { | |
251 | return drm_gem_handle_delete(file, handle); | |
252 | } | |
253 | ||
254 | /** | |
255 | * Creates a new mm object and returns a handle to it. | |
256 | */ | |
257 | int | |
258 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
259 | struct drm_file *file) | |
260 | { | |
261 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 262 | |
ff72145b DA |
263 | return i915_gem_create(file, dev, |
264 | args->size, &args->handle); | |
265 | } | |
266 | ||
8461d226 DV |
267 | static inline int |
268 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
269 | const char *gpu_vaddr, int gpu_offset, | |
270 | int length) | |
271 | { | |
272 | int ret, cpu_offset = 0; | |
273 | ||
274 | while (length > 0) { | |
275 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
276 | int this_length = min(cacheline_end - gpu_offset, length); | |
277 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
278 | ||
279 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
280 | gpu_vaddr + swizzled_gpu_offset, | |
281 | this_length); | |
282 | if (ret) | |
283 | return ret + length; | |
284 | ||
285 | cpu_offset += this_length; | |
286 | gpu_offset += this_length; | |
287 | length -= this_length; | |
288 | } | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
8c59967c | 293 | static inline int |
4f0c7cfb BW |
294 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
295 | const char __user *cpu_vaddr, | |
8c59967c DV |
296 | int length) |
297 | { | |
298 | int ret, cpu_offset = 0; | |
299 | ||
300 | while (length > 0) { | |
301 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
302 | int this_length = min(cacheline_end - gpu_offset, length); | |
303 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
304 | ||
305 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
306 | cpu_vaddr + cpu_offset, | |
307 | this_length); | |
308 | if (ret) | |
309 | return ret + length; | |
310 | ||
311 | cpu_offset += this_length; | |
312 | gpu_offset += this_length; | |
313 | length -= this_length; | |
314 | } | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
d174bd64 DV |
319 | /* Per-page copy function for the shmem pread fastpath. |
320 | * Flushes invalid cachelines before reading the target if | |
321 | * needs_clflush is set. */ | |
eb01459f | 322 | static int |
d174bd64 DV |
323 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
324 | char __user *user_data, | |
325 | bool page_do_bit17_swizzling, bool needs_clflush) | |
326 | { | |
327 | char *vaddr; | |
328 | int ret; | |
329 | ||
e7e58eb5 | 330 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
331 | return -EINVAL; |
332 | ||
333 | vaddr = kmap_atomic(page); | |
334 | if (needs_clflush) | |
335 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
336 | page_length); | |
337 | ret = __copy_to_user_inatomic(user_data, | |
338 | vaddr + shmem_page_offset, | |
339 | page_length); | |
340 | kunmap_atomic(vaddr); | |
341 | ||
f60d7f0c | 342 | return ret ? -EFAULT : 0; |
d174bd64 DV |
343 | } |
344 | ||
23c18c71 DV |
345 | static void |
346 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
347 | bool swizzled) | |
348 | { | |
e7e58eb5 | 349 | if (unlikely(swizzled)) { |
23c18c71 DV |
350 | unsigned long start = (unsigned long) addr; |
351 | unsigned long end = (unsigned long) addr + length; | |
352 | ||
353 | /* For swizzling simply ensure that we always flush both | |
354 | * channels. Lame, but simple and it works. Swizzled | |
355 | * pwrite/pread is far from a hotpath - current userspace | |
356 | * doesn't use it at all. */ | |
357 | start = round_down(start, 128); | |
358 | end = round_up(end, 128); | |
359 | ||
360 | drm_clflush_virt_range((void *)start, end - start); | |
361 | } else { | |
362 | drm_clflush_virt_range(addr, length); | |
363 | } | |
364 | ||
365 | } | |
366 | ||
d174bd64 DV |
367 | /* Only difference to the fast-path function is that this can handle bit17 |
368 | * and uses non-atomic copy and kmap functions. */ | |
369 | static int | |
370 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
371 | char __user *user_data, | |
372 | bool page_do_bit17_swizzling, bool needs_clflush) | |
373 | { | |
374 | char *vaddr; | |
375 | int ret; | |
376 | ||
377 | vaddr = kmap(page); | |
378 | if (needs_clflush) | |
23c18c71 DV |
379 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
380 | page_length, | |
381 | page_do_bit17_swizzling); | |
d174bd64 DV |
382 | |
383 | if (page_do_bit17_swizzling) | |
384 | ret = __copy_to_user_swizzled(user_data, | |
385 | vaddr, shmem_page_offset, | |
386 | page_length); | |
387 | else | |
388 | ret = __copy_to_user(user_data, | |
389 | vaddr + shmem_page_offset, | |
390 | page_length); | |
391 | kunmap(page); | |
392 | ||
f60d7f0c | 393 | return ret ? - EFAULT : 0; |
d174bd64 DV |
394 | } |
395 | ||
eb01459f | 396 | static int |
dbf7bff0 DV |
397 | i915_gem_shmem_pread(struct drm_device *dev, |
398 | struct drm_i915_gem_object *obj, | |
399 | struct drm_i915_gem_pread *args, | |
400 | struct drm_file *file) | |
eb01459f | 401 | { |
8461d226 | 402 | char __user *user_data; |
eb01459f | 403 | ssize_t remain; |
8461d226 | 404 | loff_t offset; |
eb2c0c81 | 405 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 406 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 407 | int prefaulted = 0; |
8489731c | 408 | int needs_clflush = 0; |
67d5a50c | 409 | struct sg_page_iter sg_iter; |
eb01459f | 410 | |
2bb4629a | 411 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
412 | remain = args->size; |
413 | ||
8461d226 | 414 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 415 | |
8489731c DV |
416 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
417 | /* If we're not in the cpu read domain, set ourself into the gtt | |
418 | * read domain and manually flush cachelines (if required). This | |
419 | * optimizes for the case when the gpu will dirty the data | |
420 | * anyway again before the next pread happens. */ | |
421 | if (obj->cache_level == I915_CACHE_NONE) | |
422 | needs_clflush = 1; | |
f343c5f6 | 423 | if (i915_gem_obj_ggtt_bound(obj)) { |
6c085a72 CW |
424 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
425 | if (ret) | |
426 | return ret; | |
427 | } | |
8489731c | 428 | } |
eb01459f | 429 | |
f60d7f0c CW |
430 | ret = i915_gem_object_get_pages(obj); |
431 | if (ret) | |
432 | return ret; | |
433 | ||
434 | i915_gem_object_pin_pages(obj); | |
435 | ||
8461d226 | 436 | offset = args->offset; |
eb01459f | 437 | |
67d5a50c ID |
438 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
439 | offset >> PAGE_SHIFT) { | |
2db76d7c | 440 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
441 | |
442 | if (remain <= 0) | |
443 | break; | |
444 | ||
eb01459f EA |
445 | /* Operation in this page |
446 | * | |
eb01459f | 447 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
448 | * page_length = bytes to copy for this page |
449 | */ | |
c8cbbb8b | 450 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
451 | page_length = remain; |
452 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
453 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 454 | |
8461d226 DV |
455 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
456 | (page_to_phys(page) & (1 << 17)) != 0; | |
457 | ||
d174bd64 DV |
458 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
459 | user_data, page_do_bit17_swizzling, | |
460 | needs_clflush); | |
461 | if (ret == 0) | |
462 | goto next_page; | |
dbf7bff0 | 463 | |
dbf7bff0 DV |
464 | mutex_unlock(&dev->struct_mutex); |
465 | ||
0b74b508 | 466 | if (likely(!i915_prefault_disable) && !prefaulted) { |
f56f821f | 467 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
468 | /* Userspace is tricking us, but we've already clobbered |
469 | * its pages with the prefault and promised to write the | |
470 | * data up to the first fault. Hence ignore any errors | |
471 | * and just continue. */ | |
472 | (void)ret; | |
473 | prefaulted = 1; | |
474 | } | |
eb01459f | 475 | |
d174bd64 DV |
476 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
477 | user_data, page_do_bit17_swizzling, | |
478 | needs_clflush); | |
eb01459f | 479 | |
dbf7bff0 | 480 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 481 | |
dbf7bff0 | 482 | next_page: |
e5281ccd | 483 | mark_page_accessed(page); |
e5281ccd | 484 | |
f60d7f0c | 485 | if (ret) |
8461d226 | 486 | goto out; |
8461d226 | 487 | |
eb01459f | 488 | remain -= page_length; |
8461d226 | 489 | user_data += page_length; |
eb01459f EA |
490 | offset += page_length; |
491 | } | |
492 | ||
4f27b75d | 493 | out: |
f60d7f0c CW |
494 | i915_gem_object_unpin_pages(obj); |
495 | ||
eb01459f EA |
496 | return ret; |
497 | } | |
498 | ||
673a394b EA |
499 | /** |
500 | * Reads data from the object referenced by handle. | |
501 | * | |
502 | * On error, the contents of *data are undefined. | |
503 | */ | |
504 | int | |
505 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 506 | struct drm_file *file) |
673a394b EA |
507 | { |
508 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 509 | struct drm_i915_gem_object *obj; |
35b62a89 | 510 | int ret = 0; |
673a394b | 511 | |
51311d0a CW |
512 | if (args->size == 0) |
513 | return 0; | |
514 | ||
515 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 516 | to_user_ptr(args->data_ptr), |
51311d0a CW |
517 | args->size)) |
518 | return -EFAULT; | |
519 | ||
4f27b75d | 520 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 521 | if (ret) |
4f27b75d | 522 | return ret; |
673a394b | 523 | |
05394f39 | 524 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 525 | if (&obj->base == NULL) { |
1d7cfea1 CW |
526 | ret = -ENOENT; |
527 | goto unlock; | |
4f27b75d | 528 | } |
673a394b | 529 | |
7dcd2499 | 530 | /* Bounds check source. */ |
05394f39 CW |
531 | if (args->offset > obj->base.size || |
532 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 533 | ret = -EINVAL; |
35b62a89 | 534 | goto out; |
ce9d419d CW |
535 | } |
536 | ||
1286ff73 DV |
537 | /* prime objects have no backing filp to GEM pread/pwrite |
538 | * pages from. | |
539 | */ | |
540 | if (!obj->base.filp) { | |
541 | ret = -EINVAL; | |
542 | goto out; | |
543 | } | |
544 | ||
db53a302 CW |
545 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
546 | ||
dbf7bff0 | 547 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 548 | |
35b62a89 | 549 | out: |
05394f39 | 550 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 551 | unlock: |
4f27b75d | 552 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 553 | return ret; |
673a394b EA |
554 | } |
555 | ||
0839ccb8 KP |
556 | /* This is the fast write path which cannot handle |
557 | * page faults in the source data | |
9b7530cc | 558 | */ |
0839ccb8 KP |
559 | |
560 | static inline int | |
561 | fast_user_write(struct io_mapping *mapping, | |
562 | loff_t page_base, int page_offset, | |
563 | char __user *user_data, | |
564 | int length) | |
9b7530cc | 565 | { |
4f0c7cfb BW |
566 | void __iomem *vaddr_atomic; |
567 | void *vaddr; | |
0839ccb8 | 568 | unsigned long unwritten; |
9b7530cc | 569 | |
3e4d3af5 | 570 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
571 | /* We can use the cpu mem copy function because this is X86. */ |
572 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
573 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 574 | user_data, length); |
3e4d3af5 | 575 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 576 | return unwritten; |
0839ccb8 KP |
577 | } |
578 | ||
3de09aa3 EA |
579 | /** |
580 | * This is the fast pwrite path, where we copy the data directly from the | |
581 | * user into the GTT, uncached. | |
582 | */ | |
673a394b | 583 | static int |
05394f39 CW |
584 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
585 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 586 | struct drm_i915_gem_pwrite *args, |
05394f39 | 587 | struct drm_file *file) |
673a394b | 588 | { |
0839ccb8 | 589 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 590 | ssize_t remain; |
0839ccb8 | 591 | loff_t offset, page_base; |
673a394b | 592 | char __user *user_data; |
935aaa69 DV |
593 | int page_offset, page_length, ret; |
594 | ||
86a1ee26 | 595 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
596 | if (ret) |
597 | goto out; | |
598 | ||
599 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
600 | if (ret) | |
601 | goto out_unpin; | |
602 | ||
603 | ret = i915_gem_object_put_fence(obj); | |
604 | if (ret) | |
605 | goto out_unpin; | |
673a394b | 606 | |
2bb4629a | 607 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 608 | remain = args->size; |
673a394b | 609 | |
f343c5f6 | 610 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
611 | |
612 | while (remain > 0) { | |
613 | /* Operation in this page | |
614 | * | |
0839ccb8 KP |
615 | * page_base = page offset within aperture |
616 | * page_offset = offset within page | |
617 | * page_length = bytes to copy for this page | |
673a394b | 618 | */ |
c8cbbb8b CW |
619 | page_base = offset & PAGE_MASK; |
620 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
621 | page_length = remain; |
622 | if ((page_offset + remain) > PAGE_SIZE) | |
623 | page_length = PAGE_SIZE - page_offset; | |
624 | ||
0839ccb8 | 625 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
626 | * source page isn't available. Return the error and we'll |
627 | * retry in the slow path. | |
0839ccb8 | 628 | */ |
5d4545ae | 629 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
630 | page_offset, user_data, page_length)) { |
631 | ret = -EFAULT; | |
632 | goto out_unpin; | |
633 | } | |
673a394b | 634 | |
0839ccb8 KP |
635 | remain -= page_length; |
636 | user_data += page_length; | |
637 | offset += page_length; | |
673a394b | 638 | } |
673a394b | 639 | |
935aaa69 DV |
640 | out_unpin: |
641 | i915_gem_object_unpin(obj); | |
642 | out: | |
3de09aa3 | 643 | return ret; |
673a394b EA |
644 | } |
645 | ||
d174bd64 DV |
646 | /* Per-page copy function for the shmem pwrite fastpath. |
647 | * Flushes invalid cachelines before writing to the target if | |
648 | * needs_clflush_before is set and flushes out any written cachelines after | |
649 | * writing if needs_clflush is set. */ | |
3043c60c | 650 | static int |
d174bd64 DV |
651 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
652 | char __user *user_data, | |
653 | bool page_do_bit17_swizzling, | |
654 | bool needs_clflush_before, | |
655 | bool needs_clflush_after) | |
673a394b | 656 | { |
d174bd64 | 657 | char *vaddr; |
673a394b | 658 | int ret; |
3de09aa3 | 659 | |
e7e58eb5 | 660 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 661 | return -EINVAL; |
3de09aa3 | 662 | |
d174bd64 DV |
663 | vaddr = kmap_atomic(page); |
664 | if (needs_clflush_before) | |
665 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
666 | page_length); | |
667 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
668 | user_data, | |
669 | page_length); | |
670 | if (needs_clflush_after) | |
671 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
672 | page_length); | |
673 | kunmap_atomic(vaddr); | |
3de09aa3 | 674 | |
755d2218 | 675 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
676 | } |
677 | ||
d174bd64 DV |
678 | /* Only difference to the fast-path function is that this can handle bit17 |
679 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 680 | static int |
d174bd64 DV |
681 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
682 | char __user *user_data, | |
683 | bool page_do_bit17_swizzling, | |
684 | bool needs_clflush_before, | |
685 | bool needs_clflush_after) | |
673a394b | 686 | { |
d174bd64 DV |
687 | char *vaddr; |
688 | int ret; | |
e5281ccd | 689 | |
d174bd64 | 690 | vaddr = kmap(page); |
e7e58eb5 | 691 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
692 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
693 | page_length, | |
694 | page_do_bit17_swizzling); | |
d174bd64 DV |
695 | if (page_do_bit17_swizzling) |
696 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
697 | user_data, |
698 | page_length); | |
d174bd64 DV |
699 | else |
700 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
701 | user_data, | |
702 | page_length); | |
703 | if (needs_clflush_after) | |
23c18c71 DV |
704 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
705 | page_length, | |
706 | page_do_bit17_swizzling); | |
d174bd64 | 707 | kunmap(page); |
40123c1f | 708 | |
755d2218 | 709 | return ret ? -EFAULT : 0; |
40123c1f EA |
710 | } |
711 | ||
40123c1f | 712 | static int |
e244a443 DV |
713 | i915_gem_shmem_pwrite(struct drm_device *dev, |
714 | struct drm_i915_gem_object *obj, | |
715 | struct drm_i915_gem_pwrite *args, | |
716 | struct drm_file *file) | |
40123c1f | 717 | { |
40123c1f | 718 | ssize_t remain; |
8c59967c DV |
719 | loff_t offset; |
720 | char __user *user_data; | |
eb2c0c81 | 721 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 722 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 723 | int hit_slowpath = 0; |
58642885 DV |
724 | int needs_clflush_after = 0; |
725 | int needs_clflush_before = 0; | |
67d5a50c | 726 | struct sg_page_iter sg_iter; |
40123c1f | 727 | |
2bb4629a | 728 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
729 | remain = args->size; |
730 | ||
8c59967c | 731 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 732 | |
58642885 DV |
733 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
734 | /* If we're not in the cpu write domain, set ourself into the gtt | |
735 | * write domain and manually flush cachelines (if required). This | |
736 | * optimizes for the case when the gpu will use the data | |
737 | * right away and we therefore have to clflush anyway. */ | |
738 | if (obj->cache_level == I915_CACHE_NONE) | |
739 | needs_clflush_after = 1; | |
f343c5f6 | 740 | if (i915_gem_obj_ggtt_bound(obj)) { |
6c085a72 CW |
741 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
742 | if (ret) | |
743 | return ret; | |
744 | } | |
58642885 DV |
745 | } |
746 | /* Same trick applies for invalidate partially written cachelines before | |
747 | * writing. */ | |
748 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
749 | && obj->cache_level == I915_CACHE_NONE) | |
750 | needs_clflush_before = 1; | |
751 | ||
755d2218 CW |
752 | ret = i915_gem_object_get_pages(obj); |
753 | if (ret) | |
754 | return ret; | |
755 | ||
756 | i915_gem_object_pin_pages(obj); | |
757 | ||
673a394b | 758 | offset = args->offset; |
05394f39 | 759 | obj->dirty = 1; |
673a394b | 760 | |
67d5a50c ID |
761 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
762 | offset >> PAGE_SHIFT) { | |
2db76d7c | 763 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 764 | int partial_cacheline_write; |
e5281ccd | 765 | |
9da3da66 CW |
766 | if (remain <= 0) |
767 | break; | |
768 | ||
40123c1f EA |
769 | /* Operation in this page |
770 | * | |
40123c1f | 771 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
772 | * page_length = bytes to copy for this page |
773 | */ | |
c8cbbb8b | 774 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
775 | |
776 | page_length = remain; | |
777 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
778 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 779 | |
58642885 DV |
780 | /* If we don't overwrite a cacheline completely we need to be |
781 | * careful to have up-to-date data by first clflushing. Don't | |
782 | * overcomplicate things and flush the entire patch. */ | |
783 | partial_cacheline_write = needs_clflush_before && | |
784 | ((shmem_page_offset | page_length) | |
785 | & (boot_cpu_data.x86_clflush_size - 1)); | |
786 | ||
8c59967c DV |
787 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
788 | (page_to_phys(page) & (1 << 17)) != 0; | |
789 | ||
d174bd64 DV |
790 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
791 | user_data, page_do_bit17_swizzling, | |
792 | partial_cacheline_write, | |
793 | needs_clflush_after); | |
794 | if (ret == 0) | |
795 | goto next_page; | |
e244a443 DV |
796 | |
797 | hit_slowpath = 1; | |
e244a443 | 798 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
799 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
800 | user_data, page_do_bit17_swizzling, | |
801 | partial_cacheline_write, | |
802 | needs_clflush_after); | |
40123c1f | 803 | |
e244a443 | 804 | mutex_lock(&dev->struct_mutex); |
755d2218 | 805 | |
e244a443 | 806 | next_page: |
e5281ccd CW |
807 | set_page_dirty(page); |
808 | mark_page_accessed(page); | |
e5281ccd | 809 | |
755d2218 | 810 | if (ret) |
8c59967c | 811 | goto out; |
8c59967c | 812 | |
40123c1f | 813 | remain -= page_length; |
8c59967c | 814 | user_data += page_length; |
40123c1f | 815 | offset += page_length; |
673a394b EA |
816 | } |
817 | ||
fbd5a26d | 818 | out: |
755d2218 CW |
819 | i915_gem_object_unpin_pages(obj); |
820 | ||
e244a443 | 821 | if (hit_slowpath) { |
8dcf015e DV |
822 | /* |
823 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
824 | * cachelines in-line while writing and the object moved | |
825 | * out of the cpu write domain while we've dropped the lock. | |
826 | */ | |
827 | if (!needs_clflush_after && | |
828 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
e244a443 | 829 | i915_gem_clflush_object(obj); |
e76e9aeb | 830 | i915_gem_chipset_flush(dev); |
e244a443 | 831 | } |
8c59967c | 832 | } |
673a394b | 833 | |
58642885 | 834 | if (needs_clflush_after) |
e76e9aeb | 835 | i915_gem_chipset_flush(dev); |
58642885 | 836 | |
40123c1f | 837 | return ret; |
673a394b EA |
838 | } |
839 | ||
840 | /** | |
841 | * Writes data to the object referenced by handle. | |
842 | * | |
843 | * On error, the contents of the buffer that were to be modified are undefined. | |
844 | */ | |
845 | int | |
846 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 847 | struct drm_file *file) |
673a394b EA |
848 | { |
849 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 850 | struct drm_i915_gem_object *obj; |
51311d0a CW |
851 | int ret; |
852 | ||
853 | if (args->size == 0) | |
854 | return 0; | |
855 | ||
856 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 857 | to_user_ptr(args->data_ptr), |
51311d0a CW |
858 | args->size)) |
859 | return -EFAULT; | |
860 | ||
0b74b508 XZ |
861 | if (likely(!i915_prefault_disable)) { |
862 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), | |
863 | args->size); | |
864 | if (ret) | |
865 | return -EFAULT; | |
866 | } | |
673a394b | 867 | |
fbd5a26d | 868 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 869 | if (ret) |
fbd5a26d | 870 | return ret; |
1d7cfea1 | 871 | |
05394f39 | 872 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 873 | if (&obj->base == NULL) { |
1d7cfea1 CW |
874 | ret = -ENOENT; |
875 | goto unlock; | |
fbd5a26d | 876 | } |
673a394b | 877 | |
7dcd2499 | 878 | /* Bounds check destination. */ |
05394f39 CW |
879 | if (args->offset > obj->base.size || |
880 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 881 | ret = -EINVAL; |
35b62a89 | 882 | goto out; |
ce9d419d CW |
883 | } |
884 | ||
1286ff73 DV |
885 | /* prime objects have no backing filp to GEM pread/pwrite |
886 | * pages from. | |
887 | */ | |
888 | if (!obj->base.filp) { | |
889 | ret = -EINVAL; | |
890 | goto out; | |
891 | } | |
892 | ||
db53a302 CW |
893 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
894 | ||
935aaa69 | 895 | ret = -EFAULT; |
673a394b EA |
896 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
897 | * it would end up going through the fenced access, and we'll get | |
898 | * different detiling behavior between reading and writing. | |
899 | * pread/pwrite currently are reading and writing from the CPU | |
900 | * perspective, requiring manual detiling by the client. | |
901 | */ | |
5c0480f2 | 902 | if (obj->phys_obj) { |
fbd5a26d | 903 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
904 | goto out; |
905 | } | |
906 | ||
86a1ee26 | 907 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 908 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 909 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 910 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
911 | /* Note that the gtt paths might fail with non-page-backed user |
912 | * pointers (e.g. gtt mappings when moving data between | |
913 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 914 | } |
673a394b | 915 | |
86a1ee26 | 916 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 917 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 918 | |
35b62a89 | 919 | out: |
05394f39 | 920 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 921 | unlock: |
fbd5a26d | 922 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
923 | return ret; |
924 | } | |
925 | ||
b361237b | 926 | int |
33196ded | 927 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
928 | bool interruptible) |
929 | { | |
1f83fee0 | 930 | if (i915_reset_in_progress(error)) { |
b361237b CW |
931 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
932 | * -EIO unconditionally for these. */ | |
933 | if (!interruptible) | |
934 | return -EIO; | |
935 | ||
1f83fee0 DV |
936 | /* Recovery complete, but the reset failed ... */ |
937 | if (i915_terminally_wedged(error)) | |
b361237b CW |
938 | return -EIO; |
939 | ||
940 | return -EAGAIN; | |
941 | } | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
946 | /* | |
947 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
948 | * equal. | |
949 | */ | |
950 | static int | |
951 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
952 | { | |
953 | int ret; | |
954 | ||
955 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
956 | ||
957 | ret = 0; | |
958 | if (seqno == ring->outstanding_lazy_request) | |
0025c077 | 959 | ret = i915_add_request(ring, NULL); |
b361237b CW |
960 | |
961 | return ret; | |
962 | } | |
963 | ||
964 | /** | |
965 | * __wait_seqno - wait until execution of seqno has finished | |
966 | * @ring: the ring expected to report seqno | |
967 | * @seqno: duh! | |
f69061be | 968 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
969 | * @interruptible: do an interruptible wait (normally yes) |
970 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
971 | * | |
f69061be DV |
972 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
973 | * values have been read by the caller in an smp safe manner. Where read-side | |
974 | * locks are involved, it is sufficient to read the reset_counter before | |
975 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
976 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
977 | * inserted. | |
978 | * | |
b361237b CW |
979 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
980 | * errno with remaining time filled in timeout argument. | |
981 | */ | |
982 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 983 | unsigned reset_counter, |
b361237b CW |
984 | bool interruptible, struct timespec *timeout) |
985 | { | |
986 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
987 | struct timespec before, now, wait_time={1,0}; | |
988 | unsigned long timeout_jiffies; | |
989 | long end; | |
990 | bool wait_forever = true; | |
991 | int ret; | |
992 | ||
993 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
994 | return 0; | |
995 | ||
996 | trace_i915_gem_request_wait_begin(ring, seqno); | |
997 | ||
998 | if (timeout != NULL) { | |
999 | wait_time = *timeout; | |
1000 | wait_forever = false; | |
1001 | } | |
1002 | ||
e054cc39 | 1003 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
b361237b CW |
1004 | |
1005 | if (WARN_ON(!ring->irq_get(ring))) | |
1006 | return -ENODEV; | |
1007 | ||
1008 | /* Record current time in case interrupted by signal, or wedged * */ | |
1009 | getrawmonotonic(&before); | |
1010 | ||
1011 | #define EXIT_COND \ | |
1012 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
f69061be DV |
1013 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1014 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
b361237b CW |
1015 | do { |
1016 | if (interruptible) | |
1017 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1018 | EXIT_COND, | |
1019 | timeout_jiffies); | |
1020 | else | |
1021 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1022 | timeout_jiffies); | |
1023 | ||
f69061be DV |
1024 | /* We need to check whether any gpu reset happened in between |
1025 | * the caller grabbing the seqno and now ... */ | |
1026 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
1027 | end = -EAGAIN; | |
1028 | ||
1029 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely | |
1030 | * gone. */ | |
33196ded | 1031 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1032 | if (ret) |
1033 | end = ret; | |
1034 | } while (end == 0 && wait_forever); | |
1035 | ||
1036 | getrawmonotonic(&now); | |
1037 | ||
1038 | ring->irq_put(ring); | |
1039 | trace_i915_gem_request_wait_end(ring, seqno); | |
1040 | #undef EXIT_COND | |
1041 | ||
1042 | if (timeout) { | |
1043 | struct timespec sleep_time = timespec_sub(now, before); | |
1044 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1045 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1046 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1047 | } |
1048 | ||
1049 | switch (end) { | |
1050 | case -EIO: | |
1051 | case -EAGAIN: /* Wedged */ | |
1052 | case -ERESTARTSYS: /* Signal */ | |
1053 | return (int)end; | |
1054 | case 0: /* Timeout */ | |
b361237b CW |
1055 | return -ETIME; |
1056 | default: /* Completed */ | |
1057 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1058 | return 0; | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | /** | |
1063 | * Waits for a sequence number to be signaled, and cleans up the | |
1064 | * request and object lists appropriately for that event. | |
1065 | */ | |
1066 | int | |
1067 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1068 | { | |
1069 | struct drm_device *dev = ring->dev; | |
1070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1071 | bool interruptible = dev_priv->mm.interruptible; | |
1072 | int ret; | |
1073 | ||
1074 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1075 | BUG_ON(seqno == 0); | |
1076 | ||
33196ded | 1077 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1078 | if (ret) |
1079 | return ret; | |
1080 | ||
1081 | ret = i915_gem_check_olr(ring, seqno); | |
1082 | if (ret) | |
1083 | return ret; | |
1084 | ||
f69061be DV |
1085 | return __wait_seqno(ring, seqno, |
1086 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
1087 | interruptible, NULL); | |
b361237b CW |
1088 | } |
1089 | ||
d26e3af8 CW |
1090 | static int |
1091 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1092 | struct intel_ring_buffer *ring) | |
1093 | { | |
1094 | i915_gem_retire_requests_ring(ring); | |
1095 | ||
1096 | /* Manually manage the write flush as we may have not yet | |
1097 | * retired the buffer. | |
1098 | * | |
1099 | * Note that the last_write_seqno is always the earlier of | |
1100 | * the two (read/write) seqno, so if we haved successfully waited, | |
1101 | * we know we have passed the last write. | |
1102 | */ | |
1103 | obj->last_write_seqno = 0; | |
1104 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
b361237b CW |
1109 | /** |
1110 | * Ensures that all rendering to the object has completed and the object is | |
1111 | * safe to unbind from the GTT or access from the CPU. | |
1112 | */ | |
1113 | static __must_check int | |
1114 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1115 | bool readonly) | |
1116 | { | |
1117 | struct intel_ring_buffer *ring = obj->ring; | |
1118 | u32 seqno; | |
1119 | int ret; | |
1120 | ||
1121 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1122 | if (seqno == 0) | |
1123 | return 0; | |
1124 | ||
1125 | ret = i915_wait_seqno(ring, seqno); | |
1126 | if (ret) | |
1127 | return ret; | |
1128 | ||
d26e3af8 | 1129 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1130 | } |
1131 | ||
3236f57a CW |
1132 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1133 | * as the object state may change during this call. | |
1134 | */ | |
1135 | static __must_check int | |
1136 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1137 | bool readonly) | |
1138 | { | |
1139 | struct drm_device *dev = obj->base.dev; | |
1140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1141 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1142 | unsigned reset_counter; |
3236f57a CW |
1143 | u32 seqno; |
1144 | int ret; | |
1145 | ||
1146 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1147 | BUG_ON(!dev_priv->mm.interruptible); | |
1148 | ||
1149 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1150 | if (seqno == 0) | |
1151 | return 0; | |
1152 | ||
33196ded | 1153 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1154 | if (ret) |
1155 | return ret; | |
1156 | ||
1157 | ret = i915_gem_check_olr(ring, seqno); | |
1158 | if (ret) | |
1159 | return ret; | |
1160 | ||
f69061be | 1161 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1162 | mutex_unlock(&dev->struct_mutex); |
f69061be | 1163 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3236f57a | 1164 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1165 | if (ret) |
1166 | return ret; | |
3236f57a | 1167 | |
d26e3af8 | 1168 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1169 | } |
1170 | ||
673a394b | 1171 | /** |
2ef7eeaa EA |
1172 | * Called when user space prepares to use an object with the CPU, either |
1173 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1174 | */ |
1175 | int | |
1176 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1177 | struct drm_file *file) |
673a394b EA |
1178 | { |
1179 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1180 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1181 | uint32_t read_domains = args->read_domains; |
1182 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1183 | int ret; |
1184 | ||
2ef7eeaa | 1185 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1186 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1187 | return -EINVAL; |
1188 | ||
21d509e3 | 1189 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1190 | return -EINVAL; |
1191 | ||
1192 | /* Having something in the write domain implies it's in the read | |
1193 | * domain, and only that read domain. Enforce that in the request. | |
1194 | */ | |
1195 | if (write_domain != 0 && read_domains != write_domain) | |
1196 | return -EINVAL; | |
1197 | ||
76c1dec1 | 1198 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1199 | if (ret) |
76c1dec1 | 1200 | return ret; |
1d7cfea1 | 1201 | |
05394f39 | 1202 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1203 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1204 | ret = -ENOENT; |
1205 | goto unlock; | |
76c1dec1 | 1206 | } |
673a394b | 1207 | |
3236f57a CW |
1208 | /* Try to flush the object off the GPU without holding the lock. |
1209 | * We will repeat the flush holding the lock in the normal manner | |
1210 | * to catch cases where we are gazumped. | |
1211 | */ | |
1212 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1213 | if (ret) | |
1214 | goto unref; | |
1215 | ||
2ef7eeaa EA |
1216 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1217 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1218 | |
1219 | /* Silently promote "you're not bound, there was nothing to do" | |
1220 | * to success, since the client was just asking us to | |
1221 | * make sure everything was done. | |
1222 | */ | |
1223 | if (ret == -EINVAL) | |
1224 | ret = 0; | |
2ef7eeaa | 1225 | } else { |
e47c68e9 | 1226 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1227 | } |
1228 | ||
3236f57a | 1229 | unref: |
05394f39 | 1230 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1231 | unlock: |
673a394b EA |
1232 | mutex_unlock(&dev->struct_mutex); |
1233 | return ret; | |
1234 | } | |
1235 | ||
1236 | /** | |
1237 | * Called when user space has done writes to this buffer | |
1238 | */ | |
1239 | int | |
1240 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1241 | struct drm_file *file) |
673a394b EA |
1242 | { |
1243 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1244 | struct drm_i915_gem_object *obj; |
673a394b EA |
1245 | int ret = 0; |
1246 | ||
76c1dec1 | 1247 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1248 | if (ret) |
76c1dec1 | 1249 | return ret; |
1d7cfea1 | 1250 | |
05394f39 | 1251 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1252 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1253 | ret = -ENOENT; |
1254 | goto unlock; | |
673a394b EA |
1255 | } |
1256 | ||
673a394b | 1257 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1258 | if (obj->pin_count) |
e47c68e9 EA |
1259 | i915_gem_object_flush_cpu_write_domain(obj); |
1260 | ||
05394f39 | 1261 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1262 | unlock: |
673a394b EA |
1263 | mutex_unlock(&dev->struct_mutex); |
1264 | return ret; | |
1265 | } | |
1266 | ||
1267 | /** | |
1268 | * Maps the contents of an object, returning the address it is mapped | |
1269 | * into. | |
1270 | * | |
1271 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1272 | * imply a ref on the object itself. | |
1273 | */ | |
1274 | int | |
1275 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1276 | struct drm_file *file) |
673a394b EA |
1277 | { |
1278 | struct drm_i915_gem_mmap *args = data; | |
1279 | struct drm_gem_object *obj; | |
673a394b EA |
1280 | unsigned long addr; |
1281 | ||
05394f39 | 1282 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1283 | if (obj == NULL) |
bf79cb91 | 1284 | return -ENOENT; |
673a394b | 1285 | |
1286ff73 DV |
1286 | /* prime objects have no backing filp to GEM mmap |
1287 | * pages from. | |
1288 | */ | |
1289 | if (!obj->filp) { | |
1290 | drm_gem_object_unreference_unlocked(obj); | |
1291 | return -EINVAL; | |
1292 | } | |
1293 | ||
6be5ceb0 | 1294 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1295 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1296 | args->offset); | |
bc9025bd | 1297 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1298 | if (IS_ERR((void *)addr)) |
1299 | return addr; | |
1300 | ||
1301 | args->addr_ptr = (uint64_t) addr; | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
de151cf6 JB |
1306 | /** |
1307 | * i915_gem_fault - fault a page into the GTT | |
1308 | * vma: VMA in question | |
1309 | * vmf: fault info | |
1310 | * | |
1311 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1312 | * from userspace. The fault handler takes care of binding the object to | |
1313 | * the GTT (if needed), allocating and programming a fence register (again, | |
1314 | * only if needed based on whether the old reg is still valid or the object | |
1315 | * is tiled) and inserting a new PTE into the faulting process. | |
1316 | * | |
1317 | * Note that the faulting process may involve evicting existing objects | |
1318 | * from the GTT and/or fence registers to make room. So performance may | |
1319 | * suffer if the GTT working set is large or there are few fence registers | |
1320 | * left. | |
1321 | */ | |
1322 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1323 | { | |
05394f39 CW |
1324 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1325 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1326 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1327 | pgoff_t page_offset; |
1328 | unsigned long pfn; | |
1329 | int ret = 0; | |
0f973f27 | 1330 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1331 | |
1332 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1333 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1334 | PAGE_SHIFT; | |
1335 | ||
d9bc7e9f CW |
1336 | ret = i915_mutex_lock_interruptible(dev); |
1337 | if (ret) | |
1338 | goto out; | |
a00b10c3 | 1339 | |
db53a302 CW |
1340 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1341 | ||
eb119bd6 CW |
1342 | /* Access to snoopable pages through the GTT is incoherent. */ |
1343 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1344 | ret = -EINVAL; | |
1345 | goto unlock; | |
1346 | } | |
1347 | ||
d9bc7e9f | 1348 | /* Now bind it into the GTT if needed */ |
c9839303 CW |
1349 | ret = i915_gem_object_pin(obj, 0, true, false); |
1350 | if (ret) | |
1351 | goto unlock; | |
4a684a41 | 1352 | |
c9839303 CW |
1353 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1354 | if (ret) | |
1355 | goto unpin; | |
74898d7e | 1356 | |
06d98131 | 1357 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1358 | if (ret) |
c9839303 | 1359 | goto unpin; |
7d1c4804 | 1360 | |
6299f992 CW |
1361 | obj->fault_mappable = true; |
1362 | ||
f343c5f6 BW |
1363 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1364 | pfn >>= PAGE_SHIFT; | |
1365 | pfn += page_offset; | |
de151cf6 JB |
1366 | |
1367 | /* Finally, remap it using the new GTT offset */ | |
1368 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1369 | unpin: |
1370 | i915_gem_object_unpin(obj); | |
c715089f | 1371 | unlock: |
de151cf6 | 1372 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1373 | out: |
de151cf6 | 1374 | switch (ret) { |
d9bc7e9f | 1375 | case -EIO: |
a9340cca DV |
1376 | /* If this -EIO is due to a gpu hang, give the reset code a |
1377 | * chance to clean up the mess. Otherwise return the proper | |
1378 | * SIGBUS. */ | |
1f83fee0 | 1379 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1380 | return VM_FAULT_SIGBUS; |
045e769a | 1381 | case -EAGAIN: |
d9bc7e9f CW |
1382 | /* Give the error handler a chance to run and move the |
1383 | * objects off the GPU active list. Next time we service the | |
1384 | * fault, we should be able to transition the page into the | |
1385 | * GTT without touching the GPU (and so avoid further | |
1386 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1387 | * with coherency, just lost writes. | |
1388 | */ | |
045e769a | 1389 | set_need_resched(); |
c715089f CW |
1390 | case 0: |
1391 | case -ERESTARTSYS: | |
bed636ab | 1392 | case -EINTR: |
e79e0fe3 DR |
1393 | case -EBUSY: |
1394 | /* | |
1395 | * EBUSY is ok: this just means that another thread | |
1396 | * already did the job. | |
1397 | */ | |
c715089f | 1398 | return VM_FAULT_NOPAGE; |
de151cf6 | 1399 | case -ENOMEM: |
de151cf6 | 1400 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1401 | case -ENOSPC: |
1402 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1403 | default: |
a7c2e1aa | 1404 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1405 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1406 | } |
1407 | } | |
1408 | ||
901782b2 CW |
1409 | /** |
1410 | * i915_gem_release_mmap - remove physical page mappings | |
1411 | * @obj: obj in question | |
1412 | * | |
af901ca1 | 1413 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1414 | * relinquish ownership of the pages back to the system. |
1415 | * | |
1416 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1417 | * object through the GTT and then lose the fence register due to | |
1418 | * resource pressure. Similarly if the object has been moved out of the | |
1419 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1420 | * mapping will then trigger a page fault on the next user access, allowing | |
1421 | * fixup by i915_gem_fault(). | |
1422 | */ | |
d05ca301 | 1423 | void |
05394f39 | 1424 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1425 | { |
6299f992 CW |
1426 | if (!obj->fault_mappable) |
1427 | return; | |
901782b2 | 1428 | |
f6e47884 CW |
1429 | if (obj->base.dev->dev_mapping) |
1430 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1431 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1432 | obj->base.size, 1); | |
fb7d516a | 1433 | |
6299f992 | 1434 | obj->fault_mappable = false; |
901782b2 CW |
1435 | } |
1436 | ||
0fa87796 | 1437 | uint32_t |
e28f8711 | 1438 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1439 | { |
e28f8711 | 1440 | uint32_t gtt_size; |
92b88aeb CW |
1441 | |
1442 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1443 | tiling_mode == I915_TILING_NONE) |
1444 | return size; | |
92b88aeb CW |
1445 | |
1446 | /* Previous chips need a power-of-two fence region when tiling */ | |
1447 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1448 | gtt_size = 1024*1024; |
92b88aeb | 1449 | else |
e28f8711 | 1450 | gtt_size = 512*1024; |
92b88aeb | 1451 | |
e28f8711 CW |
1452 | while (gtt_size < size) |
1453 | gtt_size <<= 1; | |
92b88aeb | 1454 | |
e28f8711 | 1455 | return gtt_size; |
92b88aeb CW |
1456 | } |
1457 | ||
de151cf6 JB |
1458 | /** |
1459 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1460 | * @obj: object to check | |
1461 | * | |
1462 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1463 | * potential fence register mapping. |
de151cf6 | 1464 | */ |
d865110c ID |
1465 | uint32_t |
1466 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1467 | int tiling_mode, bool fenced) | |
de151cf6 | 1468 | { |
de151cf6 JB |
1469 | /* |
1470 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1471 | * if a fence register is needed for the object. | |
1472 | */ | |
d865110c | 1473 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1474 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1475 | return 4096; |
1476 | ||
a00b10c3 CW |
1477 | /* |
1478 | * Previous chips need to be aligned to the size of the smallest | |
1479 | * fence register that can contain the object. | |
1480 | */ | |
e28f8711 | 1481 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1482 | } |
1483 | ||
d8cb5086 CW |
1484 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1485 | { | |
1486 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1487 | int ret; | |
1488 | ||
1489 | if (obj->base.map_list.map) | |
1490 | return 0; | |
1491 | ||
da494d7c DV |
1492 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1493 | ||
d8cb5086 CW |
1494 | ret = drm_gem_create_mmap_offset(&obj->base); |
1495 | if (ret != -ENOSPC) | |
da494d7c | 1496 | goto out; |
d8cb5086 CW |
1497 | |
1498 | /* Badly fragmented mmap space? The only way we can recover | |
1499 | * space is by destroying unwanted objects. We can't randomly release | |
1500 | * mmap_offsets as userspace expects them to be persistent for the | |
1501 | * lifetime of the objects. The closest we can is to release the | |
1502 | * offsets on purgeable objects by truncating it and marking it purged, | |
1503 | * which prevents userspace from ever using that object again. | |
1504 | */ | |
1505 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1506 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1507 | if (ret != -ENOSPC) | |
da494d7c | 1508 | goto out; |
d8cb5086 CW |
1509 | |
1510 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1511 | ret = drm_gem_create_mmap_offset(&obj->base); |
1512 | out: | |
1513 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1514 | ||
1515 | return ret; | |
d8cb5086 CW |
1516 | } |
1517 | ||
1518 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1519 | { | |
1520 | if (!obj->base.map_list.map) | |
1521 | return; | |
1522 | ||
1523 | drm_gem_free_mmap_offset(&obj->base); | |
1524 | } | |
1525 | ||
de151cf6 | 1526 | int |
ff72145b DA |
1527 | i915_gem_mmap_gtt(struct drm_file *file, |
1528 | struct drm_device *dev, | |
1529 | uint32_t handle, | |
1530 | uint64_t *offset) | |
de151cf6 | 1531 | { |
da761a6e | 1532 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1533 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1534 | int ret; |
1535 | ||
76c1dec1 | 1536 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1537 | if (ret) |
76c1dec1 | 1538 | return ret; |
de151cf6 | 1539 | |
ff72145b | 1540 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1541 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1542 | ret = -ENOENT; |
1543 | goto unlock; | |
1544 | } | |
de151cf6 | 1545 | |
5d4545ae | 1546 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1547 | ret = -E2BIG; |
ff56b0bc | 1548 | goto out; |
da761a6e CW |
1549 | } |
1550 | ||
05394f39 | 1551 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1552 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1553 | ret = -EINVAL; |
1554 | goto out; | |
ab18282d CW |
1555 | } |
1556 | ||
d8cb5086 CW |
1557 | ret = i915_gem_object_create_mmap_offset(obj); |
1558 | if (ret) | |
1559 | goto out; | |
de151cf6 | 1560 | |
ff72145b | 1561 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1562 | |
1d7cfea1 | 1563 | out: |
05394f39 | 1564 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1565 | unlock: |
de151cf6 | 1566 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1567 | return ret; |
de151cf6 JB |
1568 | } |
1569 | ||
ff72145b DA |
1570 | /** |
1571 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1572 | * @dev: DRM device | |
1573 | * @data: GTT mapping ioctl data | |
1574 | * @file: GEM object info | |
1575 | * | |
1576 | * Simply returns the fake offset to userspace so it can mmap it. | |
1577 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1578 | * up so we can get faults in the handler above. | |
1579 | * | |
1580 | * The fault handler will take care of binding the object into the GTT | |
1581 | * (since it may have been evicted to make room for something), allocating | |
1582 | * a fence register, and mapping the appropriate aperture address into | |
1583 | * userspace. | |
1584 | */ | |
1585 | int | |
1586 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1587 | struct drm_file *file) | |
1588 | { | |
1589 | struct drm_i915_gem_mmap_gtt *args = data; | |
1590 | ||
ff72145b DA |
1591 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1592 | } | |
1593 | ||
225067ee DV |
1594 | /* Immediately discard the backing storage */ |
1595 | static void | |
1596 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1597 | { |
e5281ccd | 1598 | struct inode *inode; |
e5281ccd | 1599 | |
4d6294bf | 1600 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1601 | |
4d6294bf CW |
1602 | if (obj->base.filp == NULL) |
1603 | return; | |
e5281ccd | 1604 | |
225067ee DV |
1605 | /* Our goal here is to return as much of the memory as |
1606 | * is possible back to the system as we are called from OOM. | |
1607 | * To do this we must instruct the shmfs to drop all of its | |
1608 | * backing pages, *now*. | |
1609 | */ | |
496ad9aa | 1610 | inode = file_inode(obj->base.filp); |
225067ee | 1611 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1612 | |
225067ee DV |
1613 | obj->madv = __I915_MADV_PURGED; |
1614 | } | |
e5281ccd | 1615 | |
225067ee DV |
1616 | static inline int |
1617 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1618 | { | |
1619 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1620 | } |
1621 | ||
5cdf5881 | 1622 | static void |
05394f39 | 1623 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1624 | { |
90797e6d ID |
1625 | struct sg_page_iter sg_iter; |
1626 | int ret; | |
1286ff73 | 1627 | |
05394f39 | 1628 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1629 | |
6c085a72 CW |
1630 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1631 | if (ret) { | |
1632 | /* In the event of a disaster, abandon all caches and | |
1633 | * hope for the best. | |
1634 | */ | |
1635 | WARN_ON(ret != -EIO); | |
1636 | i915_gem_clflush_object(obj); | |
1637 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1638 | } | |
1639 | ||
6dacfd2f | 1640 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1641 | i915_gem_object_save_bit_17_swizzle(obj); |
1642 | ||
05394f39 CW |
1643 | if (obj->madv == I915_MADV_DONTNEED) |
1644 | obj->dirty = 0; | |
3ef94daa | 1645 | |
90797e6d | 1646 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1647 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1648 | |
05394f39 | 1649 | if (obj->dirty) |
9da3da66 | 1650 | set_page_dirty(page); |
3ef94daa | 1651 | |
05394f39 | 1652 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1653 | mark_page_accessed(page); |
3ef94daa | 1654 | |
9da3da66 | 1655 | page_cache_release(page); |
3ef94daa | 1656 | } |
05394f39 | 1657 | obj->dirty = 0; |
673a394b | 1658 | |
9da3da66 CW |
1659 | sg_free_table(obj->pages); |
1660 | kfree(obj->pages); | |
37e680a1 | 1661 | } |
6c085a72 | 1662 | |
dd624afd | 1663 | int |
37e680a1 CW |
1664 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1665 | { | |
1666 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1667 | ||
2f745ad3 | 1668 | if (obj->pages == NULL) |
37e680a1 CW |
1669 | return 0; |
1670 | ||
f343c5f6 | 1671 | BUG_ON(i915_gem_obj_ggtt_bound(obj)); |
6c085a72 | 1672 | |
a5570178 CW |
1673 | if (obj->pages_pin_count) |
1674 | return -EBUSY; | |
1675 | ||
a2165e31 CW |
1676 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1677 | * array, hence protect them from being reaped by removing them from gtt | |
1678 | * lists early. */ | |
35c20a60 | 1679 | list_del(&obj->global_list); |
a2165e31 | 1680 | |
37e680a1 | 1681 | ops->put_pages(obj); |
05394f39 | 1682 | obj->pages = NULL; |
37e680a1 | 1683 | |
6c085a72 CW |
1684 | if (i915_gem_object_is_purgeable(obj)) |
1685 | i915_gem_object_truncate(obj); | |
1686 | ||
1687 | return 0; | |
1688 | } | |
1689 | ||
1690 | static long | |
93927ca5 DV |
1691 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1692 | bool purgeable_only) | |
6c085a72 CW |
1693 | { |
1694 | struct drm_i915_gem_object *obj, *next; | |
5cef07e1 | 1695 | struct i915_address_space *vm = &dev_priv->gtt.base; |
6c085a72 CW |
1696 | long count = 0; |
1697 | ||
1698 | list_for_each_entry_safe(obj, next, | |
1699 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1700 | global_list) { |
93927ca5 | 1701 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1702 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1703 | count += obj->base.size >> PAGE_SHIFT; |
1704 | if (count >= target) | |
1705 | return count; | |
1706 | } | |
1707 | } | |
1708 | ||
5cef07e1 | 1709 | list_for_each_entry_safe(obj, next, &vm->inactive_list, mm_list) { |
93927ca5 | 1710 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
6c085a72 | 1711 | i915_gem_object_unbind(obj) == 0 && |
37e680a1 | 1712 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1713 | count += obj->base.size >> PAGE_SHIFT; |
1714 | if (count >= target) | |
1715 | return count; | |
1716 | } | |
1717 | } | |
1718 | ||
1719 | return count; | |
1720 | } | |
1721 | ||
93927ca5 DV |
1722 | static long |
1723 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1724 | { | |
1725 | return __i915_gem_shrink(dev_priv, target, true); | |
1726 | } | |
1727 | ||
6c085a72 CW |
1728 | static void |
1729 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1730 | { | |
1731 | struct drm_i915_gem_object *obj, *next; | |
1732 | ||
1733 | i915_gem_evict_everything(dev_priv->dev); | |
1734 | ||
35c20a60 BW |
1735 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1736 | global_list) | |
37e680a1 | 1737 | i915_gem_object_put_pages(obj); |
225067ee DV |
1738 | } |
1739 | ||
37e680a1 | 1740 | static int |
6c085a72 | 1741 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1742 | { |
6c085a72 | 1743 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1744 | int page_count, i; |
1745 | struct address_space *mapping; | |
9da3da66 CW |
1746 | struct sg_table *st; |
1747 | struct scatterlist *sg; | |
90797e6d | 1748 | struct sg_page_iter sg_iter; |
e5281ccd | 1749 | struct page *page; |
90797e6d | 1750 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1751 | gfp_t gfp; |
e5281ccd | 1752 | |
6c085a72 CW |
1753 | /* Assert that the object is not currently in any GPU domain. As it |
1754 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1755 | * a GPU cache | |
1756 | */ | |
1757 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1758 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1759 | ||
9da3da66 CW |
1760 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1761 | if (st == NULL) | |
1762 | return -ENOMEM; | |
1763 | ||
05394f39 | 1764 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1765 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1766 | sg_free_table(st); | |
1767 | kfree(st); | |
e5281ccd | 1768 | return -ENOMEM; |
9da3da66 | 1769 | } |
e5281ccd | 1770 | |
9da3da66 CW |
1771 | /* Get the list of pages out of our struct file. They'll be pinned |
1772 | * at this point until we release them. | |
1773 | * | |
1774 | * Fail silently without starting the shrinker | |
1775 | */ | |
496ad9aa | 1776 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1777 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1778 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1779 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1780 | sg = st->sgl; |
1781 | st->nents = 0; | |
1782 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1783 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1784 | if (IS_ERR(page)) { | |
1785 | i915_gem_purge(dev_priv, page_count); | |
1786 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1787 | } | |
1788 | if (IS_ERR(page)) { | |
1789 | /* We've tried hard to allocate the memory by reaping | |
1790 | * our own buffer, now let the real VM do its job and | |
1791 | * go down in flames if truly OOM. | |
1792 | */ | |
caf49191 | 1793 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1794 | gfp |= __GFP_IO | __GFP_WAIT; |
1795 | ||
1796 | i915_gem_shrink_all(dev_priv); | |
1797 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1798 | if (IS_ERR(page)) | |
1799 | goto err_pages; | |
1800 | ||
caf49191 | 1801 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1802 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1803 | } | |
1625e7e5 KRW |
1804 | #ifdef CONFIG_SWIOTLB |
1805 | if (swiotlb_nr_tbl()) { | |
1806 | st->nents++; | |
1807 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1808 | sg = sg_next(sg); | |
1809 | continue; | |
1810 | } | |
1811 | #endif | |
90797e6d ID |
1812 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1813 | if (i) | |
1814 | sg = sg_next(sg); | |
1815 | st->nents++; | |
1816 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1817 | } else { | |
1818 | sg->length += PAGE_SIZE; | |
1819 | } | |
1820 | last_pfn = page_to_pfn(page); | |
e5281ccd | 1821 | } |
1625e7e5 KRW |
1822 | #ifdef CONFIG_SWIOTLB |
1823 | if (!swiotlb_nr_tbl()) | |
1824 | #endif | |
1825 | sg_mark_end(sg); | |
74ce6b6c CW |
1826 | obj->pages = st; |
1827 | ||
6dacfd2f | 1828 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1829 | i915_gem_object_do_bit_17_swizzle(obj); |
1830 | ||
1831 | return 0; | |
1832 | ||
1833 | err_pages: | |
90797e6d ID |
1834 | sg_mark_end(sg); |
1835 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1836 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1837 | sg_free_table(st); |
1838 | kfree(st); | |
e5281ccd | 1839 | return PTR_ERR(page); |
673a394b EA |
1840 | } |
1841 | ||
37e680a1 CW |
1842 | /* Ensure that the associated pages are gathered from the backing storage |
1843 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1844 | * multiple times before they are released by a single call to | |
1845 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1846 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1847 | * or as the object is itself released. | |
1848 | */ | |
1849 | int | |
1850 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1851 | { | |
1852 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1853 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1854 | int ret; | |
1855 | ||
2f745ad3 | 1856 | if (obj->pages) |
37e680a1 CW |
1857 | return 0; |
1858 | ||
43e28f09 CW |
1859 | if (obj->madv != I915_MADV_WILLNEED) { |
1860 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1861 | return -EINVAL; | |
1862 | } | |
1863 | ||
a5570178 CW |
1864 | BUG_ON(obj->pages_pin_count); |
1865 | ||
37e680a1 CW |
1866 | ret = ops->get_pages(obj); |
1867 | if (ret) | |
1868 | return ret; | |
1869 | ||
35c20a60 | 1870 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 1871 | return 0; |
673a394b EA |
1872 | } |
1873 | ||
54cf91dc | 1874 | void |
05394f39 | 1875 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1876 | struct intel_ring_buffer *ring) |
673a394b | 1877 | { |
05394f39 | 1878 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1879 | struct drm_i915_private *dev_priv = dev->dev_private; |
5cef07e1 | 1880 | struct i915_address_space *vm = &dev_priv->gtt.base; |
9d773091 | 1881 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1882 | |
852835f3 | 1883 | BUG_ON(ring == NULL); |
02978ff5 CW |
1884 | if (obj->ring != ring && obj->last_write_seqno) { |
1885 | /* Keep the seqno relative to the current ring */ | |
1886 | obj->last_write_seqno = seqno; | |
1887 | } | |
05394f39 | 1888 | obj->ring = ring; |
673a394b EA |
1889 | |
1890 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1891 | if (!obj->active) { |
1892 | drm_gem_object_reference(&obj->base); | |
1893 | obj->active = 1; | |
673a394b | 1894 | } |
e35a41de | 1895 | |
673a394b | 1896 | /* Move from whatever list we were on to the tail of execution. */ |
5cef07e1 | 1897 | list_move_tail(&obj->mm_list, &vm->active_list); |
05394f39 | 1898 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 1899 | |
0201f1ec | 1900 | obj->last_read_seqno = seqno; |
caea7476 | 1901 | |
7dd49065 | 1902 | if (obj->fenced_gpu_access) { |
caea7476 | 1903 | obj->last_fenced_seqno = seqno; |
caea7476 | 1904 | |
7dd49065 CW |
1905 | /* Bump MRU to take account of the delayed flush */ |
1906 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1907 | struct drm_i915_fence_reg *reg; | |
1908 | ||
1909 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1910 | list_move_tail(®->lru_list, | |
1911 | &dev_priv->mm.fence_list); | |
1912 | } | |
caea7476 CW |
1913 | } |
1914 | } | |
1915 | ||
1916 | static void | |
caea7476 | 1917 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1918 | { |
05394f39 | 1919 | struct drm_device *dev = obj->base.dev; |
caea7476 | 1920 | struct drm_i915_private *dev_priv = dev->dev_private; |
5cef07e1 | 1921 | struct i915_address_space *vm = &dev_priv->gtt.base; |
ce44b0ea | 1922 | |
65ce3027 | 1923 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1924 | BUG_ON(!obj->active); |
caea7476 | 1925 | |
5cef07e1 | 1926 | list_move_tail(&obj->mm_list, &vm->inactive_list); |
caea7476 | 1927 | |
65ce3027 | 1928 | list_del_init(&obj->ring_list); |
caea7476 CW |
1929 | obj->ring = NULL; |
1930 | ||
65ce3027 CW |
1931 | obj->last_read_seqno = 0; |
1932 | obj->last_write_seqno = 0; | |
1933 | obj->base.write_domain = 0; | |
1934 | ||
1935 | obj->last_fenced_seqno = 0; | |
caea7476 | 1936 | obj->fenced_gpu_access = false; |
caea7476 CW |
1937 | |
1938 | obj->active = 0; | |
1939 | drm_gem_object_unreference(&obj->base); | |
1940 | ||
1941 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1942 | } |
673a394b | 1943 | |
9d773091 | 1944 | static int |
fca26bb4 | 1945 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1946 | { |
9d773091 CW |
1947 | struct drm_i915_private *dev_priv = dev->dev_private; |
1948 | struct intel_ring_buffer *ring; | |
1949 | int ret, i, j; | |
53d227f2 | 1950 | |
107f27a5 | 1951 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1952 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1953 | ret = intel_ring_idle(ring); |
1954 | if (ret) | |
1955 | return ret; | |
9d773091 | 1956 | } |
9d773091 | 1957 | i915_gem_retire_requests(dev); |
107f27a5 CW |
1958 | |
1959 | /* Finally reset hw state */ | |
9d773091 | 1960 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 1961 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 1962 | |
9d773091 CW |
1963 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1964 | ring->sync_seqno[j] = 0; | |
1965 | } | |
53d227f2 | 1966 | |
9d773091 | 1967 | return 0; |
53d227f2 DV |
1968 | } |
1969 | ||
fca26bb4 MK |
1970 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1971 | { | |
1972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1973 | int ret; | |
1974 | ||
1975 | if (seqno == 0) | |
1976 | return -EINVAL; | |
1977 | ||
1978 | /* HWS page needs to be set less than what we | |
1979 | * will inject to ring | |
1980 | */ | |
1981 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
1982 | if (ret) | |
1983 | return ret; | |
1984 | ||
1985 | /* Carefully set the last_seqno value so that wrap | |
1986 | * detection still works | |
1987 | */ | |
1988 | dev_priv->next_seqno = seqno; | |
1989 | dev_priv->last_seqno = seqno - 1; | |
1990 | if (dev_priv->last_seqno == 0) | |
1991 | dev_priv->last_seqno--; | |
1992 | ||
1993 | return 0; | |
1994 | } | |
1995 | ||
9d773091 CW |
1996 | int |
1997 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 1998 | { |
9d773091 CW |
1999 | struct drm_i915_private *dev_priv = dev->dev_private; |
2000 | ||
2001 | /* reserve 0 for non-seqno */ | |
2002 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2003 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2004 | if (ret) |
2005 | return ret; | |
53d227f2 | 2006 | |
9d773091 CW |
2007 | dev_priv->next_seqno = 1; |
2008 | } | |
53d227f2 | 2009 | |
f72b3435 | 2010 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2011 | return 0; |
53d227f2 DV |
2012 | } |
2013 | ||
0025c077 MK |
2014 | int __i915_add_request(struct intel_ring_buffer *ring, |
2015 | struct drm_file *file, | |
7d736f4f | 2016 | struct drm_i915_gem_object *obj, |
0025c077 | 2017 | u32 *out_seqno) |
673a394b | 2018 | { |
db53a302 | 2019 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2020 | struct drm_i915_gem_request *request; |
7d736f4f | 2021 | u32 request_ring_position, request_start; |
673a394b | 2022 | int was_empty; |
3cce469c CW |
2023 | int ret; |
2024 | ||
7d736f4f | 2025 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2026 | /* |
2027 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2028 | * after having emitted the batchbuffer command. Hence we need to fix | |
2029 | * things up similar to emitting the lazy request. The difference here | |
2030 | * is that the flush _must_ happen before the next request, no matter | |
2031 | * what. | |
2032 | */ | |
a7b9761d CW |
2033 | ret = intel_ring_flush_all_caches(ring); |
2034 | if (ret) | |
2035 | return ret; | |
cc889e0f | 2036 | |
acb868d3 CW |
2037 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
2038 | if (request == NULL) | |
2039 | return -ENOMEM; | |
cc889e0f | 2040 | |
673a394b | 2041 | |
a71d8d94 CW |
2042 | /* Record the position of the start of the request so that |
2043 | * should we detect the updated seqno part-way through the | |
2044 | * GPU processing the request, we never over-estimate the | |
2045 | * position of the head. | |
2046 | */ | |
2047 | request_ring_position = intel_ring_get_tail(ring); | |
2048 | ||
9d773091 | 2049 | ret = ring->add_request(ring); |
3bb73aba CW |
2050 | if (ret) { |
2051 | kfree(request); | |
2052 | return ret; | |
2053 | } | |
673a394b | 2054 | |
9d773091 | 2055 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2056 | request->ring = ring; |
7d736f4f | 2057 | request->head = request_start; |
a71d8d94 | 2058 | request->tail = request_ring_position; |
0e50e96b | 2059 | request->ctx = ring->last_context; |
7d736f4f MK |
2060 | request->batch_obj = obj; |
2061 | ||
2062 | /* Whilst this request exists, batch_obj will be on the | |
2063 | * active_list, and so will hold the active reference. Only when this | |
2064 | * request is retired will the the batch_obj be moved onto the | |
2065 | * inactive_list and lose its active reference. Hence we do not need | |
2066 | * to explicitly hold another reference here. | |
2067 | */ | |
0e50e96b MK |
2068 | |
2069 | if (request->ctx) | |
2070 | i915_gem_context_reference(request->ctx); | |
2071 | ||
673a394b | 2072 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2073 | was_empty = list_empty(&ring->request_list); |
2074 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2075 | request->file_priv = NULL; |
852835f3 | 2076 | |
db53a302 CW |
2077 | if (file) { |
2078 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2079 | ||
1c25595f | 2080 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2081 | request->file_priv = file_priv; |
b962442e | 2082 | list_add_tail(&request->client_list, |
f787a5f5 | 2083 | &file_priv->mm.request_list); |
1c25595f | 2084 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2085 | } |
673a394b | 2086 | |
9d773091 | 2087 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2088 | ring->outstanding_lazy_request = 0; |
db53a302 | 2089 | |
db1b76ca | 2090 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2091 | i915_queue_hangcheck(ring->dev); |
2092 | ||
f047e395 | 2093 | if (was_empty) { |
b3b079db | 2094 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2095 | &dev_priv->mm.retire_work, |
2096 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2097 | intel_mark_busy(dev_priv->dev); |
2098 | } | |
f65d9421 | 2099 | } |
cc889e0f | 2100 | |
acb868d3 | 2101 | if (out_seqno) |
9d773091 | 2102 | *out_seqno = request->seqno; |
3cce469c | 2103 | return 0; |
673a394b EA |
2104 | } |
2105 | ||
f787a5f5 CW |
2106 | static inline void |
2107 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2108 | { |
1c25595f | 2109 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2110 | |
1c25595f CW |
2111 | if (!file_priv) |
2112 | return; | |
1c5d22f7 | 2113 | |
1c25595f | 2114 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2115 | if (request->file_priv) { |
2116 | list_del(&request->client_list); | |
2117 | request->file_priv = NULL; | |
2118 | } | |
1c25595f | 2119 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2120 | } |
673a394b | 2121 | |
aa60c664 MK |
2122 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj) |
2123 | { | |
f343c5f6 BW |
2124 | if (acthd >= i915_gem_obj_ggtt_offset(obj) && |
2125 | acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size) | |
aa60c664 MK |
2126 | return true; |
2127 | ||
2128 | return false; | |
2129 | } | |
2130 | ||
2131 | static bool i915_head_inside_request(const u32 acthd_unmasked, | |
2132 | const u32 request_start, | |
2133 | const u32 request_end) | |
2134 | { | |
2135 | const u32 acthd = acthd_unmasked & HEAD_ADDR; | |
2136 | ||
2137 | if (request_start < request_end) { | |
2138 | if (acthd >= request_start && acthd < request_end) | |
2139 | return true; | |
2140 | } else if (request_start > request_end) { | |
2141 | if (acthd >= request_start || acthd < request_end) | |
2142 | return true; | |
2143 | } | |
2144 | ||
2145 | return false; | |
2146 | } | |
2147 | ||
2148 | static bool i915_request_guilty(struct drm_i915_gem_request *request, | |
2149 | const u32 acthd, bool *inside) | |
2150 | { | |
2151 | /* There is a possibility that unmasked head address | |
2152 | * pointing inside the ring, matches the batch_obj address range. | |
2153 | * However this is extremely unlikely. | |
2154 | */ | |
2155 | ||
2156 | if (request->batch_obj) { | |
2157 | if (i915_head_inside_object(acthd, request->batch_obj)) { | |
2158 | *inside = true; | |
2159 | return true; | |
2160 | } | |
2161 | } | |
2162 | ||
2163 | if (i915_head_inside_request(acthd, request->head, request->tail)) { | |
2164 | *inside = false; | |
2165 | return true; | |
2166 | } | |
2167 | ||
2168 | return false; | |
2169 | } | |
2170 | ||
2171 | static void i915_set_reset_status(struct intel_ring_buffer *ring, | |
2172 | struct drm_i915_gem_request *request, | |
2173 | u32 acthd) | |
2174 | { | |
2175 | struct i915_ctx_hang_stats *hs = NULL; | |
2176 | bool inside, guilty; | |
2177 | ||
2178 | /* Innocent until proven guilty */ | |
2179 | guilty = false; | |
2180 | ||
2181 | if (ring->hangcheck.action != wait && | |
2182 | i915_request_guilty(request, acthd, &inside)) { | |
f343c5f6 | 2183 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
aa60c664 MK |
2184 | ring->name, |
2185 | inside ? "inside" : "flushing", | |
2186 | request->batch_obj ? | |
f343c5f6 | 2187 | i915_gem_obj_ggtt_offset(request->batch_obj) : 0, |
aa60c664 MK |
2188 | request->ctx ? request->ctx->id : 0, |
2189 | acthd); | |
2190 | ||
2191 | guilty = true; | |
2192 | } | |
2193 | ||
2194 | /* If contexts are disabled or this is the default context, use | |
2195 | * file_priv->reset_state | |
2196 | */ | |
2197 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) | |
2198 | hs = &request->ctx->hang_stats; | |
2199 | else if (request->file_priv) | |
2200 | hs = &request->file_priv->hang_stats; | |
2201 | ||
2202 | if (hs) { | |
2203 | if (guilty) | |
2204 | hs->batch_active++; | |
2205 | else | |
2206 | hs->batch_pending++; | |
2207 | } | |
2208 | } | |
2209 | ||
0e50e96b MK |
2210 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2211 | { | |
2212 | list_del(&request->list); | |
2213 | i915_gem_request_remove_from_client(request); | |
2214 | ||
2215 | if (request->ctx) | |
2216 | i915_gem_context_unreference(request->ctx); | |
2217 | ||
2218 | kfree(request); | |
2219 | } | |
2220 | ||
dfaae392 CW |
2221 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2222 | struct intel_ring_buffer *ring) | |
9375e446 | 2223 | { |
aa60c664 MK |
2224 | u32 completed_seqno; |
2225 | u32 acthd; | |
2226 | ||
2227 | acthd = intel_ring_get_active_head(ring); | |
2228 | completed_seqno = ring->get_seqno(ring, false); | |
2229 | ||
dfaae392 CW |
2230 | while (!list_empty(&ring->request_list)) { |
2231 | struct drm_i915_gem_request *request; | |
673a394b | 2232 | |
dfaae392 CW |
2233 | request = list_first_entry(&ring->request_list, |
2234 | struct drm_i915_gem_request, | |
2235 | list); | |
de151cf6 | 2236 | |
aa60c664 MK |
2237 | if (request->seqno > completed_seqno) |
2238 | i915_set_reset_status(ring, request, acthd); | |
2239 | ||
0e50e96b | 2240 | i915_gem_free_request(request); |
dfaae392 | 2241 | } |
673a394b | 2242 | |
dfaae392 | 2243 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2244 | struct drm_i915_gem_object *obj; |
9375e446 | 2245 | |
05394f39 CW |
2246 | obj = list_first_entry(&ring->active_list, |
2247 | struct drm_i915_gem_object, | |
2248 | ring_list); | |
9375e446 | 2249 | |
05394f39 | 2250 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2251 | } |
2252 | } | |
2253 | ||
19b2dbde | 2254 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2255 | { |
2256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2257 | int i; | |
2258 | ||
4b9de737 | 2259 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2260 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2261 | |
94a335db DV |
2262 | /* |
2263 | * Commit delayed tiling changes if we have an object still | |
2264 | * attached to the fence, otherwise just clear the fence. | |
2265 | */ | |
2266 | if (reg->obj) { | |
2267 | i915_gem_object_update_fence(reg->obj, reg, | |
2268 | reg->obj->tiling_mode); | |
2269 | } else { | |
2270 | i915_gem_write_fence(dev, i, NULL); | |
2271 | } | |
312817a3 CW |
2272 | } |
2273 | } | |
2274 | ||
069efc1d | 2275 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2276 | { |
77f01230 | 2277 | struct drm_i915_private *dev_priv = dev->dev_private; |
5cef07e1 | 2278 | struct i915_address_space *vm = &dev_priv->gtt.base; |
05394f39 | 2279 | struct drm_i915_gem_object *obj; |
b4519513 | 2280 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2281 | int i; |
673a394b | 2282 | |
b4519513 CW |
2283 | for_each_ring(ring, dev_priv, i) |
2284 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2285 | |
dfaae392 CW |
2286 | /* Move everything out of the GPU domains to ensure we do any |
2287 | * necessary invalidation upon reuse. | |
2288 | */ | |
5cef07e1 | 2289 | list_for_each_entry(obj, &vm->inactive_list, mm_list) |
05394f39 | 2290 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
069efc1d | 2291 | |
19b2dbde | 2292 | i915_gem_restore_fences(dev); |
673a394b EA |
2293 | } |
2294 | ||
2295 | /** | |
2296 | * This function clears the request list as sequence numbers are passed. | |
2297 | */ | |
a71d8d94 | 2298 | void |
db53a302 | 2299 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2300 | { |
673a394b EA |
2301 | uint32_t seqno; |
2302 | ||
db53a302 | 2303 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2304 | return; |
2305 | ||
db53a302 | 2306 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2307 | |
b2eadbc8 | 2308 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2309 | |
852835f3 | 2310 | while (!list_empty(&ring->request_list)) { |
673a394b | 2311 | struct drm_i915_gem_request *request; |
673a394b | 2312 | |
852835f3 | 2313 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2314 | struct drm_i915_gem_request, |
2315 | list); | |
673a394b | 2316 | |
dfaae392 | 2317 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2318 | break; |
2319 | ||
db53a302 | 2320 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2321 | /* We know the GPU must have read the request to have |
2322 | * sent us the seqno + interrupt, so use the position | |
2323 | * of tail of the request to update the last known position | |
2324 | * of the GPU head. | |
2325 | */ | |
2326 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2327 | |
0e50e96b | 2328 | i915_gem_free_request(request); |
b84d5f0c | 2329 | } |
673a394b | 2330 | |
b84d5f0c CW |
2331 | /* Move any buffers on the active list that are no longer referenced |
2332 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2333 | */ | |
2334 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2335 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2336 | |
0206e353 | 2337 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2338 | struct drm_i915_gem_object, |
2339 | ring_list); | |
673a394b | 2340 | |
0201f1ec | 2341 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2342 | break; |
b84d5f0c | 2343 | |
65ce3027 | 2344 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2345 | } |
9d34e5db | 2346 | |
db53a302 CW |
2347 | if (unlikely(ring->trace_irq_seqno && |
2348 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2349 | ring->irq_put(ring); |
db53a302 | 2350 | ring->trace_irq_seqno = 0; |
9d34e5db | 2351 | } |
23bc5982 | 2352 | |
db53a302 | 2353 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2354 | } |
2355 | ||
b09a1fec CW |
2356 | void |
2357 | i915_gem_retire_requests(struct drm_device *dev) | |
2358 | { | |
2359 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2360 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2361 | int i; |
b09a1fec | 2362 | |
b4519513 CW |
2363 | for_each_ring(ring, dev_priv, i) |
2364 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2365 | } |
2366 | ||
75ef9da2 | 2367 | static void |
673a394b EA |
2368 | i915_gem_retire_work_handler(struct work_struct *work) |
2369 | { | |
2370 | drm_i915_private_t *dev_priv; | |
2371 | struct drm_device *dev; | |
b4519513 | 2372 | struct intel_ring_buffer *ring; |
0a58705b CW |
2373 | bool idle; |
2374 | int i; | |
673a394b EA |
2375 | |
2376 | dev_priv = container_of(work, drm_i915_private_t, | |
2377 | mm.retire_work.work); | |
2378 | dev = dev_priv->dev; | |
2379 | ||
891b48cf CW |
2380 | /* Come back later if the device is busy... */ |
2381 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2382 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2383 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2384 | return; |
2385 | } | |
673a394b | 2386 | |
b09a1fec | 2387 | i915_gem_retire_requests(dev); |
673a394b | 2388 | |
0a58705b CW |
2389 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2390 | * objects indefinitely. | |
673a394b | 2391 | */ |
0a58705b | 2392 | idle = true; |
b4519513 | 2393 | for_each_ring(ring, dev_priv, i) { |
3bb73aba | 2394 | if (ring->gpu_caches_dirty) |
0025c077 | 2395 | i915_add_request(ring, NULL); |
0a58705b CW |
2396 | |
2397 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2398 | } |
2399 | ||
db1b76ca | 2400 | if (!dev_priv->ums.mm_suspended && !idle) |
bcb45086 CW |
2401 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2402 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2403 | if (idle) |
2404 | intel_mark_idle(dev); | |
0a58705b | 2405 | |
673a394b | 2406 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2407 | } |
2408 | ||
30dfebf3 DV |
2409 | /** |
2410 | * Ensures that an object will eventually get non-busy by flushing any required | |
2411 | * write domains, emitting any outstanding lazy request and retiring and | |
2412 | * completed requests. | |
2413 | */ | |
2414 | static int | |
2415 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2416 | { | |
2417 | int ret; | |
2418 | ||
2419 | if (obj->active) { | |
0201f1ec | 2420 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2421 | if (ret) |
2422 | return ret; | |
2423 | ||
30dfebf3 DV |
2424 | i915_gem_retire_requests_ring(obj->ring); |
2425 | } | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
23ba4fd0 BW |
2430 | /** |
2431 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2432 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2433 | * | |
2434 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2435 | * the timeout parameter. | |
2436 | * -ETIME: object is still busy after timeout | |
2437 | * -ERESTARTSYS: signal interrupted the wait | |
2438 | * -ENONENT: object doesn't exist | |
2439 | * Also possible, but rare: | |
2440 | * -EAGAIN: GPU wedged | |
2441 | * -ENOMEM: damn | |
2442 | * -ENODEV: Internal IRQ fail | |
2443 | * -E?: The add request failed | |
2444 | * | |
2445 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2446 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2447 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2448 | * without holding struct_mutex the object may become re-busied before this | |
2449 | * function completes. A similar but shorter * race condition exists in the busy | |
2450 | * ioctl | |
2451 | */ | |
2452 | int | |
2453 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2454 | { | |
f69061be | 2455 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2456 | struct drm_i915_gem_wait *args = data; |
2457 | struct drm_i915_gem_object *obj; | |
2458 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2459 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2460 | unsigned reset_counter; |
23ba4fd0 BW |
2461 | u32 seqno = 0; |
2462 | int ret = 0; | |
2463 | ||
eac1f14f BW |
2464 | if (args->timeout_ns >= 0) { |
2465 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2466 | timeout = &timeout_stack; | |
2467 | } | |
23ba4fd0 BW |
2468 | |
2469 | ret = i915_mutex_lock_interruptible(dev); | |
2470 | if (ret) | |
2471 | return ret; | |
2472 | ||
2473 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2474 | if (&obj->base == NULL) { | |
2475 | mutex_unlock(&dev->struct_mutex); | |
2476 | return -ENOENT; | |
2477 | } | |
2478 | ||
30dfebf3 DV |
2479 | /* Need to make sure the object gets inactive eventually. */ |
2480 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2481 | if (ret) |
2482 | goto out; | |
2483 | ||
2484 | if (obj->active) { | |
0201f1ec | 2485 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2486 | ring = obj->ring; |
2487 | } | |
2488 | ||
2489 | if (seqno == 0) | |
2490 | goto out; | |
2491 | ||
23ba4fd0 BW |
2492 | /* Do this after OLR check to make sure we make forward progress polling |
2493 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2494 | */ | |
2495 | if (!args->timeout_ns) { | |
2496 | ret = -ETIME; | |
2497 | goto out; | |
2498 | } | |
2499 | ||
2500 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2501 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2502 | mutex_unlock(&dev->struct_mutex); |
2503 | ||
f69061be | 2504 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
4f42f4ef | 2505 | if (timeout) |
eac1f14f | 2506 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2507 | return ret; |
2508 | ||
2509 | out: | |
2510 | drm_gem_object_unreference(&obj->base); | |
2511 | mutex_unlock(&dev->struct_mutex); | |
2512 | return ret; | |
2513 | } | |
2514 | ||
5816d648 BW |
2515 | /** |
2516 | * i915_gem_object_sync - sync an object to a ring. | |
2517 | * | |
2518 | * @obj: object which may be in use on another ring. | |
2519 | * @to: ring we wish to use the object on. May be NULL. | |
2520 | * | |
2521 | * This code is meant to abstract object synchronization with the GPU. | |
2522 | * Calling with NULL implies synchronizing the object with the CPU | |
2523 | * rather than a particular GPU ring. | |
2524 | * | |
2525 | * Returns 0 if successful, else propagates up the lower layer error. | |
2526 | */ | |
2911a35b BW |
2527 | int |
2528 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2529 | struct intel_ring_buffer *to) | |
2530 | { | |
2531 | struct intel_ring_buffer *from = obj->ring; | |
2532 | u32 seqno; | |
2533 | int ret, idx; | |
2534 | ||
2535 | if (from == NULL || to == from) | |
2536 | return 0; | |
2537 | ||
5816d648 | 2538 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2539 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2540 | |
2541 | idx = intel_ring_sync_index(from, to); | |
2542 | ||
0201f1ec | 2543 | seqno = obj->last_read_seqno; |
2911a35b BW |
2544 | if (seqno <= from->sync_seqno[idx]) |
2545 | return 0; | |
2546 | ||
b4aca010 BW |
2547 | ret = i915_gem_check_olr(obj->ring, seqno); |
2548 | if (ret) | |
2549 | return ret; | |
2911a35b | 2550 | |
1500f7ea | 2551 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2552 | if (!ret) |
7b01e260 MK |
2553 | /* We use last_read_seqno because sync_to() |
2554 | * might have just caused seqno wrap under | |
2555 | * the radar. | |
2556 | */ | |
2557 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2558 | |
e3a5a225 | 2559 | return ret; |
2911a35b BW |
2560 | } |
2561 | ||
b5ffc9bc CW |
2562 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2563 | { | |
2564 | u32 old_write_domain, old_read_domains; | |
2565 | ||
b5ffc9bc CW |
2566 | /* Force a pagefault for domain tracking on next user access */ |
2567 | i915_gem_release_mmap(obj); | |
2568 | ||
b97c3d9c KP |
2569 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2570 | return; | |
2571 | ||
97c809fd CW |
2572 | /* Wait for any direct GTT access to complete */ |
2573 | mb(); | |
2574 | ||
b5ffc9bc CW |
2575 | old_read_domains = obj->base.read_domains; |
2576 | old_write_domain = obj->base.write_domain; | |
2577 | ||
2578 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2579 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2580 | ||
2581 | trace_i915_gem_object_change_domain(obj, | |
2582 | old_read_domains, | |
2583 | old_write_domain); | |
2584 | } | |
2585 | ||
673a394b EA |
2586 | /** |
2587 | * Unbinds an object from the GTT aperture. | |
2588 | */ | |
0f973f27 | 2589 | int |
05394f39 | 2590 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2591 | { |
7bddb01f | 2592 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
2f633156 | 2593 | struct i915_vma *vma; |
43e28f09 | 2594 | int ret; |
673a394b | 2595 | |
f343c5f6 | 2596 | if (!i915_gem_obj_ggtt_bound(obj)) |
673a394b EA |
2597 | return 0; |
2598 | ||
31d8d651 CW |
2599 | if (obj->pin_count) |
2600 | return -EBUSY; | |
673a394b | 2601 | |
c4670ad0 CW |
2602 | BUG_ON(obj->pages == NULL); |
2603 | ||
a8198eea | 2604 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2605 | if (ret) |
a8198eea CW |
2606 | return ret; |
2607 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2608 | * should be safe and we need to cleanup or else we might | |
2609 | * cause memory corruption through use-after-free. | |
2610 | */ | |
2611 | ||
b5ffc9bc | 2612 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2613 | |
96b47b65 | 2614 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2615 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2616 | if (ret) |
d9e86c0e | 2617 | return ret; |
96b47b65 | 2618 | |
db53a302 CW |
2619 | trace_i915_gem_object_unbind(obj); |
2620 | ||
74898d7e DV |
2621 | if (obj->has_global_gtt_mapping) |
2622 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2623 | if (obj->has_aliasing_ppgtt_mapping) { |
2624 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2625 | obj->has_aliasing_ppgtt_mapping = 0; | |
2626 | } | |
74163907 | 2627 | i915_gem_gtt_finish_object(obj); |
401c29f6 | 2628 | i915_gem_object_unpin_pages(obj); |
7bddb01f | 2629 | |
6c085a72 | 2630 | list_del(&obj->mm_list); |
75e9e915 | 2631 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2632 | obj->map_and_fenceable = true; |
673a394b | 2633 | |
a70a3148 | 2634 | vma = i915_gem_obj_to_vma(obj, &dev_priv->gtt.base); |
2f633156 BW |
2635 | list_del(&vma->vma_link); |
2636 | drm_mm_remove_node(&vma->node); | |
2637 | i915_gem_vma_destroy(vma); | |
2638 | ||
2639 | /* Since the unbound list is global, only move to that list if | |
2640 | * no more VMAs exist. | |
2641 | * NB: Until we have real VMAs there will only ever be one */ | |
2642 | WARN_ON(!list_empty(&obj->vma_list)); | |
2643 | if (list_empty(&obj->vma_list)) | |
2644 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2645 | |
88241785 | 2646 | return 0; |
54cf91dc CW |
2647 | } |
2648 | ||
b2da9fe5 | 2649 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2650 | { |
2651 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2652 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2653 | int ret, i; |
4df2faf4 | 2654 | |
4df2faf4 | 2655 | /* Flush everything onto the inactive list. */ |
b4519513 | 2656 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2657 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2658 | if (ret) | |
2659 | return ret; | |
2660 | ||
3e960501 | 2661 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2662 | if (ret) |
2663 | return ret; | |
2664 | } | |
4df2faf4 | 2665 | |
8a1a49f9 | 2666 | return 0; |
4df2faf4 DV |
2667 | } |
2668 | ||
9ce079e4 CW |
2669 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2670 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2671 | { |
de151cf6 | 2672 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2673 | int fence_reg; |
2674 | int fence_pitch_shift; | |
de151cf6 | 2675 | |
56c844e5 ID |
2676 | if (INTEL_INFO(dev)->gen >= 6) { |
2677 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2678 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2679 | } else { | |
2680 | fence_reg = FENCE_REG_965_0; | |
2681 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2682 | } | |
2683 | ||
d18b9619 CW |
2684 | fence_reg += reg * 8; |
2685 | ||
2686 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2687 | * we split the 64-bit update into two 32-bit writes. In order | |
2688 | * for a partial fence not to be evaluated between writes, we | |
2689 | * precede the update with write to turn off the fence register, | |
2690 | * and only enable the fence as the last step. | |
2691 | * | |
2692 | * For extra levels of paranoia, we make sure each step lands | |
2693 | * before applying the next step. | |
2694 | */ | |
2695 | I915_WRITE(fence_reg, 0); | |
2696 | POSTING_READ(fence_reg); | |
2697 | ||
9ce079e4 | 2698 | if (obj) { |
f343c5f6 | 2699 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2700 | uint64_t val; |
de151cf6 | 2701 | |
f343c5f6 | 2702 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2703 | 0xfffff000) << 32; |
f343c5f6 | 2704 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2705 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2706 | if (obj->tiling_mode == I915_TILING_Y) |
2707 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2708 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2709 | |
d18b9619 CW |
2710 | I915_WRITE(fence_reg + 4, val >> 32); |
2711 | POSTING_READ(fence_reg + 4); | |
2712 | ||
2713 | I915_WRITE(fence_reg + 0, val); | |
2714 | POSTING_READ(fence_reg); | |
2715 | } else { | |
2716 | I915_WRITE(fence_reg + 4, 0); | |
2717 | POSTING_READ(fence_reg + 4); | |
2718 | } | |
de151cf6 JB |
2719 | } |
2720 | ||
9ce079e4 CW |
2721 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2722 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2723 | { |
de151cf6 | 2724 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2725 | u32 val; |
de151cf6 | 2726 | |
9ce079e4 | 2727 | if (obj) { |
f343c5f6 | 2728 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2729 | int pitch_val; |
2730 | int tile_width; | |
c6642782 | 2731 | |
f343c5f6 | 2732 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2733 | (size & -size) != size || |
f343c5f6 BW |
2734 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2735 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2736 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2737 | |
9ce079e4 CW |
2738 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2739 | tile_width = 128; | |
2740 | else | |
2741 | tile_width = 512; | |
2742 | ||
2743 | /* Note: pitch better be a power of two tile widths */ | |
2744 | pitch_val = obj->stride / tile_width; | |
2745 | pitch_val = ffs(pitch_val) - 1; | |
2746 | ||
f343c5f6 | 2747 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2748 | if (obj->tiling_mode == I915_TILING_Y) |
2749 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2750 | val |= I915_FENCE_SIZE_BITS(size); | |
2751 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2752 | val |= I830_FENCE_REG_VALID; | |
2753 | } else | |
2754 | val = 0; | |
2755 | ||
2756 | if (reg < 8) | |
2757 | reg = FENCE_REG_830_0 + reg * 4; | |
2758 | else | |
2759 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2760 | ||
2761 | I915_WRITE(reg, val); | |
2762 | POSTING_READ(reg); | |
de151cf6 JB |
2763 | } |
2764 | ||
9ce079e4 CW |
2765 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2766 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2767 | { |
de151cf6 | 2768 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2769 | uint32_t val; |
de151cf6 | 2770 | |
9ce079e4 | 2771 | if (obj) { |
f343c5f6 | 2772 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2773 | uint32_t pitch_val; |
de151cf6 | 2774 | |
f343c5f6 | 2775 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2776 | (size & -size) != size || |
f343c5f6 BW |
2777 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2778 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2779 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2780 | |
9ce079e4 CW |
2781 | pitch_val = obj->stride / 128; |
2782 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2783 | |
f343c5f6 | 2784 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2785 | if (obj->tiling_mode == I915_TILING_Y) |
2786 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2787 | val |= I830_FENCE_SIZE_BITS(size); | |
2788 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2789 | val |= I830_FENCE_REG_VALID; | |
2790 | } else | |
2791 | val = 0; | |
c6642782 | 2792 | |
9ce079e4 CW |
2793 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2794 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2795 | } | |
2796 | ||
d0a57789 CW |
2797 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2798 | { | |
2799 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2800 | } | |
2801 | ||
9ce079e4 CW |
2802 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2803 | struct drm_i915_gem_object *obj) | |
2804 | { | |
d0a57789 CW |
2805 | struct drm_i915_private *dev_priv = dev->dev_private; |
2806 | ||
2807 | /* Ensure that all CPU reads are completed before installing a fence | |
2808 | * and all writes before removing the fence. | |
2809 | */ | |
2810 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2811 | mb(); | |
2812 | ||
94a335db DV |
2813 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2814 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2815 | obj->stride, obj->tiling_mode); | |
2816 | ||
9ce079e4 CW |
2817 | switch (INTEL_INFO(dev)->gen) { |
2818 | case 7: | |
56c844e5 | 2819 | case 6: |
9ce079e4 CW |
2820 | case 5: |
2821 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2822 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2823 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2824 | default: BUG(); |
9ce079e4 | 2825 | } |
d0a57789 CW |
2826 | |
2827 | /* And similarly be paranoid that no direct access to this region | |
2828 | * is reordered to before the fence is installed. | |
2829 | */ | |
2830 | if (i915_gem_object_needs_mb(obj)) | |
2831 | mb(); | |
de151cf6 JB |
2832 | } |
2833 | ||
61050808 CW |
2834 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2835 | struct drm_i915_fence_reg *fence) | |
2836 | { | |
2837 | return fence - dev_priv->fence_regs; | |
2838 | } | |
2839 | ||
2840 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2841 | struct drm_i915_fence_reg *fence, | |
2842 | bool enable) | |
2843 | { | |
2dc8aae0 | 2844 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
2845 | int reg = fence_number(dev_priv, fence); |
2846 | ||
2847 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
2848 | |
2849 | if (enable) { | |
46a0b638 | 2850 | obj->fence_reg = reg; |
61050808 CW |
2851 | fence->obj = obj; |
2852 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2853 | } else { | |
2854 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2855 | fence->obj = NULL; | |
2856 | list_del_init(&fence->lru_list); | |
2857 | } | |
94a335db | 2858 | obj->fence_dirty = false; |
61050808 CW |
2859 | } |
2860 | ||
d9e86c0e | 2861 | static int |
d0a57789 | 2862 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2863 | { |
1c293ea3 | 2864 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2865 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2866 | if (ret) |
2867 | return ret; | |
d9e86c0e CW |
2868 | |
2869 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2870 | } |
2871 | ||
86d5bc37 | 2872 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2873 | return 0; |
2874 | } | |
2875 | ||
2876 | int | |
2877 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2878 | { | |
61050808 | 2879 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 2880 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
2881 | int ret; |
2882 | ||
d0a57789 | 2883 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
2884 | if (ret) |
2885 | return ret; | |
2886 | ||
61050808 CW |
2887 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2888 | return 0; | |
d9e86c0e | 2889 | |
f9c513e9 CW |
2890 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2891 | ||
61050808 | 2892 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 2893 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
2894 | |
2895 | return 0; | |
2896 | } | |
2897 | ||
2898 | static struct drm_i915_fence_reg * | |
a360bb1a | 2899 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2900 | { |
ae3db24a | 2901 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2902 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2903 | int i; |
ae3db24a DV |
2904 | |
2905 | /* First try to find a free reg */ | |
d9e86c0e | 2906 | avail = NULL; |
ae3db24a DV |
2907 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2908 | reg = &dev_priv->fence_regs[i]; | |
2909 | if (!reg->obj) | |
d9e86c0e | 2910 | return reg; |
ae3db24a | 2911 | |
1690e1eb | 2912 | if (!reg->pin_count) |
d9e86c0e | 2913 | avail = reg; |
ae3db24a DV |
2914 | } |
2915 | ||
d9e86c0e CW |
2916 | if (avail == NULL) |
2917 | return NULL; | |
ae3db24a DV |
2918 | |
2919 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2920 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2921 | if (reg->pin_count) |
ae3db24a DV |
2922 | continue; |
2923 | ||
8fe301ad | 2924 | return reg; |
ae3db24a DV |
2925 | } |
2926 | ||
8fe301ad | 2927 | return NULL; |
ae3db24a DV |
2928 | } |
2929 | ||
de151cf6 | 2930 | /** |
9a5a53b3 | 2931 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2932 | * @obj: object to map through a fence reg |
2933 | * | |
2934 | * When mapping objects through the GTT, userspace wants to be able to write | |
2935 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2936 | * This function walks the fence regs looking for a free one for @obj, |
2937 | * stealing one if it can't find any. | |
2938 | * | |
2939 | * It then sets up the reg based on the object's properties: address, pitch | |
2940 | * and tiling format. | |
9a5a53b3 CW |
2941 | * |
2942 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2943 | */ |
8c4b8c3f | 2944 | int |
06d98131 | 2945 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2946 | { |
05394f39 | 2947 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2948 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2949 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2950 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2951 | int ret; |
de151cf6 | 2952 | |
14415745 CW |
2953 | /* Have we updated the tiling parameters upon the object and so |
2954 | * will need to serialise the write to the associated fence register? | |
2955 | */ | |
5d82e3e6 | 2956 | if (obj->fence_dirty) { |
d0a57789 | 2957 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
2958 | if (ret) |
2959 | return ret; | |
2960 | } | |
9a5a53b3 | 2961 | |
d9e86c0e | 2962 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2963 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2964 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2965 | if (!obj->fence_dirty) { |
14415745 CW |
2966 | list_move_tail(®->lru_list, |
2967 | &dev_priv->mm.fence_list); | |
2968 | return 0; | |
2969 | } | |
2970 | } else if (enable) { | |
2971 | reg = i915_find_fence_reg(dev); | |
2972 | if (reg == NULL) | |
2973 | return -EDEADLK; | |
d9e86c0e | 2974 | |
14415745 CW |
2975 | if (reg->obj) { |
2976 | struct drm_i915_gem_object *old = reg->obj; | |
2977 | ||
d0a57789 | 2978 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
2979 | if (ret) |
2980 | return ret; | |
2981 | ||
14415745 | 2982 | i915_gem_object_fence_lost(old); |
29c5a587 | 2983 | } |
14415745 | 2984 | } else |
a09ba7fa | 2985 | return 0; |
a09ba7fa | 2986 | |
14415745 | 2987 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 2988 | |
9ce079e4 | 2989 | return 0; |
de151cf6 JB |
2990 | } |
2991 | ||
42d6ab48 CW |
2992 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2993 | struct drm_mm_node *gtt_space, | |
2994 | unsigned long cache_level) | |
2995 | { | |
2996 | struct drm_mm_node *other; | |
2997 | ||
2998 | /* On non-LLC machines we have to be careful when putting differing | |
2999 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3000 | * crossing memory domains and dying. |
42d6ab48 CW |
3001 | */ |
3002 | if (HAS_LLC(dev)) | |
3003 | return true; | |
3004 | ||
c6cfb325 | 3005 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3006 | return true; |
3007 | ||
3008 | if (list_empty(>t_space->node_list)) | |
3009 | return true; | |
3010 | ||
3011 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3012 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3013 | return false; | |
3014 | ||
3015 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3016 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3017 | return false; | |
3018 | ||
3019 | return true; | |
3020 | } | |
3021 | ||
3022 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3023 | { | |
3024 | #if WATCH_GTT | |
3025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3026 | struct drm_i915_gem_object *obj; | |
3027 | int err = 0; | |
3028 | ||
35c20a60 | 3029 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3030 | if (obj->gtt_space == NULL) { |
3031 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3032 | err++; | |
3033 | continue; | |
3034 | } | |
3035 | ||
3036 | if (obj->cache_level != obj->gtt_space->color) { | |
3037 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3038 | i915_gem_obj_ggtt_offset(obj), |
3039 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3040 | obj->cache_level, |
3041 | obj->gtt_space->color); | |
3042 | err++; | |
3043 | continue; | |
3044 | } | |
3045 | ||
3046 | if (!i915_gem_valid_gtt_space(dev, | |
3047 | obj->gtt_space, | |
3048 | obj->cache_level)) { | |
3049 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3050 | i915_gem_obj_ggtt_offset(obj), |
3051 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3052 | obj->cache_level); |
3053 | err++; | |
3054 | continue; | |
3055 | } | |
3056 | } | |
3057 | ||
3058 | WARN_ON(err); | |
3059 | #endif | |
3060 | } | |
3061 | ||
673a394b EA |
3062 | /** |
3063 | * Finds free space in the GTT aperture and binds the object there. | |
3064 | */ | |
3065 | static int | |
05394f39 | 3066 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 3067 | unsigned alignment, |
86a1ee26 CW |
3068 | bool map_and_fenceable, |
3069 | bool nonblocking) | |
673a394b | 3070 | { |
05394f39 | 3071 | struct drm_device *dev = obj->base.dev; |
673a394b | 3072 | drm_i915_private_t *dev_priv = dev->dev_private; |
5cef07e1 | 3073 | struct i915_address_space *vm = &dev_priv->gtt.base; |
5e783301 | 3074 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 3075 | bool mappable, fenceable; |
0a9ae0d7 | 3076 | size_t gtt_max = map_and_fenceable ? |
853ba5d2 | 3077 | dev_priv->gtt.mappable_end : dev_priv->gtt.base.total; |
2f633156 | 3078 | struct i915_vma *vma; |
07f73f69 | 3079 | int ret; |
673a394b | 3080 | |
2f633156 BW |
3081 | if (WARN_ON(!list_empty(&obj->vma_list))) |
3082 | return -EBUSY; | |
3083 | ||
e28f8711 CW |
3084 | fence_size = i915_gem_get_gtt_size(dev, |
3085 | obj->base.size, | |
3086 | obj->tiling_mode); | |
3087 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3088 | obj->base.size, | |
d865110c | 3089 | obj->tiling_mode, true); |
e28f8711 | 3090 | unfenced_alignment = |
d865110c | 3091 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 3092 | obj->base.size, |
d865110c | 3093 | obj->tiling_mode, false); |
a00b10c3 | 3094 | |
673a394b | 3095 | if (alignment == 0) |
5e783301 DV |
3096 | alignment = map_and_fenceable ? fence_alignment : |
3097 | unfenced_alignment; | |
75e9e915 | 3098 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
3099 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3100 | return -EINVAL; | |
3101 | } | |
3102 | ||
05394f39 | 3103 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 3104 | |
654fc607 CW |
3105 | /* If the object is bigger than the entire aperture, reject it early |
3106 | * before evicting everything in a vain attempt to find space. | |
3107 | */ | |
0a9ae0d7 | 3108 | if (obj->base.size > gtt_max) { |
3765f304 | 3109 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb CW |
3110 | obj->base.size, |
3111 | map_and_fenceable ? "mappable" : "total", | |
0a9ae0d7 | 3112 | gtt_max); |
654fc607 CW |
3113 | return -E2BIG; |
3114 | } | |
3115 | ||
37e680a1 | 3116 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
3117 | if (ret) |
3118 | return ret; | |
3119 | ||
fbdda6fb CW |
3120 | i915_gem_object_pin_pages(obj); |
3121 | ||
2f633156 | 3122 | vma = i915_gem_vma_create(obj, &dev_priv->gtt.base); |
db473b36 | 3123 | if (IS_ERR(vma)) { |
bc6bc15b DV |
3124 | ret = PTR_ERR(vma); |
3125 | goto err_unpin; | |
2f633156 BW |
3126 | } |
3127 | ||
0a9ae0d7 | 3128 | search_free: |
93bd8649 | 3129 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
2f633156 | 3130 | &vma->node, |
0a9ae0d7 BW |
3131 | size, alignment, |
3132 | obj->cache_level, 0, gtt_max); | |
dc9dd7a2 | 3133 | if (ret) { |
75e9e915 | 3134 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 3135 | obj->cache_level, |
86a1ee26 CW |
3136 | map_and_fenceable, |
3137 | nonblocking); | |
dc9dd7a2 CW |
3138 | if (ret == 0) |
3139 | goto search_free; | |
9731129c | 3140 | |
bc6bc15b | 3141 | goto err_free_vma; |
673a394b | 3142 | } |
2f633156 | 3143 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3144 | obj->cache_level))) { |
2f633156 | 3145 | ret = -EINVAL; |
bc6bc15b | 3146 | goto err_remove_node; |
673a394b EA |
3147 | } |
3148 | ||
74163907 | 3149 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3150 | if (ret) |
bc6bc15b | 3151 | goto err_remove_node; |
673a394b | 3152 | |
35c20a60 | 3153 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
5cef07e1 | 3154 | list_add_tail(&obj->mm_list, &vm->inactive_list); |
2f633156 | 3155 | list_add(&vma->vma_link, &obj->vma_list); |
bf1a1092 | 3156 | |
75e9e915 | 3157 | fenceable = |
c6cfb325 BW |
3158 | i915_gem_obj_ggtt_size(obj) == fence_size && |
3159 | (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0; | |
a00b10c3 | 3160 | |
f343c5f6 BW |
3161 | mappable = i915_gem_obj_ggtt_offset(obj) + obj->base.size <= |
3162 | dev_priv->gtt.mappable_end; | |
a00b10c3 | 3163 | |
05394f39 | 3164 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 3165 | |
db53a302 | 3166 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 3167 | i915_gem_verify_gtt(dev); |
673a394b | 3168 | return 0; |
2f633156 | 3169 | |
bc6bc15b | 3170 | err_remove_node: |
6286ef9b | 3171 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3172 | err_free_vma: |
2f633156 | 3173 | i915_gem_vma_destroy(vma); |
bc6bc15b | 3174 | err_unpin: |
2f633156 | 3175 | i915_gem_object_unpin_pages(obj); |
2f633156 | 3176 | return ret; |
673a394b EA |
3177 | } |
3178 | ||
3179 | void | |
05394f39 | 3180 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 3181 | { |
673a394b EA |
3182 | /* If we don't have a page list set up, then we're not pinned |
3183 | * to GPU, and we can ignore the cache flush because it'll happen | |
3184 | * again at bind time. | |
3185 | */ | |
05394f39 | 3186 | if (obj->pages == NULL) |
673a394b EA |
3187 | return; |
3188 | ||
769ce464 ID |
3189 | /* |
3190 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3191 | * marked as wc by the system, or the system is cache-coherent. | |
3192 | */ | |
3193 | if (obj->stolen) | |
3194 | return; | |
3195 | ||
9c23f7fc CW |
3196 | /* If the GPU is snooping the contents of the CPU cache, |
3197 | * we do not need to manually clear the CPU cache lines. However, | |
3198 | * the caches are only snooped when the render cache is | |
3199 | * flushed/invalidated. As we always have to emit invalidations | |
3200 | * and flushes when moving into and out of the RENDER domain, correct | |
3201 | * snooping behaviour occurs naturally as the result of our domain | |
3202 | * tracking. | |
3203 | */ | |
3204 | if (obj->cache_level != I915_CACHE_NONE) | |
3205 | return; | |
3206 | ||
1c5d22f7 | 3207 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3208 | |
9da3da66 | 3209 | drm_clflush_sg(obj->pages); |
e47c68e9 EA |
3210 | } |
3211 | ||
3212 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3213 | static void | |
05394f39 | 3214 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3215 | { |
1c5d22f7 CW |
3216 | uint32_t old_write_domain; |
3217 | ||
05394f39 | 3218 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3219 | return; |
3220 | ||
63256ec5 | 3221 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3222 | * to it immediately go to main memory as far as we know, so there's |
3223 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3224 | * |
3225 | * However, we do have to enforce the order so that all writes through | |
3226 | * the GTT land before any writes to the device, such as updates to | |
3227 | * the GATT itself. | |
e47c68e9 | 3228 | */ |
63256ec5 CW |
3229 | wmb(); |
3230 | ||
05394f39 CW |
3231 | old_write_domain = obj->base.write_domain; |
3232 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3233 | |
3234 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3235 | obj->base.read_domains, |
1c5d22f7 | 3236 | old_write_domain); |
e47c68e9 EA |
3237 | } |
3238 | ||
3239 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3240 | static void | |
05394f39 | 3241 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3242 | { |
1c5d22f7 | 3243 | uint32_t old_write_domain; |
e47c68e9 | 3244 | |
05394f39 | 3245 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3246 | return; |
3247 | ||
3248 | i915_gem_clflush_object(obj); | |
e76e9aeb | 3249 | i915_gem_chipset_flush(obj->base.dev); |
05394f39 CW |
3250 | old_write_domain = obj->base.write_domain; |
3251 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3252 | |
3253 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3254 | obj->base.read_domains, |
1c5d22f7 | 3255 | old_write_domain); |
e47c68e9 EA |
3256 | } |
3257 | ||
2ef7eeaa EA |
3258 | /** |
3259 | * Moves a single object to the GTT read, and possibly write domain. | |
3260 | * | |
3261 | * This function returns when the move is complete, including waiting on | |
3262 | * flushes to occur. | |
3263 | */ | |
79e53945 | 3264 | int |
2021746e | 3265 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3266 | { |
8325a09d | 3267 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3268 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3269 | int ret; |
2ef7eeaa | 3270 | |
02354392 | 3271 | /* Not valid to be called on unbound objects. */ |
f343c5f6 | 3272 | if (!i915_gem_obj_ggtt_bound(obj)) |
02354392 EA |
3273 | return -EINVAL; |
3274 | ||
8d7e3de1 CW |
3275 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3276 | return 0; | |
3277 | ||
0201f1ec | 3278 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3279 | if (ret) |
3280 | return ret; | |
3281 | ||
7213342d | 3282 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3283 | |
d0a57789 CW |
3284 | /* Serialise direct access to this object with the barriers for |
3285 | * coherent writes from the GPU, by effectively invalidating the | |
3286 | * GTT domain upon first access. | |
3287 | */ | |
3288 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3289 | mb(); | |
3290 | ||
05394f39 CW |
3291 | old_write_domain = obj->base.write_domain; |
3292 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3293 | |
e47c68e9 EA |
3294 | /* It should now be out of any other write domains, and we can update |
3295 | * the domain values for our changes. | |
3296 | */ | |
05394f39 CW |
3297 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3298 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3299 | if (write) { |
05394f39 CW |
3300 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3301 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3302 | obj->dirty = 1; | |
2ef7eeaa EA |
3303 | } |
3304 | ||
1c5d22f7 CW |
3305 | trace_i915_gem_object_change_domain(obj, |
3306 | old_read_domains, | |
3307 | old_write_domain); | |
3308 | ||
8325a09d CW |
3309 | /* And bump the LRU for this access */ |
3310 | if (i915_gem_object_is_inactive(obj)) | |
5cef07e1 BW |
3311 | list_move_tail(&obj->mm_list, |
3312 | &dev_priv->gtt.base.inactive_list); | |
8325a09d | 3313 | |
e47c68e9 EA |
3314 | return 0; |
3315 | } | |
3316 | ||
e4ffd173 CW |
3317 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3318 | enum i915_cache_level cache_level) | |
3319 | { | |
7bddb01f DV |
3320 | struct drm_device *dev = obj->base.dev; |
3321 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a70a3148 | 3322 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, &dev_priv->gtt.base); |
e4ffd173 CW |
3323 | int ret; |
3324 | ||
3325 | if (obj->cache_level == cache_level) | |
3326 | return 0; | |
3327 | ||
3328 | if (obj->pin_count) { | |
3329 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3330 | return -EBUSY; | |
3331 | } | |
3332 | ||
2f633156 | 3333 | if (vma && !i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
42d6ab48 CW |
3334 | ret = i915_gem_object_unbind(obj); |
3335 | if (ret) | |
3336 | return ret; | |
3337 | } | |
3338 | ||
f343c5f6 | 3339 | if (i915_gem_obj_ggtt_bound(obj)) { |
e4ffd173 CW |
3340 | ret = i915_gem_object_finish_gpu(obj); |
3341 | if (ret) | |
3342 | return ret; | |
3343 | ||
3344 | i915_gem_object_finish_gtt(obj); | |
3345 | ||
3346 | /* Before SandyBridge, you could not use tiling or fence | |
3347 | * registers with snooped memory, so relinquish any fences | |
3348 | * currently pointing to our region in the aperture. | |
3349 | */ | |
42d6ab48 | 3350 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3351 | ret = i915_gem_object_put_fence(obj); |
3352 | if (ret) | |
3353 | return ret; | |
3354 | } | |
3355 | ||
74898d7e DV |
3356 | if (obj->has_global_gtt_mapping) |
3357 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3358 | if (obj->has_aliasing_ppgtt_mapping) |
3359 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3360 | obj, cache_level); | |
42d6ab48 | 3361 | |
a70a3148 | 3362 | i915_gem_obj_to_vma(obj, &dev_priv->gtt.base)->node.color = cache_level; |
e4ffd173 CW |
3363 | } |
3364 | ||
3365 | if (cache_level == I915_CACHE_NONE) { | |
3366 | u32 old_read_domains, old_write_domain; | |
3367 | ||
3368 | /* If we're coming from LLC cached, then we haven't | |
3369 | * actually been tracking whether the data is in the | |
3370 | * CPU cache or not, since we only allow one bit set | |
3371 | * in obj->write_domain and have been skipping the clflushes. | |
3372 | * Just set it to the CPU cache for now. | |
3373 | */ | |
3374 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3375 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3376 | ||
3377 | old_read_domains = obj->base.read_domains; | |
3378 | old_write_domain = obj->base.write_domain; | |
3379 | ||
3380 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3381 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3382 | ||
3383 | trace_i915_gem_object_change_domain(obj, | |
3384 | old_read_domains, | |
3385 | old_write_domain); | |
3386 | } | |
3387 | ||
3388 | obj->cache_level = cache_level; | |
42d6ab48 | 3389 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3390 | return 0; |
3391 | } | |
3392 | ||
199adf40 BW |
3393 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3394 | struct drm_file *file) | |
e6994aee | 3395 | { |
199adf40 | 3396 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3397 | struct drm_i915_gem_object *obj; |
3398 | int ret; | |
3399 | ||
3400 | ret = i915_mutex_lock_interruptible(dev); | |
3401 | if (ret) | |
3402 | return ret; | |
3403 | ||
3404 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3405 | if (&obj->base == NULL) { | |
3406 | ret = -ENOENT; | |
3407 | goto unlock; | |
3408 | } | |
3409 | ||
199adf40 | 3410 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3411 | |
3412 | drm_gem_object_unreference(&obj->base); | |
3413 | unlock: | |
3414 | mutex_unlock(&dev->struct_mutex); | |
3415 | return ret; | |
3416 | } | |
3417 | ||
199adf40 BW |
3418 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3419 | struct drm_file *file) | |
e6994aee | 3420 | { |
199adf40 | 3421 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3422 | struct drm_i915_gem_object *obj; |
3423 | enum i915_cache_level level; | |
3424 | int ret; | |
3425 | ||
199adf40 BW |
3426 | switch (args->caching) { |
3427 | case I915_CACHING_NONE: | |
e6994aee CW |
3428 | level = I915_CACHE_NONE; |
3429 | break; | |
199adf40 | 3430 | case I915_CACHING_CACHED: |
e6994aee CW |
3431 | level = I915_CACHE_LLC; |
3432 | break; | |
3433 | default: | |
3434 | return -EINVAL; | |
3435 | } | |
3436 | ||
3bc2913e BW |
3437 | ret = i915_mutex_lock_interruptible(dev); |
3438 | if (ret) | |
3439 | return ret; | |
3440 | ||
e6994aee CW |
3441 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3442 | if (&obj->base == NULL) { | |
3443 | ret = -ENOENT; | |
3444 | goto unlock; | |
3445 | } | |
3446 | ||
3447 | ret = i915_gem_object_set_cache_level(obj, level); | |
3448 | ||
3449 | drm_gem_object_unreference(&obj->base); | |
3450 | unlock: | |
3451 | mutex_unlock(&dev->struct_mutex); | |
3452 | return ret; | |
3453 | } | |
3454 | ||
b9241ea3 | 3455 | /* |
2da3b9b9 CW |
3456 | * Prepare buffer for display plane (scanout, cursors, etc). |
3457 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3458 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3459 | */ |
3460 | int | |
2da3b9b9 CW |
3461 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3462 | u32 alignment, | |
919926ae | 3463 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3464 | { |
2da3b9b9 | 3465 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3466 | int ret; |
3467 | ||
0be73284 | 3468 | if (pipelined != obj->ring) { |
2911a35b BW |
3469 | ret = i915_gem_object_sync(obj, pipelined); |
3470 | if (ret) | |
b9241ea3 ZW |
3471 | return ret; |
3472 | } | |
3473 | ||
a7ef0640 EA |
3474 | /* The display engine is not coherent with the LLC cache on gen6. As |
3475 | * a result, we make sure that the pinning that is about to occur is | |
3476 | * done with uncached PTEs. This is lowest common denominator for all | |
3477 | * chipsets. | |
3478 | * | |
3479 | * However for gen6+, we could do better by using the GFDT bit instead | |
3480 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3481 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3482 | */ | |
3483 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3484 | if (ret) | |
3485 | return ret; | |
3486 | ||
2da3b9b9 CW |
3487 | /* As the user may map the buffer once pinned in the display plane |
3488 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3489 | * always use map_and_fenceable for all scanout buffers. | |
3490 | */ | |
86a1ee26 | 3491 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3492 | if (ret) |
3493 | return ret; | |
3494 | ||
b118c1e3 CW |
3495 | i915_gem_object_flush_cpu_write_domain(obj); |
3496 | ||
2da3b9b9 | 3497 | old_write_domain = obj->base.write_domain; |
05394f39 | 3498 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3499 | |
3500 | /* It should now be out of any other write domains, and we can update | |
3501 | * the domain values for our changes. | |
3502 | */ | |
e5f1d962 | 3503 | obj->base.write_domain = 0; |
05394f39 | 3504 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3505 | |
3506 | trace_i915_gem_object_change_domain(obj, | |
3507 | old_read_domains, | |
2da3b9b9 | 3508 | old_write_domain); |
b9241ea3 ZW |
3509 | |
3510 | return 0; | |
3511 | } | |
3512 | ||
85345517 | 3513 | int |
a8198eea | 3514 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3515 | { |
88241785 CW |
3516 | int ret; |
3517 | ||
a8198eea | 3518 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3519 | return 0; |
3520 | ||
0201f1ec | 3521 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3522 | if (ret) |
3523 | return ret; | |
3524 | ||
a8198eea CW |
3525 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3526 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3527 | return 0; |
85345517 CW |
3528 | } |
3529 | ||
e47c68e9 EA |
3530 | /** |
3531 | * Moves a single object to the CPU read, and possibly write domain. | |
3532 | * | |
3533 | * This function returns when the move is complete, including waiting on | |
3534 | * flushes to occur. | |
3535 | */ | |
dabdfe02 | 3536 | int |
919926ae | 3537 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3538 | { |
1c5d22f7 | 3539 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3540 | int ret; |
3541 | ||
8d7e3de1 CW |
3542 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3543 | return 0; | |
3544 | ||
0201f1ec | 3545 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3546 | if (ret) |
3547 | return ret; | |
3548 | ||
e47c68e9 | 3549 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3550 | |
05394f39 CW |
3551 | old_write_domain = obj->base.write_domain; |
3552 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3553 | |
e47c68e9 | 3554 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3555 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3556 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3557 | |
05394f39 | 3558 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3559 | } |
3560 | ||
3561 | /* It should now be out of any other write domains, and we can update | |
3562 | * the domain values for our changes. | |
3563 | */ | |
05394f39 | 3564 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3565 | |
3566 | /* If we're writing through the CPU, then the GPU read domains will | |
3567 | * need to be invalidated at next use. | |
3568 | */ | |
3569 | if (write) { | |
05394f39 CW |
3570 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3571 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3572 | } |
2ef7eeaa | 3573 | |
1c5d22f7 CW |
3574 | trace_i915_gem_object_change_domain(obj, |
3575 | old_read_domains, | |
3576 | old_write_domain); | |
3577 | ||
2ef7eeaa EA |
3578 | return 0; |
3579 | } | |
3580 | ||
673a394b EA |
3581 | /* Throttle our rendering by waiting until the ring has completed our requests |
3582 | * emitted over 20 msec ago. | |
3583 | * | |
b962442e EA |
3584 | * Note that if we were to use the current jiffies each time around the loop, |
3585 | * we wouldn't escape the function with any frames outstanding if the time to | |
3586 | * render a frame was over 20ms. | |
3587 | * | |
673a394b EA |
3588 | * This should get us reasonable parallelism between CPU and GPU but also |
3589 | * relatively low latency when blocking on a particular request to finish. | |
3590 | */ | |
40a5f0de | 3591 | static int |
f787a5f5 | 3592 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3593 | { |
f787a5f5 CW |
3594 | struct drm_i915_private *dev_priv = dev->dev_private; |
3595 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3596 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3597 | struct drm_i915_gem_request *request; |
3598 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3599 | unsigned reset_counter; |
f787a5f5 CW |
3600 | u32 seqno = 0; |
3601 | int ret; | |
93533c29 | 3602 | |
308887aa DV |
3603 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3604 | if (ret) | |
3605 | return ret; | |
3606 | ||
3607 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3608 | if (ret) | |
3609 | return ret; | |
e110e8d6 | 3610 | |
1c25595f | 3611 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3612 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3613 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3614 | break; | |
40a5f0de | 3615 | |
f787a5f5 CW |
3616 | ring = request->ring; |
3617 | seqno = request->seqno; | |
b962442e | 3618 | } |
f69061be | 3619 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3620 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3621 | |
f787a5f5 CW |
3622 | if (seqno == 0) |
3623 | return 0; | |
2bc43b5c | 3624 | |
f69061be | 3625 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
f787a5f5 CW |
3626 | if (ret == 0) |
3627 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3628 | |
3629 | return ret; | |
3630 | } | |
3631 | ||
673a394b | 3632 | int |
05394f39 CW |
3633 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3634 | uint32_t alignment, | |
86a1ee26 CW |
3635 | bool map_and_fenceable, |
3636 | bool nonblocking) | |
673a394b | 3637 | { |
673a394b EA |
3638 | int ret; |
3639 | ||
7e81a42e CW |
3640 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3641 | return -EBUSY; | |
ac0c6b5a | 3642 | |
f343c5f6 BW |
3643 | if (i915_gem_obj_ggtt_bound(obj)) { |
3644 | if ((alignment && i915_gem_obj_ggtt_offset(obj) & (alignment - 1)) || | |
05394f39 CW |
3645 | (map_and_fenceable && !obj->map_and_fenceable)) { |
3646 | WARN(obj->pin_count, | |
ae7d49d8 | 3647 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3648 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3649 | " obj->map_and_fenceable=%d\n", |
f343c5f6 | 3650 | i915_gem_obj_ggtt_offset(obj), alignment, |
75e9e915 | 3651 | map_and_fenceable, |
05394f39 | 3652 | obj->map_and_fenceable); |
ac0c6b5a CW |
3653 | ret = i915_gem_object_unbind(obj); |
3654 | if (ret) | |
3655 | return ret; | |
3656 | } | |
3657 | } | |
3658 | ||
f343c5f6 | 3659 | if (!i915_gem_obj_ggtt_bound(obj)) { |
8742267a CW |
3660 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3661 | ||
a00b10c3 | 3662 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3663 | map_and_fenceable, |
3664 | nonblocking); | |
9731129c | 3665 | if (ret) |
673a394b | 3666 | return ret; |
8742267a CW |
3667 | |
3668 | if (!dev_priv->mm.aliasing_ppgtt) | |
3669 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3670 | } |
76446cac | 3671 | |
74898d7e DV |
3672 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3673 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3674 | ||
1b50247a | 3675 | obj->pin_count++; |
6299f992 | 3676 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3677 | |
3678 | return 0; | |
3679 | } | |
3680 | ||
3681 | void | |
05394f39 | 3682 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3683 | { |
05394f39 | 3684 | BUG_ON(obj->pin_count == 0); |
f343c5f6 | 3685 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); |
673a394b | 3686 | |
1b50247a | 3687 | if (--obj->pin_count == 0) |
6299f992 | 3688 | obj->pin_mappable = false; |
673a394b EA |
3689 | } |
3690 | ||
3691 | int | |
3692 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3693 | struct drm_file *file) |
673a394b EA |
3694 | { |
3695 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3696 | struct drm_i915_gem_object *obj; |
673a394b EA |
3697 | int ret; |
3698 | ||
1d7cfea1 CW |
3699 | ret = i915_mutex_lock_interruptible(dev); |
3700 | if (ret) | |
3701 | return ret; | |
673a394b | 3702 | |
05394f39 | 3703 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3704 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3705 | ret = -ENOENT; |
3706 | goto unlock; | |
673a394b | 3707 | } |
673a394b | 3708 | |
05394f39 | 3709 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3710 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3711 | ret = -EINVAL; |
3712 | goto out; | |
3ef94daa CW |
3713 | } |
3714 | ||
05394f39 | 3715 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3716 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3717 | args->handle); | |
1d7cfea1 CW |
3718 | ret = -EINVAL; |
3719 | goto out; | |
79e53945 JB |
3720 | } |
3721 | ||
93be8788 | 3722 | if (obj->user_pin_count == 0) { |
86a1ee26 | 3723 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3724 | if (ret) |
3725 | goto out; | |
673a394b EA |
3726 | } |
3727 | ||
93be8788 CW |
3728 | obj->user_pin_count++; |
3729 | obj->pin_filp = file; | |
3730 | ||
673a394b EA |
3731 | /* XXX - flush the CPU caches for pinned objects |
3732 | * as the X server doesn't manage domains yet | |
3733 | */ | |
e47c68e9 | 3734 | i915_gem_object_flush_cpu_write_domain(obj); |
f343c5f6 | 3735 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 3736 | out: |
05394f39 | 3737 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3738 | unlock: |
673a394b | 3739 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3740 | return ret; |
673a394b EA |
3741 | } |
3742 | ||
3743 | int | |
3744 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3745 | struct drm_file *file) |
673a394b EA |
3746 | { |
3747 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3748 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3749 | int ret; |
673a394b | 3750 | |
1d7cfea1 CW |
3751 | ret = i915_mutex_lock_interruptible(dev); |
3752 | if (ret) | |
3753 | return ret; | |
673a394b | 3754 | |
05394f39 | 3755 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3756 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3757 | ret = -ENOENT; |
3758 | goto unlock; | |
673a394b | 3759 | } |
76c1dec1 | 3760 | |
05394f39 | 3761 | if (obj->pin_filp != file) { |
79e53945 JB |
3762 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3763 | args->handle); | |
1d7cfea1 CW |
3764 | ret = -EINVAL; |
3765 | goto out; | |
79e53945 | 3766 | } |
05394f39 CW |
3767 | obj->user_pin_count--; |
3768 | if (obj->user_pin_count == 0) { | |
3769 | obj->pin_filp = NULL; | |
79e53945 JB |
3770 | i915_gem_object_unpin(obj); |
3771 | } | |
673a394b | 3772 | |
1d7cfea1 | 3773 | out: |
05394f39 | 3774 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3775 | unlock: |
673a394b | 3776 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3777 | return ret; |
673a394b EA |
3778 | } |
3779 | ||
3780 | int | |
3781 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3782 | struct drm_file *file) |
673a394b EA |
3783 | { |
3784 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3785 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3786 | int ret; |
3787 | ||
76c1dec1 | 3788 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3789 | if (ret) |
76c1dec1 | 3790 | return ret; |
673a394b | 3791 | |
05394f39 | 3792 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3793 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3794 | ret = -ENOENT; |
3795 | goto unlock; | |
673a394b | 3796 | } |
d1b851fc | 3797 | |
0be555b6 CW |
3798 | /* Count all active objects as busy, even if they are currently not used |
3799 | * by the gpu. Users of this interface expect objects to eventually | |
3800 | * become non-busy without any further actions, therefore emit any | |
3801 | * necessary flushes here. | |
c4de0a5d | 3802 | */ |
30dfebf3 | 3803 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3804 | |
30dfebf3 | 3805 | args->busy = obj->active; |
e9808edd CW |
3806 | if (obj->ring) { |
3807 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3808 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3809 | } | |
673a394b | 3810 | |
05394f39 | 3811 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3812 | unlock: |
673a394b | 3813 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3814 | return ret; |
673a394b EA |
3815 | } |
3816 | ||
3817 | int | |
3818 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3819 | struct drm_file *file_priv) | |
3820 | { | |
0206e353 | 3821 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3822 | } |
3823 | ||
3ef94daa CW |
3824 | int |
3825 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3826 | struct drm_file *file_priv) | |
3827 | { | |
3828 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3829 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3830 | int ret; |
3ef94daa CW |
3831 | |
3832 | switch (args->madv) { | |
3833 | case I915_MADV_DONTNEED: | |
3834 | case I915_MADV_WILLNEED: | |
3835 | break; | |
3836 | default: | |
3837 | return -EINVAL; | |
3838 | } | |
3839 | ||
1d7cfea1 CW |
3840 | ret = i915_mutex_lock_interruptible(dev); |
3841 | if (ret) | |
3842 | return ret; | |
3843 | ||
05394f39 | 3844 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3845 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3846 | ret = -ENOENT; |
3847 | goto unlock; | |
3ef94daa | 3848 | } |
3ef94daa | 3849 | |
05394f39 | 3850 | if (obj->pin_count) { |
1d7cfea1 CW |
3851 | ret = -EINVAL; |
3852 | goto out; | |
3ef94daa CW |
3853 | } |
3854 | ||
05394f39 CW |
3855 | if (obj->madv != __I915_MADV_PURGED) |
3856 | obj->madv = args->madv; | |
3ef94daa | 3857 | |
6c085a72 CW |
3858 | /* if the object is no longer attached, discard its backing storage */ |
3859 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3860 | i915_gem_object_truncate(obj); |
3861 | ||
05394f39 | 3862 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3863 | |
1d7cfea1 | 3864 | out: |
05394f39 | 3865 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3866 | unlock: |
3ef94daa | 3867 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3868 | return ret; |
3ef94daa CW |
3869 | } |
3870 | ||
37e680a1 CW |
3871 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3872 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3873 | { |
0327d6ba | 3874 | INIT_LIST_HEAD(&obj->mm_list); |
35c20a60 | 3875 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba CW |
3876 | INIT_LIST_HEAD(&obj->ring_list); |
3877 | INIT_LIST_HEAD(&obj->exec_list); | |
2f633156 | 3878 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 3879 | |
37e680a1 CW |
3880 | obj->ops = ops; |
3881 | ||
0327d6ba CW |
3882 | obj->fence_reg = I915_FENCE_REG_NONE; |
3883 | obj->madv = I915_MADV_WILLNEED; | |
3884 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3885 | obj->map_and_fenceable = true; | |
3886 | ||
3887 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3888 | } | |
3889 | ||
37e680a1 CW |
3890 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3891 | .get_pages = i915_gem_object_get_pages_gtt, | |
3892 | .put_pages = i915_gem_object_put_pages_gtt, | |
3893 | }; | |
3894 | ||
05394f39 CW |
3895 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3896 | size_t size) | |
ac52bc56 | 3897 | { |
c397b908 | 3898 | struct drm_i915_gem_object *obj; |
5949eac4 | 3899 | struct address_space *mapping; |
1a240d4d | 3900 | gfp_t mask; |
ac52bc56 | 3901 | |
42dcedd4 | 3902 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
3903 | if (obj == NULL) |
3904 | return NULL; | |
673a394b | 3905 | |
c397b908 | 3906 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 3907 | i915_gem_object_free(obj); |
c397b908 DV |
3908 | return NULL; |
3909 | } | |
673a394b | 3910 | |
bed1ea95 CW |
3911 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3912 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3913 | /* 965gm cannot relocate objects above 4GiB. */ | |
3914 | mask &= ~__GFP_HIGHMEM; | |
3915 | mask |= __GFP_DMA32; | |
3916 | } | |
3917 | ||
496ad9aa | 3918 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 3919 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3920 | |
37e680a1 | 3921 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3922 | |
c397b908 DV |
3923 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3924 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3925 | |
3d29b842 ED |
3926 | if (HAS_LLC(dev)) { |
3927 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3928 | * cache) for about a 10% performance improvement |
3929 | * compared to uncached. Graphics requests other than | |
3930 | * display scanout are coherent with the CPU in | |
3931 | * accessing this cache. This means in this mode we | |
3932 | * don't need to clflush on the CPU side, and on the | |
3933 | * GPU side we only need to flush internal caches to | |
3934 | * get data visible to the CPU. | |
3935 | * | |
3936 | * However, we maintain the display planes as UC, and so | |
3937 | * need to rebind when first used as such. | |
3938 | */ | |
3939 | obj->cache_level = I915_CACHE_LLC; | |
3940 | } else | |
3941 | obj->cache_level = I915_CACHE_NONE; | |
3942 | ||
d861e338 DV |
3943 | trace_i915_gem_object_create(obj); |
3944 | ||
05394f39 | 3945 | return obj; |
c397b908 DV |
3946 | } |
3947 | ||
3948 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3949 | { | |
3950 | BUG(); | |
de151cf6 | 3951 | |
673a394b EA |
3952 | return 0; |
3953 | } | |
3954 | ||
1488fc08 | 3955 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3956 | { |
1488fc08 | 3957 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3958 | struct drm_device *dev = obj->base.dev; |
be72615b | 3959 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3960 | |
26e12f89 CW |
3961 | trace_i915_gem_object_destroy(obj); |
3962 | ||
1488fc08 CW |
3963 | if (obj->phys_obj) |
3964 | i915_gem_detach_phys_object(dev, obj); | |
3965 | ||
3966 | obj->pin_count = 0; | |
3967 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3968 | bool was_interruptible; | |
3969 | ||
3970 | was_interruptible = dev_priv->mm.interruptible; | |
3971 | dev_priv->mm.interruptible = false; | |
3972 | ||
3973 | WARN_ON(i915_gem_object_unbind(obj)); | |
3974 | ||
3975 | dev_priv->mm.interruptible = was_interruptible; | |
3976 | } | |
3977 | ||
1d64ae71 BW |
3978 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
3979 | * before progressing. */ | |
3980 | if (obj->stolen) | |
3981 | i915_gem_object_unpin_pages(obj); | |
3982 | ||
401c29f6 BW |
3983 | if (WARN_ON(obj->pages_pin_count)) |
3984 | obj->pages_pin_count = 0; | |
37e680a1 | 3985 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3986 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 3987 | i915_gem_object_release_stolen(obj); |
de151cf6 | 3988 | |
9da3da66 CW |
3989 | BUG_ON(obj->pages); |
3990 | ||
2f745ad3 CW |
3991 | if (obj->base.import_attach) |
3992 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 3993 | |
05394f39 CW |
3994 | drm_gem_object_release(&obj->base); |
3995 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3996 | |
05394f39 | 3997 | kfree(obj->bit_17); |
42dcedd4 | 3998 | i915_gem_object_free(obj); |
673a394b EA |
3999 | } |
4000 | ||
2f633156 BW |
4001 | struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj, |
4002 | struct i915_address_space *vm) | |
4003 | { | |
4004 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
4005 | if (vma == NULL) | |
4006 | return ERR_PTR(-ENOMEM); | |
4007 | ||
4008 | INIT_LIST_HEAD(&vma->vma_link); | |
4009 | vma->vm = vm; | |
4010 | vma->obj = obj; | |
4011 | ||
4012 | return vma; | |
4013 | } | |
4014 | ||
4015 | void i915_gem_vma_destroy(struct i915_vma *vma) | |
4016 | { | |
4017 | WARN_ON(vma->node.allocated); | |
4018 | kfree(vma); | |
4019 | } | |
4020 | ||
29105ccc CW |
4021 | int |
4022 | i915_gem_idle(struct drm_device *dev) | |
4023 | { | |
4024 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4025 | int ret; | |
28dfe52a | 4026 | |
db1b76ca | 4027 | if (dev_priv->ums.mm_suspended) { |
29105ccc CW |
4028 | mutex_unlock(&dev->struct_mutex); |
4029 | return 0; | |
28dfe52a EA |
4030 | } |
4031 | ||
b2da9fe5 | 4032 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4033 | if (ret) { |
4034 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4035 | return ret; |
6dbe2772 | 4036 | } |
b2da9fe5 | 4037 | i915_gem_retire_requests(dev); |
673a394b | 4038 | |
29105ccc | 4039 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4040 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4041 | i915_gem_evict_everything(dev); |
29105ccc | 4042 | |
99584db3 | 4043 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
4044 | |
4045 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4046 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4047 | |
29105ccc CW |
4048 | /* Cancel the retire work handler, which should be idle now. */ |
4049 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4050 | ||
673a394b EA |
4051 | return 0; |
4052 | } | |
4053 | ||
b9524a1e BW |
4054 | void i915_gem_l3_remap(struct drm_device *dev) |
4055 | { | |
4056 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4057 | u32 misccpctl; | |
4058 | int i; | |
4059 | ||
eb32e458 | 4060 | if (!HAS_L3_GPU_CACHE(dev)) |
b9524a1e BW |
4061 | return; |
4062 | ||
a4da4fa4 | 4063 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
4064 | return; |
4065 | ||
4066 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
4067 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
4068 | POSTING_READ(GEN7_MISCCPCTL); | |
4069 | ||
4070 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
4071 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 4072 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
4073 | DRM_DEBUG("0x%x was already programmed to %x\n", |
4074 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 4075 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 4076 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 4077 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
4078 | } |
4079 | ||
4080 | /* Make sure all the writes land before disabling dop clock gating */ | |
4081 | POSTING_READ(GEN7_L3LOG_BASE); | |
4082 | ||
4083 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
4084 | } | |
4085 | ||
f691e2f4 DV |
4086 | void i915_gem_init_swizzling(struct drm_device *dev) |
4087 | { | |
4088 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4089 | ||
11782b02 | 4090 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4091 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4092 | return; | |
4093 | ||
4094 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4095 | DISP_TILE_SURFACE_SWIZZLING); | |
4096 | ||
11782b02 DV |
4097 | if (IS_GEN5(dev)) |
4098 | return; | |
4099 | ||
f691e2f4 DV |
4100 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4101 | if (IS_GEN6(dev)) | |
6b26c86d | 4102 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4103 | else if (IS_GEN7(dev)) |
6b26c86d | 4104 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
4105 | else |
4106 | BUG(); | |
f691e2f4 | 4107 | } |
e21af88d | 4108 | |
67b1b571 CW |
4109 | static bool |
4110 | intel_enable_blt(struct drm_device *dev) | |
4111 | { | |
4112 | if (!HAS_BLT(dev)) | |
4113 | return false; | |
4114 | ||
4115 | /* The blitter was dysfunctional on early prototypes */ | |
4116 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4117 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4118 | " graphics performance will be degraded.\n"); | |
4119 | return false; | |
4120 | } | |
4121 | ||
4122 | return true; | |
4123 | } | |
4124 | ||
4fc7c971 | 4125 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4126 | { |
4fc7c971 | 4127 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4128 | int ret; |
68f95ba9 | 4129 | |
5c1143bb | 4130 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4131 | if (ret) |
b6913e4b | 4132 | return ret; |
68f95ba9 CW |
4133 | |
4134 | if (HAS_BSD(dev)) { | |
5c1143bb | 4135 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4136 | if (ret) |
4137 | goto cleanup_render_ring; | |
d1b851fc | 4138 | } |
68f95ba9 | 4139 | |
67b1b571 | 4140 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4141 | ret = intel_init_blt_ring_buffer(dev); |
4142 | if (ret) | |
4143 | goto cleanup_bsd_ring; | |
4144 | } | |
4145 | ||
9a8a2213 BW |
4146 | if (HAS_VEBOX(dev)) { |
4147 | ret = intel_init_vebox_ring_buffer(dev); | |
4148 | if (ret) | |
4149 | goto cleanup_blt_ring; | |
4150 | } | |
4151 | ||
4152 | ||
99433931 | 4153 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4154 | if (ret) |
9a8a2213 | 4155 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4156 | |
4157 | return 0; | |
4158 | ||
9a8a2213 BW |
4159 | cleanup_vebox_ring: |
4160 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4161 | cleanup_blt_ring: |
4162 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4163 | cleanup_bsd_ring: | |
4164 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4165 | cleanup_render_ring: | |
4166 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4167 | ||
4168 | return ret; | |
4169 | } | |
4170 | ||
4171 | int | |
4172 | i915_gem_init_hw(struct drm_device *dev) | |
4173 | { | |
4174 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4175 | int ret; | |
4176 | ||
4177 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4178 | return -EIO; | |
4179 | ||
59124506 | 4180 | if (dev_priv->ellc_size) |
05e21cc4 | 4181 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4182 | |
88a2b2a3 BW |
4183 | if (HAS_PCH_NOP(dev)) { |
4184 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4185 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4186 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4187 | } | |
4188 | ||
4fc7c971 BW |
4189 | i915_gem_l3_remap(dev); |
4190 | ||
4191 | i915_gem_init_swizzling(dev); | |
4192 | ||
4193 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4194 | if (ret) |
4195 | return ret; | |
4196 | ||
254f965c BW |
4197 | /* |
4198 | * XXX: There was some w/a described somewhere suggesting loading | |
4199 | * contexts before PPGTT. | |
4200 | */ | |
4201 | i915_gem_context_init(dev); | |
b7c36d25 BW |
4202 | if (dev_priv->mm.aliasing_ppgtt) { |
4203 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4204 | if (ret) { | |
4205 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4206 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4207 | } | |
4208 | } | |
e21af88d | 4209 | |
68f95ba9 | 4210 | return 0; |
8187a2b7 ZN |
4211 | } |
4212 | ||
1070a42b CW |
4213 | int i915_gem_init(struct drm_device *dev) |
4214 | { | |
4215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4216 | int ret; |
4217 | ||
1070a42b | 4218 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4219 | |
4220 | if (IS_VALLEYVIEW(dev)) { | |
4221 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4222 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4223 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4224 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4225 | } | |
4226 | ||
d7e5008f | 4227 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4228 | |
1070a42b CW |
4229 | ret = i915_gem_init_hw(dev); |
4230 | mutex_unlock(&dev->struct_mutex); | |
4231 | if (ret) { | |
4232 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4233 | return ret; | |
4234 | } | |
4235 | ||
53ca26ca DV |
4236 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4237 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4238 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4239 | return 0; |
4240 | } | |
4241 | ||
8187a2b7 ZN |
4242 | void |
4243 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4244 | { | |
4245 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4246 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4247 | int i; |
8187a2b7 | 4248 | |
b4519513 CW |
4249 | for_each_ring(ring, dev_priv, i) |
4250 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4251 | } |
4252 | ||
673a394b EA |
4253 | int |
4254 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4255 | struct drm_file *file_priv) | |
4256 | { | |
db1b76ca | 4257 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4258 | int ret; |
673a394b | 4259 | |
79e53945 JB |
4260 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4261 | return 0; | |
4262 | ||
1f83fee0 | 4263 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4264 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4265 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4266 | } |
4267 | ||
673a394b | 4268 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4269 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4270 | |
f691e2f4 | 4271 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4272 | if (ret != 0) { |
4273 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4274 | return ret; |
d816f6ac | 4275 | } |
9bb2d6f9 | 4276 | |
5cef07e1 | 4277 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4278 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4279 | |
5f35308b CW |
4280 | ret = drm_irq_install(dev); |
4281 | if (ret) | |
4282 | goto cleanup_ringbuffer; | |
dbb19d30 | 4283 | |
673a394b | 4284 | return 0; |
5f35308b CW |
4285 | |
4286 | cleanup_ringbuffer: | |
4287 | mutex_lock(&dev->struct_mutex); | |
4288 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4289 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4290 | mutex_unlock(&dev->struct_mutex); |
4291 | ||
4292 | return ret; | |
673a394b EA |
4293 | } |
4294 | ||
4295 | int | |
4296 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4297 | struct drm_file *file_priv) | |
4298 | { | |
db1b76ca DV |
4299 | struct drm_i915_private *dev_priv = dev->dev_private; |
4300 | int ret; | |
4301 | ||
79e53945 JB |
4302 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4303 | return 0; | |
4304 | ||
dbb19d30 | 4305 | drm_irq_uninstall(dev); |
db1b76ca DV |
4306 | |
4307 | mutex_lock(&dev->struct_mutex); | |
4308 | ret = i915_gem_idle(dev); | |
4309 | ||
4310 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4311 | * We need to replace this with a semaphore, or something. | |
4312 | * And not confound ums.mm_suspended! | |
4313 | */ | |
4314 | if (ret != 0) | |
4315 | dev_priv->ums.mm_suspended = 1; | |
4316 | mutex_unlock(&dev->struct_mutex); | |
4317 | ||
4318 | return ret; | |
673a394b EA |
4319 | } |
4320 | ||
4321 | void | |
4322 | i915_gem_lastclose(struct drm_device *dev) | |
4323 | { | |
4324 | int ret; | |
673a394b | 4325 | |
e806b495 EA |
4326 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4327 | return; | |
4328 | ||
db1b76ca | 4329 | mutex_lock(&dev->struct_mutex); |
6dbe2772 KP |
4330 | ret = i915_gem_idle(dev); |
4331 | if (ret) | |
4332 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
db1b76ca | 4333 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
4334 | } |
4335 | ||
64193406 CW |
4336 | static void |
4337 | init_ring_lists(struct intel_ring_buffer *ring) | |
4338 | { | |
4339 | INIT_LIST_HEAD(&ring->active_list); | |
4340 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4341 | } |
4342 | ||
fc8c067e BW |
4343 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
4344 | struct i915_address_space *vm) | |
4345 | { | |
4346 | vm->dev = dev_priv->dev; | |
4347 | INIT_LIST_HEAD(&vm->active_list); | |
4348 | INIT_LIST_HEAD(&vm->inactive_list); | |
4349 | INIT_LIST_HEAD(&vm->global_link); | |
4350 | list_add(&vm->global_link, &dev_priv->vm_list); | |
4351 | } | |
4352 | ||
673a394b EA |
4353 | void |
4354 | i915_gem_load(struct drm_device *dev) | |
4355 | { | |
4356 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4357 | int i; |
4358 | ||
4359 | dev_priv->slab = | |
4360 | kmem_cache_create("i915_gem_object", | |
4361 | sizeof(struct drm_i915_gem_object), 0, | |
4362 | SLAB_HWCACHE_ALIGN, | |
4363 | NULL); | |
673a394b | 4364 | |
fc8c067e BW |
4365 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4366 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4367 | ||
6c085a72 CW |
4368 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4369 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4370 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4371 | for (i = 0; i < I915_NUM_RINGS; i++) |
4372 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4373 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4374 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4375 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4376 | i915_gem_retire_work_handler); | |
1f83fee0 | 4377 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4378 | |
94400120 DA |
4379 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4380 | if (IS_GEN3(dev)) { | |
50743298 DV |
4381 | I915_WRITE(MI_ARB_STATE, |
4382 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4383 | } |
4384 | ||
72bfa19c CW |
4385 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4386 | ||
de151cf6 | 4387 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4388 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4389 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4390 | |
42b5aeab VS |
4391 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4392 | dev_priv->num_fence_regs = 32; | |
4393 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4394 | dev_priv->num_fence_regs = 16; |
4395 | else | |
4396 | dev_priv->num_fence_regs = 8; | |
4397 | ||
b5aa8a0f | 4398 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4399 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4400 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4401 | |
673a394b | 4402 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4403 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4404 | |
ce453d81 CW |
4405 | dev_priv->mm.interruptible = true; |
4406 | ||
17250b71 CW |
4407 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4408 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4409 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4410 | } |
71acb5eb DA |
4411 | |
4412 | /* | |
4413 | * Create a physically contiguous memory object for this object | |
4414 | * e.g. for cursor + overlay regs | |
4415 | */ | |
995b6762 CW |
4416 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4417 | int id, int size, int align) | |
71acb5eb DA |
4418 | { |
4419 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4420 | struct drm_i915_gem_phys_object *phys_obj; | |
4421 | int ret; | |
4422 | ||
4423 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4424 | return 0; | |
4425 | ||
9a298b2a | 4426 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4427 | if (!phys_obj) |
4428 | return -ENOMEM; | |
4429 | ||
4430 | phys_obj->id = id; | |
4431 | ||
6eeefaf3 | 4432 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4433 | if (!phys_obj->handle) { |
4434 | ret = -ENOMEM; | |
4435 | goto kfree_obj; | |
4436 | } | |
4437 | #ifdef CONFIG_X86 | |
4438 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4439 | #endif | |
4440 | ||
4441 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4442 | ||
4443 | return 0; | |
4444 | kfree_obj: | |
9a298b2a | 4445 | kfree(phys_obj); |
71acb5eb DA |
4446 | return ret; |
4447 | } | |
4448 | ||
995b6762 | 4449 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4450 | { |
4451 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4452 | struct drm_i915_gem_phys_object *phys_obj; | |
4453 | ||
4454 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4455 | return; | |
4456 | ||
4457 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4458 | if (phys_obj->cur_obj) { | |
4459 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4460 | } | |
4461 | ||
4462 | #ifdef CONFIG_X86 | |
4463 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4464 | #endif | |
4465 | drm_pci_free(dev, phys_obj->handle); | |
4466 | kfree(phys_obj); | |
4467 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4468 | } | |
4469 | ||
4470 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4471 | { | |
4472 | int i; | |
4473 | ||
260883c8 | 4474 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4475 | i915_gem_free_phys_object(dev, i); |
4476 | } | |
4477 | ||
4478 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4479 | struct drm_i915_gem_object *obj) |
71acb5eb | 4480 | { |
496ad9aa | 4481 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4482 | char *vaddr; |
71acb5eb | 4483 | int i; |
71acb5eb DA |
4484 | int page_count; |
4485 | ||
05394f39 | 4486 | if (!obj->phys_obj) |
71acb5eb | 4487 | return; |
05394f39 | 4488 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4489 | |
05394f39 | 4490 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4491 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4492 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4493 | if (!IS_ERR(page)) { |
4494 | char *dst = kmap_atomic(page); | |
4495 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4496 | kunmap_atomic(dst); | |
4497 | ||
4498 | drm_clflush_pages(&page, 1); | |
4499 | ||
4500 | set_page_dirty(page); | |
4501 | mark_page_accessed(page); | |
4502 | page_cache_release(page); | |
4503 | } | |
71acb5eb | 4504 | } |
e76e9aeb | 4505 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4506 | |
05394f39 CW |
4507 | obj->phys_obj->cur_obj = NULL; |
4508 | obj->phys_obj = NULL; | |
71acb5eb DA |
4509 | } |
4510 | ||
4511 | int | |
4512 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4513 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4514 | int id, |
4515 | int align) | |
71acb5eb | 4516 | { |
496ad9aa | 4517 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4518 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4519 | int ret = 0; |
4520 | int page_count; | |
4521 | int i; | |
4522 | ||
4523 | if (id > I915_MAX_PHYS_OBJECT) | |
4524 | return -EINVAL; | |
4525 | ||
05394f39 CW |
4526 | if (obj->phys_obj) { |
4527 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4528 | return 0; |
4529 | i915_gem_detach_phys_object(dev, obj); | |
4530 | } | |
4531 | ||
71acb5eb DA |
4532 | /* create a new object */ |
4533 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4534 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4535 | obj->base.size, align); |
71acb5eb | 4536 | if (ret) { |
05394f39 CW |
4537 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4538 | id, obj->base.size); | |
e5281ccd | 4539 | return ret; |
71acb5eb DA |
4540 | } |
4541 | } | |
4542 | ||
4543 | /* bind to the object */ | |
05394f39 CW |
4544 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4545 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4546 | |
05394f39 | 4547 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4548 | |
4549 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4550 | struct page *page; |
4551 | char *dst, *src; | |
4552 | ||
5949eac4 | 4553 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4554 | if (IS_ERR(page)) |
4555 | return PTR_ERR(page); | |
71acb5eb | 4556 | |
ff75b9bc | 4557 | src = kmap_atomic(page); |
05394f39 | 4558 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4559 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4560 | kunmap_atomic(src); |
71acb5eb | 4561 | |
e5281ccd CW |
4562 | mark_page_accessed(page); |
4563 | page_cache_release(page); | |
4564 | } | |
d78b47b9 | 4565 | |
71acb5eb | 4566 | return 0; |
71acb5eb DA |
4567 | } |
4568 | ||
4569 | static int | |
05394f39 CW |
4570 | i915_gem_phys_pwrite(struct drm_device *dev, |
4571 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4572 | struct drm_i915_gem_pwrite *args, |
4573 | struct drm_file *file_priv) | |
4574 | { | |
05394f39 | 4575 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4576 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4577 | |
b47b30cc CW |
4578 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4579 | unsigned long unwritten; | |
4580 | ||
4581 | /* The physical object once assigned is fixed for the lifetime | |
4582 | * of the obj, so we can safely drop the lock and continue | |
4583 | * to access vaddr. | |
4584 | */ | |
4585 | mutex_unlock(&dev->struct_mutex); | |
4586 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4587 | mutex_lock(&dev->struct_mutex); | |
4588 | if (unwritten) | |
4589 | return -EFAULT; | |
4590 | } | |
71acb5eb | 4591 | |
e76e9aeb | 4592 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4593 | return 0; |
4594 | } | |
b962442e | 4595 | |
f787a5f5 | 4596 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4597 | { |
f787a5f5 | 4598 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4599 | |
4600 | /* Clean up our request list when the client is going away, so that | |
4601 | * later retire_requests won't dereference our soon-to-be-gone | |
4602 | * file_priv. | |
4603 | */ | |
1c25595f | 4604 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4605 | while (!list_empty(&file_priv->mm.request_list)) { |
4606 | struct drm_i915_gem_request *request; | |
4607 | ||
4608 | request = list_first_entry(&file_priv->mm.request_list, | |
4609 | struct drm_i915_gem_request, | |
4610 | client_list); | |
4611 | list_del(&request->client_list); | |
4612 | request->file_priv = NULL; | |
4613 | } | |
1c25595f | 4614 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4615 | } |
31169714 | 4616 | |
5774506f CW |
4617 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4618 | { | |
4619 | if (!mutex_is_locked(mutex)) | |
4620 | return false; | |
4621 | ||
4622 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4623 | return mutex->owner == task; | |
4624 | #else | |
4625 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4626 | return false; | |
4627 | #endif | |
4628 | } | |
4629 | ||
31169714 | 4630 | static int |
1495f230 | 4631 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4632 | { |
17250b71 CW |
4633 | struct drm_i915_private *dev_priv = |
4634 | container_of(shrinker, | |
4635 | struct drm_i915_private, | |
4636 | mm.inactive_shrinker); | |
4637 | struct drm_device *dev = dev_priv->dev; | |
5cef07e1 | 4638 | struct i915_address_space *vm = &dev_priv->gtt.base; |
6c085a72 | 4639 | struct drm_i915_gem_object *obj; |
1495f230 | 4640 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4641 | bool unlock = true; |
17250b71 CW |
4642 | int cnt; |
4643 | ||
5774506f CW |
4644 | if (!mutex_trylock(&dev->struct_mutex)) { |
4645 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4646 | return 0; | |
4647 | ||
677feac2 DV |
4648 | if (dev_priv->mm.shrinker_no_lock_stealing) |
4649 | return 0; | |
4650 | ||
5774506f CW |
4651 | unlock = false; |
4652 | } | |
31169714 | 4653 | |
6c085a72 CW |
4654 | if (nr_to_scan) { |
4655 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
93927ca5 DV |
4656 | if (nr_to_scan > 0) |
4657 | nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan, | |
4658 | false); | |
6c085a72 CW |
4659 | if (nr_to_scan > 0) |
4660 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4661 | } |
4662 | ||
17250b71 | 4663 | cnt = 0; |
35c20a60 | 4664 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 CW |
4665 | if (obj->pages_pin_count == 0) |
4666 | cnt += obj->base.size >> PAGE_SHIFT; | |
cb54b53a | 4667 | list_for_each_entry(obj, &vm->inactive_list, mm_list) |
a5570178 | 4668 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4669 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4670 | |
5774506f CW |
4671 | if (unlock) |
4672 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4673 | return cnt; |
31169714 | 4674 | } |
a70a3148 BW |
4675 | |
4676 | /* All the new VM stuff */ | |
4677 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4678 | struct i915_address_space *vm) | |
4679 | { | |
4680 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4681 | struct i915_vma *vma; | |
4682 | ||
4683 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
4684 | vm = &dev_priv->gtt.base; | |
4685 | ||
4686 | BUG_ON(list_empty(&o->vma_list)); | |
4687 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4688 | if (vma->vm == vm) | |
4689 | return vma->node.start; | |
4690 | ||
4691 | } | |
4692 | return -1; | |
4693 | } | |
4694 | ||
4695 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4696 | struct i915_address_space *vm) | |
4697 | { | |
4698 | struct i915_vma *vma; | |
4699 | ||
4700 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
4701 | if (vma->vm == vm) | |
4702 | return true; | |
4703 | ||
4704 | return false; | |
4705 | } | |
4706 | ||
4707 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
4708 | { | |
4709 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4710 | struct i915_address_space *vm; | |
4711 | ||
4712 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) | |
4713 | if (i915_gem_obj_bound(o, vm)) | |
4714 | return true; | |
4715 | ||
4716 | return false; | |
4717 | } | |
4718 | ||
4719 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
4720 | struct i915_address_space *vm) | |
4721 | { | |
4722 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4723 | struct i915_vma *vma; | |
4724 | ||
4725 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
4726 | vm = &dev_priv->gtt.base; | |
4727 | ||
4728 | BUG_ON(list_empty(&o->vma_list)); | |
4729 | ||
4730 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
4731 | if (vma->vm == vm) | |
4732 | return vma->node.size; | |
4733 | ||
4734 | return 0; | |
4735 | } | |
4736 | ||
4737 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
4738 | struct i915_address_space *vm) | |
4739 | { | |
4740 | struct i915_vma *vma; | |
4741 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4742 | if (vma->vm == vm) | |
4743 | return vma; | |
4744 | ||
4745 | return NULL; | |
4746 | } |