Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
42 | unsigned alignment, | |
86a1ee26 CW |
43 | bool map_and_fenceable, |
44 | bool nonblocking); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
6c085a72 CW |
58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 61 | |
61050808 CW |
62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
63 | { | |
64 | if (obj->tiling_mode) | |
65 | i915_gem_release_mmap(obj); | |
66 | ||
67 | /* As we do not have an associated fence register, we will force | |
68 | * a tiling change if we ever need to acquire one. | |
69 | */ | |
5d82e3e6 | 70 | obj->fence_dirty = false; |
61050808 CW |
71 | obj->fence_reg = I915_FENCE_REG_NONE; |
72 | } | |
73 | ||
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
21dd3734 CW |
89 | static int |
90 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
91 | { |
92 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93 | struct completion *x = &dev_priv->error_completion; | |
94 | unsigned long flags; | |
95 | int ret; | |
96 | ||
97 | if (!atomic_read(&dev_priv->mm.wedged)) | |
98 | return 0; | |
99 | ||
0a6759c6 DV |
100 | /* |
101 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
102 | * userspace. If it takes that long something really bad is going on and | |
103 | * we should simply try to bail out and fail as gracefully as possible. | |
104 | */ | |
105 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
106 | if (ret == 0) { | |
107 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
108 | return -EIO; | |
109 | } else if (ret < 0) { | |
30dbf0c0 | 110 | return ret; |
0a6759c6 | 111 | } |
30dbf0c0 | 112 | |
21dd3734 CW |
113 | if (atomic_read(&dev_priv->mm.wedged)) { |
114 | /* GPU is hung, bump the completion count to account for | |
115 | * the token we just consumed so that we never hit zero and | |
116 | * end up waiting upon a subsequent completion event that | |
117 | * will never happen. | |
118 | */ | |
119 | spin_lock_irqsave(&x->wait.lock, flags); | |
120 | x->done++; | |
121 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
122 | } | |
123 | return 0; | |
30dbf0c0 CW |
124 | } |
125 | ||
54cf91dc | 126 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 127 | { |
76c1dec1 CW |
128 | int ret; |
129 | ||
21dd3734 | 130 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
131 | if (ret) |
132 | return ret; | |
133 | ||
134 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
135 | if (ret) | |
136 | return ret; | |
137 | ||
23bc5982 | 138 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
139 | return 0; |
140 | } | |
30dbf0c0 | 141 | |
7d1c4804 | 142 | static inline bool |
05394f39 | 143 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 144 | { |
6c085a72 | 145 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
146 | } |
147 | ||
79e53945 JB |
148 | int |
149 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 150 | struct drm_file *file) |
79e53945 JB |
151 | { |
152 | struct drm_i915_gem_init *args = data; | |
2021746e | 153 | |
7bb6fb8d DV |
154 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
155 | return -ENODEV; | |
156 | ||
2021746e CW |
157 | if (args->gtt_start >= args->gtt_end || |
158 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
159 | return -EINVAL; | |
79e53945 | 160 | |
f534bc0b DV |
161 | /* GEM with user mode setting was never supported on ilk and later. */ |
162 | if (INTEL_INFO(dev)->gen >= 5) | |
163 | return -ENODEV; | |
164 | ||
79e53945 | 165 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
166 | i915_gem_init_global_gtt(dev, args->gtt_start, |
167 | args->gtt_end, args->gtt_end); | |
673a394b EA |
168 | mutex_unlock(&dev->struct_mutex); |
169 | ||
2021746e | 170 | return 0; |
673a394b EA |
171 | } |
172 | ||
5a125c3c EA |
173 | int |
174 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 175 | struct drm_file *file) |
5a125c3c | 176 | { |
73aa808f | 177 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 178 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
179 | struct drm_i915_gem_object *obj; |
180 | size_t pinned; | |
5a125c3c | 181 | |
6299f992 | 182 | pinned = 0; |
73aa808f | 183 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 184 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
185 | if (obj->pin_count) |
186 | pinned += obj->gtt_space->size; | |
73aa808f | 187 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 188 | |
6299f992 | 189 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 190 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 191 | |
5a125c3c EA |
192 | return 0; |
193 | } | |
194 | ||
ff72145b DA |
195 | static int |
196 | i915_gem_create(struct drm_file *file, | |
197 | struct drm_device *dev, | |
198 | uint64_t size, | |
199 | uint32_t *handle_p) | |
673a394b | 200 | { |
05394f39 | 201 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
202 | int ret; |
203 | u32 handle; | |
673a394b | 204 | |
ff72145b | 205 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
206 | if (size == 0) |
207 | return -EINVAL; | |
673a394b EA |
208 | |
209 | /* Allocate the new object */ | |
ff72145b | 210 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
211 | if (obj == NULL) |
212 | return -ENOMEM; | |
213 | ||
05394f39 | 214 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 215 | if (ret) { |
05394f39 CW |
216 | drm_gem_object_release(&obj->base); |
217 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 218 | kfree(obj); |
673a394b | 219 | return ret; |
1dfd9754 | 220 | } |
673a394b | 221 | |
202f2fef | 222 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 223 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
224 | trace_i915_gem_object_create(obj); |
225 | ||
ff72145b | 226 | *handle_p = handle; |
673a394b EA |
227 | return 0; |
228 | } | |
229 | ||
ff72145b DA |
230 | int |
231 | i915_gem_dumb_create(struct drm_file *file, | |
232 | struct drm_device *dev, | |
233 | struct drm_mode_create_dumb *args) | |
234 | { | |
235 | /* have to work out size/pitch and return them */ | |
ed0291fd | 236 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
237 | args->size = args->pitch * args->height; |
238 | return i915_gem_create(file, dev, | |
239 | args->size, &args->handle); | |
240 | } | |
241 | ||
242 | int i915_gem_dumb_destroy(struct drm_file *file, | |
243 | struct drm_device *dev, | |
244 | uint32_t handle) | |
245 | { | |
246 | return drm_gem_handle_delete(file, handle); | |
247 | } | |
248 | ||
249 | /** | |
250 | * Creates a new mm object and returns a handle to it. | |
251 | */ | |
252 | int | |
253 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
254 | struct drm_file *file) | |
255 | { | |
256 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 257 | |
ff72145b DA |
258 | return i915_gem_create(file, dev, |
259 | args->size, &args->handle); | |
260 | } | |
261 | ||
05394f39 | 262 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 263 | { |
05394f39 | 264 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
265 | |
266 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 267 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
268 | } |
269 | ||
8461d226 DV |
270 | static inline int |
271 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
272 | const char *gpu_vaddr, int gpu_offset, | |
273 | int length) | |
274 | { | |
275 | int ret, cpu_offset = 0; | |
276 | ||
277 | while (length > 0) { | |
278 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
279 | int this_length = min(cacheline_end - gpu_offset, length); | |
280 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
281 | ||
282 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
283 | gpu_vaddr + swizzled_gpu_offset, | |
284 | this_length); | |
285 | if (ret) | |
286 | return ret + length; | |
287 | ||
288 | cpu_offset += this_length; | |
289 | gpu_offset += this_length; | |
290 | length -= this_length; | |
291 | } | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
8c59967c | 296 | static inline int |
4f0c7cfb BW |
297 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
298 | const char __user *cpu_vaddr, | |
8c59967c DV |
299 | int length) |
300 | { | |
301 | int ret, cpu_offset = 0; | |
302 | ||
303 | while (length > 0) { | |
304 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
305 | int this_length = min(cacheline_end - gpu_offset, length); | |
306 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
307 | ||
308 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
309 | cpu_vaddr + cpu_offset, | |
310 | this_length); | |
311 | if (ret) | |
312 | return ret + length; | |
313 | ||
314 | cpu_offset += this_length; | |
315 | gpu_offset += this_length; | |
316 | length -= this_length; | |
317 | } | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
d174bd64 DV |
322 | /* Per-page copy function for the shmem pread fastpath. |
323 | * Flushes invalid cachelines before reading the target if | |
324 | * needs_clflush is set. */ | |
eb01459f | 325 | static int |
d174bd64 DV |
326 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
327 | char __user *user_data, | |
328 | bool page_do_bit17_swizzling, bool needs_clflush) | |
329 | { | |
330 | char *vaddr; | |
331 | int ret; | |
332 | ||
e7e58eb5 | 333 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
334 | return -EINVAL; |
335 | ||
336 | vaddr = kmap_atomic(page); | |
337 | if (needs_clflush) | |
338 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
339 | page_length); | |
340 | ret = __copy_to_user_inatomic(user_data, | |
341 | vaddr + shmem_page_offset, | |
342 | page_length); | |
343 | kunmap_atomic(vaddr); | |
344 | ||
f60d7f0c | 345 | return ret ? -EFAULT : 0; |
d174bd64 DV |
346 | } |
347 | ||
23c18c71 DV |
348 | static void |
349 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
350 | bool swizzled) | |
351 | { | |
e7e58eb5 | 352 | if (unlikely(swizzled)) { |
23c18c71 DV |
353 | unsigned long start = (unsigned long) addr; |
354 | unsigned long end = (unsigned long) addr + length; | |
355 | ||
356 | /* For swizzling simply ensure that we always flush both | |
357 | * channels. Lame, but simple and it works. Swizzled | |
358 | * pwrite/pread is far from a hotpath - current userspace | |
359 | * doesn't use it at all. */ | |
360 | start = round_down(start, 128); | |
361 | end = round_up(end, 128); | |
362 | ||
363 | drm_clflush_virt_range((void *)start, end - start); | |
364 | } else { | |
365 | drm_clflush_virt_range(addr, length); | |
366 | } | |
367 | ||
368 | } | |
369 | ||
d174bd64 DV |
370 | /* Only difference to the fast-path function is that this can handle bit17 |
371 | * and uses non-atomic copy and kmap functions. */ | |
372 | static int | |
373 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
374 | char __user *user_data, | |
375 | bool page_do_bit17_swizzling, bool needs_clflush) | |
376 | { | |
377 | char *vaddr; | |
378 | int ret; | |
379 | ||
380 | vaddr = kmap(page); | |
381 | if (needs_clflush) | |
23c18c71 DV |
382 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
383 | page_length, | |
384 | page_do_bit17_swizzling); | |
d174bd64 DV |
385 | |
386 | if (page_do_bit17_swizzling) | |
387 | ret = __copy_to_user_swizzled(user_data, | |
388 | vaddr, shmem_page_offset, | |
389 | page_length); | |
390 | else | |
391 | ret = __copy_to_user(user_data, | |
392 | vaddr + shmem_page_offset, | |
393 | page_length); | |
394 | kunmap(page); | |
395 | ||
f60d7f0c | 396 | return ret ? - EFAULT : 0; |
d174bd64 DV |
397 | } |
398 | ||
eb01459f | 399 | static int |
dbf7bff0 DV |
400 | i915_gem_shmem_pread(struct drm_device *dev, |
401 | struct drm_i915_gem_object *obj, | |
402 | struct drm_i915_gem_pread *args, | |
403 | struct drm_file *file) | |
eb01459f | 404 | { |
8461d226 | 405 | char __user *user_data; |
eb01459f | 406 | ssize_t remain; |
8461d226 | 407 | loff_t offset; |
eb2c0c81 | 408 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 409 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 410 | int hit_slowpath = 0; |
96d79b52 | 411 | int prefaulted = 0; |
8489731c | 412 | int needs_clflush = 0; |
9da3da66 CW |
413 | struct scatterlist *sg; |
414 | int i; | |
eb01459f | 415 | |
8461d226 | 416 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
417 | remain = args->size; |
418 | ||
8461d226 | 419 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 420 | |
8489731c DV |
421 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
422 | /* If we're not in the cpu read domain, set ourself into the gtt | |
423 | * read domain and manually flush cachelines (if required). This | |
424 | * optimizes for the case when the gpu will dirty the data | |
425 | * anyway again before the next pread happens. */ | |
426 | if (obj->cache_level == I915_CACHE_NONE) | |
427 | needs_clflush = 1; | |
6c085a72 CW |
428 | if (obj->gtt_space) { |
429 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
430 | if (ret) | |
431 | return ret; | |
432 | } | |
8489731c | 433 | } |
eb01459f | 434 | |
f60d7f0c CW |
435 | ret = i915_gem_object_get_pages(obj); |
436 | if (ret) | |
437 | return ret; | |
438 | ||
439 | i915_gem_object_pin_pages(obj); | |
440 | ||
8461d226 | 441 | offset = args->offset; |
eb01459f | 442 | |
9da3da66 | 443 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd CW |
444 | struct page *page; |
445 | ||
9da3da66 CW |
446 | if (i < offset >> PAGE_SHIFT) |
447 | continue; | |
448 | ||
449 | if (remain <= 0) | |
450 | break; | |
451 | ||
eb01459f EA |
452 | /* Operation in this page |
453 | * | |
eb01459f | 454 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
455 | * page_length = bytes to copy for this page |
456 | */ | |
c8cbbb8b | 457 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
458 | page_length = remain; |
459 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
460 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 461 | |
9da3da66 | 462 | page = sg_page(sg); |
8461d226 DV |
463 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
464 | (page_to_phys(page) & (1 << 17)) != 0; | |
465 | ||
d174bd64 DV |
466 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
467 | user_data, page_do_bit17_swizzling, | |
468 | needs_clflush); | |
469 | if (ret == 0) | |
470 | goto next_page; | |
dbf7bff0 DV |
471 | |
472 | hit_slowpath = 1; | |
dbf7bff0 DV |
473 | mutex_unlock(&dev->struct_mutex); |
474 | ||
96d79b52 | 475 | if (!prefaulted) { |
f56f821f | 476 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
477 | /* Userspace is tricking us, but we've already clobbered |
478 | * its pages with the prefault and promised to write the | |
479 | * data up to the first fault. Hence ignore any errors | |
480 | * and just continue. */ | |
481 | (void)ret; | |
482 | prefaulted = 1; | |
483 | } | |
eb01459f | 484 | |
d174bd64 DV |
485 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
486 | user_data, page_do_bit17_swizzling, | |
487 | needs_clflush); | |
eb01459f | 488 | |
dbf7bff0 | 489 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 490 | |
dbf7bff0 | 491 | next_page: |
e5281ccd | 492 | mark_page_accessed(page); |
e5281ccd | 493 | |
f60d7f0c | 494 | if (ret) |
8461d226 | 495 | goto out; |
8461d226 | 496 | |
eb01459f | 497 | remain -= page_length; |
8461d226 | 498 | user_data += page_length; |
eb01459f EA |
499 | offset += page_length; |
500 | } | |
501 | ||
4f27b75d | 502 | out: |
f60d7f0c CW |
503 | i915_gem_object_unpin_pages(obj); |
504 | ||
dbf7bff0 DV |
505 | if (hit_slowpath) { |
506 | /* Fixup: Kill any reinstated backing storage pages */ | |
507 | if (obj->madv == __I915_MADV_PURGED) | |
508 | i915_gem_object_truncate(obj); | |
509 | } | |
eb01459f EA |
510 | |
511 | return ret; | |
512 | } | |
513 | ||
673a394b EA |
514 | /** |
515 | * Reads data from the object referenced by handle. | |
516 | * | |
517 | * On error, the contents of *data are undefined. | |
518 | */ | |
519 | int | |
520 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 521 | struct drm_file *file) |
673a394b EA |
522 | { |
523 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 524 | struct drm_i915_gem_object *obj; |
35b62a89 | 525 | int ret = 0; |
673a394b | 526 | |
51311d0a CW |
527 | if (args->size == 0) |
528 | return 0; | |
529 | ||
530 | if (!access_ok(VERIFY_WRITE, | |
531 | (char __user *)(uintptr_t)args->data_ptr, | |
532 | args->size)) | |
533 | return -EFAULT; | |
534 | ||
4f27b75d | 535 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 536 | if (ret) |
4f27b75d | 537 | return ret; |
673a394b | 538 | |
05394f39 | 539 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 540 | if (&obj->base == NULL) { |
1d7cfea1 CW |
541 | ret = -ENOENT; |
542 | goto unlock; | |
4f27b75d | 543 | } |
673a394b | 544 | |
7dcd2499 | 545 | /* Bounds check source. */ |
05394f39 CW |
546 | if (args->offset > obj->base.size || |
547 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 548 | ret = -EINVAL; |
35b62a89 | 549 | goto out; |
ce9d419d CW |
550 | } |
551 | ||
1286ff73 DV |
552 | /* prime objects have no backing filp to GEM pread/pwrite |
553 | * pages from. | |
554 | */ | |
555 | if (!obj->base.filp) { | |
556 | ret = -EINVAL; | |
557 | goto out; | |
558 | } | |
559 | ||
db53a302 CW |
560 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
561 | ||
dbf7bff0 | 562 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 563 | |
35b62a89 | 564 | out: |
05394f39 | 565 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 566 | unlock: |
4f27b75d | 567 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 568 | return ret; |
673a394b EA |
569 | } |
570 | ||
0839ccb8 KP |
571 | /* This is the fast write path which cannot handle |
572 | * page faults in the source data | |
9b7530cc | 573 | */ |
0839ccb8 KP |
574 | |
575 | static inline int | |
576 | fast_user_write(struct io_mapping *mapping, | |
577 | loff_t page_base, int page_offset, | |
578 | char __user *user_data, | |
579 | int length) | |
9b7530cc | 580 | { |
4f0c7cfb BW |
581 | void __iomem *vaddr_atomic; |
582 | void *vaddr; | |
0839ccb8 | 583 | unsigned long unwritten; |
9b7530cc | 584 | |
3e4d3af5 | 585 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
586 | /* We can use the cpu mem copy function because this is X86. */ |
587 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
588 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 589 | user_data, length); |
3e4d3af5 | 590 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 591 | return unwritten; |
0839ccb8 KP |
592 | } |
593 | ||
3de09aa3 EA |
594 | /** |
595 | * This is the fast pwrite path, where we copy the data directly from the | |
596 | * user into the GTT, uncached. | |
597 | */ | |
673a394b | 598 | static int |
05394f39 CW |
599 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
600 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 601 | struct drm_i915_gem_pwrite *args, |
05394f39 | 602 | struct drm_file *file) |
673a394b | 603 | { |
0839ccb8 | 604 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 605 | ssize_t remain; |
0839ccb8 | 606 | loff_t offset, page_base; |
673a394b | 607 | char __user *user_data; |
935aaa69 DV |
608 | int page_offset, page_length, ret; |
609 | ||
86a1ee26 | 610 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
611 | if (ret) |
612 | goto out; | |
613 | ||
614 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
615 | if (ret) | |
616 | goto out_unpin; | |
617 | ||
618 | ret = i915_gem_object_put_fence(obj); | |
619 | if (ret) | |
620 | goto out_unpin; | |
673a394b EA |
621 | |
622 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
623 | remain = args->size; | |
673a394b | 624 | |
05394f39 | 625 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
626 | |
627 | while (remain > 0) { | |
628 | /* Operation in this page | |
629 | * | |
0839ccb8 KP |
630 | * page_base = page offset within aperture |
631 | * page_offset = offset within page | |
632 | * page_length = bytes to copy for this page | |
673a394b | 633 | */ |
c8cbbb8b CW |
634 | page_base = offset & PAGE_MASK; |
635 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
636 | page_length = remain; |
637 | if ((page_offset + remain) > PAGE_SIZE) | |
638 | page_length = PAGE_SIZE - page_offset; | |
639 | ||
0839ccb8 | 640 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
641 | * source page isn't available. Return the error and we'll |
642 | * retry in the slow path. | |
0839ccb8 | 643 | */ |
fbd5a26d | 644 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
645 | page_offset, user_data, page_length)) { |
646 | ret = -EFAULT; | |
647 | goto out_unpin; | |
648 | } | |
673a394b | 649 | |
0839ccb8 KP |
650 | remain -= page_length; |
651 | user_data += page_length; | |
652 | offset += page_length; | |
673a394b | 653 | } |
673a394b | 654 | |
935aaa69 DV |
655 | out_unpin: |
656 | i915_gem_object_unpin(obj); | |
657 | out: | |
3de09aa3 | 658 | return ret; |
673a394b EA |
659 | } |
660 | ||
d174bd64 DV |
661 | /* Per-page copy function for the shmem pwrite fastpath. |
662 | * Flushes invalid cachelines before writing to the target if | |
663 | * needs_clflush_before is set and flushes out any written cachelines after | |
664 | * writing if needs_clflush is set. */ | |
3043c60c | 665 | static int |
d174bd64 DV |
666 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
667 | char __user *user_data, | |
668 | bool page_do_bit17_swizzling, | |
669 | bool needs_clflush_before, | |
670 | bool needs_clflush_after) | |
673a394b | 671 | { |
d174bd64 | 672 | char *vaddr; |
673a394b | 673 | int ret; |
3de09aa3 | 674 | |
e7e58eb5 | 675 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 676 | return -EINVAL; |
3de09aa3 | 677 | |
d174bd64 DV |
678 | vaddr = kmap_atomic(page); |
679 | if (needs_clflush_before) | |
680 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
681 | page_length); | |
682 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
683 | user_data, | |
684 | page_length); | |
685 | if (needs_clflush_after) | |
686 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
687 | page_length); | |
688 | kunmap_atomic(vaddr); | |
3de09aa3 | 689 | |
755d2218 | 690 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
691 | } |
692 | ||
d174bd64 DV |
693 | /* Only difference to the fast-path function is that this can handle bit17 |
694 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 695 | static int |
d174bd64 DV |
696 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
697 | char __user *user_data, | |
698 | bool page_do_bit17_swizzling, | |
699 | bool needs_clflush_before, | |
700 | bool needs_clflush_after) | |
673a394b | 701 | { |
d174bd64 DV |
702 | char *vaddr; |
703 | int ret; | |
e5281ccd | 704 | |
d174bd64 | 705 | vaddr = kmap(page); |
e7e58eb5 | 706 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
707 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
708 | page_length, | |
709 | page_do_bit17_swizzling); | |
d174bd64 DV |
710 | if (page_do_bit17_swizzling) |
711 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
712 | user_data, |
713 | page_length); | |
d174bd64 DV |
714 | else |
715 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
716 | user_data, | |
717 | page_length); | |
718 | if (needs_clflush_after) | |
23c18c71 DV |
719 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
720 | page_length, | |
721 | page_do_bit17_swizzling); | |
d174bd64 | 722 | kunmap(page); |
40123c1f | 723 | |
755d2218 | 724 | return ret ? -EFAULT : 0; |
40123c1f EA |
725 | } |
726 | ||
40123c1f | 727 | static int |
e244a443 DV |
728 | i915_gem_shmem_pwrite(struct drm_device *dev, |
729 | struct drm_i915_gem_object *obj, | |
730 | struct drm_i915_gem_pwrite *args, | |
731 | struct drm_file *file) | |
40123c1f | 732 | { |
40123c1f | 733 | ssize_t remain; |
8c59967c DV |
734 | loff_t offset; |
735 | char __user *user_data; | |
eb2c0c81 | 736 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 737 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 738 | int hit_slowpath = 0; |
58642885 DV |
739 | int needs_clflush_after = 0; |
740 | int needs_clflush_before = 0; | |
9da3da66 CW |
741 | int i; |
742 | struct scatterlist *sg; | |
40123c1f | 743 | |
8c59967c | 744 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
745 | remain = args->size; |
746 | ||
8c59967c | 747 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 748 | |
58642885 DV |
749 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
750 | /* If we're not in the cpu write domain, set ourself into the gtt | |
751 | * write domain and manually flush cachelines (if required). This | |
752 | * optimizes for the case when the gpu will use the data | |
753 | * right away and we therefore have to clflush anyway. */ | |
754 | if (obj->cache_level == I915_CACHE_NONE) | |
755 | needs_clflush_after = 1; | |
6c085a72 CW |
756 | if (obj->gtt_space) { |
757 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
758 | if (ret) | |
759 | return ret; | |
760 | } | |
58642885 DV |
761 | } |
762 | /* Same trick applies for invalidate partially written cachelines before | |
763 | * writing. */ | |
764 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
765 | && obj->cache_level == I915_CACHE_NONE) | |
766 | needs_clflush_before = 1; | |
767 | ||
755d2218 CW |
768 | ret = i915_gem_object_get_pages(obj); |
769 | if (ret) | |
770 | return ret; | |
771 | ||
772 | i915_gem_object_pin_pages(obj); | |
773 | ||
673a394b | 774 | offset = args->offset; |
05394f39 | 775 | obj->dirty = 1; |
673a394b | 776 | |
9da3da66 | 777 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd | 778 | struct page *page; |
58642885 | 779 | int partial_cacheline_write; |
e5281ccd | 780 | |
9da3da66 CW |
781 | if (i < offset >> PAGE_SHIFT) |
782 | continue; | |
783 | ||
784 | if (remain <= 0) | |
785 | break; | |
786 | ||
40123c1f EA |
787 | /* Operation in this page |
788 | * | |
40123c1f | 789 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
790 | * page_length = bytes to copy for this page |
791 | */ | |
c8cbbb8b | 792 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
793 | |
794 | page_length = remain; | |
795 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
796 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 797 | |
58642885 DV |
798 | /* If we don't overwrite a cacheline completely we need to be |
799 | * careful to have up-to-date data by first clflushing. Don't | |
800 | * overcomplicate things and flush the entire patch. */ | |
801 | partial_cacheline_write = needs_clflush_before && | |
802 | ((shmem_page_offset | page_length) | |
803 | & (boot_cpu_data.x86_clflush_size - 1)); | |
804 | ||
9da3da66 | 805 | page = sg_page(sg); |
8c59967c DV |
806 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
807 | (page_to_phys(page) & (1 << 17)) != 0; | |
808 | ||
d174bd64 DV |
809 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
810 | user_data, page_do_bit17_swizzling, | |
811 | partial_cacheline_write, | |
812 | needs_clflush_after); | |
813 | if (ret == 0) | |
814 | goto next_page; | |
e244a443 DV |
815 | |
816 | hit_slowpath = 1; | |
e244a443 | 817 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
818 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
819 | user_data, page_do_bit17_swizzling, | |
820 | partial_cacheline_write, | |
821 | needs_clflush_after); | |
40123c1f | 822 | |
e244a443 | 823 | mutex_lock(&dev->struct_mutex); |
755d2218 | 824 | |
e244a443 | 825 | next_page: |
e5281ccd CW |
826 | set_page_dirty(page); |
827 | mark_page_accessed(page); | |
e5281ccd | 828 | |
755d2218 | 829 | if (ret) |
8c59967c | 830 | goto out; |
8c59967c | 831 | |
40123c1f | 832 | remain -= page_length; |
8c59967c | 833 | user_data += page_length; |
40123c1f | 834 | offset += page_length; |
673a394b EA |
835 | } |
836 | ||
fbd5a26d | 837 | out: |
755d2218 CW |
838 | i915_gem_object_unpin_pages(obj); |
839 | ||
e244a443 DV |
840 | if (hit_slowpath) { |
841 | /* Fixup: Kill any reinstated backing storage pages */ | |
842 | if (obj->madv == __I915_MADV_PURGED) | |
843 | i915_gem_object_truncate(obj); | |
844 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
845 | * domain anymore. */ | |
846 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
847 | i915_gem_clflush_object(obj); | |
848 | intel_gtt_chipset_flush(); | |
849 | } | |
8c59967c | 850 | } |
673a394b | 851 | |
58642885 DV |
852 | if (needs_clflush_after) |
853 | intel_gtt_chipset_flush(); | |
854 | ||
40123c1f | 855 | return ret; |
673a394b EA |
856 | } |
857 | ||
858 | /** | |
859 | * Writes data to the object referenced by handle. | |
860 | * | |
861 | * On error, the contents of the buffer that were to be modified are undefined. | |
862 | */ | |
863 | int | |
864 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 865 | struct drm_file *file) |
673a394b EA |
866 | { |
867 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 868 | struct drm_i915_gem_object *obj; |
51311d0a CW |
869 | int ret; |
870 | ||
871 | if (args->size == 0) | |
872 | return 0; | |
873 | ||
874 | if (!access_ok(VERIFY_READ, | |
875 | (char __user *)(uintptr_t)args->data_ptr, | |
876 | args->size)) | |
877 | return -EFAULT; | |
878 | ||
f56f821f DV |
879 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
880 | args->size); | |
51311d0a CW |
881 | if (ret) |
882 | return -EFAULT; | |
673a394b | 883 | |
fbd5a26d | 884 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 885 | if (ret) |
fbd5a26d | 886 | return ret; |
1d7cfea1 | 887 | |
05394f39 | 888 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 889 | if (&obj->base == NULL) { |
1d7cfea1 CW |
890 | ret = -ENOENT; |
891 | goto unlock; | |
fbd5a26d | 892 | } |
673a394b | 893 | |
7dcd2499 | 894 | /* Bounds check destination. */ |
05394f39 CW |
895 | if (args->offset > obj->base.size || |
896 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 897 | ret = -EINVAL; |
35b62a89 | 898 | goto out; |
ce9d419d CW |
899 | } |
900 | ||
1286ff73 DV |
901 | /* prime objects have no backing filp to GEM pread/pwrite |
902 | * pages from. | |
903 | */ | |
904 | if (!obj->base.filp) { | |
905 | ret = -EINVAL; | |
906 | goto out; | |
907 | } | |
908 | ||
db53a302 CW |
909 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
910 | ||
935aaa69 | 911 | ret = -EFAULT; |
673a394b EA |
912 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
913 | * it would end up going through the fenced access, and we'll get | |
914 | * different detiling behavior between reading and writing. | |
915 | * pread/pwrite currently are reading and writing from the CPU | |
916 | * perspective, requiring manual detiling by the client. | |
917 | */ | |
5c0480f2 | 918 | if (obj->phys_obj) { |
fbd5a26d | 919 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
920 | goto out; |
921 | } | |
922 | ||
86a1ee26 | 923 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 924 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 925 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 926 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
927 | /* Note that the gtt paths might fail with non-page-backed user |
928 | * pointers (e.g. gtt mappings when moving data between | |
929 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 930 | } |
673a394b | 931 | |
86a1ee26 | 932 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 933 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 934 | |
35b62a89 | 935 | out: |
05394f39 | 936 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 937 | unlock: |
fbd5a26d | 938 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
939 | return ret; |
940 | } | |
941 | ||
b361237b CW |
942 | int |
943 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
944 | bool interruptible) | |
945 | { | |
946 | if (atomic_read(&dev_priv->mm.wedged)) { | |
947 | struct completion *x = &dev_priv->error_completion; | |
948 | bool recovery_complete; | |
949 | unsigned long flags; | |
950 | ||
951 | /* Give the error handler a chance to run. */ | |
952 | spin_lock_irqsave(&x->wait.lock, flags); | |
953 | recovery_complete = x->done > 0; | |
954 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
955 | ||
956 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
957 | * -EIO unconditionally for these. */ | |
958 | if (!interruptible) | |
959 | return -EIO; | |
960 | ||
961 | /* Recovery complete, but still wedged means reset failure. */ | |
962 | if (recovery_complete) | |
963 | return -EIO; | |
964 | ||
965 | return -EAGAIN; | |
966 | } | |
967 | ||
968 | return 0; | |
969 | } | |
970 | ||
971 | /* | |
972 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
973 | * equal. | |
974 | */ | |
975 | static int | |
976 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
977 | { | |
978 | int ret; | |
979 | ||
980 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
981 | ||
982 | ret = 0; | |
983 | if (seqno == ring->outstanding_lazy_request) | |
984 | ret = i915_add_request(ring, NULL, NULL); | |
985 | ||
986 | return ret; | |
987 | } | |
988 | ||
989 | /** | |
990 | * __wait_seqno - wait until execution of seqno has finished | |
991 | * @ring: the ring expected to report seqno | |
992 | * @seqno: duh! | |
993 | * @interruptible: do an interruptible wait (normally yes) | |
994 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
995 | * | |
996 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
997 | * errno with remaining time filled in timeout argument. | |
998 | */ | |
999 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
1000 | bool interruptible, struct timespec *timeout) | |
1001 | { | |
1002 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1003 | struct timespec before, now, wait_time={1,0}; | |
1004 | unsigned long timeout_jiffies; | |
1005 | long end; | |
1006 | bool wait_forever = true; | |
1007 | int ret; | |
1008 | ||
1009 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
1010 | return 0; | |
1011 | ||
1012 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1013 | ||
1014 | if (timeout != NULL) { | |
1015 | wait_time = *timeout; | |
1016 | wait_forever = false; | |
1017 | } | |
1018 | ||
1019 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1020 | ||
1021 | if (WARN_ON(!ring->irq_get(ring))) | |
1022 | return -ENODEV; | |
1023 | ||
1024 | /* Record current time in case interrupted by signal, or wedged * */ | |
1025 | getrawmonotonic(&before); | |
1026 | ||
1027 | #define EXIT_COND \ | |
1028 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
1029 | atomic_read(&dev_priv->mm.wedged)) | |
1030 | do { | |
1031 | if (interruptible) | |
1032 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1033 | EXIT_COND, | |
1034 | timeout_jiffies); | |
1035 | else | |
1036 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1037 | timeout_jiffies); | |
1038 | ||
1039 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1040 | if (ret) | |
1041 | end = ret; | |
1042 | } while (end == 0 && wait_forever); | |
1043 | ||
1044 | getrawmonotonic(&now); | |
1045 | ||
1046 | ring->irq_put(ring); | |
1047 | trace_i915_gem_request_wait_end(ring, seqno); | |
1048 | #undef EXIT_COND | |
1049 | ||
1050 | if (timeout) { | |
1051 | struct timespec sleep_time = timespec_sub(now, before); | |
1052 | *timeout = timespec_sub(*timeout, sleep_time); | |
1053 | } | |
1054 | ||
1055 | switch (end) { | |
1056 | case -EIO: | |
1057 | case -EAGAIN: /* Wedged */ | |
1058 | case -ERESTARTSYS: /* Signal */ | |
1059 | return (int)end; | |
1060 | case 0: /* Timeout */ | |
1061 | if (timeout) | |
1062 | set_normalized_timespec(timeout, 0, 0); | |
1063 | return -ETIME; | |
1064 | default: /* Completed */ | |
1065 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1066 | return 0; | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | /** | |
1071 | * Waits for a sequence number to be signaled, and cleans up the | |
1072 | * request and object lists appropriately for that event. | |
1073 | */ | |
1074 | int | |
1075 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1076 | { | |
1077 | struct drm_device *dev = ring->dev; | |
1078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1079 | bool interruptible = dev_priv->mm.interruptible; | |
1080 | int ret; | |
1081 | ||
1082 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1083 | BUG_ON(seqno == 0); | |
1084 | ||
1085 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1086 | if (ret) | |
1087 | return ret; | |
1088 | ||
1089 | ret = i915_gem_check_olr(ring, seqno); | |
1090 | if (ret) | |
1091 | return ret; | |
1092 | ||
1093 | return __wait_seqno(ring, seqno, interruptible, NULL); | |
1094 | } | |
1095 | ||
1096 | /** | |
1097 | * Ensures that all rendering to the object has completed and the object is | |
1098 | * safe to unbind from the GTT or access from the CPU. | |
1099 | */ | |
1100 | static __must_check int | |
1101 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1102 | bool readonly) | |
1103 | { | |
1104 | struct intel_ring_buffer *ring = obj->ring; | |
1105 | u32 seqno; | |
1106 | int ret; | |
1107 | ||
1108 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1109 | if (seqno == 0) | |
1110 | return 0; | |
1111 | ||
1112 | ret = i915_wait_seqno(ring, seqno); | |
1113 | if (ret) | |
1114 | return ret; | |
1115 | ||
1116 | i915_gem_retire_requests_ring(ring); | |
1117 | ||
1118 | /* Manually manage the write flush as we may have not yet | |
1119 | * retired the buffer. | |
1120 | */ | |
1121 | if (obj->last_write_seqno && | |
1122 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1123 | obj->last_write_seqno = 0; | |
1124 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1125 | } | |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
3236f57a CW |
1130 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1131 | * as the object state may change during this call. | |
1132 | */ | |
1133 | static __must_check int | |
1134 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1135 | bool readonly) | |
1136 | { | |
1137 | struct drm_device *dev = obj->base.dev; | |
1138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1139 | struct intel_ring_buffer *ring = obj->ring; | |
1140 | u32 seqno; | |
1141 | int ret; | |
1142 | ||
1143 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1144 | BUG_ON(!dev_priv->mm.interruptible); | |
1145 | ||
1146 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1147 | if (seqno == 0) | |
1148 | return 0; | |
1149 | ||
1150 | ret = i915_gem_check_wedge(dev_priv, true); | |
1151 | if (ret) | |
1152 | return ret; | |
1153 | ||
1154 | ret = i915_gem_check_olr(ring, seqno); | |
1155 | if (ret) | |
1156 | return ret; | |
1157 | ||
1158 | mutex_unlock(&dev->struct_mutex); | |
1159 | ret = __wait_seqno(ring, seqno, true, NULL); | |
1160 | mutex_lock(&dev->struct_mutex); | |
1161 | ||
1162 | i915_gem_retire_requests_ring(ring); | |
1163 | ||
1164 | /* Manually manage the write flush as we may have not yet | |
1165 | * retired the buffer. | |
1166 | */ | |
1167 | if (obj->last_write_seqno && | |
1168 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1169 | obj->last_write_seqno = 0; | |
1170 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1171 | } | |
1172 | ||
1173 | return ret; | |
1174 | } | |
1175 | ||
673a394b | 1176 | /** |
2ef7eeaa EA |
1177 | * Called when user space prepares to use an object with the CPU, either |
1178 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1179 | */ |
1180 | int | |
1181 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1182 | struct drm_file *file) |
673a394b EA |
1183 | { |
1184 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1185 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1186 | uint32_t read_domains = args->read_domains; |
1187 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1188 | int ret; |
1189 | ||
2ef7eeaa | 1190 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1191 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1192 | return -EINVAL; |
1193 | ||
21d509e3 | 1194 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1195 | return -EINVAL; |
1196 | ||
1197 | /* Having something in the write domain implies it's in the read | |
1198 | * domain, and only that read domain. Enforce that in the request. | |
1199 | */ | |
1200 | if (write_domain != 0 && read_domains != write_domain) | |
1201 | return -EINVAL; | |
1202 | ||
76c1dec1 | 1203 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1204 | if (ret) |
76c1dec1 | 1205 | return ret; |
1d7cfea1 | 1206 | |
05394f39 | 1207 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1208 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1209 | ret = -ENOENT; |
1210 | goto unlock; | |
76c1dec1 | 1211 | } |
673a394b | 1212 | |
3236f57a CW |
1213 | /* Try to flush the object off the GPU without holding the lock. |
1214 | * We will repeat the flush holding the lock in the normal manner | |
1215 | * to catch cases where we are gazumped. | |
1216 | */ | |
1217 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1218 | if (ret) | |
1219 | goto unref; | |
1220 | ||
2ef7eeaa EA |
1221 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1222 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1223 | |
1224 | /* Silently promote "you're not bound, there was nothing to do" | |
1225 | * to success, since the client was just asking us to | |
1226 | * make sure everything was done. | |
1227 | */ | |
1228 | if (ret == -EINVAL) | |
1229 | ret = 0; | |
2ef7eeaa | 1230 | } else { |
e47c68e9 | 1231 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1232 | } |
1233 | ||
3236f57a | 1234 | unref: |
05394f39 | 1235 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1236 | unlock: |
673a394b EA |
1237 | mutex_unlock(&dev->struct_mutex); |
1238 | return ret; | |
1239 | } | |
1240 | ||
1241 | /** | |
1242 | * Called when user space has done writes to this buffer | |
1243 | */ | |
1244 | int | |
1245 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1246 | struct drm_file *file) |
673a394b EA |
1247 | { |
1248 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1249 | struct drm_i915_gem_object *obj; |
673a394b EA |
1250 | int ret = 0; |
1251 | ||
76c1dec1 | 1252 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1253 | if (ret) |
76c1dec1 | 1254 | return ret; |
1d7cfea1 | 1255 | |
05394f39 | 1256 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1257 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1258 | ret = -ENOENT; |
1259 | goto unlock; | |
673a394b EA |
1260 | } |
1261 | ||
673a394b | 1262 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1263 | if (obj->pin_count) |
e47c68e9 EA |
1264 | i915_gem_object_flush_cpu_write_domain(obj); |
1265 | ||
05394f39 | 1266 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1267 | unlock: |
673a394b EA |
1268 | mutex_unlock(&dev->struct_mutex); |
1269 | return ret; | |
1270 | } | |
1271 | ||
1272 | /** | |
1273 | * Maps the contents of an object, returning the address it is mapped | |
1274 | * into. | |
1275 | * | |
1276 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1277 | * imply a ref on the object itself. | |
1278 | */ | |
1279 | int | |
1280 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1281 | struct drm_file *file) |
673a394b EA |
1282 | { |
1283 | struct drm_i915_gem_mmap *args = data; | |
1284 | struct drm_gem_object *obj; | |
673a394b EA |
1285 | unsigned long addr; |
1286 | ||
05394f39 | 1287 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1288 | if (obj == NULL) |
bf79cb91 | 1289 | return -ENOENT; |
673a394b | 1290 | |
1286ff73 DV |
1291 | /* prime objects have no backing filp to GEM mmap |
1292 | * pages from. | |
1293 | */ | |
1294 | if (!obj->filp) { | |
1295 | drm_gem_object_unreference_unlocked(obj); | |
1296 | return -EINVAL; | |
1297 | } | |
1298 | ||
6be5ceb0 | 1299 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1300 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1301 | args->offset); | |
bc9025bd | 1302 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1303 | if (IS_ERR((void *)addr)) |
1304 | return addr; | |
1305 | ||
1306 | args->addr_ptr = (uint64_t) addr; | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
de151cf6 JB |
1311 | /** |
1312 | * i915_gem_fault - fault a page into the GTT | |
1313 | * vma: VMA in question | |
1314 | * vmf: fault info | |
1315 | * | |
1316 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1317 | * from userspace. The fault handler takes care of binding the object to | |
1318 | * the GTT (if needed), allocating and programming a fence register (again, | |
1319 | * only if needed based on whether the old reg is still valid or the object | |
1320 | * is tiled) and inserting a new PTE into the faulting process. | |
1321 | * | |
1322 | * Note that the faulting process may involve evicting existing objects | |
1323 | * from the GTT and/or fence registers to make room. So performance may | |
1324 | * suffer if the GTT working set is large or there are few fence registers | |
1325 | * left. | |
1326 | */ | |
1327 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1328 | { | |
05394f39 CW |
1329 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1330 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1331 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1332 | pgoff_t page_offset; |
1333 | unsigned long pfn; | |
1334 | int ret = 0; | |
0f973f27 | 1335 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1336 | |
1337 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1338 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1339 | PAGE_SHIFT; | |
1340 | ||
d9bc7e9f CW |
1341 | ret = i915_mutex_lock_interruptible(dev); |
1342 | if (ret) | |
1343 | goto out; | |
a00b10c3 | 1344 | |
db53a302 CW |
1345 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1346 | ||
d9bc7e9f | 1347 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1348 | if (!obj->map_and_fenceable) { |
1349 | ret = i915_gem_object_unbind(obj); | |
1350 | if (ret) | |
1351 | goto unlock; | |
a00b10c3 | 1352 | } |
05394f39 | 1353 | if (!obj->gtt_space) { |
86a1ee26 | 1354 | ret = i915_gem_object_bind_to_gtt(obj, 0, true, false); |
c715089f CW |
1355 | if (ret) |
1356 | goto unlock; | |
de151cf6 | 1357 | |
e92d03bf EA |
1358 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1359 | if (ret) | |
1360 | goto unlock; | |
1361 | } | |
4a684a41 | 1362 | |
74898d7e DV |
1363 | if (!obj->has_global_gtt_mapping) |
1364 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1365 | ||
06d98131 | 1366 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1367 | if (ret) |
1368 | goto unlock; | |
de151cf6 | 1369 | |
05394f39 CW |
1370 | if (i915_gem_object_is_inactive(obj)) |
1371 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1372 | |
6299f992 CW |
1373 | obj->fault_mappable = true; |
1374 | ||
dd2757f8 | 1375 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1376 | page_offset; |
1377 | ||
1378 | /* Finally, remap it using the new GTT offset */ | |
1379 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1380 | unlock: |
de151cf6 | 1381 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1382 | out: |
de151cf6 | 1383 | switch (ret) { |
d9bc7e9f | 1384 | case -EIO: |
a9340cca DV |
1385 | /* If this -EIO is due to a gpu hang, give the reset code a |
1386 | * chance to clean up the mess. Otherwise return the proper | |
1387 | * SIGBUS. */ | |
1388 | if (!atomic_read(&dev_priv->mm.wedged)) | |
1389 | return VM_FAULT_SIGBUS; | |
045e769a | 1390 | case -EAGAIN: |
d9bc7e9f CW |
1391 | /* Give the error handler a chance to run and move the |
1392 | * objects off the GPU active list. Next time we service the | |
1393 | * fault, we should be able to transition the page into the | |
1394 | * GTT without touching the GPU (and so avoid further | |
1395 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1396 | * with coherency, just lost writes. | |
1397 | */ | |
045e769a | 1398 | set_need_resched(); |
c715089f CW |
1399 | case 0: |
1400 | case -ERESTARTSYS: | |
bed636ab | 1401 | case -EINTR: |
e79e0fe3 DR |
1402 | case -EBUSY: |
1403 | /* | |
1404 | * EBUSY is ok: this just means that another thread | |
1405 | * already did the job. | |
1406 | */ | |
c715089f | 1407 | return VM_FAULT_NOPAGE; |
de151cf6 | 1408 | case -ENOMEM: |
de151cf6 | 1409 | return VM_FAULT_OOM; |
de151cf6 | 1410 | default: |
4d0f817e | 1411 | WARN_ON_ONCE(ret); |
c715089f | 1412 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1413 | } |
1414 | } | |
1415 | ||
901782b2 CW |
1416 | /** |
1417 | * i915_gem_release_mmap - remove physical page mappings | |
1418 | * @obj: obj in question | |
1419 | * | |
af901ca1 | 1420 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1421 | * relinquish ownership of the pages back to the system. |
1422 | * | |
1423 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1424 | * object through the GTT and then lose the fence register due to | |
1425 | * resource pressure. Similarly if the object has been moved out of the | |
1426 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1427 | * mapping will then trigger a page fault on the next user access, allowing | |
1428 | * fixup by i915_gem_fault(). | |
1429 | */ | |
d05ca301 | 1430 | void |
05394f39 | 1431 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1432 | { |
6299f992 CW |
1433 | if (!obj->fault_mappable) |
1434 | return; | |
901782b2 | 1435 | |
f6e47884 CW |
1436 | if (obj->base.dev->dev_mapping) |
1437 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1438 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1439 | obj->base.size, 1); | |
fb7d516a | 1440 | |
6299f992 | 1441 | obj->fault_mappable = false; |
901782b2 CW |
1442 | } |
1443 | ||
92b88aeb | 1444 | static uint32_t |
e28f8711 | 1445 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1446 | { |
e28f8711 | 1447 | uint32_t gtt_size; |
92b88aeb CW |
1448 | |
1449 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1450 | tiling_mode == I915_TILING_NONE) |
1451 | return size; | |
92b88aeb CW |
1452 | |
1453 | /* Previous chips need a power-of-two fence region when tiling */ | |
1454 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1455 | gtt_size = 1024*1024; |
92b88aeb | 1456 | else |
e28f8711 | 1457 | gtt_size = 512*1024; |
92b88aeb | 1458 | |
e28f8711 CW |
1459 | while (gtt_size < size) |
1460 | gtt_size <<= 1; | |
92b88aeb | 1461 | |
e28f8711 | 1462 | return gtt_size; |
92b88aeb CW |
1463 | } |
1464 | ||
de151cf6 JB |
1465 | /** |
1466 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1467 | * @obj: object to check | |
1468 | * | |
1469 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1470 | * potential fence register mapping. |
de151cf6 JB |
1471 | */ |
1472 | static uint32_t | |
e28f8711 CW |
1473 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1474 | uint32_t size, | |
1475 | int tiling_mode) | |
de151cf6 | 1476 | { |
de151cf6 JB |
1477 | /* |
1478 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1479 | * if a fence register is needed for the object. | |
1480 | */ | |
a00b10c3 | 1481 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1482 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1483 | return 4096; |
1484 | ||
a00b10c3 CW |
1485 | /* |
1486 | * Previous chips need to be aligned to the size of the smallest | |
1487 | * fence register that can contain the object. | |
1488 | */ | |
e28f8711 | 1489 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1490 | } |
1491 | ||
5e783301 DV |
1492 | /** |
1493 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1494 | * unfenced object | |
e28f8711 CW |
1495 | * @dev: the device |
1496 | * @size: size of the object | |
1497 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1498 | * |
1499 | * Return the required GTT alignment for an object, only taking into account | |
1500 | * unfenced tiled surface requirements. | |
1501 | */ | |
467cffba | 1502 | uint32_t |
e28f8711 CW |
1503 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1504 | uint32_t size, | |
1505 | int tiling_mode) | |
5e783301 | 1506 | { |
5e783301 DV |
1507 | /* |
1508 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1509 | */ | |
1510 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1511 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1512 | return 4096; |
1513 | ||
e28f8711 CW |
1514 | /* Previous hardware however needs to be aligned to a power-of-two |
1515 | * tile height. The simplest method for determining this is to reuse | |
1516 | * the power-of-tile object size. | |
5e783301 | 1517 | */ |
e28f8711 | 1518 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1519 | } |
1520 | ||
d8cb5086 CW |
1521 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1522 | { | |
1523 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1524 | int ret; | |
1525 | ||
1526 | if (obj->base.map_list.map) | |
1527 | return 0; | |
1528 | ||
1529 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1530 | if (ret != -ENOSPC) | |
1531 | return ret; | |
1532 | ||
1533 | /* Badly fragmented mmap space? The only way we can recover | |
1534 | * space is by destroying unwanted objects. We can't randomly release | |
1535 | * mmap_offsets as userspace expects them to be persistent for the | |
1536 | * lifetime of the objects. The closest we can is to release the | |
1537 | * offsets on purgeable objects by truncating it and marking it purged, | |
1538 | * which prevents userspace from ever using that object again. | |
1539 | */ | |
1540 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1541 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1542 | if (ret != -ENOSPC) | |
1543 | return ret; | |
1544 | ||
1545 | i915_gem_shrink_all(dev_priv); | |
1546 | return drm_gem_create_mmap_offset(&obj->base); | |
1547 | } | |
1548 | ||
1549 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1550 | { | |
1551 | if (!obj->base.map_list.map) | |
1552 | return; | |
1553 | ||
1554 | drm_gem_free_mmap_offset(&obj->base); | |
1555 | } | |
1556 | ||
de151cf6 | 1557 | int |
ff72145b DA |
1558 | i915_gem_mmap_gtt(struct drm_file *file, |
1559 | struct drm_device *dev, | |
1560 | uint32_t handle, | |
1561 | uint64_t *offset) | |
de151cf6 | 1562 | { |
da761a6e | 1563 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1564 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1565 | int ret; |
1566 | ||
76c1dec1 | 1567 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1568 | if (ret) |
76c1dec1 | 1569 | return ret; |
de151cf6 | 1570 | |
ff72145b | 1571 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1572 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1573 | ret = -ENOENT; |
1574 | goto unlock; | |
1575 | } | |
de151cf6 | 1576 | |
05394f39 | 1577 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1578 | ret = -E2BIG; |
ff56b0bc | 1579 | goto out; |
da761a6e CW |
1580 | } |
1581 | ||
05394f39 | 1582 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1583 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1584 | ret = -EINVAL; |
1585 | goto out; | |
ab18282d CW |
1586 | } |
1587 | ||
d8cb5086 CW |
1588 | ret = i915_gem_object_create_mmap_offset(obj); |
1589 | if (ret) | |
1590 | goto out; | |
de151cf6 | 1591 | |
ff72145b | 1592 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1593 | |
1d7cfea1 | 1594 | out: |
05394f39 | 1595 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1596 | unlock: |
de151cf6 | 1597 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1598 | return ret; |
de151cf6 JB |
1599 | } |
1600 | ||
ff72145b DA |
1601 | /** |
1602 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1603 | * @dev: DRM device | |
1604 | * @data: GTT mapping ioctl data | |
1605 | * @file: GEM object info | |
1606 | * | |
1607 | * Simply returns the fake offset to userspace so it can mmap it. | |
1608 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1609 | * up so we can get faults in the handler above. | |
1610 | * | |
1611 | * The fault handler will take care of binding the object into the GTT | |
1612 | * (since it may have been evicted to make room for something), allocating | |
1613 | * a fence register, and mapping the appropriate aperture address into | |
1614 | * userspace. | |
1615 | */ | |
1616 | int | |
1617 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1618 | struct drm_file *file) | |
1619 | { | |
1620 | struct drm_i915_gem_mmap_gtt *args = data; | |
1621 | ||
ff72145b DA |
1622 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1623 | } | |
1624 | ||
225067ee DV |
1625 | /* Immediately discard the backing storage */ |
1626 | static void | |
1627 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1628 | { |
e5281ccd | 1629 | struct inode *inode; |
e5281ccd | 1630 | |
4d6294bf | 1631 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1632 | |
4d6294bf CW |
1633 | if (obj->base.filp == NULL) |
1634 | return; | |
e5281ccd | 1635 | |
225067ee DV |
1636 | /* Our goal here is to return as much of the memory as |
1637 | * is possible back to the system as we are called from OOM. | |
1638 | * To do this we must instruct the shmfs to drop all of its | |
1639 | * backing pages, *now*. | |
1640 | */ | |
05394f39 | 1641 | inode = obj->base.filp->f_path.dentry->d_inode; |
225067ee | 1642 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1643 | |
225067ee DV |
1644 | obj->madv = __I915_MADV_PURGED; |
1645 | } | |
e5281ccd | 1646 | |
225067ee DV |
1647 | static inline int |
1648 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1649 | { | |
1650 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1651 | } |
1652 | ||
37e680a1 | 1653 | static void |
05394f39 | 1654 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1655 | { |
05394f39 | 1656 | int page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1657 | struct scatterlist *sg; |
6c085a72 | 1658 | int ret, i; |
673a394b | 1659 | |
05394f39 | 1660 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1661 | |
6c085a72 CW |
1662 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1663 | if (ret) { | |
1664 | /* In the event of a disaster, abandon all caches and | |
1665 | * hope for the best. | |
1666 | */ | |
1667 | WARN_ON(ret != -EIO); | |
1668 | i915_gem_clflush_object(obj); | |
1669 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1670 | } | |
1671 | ||
6dacfd2f | 1672 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1673 | i915_gem_object_save_bit_17_swizzle(obj); |
1674 | ||
05394f39 CW |
1675 | if (obj->madv == I915_MADV_DONTNEED) |
1676 | obj->dirty = 0; | |
3ef94daa | 1677 | |
9da3da66 CW |
1678 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
1679 | struct page *page = sg_page(sg); | |
1680 | ||
05394f39 | 1681 | if (obj->dirty) |
9da3da66 | 1682 | set_page_dirty(page); |
3ef94daa | 1683 | |
05394f39 | 1684 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1685 | mark_page_accessed(page); |
3ef94daa | 1686 | |
9da3da66 | 1687 | page_cache_release(page); |
3ef94daa | 1688 | } |
05394f39 | 1689 | obj->dirty = 0; |
673a394b | 1690 | |
9da3da66 CW |
1691 | sg_free_table(obj->pages); |
1692 | kfree(obj->pages); | |
37e680a1 | 1693 | } |
6c085a72 | 1694 | |
37e680a1 CW |
1695 | static int |
1696 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) | |
1697 | { | |
1698 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1699 | ||
2f745ad3 | 1700 | if (obj->pages == NULL) |
37e680a1 CW |
1701 | return 0; |
1702 | ||
1703 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1704 | |
a5570178 CW |
1705 | if (obj->pages_pin_count) |
1706 | return -EBUSY; | |
1707 | ||
37e680a1 | 1708 | ops->put_pages(obj); |
9da3da66 | 1709 | obj->pages = NULL; |
37e680a1 CW |
1710 | |
1711 | list_del(&obj->gtt_list); | |
6c085a72 CW |
1712 | if (i915_gem_object_is_purgeable(obj)) |
1713 | i915_gem_object_truncate(obj); | |
1714 | ||
1715 | return 0; | |
1716 | } | |
1717 | ||
1718 | static long | |
1719 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1720 | { | |
1721 | struct drm_i915_gem_object *obj, *next; | |
1722 | long count = 0; | |
1723 | ||
1724 | list_for_each_entry_safe(obj, next, | |
1725 | &dev_priv->mm.unbound_list, | |
1726 | gtt_list) { | |
1727 | if (i915_gem_object_is_purgeable(obj) && | |
37e680a1 | 1728 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1729 | count += obj->base.size >> PAGE_SHIFT; |
1730 | if (count >= target) | |
1731 | return count; | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | list_for_each_entry_safe(obj, next, | |
1736 | &dev_priv->mm.inactive_list, | |
1737 | mm_list) { | |
1738 | if (i915_gem_object_is_purgeable(obj) && | |
1739 | i915_gem_object_unbind(obj) == 0 && | |
37e680a1 | 1740 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1741 | count += obj->base.size >> PAGE_SHIFT; |
1742 | if (count >= target) | |
1743 | return count; | |
1744 | } | |
1745 | } | |
1746 | ||
1747 | return count; | |
1748 | } | |
1749 | ||
1750 | static void | |
1751 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1752 | { | |
1753 | struct drm_i915_gem_object *obj, *next; | |
1754 | ||
1755 | i915_gem_evict_everything(dev_priv->dev); | |
1756 | ||
1757 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1758 | i915_gem_object_put_pages(obj); |
225067ee DV |
1759 | } |
1760 | ||
37e680a1 | 1761 | static int |
6c085a72 | 1762 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1763 | { |
6c085a72 | 1764 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1765 | int page_count, i; |
1766 | struct address_space *mapping; | |
9da3da66 CW |
1767 | struct sg_table *st; |
1768 | struct scatterlist *sg; | |
e5281ccd | 1769 | struct page *page; |
6c085a72 | 1770 | gfp_t gfp; |
e5281ccd | 1771 | |
6c085a72 CW |
1772 | /* Assert that the object is not currently in any GPU domain. As it |
1773 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1774 | * a GPU cache | |
1775 | */ | |
1776 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1777 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1778 | ||
9da3da66 CW |
1779 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1780 | if (st == NULL) | |
1781 | return -ENOMEM; | |
1782 | ||
05394f39 | 1783 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1784 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1785 | sg_free_table(st); | |
1786 | kfree(st); | |
e5281ccd | 1787 | return -ENOMEM; |
9da3da66 | 1788 | } |
e5281ccd | 1789 | |
9da3da66 CW |
1790 | /* Get the list of pages out of our struct file. They'll be pinned |
1791 | * at this point until we release them. | |
1792 | * | |
1793 | * Fail silently without starting the shrinker | |
1794 | */ | |
6c085a72 CW |
1795 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
1796 | gfp = mapping_gfp_mask(mapping); | |
d7c3b937 | 1797 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 | 1798 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
9da3da66 | 1799 | for_each_sg(st->sgl, sg, page_count, i) { |
6c085a72 CW |
1800 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1801 | if (IS_ERR(page)) { | |
1802 | i915_gem_purge(dev_priv, page_count); | |
1803 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1804 | } | |
1805 | if (IS_ERR(page)) { | |
1806 | /* We've tried hard to allocate the memory by reaping | |
1807 | * our own buffer, now let the real VM do its job and | |
1808 | * go down in flames if truly OOM. | |
1809 | */ | |
d7c3b937 | 1810 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN); |
6c085a72 CW |
1811 | gfp |= __GFP_IO | __GFP_WAIT; |
1812 | ||
1813 | i915_gem_shrink_all(dev_priv); | |
1814 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1815 | if (IS_ERR(page)) | |
1816 | goto err_pages; | |
1817 | ||
d7c3b937 | 1818 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 CW |
1819 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1820 | } | |
e5281ccd | 1821 | |
9da3da66 | 1822 | sg_set_page(sg, page, PAGE_SIZE, 0); |
e5281ccd CW |
1823 | } |
1824 | ||
6dacfd2f | 1825 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1826 | i915_gem_object_do_bit_17_swizzle(obj); |
1827 | ||
9da3da66 | 1828 | obj->pages = st; |
e5281ccd CW |
1829 | return 0; |
1830 | ||
1831 | err_pages: | |
9da3da66 CW |
1832 | for_each_sg(st->sgl, sg, i, page_count) |
1833 | page_cache_release(sg_page(sg)); | |
1834 | sg_free_table(st); | |
1835 | kfree(st); | |
e5281ccd | 1836 | return PTR_ERR(page); |
673a394b EA |
1837 | } |
1838 | ||
37e680a1 CW |
1839 | /* Ensure that the associated pages are gathered from the backing storage |
1840 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1841 | * multiple times before they are released by a single call to | |
1842 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1843 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1844 | * or as the object is itself released. | |
1845 | */ | |
1846 | int | |
1847 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1848 | { | |
1849 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1850 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1851 | int ret; | |
1852 | ||
2f745ad3 | 1853 | if (obj->pages) |
37e680a1 CW |
1854 | return 0; |
1855 | ||
a5570178 CW |
1856 | BUG_ON(obj->pages_pin_count); |
1857 | ||
37e680a1 CW |
1858 | ret = ops->get_pages(obj); |
1859 | if (ret) | |
1860 | return ret; | |
1861 | ||
1862 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1863 | return 0; | |
1864 | } | |
1865 | ||
54cf91dc | 1866 | void |
05394f39 | 1867 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1868 | struct intel_ring_buffer *ring, |
1869 | u32 seqno) | |
673a394b | 1870 | { |
05394f39 | 1871 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1872 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1873 | |
852835f3 | 1874 | BUG_ON(ring == NULL); |
05394f39 | 1875 | obj->ring = ring; |
673a394b EA |
1876 | |
1877 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1878 | if (!obj->active) { |
1879 | drm_gem_object_reference(&obj->base); | |
1880 | obj->active = 1; | |
673a394b | 1881 | } |
e35a41de | 1882 | |
673a394b | 1883 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1884 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1885 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1886 | |
0201f1ec | 1887 | obj->last_read_seqno = seqno; |
caea7476 | 1888 | |
7dd49065 | 1889 | if (obj->fenced_gpu_access) { |
caea7476 | 1890 | obj->last_fenced_seqno = seqno; |
caea7476 | 1891 | |
7dd49065 CW |
1892 | /* Bump MRU to take account of the delayed flush */ |
1893 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1894 | struct drm_i915_fence_reg *reg; | |
1895 | ||
1896 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1897 | list_move_tail(®->lru_list, | |
1898 | &dev_priv->mm.fence_list); | |
1899 | } | |
caea7476 CW |
1900 | } |
1901 | } | |
1902 | ||
caea7476 CW |
1903 | static void |
1904 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1905 | { | |
1906 | struct drm_device *dev = obj->base.dev; | |
1907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1908 | ||
65ce3027 | 1909 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
caea7476 | 1910 | BUG_ON(!obj->active); |
65ce3027 | 1911 | |
f047e395 CW |
1912 | if (obj->pin_count) /* are we a framebuffer? */ |
1913 | intel_mark_fb_idle(obj); | |
1914 | ||
1915 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1916 | ||
65ce3027 | 1917 | list_del_init(&obj->ring_list); |
caea7476 CW |
1918 | obj->ring = NULL; |
1919 | ||
65ce3027 CW |
1920 | obj->last_read_seqno = 0; |
1921 | obj->last_write_seqno = 0; | |
1922 | obj->base.write_domain = 0; | |
1923 | ||
1924 | obj->last_fenced_seqno = 0; | |
caea7476 | 1925 | obj->fenced_gpu_access = false; |
caea7476 CW |
1926 | |
1927 | obj->active = 0; | |
1928 | drm_gem_object_unreference(&obj->base); | |
1929 | ||
1930 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1931 | } |
673a394b | 1932 | |
53d227f2 DV |
1933 | static u32 |
1934 | i915_gem_get_seqno(struct drm_device *dev) | |
1935 | { | |
1936 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1937 | u32 seqno = dev_priv->next_seqno; | |
1938 | ||
1939 | /* reserve 0 for non-seqno */ | |
1940 | if (++dev_priv->next_seqno == 0) | |
1941 | dev_priv->next_seqno = 1; | |
1942 | ||
1943 | return seqno; | |
1944 | } | |
1945 | ||
1946 | u32 | |
1947 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1948 | { | |
1949 | if (ring->outstanding_lazy_request == 0) | |
1950 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1951 | ||
1952 | return ring->outstanding_lazy_request; | |
1953 | } | |
1954 | ||
3cce469c | 1955 | int |
db53a302 | 1956 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1957 | struct drm_file *file, |
acb868d3 | 1958 | u32 *out_seqno) |
673a394b | 1959 | { |
db53a302 | 1960 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 1961 | struct drm_i915_gem_request *request; |
a71d8d94 | 1962 | u32 request_ring_position; |
acb868d3 | 1963 | u32 seqno; |
673a394b | 1964 | int was_empty; |
3cce469c CW |
1965 | int ret; |
1966 | ||
cc889e0f DV |
1967 | /* |
1968 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1969 | * after having emitted the batchbuffer command. Hence we need to fix | |
1970 | * things up similar to emitting the lazy request. The difference here | |
1971 | * is that the flush _must_ happen before the next request, no matter | |
1972 | * what. | |
1973 | */ | |
a7b9761d CW |
1974 | ret = intel_ring_flush_all_caches(ring); |
1975 | if (ret) | |
1976 | return ret; | |
cc889e0f | 1977 | |
acb868d3 CW |
1978 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
1979 | if (request == NULL) | |
1980 | return -ENOMEM; | |
3bb73aba | 1981 | |
53d227f2 | 1982 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1983 | |
a71d8d94 CW |
1984 | /* Record the position of the start of the request so that |
1985 | * should we detect the updated seqno part-way through the | |
1986 | * GPU processing the request, we never over-estimate the | |
1987 | * position of the head. | |
1988 | */ | |
1989 | request_ring_position = intel_ring_get_tail(ring); | |
1990 | ||
3cce469c | 1991 | ret = ring->add_request(ring, &seqno); |
3bb73aba CW |
1992 | if (ret) { |
1993 | kfree(request); | |
1994 | return ret; | |
1995 | } | |
673a394b | 1996 | |
db53a302 | 1997 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1998 | |
1999 | request->seqno = seqno; | |
852835f3 | 2000 | request->ring = ring; |
a71d8d94 | 2001 | request->tail = request_ring_position; |
673a394b | 2002 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2003 | was_empty = list_empty(&ring->request_list); |
2004 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2005 | request->file_priv = NULL; |
852835f3 | 2006 | |
db53a302 CW |
2007 | if (file) { |
2008 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2009 | ||
1c25595f | 2010 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2011 | request->file_priv = file_priv; |
b962442e | 2012 | list_add_tail(&request->client_list, |
f787a5f5 | 2013 | &file_priv->mm.request_list); |
1c25595f | 2014 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2015 | } |
673a394b | 2016 | |
5391d0cf | 2017 | ring->outstanding_lazy_request = 0; |
db53a302 | 2018 | |
f65d9421 | 2019 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
2020 | if (i915_enable_hangcheck) { |
2021 | mod_timer(&dev_priv->hangcheck_timer, | |
cecc21fe | 2022 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 2023 | } |
f047e395 | 2024 | if (was_empty) { |
b3b079db | 2025 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2026 | &dev_priv->mm.retire_work, |
2027 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2028 | intel_mark_busy(dev_priv->dev); |
2029 | } | |
f65d9421 | 2030 | } |
cc889e0f | 2031 | |
acb868d3 CW |
2032 | if (out_seqno) |
2033 | *out_seqno = seqno; | |
3cce469c | 2034 | return 0; |
673a394b EA |
2035 | } |
2036 | ||
f787a5f5 CW |
2037 | static inline void |
2038 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2039 | { |
1c25595f | 2040 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2041 | |
1c25595f CW |
2042 | if (!file_priv) |
2043 | return; | |
1c5d22f7 | 2044 | |
1c25595f | 2045 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2046 | if (request->file_priv) { |
2047 | list_del(&request->client_list); | |
2048 | request->file_priv = NULL; | |
2049 | } | |
1c25595f | 2050 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2051 | } |
673a394b | 2052 | |
dfaae392 CW |
2053 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2054 | struct intel_ring_buffer *ring) | |
9375e446 | 2055 | { |
dfaae392 CW |
2056 | while (!list_empty(&ring->request_list)) { |
2057 | struct drm_i915_gem_request *request; | |
673a394b | 2058 | |
dfaae392 CW |
2059 | request = list_first_entry(&ring->request_list, |
2060 | struct drm_i915_gem_request, | |
2061 | list); | |
de151cf6 | 2062 | |
dfaae392 | 2063 | list_del(&request->list); |
f787a5f5 | 2064 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2065 | kfree(request); |
2066 | } | |
673a394b | 2067 | |
dfaae392 | 2068 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2069 | struct drm_i915_gem_object *obj; |
9375e446 | 2070 | |
05394f39 CW |
2071 | obj = list_first_entry(&ring->active_list, |
2072 | struct drm_i915_gem_object, | |
2073 | ring_list); | |
9375e446 | 2074 | |
05394f39 | 2075 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2076 | } |
2077 | } | |
2078 | ||
312817a3 CW |
2079 | static void i915_gem_reset_fences(struct drm_device *dev) |
2080 | { | |
2081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2082 | int i; | |
2083 | ||
4b9de737 | 2084 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2085 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2086 | |
ada726c7 | 2087 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 2088 | |
ada726c7 CW |
2089 | if (reg->obj) |
2090 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2091 | |
ada726c7 CW |
2092 | reg->pin_count = 0; |
2093 | reg->obj = NULL; | |
2094 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2095 | } |
ada726c7 CW |
2096 | |
2097 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2098 | } |
2099 | ||
069efc1d | 2100 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2101 | { |
77f01230 | 2102 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2103 | struct drm_i915_gem_object *obj; |
b4519513 | 2104 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2105 | int i; |
673a394b | 2106 | |
b4519513 CW |
2107 | for_each_ring(ring, dev_priv, i) |
2108 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2109 | |
dfaae392 CW |
2110 | /* Move everything out of the GPU domains to ensure we do any |
2111 | * necessary invalidation upon reuse. | |
2112 | */ | |
05394f39 | 2113 | list_for_each_entry(obj, |
77f01230 | 2114 | &dev_priv->mm.inactive_list, |
69dc4987 | 2115 | mm_list) |
77f01230 | 2116 | { |
05394f39 | 2117 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2118 | } |
069efc1d CW |
2119 | |
2120 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 2121 | i915_gem_reset_fences(dev); |
673a394b EA |
2122 | } |
2123 | ||
2124 | /** | |
2125 | * This function clears the request list as sequence numbers are passed. | |
2126 | */ | |
a71d8d94 | 2127 | void |
db53a302 | 2128 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2129 | { |
673a394b | 2130 | uint32_t seqno; |
1ec14ad3 | 2131 | int i; |
673a394b | 2132 | |
db53a302 | 2133 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2134 | return; |
2135 | ||
db53a302 | 2136 | WARN_ON(i915_verify_lists(ring->dev)); |
5c81fe85 | 2137 | |
b2eadbc8 | 2138 | seqno = ring->get_seqno(ring, true); |
604dd3ec | 2139 | |
076e2c0e | 2140 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
2141 | if (seqno >= ring->sync_seqno[i]) |
2142 | ring->sync_seqno[i] = 0; | |
5c81fe85 | 2143 | |
852835f3 | 2144 | while (!list_empty(&ring->request_list)) { |
673a394b | 2145 | struct drm_i915_gem_request *request; |
604dd3ec | 2146 | |
852835f3 | 2147 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2148 | struct drm_i915_gem_request, |
2149 | list); | |
5c81fe85 | 2150 | |
dfaae392 | 2151 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c | 2152 | break; |
604dd3ec | 2153 | |
db53a302 | 2154 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2155 | /* We know the GPU must have read the request to have |
2156 | * sent us the seqno + interrupt, so use the position | |
2157 | * of tail of the request to update the last known position | |
2158 | * of the GPU head. | |
2159 | */ | |
2160 | ring->last_retired_head = request->tail; | |
604dd3ec | 2161 | |
b84d5f0c | 2162 | list_del(&request->list); |
f787a5f5 | 2163 | i915_gem_request_remove_from_client(request); |
b84d5f0c | 2164 | kfree(request); |
5c81fe85 BW |
2165 | } |
2166 | ||
b84d5f0c CW |
2167 | /* Move any buffers on the active list that are no longer referenced |
2168 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2169 | */ | |
2170 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2171 | struct drm_i915_gem_object *obj; |
604dd3ec | 2172 | |
0206e353 | 2173 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2174 | struct drm_i915_gem_object, |
2175 | ring_list); | |
673a394b | 2176 | |
0201f1ec | 2177 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2178 | break; |
673a394b | 2179 | |
65ce3027 | 2180 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2181 | } |
3cce469c | 2182 | |
db53a302 CW |
2183 | if (unlikely(ring->trace_irq_seqno && |
2184 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2185 | ring->irq_put(ring); |
db53a302 | 2186 | ring->trace_irq_seqno = 0; |
9d34e5db | 2187 | } |
23bc5982 | 2188 | |
db53a302 | 2189 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2190 | } |
ffed1d09 | 2191 | |
b09a1fec CW |
2192 | void |
2193 | i915_gem_retire_requests(struct drm_device *dev) | |
2194 | { | |
2195 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2196 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2197 | int i; |
673a394b | 2198 | |
b4519513 CW |
2199 | for_each_ring(ring, dev_priv, i) |
2200 | i915_gem_retire_requests_ring(ring); | |
673a394b EA |
2201 | } |
2202 | ||
75ef9da2 | 2203 | static void |
673a394b | 2204 | i915_gem_retire_work_handler(struct work_struct *work) |
673a394b | 2205 | { |
673a394b EA |
2206 | drm_i915_private_t *dev_priv; |
2207 | struct drm_device *dev; | |
b4519513 | 2208 | struct intel_ring_buffer *ring; |
0a58705b CW |
2209 | bool idle; |
2210 | int i; | |
673a394b | 2211 | |
673a394b EA |
2212 | dev_priv = container_of(work, drm_i915_private_t, |
2213 | mm.retire_work.work); | |
2214 | dev = dev_priv->dev; | |
0201f1ec | 2215 | |
891b48cf CW |
2216 | /* Come back later if the device is busy... */ |
2217 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2218 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2219 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2220 | return; |
2221 | } | |
2222 | ||
b09a1fec | 2223 | i915_gem_retire_requests(dev); |
0201f1ec | 2224 | |
0a58705b CW |
2225 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2226 | * objects indefinitely. | |
0201f1ec | 2227 | */ |
0a58705b | 2228 | idle = true; |
b4519513 | 2229 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2230 | if (ring->gpu_caches_dirty) |
2231 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2232 | |
2233 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2234 | } |
2235 | ||
0a58705b | 2236 | if (!dev_priv->mm.suspended && !idle) |
bcb45086 CW |
2237 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2238 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2239 | if (idle) |
2240 | intel_mark_idle(dev); | |
0a58705b | 2241 | |
673a394b | 2242 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2243 | } |
2244 | ||
30dfebf3 DV |
2245 | /** |
2246 | * Ensures that an object will eventually get non-busy by flushing any required | |
2247 | * write domains, emitting any outstanding lazy request and retiring and | |
2248 | * completed requests. | |
2249 | */ | |
2250 | static int | |
2251 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2252 | { | |
2253 | int ret; | |
2254 | ||
2255 | if (obj->active) { | |
0201f1ec | 2256 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2257 | if (ret) |
2258 | return ret; | |
0201f1ec | 2259 | |
30dfebf3 DV |
2260 | i915_gem_retire_requests_ring(obj->ring); |
2261 | } | |
2262 | ||
2263 | return 0; | |
2264 | } | |
2265 | ||
23ba4fd0 BW |
2266 | /** |
2267 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2268 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2269 | * | |
2270 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2271 | * the timeout parameter. | |
2272 | * -ETIME: object is still busy after timeout | |
2273 | * -ERESTARTSYS: signal interrupted the wait | |
2274 | * -ENONENT: object doesn't exist | |
2275 | * Also possible, but rare: | |
2276 | * -EAGAIN: GPU wedged | |
2277 | * -ENOMEM: damn | |
2278 | * -ENODEV: Internal IRQ fail | |
2279 | * -E?: The add request failed | |
2280 | * | |
2281 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2282 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2283 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2284 | * without holding struct_mutex the object may become re-busied before this | |
2285 | * function completes. A similar but shorter * race condition exists in the busy | |
2286 | * ioctl | |
2287 | */ | |
2288 | int | |
2289 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2290 | { | |
2291 | struct drm_i915_gem_wait *args = data; | |
2292 | struct drm_i915_gem_object *obj; | |
2293 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2294 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2295 | u32 seqno = 0; |
2296 | int ret = 0; | |
2297 | ||
eac1f14f BW |
2298 | if (args->timeout_ns >= 0) { |
2299 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2300 | timeout = &timeout_stack; | |
2301 | } | |
23ba4fd0 BW |
2302 | |
2303 | ret = i915_mutex_lock_interruptible(dev); | |
2304 | if (ret) | |
2305 | return ret; | |
2306 | ||
2307 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2308 | if (&obj->base == NULL) { | |
2309 | mutex_unlock(&dev->struct_mutex); | |
2310 | return -ENOENT; | |
2311 | } | |
2312 | ||
30dfebf3 DV |
2313 | /* Need to make sure the object gets inactive eventually. */ |
2314 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2315 | if (ret) |
2316 | goto out; | |
2317 | ||
2318 | if (obj->active) { | |
0201f1ec | 2319 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2320 | ring = obj->ring; |
2321 | } | |
2322 | ||
2323 | if (seqno == 0) | |
2324 | goto out; | |
2325 | ||
23ba4fd0 BW |
2326 | /* Do this after OLR check to make sure we make forward progress polling |
2327 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2328 | */ | |
2329 | if (!args->timeout_ns) { | |
2330 | ret = -ETIME; | |
2331 | goto out; | |
2332 | } | |
2333 | ||
2334 | drm_gem_object_unreference(&obj->base); | |
2335 | mutex_unlock(&dev->struct_mutex); | |
2336 | ||
eac1f14f BW |
2337 | ret = __wait_seqno(ring, seqno, true, timeout); |
2338 | if (timeout) { | |
2339 | WARN_ON(!timespec_valid(timeout)); | |
2340 | args->timeout_ns = timespec_to_ns(timeout); | |
2341 | } | |
23ba4fd0 BW |
2342 | return ret; |
2343 | ||
2344 | out: | |
2345 | drm_gem_object_unreference(&obj->base); | |
2346 | mutex_unlock(&dev->struct_mutex); | |
2347 | return ret; | |
2348 | } | |
2349 | ||
5816d648 BW |
2350 | /** |
2351 | * i915_gem_object_sync - sync an object to a ring. | |
2352 | * | |
2353 | * @obj: object which may be in use on another ring. | |
2354 | * @to: ring we wish to use the object on. May be NULL. | |
2355 | * | |
2356 | * This code is meant to abstract object synchronization with the GPU. | |
2357 | * Calling with NULL implies synchronizing the object with the CPU | |
2358 | * rather than a particular GPU ring. | |
2359 | * | |
2360 | * Returns 0 if successful, else propagates up the lower layer error. | |
2361 | */ | |
2911a35b BW |
2362 | int |
2363 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2364 | struct intel_ring_buffer *to) | |
2365 | { | |
2366 | struct intel_ring_buffer *from = obj->ring; | |
2367 | u32 seqno; | |
2368 | int ret, idx; | |
2369 | ||
2370 | if (from == NULL || to == from) | |
2371 | return 0; | |
2372 | ||
5816d648 | 2373 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2374 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2375 | |
2376 | idx = intel_ring_sync_index(from, to); | |
2377 | ||
0201f1ec | 2378 | seqno = obj->last_read_seqno; |
2911a35b BW |
2379 | if (seqno <= from->sync_seqno[idx]) |
2380 | return 0; | |
2381 | ||
b4aca010 BW |
2382 | ret = i915_gem_check_olr(obj->ring, seqno); |
2383 | if (ret) | |
2384 | return ret; | |
2911a35b | 2385 | |
1500f7ea | 2386 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
2387 | if (!ret) |
2388 | from->sync_seqno[idx] = seqno; | |
2911a35b | 2389 | |
e3a5a225 | 2390 | return ret; |
2911a35b BW |
2391 | } |
2392 | ||
b5ffc9bc CW |
2393 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2394 | { | |
2395 | u32 old_write_domain, old_read_domains; | |
2396 | ||
b5ffc9bc CW |
2397 | /* Act a barrier for all accesses through the GTT */ |
2398 | mb(); | |
2399 | ||
2400 | /* Force a pagefault for domain tracking on next user access */ | |
2401 | i915_gem_release_mmap(obj); | |
2402 | ||
b97c3d9c KP |
2403 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2404 | return; | |
2405 | ||
b5ffc9bc CW |
2406 | old_read_domains = obj->base.read_domains; |
2407 | old_write_domain = obj->base.write_domain; | |
2408 | ||
2409 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2410 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2411 | ||
2412 | trace_i915_gem_object_change_domain(obj, | |
2413 | old_read_domains, | |
2414 | old_write_domain); | |
2415 | } | |
2416 | ||
673a394b EA |
2417 | /** |
2418 | * Unbinds an object from the GTT aperture. | |
2419 | */ | |
0f973f27 | 2420 | int |
05394f39 | 2421 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2422 | { |
7bddb01f | 2423 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2424 | int ret = 0; |
2425 | ||
05394f39 | 2426 | if (obj->gtt_space == NULL) |
673a394b EA |
2427 | return 0; |
2428 | ||
31d8d651 CW |
2429 | if (obj->pin_count) |
2430 | return -EBUSY; | |
673a394b | 2431 | |
c4670ad0 CW |
2432 | BUG_ON(obj->pages == NULL); |
2433 | ||
a8198eea | 2434 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2435 | if (ret) |
a8198eea CW |
2436 | return ret; |
2437 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2438 | * should be safe and we need to cleanup or else we might | |
2439 | * cause memory corruption through use-after-free. | |
2440 | */ | |
2441 | ||
b5ffc9bc | 2442 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2443 | |
96b47b65 | 2444 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2445 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2446 | if (ret) |
d9e86c0e | 2447 | return ret; |
96b47b65 | 2448 | |
db53a302 CW |
2449 | trace_i915_gem_object_unbind(obj); |
2450 | ||
74898d7e DV |
2451 | if (obj->has_global_gtt_mapping) |
2452 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2453 | if (obj->has_aliasing_ppgtt_mapping) { |
2454 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2455 | obj->has_aliasing_ppgtt_mapping = 0; | |
2456 | } | |
74163907 | 2457 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2458 | |
6c085a72 CW |
2459 | list_del(&obj->mm_list); |
2460 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2461 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2462 | obj->map_and_fenceable = true; |
673a394b | 2463 | |
05394f39 CW |
2464 | drm_mm_put_block(obj->gtt_space); |
2465 | obj->gtt_space = NULL; | |
2466 | obj->gtt_offset = 0; | |
673a394b | 2467 | |
6c085a72 | 2468 | return 0; |
673a394b EA |
2469 | } |
2470 | ||
b2da9fe5 | 2471 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2472 | { |
69c2fc89 | 2473 | if (list_empty(&ring->active_list)) |
64193406 CW |
2474 | return 0; |
2475 | ||
199b2bc2 | 2476 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2477 | } |
2478 | ||
b2da9fe5 | 2479 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2480 | { |
2481 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2482 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2483 | int ret, i; |
4df2faf4 | 2484 | |
4df2faf4 | 2485 | /* Flush everything onto the inactive list. */ |
b4519513 | 2486 | for_each_ring(ring, dev_priv, i) { |
b6c7488d | 2487 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
1ec14ad3 CW |
2488 | if (ret) |
2489 | return ret; | |
b4519513 | 2490 | |
b4519513 | 2491 | ret = i915_ring_idle(ring); |
f2ef6eb1 BW |
2492 | if (ret) |
2493 | return ret; | |
1ec14ad3 | 2494 | } |
4df2faf4 | 2495 | |
8a1a49f9 | 2496 | return 0; |
4df2faf4 DV |
2497 | } |
2498 | ||
9ce079e4 CW |
2499 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2500 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2501 | { |
4e901fdc | 2502 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2503 | uint64_t val; |
2504 | ||
9ce079e4 CW |
2505 | if (obj) { |
2506 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2507 | |
9ce079e4 CW |
2508 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2509 | 0xfffff000) << 32; | |
2510 | val |= obj->gtt_offset & 0xfffff000; | |
2511 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2512 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2513 | |
9ce079e4 CW |
2514 | if (obj->tiling_mode == I915_TILING_Y) |
2515 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2516 | val |= I965_FENCE_REG_VALID; | |
2517 | } else | |
2518 | val = 0; | |
c6642782 | 2519 | |
9ce079e4 CW |
2520 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2521 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2522 | } |
2523 | ||
9ce079e4 CW |
2524 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2525 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2526 | { |
de151cf6 | 2527 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2528 | uint64_t val; |
2529 | ||
9ce079e4 CW |
2530 | if (obj) { |
2531 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2532 | |
9ce079e4 CW |
2533 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2534 | 0xfffff000) << 32; | |
2535 | val |= obj->gtt_offset & 0xfffff000; | |
2536 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2537 | if (obj->tiling_mode == I915_TILING_Y) | |
2538 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2539 | val |= I965_FENCE_REG_VALID; | |
2540 | } else | |
2541 | val = 0; | |
c6642782 | 2542 | |
9ce079e4 CW |
2543 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2544 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2545 | } |
2546 | ||
9ce079e4 CW |
2547 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2548 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2549 | { |
de151cf6 | 2550 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2551 | u32 val; |
de151cf6 | 2552 | |
9ce079e4 CW |
2553 | if (obj) { |
2554 | u32 size = obj->gtt_space->size; | |
2555 | int pitch_val; | |
2556 | int tile_width; | |
c6642782 | 2557 | |
9ce079e4 CW |
2558 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2559 | (size & -size) != size || | |
2560 | (obj->gtt_offset & (size - 1)), | |
2561 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2562 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2563 | |
9ce079e4 CW |
2564 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2565 | tile_width = 128; | |
2566 | else | |
2567 | tile_width = 512; | |
2568 | ||
2569 | /* Note: pitch better be a power of two tile widths */ | |
2570 | pitch_val = obj->stride / tile_width; | |
2571 | pitch_val = ffs(pitch_val) - 1; | |
2572 | ||
2573 | val = obj->gtt_offset; | |
2574 | if (obj->tiling_mode == I915_TILING_Y) | |
2575 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2576 | val |= I915_FENCE_SIZE_BITS(size); | |
2577 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2578 | val |= I830_FENCE_REG_VALID; | |
2579 | } else | |
2580 | val = 0; | |
2581 | ||
2582 | if (reg < 8) | |
2583 | reg = FENCE_REG_830_0 + reg * 4; | |
2584 | else | |
2585 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2586 | ||
2587 | I915_WRITE(reg, val); | |
2588 | POSTING_READ(reg); | |
de151cf6 JB |
2589 | } |
2590 | ||
9ce079e4 CW |
2591 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2592 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2593 | { |
de151cf6 | 2594 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2595 | uint32_t val; |
de151cf6 | 2596 | |
9ce079e4 CW |
2597 | if (obj) { |
2598 | u32 size = obj->gtt_space->size; | |
2599 | uint32_t pitch_val; | |
de151cf6 | 2600 | |
9ce079e4 CW |
2601 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2602 | (size & -size) != size || | |
2603 | (obj->gtt_offset & (size - 1)), | |
2604 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2605 | obj->gtt_offset, size); | |
e76a16de | 2606 | |
9ce079e4 CW |
2607 | pitch_val = obj->stride / 128; |
2608 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2609 | |
9ce079e4 CW |
2610 | val = obj->gtt_offset; |
2611 | if (obj->tiling_mode == I915_TILING_Y) | |
2612 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2613 | val |= I830_FENCE_SIZE_BITS(size); | |
2614 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2615 | val |= I830_FENCE_REG_VALID; | |
2616 | } else | |
2617 | val = 0; | |
c6642782 | 2618 | |
9ce079e4 CW |
2619 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2620 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2621 | } | |
2622 | ||
2623 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2624 | struct drm_i915_gem_object *obj) | |
2625 | { | |
2626 | switch (INTEL_INFO(dev)->gen) { | |
2627 | case 7: | |
2628 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2629 | case 5: | |
2630 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2631 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2632 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2633 | default: break; | |
2634 | } | |
de151cf6 JB |
2635 | } |
2636 | ||
61050808 CW |
2637 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2638 | struct drm_i915_fence_reg *fence) | |
2639 | { | |
2640 | return fence - dev_priv->fence_regs; | |
2641 | } | |
2642 | ||
2643 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2644 | struct drm_i915_fence_reg *fence, | |
2645 | bool enable) | |
2646 | { | |
2647 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2648 | int reg = fence_number(dev_priv, fence); | |
2649 | ||
2650 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2651 | ||
2652 | if (enable) { | |
2653 | obj->fence_reg = reg; | |
2654 | fence->obj = obj; | |
2655 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2656 | } else { | |
2657 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2658 | fence->obj = NULL; | |
2659 | list_del_init(&fence->lru_list); | |
2660 | } | |
2661 | } | |
2662 | ||
d9e86c0e | 2663 | static int |
a360bb1a | 2664 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2665 | { |
1c293ea3 | 2666 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2667 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2668 | if (ret) |
2669 | return ret; | |
d9e86c0e CW |
2670 | |
2671 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2672 | } |
2673 | ||
63256ec5 CW |
2674 | /* Ensure that all CPU reads are completed before installing a fence |
2675 | * and all writes before removing the fence. | |
2676 | */ | |
2677 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2678 | mb(); | |
2679 | ||
86d5bc37 | 2680 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2681 | return 0; |
2682 | } | |
2683 | ||
2684 | int | |
2685 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2686 | { | |
61050808 | 2687 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2688 | int ret; |
2689 | ||
a360bb1a | 2690 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2691 | if (ret) |
2692 | return ret; | |
2693 | ||
61050808 CW |
2694 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2695 | return 0; | |
d9e86c0e | 2696 | |
61050808 CW |
2697 | i915_gem_object_update_fence(obj, |
2698 | &dev_priv->fence_regs[obj->fence_reg], | |
2699 | false); | |
2700 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2701 | |
2702 | return 0; | |
2703 | } | |
2704 | ||
2705 | static struct drm_i915_fence_reg * | |
a360bb1a | 2706 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2707 | { |
ae3db24a | 2708 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2709 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2710 | int i; |
ae3db24a DV |
2711 | |
2712 | /* First try to find a free reg */ | |
d9e86c0e | 2713 | avail = NULL; |
ae3db24a DV |
2714 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2715 | reg = &dev_priv->fence_regs[i]; | |
2716 | if (!reg->obj) | |
d9e86c0e | 2717 | return reg; |
ae3db24a | 2718 | |
1690e1eb | 2719 | if (!reg->pin_count) |
d9e86c0e | 2720 | avail = reg; |
ae3db24a DV |
2721 | } |
2722 | ||
d9e86c0e CW |
2723 | if (avail == NULL) |
2724 | return NULL; | |
ae3db24a DV |
2725 | |
2726 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2727 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2728 | if (reg->pin_count) |
ae3db24a DV |
2729 | continue; |
2730 | ||
8fe301ad | 2731 | return reg; |
ae3db24a DV |
2732 | } |
2733 | ||
8fe301ad | 2734 | return NULL; |
ae3db24a DV |
2735 | } |
2736 | ||
de151cf6 | 2737 | /** |
9a5a53b3 | 2738 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2739 | * @obj: object to map through a fence reg |
2740 | * | |
2741 | * When mapping objects through the GTT, userspace wants to be able to write | |
2742 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2743 | * This function walks the fence regs looking for a free one for @obj, |
2744 | * stealing one if it can't find any. | |
2745 | * | |
2746 | * It then sets up the reg based on the object's properties: address, pitch | |
2747 | * and tiling format. | |
9a5a53b3 CW |
2748 | * |
2749 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2750 | */ |
8c4b8c3f | 2751 | int |
06d98131 | 2752 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2753 | { |
05394f39 | 2754 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2755 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2756 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2757 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2758 | int ret; |
de151cf6 | 2759 | |
14415745 CW |
2760 | /* Have we updated the tiling parameters upon the object and so |
2761 | * will need to serialise the write to the associated fence register? | |
2762 | */ | |
5d82e3e6 | 2763 | if (obj->fence_dirty) { |
14415745 CW |
2764 | ret = i915_gem_object_flush_fence(obj); |
2765 | if (ret) | |
2766 | return ret; | |
2767 | } | |
9a5a53b3 | 2768 | |
d9e86c0e | 2769 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2770 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2771 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2772 | if (!obj->fence_dirty) { |
14415745 CW |
2773 | list_move_tail(®->lru_list, |
2774 | &dev_priv->mm.fence_list); | |
2775 | return 0; | |
2776 | } | |
2777 | } else if (enable) { | |
2778 | reg = i915_find_fence_reg(dev); | |
2779 | if (reg == NULL) | |
2780 | return -EDEADLK; | |
d9e86c0e | 2781 | |
14415745 CW |
2782 | if (reg->obj) { |
2783 | struct drm_i915_gem_object *old = reg->obj; | |
2784 | ||
2785 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2786 | if (ret) |
2787 | return ret; | |
2788 | ||
14415745 | 2789 | i915_gem_object_fence_lost(old); |
29c5a587 | 2790 | } |
14415745 | 2791 | } else |
a09ba7fa | 2792 | return 0; |
a09ba7fa | 2793 | |
14415745 | 2794 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2795 | obj->fence_dirty = false; |
14415745 | 2796 | |
9ce079e4 | 2797 | return 0; |
de151cf6 JB |
2798 | } |
2799 | ||
42d6ab48 CW |
2800 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2801 | struct drm_mm_node *gtt_space, | |
2802 | unsigned long cache_level) | |
2803 | { | |
2804 | struct drm_mm_node *other; | |
2805 | ||
2806 | /* On non-LLC machines we have to be careful when putting differing | |
2807 | * types of snoopable memory together to avoid the prefetcher | |
2808 | * crossing memory domains and dieing. | |
2809 | */ | |
2810 | if (HAS_LLC(dev)) | |
2811 | return true; | |
2812 | ||
2813 | if (gtt_space == NULL) | |
2814 | return true; | |
2815 | ||
2816 | if (list_empty(>t_space->node_list)) | |
2817 | return true; | |
2818 | ||
2819 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2820 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2821 | return false; | |
2822 | ||
2823 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2824 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2825 | return false; | |
2826 | ||
2827 | return true; | |
2828 | } | |
2829 | ||
2830 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2831 | { | |
2832 | #if WATCH_GTT | |
2833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2834 | struct drm_i915_gem_object *obj; | |
2835 | int err = 0; | |
2836 | ||
2837 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2838 | if (obj->gtt_space == NULL) { | |
2839 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2840 | err++; | |
2841 | continue; | |
2842 | } | |
2843 | ||
2844 | if (obj->cache_level != obj->gtt_space->color) { | |
2845 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2846 | obj->gtt_space->start, | |
2847 | obj->gtt_space->start + obj->gtt_space->size, | |
2848 | obj->cache_level, | |
2849 | obj->gtt_space->color); | |
2850 | err++; | |
2851 | continue; | |
2852 | } | |
2853 | ||
2854 | if (!i915_gem_valid_gtt_space(dev, | |
2855 | obj->gtt_space, | |
2856 | obj->cache_level)) { | |
2857 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2858 | obj->gtt_space->start, | |
2859 | obj->gtt_space->start + obj->gtt_space->size, | |
2860 | obj->cache_level); | |
2861 | err++; | |
2862 | continue; | |
2863 | } | |
2864 | } | |
2865 | ||
2866 | WARN_ON(err); | |
2867 | #endif | |
2868 | } | |
2869 | ||
673a394b EA |
2870 | /** |
2871 | * Finds free space in the GTT aperture and binds the object there. | |
2872 | */ | |
2873 | static int | |
05394f39 | 2874 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2875 | unsigned alignment, |
86a1ee26 CW |
2876 | bool map_and_fenceable, |
2877 | bool nonblocking) | |
673a394b | 2878 | { |
05394f39 | 2879 | struct drm_device *dev = obj->base.dev; |
673a394b | 2880 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2881 | struct drm_mm_node *free_space; |
5e783301 | 2882 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2883 | bool mappable, fenceable; |
07f73f69 | 2884 | int ret; |
673a394b | 2885 | |
05394f39 | 2886 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2887 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2888 | return -EINVAL; | |
2889 | } | |
2890 | ||
e28f8711 CW |
2891 | fence_size = i915_gem_get_gtt_size(dev, |
2892 | obj->base.size, | |
2893 | obj->tiling_mode); | |
2894 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2895 | obj->base.size, | |
2896 | obj->tiling_mode); | |
2897 | unfenced_alignment = | |
2898 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2899 | obj->base.size, | |
2900 | obj->tiling_mode); | |
a00b10c3 | 2901 | |
673a394b | 2902 | if (alignment == 0) |
5e783301 DV |
2903 | alignment = map_and_fenceable ? fence_alignment : |
2904 | unfenced_alignment; | |
75e9e915 | 2905 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2906 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2907 | return -EINVAL; | |
2908 | } | |
2909 | ||
05394f39 | 2910 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2911 | |
654fc607 CW |
2912 | /* If the object is bigger than the entire aperture, reject it early |
2913 | * before evicting everything in a vain attempt to find space. | |
2914 | */ | |
05394f39 | 2915 | if (obj->base.size > |
75e9e915 | 2916 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2917 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2918 | return -E2BIG; | |
2919 | } | |
2920 | ||
37e680a1 | 2921 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2922 | if (ret) |
2923 | return ret; | |
2924 | ||
673a394b | 2925 | search_free: |
75e9e915 | 2926 | if (map_and_fenceable) |
920afa77 | 2927 | free_space = |
42d6ab48 CW |
2928 | drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space, |
2929 | size, alignment, obj->cache_level, | |
2930 | 0, dev_priv->mm.gtt_mappable_end, | |
2931 | false); | |
920afa77 | 2932 | else |
42d6ab48 CW |
2933 | free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space, |
2934 | size, alignment, obj->cache_level, | |
2935 | false); | |
920afa77 DV |
2936 | |
2937 | if (free_space != NULL) { | |
75e9e915 | 2938 | if (map_and_fenceable) |
05394f39 | 2939 | obj->gtt_space = |
920afa77 | 2940 | drm_mm_get_block_range_generic(free_space, |
42d6ab48 | 2941 | size, alignment, obj->cache_level, |
6b9d89b4 | 2942 | 0, dev_priv->mm.gtt_mappable_end, |
42d6ab48 | 2943 | false); |
920afa77 | 2944 | else |
05394f39 | 2945 | obj->gtt_space = |
42d6ab48 CW |
2946 | drm_mm_get_block_generic(free_space, |
2947 | size, alignment, obj->cache_level, | |
2948 | false); | |
920afa77 | 2949 | } |
05394f39 | 2950 | if (obj->gtt_space == NULL) { |
75e9e915 | 2951 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2952 | obj->cache_level, |
86a1ee26 CW |
2953 | map_and_fenceable, |
2954 | nonblocking); | |
9731129c | 2955 | if (ret) |
673a394b | 2956 | return ret; |
9731129c | 2957 | |
673a394b EA |
2958 | goto search_free; |
2959 | } | |
42d6ab48 CW |
2960 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, |
2961 | obj->gtt_space, | |
2962 | obj->cache_level))) { | |
2963 | drm_mm_put_block(obj->gtt_space); | |
2964 | obj->gtt_space = NULL; | |
2965 | return -EINVAL; | |
2966 | } | |
673a394b | 2967 | |
673a394b | 2968 | |
74163907 | 2969 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2970 | if (ret) { |
05394f39 CW |
2971 | drm_mm_put_block(obj->gtt_space); |
2972 | obj->gtt_space = NULL; | |
6c085a72 | 2973 | return ret; |
673a394b | 2974 | } |
673a394b | 2975 | |
0ebb9829 DV |
2976 | if (!dev_priv->mm.aliasing_ppgtt) |
2977 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2978 | |
6c085a72 | 2979 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2980 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2981 | |
6299f992 | 2982 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2983 | |
75e9e915 | 2984 | fenceable = |
05394f39 | 2985 | obj->gtt_space->size == fence_size && |
0206e353 | 2986 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2987 | |
75e9e915 | 2988 | mappable = |
05394f39 | 2989 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2990 | |
05394f39 | 2991 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2992 | |
db53a302 | 2993 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 2994 | i915_gem_verify_gtt(dev); |
673a394b EA |
2995 | return 0; |
2996 | } | |
2997 | ||
2998 | void | |
05394f39 | 2999 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 3000 | { |
673a394b EA |
3001 | /* If we don't have a page list set up, then we're not pinned |
3002 | * to GPU, and we can ignore the cache flush because it'll happen | |
3003 | * again at bind time. | |
3004 | */ | |
05394f39 | 3005 | if (obj->pages == NULL) |
673a394b EA |
3006 | return; |
3007 | ||
9c23f7fc CW |
3008 | /* If the GPU is snooping the contents of the CPU cache, |
3009 | * we do not need to manually clear the CPU cache lines. However, | |
3010 | * the caches are only snooped when the render cache is | |
3011 | * flushed/invalidated. As we always have to emit invalidations | |
3012 | * and flushes when moving into and out of the RENDER domain, correct | |
3013 | * snooping behaviour occurs naturally as the result of our domain | |
3014 | * tracking. | |
3015 | */ | |
3016 | if (obj->cache_level != I915_CACHE_NONE) | |
3017 | return; | |
3018 | ||
1c5d22f7 | 3019 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3020 | |
9da3da66 | 3021 | drm_clflush_sg(obj->pages); |
673a394b EA |
3022 | } |
3023 | ||
e47c68e9 EA |
3024 | /** Flushes the GTT write domain for the object if it's dirty. */ |
3025 | static void | |
05394f39 | 3026 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3027 | { |
1c5d22f7 CW |
3028 | uint32_t old_write_domain; |
3029 | ||
05394f39 | 3030 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3031 | return; |
3032 | ||
63256ec5 | 3033 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3034 | * to it immediately go to main memory as far as we know, so there's |
3035 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3036 | * |
3037 | * However, we do have to enforce the order so that all writes through | |
3038 | * the GTT land before any writes to the device, such as updates to | |
3039 | * the GATT itself. | |
e47c68e9 | 3040 | */ |
63256ec5 CW |
3041 | wmb(); |
3042 | ||
05394f39 CW |
3043 | old_write_domain = obj->base.write_domain; |
3044 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3045 | |
3046 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3047 | obj->base.read_domains, |
1c5d22f7 | 3048 | old_write_domain); |
e47c68e9 EA |
3049 | } |
3050 | ||
3051 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3052 | static void | |
05394f39 | 3053 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3054 | { |
1c5d22f7 | 3055 | uint32_t old_write_domain; |
e47c68e9 | 3056 | |
05394f39 | 3057 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3058 | return; |
3059 | ||
3060 | i915_gem_clflush_object(obj); | |
40ce6575 | 3061 | intel_gtt_chipset_flush(); |
05394f39 CW |
3062 | old_write_domain = obj->base.write_domain; |
3063 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3064 | |
3065 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3066 | obj->base.read_domains, |
1c5d22f7 | 3067 | old_write_domain); |
e47c68e9 EA |
3068 | } |
3069 | ||
2ef7eeaa EA |
3070 | /** |
3071 | * Moves a single object to the GTT read, and possibly write domain. | |
3072 | * | |
3073 | * This function returns when the move is complete, including waiting on | |
3074 | * flushes to occur. | |
3075 | */ | |
79e53945 | 3076 | int |
2021746e | 3077 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3078 | { |
8325a09d | 3079 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3080 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3081 | int ret; |
2ef7eeaa | 3082 | |
02354392 | 3083 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3084 | if (obj->gtt_space == NULL) |
02354392 EA |
3085 | return -EINVAL; |
3086 | ||
8d7e3de1 CW |
3087 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3088 | return 0; | |
3089 | ||
0201f1ec CW |
3090 | ret = i915_gem_object_wait_rendering(obj, !write); |
3091 | if (ret) | |
3092 | return ret; | |
2dafb1e0 | 3093 | |
7213342d | 3094 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3095 | |
05394f39 CW |
3096 | old_write_domain = obj->base.write_domain; |
3097 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3098 | |
e47c68e9 EA |
3099 | /* It should now be out of any other write domains, and we can update |
3100 | * the domain values for our changes. | |
3101 | */ | |
05394f39 CW |
3102 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3103 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3104 | if (write) { |
05394f39 CW |
3105 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3106 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3107 | obj->dirty = 1; | |
2ef7eeaa EA |
3108 | } |
3109 | ||
1c5d22f7 CW |
3110 | trace_i915_gem_object_change_domain(obj, |
3111 | old_read_domains, | |
3112 | old_write_domain); | |
3113 | ||
8325a09d CW |
3114 | /* And bump the LRU for this access */ |
3115 | if (i915_gem_object_is_inactive(obj)) | |
3116 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3117 | ||
e47c68e9 EA |
3118 | return 0; |
3119 | } | |
3120 | ||
e4ffd173 CW |
3121 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3122 | enum i915_cache_level cache_level) | |
3123 | { | |
7bddb01f DV |
3124 | struct drm_device *dev = obj->base.dev; |
3125 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3126 | int ret; |
3127 | ||
3128 | if (obj->cache_level == cache_level) | |
3129 | return 0; | |
3130 | ||
3131 | if (obj->pin_count) { | |
3132 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3133 | return -EBUSY; | |
3134 | } | |
3135 | ||
42d6ab48 CW |
3136 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3137 | ret = i915_gem_object_unbind(obj); | |
3138 | if (ret) | |
3139 | return ret; | |
3140 | } | |
3141 | ||
e4ffd173 CW |
3142 | if (obj->gtt_space) { |
3143 | ret = i915_gem_object_finish_gpu(obj); | |
3144 | if (ret) | |
3145 | return ret; | |
3146 | ||
3147 | i915_gem_object_finish_gtt(obj); | |
3148 | ||
3149 | /* Before SandyBridge, you could not use tiling or fence | |
3150 | * registers with snooped memory, so relinquish any fences | |
3151 | * currently pointing to our region in the aperture. | |
3152 | */ | |
42d6ab48 | 3153 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3154 | ret = i915_gem_object_put_fence(obj); |
3155 | if (ret) | |
3156 | return ret; | |
3157 | } | |
3158 | ||
74898d7e DV |
3159 | if (obj->has_global_gtt_mapping) |
3160 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3161 | if (obj->has_aliasing_ppgtt_mapping) |
3162 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3163 | obj, cache_level); | |
42d6ab48 CW |
3164 | |
3165 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3166 | } |
3167 | ||
3168 | if (cache_level == I915_CACHE_NONE) { | |
3169 | u32 old_read_domains, old_write_domain; | |
3170 | ||
3171 | /* If we're coming from LLC cached, then we haven't | |
3172 | * actually been tracking whether the data is in the | |
3173 | * CPU cache or not, since we only allow one bit set | |
3174 | * in obj->write_domain and have been skipping the clflushes. | |
3175 | * Just set it to the CPU cache for now. | |
3176 | */ | |
3177 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3178 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3179 | ||
3180 | old_read_domains = obj->base.read_domains; | |
3181 | old_write_domain = obj->base.write_domain; | |
3182 | ||
3183 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3184 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3185 | ||
3186 | trace_i915_gem_object_change_domain(obj, | |
3187 | old_read_domains, | |
3188 | old_write_domain); | |
3189 | } | |
3190 | ||
3191 | obj->cache_level = cache_level; | |
42d6ab48 | 3192 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3193 | return 0; |
3194 | } | |
3195 | ||
199adf40 BW |
3196 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3197 | struct drm_file *file) | |
e6994aee | 3198 | { |
199adf40 | 3199 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3200 | struct drm_i915_gem_object *obj; |
3201 | int ret; | |
3202 | ||
3203 | ret = i915_mutex_lock_interruptible(dev); | |
3204 | if (ret) | |
3205 | return ret; | |
3206 | ||
3207 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3208 | if (&obj->base == NULL) { | |
3209 | ret = -ENOENT; | |
3210 | goto unlock; | |
3211 | } | |
3212 | ||
199adf40 | 3213 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3214 | |
3215 | drm_gem_object_unreference(&obj->base); | |
3216 | unlock: | |
3217 | mutex_unlock(&dev->struct_mutex); | |
3218 | return ret; | |
3219 | } | |
3220 | ||
199adf40 BW |
3221 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3222 | struct drm_file *file) | |
e6994aee | 3223 | { |
199adf40 | 3224 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3225 | struct drm_i915_gem_object *obj; |
3226 | enum i915_cache_level level; | |
3227 | int ret; | |
3228 | ||
199adf40 BW |
3229 | switch (args->caching) { |
3230 | case I915_CACHING_NONE: | |
e6994aee CW |
3231 | level = I915_CACHE_NONE; |
3232 | break; | |
199adf40 | 3233 | case I915_CACHING_CACHED: |
e6994aee CW |
3234 | level = I915_CACHE_LLC; |
3235 | break; | |
3236 | default: | |
3237 | return -EINVAL; | |
3238 | } | |
3239 | ||
3bc2913e BW |
3240 | ret = i915_mutex_lock_interruptible(dev); |
3241 | if (ret) | |
3242 | return ret; | |
3243 | ||
e6994aee CW |
3244 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3245 | if (&obj->base == NULL) { | |
3246 | ret = -ENOENT; | |
3247 | goto unlock; | |
3248 | } | |
3249 | ||
3250 | ret = i915_gem_object_set_cache_level(obj, level); | |
3251 | ||
3252 | drm_gem_object_unreference(&obj->base); | |
3253 | unlock: | |
3254 | mutex_unlock(&dev->struct_mutex); | |
3255 | return ret; | |
3256 | } | |
3257 | ||
b9241ea3 | 3258 | /* |
2da3b9b9 CW |
3259 | * Prepare buffer for display plane (scanout, cursors, etc). |
3260 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3261 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3262 | */ |
3263 | int | |
2da3b9b9 CW |
3264 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3265 | u32 alignment, | |
919926ae | 3266 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3267 | { |
2da3b9b9 | 3268 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3269 | int ret; |
3270 | ||
0be73284 | 3271 | if (pipelined != obj->ring) { |
2911a35b BW |
3272 | ret = i915_gem_object_sync(obj, pipelined); |
3273 | if (ret) | |
b9241ea3 ZW |
3274 | return ret; |
3275 | } | |
3276 | ||
a7ef0640 EA |
3277 | /* The display engine is not coherent with the LLC cache on gen6. As |
3278 | * a result, we make sure that the pinning that is about to occur is | |
3279 | * done with uncached PTEs. This is lowest common denominator for all | |
3280 | * chipsets. | |
3281 | * | |
3282 | * However for gen6+, we could do better by using the GFDT bit instead | |
3283 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3284 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3285 | */ | |
3286 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3287 | if (ret) | |
3288 | return ret; | |
3289 | ||
2da3b9b9 CW |
3290 | /* As the user may map the buffer once pinned in the display plane |
3291 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3292 | * always use map_and_fenceable for all scanout buffers. | |
3293 | */ | |
86a1ee26 | 3294 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3295 | if (ret) |
3296 | return ret; | |
3297 | ||
b118c1e3 CW |
3298 | i915_gem_object_flush_cpu_write_domain(obj); |
3299 | ||
2da3b9b9 | 3300 | old_write_domain = obj->base.write_domain; |
05394f39 | 3301 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3302 | |
3303 | /* It should now be out of any other write domains, and we can update | |
3304 | * the domain values for our changes. | |
3305 | */ | |
e5f1d962 | 3306 | obj->base.write_domain = 0; |
05394f39 | 3307 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3308 | |
3309 | trace_i915_gem_object_change_domain(obj, | |
3310 | old_read_domains, | |
2da3b9b9 | 3311 | old_write_domain); |
b9241ea3 ZW |
3312 | |
3313 | return 0; | |
3314 | } | |
3315 | ||
85345517 | 3316 | int |
a8198eea | 3317 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3318 | { |
88241785 CW |
3319 | int ret; |
3320 | ||
a8198eea | 3321 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3322 | return 0; |
3323 | ||
0201f1ec | 3324 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3325 | if (ret) |
3326 | return ret; | |
3327 | ||
a8198eea CW |
3328 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3329 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3330 | return 0; |
85345517 CW |
3331 | } |
3332 | ||
e47c68e9 EA |
3333 | /** |
3334 | * Moves a single object to the CPU read, and possibly write domain. | |
3335 | * | |
3336 | * This function returns when the move is complete, including waiting on | |
3337 | * flushes to occur. | |
3338 | */ | |
dabdfe02 | 3339 | int |
919926ae | 3340 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3341 | { |
1c5d22f7 | 3342 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3343 | int ret; |
3344 | ||
8d7e3de1 CW |
3345 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3346 | return 0; | |
3347 | ||
0201f1ec CW |
3348 | ret = i915_gem_object_wait_rendering(obj, !write); |
3349 | if (ret) | |
3350 | return ret; | |
2ef7eeaa | 3351 | |
e47c68e9 | 3352 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3353 | |
05394f39 CW |
3354 | old_write_domain = obj->base.write_domain; |
3355 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3356 | |
e47c68e9 | 3357 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3358 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3359 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3360 | |
05394f39 | 3361 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3362 | } |
3363 | ||
3364 | /* It should now be out of any other write domains, and we can update | |
3365 | * the domain values for our changes. | |
3366 | */ | |
05394f39 | 3367 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3368 | |
3369 | /* If we're writing through the CPU, then the GPU read domains will | |
3370 | * need to be invalidated at next use. | |
3371 | */ | |
3372 | if (write) { | |
05394f39 CW |
3373 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3374 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3375 | } |
2ef7eeaa | 3376 | |
1c5d22f7 CW |
3377 | trace_i915_gem_object_change_domain(obj, |
3378 | old_read_domains, | |
3379 | old_write_domain); | |
3380 | ||
2ef7eeaa EA |
3381 | return 0; |
3382 | } | |
3383 | ||
673a394b EA |
3384 | /* Throttle our rendering by waiting until the ring has completed our requests |
3385 | * emitted over 20 msec ago. | |
3386 | * | |
b962442e EA |
3387 | * Note that if we were to use the current jiffies each time around the loop, |
3388 | * we wouldn't escape the function with any frames outstanding if the time to | |
3389 | * render a frame was over 20ms. | |
3390 | * | |
673a394b EA |
3391 | * This should get us reasonable parallelism between CPU and GPU but also |
3392 | * relatively low latency when blocking on a particular request to finish. | |
3393 | */ | |
40a5f0de | 3394 | static int |
f787a5f5 | 3395 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3396 | { |
f787a5f5 CW |
3397 | struct drm_i915_private *dev_priv = dev->dev_private; |
3398 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3399 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3400 | struct drm_i915_gem_request *request; |
3401 | struct intel_ring_buffer *ring = NULL; | |
3402 | u32 seqno = 0; | |
3403 | int ret; | |
93533c29 | 3404 | |
e110e8d6 CW |
3405 | if (atomic_read(&dev_priv->mm.wedged)) |
3406 | return -EIO; | |
3407 | ||
1c25595f | 3408 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3409 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3410 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3411 | break; | |
40a5f0de | 3412 | |
f787a5f5 CW |
3413 | ring = request->ring; |
3414 | seqno = request->seqno; | |
b962442e | 3415 | } |
1c25595f | 3416 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3417 | |
f787a5f5 CW |
3418 | if (seqno == 0) |
3419 | return 0; | |
2bc43b5c | 3420 | |
5c81fe85 | 3421 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3422 | if (ret == 0) |
3423 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3424 | |
3425 | return ret; | |
3426 | } | |
3427 | ||
673a394b | 3428 | int |
05394f39 CW |
3429 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3430 | uint32_t alignment, | |
86a1ee26 CW |
3431 | bool map_and_fenceable, |
3432 | bool nonblocking) | |
673a394b | 3433 | { |
673a394b EA |
3434 | int ret; |
3435 | ||
7e81a42e CW |
3436 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3437 | return -EBUSY; | |
ac0c6b5a | 3438 | |
05394f39 CW |
3439 | if (obj->gtt_space != NULL) { |
3440 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3441 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3442 | WARN(obj->pin_count, | |
ae7d49d8 | 3443 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3444 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3445 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3446 | obj->gtt_offset, alignment, |
75e9e915 | 3447 | map_and_fenceable, |
05394f39 | 3448 | obj->map_and_fenceable); |
ac0c6b5a CW |
3449 | ret = i915_gem_object_unbind(obj); |
3450 | if (ret) | |
3451 | return ret; | |
3452 | } | |
3453 | } | |
3454 | ||
05394f39 | 3455 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3456 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3457 | map_and_fenceable, |
3458 | nonblocking); | |
9731129c | 3459 | if (ret) |
673a394b | 3460 | return ret; |
22c344e9 | 3461 | } |
76446cac | 3462 | |
74898d7e DV |
3463 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3464 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3465 | ||
1b50247a | 3466 | obj->pin_count++; |
6299f992 | 3467 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3468 | |
3469 | return 0; | |
3470 | } | |
3471 | ||
3472 | void | |
05394f39 | 3473 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3474 | { |
05394f39 CW |
3475 | BUG_ON(obj->pin_count == 0); |
3476 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3477 | |
1b50247a | 3478 | if (--obj->pin_count == 0) |
6299f992 | 3479 | obj->pin_mappable = false; |
673a394b EA |
3480 | } |
3481 | ||
3482 | int | |
3483 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3484 | struct drm_file *file) |
673a394b EA |
3485 | { |
3486 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3487 | struct drm_i915_gem_object *obj; |
673a394b EA |
3488 | int ret; |
3489 | ||
1d7cfea1 CW |
3490 | ret = i915_mutex_lock_interruptible(dev); |
3491 | if (ret) | |
3492 | return ret; | |
673a394b | 3493 | |
05394f39 | 3494 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3495 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3496 | ret = -ENOENT; |
3497 | goto unlock; | |
673a394b | 3498 | } |
673a394b | 3499 | |
05394f39 | 3500 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3501 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3502 | ret = -EINVAL; |
3503 | goto out; | |
3ef94daa CW |
3504 | } |
3505 | ||
05394f39 | 3506 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3507 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3508 | args->handle); | |
1d7cfea1 CW |
3509 | ret = -EINVAL; |
3510 | goto out; | |
79e53945 JB |
3511 | } |
3512 | ||
05394f39 CW |
3513 | obj->user_pin_count++; |
3514 | obj->pin_filp = file; | |
3515 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3516 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3517 | if (ret) |
3518 | goto out; | |
673a394b EA |
3519 | } |
3520 | ||
3521 | /* XXX - flush the CPU caches for pinned objects | |
3522 | * as the X server doesn't manage domains yet | |
3523 | */ | |
e47c68e9 | 3524 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3525 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3526 | out: |
05394f39 | 3527 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3528 | unlock: |
673a394b | 3529 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3530 | return ret; |
673a394b EA |
3531 | } |
3532 | ||
3533 | int | |
3534 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3535 | struct drm_file *file) |
673a394b EA |
3536 | { |
3537 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3538 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3539 | int ret; |
673a394b | 3540 | |
1d7cfea1 CW |
3541 | ret = i915_mutex_lock_interruptible(dev); |
3542 | if (ret) | |
3543 | return ret; | |
673a394b | 3544 | |
05394f39 | 3545 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3546 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3547 | ret = -ENOENT; |
3548 | goto unlock; | |
673a394b | 3549 | } |
76c1dec1 | 3550 | |
05394f39 | 3551 | if (obj->pin_filp != file) { |
79e53945 JB |
3552 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3553 | args->handle); | |
1d7cfea1 CW |
3554 | ret = -EINVAL; |
3555 | goto out; | |
79e53945 | 3556 | } |
05394f39 CW |
3557 | obj->user_pin_count--; |
3558 | if (obj->user_pin_count == 0) { | |
3559 | obj->pin_filp = NULL; | |
79e53945 JB |
3560 | i915_gem_object_unpin(obj); |
3561 | } | |
673a394b | 3562 | |
1d7cfea1 | 3563 | out: |
05394f39 | 3564 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3565 | unlock: |
673a394b | 3566 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3567 | return ret; |
673a394b EA |
3568 | } |
3569 | ||
3570 | int | |
3571 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3572 | struct drm_file *file) |
673a394b EA |
3573 | { |
3574 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3575 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3576 | int ret; |
3577 | ||
76c1dec1 | 3578 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3579 | if (ret) |
76c1dec1 | 3580 | return ret; |
673a394b | 3581 | |
05394f39 | 3582 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3583 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3584 | ret = -ENOENT; |
3585 | goto unlock; | |
673a394b | 3586 | } |
d1b851fc | 3587 | |
0be555b6 CW |
3588 | /* Count all active objects as busy, even if they are currently not used |
3589 | * by the gpu. Users of this interface expect objects to eventually | |
3590 | * become non-busy without any further actions, therefore emit any | |
3591 | * necessary flushes here. | |
c4de0a5d | 3592 | */ |
30dfebf3 | 3593 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3594 | |
30dfebf3 | 3595 | args->busy = obj->active; |
e9808edd CW |
3596 | if (obj->ring) { |
3597 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3598 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3599 | } | |
673a394b | 3600 | |
05394f39 | 3601 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3602 | unlock: |
673a394b | 3603 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3604 | return ret; |
673a394b EA |
3605 | } |
3606 | ||
3607 | int | |
3608 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3609 | struct drm_file *file_priv) | |
3610 | { | |
0206e353 | 3611 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3612 | } |
3613 | ||
3ef94daa CW |
3614 | int |
3615 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3616 | struct drm_file *file_priv) | |
3617 | { | |
3618 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3619 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3620 | int ret; |
3ef94daa CW |
3621 | |
3622 | switch (args->madv) { | |
3623 | case I915_MADV_DONTNEED: | |
3624 | case I915_MADV_WILLNEED: | |
3625 | break; | |
3626 | default: | |
3627 | return -EINVAL; | |
3628 | } | |
3629 | ||
1d7cfea1 CW |
3630 | ret = i915_mutex_lock_interruptible(dev); |
3631 | if (ret) | |
3632 | return ret; | |
3633 | ||
05394f39 | 3634 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3635 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3636 | ret = -ENOENT; |
3637 | goto unlock; | |
3ef94daa | 3638 | } |
3ef94daa | 3639 | |
05394f39 | 3640 | if (obj->pin_count) { |
1d7cfea1 CW |
3641 | ret = -EINVAL; |
3642 | goto out; | |
3ef94daa CW |
3643 | } |
3644 | ||
05394f39 CW |
3645 | if (obj->madv != __I915_MADV_PURGED) |
3646 | obj->madv = args->madv; | |
3ef94daa | 3647 | |
6c085a72 CW |
3648 | /* if the object is no longer attached, discard its backing storage */ |
3649 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3650 | i915_gem_object_truncate(obj); |
3651 | ||
05394f39 | 3652 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3653 | |
1d7cfea1 | 3654 | out: |
05394f39 | 3655 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3656 | unlock: |
3ef94daa | 3657 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3658 | return ret; |
3ef94daa CW |
3659 | } |
3660 | ||
37e680a1 CW |
3661 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3662 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3663 | { |
0327d6ba CW |
3664 | INIT_LIST_HEAD(&obj->mm_list); |
3665 | INIT_LIST_HEAD(&obj->gtt_list); | |
3666 | INIT_LIST_HEAD(&obj->ring_list); | |
3667 | INIT_LIST_HEAD(&obj->exec_list); | |
3668 | ||
37e680a1 CW |
3669 | obj->ops = ops; |
3670 | ||
0327d6ba CW |
3671 | obj->fence_reg = I915_FENCE_REG_NONE; |
3672 | obj->madv = I915_MADV_WILLNEED; | |
3673 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3674 | obj->map_and_fenceable = true; | |
3675 | ||
3676 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3677 | } | |
3678 | ||
37e680a1 CW |
3679 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3680 | .get_pages = i915_gem_object_get_pages_gtt, | |
3681 | .put_pages = i915_gem_object_put_pages_gtt, | |
3682 | }; | |
3683 | ||
05394f39 CW |
3684 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3685 | size_t size) | |
ac52bc56 | 3686 | { |
c397b908 | 3687 | struct drm_i915_gem_object *obj; |
5949eac4 | 3688 | struct address_space *mapping; |
bed1ea95 | 3689 | u32 mask; |
ac52bc56 | 3690 | |
c397b908 DV |
3691 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3692 | if (obj == NULL) | |
3693 | return NULL; | |
673a394b | 3694 | |
c397b908 DV |
3695 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3696 | kfree(obj); | |
3697 | return NULL; | |
3698 | } | |
673a394b | 3699 | |
bed1ea95 CW |
3700 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3701 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3702 | /* 965gm cannot relocate objects above 4GiB. */ | |
3703 | mask &= ~__GFP_HIGHMEM; | |
3704 | mask |= __GFP_DMA32; | |
3705 | } | |
3706 | ||
5949eac4 | 3707 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3708 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3709 | |
37e680a1 | 3710 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3711 | |
c397b908 DV |
3712 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3713 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3714 | |
3d29b842 ED |
3715 | if (HAS_LLC(dev)) { |
3716 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3717 | * cache) for about a 10% performance improvement |
3718 | * compared to uncached. Graphics requests other than | |
3719 | * display scanout are coherent with the CPU in | |
3720 | * accessing this cache. This means in this mode we | |
3721 | * don't need to clflush on the CPU side, and on the | |
3722 | * GPU side we only need to flush internal caches to | |
3723 | * get data visible to the CPU. | |
3724 | * | |
3725 | * However, we maintain the display planes as UC, and so | |
3726 | * need to rebind when first used as such. | |
3727 | */ | |
3728 | obj->cache_level = I915_CACHE_LLC; | |
3729 | } else | |
3730 | obj->cache_level = I915_CACHE_NONE; | |
3731 | ||
05394f39 | 3732 | return obj; |
c397b908 DV |
3733 | } |
3734 | ||
3735 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3736 | { | |
3737 | BUG(); | |
de151cf6 | 3738 | |
673a394b EA |
3739 | return 0; |
3740 | } | |
3741 | ||
1488fc08 | 3742 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3743 | { |
1488fc08 | 3744 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3745 | struct drm_device *dev = obj->base.dev; |
be72615b | 3746 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3747 | |
26e12f89 CW |
3748 | trace_i915_gem_object_destroy(obj); |
3749 | ||
1488fc08 CW |
3750 | if (obj->phys_obj) |
3751 | i915_gem_detach_phys_object(dev, obj); | |
3752 | ||
3753 | obj->pin_count = 0; | |
3754 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3755 | bool was_interruptible; | |
3756 | ||
3757 | was_interruptible = dev_priv->mm.interruptible; | |
3758 | dev_priv->mm.interruptible = false; | |
3759 | ||
3760 | WARN_ON(i915_gem_object_unbind(obj)); | |
3761 | ||
3762 | dev_priv->mm.interruptible = was_interruptible; | |
3763 | } | |
3764 | ||
a5570178 | 3765 | obj->pages_pin_count = 0; |
37e680a1 | 3766 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3767 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 3768 | |
9da3da66 CW |
3769 | BUG_ON(obj->pages); |
3770 | ||
2f745ad3 CW |
3771 | if (obj->base.import_attach) |
3772 | drm_prime_gem_destroy(&obj->base, NULL); | |
3773 | ||
05394f39 CW |
3774 | drm_gem_object_release(&obj->base); |
3775 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3776 | |
05394f39 CW |
3777 | kfree(obj->bit_17); |
3778 | kfree(obj); | |
673a394b EA |
3779 | } |
3780 | ||
29105ccc CW |
3781 | int |
3782 | i915_gem_idle(struct drm_device *dev) | |
3783 | { | |
3784 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3785 | int ret; | |
28dfe52a | 3786 | |
29105ccc | 3787 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3788 | |
87acb0a5 | 3789 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3790 | mutex_unlock(&dev->struct_mutex); |
3791 | return 0; | |
28dfe52a EA |
3792 | } |
3793 | ||
b2da9fe5 | 3794 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3795 | if (ret) { |
3796 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3797 | return ret; |
6dbe2772 | 3798 | } |
b2da9fe5 | 3799 | i915_gem_retire_requests(dev); |
673a394b | 3800 | |
29105ccc | 3801 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3802 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3803 | i915_gem_evict_everything(dev); |
29105ccc | 3804 | |
312817a3 CW |
3805 | i915_gem_reset_fences(dev); |
3806 | ||
29105ccc CW |
3807 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3808 | * We need to replace this with a semaphore, or something. | |
3809 | * And not confound mm.suspended! | |
3810 | */ | |
3811 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3812 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3813 | |
3814 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3815 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3816 | |
6dbe2772 KP |
3817 | mutex_unlock(&dev->struct_mutex); |
3818 | ||
29105ccc CW |
3819 | /* Cancel the retire work handler, which should be idle now. */ |
3820 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3821 | ||
673a394b EA |
3822 | return 0; |
3823 | } | |
3824 | ||
b9524a1e BW |
3825 | void i915_gem_l3_remap(struct drm_device *dev) |
3826 | { | |
3827 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3828 | u32 misccpctl; | |
3829 | int i; | |
3830 | ||
3831 | if (!IS_IVYBRIDGE(dev)) | |
3832 | return; | |
3833 | ||
a4da4fa4 | 3834 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
3835 | return; |
3836 | ||
3837 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3838 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3839 | POSTING_READ(GEN7_MISCCPCTL); | |
3840 | ||
3841 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3842 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 3843 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
3844 | DRM_DEBUG("0x%x was already programmed to %x\n", |
3845 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 3846 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 3847 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 3848 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
3849 | } |
3850 | ||
3851 | /* Make sure all the writes land before disabling dop clock gating */ | |
3852 | POSTING_READ(GEN7_L3LOG_BASE); | |
3853 | ||
3854 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3855 | } | |
3856 | ||
f691e2f4 DV |
3857 | void i915_gem_init_swizzling(struct drm_device *dev) |
3858 | { | |
3859 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3860 | ||
11782b02 | 3861 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3862 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3863 | return; | |
3864 | ||
3865 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3866 | DISP_TILE_SURFACE_SWIZZLING); | |
3867 | ||
11782b02 DV |
3868 | if (IS_GEN5(dev)) |
3869 | return; | |
3870 | ||
f691e2f4 DV |
3871 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3872 | if (IS_GEN6(dev)) | |
6b26c86d | 3873 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3874 | else |
6b26c86d | 3875 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3876 | } |
e21af88d DV |
3877 | |
3878 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3879 | { | |
3880 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3881 | uint32_t pd_offset; | |
3882 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3883 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3884 | uint32_t __iomem *pd_addr; | |
3885 | uint32_t pd_entry; | |
e21af88d DV |
3886 | int i; |
3887 | ||
3888 | if (!dev_priv->mm.aliasing_ppgtt) | |
3889 | return; | |
3890 | ||
55a254ac DV |
3891 | |
3892 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3893 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3894 | dma_addr_t pt_addr; | |
3895 | ||
3896 | if (dev_priv->mm.gtt->needs_dmar) | |
3897 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3898 | else | |
3899 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3900 | ||
3901 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3902 | pd_entry |= GEN6_PDE_VALID; | |
3903 | ||
3904 | writel(pd_entry, pd_addr + i); | |
3905 | } | |
3906 | readl(pd_addr); | |
3907 | ||
3908 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3909 | pd_offset /= 64; /* in cachelines, */ |
3910 | pd_offset <<= 16; | |
3911 | ||
3912 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3913 | uint32_t ecochk, gab_ctl, ecobits; |
3914 | ||
3915 | ecobits = I915_READ(GAC_ECO_BITS); | |
3916 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3917 | |
3918 | gab_ctl = I915_READ(GAB_CTL); | |
3919 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3920 | ||
3921 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3922 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3923 | ECOCHK_PPGTT_CACHE64B); | |
6b26c86d | 3924 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3925 | } else if (INTEL_INFO(dev)->gen >= 7) { |
3926 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3927 | /* GFX_MODE is per-ring on gen7+ */ | |
3928 | } | |
3929 | ||
b4519513 | 3930 | for_each_ring(ring, dev_priv, i) { |
e21af88d DV |
3931 | if (INTEL_INFO(dev)->gen >= 7) |
3932 | I915_WRITE(RING_MODE_GEN7(ring), | |
6b26c86d | 3933 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3934 | |
3935 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3936 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3937 | } | |
3938 | } | |
3939 | ||
67b1b571 CW |
3940 | static bool |
3941 | intel_enable_blt(struct drm_device *dev) | |
3942 | { | |
3943 | if (!HAS_BLT(dev)) | |
3944 | return false; | |
3945 | ||
3946 | /* The blitter was dysfunctional on early prototypes */ | |
3947 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3948 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3949 | " graphics performance will be degraded.\n"); | |
3950 | return false; | |
3951 | } | |
3952 | ||
3953 | return true; | |
3954 | } | |
3955 | ||
8187a2b7 | 3956 | int |
f691e2f4 | 3957 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3958 | { |
3959 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3960 | int ret; | |
68f95ba9 | 3961 | |
8ecd1a66 DV |
3962 | if (!intel_enable_gtt()) |
3963 | return -EIO; | |
3964 | ||
eda2d7f5 RV |
3965 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
3966 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
3967 | ||
b9524a1e BW |
3968 | i915_gem_l3_remap(dev); |
3969 | ||
f691e2f4 DV |
3970 | i915_gem_init_swizzling(dev); |
3971 | ||
5c1143bb | 3972 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3973 | if (ret) |
b6913e4b | 3974 | return ret; |
68f95ba9 CW |
3975 | |
3976 | if (HAS_BSD(dev)) { | |
5c1143bb | 3977 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3978 | if (ret) |
3979 | goto cleanup_render_ring; | |
d1b851fc | 3980 | } |
68f95ba9 | 3981 | |
67b1b571 | 3982 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3983 | ret = intel_init_blt_ring_buffer(dev); |
3984 | if (ret) | |
3985 | goto cleanup_bsd_ring; | |
3986 | } | |
3987 | ||
6f392d54 CW |
3988 | dev_priv->next_seqno = 1; |
3989 | ||
254f965c BW |
3990 | /* |
3991 | * XXX: There was some w/a described somewhere suggesting loading | |
3992 | * contexts before PPGTT. | |
3993 | */ | |
3994 | i915_gem_context_init(dev); | |
e21af88d DV |
3995 | i915_gem_init_ppgtt(dev); |
3996 | ||
68f95ba9 CW |
3997 | return 0; |
3998 | ||
549f7365 | 3999 | cleanup_bsd_ring: |
1ec14ad3 | 4000 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 4001 | cleanup_render_ring: |
1ec14ad3 | 4002 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
4003 | return ret; |
4004 | } | |
4005 | ||
1070a42b CW |
4006 | static bool |
4007 | intel_enable_ppgtt(struct drm_device *dev) | |
4008 | { | |
4009 | if (i915_enable_ppgtt >= 0) | |
4010 | return i915_enable_ppgtt; | |
4011 | ||
4012 | #ifdef CONFIG_INTEL_IOMMU | |
4013 | /* Disable ppgtt on SNB if VT-d is on. */ | |
4014 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
4015 | return false; | |
4016 | #endif | |
4017 | ||
4018 | return true; | |
4019 | } | |
4020 | ||
4021 | int i915_gem_init(struct drm_device *dev) | |
4022 | { | |
4023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4024 | unsigned long gtt_size, mappable_size; | |
4025 | int ret; | |
4026 | ||
4027 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
4028 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
4029 | ||
4030 | mutex_lock(&dev->struct_mutex); | |
4031 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
4032 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
4033 | * aperture accordingly when using aliasing ppgtt. */ | |
4034 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
4035 | ||
4036 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
4037 | ||
4038 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
4039 | if (ret) { | |
4040 | mutex_unlock(&dev->struct_mutex); | |
4041 | return ret; | |
4042 | } | |
4043 | } else { | |
4044 | /* Let GEM Manage all of the aperture. | |
4045 | * | |
4046 | * However, leave one page at the end still bound to the scratch | |
4047 | * page. There are a number of places where the hardware | |
4048 | * apparently prefetches past the end of the object, and we've | |
4049 | * seen multiple hangs with the GPU head pointer stuck in a | |
4050 | * batchbuffer bound at the last page of the aperture. One page | |
4051 | * should be enough to keep any prefetching inside of the | |
4052 | * aperture. | |
4053 | */ | |
4054 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
4055 | gtt_size); | |
4056 | } | |
4057 | ||
4058 | ret = i915_gem_init_hw(dev); | |
4059 | mutex_unlock(&dev->struct_mutex); | |
4060 | if (ret) { | |
4061 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4062 | return ret; | |
4063 | } | |
4064 | ||
53ca26ca DV |
4065 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4066 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4067 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4068 | return 0; |
4069 | } | |
4070 | ||
8187a2b7 ZN |
4071 | void |
4072 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4073 | { | |
4074 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4075 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4076 | int i; |
8187a2b7 | 4077 | |
b4519513 CW |
4078 | for_each_ring(ring, dev_priv, i) |
4079 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4080 | } |
4081 | ||
673a394b EA |
4082 | int |
4083 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4084 | struct drm_file *file_priv) | |
4085 | { | |
4086 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4087 | int ret; |
673a394b | 4088 | |
79e53945 JB |
4089 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4090 | return 0; | |
4091 | ||
ba1234d1 | 4092 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4093 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4094 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4095 | } |
4096 | ||
673a394b | 4097 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4098 | dev_priv->mm.suspended = 0; |
4099 | ||
f691e2f4 | 4100 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4101 | if (ret != 0) { |
4102 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4103 | return ret; |
d816f6ac | 4104 | } |
9bb2d6f9 | 4105 | |
69dc4987 | 4106 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4107 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4108 | |
5f35308b CW |
4109 | ret = drm_irq_install(dev); |
4110 | if (ret) | |
4111 | goto cleanup_ringbuffer; | |
dbb19d30 | 4112 | |
673a394b | 4113 | return 0; |
5f35308b CW |
4114 | |
4115 | cleanup_ringbuffer: | |
4116 | mutex_lock(&dev->struct_mutex); | |
4117 | i915_gem_cleanup_ringbuffer(dev); | |
4118 | dev_priv->mm.suspended = 1; | |
4119 | mutex_unlock(&dev->struct_mutex); | |
4120 | ||
4121 | return ret; | |
673a394b EA |
4122 | } |
4123 | ||
4124 | int | |
4125 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4126 | struct drm_file *file_priv) | |
4127 | { | |
79e53945 JB |
4128 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4129 | return 0; | |
4130 | ||
dbb19d30 | 4131 | drm_irq_uninstall(dev); |
e6890f6f | 4132 | return i915_gem_idle(dev); |
673a394b EA |
4133 | } |
4134 | ||
4135 | void | |
4136 | i915_gem_lastclose(struct drm_device *dev) | |
4137 | { | |
4138 | int ret; | |
673a394b | 4139 | |
e806b495 EA |
4140 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4141 | return; | |
4142 | ||
6dbe2772 KP |
4143 | ret = i915_gem_idle(dev); |
4144 | if (ret) | |
4145 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4146 | } |
4147 | ||
64193406 CW |
4148 | static void |
4149 | init_ring_lists(struct intel_ring_buffer *ring) | |
4150 | { | |
4151 | INIT_LIST_HEAD(&ring->active_list); | |
4152 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4153 | } |
4154 | ||
673a394b EA |
4155 | void |
4156 | i915_gem_load(struct drm_device *dev) | |
4157 | { | |
b5aa8a0f | 4158 | int i; |
673a394b EA |
4159 | drm_i915_private_t *dev_priv = dev->dev_private; |
4160 | ||
69dc4987 | 4161 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4162 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4163 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4164 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4165 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4166 | for (i = 0; i < I915_NUM_RINGS; i++) |
4167 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4168 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4169 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4170 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4171 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4172 | init_completion(&dev_priv->error_completion); |
31169714 | 4173 | |
94400120 DA |
4174 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4175 | if (IS_GEN3(dev)) { | |
50743298 DV |
4176 | I915_WRITE(MI_ARB_STATE, |
4177 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4178 | } |
4179 | ||
72bfa19c CW |
4180 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4181 | ||
de151cf6 | 4182 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4183 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4184 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4185 | |
a6c45cf0 | 4186 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4187 | dev_priv->num_fence_regs = 16; |
4188 | else | |
4189 | dev_priv->num_fence_regs = 8; | |
4190 | ||
b5aa8a0f | 4191 | /* Initialize fence registers to zero */ |
ada726c7 | 4192 | i915_gem_reset_fences(dev); |
10ed13e4 | 4193 | |
673a394b | 4194 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4195 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4196 | |
ce453d81 CW |
4197 | dev_priv->mm.interruptible = true; |
4198 | ||
17250b71 CW |
4199 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4200 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4201 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4202 | } |
71acb5eb DA |
4203 | |
4204 | /* | |
4205 | * Create a physically contiguous memory object for this object | |
4206 | * e.g. for cursor + overlay regs | |
4207 | */ | |
995b6762 CW |
4208 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4209 | int id, int size, int align) | |
71acb5eb DA |
4210 | { |
4211 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4212 | struct drm_i915_gem_phys_object *phys_obj; | |
4213 | int ret; | |
4214 | ||
4215 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4216 | return 0; | |
4217 | ||
9a298b2a | 4218 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4219 | if (!phys_obj) |
4220 | return -ENOMEM; | |
4221 | ||
4222 | phys_obj->id = id; | |
4223 | ||
6eeefaf3 | 4224 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4225 | if (!phys_obj->handle) { |
4226 | ret = -ENOMEM; | |
4227 | goto kfree_obj; | |
4228 | } | |
4229 | #ifdef CONFIG_X86 | |
4230 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4231 | #endif | |
4232 | ||
4233 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4234 | ||
4235 | return 0; | |
4236 | kfree_obj: | |
9a298b2a | 4237 | kfree(phys_obj); |
71acb5eb DA |
4238 | return ret; |
4239 | } | |
4240 | ||
995b6762 | 4241 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4242 | { |
4243 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4244 | struct drm_i915_gem_phys_object *phys_obj; | |
4245 | ||
4246 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4247 | return; | |
4248 | ||
4249 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4250 | if (phys_obj->cur_obj) { | |
4251 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4252 | } | |
4253 | ||
4254 | #ifdef CONFIG_X86 | |
4255 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4256 | #endif | |
4257 | drm_pci_free(dev, phys_obj->handle); | |
4258 | kfree(phys_obj); | |
4259 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4260 | } | |
4261 | ||
4262 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4263 | { | |
4264 | int i; | |
4265 | ||
260883c8 | 4266 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4267 | i915_gem_free_phys_object(dev, i); |
4268 | } | |
4269 | ||
4270 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4271 | struct drm_i915_gem_object *obj) |
71acb5eb | 4272 | { |
05394f39 | 4273 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4274 | char *vaddr; |
71acb5eb | 4275 | int i; |
71acb5eb DA |
4276 | int page_count; |
4277 | ||
05394f39 | 4278 | if (!obj->phys_obj) |
71acb5eb | 4279 | return; |
05394f39 | 4280 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4281 | |
05394f39 | 4282 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4283 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4284 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4285 | if (!IS_ERR(page)) { |
4286 | char *dst = kmap_atomic(page); | |
4287 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4288 | kunmap_atomic(dst); | |
4289 | ||
4290 | drm_clflush_pages(&page, 1); | |
4291 | ||
4292 | set_page_dirty(page); | |
4293 | mark_page_accessed(page); | |
4294 | page_cache_release(page); | |
4295 | } | |
71acb5eb | 4296 | } |
40ce6575 | 4297 | intel_gtt_chipset_flush(); |
d78b47b9 | 4298 | |
05394f39 CW |
4299 | obj->phys_obj->cur_obj = NULL; |
4300 | obj->phys_obj = NULL; | |
71acb5eb DA |
4301 | } |
4302 | ||
4303 | int | |
4304 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4305 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4306 | int id, |
4307 | int align) | |
71acb5eb | 4308 | { |
05394f39 | 4309 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4310 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4311 | int ret = 0; |
4312 | int page_count; | |
4313 | int i; | |
4314 | ||
4315 | if (id > I915_MAX_PHYS_OBJECT) | |
4316 | return -EINVAL; | |
4317 | ||
05394f39 CW |
4318 | if (obj->phys_obj) { |
4319 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4320 | return 0; |
4321 | i915_gem_detach_phys_object(dev, obj); | |
4322 | } | |
4323 | ||
71acb5eb DA |
4324 | /* create a new object */ |
4325 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4326 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4327 | obj->base.size, align); |
71acb5eb | 4328 | if (ret) { |
05394f39 CW |
4329 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4330 | id, obj->base.size); | |
e5281ccd | 4331 | return ret; |
71acb5eb DA |
4332 | } |
4333 | } | |
4334 | ||
4335 | /* bind to the object */ | |
05394f39 CW |
4336 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4337 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4338 | |
05394f39 | 4339 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4340 | |
4341 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4342 | struct page *page; |
4343 | char *dst, *src; | |
4344 | ||
5949eac4 | 4345 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4346 | if (IS_ERR(page)) |
4347 | return PTR_ERR(page); | |
71acb5eb | 4348 | |
ff75b9bc | 4349 | src = kmap_atomic(page); |
05394f39 | 4350 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4351 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4352 | kunmap_atomic(src); |
71acb5eb | 4353 | |
e5281ccd CW |
4354 | mark_page_accessed(page); |
4355 | page_cache_release(page); | |
4356 | } | |
d78b47b9 | 4357 | |
71acb5eb | 4358 | return 0; |
71acb5eb DA |
4359 | } |
4360 | ||
4361 | static int | |
05394f39 CW |
4362 | i915_gem_phys_pwrite(struct drm_device *dev, |
4363 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4364 | struct drm_i915_gem_pwrite *args, |
4365 | struct drm_file *file_priv) | |
4366 | { | |
05394f39 | 4367 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4368 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4369 | |
b47b30cc CW |
4370 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4371 | unsigned long unwritten; | |
4372 | ||
4373 | /* The physical object once assigned is fixed for the lifetime | |
4374 | * of the obj, so we can safely drop the lock and continue | |
4375 | * to access vaddr. | |
4376 | */ | |
4377 | mutex_unlock(&dev->struct_mutex); | |
4378 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4379 | mutex_lock(&dev->struct_mutex); | |
4380 | if (unwritten) | |
4381 | return -EFAULT; | |
4382 | } | |
71acb5eb | 4383 | |
40ce6575 | 4384 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4385 | return 0; |
4386 | } | |
b962442e | 4387 | |
f787a5f5 | 4388 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4389 | { |
f787a5f5 | 4390 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4391 | |
4392 | /* Clean up our request list when the client is going away, so that | |
4393 | * later retire_requests won't dereference our soon-to-be-gone | |
4394 | * file_priv. | |
4395 | */ | |
1c25595f | 4396 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4397 | while (!list_empty(&file_priv->mm.request_list)) { |
4398 | struct drm_i915_gem_request *request; | |
4399 | ||
4400 | request = list_first_entry(&file_priv->mm.request_list, | |
4401 | struct drm_i915_gem_request, | |
4402 | client_list); | |
4403 | list_del(&request->client_list); | |
4404 | request->file_priv = NULL; | |
4405 | } | |
1c25595f | 4406 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4407 | } |
31169714 | 4408 | |
31169714 | 4409 | static int |
1495f230 | 4410 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4411 | { |
17250b71 CW |
4412 | struct drm_i915_private *dev_priv = |
4413 | container_of(shrinker, | |
4414 | struct drm_i915_private, | |
4415 | mm.inactive_shrinker); | |
4416 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4417 | struct drm_i915_gem_object *obj; |
1495f230 | 4418 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4419 | int cnt; |
4420 | ||
4421 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4422 | return 0; |
31169714 | 4423 | |
6c085a72 CW |
4424 | if (nr_to_scan) { |
4425 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4426 | if (nr_to_scan > 0) | |
4427 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4428 | } |
4429 | ||
17250b71 | 4430 | cnt = 0; |
6c085a72 | 4431 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4432 | if (obj->pages_pin_count == 0) |
4433 | cnt += obj->base.size >> PAGE_SHIFT; | |
6c085a72 | 4434 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
a5570178 | 4435 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4436 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4437 | |
17250b71 | 4438 | mutex_unlock(&dev->struct_mutex); |
6c085a72 | 4439 | return cnt; |
31169714 | 4440 | } |