Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
42 | bool force); | |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
c8725f3d CW |
46 | static void |
47 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
48 | ||
05394f39 CW |
49 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
50 | struct drm_i915_gem_object *obj, | |
71acb5eb | 51 | struct drm_i915_gem_pwrite *args, |
05394f39 | 52 | struct drm_file *file); |
673a394b | 53 | |
61050808 CW |
54 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
55 | struct drm_i915_gem_object *obj); | |
56 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
57 | struct drm_i915_fence_reg *fence, | |
58 | bool enable); | |
59 | ||
ceabbba5 | 60 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 61 | struct shrink_control *sc); |
ceabbba5 | 62 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 63 | struct shrink_control *sc); |
d9973b43 CW |
64 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
65 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 66 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 67 | |
c76ce038 CW |
68 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
69 | enum i915_cache_level level) | |
70 | { | |
71 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
72 | } | |
73 | ||
2c22569b CW |
74 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
75 | { | |
76 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
77 | return true; | |
78 | ||
79 | return obj->pin_display; | |
80 | } | |
81 | ||
61050808 CW |
82 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
83 | { | |
84 | if (obj->tiling_mode) | |
85 | i915_gem_release_mmap(obj); | |
86 | ||
87 | /* As we do not have an associated fence register, we will force | |
88 | * a tiling change if we ever need to acquire one. | |
89 | */ | |
5d82e3e6 | 90 | obj->fence_dirty = false; |
61050808 CW |
91 | obj->fence_reg = I915_FENCE_REG_NONE; |
92 | } | |
93 | ||
73aa808f CW |
94 | /* some bookkeeping */ |
95 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
96 | size_t size) | |
97 | { | |
c20e8355 | 98 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | dev_priv->mm.object_count++; |
100 | dev_priv->mm.object_memory += size; | |
c20e8355 | 101 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
102 | } |
103 | ||
104 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
105 | size_t size) | |
106 | { | |
c20e8355 | 107 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
108 | dev_priv->mm.object_count--; |
109 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 110 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
111 | } |
112 | ||
21dd3734 | 113 | static int |
33196ded | 114 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 115 | { |
30dbf0c0 CW |
116 | int ret; |
117 | ||
7abb690a DV |
118 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
119 | i915_terminally_wedged(error)) | |
1f83fee0 | 120 | if (EXIT_COND) |
30dbf0c0 CW |
121 | return 0; |
122 | ||
0a6759c6 DV |
123 | /* |
124 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
125 | * userspace. If it takes that long something really bad is going on and | |
126 | * we should simply try to bail out and fail as gracefully as possible. | |
127 | */ | |
1f83fee0 DV |
128 | ret = wait_event_interruptible_timeout(error->reset_queue, |
129 | EXIT_COND, | |
130 | 10*HZ); | |
0a6759c6 DV |
131 | if (ret == 0) { |
132 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
133 | return -EIO; | |
134 | } else if (ret < 0) { | |
30dbf0c0 | 135 | return ret; |
0a6759c6 | 136 | } |
1f83fee0 | 137 | #undef EXIT_COND |
30dbf0c0 | 138 | |
21dd3734 | 139 | return 0; |
30dbf0c0 CW |
140 | } |
141 | ||
54cf91dc | 142 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 143 | { |
33196ded | 144 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
145 | int ret; |
146 | ||
33196ded | 147 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
148 | if (ret) |
149 | return ret; | |
150 | ||
151 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
152 | if (ret) | |
153 | return ret; | |
154 | ||
23bc5982 | 155 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
156 | return 0; |
157 | } | |
30dbf0c0 | 158 | |
7d1c4804 | 159 | static inline bool |
05394f39 | 160 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 161 | { |
9843877d | 162 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
163 | } |
164 | ||
79e53945 JB |
165 | int |
166 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 167 | struct drm_file *file) |
79e53945 | 168 | { |
93d18799 | 169 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 170 | struct drm_i915_gem_init *args = data; |
2021746e | 171 | |
7bb6fb8d DV |
172 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
173 | return -ENODEV; | |
174 | ||
2021746e CW |
175 | if (args->gtt_start >= args->gtt_end || |
176 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
177 | return -EINVAL; | |
79e53945 | 178 | |
f534bc0b DV |
179 | /* GEM with user mode setting was never supported on ilk and later. */ |
180 | if (INTEL_INFO(dev)->gen >= 5) | |
181 | return -ENODEV; | |
182 | ||
79e53945 | 183 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
184 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
185 | args->gtt_end); | |
93d18799 | 186 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
187 | mutex_unlock(&dev->struct_mutex); |
188 | ||
2021746e | 189 | return 0; |
673a394b EA |
190 | } |
191 | ||
5a125c3c EA |
192 | int |
193 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 194 | struct drm_file *file) |
5a125c3c | 195 | { |
73aa808f | 196 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 197 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
198 | struct drm_i915_gem_object *obj; |
199 | size_t pinned; | |
5a125c3c | 200 | |
6299f992 | 201 | pinned = 0; |
73aa808f | 202 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 203 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 204 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 205 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 206 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 207 | |
853ba5d2 | 208 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 209 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 210 | |
5a125c3c EA |
211 | return 0; |
212 | } | |
213 | ||
42dcedd4 CW |
214 | void *i915_gem_object_alloc(struct drm_device *dev) |
215 | { | |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 217 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
218 | } |
219 | ||
220 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
221 | { | |
222 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
223 | kmem_cache_free(dev_priv->slab, obj); | |
224 | } | |
225 | ||
ff72145b DA |
226 | static int |
227 | i915_gem_create(struct drm_file *file, | |
228 | struct drm_device *dev, | |
229 | uint64_t size, | |
230 | uint32_t *handle_p) | |
673a394b | 231 | { |
05394f39 | 232 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
233 | int ret; |
234 | u32 handle; | |
673a394b | 235 | |
ff72145b | 236 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
237 | if (size == 0) |
238 | return -EINVAL; | |
673a394b EA |
239 | |
240 | /* Allocate the new object */ | |
ff72145b | 241 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
242 | if (obj == NULL) |
243 | return -ENOMEM; | |
244 | ||
05394f39 | 245 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 246 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
247 | drm_gem_object_unreference_unlocked(&obj->base); |
248 | if (ret) | |
249 | return ret; | |
202f2fef | 250 | |
ff72145b | 251 | *handle_p = handle; |
673a394b EA |
252 | return 0; |
253 | } | |
254 | ||
ff72145b DA |
255 | int |
256 | i915_gem_dumb_create(struct drm_file *file, | |
257 | struct drm_device *dev, | |
258 | struct drm_mode_create_dumb *args) | |
259 | { | |
260 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 261 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
262 | args->size = args->pitch * args->height; |
263 | return i915_gem_create(file, dev, | |
264 | args->size, &args->handle); | |
265 | } | |
266 | ||
ff72145b DA |
267 | /** |
268 | * Creates a new mm object and returns a handle to it. | |
269 | */ | |
270 | int | |
271 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
272 | struct drm_file *file) | |
273 | { | |
274 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 275 | |
ff72145b DA |
276 | return i915_gem_create(file, dev, |
277 | args->size, &args->handle); | |
278 | } | |
279 | ||
8461d226 DV |
280 | static inline int |
281 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
282 | const char *gpu_vaddr, int gpu_offset, | |
283 | int length) | |
284 | { | |
285 | int ret, cpu_offset = 0; | |
286 | ||
287 | while (length > 0) { | |
288 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
289 | int this_length = min(cacheline_end - gpu_offset, length); | |
290 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
291 | ||
292 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
293 | gpu_vaddr + swizzled_gpu_offset, | |
294 | this_length); | |
295 | if (ret) | |
296 | return ret + length; | |
297 | ||
298 | cpu_offset += this_length; | |
299 | gpu_offset += this_length; | |
300 | length -= this_length; | |
301 | } | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
8c59967c | 306 | static inline int |
4f0c7cfb BW |
307 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
308 | const char __user *cpu_vaddr, | |
8c59967c DV |
309 | int length) |
310 | { | |
311 | int ret, cpu_offset = 0; | |
312 | ||
313 | while (length > 0) { | |
314 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
315 | int this_length = min(cacheline_end - gpu_offset, length); | |
316 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
317 | ||
318 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
319 | cpu_vaddr + cpu_offset, | |
320 | this_length); | |
321 | if (ret) | |
322 | return ret + length; | |
323 | ||
324 | cpu_offset += this_length; | |
325 | gpu_offset += this_length; | |
326 | length -= this_length; | |
327 | } | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
4c914c0c BV |
332 | /* |
333 | * Pins the specified object's pages and synchronizes the object with | |
334 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
335 | * flush the object from the CPU cache. | |
336 | */ | |
337 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
338 | int *needs_clflush) | |
339 | { | |
340 | int ret; | |
341 | ||
342 | *needs_clflush = 0; | |
343 | ||
344 | if (!obj->base.filp) | |
345 | return -EINVAL; | |
346 | ||
347 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
348 | /* If we're not in the cpu read domain, set ourself into the gtt | |
349 | * read domain and manually flush cachelines (if required). This | |
350 | * optimizes for the case when the gpu will dirty the data | |
351 | * anyway again before the next pread happens. */ | |
352 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
353 | obj->cache_level); | |
354 | ret = i915_gem_object_wait_rendering(obj, true); | |
355 | if (ret) | |
356 | return ret; | |
c8725f3d CW |
357 | |
358 | i915_gem_object_retire(obj); | |
4c914c0c BV |
359 | } |
360 | ||
361 | ret = i915_gem_object_get_pages(obj); | |
362 | if (ret) | |
363 | return ret; | |
364 | ||
365 | i915_gem_object_pin_pages(obj); | |
366 | ||
367 | return ret; | |
368 | } | |
369 | ||
d174bd64 DV |
370 | /* Per-page copy function for the shmem pread fastpath. |
371 | * Flushes invalid cachelines before reading the target if | |
372 | * needs_clflush is set. */ | |
eb01459f | 373 | static int |
d174bd64 DV |
374 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
375 | char __user *user_data, | |
376 | bool page_do_bit17_swizzling, bool needs_clflush) | |
377 | { | |
378 | char *vaddr; | |
379 | int ret; | |
380 | ||
e7e58eb5 | 381 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
382 | return -EINVAL; |
383 | ||
384 | vaddr = kmap_atomic(page); | |
385 | if (needs_clflush) | |
386 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
387 | page_length); | |
388 | ret = __copy_to_user_inatomic(user_data, | |
389 | vaddr + shmem_page_offset, | |
390 | page_length); | |
391 | kunmap_atomic(vaddr); | |
392 | ||
f60d7f0c | 393 | return ret ? -EFAULT : 0; |
d174bd64 DV |
394 | } |
395 | ||
23c18c71 DV |
396 | static void |
397 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
398 | bool swizzled) | |
399 | { | |
e7e58eb5 | 400 | if (unlikely(swizzled)) { |
23c18c71 DV |
401 | unsigned long start = (unsigned long) addr; |
402 | unsigned long end = (unsigned long) addr + length; | |
403 | ||
404 | /* For swizzling simply ensure that we always flush both | |
405 | * channels. Lame, but simple and it works. Swizzled | |
406 | * pwrite/pread is far from a hotpath - current userspace | |
407 | * doesn't use it at all. */ | |
408 | start = round_down(start, 128); | |
409 | end = round_up(end, 128); | |
410 | ||
411 | drm_clflush_virt_range((void *)start, end - start); | |
412 | } else { | |
413 | drm_clflush_virt_range(addr, length); | |
414 | } | |
415 | ||
416 | } | |
417 | ||
d174bd64 DV |
418 | /* Only difference to the fast-path function is that this can handle bit17 |
419 | * and uses non-atomic copy and kmap functions. */ | |
420 | static int | |
421 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
422 | char __user *user_data, | |
423 | bool page_do_bit17_swizzling, bool needs_clflush) | |
424 | { | |
425 | char *vaddr; | |
426 | int ret; | |
427 | ||
428 | vaddr = kmap(page); | |
429 | if (needs_clflush) | |
23c18c71 DV |
430 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
431 | page_length, | |
432 | page_do_bit17_swizzling); | |
d174bd64 DV |
433 | |
434 | if (page_do_bit17_swizzling) | |
435 | ret = __copy_to_user_swizzled(user_data, | |
436 | vaddr, shmem_page_offset, | |
437 | page_length); | |
438 | else | |
439 | ret = __copy_to_user(user_data, | |
440 | vaddr + shmem_page_offset, | |
441 | page_length); | |
442 | kunmap(page); | |
443 | ||
f60d7f0c | 444 | return ret ? - EFAULT : 0; |
d174bd64 DV |
445 | } |
446 | ||
eb01459f | 447 | static int |
dbf7bff0 DV |
448 | i915_gem_shmem_pread(struct drm_device *dev, |
449 | struct drm_i915_gem_object *obj, | |
450 | struct drm_i915_gem_pread *args, | |
451 | struct drm_file *file) | |
eb01459f | 452 | { |
8461d226 | 453 | char __user *user_data; |
eb01459f | 454 | ssize_t remain; |
8461d226 | 455 | loff_t offset; |
eb2c0c81 | 456 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 457 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 458 | int prefaulted = 0; |
8489731c | 459 | int needs_clflush = 0; |
67d5a50c | 460 | struct sg_page_iter sg_iter; |
eb01459f | 461 | |
2bb4629a | 462 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
463 | remain = args->size; |
464 | ||
8461d226 | 465 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 466 | |
4c914c0c | 467 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
468 | if (ret) |
469 | return ret; | |
470 | ||
8461d226 | 471 | offset = args->offset; |
eb01459f | 472 | |
67d5a50c ID |
473 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
474 | offset >> PAGE_SHIFT) { | |
2db76d7c | 475 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
476 | |
477 | if (remain <= 0) | |
478 | break; | |
479 | ||
eb01459f EA |
480 | /* Operation in this page |
481 | * | |
eb01459f | 482 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
483 | * page_length = bytes to copy for this page |
484 | */ | |
c8cbbb8b | 485 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
486 | page_length = remain; |
487 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
488 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 489 | |
8461d226 DV |
490 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
491 | (page_to_phys(page) & (1 << 17)) != 0; | |
492 | ||
d174bd64 DV |
493 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
494 | user_data, page_do_bit17_swizzling, | |
495 | needs_clflush); | |
496 | if (ret == 0) | |
497 | goto next_page; | |
dbf7bff0 | 498 | |
dbf7bff0 DV |
499 | mutex_unlock(&dev->struct_mutex); |
500 | ||
d330a953 | 501 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 502 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
503 | /* Userspace is tricking us, but we've already clobbered |
504 | * its pages with the prefault and promised to write the | |
505 | * data up to the first fault. Hence ignore any errors | |
506 | * and just continue. */ | |
507 | (void)ret; | |
508 | prefaulted = 1; | |
509 | } | |
eb01459f | 510 | |
d174bd64 DV |
511 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
512 | user_data, page_do_bit17_swizzling, | |
513 | needs_clflush); | |
eb01459f | 514 | |
dbf7bff0 | 515 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 516 | |
f60d7f0c | 517 | if (ret) |
8461d226 | 518 | goto out; |
8461d226 | 519 | |
17793c9a | 520 | next_page: |
eb01459f | 521 | remain -= page_length; |
8461d226 | 522 | user_data += page_length; |
eb01459f EA |
523 | offset += page_length; |
524 | } | |
525 | ||
4f27b75d | 526 | out: |
f60d7f0c CW |
527 | i915_gem_object_unpin_pages(obj); |
528 | ||
eb01459f EA |
529 | return ret; |
530 | } | |
531 | ||
673a394b EA |
532 | /** |
533 | * Reads data from the object referenced by handle. | |
534 | * | |
535 | * On error, the contents of *data are undefined. | |
536 | */ | |
537 | int | |
538 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 539 | struct drm_file *file) |
673a394b EA |
540 | { |
541 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 542 | struct drm_i915_gem_object *obj; |
35b62a89 | 543 | int ret = 0; |
673a394b | 544 | |
51311d0a CW |
545 | if (args->size == 0) |
546 | return 0; | |
547 | ||
548 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 549 | to_user_ptr(args->data_ptr), |
51311d0a CW |
550 | args->size)) |
551 | return -EFAULT; | |
552 | ||
4f27b75d | 553 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 554 | if (ret) |
4f27b75d | 555 | return ret; |
673a394b | 556 | |
05394f39 | 557 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 558 | if (&obj->base == NULL) { |
1d7cfea1 CW |
559 | ret = -ENOENT; |
560 | goto unlock; | |
4f27b75d | 561 | } |
673a394b | 562 | |
7dcd2499 | 563 | /* Bounds check source. */ |
05394f39 CW |
564 | if (args->offset > obj->base.size || |
565 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 566 | ret = -EINVAL; |
35b62a89 | 567 | goto out; |
ce9d419d CW |
568 | } |
569 | ||
1286ff73 DV |
570 | /* prime objects have no backing filp to GEM pread/pwrite |
571 | * pages from. | |
572 | */ | |
573 | if (!obj->base.filp) { | |
574 | ret = -EINVAL; | |
575 | goto out; | |
576 | } | |
577 | ||
db53a302 CW |
578 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
579 | ||
dbf7bff0 | 580 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 581 | |
35b62a89 | 582 | out: |
05394f39 | 583 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 584 | unlock: |
4f27b75d | 585 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 586 | return ret; |
673a394b EA |
587 | } |
588 | ||
0839ccb8 KP |
589 | /* This is the fast write path which cannot handle |
590 | * page faults in the source data | |
9b7530cc | 591 | */ |
0839ccb8 KP |
592 | |
593 | static inline int | |
594 | fast_user_write(struct io_mapping *mapping, | |
595 | loff_t page_base, int page_offset, | |
596 | char __user *user_data, | |
597 | int length) | |
9b7530cc | 598 | { |
4f0c7cfb BW |
599 | void __iomem *vaddr_atomic; |
600 | void *vaddr; | |
0839ccb8 | 601 | unsigned long unwritten; |
9b7530cc | 602 | |
3e4d3af5 | 603 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
604 | /* We can use the cpu mem copy function because this is X86. */ |
605 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
606 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 607 | user_data, length); |
3e4d3af5 | 608 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 609 | return unwritten; |
0839ccb8 KP |
610 | } |
611 | ||
3de09aa3 EA |
612 | /** |
613 | * This is the fast pwrite path, where we copy the data directly from the | |
614 | * user into the GTT, uncached. | |
615 | */ | |
673a394b | 616 | static int |
05394f39 CW |
617 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
618 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 619 | struct drm_i915_gem_pwrite *args, |
05394f39 | 620 | struct drm_file *file) |
673a394b | 621 | { |
3e31c6c0 | 622 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 623 | ssize_t remain; |
0839ccb8 | 624 | loff_t offset, page_base; |
673a394b | 625 | char __user *user_data; |
935aaa69 DV |
626 | int page_offset, page_length, ret; |
627 | ||
1ec9e26d | 628 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
629 | if (ret) |
630 | goto out; | |
631 | ||
632 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
633 | if (ret) | |
634 | goto out_unpin; | |
635 | ||
636 | ret = i915_gem_object_put_fence(obj); | |
637 | if (ret) | |
638 | goto out_unpin; | |
673a394b | 639 | |
2bb4629a | 640 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 641 | remain = args->size; |
673a394b | 642 | |
f343c5f6 | 643 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
644 | |
645 | while (remain > 0) { | |
646 | /* Operation in this page | |
647 | * | |
0839ccb8 KP |
648 | * page_base = page offset within aperture |
649 | * page_offset = offset within page | |
650 | * page_length = bytes to copy for this page | |
673a394b | 651 | */ |
c8cbbb8b CW |
652 | page_base = offset & PAGE_MASK; |
653 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
654 | page_length = remain; |
655 | if ((page_offset + remain) > PAGE_SIZE) | |
656 | page_length = PAGE_SIZE - page_offset; | |
657 | ||
0839ccb8 | 658 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
659 | * source page isn't available. Return the error and we'll |
660 | * retry in the slow path. | |
0839ccb8 | 661 | */ |
5d4545ae | 662 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
663 | page_offset, user_data, page_length)) { |
664 | ret = -EFAULT; | |
665 | goto out_unpin; | |
666 | } | |
673a394b | 667 | |
0839ccb8 KP |
668 | remain -= page_length; |
669 | user_data += page_length; | |
670 | offset += page_length; | |
673a394b | 671 | } |
673a394b | 672 | |
935aaa69 | 673 | out_unpin: |
d7f46fc4 | 674 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 675 | out: |
3de09aa3 | 676 | return ret; |
673a394b EA |
677 | } |
678 | ||
d174bd64 DV |
679 | /* Per-page copy function for the shmem pwrite fastpath. |
680 | * Flushes invalid cachelines before writing to the target if | |
681 | * needs_clflush_before is set and flushes out any written cachelines after | |
682 | * writing if needs_clflush is set. */ | |
3043c60c | 683 | static int |
d174bd64 DV |
684 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
685 | char __user *user_data, | |
686 | bool page_do_bit17_swizzling, | |
687 | bool needs_clflush_before, | |
688 | bool needs_clflush_after) | |
673a394b | 689 | { |
d174bd64 | 690 | char *vaddr; |
673a394b | 691 | int ret; |
3de09aa3 | 692 | |
e7e58eb5 | 693 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 694 | return -EINVAL; |
3de09aa3 | 695 | |
d174bd64 DV |
696 | vaddr = kmap_atomic(page); |
697 | if (needs_clflush_before) | |
698 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
699 | page_length); | |
c2831a94 CW |
700 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
701 | user_data, page_length); | |
d174bd64 DV |
702 | if (needs_clflush_after) |
703 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
704 | page_length); | |
705 | kunmap_atomic(vaddr); | |
3de09aa3 | 706 | |
755d2218 | 707 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
708 | } |
709 | ||
d174bd64 DV |
710 | /* Only difference to the fast-path function is that this can handle bit17 |
711 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 712 | static int |
d174bd64 DV |
713 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
714 | char __user *user_data, | |
715 | bool page_do_bit17_swizzling, | |
716 | bool needs_clflush_before, | |
717 | bool needs_clflush_after) | |
673a394b | 718 | { |
d174bd64 DV |
719 | char *vaddr; |
720 | int ret; | |
e5281ccd | 721 | |
d174bd64 | 722 | vaddr = kmap(page); |
e7e58eb5 | 723 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
724 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
725 | page_length, | |
726 | page_do_bit17_swizzling); | |
d174bd64 DV |
727 | if (page_do_bit17_swizzling) |
728 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
729 | user_data, |
730 | page_length); | |
d174bd64 DV |
731 | else |
732 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
733 | user_data, | |
734 | page_length); | |
735 | if (needs_clflush_after) | |
23c18c71 DV |
736 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
737 | page_length, | |
738 | page_do_bit17_swizzling); | |
d174bd64 | 739 | kunmap(page); |
40123c1f | 740 | |
755d2218 | 741 | return ret ? -EFAULT : 0; |
40123c1f EA |
742 | } |
743 | ||
40123c1f | 744 | static int |
e244a443 DV |
745 | i915_gem_shmem_pwrite(struct drm_device *dev, |
746 | struct drm_i915_gem_object *obj, | |
747 | struct drm_i915_gem_pwrite *args, | |
748 | struct drm_file *file) | |
40123c1f | 749 | { |
40123c1f | 750 | ssize_t remain; |
8c59967c DV |
751 | loff_t offset; |
752 | char __user *user_data; | |
eb2c0c81 | 753 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 754 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 755 | int hit_slowpath = 0; |
58642885 DV |
756 | int needs_clflush_after = 0; |
757 | int needs_clflush_before = 0; | |
67d5a50c | 758 | struct sg_page_iter sg_iter; |
40123c1f | 759 | |
2bb4629a | 760 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
761 | remain = args->size; |
762 | ||
8c59967c | 763 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 764 | |
58642885 DV |
765 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
766 | /* If we're not in the cpu write domain, set ourself into the gtt | |
767 | * write domain and manually flush cachelines (if required). This | |
768 | * optimizes for the case when the gpu will use the data | |
769 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 770 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
771 | ret = i915_gem_object_wait_rendering(obj, false); |
772 | if (ret) | |
773 | return ret; | |
c8725f3d CW |
774 | |
775 | i915_gem_object_retire(obj); | |
58642885 | 776 | } |
c76ce038 CW |
777 | /* Same trick applies to invalidate partially written cachelines read |
778 | * before writing. */ | |
779 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
780 | needs_clflush_before = | |
781 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 782 | |
755d2218 CW |
783 | ret = i915_gem_object_get_pages(obj); |
784 | if (ret) | |
785 | return ret; | |
786 | ||
787 | i915_gem_object_pin_pages(obj); | |
788 | ||
673a394b | 789 | offset = args->offset; |
05394f39 | 790 | obj->dirty = 1; |
673a394b | 791 | |
67d5a50c ID |
792 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
793 | offset >> PAGE_SHIFT) { | |
2db76d7c | 794 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 795 | int partial_cacheline_write; |
e5281ccd | 796 | |
9da3da66 CW |
797 | if (remain <= 0) |
798 | break; | |
799 | ||
40123c1f EA |
800 | /* Operation in this page |
801 | * | |
40123c1f | 802 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
803 | * page_length = bytes to copy for this page |
804 | */ | |
c8cbbb8b | 805 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
806 | |
807 | page_length = remain; | |
808 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
809 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 810 | |
58642885 DV |
811 | /* If we don't overwrite a cacheline completely we need to be |
812 | * careful to have up-to-date data by first clflushing. Don't | |
813 | * overcomplicate things and flush the entire patch. */ | |
814 | partial_cacheline_write = needs_clflush_before && | |
815 | ((shmem_page_offset | page_length) | |
816 | & (boot_cpu_data.x86_clflush_size - 1)); | |
817 | ||
8c59967c DV |
818 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
819 | (page_to_phys(page) & (1 << 17)) != 0; | |
820 | ||
d174bd64 DV |
821 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
822 | user_data, page_do_bit17_swizzling, | |
823 | partial_cacheline_write, | |
824 | needs_clflush_after); | |
825 | if (ret == 0) | |
826 | goto next_page; | |
e244a443 DV |
827 | |
828 | hit_slowpath = 1; | |
e244a443 | 829 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
830 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
831 | user_data, page_do_bit17_swizzling, | |
832 | partial_cacheline_write, | |
833 | needs_clflush_after); | |
40123c1f | 834 | |
e244a443 | 835 | mutex_lock(&dev->struct_mutex); |
755d2218 | 836 | |
755d2218 | 837 | if (ret) |
8c59967c | 838 | goto out; |
8c59967c | 839 | |
17793c9a | 840 | next_page: |
40123c1f | 841 | remain -= page_length; |
8c59967c | 842 | user_data += page_length; |
40123c1f | 843 | offset += page_length; |
673a394b EA |
844 | } |
845 | ||
fbd5a26d | 846 | out: |
755d2218 CW |
847 | i915_gem_object_unpin_pages(obj); |
848 | ||
e244a443 | 849 | if (hit_slowpath) { |
8dcf015e DV |
850 | /* |
851 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
852 | * cachelines in-line while writing and the object moved | |
853 | * out of the cpu write domain while we've dropped the lock. | |
854 | */ | |
855 | if (!needs_clflush_after && | |
856 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
857 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
858 | i915_gem_chipset_flush(dev); | |
e244a443 | 859 | } |
8c59967c | 860 | } |
673a394b | 861 | |
58642885 | 862 | if (needs_clflush_after) |
e76e9aeb | 863 | i915_gem_chipset_flush(dev); |
58642885 | 864 | |
40123c1f | 865 | return ret; |
673a394b EA |
866 | } |
867 | ||
868 | /** | |
869 | * Writes data to the object referenced by handle. | |
870 | * | |
871 | * On error, the contents of the buffer that were to be modified are undefined. | |
872 | */ | |
873 | int | |
874 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 875 | struct drm_file *file) |
673a394b EA |
876 | { |
877 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 878 | struct drm_i915_gem_object *obj; |
51311d0a CW |
879 | int ret; |
880 | ||
881 | if (args->size == 0) | |
882 | return 0; | |
883 | ||
884 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 885 | to_user_ptr(args->data_ptr), |
51311d0a CW |
886 | args->size)) |
887 | return -EFAULT; | |
888 | ||
d330a953 | 889 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
890 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
891 | args->size); | |
892 | if (ret) | |
893 | return -EFAULT; | |
894 | } | |
673a394b | 895 | |
fbd5a26d | 896 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 897 | if (ret) |
fbd5a26d | 898 | return ret; |
1d7cfea1 | 899 | |
05394f39 | 900 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 901 | if (&obj->base == NULL) { |
1d7cfea1 CW |
902 | ret = -ENOENT; |
903 | goto unlock; | |
fbd5a26d | 904 | } |
673a394b | 905 | |
7dcd2499 | 906 | /* Bounds check destination. */ |
05394f39 CW |
907 | if (args->offset > obj->base.size || |
908 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 909 | ret = -EINVAL; |
35b62a89 | 910 | goto out; |
ce9d419d CW |
911 | } |
912 | ||
1286ff73 DV |
913 | /* prime objects have no backing filp to GEM pread/pwrite |
914 | * pages from. | |
915 | */ | |
916 | if (!obj->base.filp) { | |
917 | ret = -EINVAL; | |
918 | goto out; | |
919 | } | |
920 | ||
db53a302 CW |
921 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
922 | ||
935aaa69 | 923 | ret = -EFAULT; |
673a394b EA |
924 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
925 | * it would end up going through the fenced access, and we'll get | |
926 | * different detiling behavior between reading and writing. | |
927 | * pread/pwrite currently are reading and writing from the CPU | |
928 | * perspective, requiring manual detiling by the client. | |
929 | */ | |
5c0480f2 | 930 | if (obj->phys_obj) { |
fbd5a26d | 931 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
932 | goto out; |
933 | } | |
934 | ||
2c22569b CW |
935 | if (obj->tiling_mode == I915_TILING_NONE && |
936 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
937 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 938 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
939 | /* Note that the gtt paths might fail with non-page-backed user |
940 | * pointers (e.g. gtt mappings when moving data between | |
941 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 942 | } |
673a394b | 943 | |
86a1ee26 | 944 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 945 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 946 | |
35b62a89 | 947 | out: |
05394f39 | 948 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 949 | unlock: |
fbd5a26d | 950 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
951 | return ret; |
952 | } | |
953 | ||
b361237b | 954 | int |
33196ded | 955 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
956 | bool interruptible) |
957 | { | |
1f83fee0 | 958 | if (i915_reset_in_progress(error)) { |
b361237b CW |
959 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
960 | * -EIO unconditionally for these. */ | |
961 | if (!interruptible) | |
962 | return -EIO; | |
963 | ||
1f83fee0 DV |
964 | /* Recovery complete, but the reset failed ... */ |
965 | if (i915_terminally_wedged(error)) | |
b361237b CW |
966 | return -EIO; |
967 | ||
968 | return -EAGAIN; | |
969 | } | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
974 | /* | |
975 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
976 | * equal. | |
977 | */ | |
978 | static int | |
979 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
980 | { | |
981 | int ret; | |
982 | ||
983 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
984 | ||
985 | ret = 0; | |
1823521d | 986 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 987 | ret = i915_add_request(ring, NULL); |
b361237b CW |
988 | |
989 | return ret; | |
990 | } | |
991 | ||
094f9a54 CW |
992 | static void fake_irq(unsigned long data) |
993 | { | |
994 | wake_up_process((struct task_struct *)data); | |
995 | } | |
996 | ||
997 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
998 | struct intel_ring_buffer *ring) | |
999 | { | |
1000 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1001 | } | |
1002 | ||
b29c19b6 CW |
1003 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1004 | { | |
1005 | if (file_priv == NULL) | |
1006 | return true; | |
1007 | ||
1008 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1009 | } | |
1010 | ||
b361237b CW |
1011 | /** |
1012 | * __wait_seqno - wait until execution of seqno has finished | |
1013 | * @ring: the ring expected to report seqno | |
1014 | * @seqno: duh! | |
f69061be | 1015 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
1016 | * @interruptible: do an interruptible wait (normally yes) |
1017 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1018 | * | |
f69061be DV |
1019 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1020 | * values have been read by the caller in an smp safe manner. Where read-side | |
1021 | * locks are involved, it is sufficient to read the reset_counter before | |
1022 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1023 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1024 | * inserted. | |
1025 | * | |
b361237b CW |
1026 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1027 | * errno with remaining time filled in timeout argument. | |
1028 | */ | |
1029 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 1030 | unsigned reset_counter, |
b29c19b6 CW |
1031 | bool interruptible, |
1032 | struct timespec *timeout, | |
1033 | struct drm_i915_file_private *file_priv) | |
b361237b | 1034 | { |
3d13ef2e | 1035 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1036 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1037 | const bool irq_test_in_progress = |
1038 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 CW |
1039 | struct timespec before, now; |
1040 | DEFINE_WAIT(wait); | |
47e9766d | 1041 | unsigned long timeout_expire; |
b361237b CW |
1042 | int ret; |
1043 | ||
5d584b2e | 1044 | WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n"); |
c67a470b | 1045 | |
b361237b CW |
1046 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1047 | return 0; | |
1048 | ||
47e9766d | 1049 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
b361237b | 1050 | |
3d13ef2e | 1051 | if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1052 | gen6_rps_boost(dev_priv); |
1053 | if (file_priv) | |
1054 | mod_delayed_work(dev_priv->wq, | |
1055 | &file_priv->mm.idle_work, | |
1056 | msecs_to_jiffies(100)); | |
1057 | } | |
1058 | ||
168c3f21 | 1059 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1060 | return -ENODEV; |
1061 | ||
094f9a54 CW |
1062 | /* Record current time in case interrupted by signal, or wedged */ |
1063 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1064 | getrawmonotonic(&before); |
094f9a54 CW |
1065 | for (;;) { |
1066 | struct timer_list timer; | |
b361237b | 1067 | |
094f9a54 CW |
1068 | prepare_to_wait(&ring->irq_queue, &wait, |
1069 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1070 | |
f69061be DV |
1071 | /* We need to check whether any gpu reset happened in between |
1072 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1073 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1074 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1075 | * is truely gone. */ | |
1076 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1077 | if (ret == 0) | |
1078 | ret = -EAGAIN; | |
1079 | break; | |
1080 | } | |
f69061be | 1081 | |
094f9a54 CW |
1082 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1083 | ret = 0; | |
1084 | break; | |
1085 | } | |
b361237b | 1086 | |
094f9a54 CW |
1087 | if (interruptible && signal_pending(current)) { |
1088 | ret = -ERESTARTSYS; | |
1089 | break; | |
1090 | } | |
1091 | ||
47e9766d | 1092 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1093 | ret = -ETIME; |
1094 | break; | |
1095 | } | |
1096 | ||
1097 | timer.function = NULL; | |
1098 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1099 | unsigned long expire; |
1100 | ||
094f9a54 | 1101 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1102 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1103 | mod_timer(&timer, expire); |
1104 | } | |
1105 | ||
5035c275 | 1106 | io_schedule(); |
094f9a54 | 1107 | |
094f9a54 CW |
1108 | if (timer.function) { |
1109 | del_singleshot_timer_sync(&timer); | |
1110 | destroy_timer_on_stack(&timer); | |
1111 | } | |
1112 | } | |
b361237b | 1113 | getrawmonotonic(&now); |
094f9a54 | 1114 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b | 1115 | |
168c3f21 MK |
1116 | if (!irq_test_in_progress) |
1117 | ring->irq_put(ring); | |
094f9a54 CW |
1118 | |
1119 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1120 | |
1121 | if (timeout) { | |
1122 | struct timespec sleep_time = timespec_sub(now, before); | |
1123 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1124 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1125 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1126 | } |
1127 | ||
094f9a54 | 1128 | return ret; |
b361237b CW |
1129 | } |
1130 | ||
1131 | /** | |
1132 | * Waits for a sequence number to be signaled, and cleans up the | |
1133 | * request and object lists appropriately for that event. | |
1134 | */ | |
1135 | int | |
1136 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1137 | { | |
1138 | struct drm_device *dev = ring->dev; | |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1140 | bool interruptible = dev_priv->mm.interruptible; | |
1141 | int ret; | |
1142 | ||
1143 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1144 | BUG_ON(seqno == 0); | |
1145 | ||
33196ded | 1146 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1147 | if (ret) |
1148 | return ret; | |
1149 | ||
1150 | ret = i915_gem_check_olr(ring, seqno); | |
1151 | if (ret) | |
1152 | return ret; | |
1153 | ||
f69061be DV |
1154 | return __wait_seqno(ring, seqno, |
1155 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1156 | interruptible, NULL, NULL); |
b361237b CW |
1157 | } |
1158 | ||
d26e3af8 CW |
1159 | static int |
1160 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1161 | struct intel_ring_buffer *ring) | |
1162 | { | |
c8725f3d CW |
1163 | if (!obj->active) |
1164 | return 0; | |
d26e3af8 CW |
1165 | |
1166 | /* Manually manage the write flush as we may have not yet | |
1167 | * retired the buffer. | |
1168 | * | |
1169 | * Note that the last_write_seqno is always the earlier of | |
1170 | * the two (read/write) seqno, so if we haved successfully waited, | |
1171 | * we know we have passed the last write. | |
1172 | */ | |
1173 | obj->last_write_seqno = 0; | |
d26e3af8 CW |
1174 | |
1175 | return 0; | |
1176 | } | |
1177 | ||
b361237b CW |
1178 | /** |
1179 | * Ensures that all rendering to the object has completed and the object is | |
1180 | * safe to unbind from the GTT or access from the CPU. | |
1181 | */ | |
1182 | static __must_check int | |
1183 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1184 | bool readonly) | |
1185 | { | |
1186 | struct intel_ring_buffer *ring = obj->ring; | |
1187 | u32 seqno; | |
1188 | int ret; | |
1189 | ||
1190 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1191 | if (seqno == 0) | |
1192 | return 0; | |
1193 | ||
1194 | ret = i915_wait_seqno(ring, seqno); | |
1195 | if (ret) | |
1196 | return ret; | |
1197 | ||
d26e3af8 | 1198 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1199 | } |
1200 | ||
3236f57a CW |
1201 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1202 | * as the object state may change during this call. | |
1203 | */ | |
1204 | static __must_check int | |
1205 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1206 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1207 | bool readonly) |
1208 | { | |
1209 | struct drm_device *dev = obj->base.dev; | |
1210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1211 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1212 | unsigned reset_counter; |
3236f57a CW |
1213 | u32 seqno; |
1214 | int ret; | |
1215 | ||
1216 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1217 | BUG_ON(!dev_priv->mm.interruptible); | |
1218 | ||
1219 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1220 | if (seqno == 0) | |
1221 | return 0; | |
1222 | ||
33196ded | 1223 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1224 | if (ret) |
1225 | return ret; | |
1226 | ||
1227 | ret = i915_gem_check_olr(ring, seqno); | |
1228 | if (ret) | |
1229 | return ret; | |
1230 | ||
f69061be | 1231 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1232 | mutex_unlock(&dev->struct_mutex); |
6e4930f6 | 1233 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
3236f57a | 1234 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1235 | if (ret) |
1236 | return ret; | |
3236f57a | 1237 | |
d26e3af8 | 1238 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1239 | } |
1240 | ||
673a394b | 1241 | /** |
2ef7eeaa EA |
1242 | * Called when user space prepares to use an object with the CPU, either |
1243 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1244 | */ |
1245 | int | |
1246 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1247 | struct drm_file *file) |
673a394b EA |
1248 | { |
1249 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1250 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1251 | uint32_t read_domains = args->read_domains; |
1252 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1253 | int ret; |
1254 | ||
2ef7eeaa | 1255 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1256 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1257 | return -EINVAL; |
1258 | ||
21d509e3 | 1259 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1260 | return -EINVAL; |
1261 | ||
1262 | /* Having something in the write domain implies it's in the read | |
1263 | * domain, and only that read domain. Enforce that in the request. | |
1264 | */ | |
1265 | if (write_domain != 0 && read_domains != write_domain) | |
1266 | return -EINVAL; | |
1267 | ||
76c1dec1 | 1268 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1269 | if (ret) |
76c1dec1 | 1270 | return ret; |
1d7cfea1 | 1271 | |
05394f39 | 1272 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1273 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1274 | ret = -ENOENT; |
1275 | goto unlock; | |
76c1dec1 | 1276 | } |
673a394b | 1277 | |
3236f57a CW |
1278 | /* Try to flush the object off the GPU without holding the lock. |
1279 | * We will repeat the flush holding the lock in the normal manner | |
1280 | * to catch cases where we are gazumped. | |
1281 | */ | |
6e4930f6 CW |
1282 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1283 | file->driver_priv, | |
1284 | !write_domain); | |
3236f57a CW |
1285 | if (ret) |
1286 | goto unref; | |
1287 | ||
2ef7eeaa EA |
1288 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1289 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1290 | |
1291 | /* Silently promote "you're not bound, there was nothing to do" | |
1292 | * to success, since the client was just asking us to | |
1293 | * make sure everything was done. | |
1294 | */ | |
1295 | if (ret == -EINVAL) | |
1296 | ret = 0; | |
2ef7eeaa | 1297 | } else { |
e47c68e9 | 1298 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1299 | } |
1300 | ||
3236f57a | 1301 | unref: |
05394f39 | 1302 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1303 | unlock: |
673a394b EA |
1304 | mutex_unlock(&dev->struct_mutex); |
1305 | return ret; | |
1306 | } | |
1307 | ||
1308 | /** | |
1309 | * Called when user space has done writes to this buffer | |
1310 | */ | |
1311 | int | |
1312 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1313 | struct drm_file *file) |
673a394b EA |
1314 | { |
1315 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1316 | struct drm_i915_gem_object *obj; |
673a394b EA |
1317 | int ret = 0; |
1318 | ||
76c1dec1 | 1319 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1320 | if (ret) |
76c1dec1 | 1321 | return ret; |
1d7cfea1 | 1322 | |
05394f39 | 1323 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1324 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1325 | ret = -ENOENT; |
1326 | goto unlock; | |
673a394b EA |
1327 | } |
1328 | ||
673a394b | 1329 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1330 | if (obj->pin_display) |
1331 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1332 | |
05394f39 | 1333 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1334 | unlock: |
673a394b EA |
1335 | mutex_unlock(&dev->struct_mutex); |
1336 | return ret; | |
1337 | } | |
1338 | ||
1339 | /** | |
1340 | * Maps the contents of an object, returning the address it is mapped | |
1341 | * into. | |
1342 | * | |
1343 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1344 | * imply a ref on the object itself. | |
1345 | */ | |
1346 | int | |
1347 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1348 | struct drm_file *file) |
673a394b EA |
1349 | { |
1350 | struct drm_i915_gem_mmap *args = data; | |
1351 | struct drm_gem_object *obj; | |
673a394b EA |
1352 | unsigned long addr; |
1353 | ||
05394f39 | 1354 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1355 | if (obj == NULL) |
bf79cb91 | 1356 | return -ENOENT; |
673a394b | 1357 | |
1286ff73 DV |
1358 | /* prime objects have no backing filp to GEM mmap |
1359 | * pages from. | |
1360 | */ | |
1361 | if (!obj->filp) { | |
1362 | drm_gem_object_unreference_unlocked(obj); | |
1363 | return -EINVAL; | |
1364 | } | |
1365 | ||
6be5ceb0 | 1366 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1367 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1368 | args->offset); | |
bc9025bd | 1369 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1370 | if (IS_ERR((void *)addr)) |
1371 | return addr; | |
1372 | ||
1373 | args->addr_ptr = (uint64_t) addr; | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
de151cf6 JB |
1378 | /** |
1379 | * i915_gem_fault - fault a page into the GTT | |
1380 | * vma: VMA in question | |
1381 | * vmf: fault info | |
1382 | * | |
1383 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1384 | * from userspace. The fault handler takes care of binding the object to | |
1385 | * the GTT (if needed), allocating and programming a fence register (again, | |
1386 | * only if needed based on whether the old reg is still valid or the object | |
1387 | * is tiled) and inserting a new PTE into the faulting process. | |
1388 | * | |
1389 | * Note that the faulting process may involve evicting existing objects | |
1390 | * from the GTT and/or fence registers to make room. So performance may | |
1391 | * suffer if the GTT working set is large or there are few fence registers | |
1392 | * left. | |
1393 | */ | |
1394 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1395 | { | |
05394f39 CW |
1396 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1397 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1398 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1399 | pgoff_t page_offset; |
1400 | unsigned long pfn; | |
1401 | int ret = 0; | |
0f973f27 | 1402 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1403 | |
f65c9168 PZ |
1404 | intel_runtime_pm_get(dev_priv); |
1405 | ||
de151cf6 JB |
1406 | /* We don't use vmf->pgoff since that has the fake offset */ |
1407 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1408 | PAGE_SHIFT; | |
1409 | ||
d9bc7e9f CW |
1410 | ret = i915_mutex_lock_interruptible(dev); |
1411 | if (ret) | |
1412 | goto out; | |
a00b10c3 | 1413 | |
db53a302 CW |
1414 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1415 | ||
6e4930f6 CW |
1416 | /* Try to flush the object off the GPU first without holding the lock. |
1417 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1418 | * repeat the flush holding the lock in the normal manner to catch cases | |
1419 | * where we are gazumped. | |
1420 | */ | |
1421 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1422 | if (ret) | |
1423 | goto unlock; | |
1424 | ||
eb119bd6 CW |
1425 | /* Access to snoopable pages through the GTT is incoherent. */ |
1426 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1427 | ret = -EINVAL; | |
1428 | goto unlock; | |
1429 | } | |
1430 | ||
d9bc7e9f | 1431 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1432 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1433 | if (ret) |
1434 | goto unlock; | |
4a684a41 | 1435 | |
c9839303 CW |
1436 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1437 | if (ret) | |
1438 | goto unpin; | |
74898d7e | 1439 | |
06d98131 | 1440 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1441 | if (ret) |
c9839303 | 1442 | goto unpin; |
7d1c4804 | 1443 | |
6299f992 CW |
1444 | obj->fault_mappable = true; |
1445 | ||
f343c5f6 BW |
1446 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1447 | pfn >>= PAGE_SHIFT; | |
1448 | pfn += page_offset; | |
de151cf6 JB |
1449 | |
1450 | /* Finally, remap it using the new GTT offset */ | |
1451 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 | 1452 | unpin: |
d7f46fc4 | 1453 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1454 | unlock: |
de151cf6 | 1455 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1456 | out: |
de151cf6 | 1457 | switch (ret) { |
d9bc7e9f | 1458 | case -EIO: |
a9340cca DV |
1459 | /* If this -EIO is due to a gpu hang, give the reset code a |
1460 | * chance to clean up the mess. Otherwise return the proper | |
1461 | * SIGBUS. */ | |
f65c9168 PZ |
1462 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
1463 | ret = VM_FAULT_SIGBUS; | |
1464 | break; | |
1465 | } | |
045e769a | 1466 | case -EAGAIN: |
571c608d DV |
1467 | /* |
1468 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1469 | * handler to reset everything when re-faulting in | |
1470 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1471 | */ |
c715089f CW |
1472 | case 0: |
1473 | case -ERESTARTSYS: | |
bed636ab | 1474 | case -EINTR: |
e79e0fe3 DR |
1475 | case -EBUSY: |
1476 | /* | |
1477 | * EBUSY is ok: this just means that another thread | |
1478 | * already did the job. | |
1479 | */ | |
f65c9168 PZ |
1480 | ret = VM_FAULT_NOPAGE; |
1481 | break; | |
de151cf6 | 1482 | case -ENOMEM: |
f65c9168 PZ |
1483 | ret = VM_FAULT_OOM; |
1484 | break; | |
a7c2e1aa | 1485 | case -ENOSPC: |
45d67817 | 1486 | case -EFAULT: |
f65c9168 PZ |
1487 | ret = VM_FAULT_SIGBUS; |
1488 | break; | |
de151cf6 | 1489 | default: |
a7c2e1aa | 1490 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1491 | ret = VM_FAULT_SIGBUS; |
1492 | break; | |
de151cf6 | 1493 | } |
f65c9168 PZ |
1494 | |
1495 | intel_runtime_pm_put(dev_priv); | |
1496 | return ret; | |
de151cf6 JB |
1497 | } |
1498 | ||
48018a57 PZ |
1499 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
1500 | { | |
1501 | struct i915_vma *vma; | |
1502 | ||
1503 | /* | |
1504 | * Only the global gtt is relevant for gtt memory mappings, so restrict | |
1505 | * list traversal to objects bound into the global address space. Note | |
1506 | * that the active list should be empty, but better safe than sorry. | |
1507 | */ | |
1508 | WARN_ON(!list_empty(&dev_priv->gtt.base.active_list)); | |
1509 | list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list) | |
1510 | i915_gem_release_mmap(vma->obj); | |
1511 | list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list) | |
1512 | i915_gem_release_mmap(vma->obj); | |
1513 | } | |
1514 | ||
901782b2 CW |
1515 | /** |
1516 | * i915_gem_release_mmap - remove physical page mappings | |
1517 | * @obj: obj in question | |
1518 | * | |
af901ca1 | 1519 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1520 | * relinquish ownership of the pages back to the system. |
1521 | * | |
1522 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1523 | * object through the GTT and then lose the fence register due to | |
1524 | * resource pressure. Similarly if the object has been moved out of the | |
1525 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1526 | * mapping will then trigger a page fault on the next user access, allowing | |
1527 | * fixup by i915_gem_fault(). | |
1528 | */ | |
d05ca301 | 1529 | void |
05394f39 | 1530 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1531 | { |
6299f992 CW |
1532 | if (!obj->fault_mappable) |
1533 | return; | |
901782b2 | 1534 | |
6796cb16 DH |
1535 | drm_vma_node_unmap(&obj->base.vma_node, |
1536 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1537 | obj->fault_mappable = false; |
901782b2 CW |
1538 | } |
1539 | ||
0fa87796 | 1540 | uint32_t |
e28f8711 | 1541 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1542 | { |
e28f8711 | 1543 | uint32_t gtt_size; |
92b88aeb CW |
1544 | |
1545 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1546 | tiling_mode == I915_TILING_NONE) |
1547 | return size; | |
92b88aeb CW |
1548 | |
1549 | /* Previous chips need a power-of-two fence region when tiling */ | |
1550 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1551 | gtt_size = 1024*1024; |
92b88aeb | 1552 | else |
e28f8711 | 1553 | gtt_size = 512*1024; |
92b88aeb | 1554 | |
e28f8711 CW |
1555 | while (gtt_size < size) |
1556 | gtt_size <<= 1; | |
92b88aeb | 1557 | |
e28f8711 | 1558 | return gtt_size; |
92b88aeb CW |
1559 | } |
1560 | ||
de151cf6 JB |
1561 | /** |
1562 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1563 | * @obj: object to check | |
1564 | * | |
1565 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1566 | * potential fence register mapping. |
de151cf6 | 1567 | */ |
d865110c ID |
1568 | uint32_t |
1569 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1570 | int tiling_mode, bool fenced) | |
de151cf6 | 1571 | { |
de151cf6 JB |
1572 | /* |
1573 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1574 | * if a fence register is needed for the object. | |
1575 | */ | |
d865110c | 1576 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1577 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1578 | return 4096; |
1579 | ||
a00b10c3 CW |
1580 | /* |
1581 | * Previous chips need to be aligned to the size of the smallest | |
1582 | * fence register that can contain the object. | |
1583 | */ | |
e28f8711 | 1584 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1585 | } |
1586 | ||
d8cb5086 CW |
1587 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1588 | { | |
1589 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1590 | int ret; | |
1591 | ||
0de23977 | 1592 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1593 | return 0; |
1594 | ||
da494d7c DV |
1595 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1596 | ||
d8cb5086 CW |
1597 | ret = drm_gem_create_mmap_offset(&obj->base); |
1598 | if (ret != -ENOSPC) | |
da494d7c | 1599 | goto out; |
d8cb5086 CW |
1600 | |
1601 | /* Badly fragmented mmap space? The only way we can recover | |
1602 | * space is by destroying unwanted objects. We can't randomly release | |
1603 | * mmap_offsets as userspace expects them to be persistent for the | |
1604 | * lifetime of the objects. The closest we can is to release the | |
1605 | * offsets on purgeable objects by truncating it and marking it purged, | |
1606 | * which prevents userspace from ever using that object again. | |
1607 | */ | |
1608 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1609 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1610 | if (ret != -ENOSPC) | |
da494d7c | 1611 | goto out; |
d8cb5086 CW |
1612 | |
1613 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1614 | ret = drm_gem_create_mmap_offset(&obj->base); |
1615 | out: | |
1616 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1617 | ||
1618 | return ret; | |
d8cb5086 CW |
1619 | } |
1620 | ||
1621 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1622 | { | |
d8cb5086 CW |
1623 | drm_gem_free_mmap_offset(&obj->base); |
1624 | } | |
1625 | ||
de151cf6 | 1626 | int |
ff72145b DA |
1627 | i915_gem_mmap_gtt(struct drm_file *file, |
1628 | struct drm_device *dev, | |
1629 | uint32_t handle, | |
1630 | uint64_t *offset) | |
de151cf6 | 1631 | { |
da761a6e | 1632 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1633 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1634 | int ret; |
1635 | ||
76c1dec1 | 1636 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1637 | if (ret) |
76c1dec1 | 1638 | return ret; |
de151cf6 | 1639 | |
ff72145b | 1640 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1641 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1642 | ret = -ENOENT; |
1643 | goto unlock; | |
1644 | } | |
de151cf6 | 1645 | |
5d4545ae | 1646 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1647 | ret = -E2BIG; |
ff56b0bc | 1648 | goto out; |
da761a6e CW |
1649 | } |
1650 | ||
05394f39 | 1651 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1652 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1653 | ret = -EFAULT; |
1d7cfea1 | 1654 | goto out; |
ab18282d CW |
1655 | } |
1656 | ||
d8cb5086 CW |
1657 | ret = i915_gem_object_create_mmap_offset(obj); |
1658 | if (ret) | |
1659 | goto out; | |
de151cf6 | 1660 | |
0de23977 | 1661 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1662 | |
1d7cfea1 | 1663 | out: |
05394f39 | 1664 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1665 | unlock: |
de151cf6 | 1666 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1667 | return ret; |
de151cf6 JB |
1668 | } |
1669 | ||
ff72145b DA |
1670 | /** |
1671 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1672 | * @dev: DRM device | |
1673 | * @data: GTT mapping ioctl data | |
1674 | * @file: GEM object info | |
1675 | * | |
1676 | * Simply returns the fake offset to userspace so it can mmap it. | |
1677 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1678 | * up so we can get faults in the handler above. | |
1679 | * | |
1680 | * The fault handler will take care of binding the object into the GTT | |
1681 | * (since it may have been evicted to make room for something), allocating | |
1682 | * a fence register, and mapping the appropriate aperture address into | |
1683 | * userspace. | |
1684 | */ | |
1685 | int | |
1686 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1687 | struct drm_file *file) | |
1688 | { | |
1689 | struct drm_i915_gem_mmap_gtt *args = data; | |
1690 | ||
ff72145b DA |
1691 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1692 | } | |
1693 | ||
225067ee DV |
1694 | /* Immediately discard the backing storage */ |
1695 | static void | |
1696 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1697 | { |
e5281ccd | 1698 | struct inode *inode; |
e5281ccd | 1699 | |
4d6294bf | 1700 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1701 | |
4d6294bf CW |
1702 | if (obj->base.filp == NULL) |
1703 | return; | |
e5281ccd | 1704 | |
225067ee DV |
1705 | /* Our goal here is to return as much of the memory as |
1706 | * is possible back to the system as we are called from OOM. | |
1707 | * To do this we must instruct the shmfs to drop all of its | |
1708 | * backing pages, *now*. | |
1709 | */ | |
496ad9aa | 1710 | inode = file_inode(obj->base.filp); |
225067ee | 1711 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1712 | |
225067ee DV |
1713 | obj->madv = __I915_MADV_PURGED; |
1714 | } | |
e5281ccd | 1715 | |
225067ee DV |
1716 | static inline int |
1717 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1718 | { | |
1719 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1720 | } |
1721 | ||
5cdf5881 | 1722 | static void |
05394f39 | 1723 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1724 | { |
90797e6d ID |
1725 | struct sg_page_iter sg_iter; |
1726 | int ret; | |
1286ff73 | 1727 | |
05394f39 | 1728 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1729 | |
6c085a72 CW |
1730 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1731 | if (ret) { | |
1732 | /* In the event of a disaster, abandon all caches and | |
1733 | * hope for the best. | |
1734 | */ | |
1735 | WARN_ON(ret != -EIO); | |
2c22569b | 1736 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1737 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1738 | } | |
1739 | ||
6dacfd2f | 1740 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1741 | i915_gem_object_save_bit_17_swizzle(obj); |
1742 | ||
05394f39 CW |
1743 | if (obj->madv == I915_MADV_DONTNEED) |
1744 | obj->dirty = 0; | |
3ef94daa | 1745 | |
90797e6d | 1746 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1747 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1748 | |
05394f39 | 1749 | if (obj->dirty) |
9da3da66 | 1750 | set_page_dirty(page); |
3ef94daa | 1751 | |
05394f39 | 1752 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1753 | mark_page_accessed(page); |
3ef94daa | 1754 | |
9da3da66 | 1755 | page_cache_release(page); |
3ef94daa | 1756 | } |
05394f39 | 1757 | obj->dirty = 0; |
673a394b | 1758 | |
9da3da66 CW |
1759 | sg_free_table(obj->pages); |
1760 | kfree(obj->pages); | |
37e680a1 | 1761 | } |
6c085a72 | 1762 | |
dd624afd | 1763 | int |
37e680a1 CW |
1764 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1765 | { | |
1766 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1767 | ||
2f745ad3 | 1768 | if (obj->pages == NULL) |
37e680a1 CW |
1769 | return 0; |
1770 | ||
a5570178 CW |
1771 | if (obj->pages_pin_count) |
1772 | return -EBUSY; | |
1773 | ||
9843877d | 1774 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1775 | |
a2165e31 CW |
1776 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1777 | * array, hence protect them from being reaped by removing them from gtt | |
1778 | * lists early. */ | |
35c20a60 | 1779 | list_del(&obj->global_list); |
a2165e31 | 1780 | |
37e680a1 | 1781 | ops->put_pages(obj); |
05394f39 | 1782 | obj->pages = NULL; |
37e680a1 | 1783 | |
6c085a72 CW |
1784 | if (i915_gem_object_is_purgeable(obj)) |
1785 | i915_gem_object_truncate(obj); | |
1786 | ||
1787 | return 0; | |
1788 | } | |
1789 | ||
d9973b43 | 1790 | static unsigned long |
93927ca5 DV |
1791 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1792 | bool purgeable_only) | |
6c085a72 | 1793 | { |
c8725f3d CW |
1794 | struct list_head still_in_list; |
1795 | struct drm_i915_gem_object *obj; | |
d9973b43 | 1796 | unsigned long count = 0; |
6c085a72 | 1797 | |
57094f82 | 1798 | /* |
c8725f3d | 1799 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
1800 | * (due to retiring requests) we have to strictly process only |
1801 | * one element of the list at the time, and recheck the list | |
1802 | * on every iteration. | |
c8725f3d CW |
1803 | * |
1804 | * In particular, we must hold a reference whilst removing the | |
1805 | * object as we may end up waiting for and/or retiring the objects. | |
1806 | * This might release the final reference (held by the active list) | |
1807 | * and result in the object being freed from under us. This is | |
1808 | * similar to the precautions the eviction code must take whilst | |
1809 | * removing objects. | |
1810 | * | |
1811 | * Also note that although these lists do not hold a reference to | |
1812 | * the object we can safely grab one here: The final object | |
1813 | * unreferencing and the bound_list are both protected by the | |
1814 | * dev->struct_mutex and so we won't ever be able to observe an | |
1815 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 1816 | */ |
c8725f3d CW |
1817 | INIT_LIST_HEAD(&still_in_list); |
1818 | while (count < target && !list_empty(&dev_priv->mm.unbound_list)) { | |
1819 | obj = list_first_entry(&dev_priv->mm.unbound_list, | |
1820 | typeof(*obj), global_list); | |
1821 | list_move_tail(&obj->global_list, &still_in_list); | |
1822 | ||
1823 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) | |
1824 | continue; | |
1825 | ||
1826 | drm_gem_object_reference(&obj->base); | |
1827 | ||
1828 | if (i915_gem_object_put_pages(obj) == 0) | |
1829 | count += obj->base.size >> PAGE_SHIFT; | |
1830 | ||
1831 | drm_gem_object_unreference(&obj->base); | |
1832 | } | |
1833 | list_splice(&still_in_list, &dev_priv->mm.unbound_list); | |
1834 | ||
1835 | INIT_LIST_HEAD(&still_in_list); | |
57094f82 | 1836 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { |
07fe0b12 | 1837 | struct i915_vma *vma, *v; |
80dcfdbd | 1838 | |
57094f82 CW |
1839 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1840 | typeof(*obj), global_list); | |
c8725f3d | 1841 | list_move_tail(&obj->global_list, &still_in_list); |
57094f82 | 1842 | |
80dcfdbd BW |
1843 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1844 | continue; | |
1845 | ||
57094f82 CW |
1846 | drm_gem_object_reference(&obj->base); |
1847 | ||
07fe0b12 BW |
1848 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1849 | if (i915_vma_unbind(vma)) | |
1850 | break; | |
80dcfdbd | 1851 | |
57094f82 | 1852 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1853 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1854 | |
1855 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1856 | } |
c8725f3d | 1857 | list_splice(&still_in_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1858 | |
1859 | return count; | |
1860 | } | |
1861 | ||
d9973b43 | 1862 | static unsigned long |
93927ca5 DV |
1863 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
1864 | { | |
1865 | return __i915_gem_shrink(dev_priv, target, true); | |
1866 | } | |
1867 | ||
d9973b43 | 1868 | static unsigned long |
6c085a72 CW |
1869 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
1870 | { | |
6c085a72 | 1871 | i915_gem_evict_everything(dev_priv->dev); |
c8725f3d | 1872 | return __i915_gem_shrink(dev_priv, LONG_MAX, false); |
225067ee DV |
1873 | } |
1874 | ||
37e680a1 | 1875 | static int |
6c085a72 | 1876 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1877 | { |
6c085a72 | 1878 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1879 | int page_count, i; |
1880 | struct address_space *mapping; | |
9da3da66 CW |
1881 | struct sg_table *st; |
1882 | struct scatterlist *sg; | |
90797e6d | 1883 | struct sg_page_iter sg_iter; |
e5281ccd | 1884 | struct page *page; |
90797e6d | 1885 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1886 | gfp_t gfp; |
e5281ccd | 1887 | |
6c085a72 CW |
1888 | /* Assert that the object is not currently in any GPU domain. As it |
1889 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1890 | * a GPU cache | |
1891 | */ | |
1892 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1893 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1894 | ||
9da3da66 CW |
1895 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1896 | if (st == NULL) | |
1897 | return -ENOMEM; | |
1898 | ||
05394f39 | 1899 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1900 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 1901 | kfree(st); |
e5281ccd | 1902 | return -ENOMEM; |
9da3da66 | 1903 | } |
e5281ccd | 1904 | |
9da3da66 CW |
1905 | /* Get the list of pages out of our struct file. They'll be pinned |
1906 | * at this point until we release them. | |
1907 | * | |
1908 | * Fail silently without starting the shrinker | |
1909 | */ | |
496ad9aa | 1910 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1911 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1912 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1913 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1914 | sg = st->sgl; |
1915 | st->nents = 0; | |
1916 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1917 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1918 | if (IS_ERR(page)) { | |
1919 | i915_gem_purge(dev_priv, page_count); | |
1920 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1921 | } | |
1922 | if (IS_ERR(page)) { | |
1923 | /* We've tried hard to allocate the memory by reaping | |
1924 | * our own buffer, now let the real VM do its job and | |
1925 | * go down in flames if truly OOM. | |
1926 | */ | |
caf49191 | 1927 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1928 | gfp |= __GFP_IO | __GFP_WAIT; |
1929 | ||
1930 | i915_gem_shrink_all(dev_priv); | |
1931 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1932 | if (IS_ERR(page)) | |
1933 | goto err_pages; | |
1934 | ||
caf49191 | 1935 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1936 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1937 | } | |
426729dc KRW |
1938 | #ifdef CONFIG_SWIOTLB |
1939 | if (swiotlb_nr_tbl()) { | |
1940 | st->nents++; | |
1941 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1942 | sg = sg_next(sg); | |
1943 | continue; | |
1944 | } | |
1945 | #endif | |
90797e6d ID |
1946 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1947 | if (i) | |
1948 | sg = sg_next(sg); | |
1949 | st->nents++; | |
1950 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1951 | } else { | |
1952 | sg->length += PAGE_SIZE; | |
1953 | } | |
1954 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
1955 | |
1956 | /* Check that the i965g/gm workaround works. */ | |
1957 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 1958 | } |
426729dc KRW |
1959 | #ifdef CONFIG_SWIOTLB |
1960 | if (!swiotlb_nr_tbl()) | |
1961 | #endif | |
1962 | sg_mark_end(sg); | |
74ce6b6c CW |
1963 | obj->pages = st; |
1964 | ||
6dacfd2f | 1965 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1966 | i915_gem_object_do_bit_17_swizzle(obj); |
1967 | ||
1968 | return 0; | |
1969 | ||
1970 | err_pages: | |
90797e6d ID |
1971 | sg_mark_end(sg); |
1972 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1973 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1974 | sg_free_table(st); |
1975 | kfree(st); | |
0820baf3 CW |
1976 | |
1977 | /* shmemfs first checks if there is enough memory to allocate the page | |
1978 | * and reports ENOSPC should there be insufficient, along with the usual | |
1979 | * ENOMEM for a genuine allocation failure. | |
1980 | * | |
1981 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
1982 | * space and so want to translate the error from shmemfs back to our | |
1983 | * usual understanding of ENOMEM. | |
1984 | */ | |
1985 | if (PTR_ERR(page) == -ENOSPC) | |
1986 | return -ENOMEM; | |
1987 | else | |
1988 | return PTR_ERR(page); | |
673a394b EA |
1989 | } |
1990 | ||
37e680a1 CW |
1991 | /* Ensure that the associated pages are gathered from the backing storage |
1992 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1993 | * multiple times before they are released by a single call to | |
1994 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1995 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1996 | * or as the object is itself released. | |
1997 | */ | |
1998 | int | |
1999 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2000 | { | |
2001 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2002 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2003 | int ret; | |
2004 | ||
2f745ad3 | 2005 | if (obj->pages) |
37e680a1 CW |
2006 | return 0; |
2007 | ||
43e28f09 | 2008 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2009 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2010 | return -EFAULT; |
43e28f09 CW |
2011 | } |
2012 | ||
a5570178 CW |
2013 | BUG_ON(obj->pages_pin_count); |
2014 | ||
37e680a1 CW |
2015 | ret = ops->get_pages(obj); |
2016 | if (ret) | |
2017 | return ret; | |
2018 | ||
35c20a60 | 2019 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2020 | return 0; |
673a394b EA |
2021 | } |
2022 | ||
e2d05a8b | 2023 | static void |
05394f39 | 2024 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 2025 | struct intel_ring_buffer *ring) |
673a394b | 2026 | { |
05394f39 | 2027 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 2028 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 2029 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 2030 | |
852835f3 | 2031 | BUG_ON(ring == NULL); |
02978ff5 CW |
2032 | if (obj->ring != ring && obj->last_write_seqno) { |
2033 | /* Keep the seqno relative to the current ring */ | |
2034 | obj->last_write_seqno = seqno; | |
2035 | } | |
05394f39 | 2036 | obj->ring = ring; |
673a394b EA |
2037 | |
2038 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2039 | if (!obj->active) { |
2040 | drm_gem_object_reference(&obj->base); | |
2041 | obj->active = 1; | |
673a394b | 2042 | } |
e35a41de | 2043 | |
05394f39 | 2044 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2045 | |
0201f1ec | 2046 | obj->last_read_seqno = seqno; |
caea7476 | 2047 | |
7dd49065 | 2048 | if (obj->fenced_gpu_access) { |
caea7476 | 2049 | obj->last_fenced_seqno = seqno; |
caea7476 | 2050 | |
7dd49065 CW |
2051 | /* Bump MRU to take account of the delayed flush */ |
2052 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2053 | struct drm_i915_fence_reg *reg; | |
2054 | ||
2055 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
2056 | list_move_tail(®->lru_list, | |
2057 | &dev_priv->mm.fence_list); | |
2058 | } | |
caea7476 CW |
2059 | } |
2060 | } | |
2061 | ||
e2d05a8b BW |
2062 | void i915_vma_move_to_active(struct i915_vma *vma, |
2063 | struct intel_ring_buffer *ring) | |
2064 | { | |
2065 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2066 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2067 | } | |
2068 | ||
caea7476 | 2069 | static void |
caea7476 | 2070 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2071 | { |
ca191b13 | 2072 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2073 | struct i915_address_space *vm; |
2074 | struct i915_vma *vma; | |
ce44b0ea | 2075 | |
65ce3027 | 2076 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2077 | BUG_ON(!obj->active); |
caea7476 | 2078 | |
feb822cf BW |
2079 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2080 | vma = i915_gem_obj_to_vma(obj, vm); | |
2081 | if (vma && !list_empty(&vma->mm_list)) | |
2082 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2083 | } | |
caea7476 | 2084 | |
65ce3027 | 2085 | list_del_init(&obj->ring_list); |
caea7476 CW |
2086 | obj->ring = NULL; |
2087 | ||
65ce3027 CW |
2088 | obj->last_read_seqno = 0; |
2089 | obj->last_write_seqno = 0; | |
2090 | obj->base.write_domain = 0; | |
2091 | ||
2092 | obj->last_fenced_seqno = 0; | |
caea7476 | 2093 | obj->fenced_gpu_access = false; |
caea7476 CW |
2094 | |
2095 | obj->active = 0; | |
2096 | drm_gem_object_unreference(&obj->base); | |
2097 | ||
2098 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2099 | } |
673a394b | 2100 | |
c8725f3d CW |
2101 | static void |
2102 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2103 | { | |
2104 | struct intel_ring_buffer *ring = obj->ring; | |
2105 | ||
2106 | if (ring == NULL) | |
2107 | return; | |
2108 | ||
2109 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
2110 | obj->last_read_seqno)) | |
2111 | i915_gem_object_move_to_inactive(obj); | |
2112 | } | |
2113 | ||
9d773091 | 2114 | static int |
fca26bb4 | 2115 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2116 | { |
9d773091 CW |
2117 | struct drm_i915_private *dev_priv = dev->dev_private; |
2118 | struct intel_ring_buffer *ring; | |
2119 | int ret, i, j; | |
53d227f2 | 2120 | |
107f27a5 | 2121 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2122 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2123 | ret = intel_ring_idle(ring); |
2124 | if (ret) | |
2125 | return ret; | |
9d773091 | 2126 | } |
9d773091 | 2127 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2128 | |
2129 | /* Finally reset hw state */ | |
9d773091 | 2130 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2131 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2132 | |
ebc348b2 BW |
2133 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2134 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2135 | } |
53d227f2 | 2136 | |
9d773091 | 2137 | return 0; |
53d227f2 DV |
2138 | } |
2139 | ||
fca26bb4 MK |
2140 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2141 | { | |
2142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2143 | int ret; | |
2144 | ||
2145 | if (seqno == 0) | |
2146 | return -EINVAL; | |
2147 | ||
2148 | /* HWS page needs to be set less than what we | |
2149 | * will inject to ring | |
2150 | */ | |
2151 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2152 | if (ret) | |
2153 | return ret; | |
2154 | ||
2155 | /* Carefully set the last_seqno value so that wrap | |
2156 | * detection still works | |
2157 | */ | |
2158 | dev_priv->next_seqno = seqno; | |
2159 | dev_priv->last_seqno = seqno - 1; | |
2160 | if (dev_priv->last_seqno == 0) | |
2161 | dev_priv->last_seqno--; | |
2162 | ||
2163 | return 0; | |
2164 | } | |
2165 | ||
9d773091 CW |
2166 | int |
2167 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2168 | { |
9d773091 CW |
2169 | struct drm_i915_private *dev_priv = dev->dev_private; |
2170 | ||
2171 | /* reserve 0 for non-seqno */ | |
2172 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2173 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2174 | if (ret) |
2175 | return ret; | |
53d227f2 | 2176 | |
9d773091 CW |
2177 | dev_priv->next_seqno = 1; |
2178 | } | |
53d227f2 | 2179 | |
f72b3435 | 2180 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2181 | return 0; |
53d227f2 DV |
2182 | } |
2183 | ||
0025c077 MK |
2184 | int __i915_add_request(struct intel_ring_buffer *ring, |
2185 | struct drm_file *file, | |
7d736f4f | 2186 | struct drm_i915_gem_object *obj, |
0025c077 | 2187 | u32 *out_seqno) |
673a394b | 2188 | { |
3e31c6c0 | 2189 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2190 | struct drm_i915_gem_request *request; |
7d736f4f | 2191 | u32 request_ring_position, request_start; |
3cce469c CW |
2192 | int ret; |
2193 | ||
7d736f4f | 2194 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2195 | /* |
2196 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2197 | * after having emitted the batchbuffer command. Hence we need to fix | |
2198 | * things up similar to emitting the lazy request. The difference here | |
2199 | * is that the flush _must_ happen before the next request, no matter | |
2200 | * what. | |
2201 | */ | |
a7b9761d CW |
2202 | ret = intel_ring_flush_all_caches(ring); |
2203 | if (ret) | |
2204 | return ret; | |
cc889e0f | 2205 | |
3c0e234c CW |
2206 | request = ring->preallocated_lazy_request; |
2207 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2208 | return -ENOMEM; |
cc889e0f | 2209 | |
a71d8d94 CW |
2210 | /* Record the position of the start of the request so that |
2211 | * should we detect the updated seqno part-way through the | |
2212 | * GPU processing the request, we never over-estimate the | |
2213 | * position of the head. | |
2214 | */ | |
2215 | request_ring_position = intel_ring_get_tail(ring); | |
2216 | ||
9d773091 | 2217 | ret = ring->add_request(ring); |
3c0e234c | 2218 | if (ret) |
3bb73aba | 2219 | return ret; |
673a394b | 2220 | |
9d773091 | 2221 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2222 | request->ring = ring; |
7d736f4f | 2223 | request->head = request_start; |
a71d8d94 | 2224 | request->tail = request_ring_position; |
7d736f4f MK |
2225 | |
2226 | /* Whilst this request exists, batch_obj will be on the | |
2227 | * active_list, and so will hold the active reference. Only when this | |
2228 | * request is retired will the the batch_obj be moved onto the | |
2229 | * inactive_list and lose its active reference. Hence we do not need | |
2230 | * to explicitly hold another reference here. | |
2231 | */ | |
9a7e0c2a | 2232 | request->batch_obj = obj; |
0e50e96b | 2233 | |
9a7e0c2a CW |
2234 | /* Hold a reference to the current context so that we can inspect |
2235 | * it later in case a hangcheck error event fires. | |
2236 | */ | |
2237 | request->ctx = ring->last_context; | |
0e50e96b MK |
2238 | if (request->ctx) |
2239 | i915_gem_context_reference(request->ctx); | |
2240 | ||
673a394b | 2241 | request->emitted_jiffies = jiffies; |
852835f3 | 2242 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2243 | request->file_priv = NULL; |
852835f3 | 2244 | |
db53a302 CW |
2245 | if (file) { |
2246 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2247 | ||
1c25595f | 2248 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2249 | request->file_priv = file_priv; |
b962442e | 2250 | list_add_tail(&request->client_list, |
f787a5f5 | 2251 | &file_priv->mm.request_list); |
1c25595f | 2252 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2253 | } |
673a394b | 2254 | |
9d773091 | 2255 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2256 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2257 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2258 | |
db1b76ca | 2259 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2260 | i915_queue_hangcheck(ring->dev); |
2261 | ||
f62a0076 CW |
2262 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2263 | queue_delayed_work(dev_priv->wq, | |
2264 | &dev_priv->mm.retire_work, | |
2265 | round_jiffies_up_relative(HZ)); | |
2266 | intel_mark_busy(dev_priv->dev); | |
f65d9421 | 2267 | } |
cc889e0f | 2268 | |
acb868d3 | 2269 | if (out_seqno) |
9d773091 | 2270 | *out_seqno = request->seqno; |
3cce469c | 2271 | return 0; |
673a394b EA |
2272 | } |
2273 | ||
f787a5f5 CW |
2274 | static inline void |
2275 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2276 | { |
1c25595f | 2277 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2278 | |
1c25595f CW |
2279 | if (!file_priv) |
2280 | return; | |
1c5d22f7 | 2281 | |
1c25595f | 2282 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2283 | list_del(&request->client_list); |
2284 | request->file_priv = NULL; | |
1c25595f | 2285 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2286 | } |
673a394b | 2287 | |
939fd762 | 2288 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
44e2c070 | 2289 | const struct i915_hw_context *ctx) |
be62acb4 | 2290 | { |
44e2c070 | 2291 | unsigned long elapsed; |
be62acb4 | 2292 | |
44e2c070 MK |
2293 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2294 | ||
2295 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2296 | return true; |
2297 | ||
2298 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2299 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2300 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2301 | return true; |
88b4aa87 MK |
2302 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2303 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2304 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2305 | return true; |
3fac8978 | 2306 | } |
be62acb4 MK |
2307 | } |
2308 | ||
2309 | return false; | |
2310 | } | |
2311 | ||
939fd762 MK |
2312 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
2313 | struct i915_hw_context *ctx, | |
b6b0fac0 | 2314 | const bool guilty) |
aa60c664 | 2315 | { |
44e2c070 MK |
2316 | struct i915_ctx_hang_stats *hs; |
2317 | ||
2318 | if (WARN_ON(!ctx)) | |
2319 | return; | |
aa60c664 | 2320 | |
44e2c070 MK |
2321 | hs = &ctx->hang_stats; |
2322 | ||
2323 | if (guilty) { | |
939fd762 | 2324 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2325 | hs->batch_active++; |
2326 | hs->guilty_ts = get_seconds(); | |
2327 | } else { | |
2328 | hs->batch_pending++; | |
aa60c664 MK |
2329 | } |
2330 | } | |
2331 | ||
0e50e96b MK |
2332 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2333 | { | |
2334 | list_del(&request->list); | |
2335 | i915_gem_request_remove_from_client(request); | |
2336 | ||
2337 | if (request->ctx) | |
2338 | i915_gem_context_unreference(request->ctx); | |
2339 | ||
2340 | kfree(request); | |
2341 | } | |
2342 | ||
8d9fc7fd CW |
2343 | struct drm_i915_gem_request * |
2344 | i915_gem_find_active_request(struct intel_ring_buffer *ring) | |
9375e446 | 2345 | { |
4db080f9 | 2346 | struct drm_i915_gem_request *request; |
8d9fc7fd CW |
2347 | u32 completed_seqno; |
2348 | ||
2349 | completed_seqno = ring->get_seqno(ring, false); | |
4db080f9 CW |
2350 | |
2351 | list_for_each_entry(request, &ring->request_list, list) { | |
2352 | if (i915_seqno_passed(completed_seqno, request->seqno)) | |
2353 | continue; | |
aa60c664 | 2354 | |
b6b0fac0 | 2355 | return request; |
4db080f9 | 2356 | } |
b6b0fac0 MK |
2357 | |
2358 | return NULL; | |
2359 | } | |
2360 | ||
2361 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
2362 | struct intel_ring_buffer *ring) | |
2363 | { | |
2364 | struct drm_i915_gem_request *request; | |
2365 | bool ring_hung; | |
2366 | ||
8d9fc7fd | 2367 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2368 | |
2369 | if (request == NULL) | |
2370 | return; | |
2371 | ||
2372 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2373 | ||
939fd762 | 2374 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2375 | |
2376 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2377 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2378 | } |
aa60c664 | 2379 | |
4db080f9 CW |
2380 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
2381 | struct intel_ring_buffer *ring) | |
2382 | { | |
dfaae392 | 2383 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2384 | struct drm_i915_gem_object *obj; |
9375e446 | 2385 | |
05394f39 CW |
2386 | obj = list_first_entry(&ring->active_list, |
2387 | struct drm_i915_gem_object, | |
2388 | ring_list); | |
9375e446 | 2389 | |
05394f39 | 2390 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2391 | } |
1d62beea BW |
2392 | |
2393 | /* | |
2394 | * We must free the requests after all the corresponding objects have | |
2395 | * been moved off active lists. Which is the same order as the normal | |
2396 | * retire_requests function does. This is important if object hold | |
2397 | * implicit references on things like e.g. ppgtt address spaces through | |
2398 | * the request. | |
2399 | */ | |
2400 | while (!list_empty(&ring->request_list)) { | |
2401 | struct drm_i915_gem_request *request; | |
2402 | ||
2403 | request = list_first_entry(&ring->request_list, | |
2404 | struct drm_i915_gem_request, | |
2405 | list); | |
2406 | ||
2407 | i915_gem_free_request(request); | |
2408 | } | |
e3efda49 CW |
2409 | |
2410 | /* These may not have been flush before the reset, do so now */ | |
2411 | kfree(ring->preallocated_lazy_request); | |
2412 | ring->preallocated_lazy_request = NULL; | |
2413 | ring->outstanding_lazy_seqno = 0; | |
673a394b EA |
2414 | } |
2415 | ||
19b2dbde | 2416 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2417 | { |
2418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2419 | int i; | |
2420 | ||
4b9de737 | 2421 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2422 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2423 | |
94a335db DV |
2424 | /* |
2425 | * Commit delayed tiling changes if we have an object still | |
2426 | * attached to the fence, otherwise just clear the fence. | |
2427 | */ | |
2428 | if (reg->obj) { | |
2429 | i915_gem_object_update_fence(reg->obj, reg, | |
2430 | reg->obj->tiling_mode); | |
2431 | } else { | |
2432 | i915_gem_write_fence(dev, i, NULL); | |
2433 | } | |
312817a3 CW |
2434 | } |
2435 | } | |
2436 | ||
069efc1d | 2437 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2438 | { |
77f01230 | 2439 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2440 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2441 | int i; |
673a394b | 2442 | |
4db080f9 CW |
2443 | /* |
2444 | * Before we free the objects from the requests, we need to inspect | |
2445 | * them for finding the guilty party. As the requests only borrow | |
2446 | * their reference to the objects, the inspection must be done first. | |
2447 | */ | |
2448 | for_each_ring(ring, dev_priv, i) | |
2449 | i915_gem_reset_ring_status(dev_priv, ring); | |
2450 | ||
b4519513 | 2451 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2452 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2453 | |
acce9ffa BW |
2454 | i915_gem_context_reset(dev); |
2455 | ||
19b2dbde | 2456 | i915_gem_restore_fences(dev); |
673a394b EA |
2457 | } |
2458 | ||
2459 | /** | |
2460 | * This function clears the request list as sequence numbers are passed. | |
2461 | */ | |
1cf0ba14 | 2462 | void |
db53a302 | 2463 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2464 | { |
673a394b EA |
2465 | uint32_t seqno; |
2466 | ||
db53a302 | 2467 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2468 | return; |
2469 | ||
db53a302 | 2470 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2471 | |
b2eadbc8 | 2472 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2473 | |
e9103038 CW |
2474 | /* Move any buffers on the active list that are no longer referenced |
2475 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2476 | * before we free the context associated with the requests. | |
2477 | */ | |
2478 | while (!list_empty(&ring->active_list)) { | |
2479 | struct drm_i915_gem_object *obj; | |
2480 | ||
2481 | obj = list_first_entry(&ring->active_list, | |
2482 | struct drm_i915_gem_object, | |
2483 | ring_list); | |
2484 | ||
2485 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) | |
2486 | break; | |
2487 | ||
2488 | i915_gem_object_move_to_inactive(obj); | |
2489 | } | |
2490 | ||
2491 | ||
852835f3 | 2492 | while (!list_empty(&ring->request_list)) { |
673a394b | 2493 | struct drm_i915_gem_request *request; |
673a394b | 2494 | |
852835f3 | 2495 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2496 | struct drm_i915_gem_request, |
2497 | list); | |
673a394b | 2498 | |
dfaae392 | 2499 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2500 | break; |
2501 | ||
db53a302 | 2502 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2503 | /* We know the GPU must have read the request to have |
2504 | * sent us the seqno + interrupt, so use the position | |
2505 | * of tail of the request to update the last known position | |
2506 | * of the GPU head. | |
2507 | */ | |
2508 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2509 | |
0e50e96b | 2510 | i915_gem_free_request(request); |
b84d5f0c | 2511 | } |
673a394b | 2512 | |
db53a302 CW |
2513 | if (unlikely(ring->trace_irq_seqno && |
2514 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2515 | ring->irq_put(ring); |
db53a302 | 2516 | ring->trace_irq_seqno = 0; |
9d34e5db | 2517 | } |
23bc5982 | 2518 | |
db53a302 | 2519 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2520 | } |
2521 | ||
b29c19b6 | 2522 | bool |
b09a1fec CW |
2523 | i915_gem_retire_requests(struct drm_device *dev) |
2524 | { | |
3e31c6c0 | 2525 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2526 | struct intel_ring_buffer *ring; |
b29c19b6 | 2527 | bool idle = true; |
1ec14ad3 | 2528 | int i; |
b09a1fec | 2529 | |
b29c19b6 | 2530 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2531 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2532 | idle &= list_empty(&ring->request_list); |
2533 | } | |
2534 | ||
2535 | if (idle) | |
2536 | mod_delayed_work(dev_priv->wq, | |
2537 | &dev_priv->mm.idle_work, | |
2538 | msecs_to_jiffies(100)); | |
2539 | ||
2540 | return idle; | |
b09a1fec CW |
2541 | } |
2542 | ||
75ef9da2 | 2543 | static void |
673a394b EA |
2544 | i915_gem_retire_work_handler(struct work_struct *work) |
2545 | { | |
b29c19b6 CW |
2546 | struct drm_i915_private *dev_priv = |
2547 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2548 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2549 | bool idle; |
673a394b | 2550 | |
891b48cf | 2551 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2552 | idle = false; |
2553 | if (mutex_trylock(&dev->struct_mutex)) { | |
2554 | idle = i915_gem_retire_requests(dev); | |
2555 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2556 | } |
b29c19b6 | 2557 | if (!idle) |
bcb45086 CW |
2558 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2559 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2560 | } |
0a58705b | 2561 | |
b29c19b6 CW |
2562 | static void |
2563 | i915_gem_idle_work_handler(struct work_struct *work) | |
2564 | { | |
2565 | struct drm_i915_private *dev_priv = | |
2566 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2567 | ||
2568 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2569 | } |
2570 | ||
30dfebf3 DV |
2571 | /** |
2572 | * Ensures that an object will eventually get non-busy by flushing any required | |
2573 | * write domains, emitting any outstanding lazy request and retiring and | |
2574 | * completed requests. | |
2575 | */ | |
2576 | static int | |
2577 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2578 | { | |
2579 | int ret; | |
2580 | ||
2581 | if (obj->active) { | |
0201f1ec | 2582 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2583 | if (ret) |
2584 | return ret; | |
2585 | ||
30dfebf3 DV |
2586 | i915_gem_retire_requests_ring(obj->ring); |
2587 | } | |
2588 | ||
2589 | return 0; | |
2590 | } | |
2591 | ||
23ba4fd0 BW |
2592 | /** |
2593 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2594 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2595 | * | |
2596 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2597 | * the timeout parameter. | |
2598 | * -ETIME: object is still busy after timeout | |
2599 | * -ERESTARTSYS: signal interrupted the wait | |
2600 | * -ENONENT: object doesn't exist | |
2601 | * Also possible, but rare: | |
2602 | * -EAGAIN: GPU wedged | |
2603 | * -ENOMEM: damn | |
2604 | * -ENODEV: Internal IRQ fail | |
2605 | * -E?: The add request failed | |
2606 | * | |
2607 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2608 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2609 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2610 | * without holding struct_mutex the object may become re-busied before this | |
2611 | * function completes. A similar but shorter * race condition exists in the busy | |
2612 | * ioctl | |
2613 | */ | |
2614 | int | |
2615 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2616 | { | |
3e31c6c0 | 2617 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2618 | struct drm_i915_gem_wait *args = data; |
2619 | struct drm_i915_gem_object *obj; | |
2620 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2621 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2622 | unsigned reset_counter; |
23ba4fd0 BW |
2623 | u32 seqno = 0; |
2624 | int ret = 0; | |
2625 | ||
eac1f14f BW |
2626 | if (args->timeout_ns >= 0) { |
2627 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2628 | timeout = &timeout_stack; | |
2629 | } | |
23ba4fd0 BW |
2630 | |
2631 | ret = i915_mutex_lock_interruptible(dev); | |
2632 | if (ret) | |
2633 | return ret; | |
2634 | ||
2635 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2636 | if (&obj->base == NULL) { | |
2637 | mutex_unlock(&dev->struct_mutex); | |
2638 | return -ENOENT; | |
2639 | } | |
2640 | ||
30dfebf3 DV |
2641 | /* Need to make sure the object gets inactive eventually. */ |
2642 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2643 | if (ret) |
2644 | goto out; | |
2645 | ||
2646 | if (obj->active) { | |
0201f1ec | 2647 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2648 | ring = obj->ring; |
2649 | } | |
2650 | ||
2651 | if (seqno == 0) | |
2652 | goto out; | |
2653 | ||
23ba4fd0 BW |
2654 | /* Do this after OLR check to make sure we make forward progress polling |
2655 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2656 | */ | |
2657 | if (!args->timeout_ns) { | |
2658 | ret = -ETIME; | |
2659 | goto out; | |
2660 | } | |
2661 | ||
2662 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2663 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2664 | mutex_unlock(&dev->struct_mutex); |
2665 | ||
b29c19b6 | 2666 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2667 | if (timeout) |
eac1f14f | 2668 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2669 | return ret; |
2670 | ||
2671 | out: | |
2672 | drm_gem_object_unreference(&obj->base); | |
2673 | mutex_unlock(&dev->struct_mutex); | |
2674 | return ret; | |
2675 | } | |
2676 | ||
5816d648 BW |
2677 | /** |
2678 | * i915_gem_object_sync - sync an object to a ring. | |
2679 | * | |
2680 | * @obj: object which may be in use on another ring. | |
2681 | * @to: ring we wish to use the object on. May be NULL. | |
2682 | * | |
2683 | * This code is meant to abstract object synchronization with the GPU. | |
2684 | * Calling with NULL implies synchronizing the object with the CPU | |
2685 | * rather than a particular GPU ring. | |
2686 | * | |
2687 | * Returns 0 if successful, else propagates up the lower layer error. | |
2688 | */ | |
2911a35b BW |
2689 | int |
2690 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2691 | struct intel_ring_buffer *to) | |
2692 | { | |
2693 | struct intel_ring_buffer *from = obj->ring; | |
2694 | u32 seqno; | |
2695 | int ret, idx; | |
2696 | ||
2697 | if (from == NULL || to == from) | |
2698 | return 0; | |
2699 | ||
5816d648 | 2700 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2701 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2702 | |
2703 | idx = intel_ring_sync_index(from, to); | |
2704 | ||
0201f1ec | 2705 | seqno = obj->last_read_seqno; |
ebc348b2 | 2706 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2707 | return 0; |
2708 | ||
b4aca010 BW |
2709 | ret = i915_gem_check_olr(obj->ring, seqno); |
2710 | if (ret) | |
2711 | return ret; | |
2911a35b | 2712 | |
b52b89da | 2713 | trace_i915_gem_ring_sync_to(from, to, seqno); |
ebc348b2 | 2714 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 2715 | if (!ret) |
7b01e260 MK |
2716 | /* We use last_read_seqno because sync_to() |
2717 | * might have just caused seqno wrap under | |
2718 | * the radar. | |
2719 | */ | |
ebc348b2 | 2720 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
2911a35b | 2721 | |
e3a5a225 | 2722 | return ret; |
2911a35b BW |
2723 | } |
2724 | ||
b5ffc9bc CW |
2725 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2726 | { | |
2727 | u32 old_write_domain, old_read_domains; | |
2728 | ||
b5ffc9bc CW |
2729 | /* Force a pagefault for domain tracking on next user access */ |
2730 | i915_gem_release_mmap(obj); | |
2731 | ||
b97c3d9c KP |
2732 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2733 | return; | |
2734 | ||
97c809fd CW |
2735 | /* Wait for any direct GTT access to complete */ |
2736 | mb(); | |
2737 | ||
b5ffc9bc CW |
2738 | old_read_domains = obj->base.read_domains; |
2739 | old_write_domain = obj->base.write_domain; | |
2740 | ||
2741 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2742 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2743 | ||
2744 | trace_i915_gem_object_change_domain(obj, | |
2745 | old_read_domains, | |
2746 | old_write_domain); | |
2747 | } | |
2748 | ||
07fe0b12 | 2749 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2750 | { |
07fe0b12 | 2751 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 2752 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2753 | int ret; |
673a394b | 2754 | |
07fe0b12 | 2755 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2756 | return 0; |
2757 | ||
0ff501cb DV |
2758 | if (!drm_mm_node_allocated(&vma->node)) { |
2759 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
2760 | return 0; |
2761 | } | |
433544bd | 2762 | |
d7f46fc4 | 2763 | if (vma->pin_count) |
31d8d651 | 2764 | return -EBUSY; |
673a394b | 2765 | |
c4670ad0 CW |
2766 | BUG_ON(obj->pages == NULL); |
2767 | ||
a8198eea | 2768 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2769 | if (ret) |
a8198eea CW |
2770 | return ret; |
2771 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2772 | * should be safe and we need to cleanup or else we might | |
2773 | * cause memory corruption through use-after-free. | |
2774 | */ | |
2775 | ||
8b1bc9b4 DV |
2776 | if (i915_is_ggtt(vma->vm)) { |
2777 | i915_gem_object_finish_gtt(obj); | |
5323fd04 | 2778 | |
8b1bc9b4 DV |
2779 | /* release the fence reg _after_ flushing */ |
2780 | ret = i915_gem_object_put_fence(obj); | |
2781 | if (ret) | |
2782 | return ret; | |
2783 | } | |
96b47b65 | 2784 | |
07fe0b12 | 2785 | trace_i915_vma_unbind(vma); |
db53a302 | 2786 | |
6f65e29a BW |
2787 | vma->unbind_vma(vma); |
2788 | ||
74163907 | 2789 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2790 | |
64bf9303 | 2791 | list_del_init(&vma->mm_list); |
75e9e915 | 2792 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2793 | if (i915_is_ggtt(vma->vm)) |
2794 | obj->map_and_fenceable = true; | |
673a394b | 2795 | |
2f633156 BW |
2796 | drm_mm_remove_node(&vma->node); |
2797 | i915_gem_vma_destroy(vma); | |
2798 | ||
2799 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2800 | * no more VMAs exist. */ |
2f633156 BW |
2801 | if (list_empty(&obj->vma_list)) |
2802 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2803 | |
70903c3b CW |
2804 | /* And finally now the object is completely decoupled from this vma, |
2805 | * we can drop its hold on the backing storage and allow it to be | |
2806 | * reaped by the shrinker. | |
2807 | */ | |
2808 | i915_gem_object_unpin_pages(obj); | |
2809 | ||
88241785 | 2810 | return 0; |
54cf91dc CW |
2811 | } |
2812 | ||
b2da9fe5 | 2813 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 2814 | { |
3e31c6c0 | 2815 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2816 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2817 | int ret, i; |
4df2faf4 | 2818 | |
4df2faf4 | 2819 | /* Flush everything onto the inactive list. */ |
b4519513 | 2820 | for_each_ring(ring, dev_priv, i) { |
691e6415 | 2821 | ret = i915_switch_context(ring, ring->default_context); |
b6c7488d BW |
2822 | if (ret) |
2823 | return ret; | |
2824 | ||
3e960501 | 2825 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2826 | if (ret) |
2827 | return ret; | |
2828 | } | |
4df2faf4 | 2829 | |
8a1a49f9 | 2830 | return 0; |
4df2faf4 DV |
2831 | } |
2832 | ||
9ce079e4 CW |
2833 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2834 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2835 | { |
3e31c6c0 | 2836 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
2837 | int fence_reg; |
2838 | int fence_pitch_shift; | |
de151cf6 | 2839 | |
56c844e5 ID |
2840 | if (INTEL_INFO(dev)->gen >= 6) { |
2841 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2842 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2843 | } else { | |
2844 | fence_reg = FENCE_REG_965_0; | |
2845 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2846 | } | |
2847 | ||
d18b9619 CW |
2848 | fence_reg += reg * 8; |
2849 | ||
2850 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2851 | * we split the 64-bit update into two 32-bit writes. In order | |
2852 | * for a partial fence not to be evaluated between writes, we | |
2853 | * precede the update with write to turn off the fence register, | |
2854 | * and only enable the fence as the last step. | |
2855 | * | |
2856 | * For extra levels of paranoia, we make sure each step lands | |
2857 | * before applying the next step. | |
2858 | */ | |
2859 | I915_WRITE(fence_reg, 0); | |
2860 | POSTING_READ(fence_reg); | |
2861 | ||
9ce079e4 | 2862 | if (obj) { |
f343c5f6 | 2863 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2864 | uint64_t val; |
de151cf6 | 2865 | |
f343c5f6 | 2866 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2867 | 0xfffff000) << 32; |
f343c5f6 | 2868 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2869 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2870 | if (obj->tiling_mode == I915_TILING_Y) |
2871 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2872 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2873 | |
d18b9619 CW |
2874 | I915_WRITE(fence_reg + 4, val >> 32); |
2875 | POSTING_READ(fence_reg + 4); | |
2876 | ||
2877 | I915_WRITE(fence_reg + 0, val); | |
2878 | POSTING_READ(fence_reg); | |
2879 | } else { | |
2880 | I915_WRITE(fence_reg + 4, 0); | |
2881 | POSTING_READ(fence_reg + 4); | |
2882 | } | |
de151cf6 JB |
2883 | } |
2884 | ||
9ce079e4 CW |
2885 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2886 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2887 | { |
3e31c6c0 | 2888 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 2889 | u32 val; |
de151cf6 | 2890 | |
9ce079e4 | 2891 | if (obj) { |
f343c5f6 | 2892 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2893 | int pitch_val; |
2894 | int tile_width; | |
c6642782 | 2895 | |
f343c5f6 | 2896 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2897 | (size & -size) != size || |
f343c5f6 BW |
2898 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2899 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2900 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2901 | |
9ce079e4 CW |
2902 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2903 | tile_width = 128; | |
2904 | else | |
2905 | tile_width = 512; | |
2906 | ||
2907 | /* Note: pitch better be a power of two tile widths */ | |
2908 | pitch_val = obj->stride / tile_width; | |
2909 | pitch_val = ffs(pitch_val) - 1; | |
2910 | ||
f343c5f6 | 2911 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2912 | if (obj->tiling_mode == I915_TILING_Y) |
2913 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2914 | val |= I915_FENCE_SIZE_BITS(size); | |
2915 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2916 | val |= I830_FENCE_REG_VALID; | |
2917 | } else | |
2918 | val = 0; | |
2919 | ||
2920 | if (reg < 8) | |
2921 | reg = FENCE_REG_830_0 + reg * 4; | |
2922 | else | |
2923 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2924 | ||
2925 | I915_WRITE(reg, val); | |
2926 | POSTING_READ(reg); | |
de151cf6 JB |
2927 | } |
2928 | ||
9ce079e4 CW |
2929 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2930 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2931 | { |
3e31c6c0 | 2932 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 2933 | uint32_t val; |
de151cf6 | 2934 | |
9ce079e4 | 2935 | if (obj) { |
f343c5f6 | 2936 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2937 | uint32_t pitch_val; |
de151cf6 | 2938 | |
f343c5f6 | 2939 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2940 | (size & -size) != size || |
f343c5f6 BW |
2941 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2942 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2943 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2944 | |
9ce079e4 CW |
2945 | pitch_val = obj->stride / 128; |
2946 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2947 | |
f343c5f6 | 2948 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2949 | if (obj->tiling_mode == I915_TILING_Y) |
2950 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2951 | val |= I830_FENCE_SIZE_BITS(size); | |
2952 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2953 | val |= I830_FENCE_REG_VALID; | |
2954 | } else | |
2955 | val = 0; | |
c6642782 | 2956 | |
9ce079e4 CW |
2957 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2958 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2959 | } | |
2960 | ||
d0a57789 CW |
2961 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2962 | { | |
2963 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2964 | } | |
2965 | ||
9ce079e4 CW |
2966 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2967 | struct drm_i915_gem_object *obj) | |
2968 | { | |
d0a57789 CW |
2969 | struct drm_i915_private *dev_priv = dev->dev_private; |
2970 | ||
2971 | /* Ensure that all CPU reads are completed before installing a fence | |
2972 | * and all writes before removing the fence. | |
2973 | */ | |
2974 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2975 | mb(); | |
2976 | ||
94a335db DV |
2977 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2978 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2979 | obj->stride, obj->tiling_mode); | |
2980 | ||
9ce079e4 | 2981 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 2982 | case 8: |
9ce079e4 | 2983 | case 7: |
56c844e5 | 2984 | case 6: |
9ce079e4 CW |
2985 | case 5: |
2986 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2987 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2988 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2989 | default: BUG(); |
9ce079e4 | 2990 | } |
d0a57789 CW |
2991 | |
2992 | /* And similarly be paranoid that no direct access to this region | |
2993 | * is reordered to before the fence is installed. | |
2994 | */ | |
2995 | if (i915_gem_object_needs_mb(obj)) | |
2996 | mb(); | |
de151cf6 JB |
2997 | } |
2998 | ||
61050808 CW |
2999 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3000 | struct drm_i915_fence_reg *fence) | |
3001 | { | |
3002 | return fence - dev_priv->fence_regs; | |
3003 | } | |
3004 | ||
3005 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3006 | struct drm_i915_fence_reg *fence, | |
3007 | bool enable) | |
3008 | { | |
2dc8aae0 | 3009 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3010 | int reg = fence_number(dev_priv, fence); |
3011 | ||
3012 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3013 | |
3014 | if (enable) { | |
46a0b638 | 3015 | obj->fence_reg = reg; |
61050808 CW |
3016 | fence->obj = obj; |
3017 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3018 | } else { | |
3019 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3020 | fence->obj = NULL; | |
3021 | list_del_init(&fence->lru_list); | |
3022 | } | |
94a335db | 3023 | obj->fence_dirty = false; |
61050808 CW |
3024 | } |
3025 | ||
d9e86c0e | 3026 | static int |
d0a57789 | 3027 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3028 | { |
1c293ea3 | 3029 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3030 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3031 | if (ret) |
3032 | return ret; | |
d9e86c0e CW |
3033 | |
3034 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3035 | } |
3036 | ||
86d5bc37 | 3037 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3038 | return 0; |
3039 | } | |
3040 | ||
3041 | int | |
3042 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3043 | { | |
61050808 | 3044 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3045 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3046 | int ret; |
3047 | ||
d0a57789 | 3048 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3049 | if (ret) |
3050 | return ret; | |
3051 | ||
61050808 CW |
3052 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3053 | return 0; | |
d9e86c0e | 3054 | |
f9c513e9 CW |
3055 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3056 | ||
aff10b30 DV |
3057 | if (WARN_ON(fence->pin_count)) |
3058 | return -EBUSY; | |
3059 | ||
61050808 | 3060 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3061 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3062 | |
3063 | return 0; | |
3064 | } | |
3065 | ||
3066 | static struct drm_i915_fence_reg * | |
a360bb1a | 3067 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3068 | { |
ae3db24a | 3069 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3070 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3071 | int i; |
ae3db24a DV |
3072 | |
3073 | /* First try to find a free reg */ | |
d9e86c0e | 3074 | avail = NULL; |
ae3db24a DV |
3075 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3076 | reg = &dev_priv->fence_regs[i]; | |
3077 | if (!reg->obj) | |
d9e86c0e | 3078 | return reg; |
ae3db24a | 3079 | |
1690e1eb | 3080 | if (!reg->pin_count) |
d9e86c0e | 3081 | avail = reg; |
ae3db24a DV |
3082 | } |
3083 | ||
d9e86c0e | 3084 | if (avail == NULL) |
5dce5b93 | 3085 | goto deadlock; |
ae3db24a DV |
3086 | |
3087 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3088 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3089 | if (reg->pin_count) |
ae3db24a DV |
3090 | continue; |
3091 | ||
8fe301ad | 3092 | return reg; |
ae3db24a DV |
3093 | } |
3094 | ||
5dce5b93 CW |
3095 | deadlock: |
3096 | /* Wait for completion of pending flips which consume fences */ | |
3097 | if (intel_has_pending_fb_unpin(dev)) | |
3098 | return ERR_PTR(-EAGAIN); | |
3099 | ||
3100 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3101 | } |
3102 | ||
de151cf6 | 3103 | /** |
9a5a53b3 | 3104 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3105 | * @obj: object to map through a fence reg |
3106 | * | |
3107 | * When mapping objects through the GTT, userspace wants to be able to write | |
3108 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3109 | * This function walks the fence regs looking for a free one for @obj, |
3110 | * stealing one if it can't find any. | |
3111 | * | |
3112 | * It then sets up the reg based on the object's properties: address, pitch | |
3113 | * and tiling format. | |
9a5a53b3 CW |
3114 | * |
3115 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3116 | */ |
8c4b8c3f | 3117 | int |
06d98131 | 3118 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3119 | { |
05394f39 | 3120 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3121 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3122 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3123 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3124 | int ret; |
de151cf6 | 3125 | |
14415745 CW |
3126 | /* Have we updated the tiling parameters upon the object and so |
3127 | * will need to serialise the write to the associated fence register? | |
3128 | */ | |
5d82e3e6 | 3129 | if (obj->fence_dirty) { |
d0a57789 | 3130 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3131 | if (ret) |
3132 | return ret; | |
3133 | } | |
9a5a53b3 | 3134 | |
d9e86c0e | 3135 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3136 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3137 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3138 | if (!obj->fence_dirty) { |
14415745 CW |
3139 | list_move_tail(®->lru_list, |
3140 | &dev_priv->mm.fence_list); | |
3141 | return 0; | |
3142 | } | |
3143 | } else if (enable) { | |
3144 | reg = i915_find_fence_reg(dev); | |
5dce5b93 CW |
3145 | if (IS_ERR(reg)) |
3146 | return PTR_ERR(reg); | |
d9e86c0e | 3147 | |
14415745 CW |
3148 | if (reg->obj) { |
3149 | struct drm_i915_gem_object *old = reg->obj; | |
3150 | ||
d0a57789 | 3151 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3152 | if (ret) |
3153 | return ret; | |
3154 | ||
14415745 | 3155 | i915_gem_object_fence_lost(old); |
29c5a587 | 3156 | } |
14415745 | 3157 | } else |
a09ba7fa | 3158 | return 0; |
a09ba7fa | 3159 | |
14415745 | 3160 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3161 | |
9ce079e4 | 3162 | return 0; |
de151cf6 JB |
3163 | } |
3164 | ||
42d6ab48 CW |
3165 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3166 | struct drm_mm_node *gtt_space, | |
3167 | unsigned long cache_level) | |
3168 | { | |
3169 | struct drm_mm_node *other; | |
3170 | ||
3171 | /* On non-LLC machines we have to be careful when putting differing | |
3172 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3173 | * crossing memory domains and dying. |
42d6ab48 CW |
3174 | */ |
3175 | if (HAS_LLC(dev)) | |
3176 | return true; | |
3177 | ||
c6cfb325 | 3178 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3179 | return true; |
3180 | ||
3181 | if (list_empty(>t_space->node_list)) | |
3182 | return true; | |
3183 | ||
3184 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3185 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3186 | return false; | |
3187 | ||
3188 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3189 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3190 | return false; | |
3191 | ||
3192 | return true; | |
3193 | } | |
3194 | ||
3195 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3196 | { | |
3197 | #if WATCH_GTT | |
3198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3199 | struct drm_i915_gem_object *obj; | |
3200 | int err = 0; | |
3201 | ||
35c20a60 | 3202 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3203 | if (obj->gtt_space == NULL) { |
3204 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3205 | err++; | |
3206 | continue; | |
3207 | } | |
3208 | ||
3209 | if (obj->cache_level != obj->gtt_space->color) { | |
3210 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3211 | i915_gem_obj_ggtt_offset(obj), |
3212 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3213 | obj->cache_level, |
3214 | obj->gtt_space->color); | |
3215 | err++; | |
3216 | continue; | |
3217 | } | |
3218 | ||
3219 | if (!i915_gem_valid_gtt_space(dev, | |
3220 | obj->gtt_space, | |
3221 | obj->cache_level)) { | |
3222 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3223 | i915_gem_obj_ggtt_offset(obj), |
3224 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3225 | obj->cache_level); |
3226 | err++; | |
3227 | continue; | |
3228 | } | |
3229 | } | |
3230 | ||
3231 | WARN_ON(err); | |
3232 | #endif | |
3233 | } | |
3234 | ||
673a394b EA |
3235 | /** |
3236 | * Finds free space in the GTT aperture and binds the object there. | |
3237 | */ | |
262de145 | 3238 | static struct i915_vma * |
07fe0b12 BW |
3239 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3240 | struct i915_address_space *vm, | |
3241 | unsigned alignment, | |
1ec9e26d | 3242 | unsigned flags) |
673a394b | 3243 | { |
05394f39 | 3244 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3245 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3246 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 | 3247 | size_t gtt_max = |
1ec9e26d | 3248 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3249 | struct i915_vma *vma; |
07f73f69 | 3250 | int ret; |
673a394b | 3251 | |
e28f8711 CW |
3252 | fence_size = i915_gem_get_gtt_size(dev, |
3253 | obj->base.size, | |
3254 | obj->tiling_mode); | |
3255 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3256 | obj->base.size, | |
d865110c | 3257 | obj->tiling_mode, true); |
e28f8711 | 3258 | unfenced_alignment = |
d865110c | 3259 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3260 | obj->base.size, |
3261 | obj->tiling_mode, false); | |
a00b10c3 | 3262 | |
673a394b | 3263 | if (alignment == 0) |
1ec9e26d | 3264 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3265 | unfenced_alignment; |
1ec9e26d | 3266 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3267 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3268 | return ERR_PTR(-EINVAL); |
673a394b EA |
3269 | } |
3270 | ||
1ec9e26d | 3271 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3272 | |
654fc607 CW |
3273 | /* If the object is bigger than the entire aperture, reject it early |
3274 | * before evicting everything in a vain attempt to find space. | |
3275 | */ | |
0a9ae0d7 | 3276 | if (obj->base.size > gtt_max) { |
bd9b6a4e | 3277 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb | 3278 | obj->base.size, |
1ec9e26d | 3279 | flags & PIN_MAPPABLE ? "mappable" : "total", |
0a9ae0d7 | 3280 | gtt_max); |
262de145 | 3281 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3282 | } |
3283 | ||
37e680a1 | 3284 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3285 | if (ret) |
262de145 | 3286 | return ERR_PTR(ret); |
6c085a72 | 3287 | |
fbdda6fb CW |
3288 | i915_gem_object_pin_pages(obj); |
3289 | ||
accfef2e | 3290 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3291 | if (IS_ERR(vma)) |
bc6bc15b | 3292 | goto err_unpin; |
2f633156 | 3293 | |
0a9ae0d7 | 3294 | search_free: |
07fe0b12 | 3295 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3296 | size, alignment, |
31e5d7c6 | 3297 | obj->cache_level, 0, gtt_max, |
62347f9e LK |
3298 | DRM_MM_SEARCH_DEFAULT, |
3299 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3300 | if (ret) { |
f6cd1f15 | 3301 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
1ec9e26d | 3302 | obj->cache_level, flags); |
dc9dd7a2 CW |
3303 | if (ret == 0) |
3304 | goto search_free; | |
9731129c | 3305 | |
bc6bc15b | 3306 | goto err_free_vma; |
673a394b | 3307 | } |
2f633156 | 3308 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3309 | obj->cache_level))) { |
2f633156 | 3310 | ret = -EINVAL; |
bc6bc15b | 3311 | goto err_remove_node; |
673a394b EA |
3312 | } |
3313 | ||
74163907 | 3314 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3315 | if (ret) |
bc6bc15b | 3316 | goto err_remove_node; |
673a394b | 3317 | |
35c20a60 | 3318 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3319 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3320 | |
4bd561b3 BW |
3321 | if (i915_is_ggtt(vm)) { |
3322 | bool mappable, fenceable; | |
a00b10c3 | 3323 | |
49987099 DV |
3324 | fenceable = (vma->node.size == fence_size && |
3325 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3326 | |
49987099 DV |
3327 | mappable = (vma->node.start + obj->base.size <= |
3328 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3329 | |
5cacaac7 | 3330 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3331 | } |
75e9e915 | 3332 | |
1ec9e26d | 3333 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
75e9e915 | 3334 | |
1ec9e26d | 3335 | trace_i915_vma_bind(vma, flags); |
8ea99c92 DV |
3336 | vma->bind_vma(vma, obj->cache_level, |
3337 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); | |
3338 | ||
42d6ab48 | 3339 | i915_gem_verify_gtt(dev); |
262de145 | 3340 | return vma; |
2f633156 | 3341 | |
bc6bc15b | 3342 | err_remove_node: |
6286ef9b | 3343 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3344 | err_free_vma: |
2f633156 | 3345 | i915_gem_vma_destroy(vma); |
262de145 | 3346 | vma = ERR_PTR(ret); |
bc6bc15b | 3347 | err_unpin: |
2f633156 | 3348 | i915_gem_object_unpin_pages(obj); |
262de145 | 3349 | return vma; |
673a394b EA |
3350 | } |
3351 | ||
000433b6 | 3352 | bool |
2c22569b CW |
3353 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3354 | bool force) | |
673a394b | 3355 | { |
673a394b EA |
3356 | /* If we don't have a page list set up, then we're not pinned |
3357 | * to GPU, and we can ignore the cache flush because it'll happen | |
3358 | * again at bind time. | |
3359 | */ | |
05394f39 | 3360 | if (obj->pages == NULL) |
000433b6 | 3361 | return false; |
673a394b | 3362 | |
769ce464 ID |
3363 | /* |
3364 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3365 | * marked as wc by the system, or the system is cache-coherent. | |
3366 | */ | |
3367 | if (obj->stolen) | |
000433b6 | 3368 | return false; |
769ce464 | 3369 | |
9c23f7fc CW |
3370 | /* If the GPU is snooping the contents of the CPU cache, |
3371 | * we do not need to manually clear the CPU cache lines. However, | |
3372 | * the caches are only snooped when the render cache is | |
3373 | * flushed/invalidated. As we always have to emit invalidations | |
3374 | * and flushes when moving into and out of the RENDER domain, correct | |
3375 | * snooping behaviour occurs naturally as the result of our domain | |
3376 | * tracking. | |
3377 | */ | |
2c22569b | 3378 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3379 | return false; |
9c23f7fc | 3380 | |
1c5d22f7 | 3381 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3382 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3383 | |
3384 | return true; | |
e47c68e9 EA |
3385 | } |
3386 | ||
3387 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3388 | static void | |
05394f39 | 3389 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3390 | { |
1c5d22f7 CW |
3391 | uint32_t old_write_domain; |
3392 | ||
05394f39 | 3393 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3394 | return; |
3395 | ||
63256ec5 | 3396 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3397 | * to it immediately go to main memory as far as we know, so there's |
3398 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3399 | * |
3400 | * However, we do have to enforce the order so that all writes through | |
3401 | * the GTT land before any writes to the device, such as updates to | |
3402 | * the GATT itself. | |
e47c68e9 | 3403 | */ |
63256ec5 CW |
3404 | wmb(); |
3405 | ||
05394f39 CW |
3406 | old_write_domain = obj->base.write_domain; |
3407 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3408 | |
3409 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3410 | obj->base.read_domains, |
1c5d22f7 | 3411 | old_write_domain); |
e47c68e9 EA |
3412 | } |
3413 | ||
3414 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3415 | static void | |
2c22569b CW |
3416 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3417 | bool force) | |
e47c68e9 | 3418 | { |
1c5d22f7 | 3419 | uint32_t old_write_domain; |
e47c68e9 | 3420 | |
05394f39 | 3421 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3422 | return; |
3423 | ||
000433b6 CW |
3424 | if (i915_gem_clflush_object(obj, force)) |
3425 | i915_gem_chipset_flush(obj->base.dev); | |
3426 | ||
05394f39 CW |
3427 | old_write_domain = obj->base.write_domain; |
3428 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3429 | |
3430 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3431 | obj->base.read_domains, |
1c5d22f7 | 3432 | old_write_domain); |
e47c68e9 EA |
3433 | } |
3434 | ||
2ef7eeaa EA |
3435 | /** |
3436 | * Moves a single object to the GTT read, and possibly write domain. | |
3437 | * | |
3438 | * This function returns when the move is complete, including waiting on | |
3439 | * flushes to occur. | |
3440 | */ | |
79e53945 | 3441 | int |
2021746e | 3442 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3443 | { |
3e31c6c0 | 3444 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3445 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3446 | int ret; |
2ef7eeaa | 3447 | |
02354392 | 3448 | /* Not valid to be called on unbound objects. */ |
9843877d | 3449 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3450 | return -EINVAL; |
3451 | ||
8d7e3de1 CW |
3452 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3453 | return 0; | |
3454 | ||
0201f1ec | 3455 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3456 | if (ret) |
3457 | return ret; | |
3458 | ||
c8725f3d | 3459 | i915_gem_object_retire(obj); |
2c22569b | 3460 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3461 | |
d0a57789 CW |
3462 | /* Serialise direct access to this object with the barriers for |
3463 | * coherent writes from the GPU, by effectively invalidating the | |
3464 | * GTT domain upon first access. | |
3465 | */ | |
3466 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3467 | mb(); | |
3468 | ||
05394f39 CW |
3469 | old_write_domain = obj->base.write_domain; |
3470 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3471 | |
e47c68e9 EA |
3472 | /* It should now be out of any other write domains, and we can update |
3473 | * the domain values for our changes. | |
3474 | */ | |
05394f39 CW |
3475 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3476 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3477 | if (write) { |
05394f39 CW |
3478 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3479 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3480 | obj->dirty = 1; | |
2ef7eeaa EA |
3481 | } |
3482 | ||
1c5d22f7 CW |
3483 | trace_i915_gem_object_change_domain(obj, |
3484 | old_read_domains, | |
3485 | old_write_domain); | |
3486 | ||
8325a09d | 3487 | /* And bump the LRU for this access */ |
ca191b13 | 3488 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3489 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3490 | if (vma) |
3491 | list_move_tail(&vma->mm_list, | |
3492 | &dev_priv->gtt.base.inactive_list); | |
3493 | ||
3494 | } | |
8325a09d | 3495 | |
e47c68e9 EA |
3496 | return 0; |
3497 | } | |
3498 | ||
e4ffd173 CW |
3499 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3500 | enum i915_cache_level cache_level) | |
3501 | { | |
7bddb01f | 3502 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3503 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3504 | int ret; |
3505 | ||
3506 | if (obj->cache_level == cache_level) | |
3507 | return 0; | |
3508 | ||
d7f46fc4 | 3509 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3510 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3511 | return -EBUSY; | |
3512 | } | |
3513 | ||
df6f783a | 3514 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
3089c6f2 | 3515 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
07fe0b12 | 3516 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3517 | if (ret) |
3518 | return ret; | |
3089c6f2 | 3519 | } |
42d6ab48 CW |
3520 | } |
3521 | ||
3089c6f2 | 3522 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3523 | ret = i915_gem_object_finish_gpu(obj); |
3524 | if (ret) | |
3525 | return ret; | |
3526 | ||
3527 | i915_gem_object_finish_gtt(obj); | |
3528 | ||
3529 | /* Before SandyBridge, you could not use tiling or fence | |
3530 | * registers with snooped memory, so relinquish any fences | |
3531 | * currently pointing to our region in the aperture. | |
3532 | */ | |
42d6ab48 | 3533 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3534 | ret = i915_gem_object_put_fence(obj); |
3535 | if (ret) | |
3536 | return ret; | |
3537 | } | |
3538 | ||
6f65e29a | 3539 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3540 | if (drm_mm_node_allocated(&vma->node)) |
3541 | vma->bind_vma(vma, cache_level, | |
3542 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); | |
e4ffd173 CW |
3543 | } |
3544 | ||
2c22569b CW |
3545 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3546 | vma->node.color = cache_level; | |
3547 | obj->cache_level = cache_level; | |
3548 | ||
3549 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3550 | u32 old_read_domains, old_write_domain; |
3551 | ||
3552 | /* If we're coming from LLC cached, then we haven't | |
3553 | * actually been tracking whether the data is in the | |
3554 | * CPU cache or not, since we only allow one bit set | |
3555 | * in obj->write_domain and have been skipping the clflushes. | |
3556 | * Just set it to the CPU cache for now. | |
3557 | */ | |
c8725f3d | 3558 | i915_gem_object_retire(obj); |
e4ffd173 | 3559 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e4ffd173 CW |
3560 | |
3561 | old_read_domains = obj->base.read_domains; | |
3562 | old_write_domain = obj->base.write_domain; | |
3563 | ||
3564 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3565 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3566 | ||
3567 | trace_i915_gem_object_change_domain(obj, | |
3568 | old_read_domains, | |
3569 | old_write_domain); | |
3570 | } | |
3571 | ||
42d6ab48 | 3572 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3573 | return 0; |
3574 | } | |
3575 | ||
199adf40 BW |
3576 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3577 | struct drm_file *file) | |
e6994aee | 3578 | { |
199adf40 | 3579 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3580 | struct drm_i915_gem_object *obj; |
3581 | int ret; | |
3582 | ||
3583 | ret = i915_mutex_lock_interruptible(dev); | |
3584 | if (ret) | |
3585 | return ret; | |
3586 | ||
3587 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3588 | if (&obj->base == NULL) { | |
3589 | ret = -ENOENT; | |
3590 | goto unlock; | |
3591 | } | |
3592 | ||
651d794f CW |
3593 | switch (obj->cache_level) { |
3594 | case I915_CACHE_LLC: | |
3595 | case I915_CACHE_L3_LLC: | |
3596 | args->caching = I915_CACHING_CACHED; | |
3597 | break; | |
3598 | ||
4257d3ba CW |
3599 | case I915_CACHE_WT: |
3600 | args->caching = I915_CACHING_DISPLAY; | |
3601 | break; | |
3602 | ||
651d794f CW |
3603 | default: |
3604 | args->caching = I915_CACHING_NONE; | |
3605 | break; | |
3606 | } | |
e6994aee CW |
3607 | |
3608 | drm_gem_object_unreference(&obj->base); | |
3609 | unlock: | |
3610 | mutex_unlock(&dev->struct_mutex); | |
3611 | return ret; | |
3612 | } | |
3613 | ||
199adf40 BW |
3614 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3615 | struct drm_file *file) | |
e6994aee | 3616 | { |
199adf40 | 3617 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3618 | struct drm_i915_gem_object *obj; |
3619 | enum i915_cache_level level; | |
3620 | int ret; | |
3621 | ||
199adf40 BW |
3622 | switch (args->caching) { |
3623 | case I915_CACHING_NONE: | |
e6994aee CW |
3624 | level = I915_CACHE_NONE; |
3625 | break; | |
199adf40 | 3626 | case I915_CACHING_CACHED: |
e6994aee CW |
3627 | level = I915_CACHE_LLC; |
3628 | break; | |
4257d3ba CW |
3629 | case I915_CACHING_DISPLAY: |
3630 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3631 | break; | |
e6994aee CW |
3632 | default: |
3633 | return -EINVAL; | |
3634 | } | |
3635 | ||
3bc2913e BW |
3636 | ret = i915_mutex_lock_interruptible(dev); |
3637 | if (ret) | |
3638 | return ret; | |
3639 | ||
e6994aee CW |
3640 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3641 | if (&obj->base == NULL) { | |
3642 | ret = -ENOENT; | |
3643 | goto unlock; | |
3644 | } | |
3645 | ||
3646 | ret = i915_gem_object_set_cache_level(obj, level); | |
3647 | ||
3648 | drm_gem_object_unreference(&obj->base); | |
3649 | unlock: | |
3650 | mutex_unlock(&dev->struct_mutex); | |
3651 | return ret; | |
3652 | } | |
3653 | ||
cc98b413 CW |
3654 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3655 | { | |
19656430 OM |
3656 | struct i915_vma *vma; |
3657 | ||
3658 | if (list_empty(&obj->vma_list)) | |
3659 | return false; | |
3660 | ||
3661 | vma = i915_gem_obj_to_ggtt(obj); | |
3662 | if (!vma) | |
3663 | return false; | |
3664 | ||
cc98b413 CW |
3665 | /* There are 3 sources that pin objects: |
3666 | * 1. The display engine (scanouts, sprites, cursors); | |
3667 | * 2. Reservations for execbuffer; | |
3668 | * 3. The user. | |
3669 | * | |
3670 | * We can ignore reservations as we hold the struct_mutex and | |
3671 | * are only called outside of the reservation path. The user | |
3672 | * can only increment pin_count once, and so if after | |
3673 | * subtracting the potential reference by the user, any pin_count | |
3674 | * remains, it must be due to another use by the display engine. | |
3675 | */ | |
19656430 | 3676 | return vma->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3677 | } |
3678 | ||
b9241ea3 | 3679 | /* |
2da3b9b9 CW |
3680 | * Prepare buffer for display plane (scanout, cursors, etc). |
3681 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3682 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3683 | */ |
3684 | int | |
2da3b9b9 CW |
3685 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3686 | u32 alignment, | |
919926ae | 3687 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3688 | { |
2da3b9b9 | 3689 | u32 old_read_domains, old_write_domain; |
19656430 | 3690 | bool was_pin_display; |
b9241ea3 ZW |
3691 | int ret; |
3692 | ||
0be73284 | 3693 | if (pipelined != obj->ring) { |
2911a35b BW |
3694 | ret = i915_gem_object_sync(obj, pipelined); |
3695 | if (ret) | |
b9241ea3 ZW |
3696 | return ret; |
3697 | } | |
3698 | ||
cc98b413 CW |
3699 | /* Mark the pin_display early so that we account for the |
3700 | * display coherency whilst setting up the cache domains. | |
3701 | */ | |
19656430 | 3702 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3703 | obj->pin_display = true; |
3704 | ||
a7ef0640 EA |
3705 | /* The display engine is not coherent with the LLC cache on gen6. As |
3706 | * a result, we make sure that the pinning that is about to occur is | |
3707 | * done with uncached PTEs. This is lowest common denominator for all | |
3708 | * chipsets. | |
3709 | * | |
3710 | * However for gen6+, we could do better by using the GFDT bit instead | |
3711 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3712 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3713 | */ | |
651d794f CW |
3714 | ret = i915_gem_object_set_cache_level(obj, |
3715 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3716 | if (ret) |
cc98b413 | 3717 | goto err_unpin_display; |
a7ef0640 | 3718 | |
2da3b9b9 CW |
3719 | /* As the user may map the buffer once pinned in the display plane |
3720 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3721 | * always use map_and_fenceable for all scanout buffers. | |
3722 | */ | |
1ec9e26d | 3723 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3724 | if (ret) |
cc98b413 | 3725 | goto err_unpin_display; |
2da3b9b9 | 3726 | |
2c22569b | 3727 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3728 | |
2da3b9b9 | 3729 | old_write_domain = obj->base.write_domain; |
05394f39 | 3730 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3731 | |
3732 | /* It should now be out of any other write domains, and we can update | |
3733 | * the domain values for our changes. | |
3734 | */ | |
e5f1d962 | 3735 | obj->base.write_domain = 0; |
05394f39 | 3736 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3737 | |
3738 | trace_i915_gem_object_change_domain(obj, | |
3739 | old_read_domains, | |
2da3b9b9 | 3740 | old_write_domain); |
b9241ea3 ZW |
3741 | |
3742 | return 0; | |
cc98b413 CW |
3743 | |
3744 | err_unpin_display: | |
19656430 OM |
3745 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3746 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
3747 | return ret; |
3748 | } | |
3749 | ||
3750 | void | |
3751 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3752 | { | |
d7f46fc4 | 3753 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3754 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3755 | } |
3756 | ||
85345517 | 3757 | int |
a8198eea | 3758 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3759 | { |
88241785 CW |
3760 | int ret; |
3761 | ||
a8198eea | 3762 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3763 | return 0; |
3764 | ||
0201f1ec | 3765 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3766 | if (ret) |
3767 | return ret; | |
3768 | ||
a8198eea CW |
3769 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3770 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3771 | return 0; |
85345517 CW |
3772 | } |
3773 | ||
e47c68e9 EA |
3774 | /** |
3775 | * Moves a single object to the CPU read, and possibly write domain. | |
3776 | * | |
3777 | * This function returns when the move is complete, including waiting on | |
3778 | * flushes to occur. | |
3779 | */ | |
dabdfe02 | 3780 | int |
919926ae | 3781 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3782 | { |
1c5d22f7 | 3783 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3784 | int ret; |
3785 | ||
8d7e3de1 CW |
3786 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3787 | return 0; | |
3788 | ||
0201f1ec | 3789 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3790 | if (ret) |
3791 | return ret; | |
3792 | ||
c8725f3d | 3793 | i915_gem_object_retire(obj); |
e47c68e9 | 3794 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3795 | |
05394f39 CW |
3796 | old_write_domain = obj->base.write_domain; |
3797 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3798 | |
e47c68e9 | 3799 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3800 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3801 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3802 | |
05394f39 | 3803 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3804 | } |
3805 | ||
3806 | /* It should now be out of any other write domains, and we can update | |
3807 | * the domain values for our changes. | |
3808 | */ | |
05394f39 | 3809 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3810 | |
3811 | /* If we're writing through the CPU, then the GPU read domains will | |
3812 | * need to be invalidated at next use. | |
3813 | */ | |
3814 | if (write) { | |
05394f39 CW |
3815 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3816 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3817 | } |
2ef7eeaa | 3818 | |
1c5d22f7 CW |
3819 | trace_i915_gem_object_change_domain(obj, |
3820 | old_read_domains, | |
3821 | old_write_domain); | |
3822 | ||
2ef7eeaa EA |
3823 | return 0; |
3824 | } | |
3825 | ||
673a394b EA |
3826 | /* Throttle our rendering by waiting until the ring has completed our requests |
3827 | * emitted over 20 msec ago. | |
3828 | * | |
b962442e EA |
3829 | * Note that if we were to use the current jiffies each time around the loop, |
3830 | * we wouldn't escape the function with any frames outstanding if the time to | |
3831 | * render a frame was over 20ms. | |
3832 | * | |
673a394b EA |
3833 | * This should get us reasonable parallelism between CPU and GPU but also |
3834 | * relatively low latency when blocking on a particular request to finish. | |
3835 | */ | |
40a5f0de | 3836 | static int |
f787a5f5 | 3837 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3838 | { |
f787a5f5 CW |
3839 | struct drm_i915_private *dev_priv = dev->dev_private; |
3840 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3841 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3842 | struct drm_i915_gem_request *request; |
3843 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3844 | unsigned reset_counter; |
f787a5f5 CW |
3845 | u32 seqno = 0; |
3846 | int ret; | |
93533c29 | 3847 | |
308887aa DV |
3848 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3849 | if (ret) | |
3850 | return ret; | |
3851 | ||
3852 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3853 | if (ret) | |
3854 | return ret; | |
e110e8d6 | 3855 | |
1c25595f | 3856 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3857 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3858 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3859 | break; | |
40a5f0de | 3860 | |
f787a5f5 CW |
3861 | ring = request->ring; |
3862 | seqno = request->seqno; | |
b962442e | 3863 | } |
f69061be | 3864 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3865 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3866 | |
f787a5f5 CW |
3867 | if (seqno == 0) |
3868 | return 0; | |
2bc43b5c | 3869 | |
b29c19b6 | 3870 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
3871 | if (ret == 0) |
3872 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3873 | |
3874 | return ret; | |
3875 | } | |
3876 | ||
673a394b | 3877 | int |
05394f39 | 3878 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3879 | struct i915_address_space *vm, |
05394f39 | 3880 | uint32_t alignment, |
1ec9e26d | 3881 | unsigned flags) |
673a394b | 3882 | { |
6e7186af | 3883 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 3884 | struct i915_vma *vma; |
673a394b EA |
3885 | int ret; |
3886 | ||
6e7186af BW |
3887 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
3888 | return -ENODEV; | |
3889 | ||
bf3d149b | 3890 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 3891 | return -EINVAL; |
07fe0b12 BW |
3892 | |
3893 | vma = i915_gem_obj_to_vma(obj, vm); | |
07fe0b12 | 3894 | if (vma) { |
d7f46fc4 BW |
3895 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3896 | return -EBUSY; | |
3897 | ||
07fe0b12 BW |
3898 | if ((alignment && |
3899 | vma->node.start & (alignment - 1)) || | |
1ec9e26d | 3900 | (flags & PIN_MAPPABLE && !obj->map_and_fenceable)) { |
d7f46fc4 | 3901 | WARN(vma->pin_count, |
ae7d49d8 | 3902 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3903 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3904 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3905 | i915_gem_obj_offset(obj, vm), alignment, |
1ec9e26d | 3906 | flags & PIN_MAPPABLE, |
05394f39 | 3907 | obj->map_and_fenceable); |
07fe0b12 | 3908 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3909 | if (ret) |
3910 | return ret; | |
8ea99c92 DV |
3911 | |
3912 | vma = NULL; | |
ac0c6b5a CW |
3913 | } |
3914 | } | |
3915 | ||
8ea99c92 | 3916 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
3917 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
3918 | if (IS_ERR(vma)) | |
3919 | return PTR_ERR(vma); | |
22c344e9 | 3920 | } |
76446cac | 3921 | |
8ea99c92 DV |
3922 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
3923 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
74898d7e | 3924 | |
8ea99c92 | 3925 | vma->pin_count++; |
1ec9e26d DV |
3926 | if (flags & PIN_MAPPABLE) |
3927 | obj->pin_mappable |= true; | |
673a394b EA |
3928 | |
3929 | return 0; | |
3930 | } | |
3931 | ||
3932 | void | |
d7f46fc4 | 3933 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3934 | { |
d7f46fc4 | 3935 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 3936 | |
d7f46fc4 BW |
3937 | BUG_ON(!vma); |
3938 | BUG_ON(vma->pin_count == 0); | |
3939 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
3940 | ||
3941 | if (--vma->pin_count == 0) | |
6299f992 | 3942 | obj->pin_mappable = false; |
673a394b EA |
3943 | } |
3944 | ||
d8ffa60b DV |
3945 | bool |
3946 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
3947 | { | |
3948 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
3949 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
3950 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
3951 | ||
3952 | WARN_ON(!ggtt_vma || | |
3953 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
3954 | ggtt_vma->pin_count); | |
3955 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
3956 | return true; | |
3957 | } else | |
3958 | return false; | |
3959 | } | |
3960 | ||
3961 | void | |
3962 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
3963 | { | |
3964 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
3965 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
3966 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
3967 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
3968 | } | |
3969 | } | |
3970 | ||
673a394b EA |
3971 | int |
3972 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3973 | struct drm_file *file) |
673a394b EA |
3974 | { |
3975 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3976 | struct drm_i915_gem_object *obj; |
673a394b EA |
3977 | int ret; |
3978 | ||
02f6bccc DV |
3979 | if (INTEL_INFO(dev)->gen >= 6) |
3980 | return -ENODEV; | |
3981 | ||
1d7cfea1 CW |
3982 | ret = i915_mutex_lock_interruptible(dev); |
3983 | if (ret) | |
3984 | return ret; | |
673a394b | 3985 | |
05394f39 | 3986 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3987 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3988 | ret = -ENOENT; |
3989 | goto unlock; | |
673a394b | 3990 | } |
673a394b | 3991 | |
05394f39 | 3992 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 3993 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
8c99e57d | 3994 | ret = -EFAULT; |
1d7cfea1 | 3995 | goto out; |
3ef94daa CW |
3996 | } |
3997 | ||
05394f39 | 3998 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
bd9b6a4e | 3999 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4000 | args->handle); |
1d7cfea1 CW |
4001 | ret = -EINVAL; |
4002 | goto out; | |
79e53945 JB |
4003 | } |
4004 | ||
aa5f8021 DV |
4005 | if (obj->user_pin_count == ULONG_MAX) { |
4006 | ret = -EBUSY; | |
4007 | goto out; | |
4008 | } | |
4009 | ||
93be8788 | 4010 | if (obj->user_pin_count == 0) { |
1ec9e26d | 4011 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
1d7cfea1 CW |
4012 | if (ret) |
4013 | goto out; | |
673a394b EA |
4014 | } |
4015 | ||
93be8788 CW |
4016 | obj->user_pin_count++; |
4017 | obj->pin_filp = file; | |
4018 | ||
f343c5f6 | 4019 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 4020 | out: |
05394f39 | 4021 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4022 | unlock: |
673a394b | 4023 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4024 | return ret; |
673a394b EA |
4025 | } |
4026 | ||
4027 | int | |
4028 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4029 | struct drm_file *file) |
673a394b EA |
4030 | { |
4031 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4032 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4033 | int ret; |
673a394b | 4034 | |
1d7cfea1 CW |
4035 | ret = i915_mutex_lock_interruptible(dev); |
4036 | if (ret) | |
4037 | return ret; | |
673a394b | 4038 | |
05394f39 | 4039 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4040 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4041 | ret = -ENOENT; |
4042 | goto unlock; | |
673a394b | 4043 | } |
76c1dec1 | 4044 | |
05394f39 | 4045 | if (obj->pin_filp != file) { |
bd9b6a4e | 4046 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
79e53945 | 4047 | args->handle); |
1d7cfea1 CW |
4048 | ret = -EINVAL; |
4049 | goto out; | |
79e53945 | 4050 | } |
05394f39 CW |
4051 | obj->user_pin_count--; |
4052 | if (obj->user_pin_count == 0) { | |
4053 | obj->pin_filp = NULL; | |
d7f46fc4 | 4054 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 4055 | } |
673a394b | 4056 | |
1d7cfea1 | 4057 | out: |
05394f39 | 4058 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4059 | unlock: |
673a394b | 4060 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4061 | return ret; |
673a394b EA |
4062 | } |
4063 | ||
4064 | int | |
4065 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4066 | struct drm_file *file) |
673a394b EA |
4067 | { |
4068 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4069 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4070 | int ret; |
4071 | ||
76c1dec1 | 4072 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4073 | if (ret) |
76c1dec1 | 4074 | return ret; |
673a394b | 4075 | |
05394f39 | 4076 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4077 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4078 | ret = -ENOENT; |
4079 | goto unlock; | |
673a394b | 4080 | } |
d1b851fc | 4081 | |
0be555b6 CW |
4082 | /* Count all active objects as busy, even if they are currently not used |
4083 | * by the gpu. Users of this interface expect objects to eventually | |
4084 | * become non-busy without any further actions, therefore emit any | |
4085 | * necessary flushes here. | |
c4de0a5d | 4086 | */ |
30dfebf3 | 4087 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4088 | |
30dfebf3 | 4089 | args->busy = obj->active; |
e9808edd CW |
4090 | if (obj->ring) { |
4091 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4092 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4093 | } | |
673a394b | 4094 | |
05394f39 | 4095 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4096 | unlock: |
673a394b | 4097 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4098 | return ret; |
673a394b EA |
4099 | } |
4100 | ||
4101 | int | |
4102 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4103 | struct drm_file *file_priv) | |
4104 | { | |
0206e353 | 4105 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4106 | } |
4107 | ||
3ef94daa CW |
4108 | int |
4109 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4110 | struct drm_file *file_priv) | |
4111 | { | |
4112 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4113 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4114 | int ret; |
3ef94daa CW |
4115 | |
4116 | switch (args->madv) { | |
4117 | case I915_MADV_DONTNEED: | |
4118 | case I915_MADV_WILLNEED: | |
4119 | break; | |
4120 | default: | |
4121 | return -EINVAL; | |
4122 | } | |
4123 | ||
1d7cfea1 CW |
4124 | ret = i915_mutex_lock_interruptible(dev); |
4125 | if (ret) | |
4126 | return ret; | |
4127 | ||
05394f39 | 4128 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4129 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4130 | ret = -ENOENT; |
4131 | goto unlock; | |
3ef94daa | 4132 | } |
3ef94daa | 4133 | |
d7f46fc4 | 4134 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4135 | ret = -EINVAL; |
4136 | goto out; | |
3ef94daa CW |
4137 | } |
4138 | ||
05394f39 CW |
4139 | if (obj->madv != __I915_MADV_PURGED) |
4140 | obj->madv = args->madv; | |
3ef94daa | 4141 | |
6c085a72 CW |
4142 | /* if the object is no longer attached, discard its backing storage */ |
4143 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4144 | i915_gem_object_truncate(obj); |
4145 | ||
05394f39 | 4146 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4147 | |
1d7cfea1 | 4148 | out: |
05394f39 | 4149 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4150 | unlock: |
3ef94daa | 4151 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4152 | return ret; |
3ef94daa CW |
4153 | } |
4154 | ||
37e680a1 CW |
4155 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4156 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4157 | { |
35c20a60 | 4158 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4159 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4160 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4161 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4162 | |
37e680a1 CW |
4163 | obj->ops = ops; |
4164 | ||
0327d6ba CW |
4165 | obj->fence_reg = I915_FENCE_REG_NONE; |
4166 | obj->madv = I915_MADV_WILLNEED; | |
4167 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4168 | obj->map_and_fenceable = true; | |
4169 | ||
4170 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4171 | } | |
4172 | ||
37e680a1 CW |
4173 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4174 | .get_pages = i915_gem_object_get_pages_gtt, | |
4175 | .put_pages = i915_gem_object_put_pages_gtt, | |
4176 | }; | |
4177 | ||
05394f39 CW |
4178 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4179 | size_t size) | |
ac52bc56 | 4180 | { |
c397b908 | 4181 | struct drm_i915_gem_object *obj; |
5949eac4 | 4182 | struct address_space *mapping; |
1a240d4d | 4183 | gfp_t mask; |
ac52bc56 | 4184 | |
42dcedd4 | 4185 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4186 | if (obj == NULL) |
4187 | return NULL; | |
673a394b | 4188 | |
c397b908 | 4189 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4190 | i915_gem_object_free(obj); |
c397b908 DV |
4191 | return NULL; |
4192 | } | |
673a394b | 4193 | |
bed1ea95 CW |
4194 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4195 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4196 | /* 965gm cannot relocate objects above 4GiB. */ | |
4197 | mask &= ~__GFP_HIGHMEM; | |
4198 | mask |= __GFP_DMA32; | |
4199 | } | |
4200 | ||
496ad9aa | 4201 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4202 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4203 | |
37e680a1 | 4204 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4205 | |
c397b908 DV |
4206 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4207 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4208 | |
3d29b842 ED |
4209 | if (HAS_LLC(dev)) { |
4210 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4211 | * cache) for about a 10% performance improvement |
4212 | * compared to uncached. Graphics requests other than | |
4213 | * display scanout are coherent with the CPU in | |
4214 | * accessing this cache. This means in this mode we | |
4215 | * don't need to clflush on the CPU side, and on the | |
4216 | * GPU side we only need to flush internal caches to | |
4217 | * get data visible to the CPU. | |
4218 | * | |
4219 | * However, we maintain the display planes as UC, and so | |
4220 | * need to rebind when first used as such. | |
4221 | */ | |
4222 | obj->cache_level = I915_CACHE_LLC; | |
4223 | } else | |
4224 | obj->cache_level = I915_CACHE_NONE; | |
4225 | ||
d861e338 DV |
4226 | trace_i915_gem_object_create(obj); |
4227 | ||
05394f39 | 4228 | return obj; |
c397b908 DV |
4229 | } |
4230 | ||
1488fc08 | 4231 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4232 | { |
1488fc08 | 4233 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4234 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4235 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4236 | struct i915_vma *vma, *next; |
673a394b | 4237 | |
f65c9168 PZ |
4238 | intel_runtime_pm_get(dev_priv); |
4239 | ||
26e12f89 CW |
4240 | trace_i915_gem_object_destroy(obj); |
4241 | ||
1488fc08 CW |
4242 | if (obj->phys_obj) |
4243 | i915_gem_detach_phys_object(dev, obj); | |
4244 | ||
07fe0b12 | 4245 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4246 | int ret; |
4247 | ||
4248 | vma->pin_count = 0; | |
4249 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4250 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4251 | bool was_interruptible; | |
1488fc08 | 4252 | |
07fe0b12 BW |
4253 | was_interruptible = dev_priv->mm.interruptible; |
4254 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4255 | |
07fe0b12 | 4256 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4257 | |
07fe0b12 BW |
4258 | dev_priv->mm.interruptible = was_interruptible; |
4259 | } | |
1488fc08 CW |
4260 | } |
4261 | ||
1d64ae71 BW |
4262 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4263 | * before progressing. */ | |
4264 | if (obj->stolen) | |
4265 | i915_gem_object_unpin_pages(obj); | |
4266 | ||
401c29f6 BW |
4267 | if (WARN_ON(obj->pages_pin_count)) |
4268 | obj->pages_pin_count = 0; | |
37e680a1 | 4269 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4270 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4271 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4272 | |
9da3da66 CW |
4273 | BUG_ON(obj->pages); |
4274 | ||
2f745ad3 CW |
4275 | if (obj->base.import_attach) |
4276 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4277 | |
5cc9ed4b CW |
4278 | if (obj->ops->release) |
4279 | obj->ops->release(obj); | |
4280 | ||
05394f39 CW |
4281 | drm_gem_object_release(&obj->base); |
4282 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4283 | |
05394f39 | 4284 | kfree(obj->bit_17); |
42dcedd4 | 4285 | i915_gem_object_free(obj); |
f65c9168 PZ |
4286 | |
4287 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4288 | } |
4289 | ||
e656a6cb | 4290 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4291 | struct i915_address_space *vm) |
e656a6cb DV |
4292 | { |
4293 | struct i915_vma *vma; | |
4294 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4295 | if (vma->vm == vm) | |
4296 | return vma; | |
4297 | ||
4298 | return NULL; | |
4299 | } | |
4300 | ||
2f633156 BW |
4301 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4302 | { | |
4303 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4304 | |
4305 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4306 | if (!list_empty(&vma->exec_list)) | |
4307 | return; | |
4308 | ||
8b9c2b94 | 4309 | list_del(&vma->vma_link); |
b93dab6e | 4310 | |
2f633156 BW |
4311 | kfree(vma); |
4312 | } | |
4313 | ||
e3efda49 CW |
4314 | static void |
4315 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4316 | { | |
4317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4318 | struct intel_ring_buffer *ring; | |
4319 | int i; | |
4320 | ||
4321 | for_each_ring(ring, dev_priv, i) | |
4322 | intel_stop_ring_buffer(ring); | |
4323 | } | |
4324 | ||
29105ccc | 4325 | int |
45c5f202 | 4326 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4327 | { |
3e31c6c0 | 4328 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4329 | int ret = 0; |
28dfe52a | 4330 | |
45c5f202 | 4331 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4332 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4333 | goto err; |
28dfe52a | 4334 | |
b2da9fe5 | 4335 | ret = i915_gpu_idle(dev); |
f7403347 | 4336 | if (ret) |
45c5f202 | 4337 | goto err; |
f7403347 | 4338 | |
b2da9fe5 | 4339 | i915_gem_retire_requests(dev); |
673a394b | 4340 | |
29105ccc | 4341 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4342 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4343 | i915_gem_evict_everything(dev); |
29105ccc | 4344 | |
29105ccc | 4345 | i915_kernel_lost_context(dev); |
e3efda49 | 4346 | i915_gem_stop_ringbuffers(dev); |
29105ccc | 4347 | |
45c5f202 CW |
4348 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4349 | * We need to replace this with a semaphore, or something. | |
4350 | * And not confound ums.mm_suspended! | |
4351 | */ | |
4352 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4353 | DRIVER_MODESET); | |
4354 | mutex_unlock(&dev->struct_mutex); | |
4355 | ||
4356 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4357 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
b29c19b6 | 4358 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4359 | |
673a394b | 4360 | return 0; |
45c5f202 CW |
4361 | |
4362 | err: | |
4363 | mutex_unlock(&dev->struct_mutex); | |
4364 | return ret; | |
673a394b EA |
4365 | } |
4366 | ||
c3787e2e | 4367 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice) |
b9524a1e | 4368 | { |
c3787e2e | 4369 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4370 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4371 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4372 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4373 | int i, ret; |
b9524a1e | 4374 | |
040d2baa | 4375 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4376 | return 0; |
b9524a1e | 4377 | |
c3787e2e BW |
4378 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4379 | if (ret) | |
4380 | return ret; | |
b9524a1e | 4381 | |
c3787e2e BW |
4382 | /* |
4383 | * Note: We do not worry about the concurrent register cacheline hang | |
4384 | * here because no other code should access these registers other than | |
4385 | * at initialization time. | |
4386 | */ | |
b9524a1e | 4387 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4388 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4389 | intel_ring_emit(ring, reg_base + i); | |
4390 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4391 | } |
4392 | ||
c3787e2e | 4393 | intel_ring_advance(ring); |
b9524a1e | 4394 | |
c3787e2e | 4395 | return ret; |
b9524a1e BW |
4396 | } |
4397 | ||
f691e2f4 DV |
4398 | void i915_gem_init_swizzling(struct drm_device *dev) |
4399 | { | |
3e31c6c0 | 4400 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4401 | |
11782b02 | 4402 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4403 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4404 | return; | |
4405 | ||
4406 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4407 | DISP_TILE_SURFACE_SWIZZLING); | |
4408 | ||
11782b02 DV |
4409 | if (IS_GEN5(dev)) |
4410 | return; | |
4411 | ||
f691e2f4 DV |
4412 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4413 | if (IS_GEN6(dev)) | |
6b26c86d | 4414 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4415 | else if (IS_GEN7(dev)) |
6b26c86d | 4416 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4417 | else if (IS_GEN8(dev)) |
4418 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4419 | else |
4420 | BUG(); | |
f691e2f4 | 4421 | } |
e21af88d | 4422 | |
67b1b571 CW |
4423 | static bool |
4424 | intel_enable_blt(struct drm_device *dev) | |
4425 | { | |
4426 | if (!HAS_BLT(dev)) | |
4427 | return false; | |
4428 | ||
4429 | /* The blitter was dysfunctional on early prototypes */ | |
4430 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4431 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4432 | " graphics performance will be degraded.\n"); | |
4433 | return false; | |
4434 | } | |
4435 | ||
4436 | return true; | |
4437 | } | |
4438 | ||
4fc7c971 | 4439 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4440 | { |
4fc7c971 | 4441 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4442 | int ret; |
68f95ba9 | 4443 | |
5c1143bb | 4444 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4445 | if (ret) |
b6913e4b | 4446 | return ret; |
68f95ba9 CW |
4447 | |
4448 | if (HAS_BSD(dev)) { | |
5c1143bb | 4449 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4450 | if (ret) |
4451 | goto cleanup_render_ring; | |
d1b851fc | 4452 | } |
68f95ba9 | 4453 | |
67b1b571 | 4454 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4455 | ret = intel_init_blt_ring_buffer(dev); |
4456 | if (ret) | |
4457 | goto cleanup_bsd_ring; | |
4458 | } | |
4459 | ||
9a8a2213 BW |
4460 | if (HAS_VEBOX(dev)) { |
4461 | ret = intel_init_vebox_ring_buffer(dev); | |
4462 | if (ret) | |
4463 | goto cleanup_blt_ring; | |
4464 | } | |
4465 | ||
845f74a7 ZY |
4466 | if (HAS_BSD2(dev)) { |
4467 | ret = intel_init_bsd2_ring_buffer(dev); | |
4468 | if (ret) | |
4469 | goto cleanup_vebox_ring; | |
4470 | } | |
9a8a2213 | 4471 | |
99433931 | 4472 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4473 | if (ret) |
845f74a7 | 4474 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4475 | |
4476 | return 0; | |
4477 | ||
845f74a7 ZY |
4478 | cleanup_bsd2_ring: |
4479 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4480 | cleanup_vebox_ring: |
4481 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4482 | cleanup_blt_ring: |
4483 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4484 | cleanup_bsd_ring: | |
4485 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4486 | cleanup_render_ring: | |
4487 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4488 | ||
4489 | return ret; | |
4490 | } | |
4491 | ||
4492 | int | |
4493 | i915_gem_init_hw(struct drm_device *dev) | |
4494 | { | |
3e31c6c0 | 4495 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4496 | int ret, i; |
4fc7c971 BW |
4497 | |
4498 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4499 | return -EIO; | |
4500 | ||
59124506 | 4501 | if (dev_priv->ellc_size) |
05e21cc4 | 4502 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4503 | |
0bf21347 VS |
4504 | if (IS_HASWELL(dev)) |
4505 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4506 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4507 | |
88a2b2a3 | 4508 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4509 | if (IS_IVYBRIDGE(dev)) { |
4510 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4511 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4512 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4513 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4514 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4515 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4516 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4517 | } | |
88a2b2a3 BW |
4518 | } |
4519 | ||
4fc7c971 BW |
4520 | i915_gem_init_swizzling(dev); |
4521 | ||
4522 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4523 | if (ret) |
4524 | return ret; | |
4525 | ||
c3787e2e BW |
4526 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4527 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4528 | ||
254f965c | 4529 | /* |
2fa48d8d BW |
4530 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4531 | * default context switch however is something we'd like to do after | |
4532 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4533 | * goes with our code better). Context switching requires rings (for | |
4534 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4535 | */ |
2fa48d8d | 4536 | ret = i915_gem_context_enable(dev_priv); |
60990320 | 4537 | if (ret && ret != -EIO) { |
2fa48d8d | 4538 | DRM_ERROR("Context enable failed %d\n", ret); |
60990320 | 4539 | i915_gem_cleanup_ringbuffer(dev); |
b7c36d25 | 4540 | } |
e21af88d | 4541 | |
2fa48d8d | 4542 | return ret; |
8187a2b7 ZN |
4543 | } |
4544 | ||
1070a42b CW |
4545 | int i915_gem_init(struct drm_device *dev) |
4546 | { | |
4547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4548 | int ret; |
4549 | ||
1070a42b | 4550 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4551 | |
4552 | if (IS_VALLEYVIEW(dev)) { | |
4553 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4554 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4555 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4556 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4557 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4558 | } | |
4559 | ||
5cc9ed4b | 4560 | i915_gem_init_userptr(dev); |
d7e5008f | 4561 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4562 | |
2fa48d8d | 4563 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4564 | if (ret) { |
4565 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4566 | return ret; |
e3848694 | 4567 | } |
2fa48d8d | 4568 | |
1070a42b | 4569 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4570 | if (ret == -EIO) { |
4571 | /* Allow ring initialisation to fail by marking the GPU as | |
4572 | * wedged. But we only want to do this where the GPU is angry, | |
4573 | * for all other failure, such as an allocation failure, bail. | |
4574 | */ | |
4575 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4576 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4577 | ret = 0; | |
1070a42b | 4578 | } |
60990320 | 4579 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4580 | |
53ca26ca DV |
4581 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4582 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4583 | dev_priv->dri1.allow_batchbuffer = 1; | |
60990320 | 4584 | return ret; |
1070a42b CW |
4585 | } |
4586 | ||
8187a2b7 ZN |
4587 | void |
4588 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4589 | { | |
3e31c6c0 | 4590 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4591 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4592 | int i; |
8187a2b7 | 4593 | |
b4519513 CW |
4594 | for_each_ring(ring, dev_priv, i) |
4595 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4596 | } |
4597 | ||
673a394b EA |
4598 | int |
4599 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4600 | struct drm_file *file_priv) | |
4601 | { | |
db1b76ca | 4602 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4603 | int ret; |
673a394b | 4604 | |
79e53945 JB |
4605 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4606 | return 0; | |
4607 | ||
1f83fee0 | 4608 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4609 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4610 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4611 | } |
4612 | ||
673a394b | 4613 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4614 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4615 | |
f691e2f4 | 4616 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4617 | if (ret != 0) { |
4618 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4619 | return ret; |
d816f6ac | 4620 | } |
9bb2d6f9 | 4621 | |
5cef07e1 | 4622 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
dbb19d30 | 4623 | |
bb0f1b5c | 4624 | ret = drm_irq_install(dev, dev->pdev->irq); |
5f35308b CW |
4625 | if (ret) |
4626 | goto cleanup_ringbuffer; | |
e090c53b | 4627 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4628 | |
673a394b | 4629 | return 0; |
5f35308b CW |
4630 | |
4631 | cleanup_ringbuffer: | |
5f35308b | 4632 | i915_gem_cleanup_ringbuffer(dev); |
db1b76ca | 4633 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4634 | mutex_unlock(&dev->struct_mutex); |
4635 | ||
4636 | return ret; | |
673a394b EA |
4637 | } |
4638 | ||
4639 | int | |
4640 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4641 | struct drm_file *file_priv) | |
4642 | { | |
79e53945 JB |
4643 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4644 | return 0; | |
4645 | ||
e090c53b | 4646 | mutex_lock(&dev->struct_mutex); |
dbb19d30 | 4647 | drm_irq_uninstall(dev); |
e090c53b | 4648 | mutex_unlock(&dev->struct_mutex); |
db1b76ca | 4649 | |
45c5f202 | 4650 | return i915_gem_suspend(dev); |
673a394b EA |
4651 | } |
4652 | ||
4653 | void | |
4654 | i915_gem_lastclose(struct drm_device *dev) | |
4655 | { | |
4656 | int ret; | |
673a394b | 4657 | |
e806b495 EA |
4658 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4659 | return; | |
4660 | ||
45c5f202 | 4661 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4662 | if (ret) |
4663 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4664 | } |
4665 | ||
64193406 CW |
4666 | static void |
4667 | init_ring_lists(struct intel_ring_buffer *ring) | |
4668 | { | |
4669 | INIT_LIST_HEAD(&ring->active_list); | |
4670 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4671 | } |
4672 | ||
7e0d96bc BW |
4673 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4674 | struct i915_address_space *vm) | |
fc8c067e | 4675 | { |
7e0d96bc BW |
4676 | if (!i915_is_ggtt(vm)) |
4677 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4678 | vm->dev = dev_priv->dev; |
4679 | INIT_LIST_HEAD(&vm->active_list); | |
4680 | INIT_LIST_HEAD(&vm->inactive_list); | |
4681 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4682 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4683 | } |
4684 | ||
673a394b EA |
4685 | void |
4686 | i915_gem_load(struct drm_device *dev) | |
4687 | { | |
3e31c6c0 | 4688 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4689 | int i; |
4690 | ||
4691 | dev_priv->slab = | |
4692 | kmem_cache_create("i915_gem_object", | |
4693 | sizeof(struct drm_i915_gem_object), 0, | |
4694 | SLAB_HWCACHE_ALIGN, | |
4695 | NULL); | |
673a394b | 4696 | |
fc8c067e BW |
4697 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4698 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4699 | ||
a33afea5 | 4700 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4701 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4702 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4703 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4704 | for (i = 0; i < I915_NUM_RINGS; i++) |
4705 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4706 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4707 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4708 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4709 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4710 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4711 | i915_gem_idle_work_handler); | |
1f83fee0 | 4712 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4713 | |
94400120 DA |
4714 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4715 | if (IS_GEN3(dev)) { | |
50743298 DV |
4716 | I915_WRITE(MI_ARB_STATE, |
4717 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4718 | } |
4719 | ||
72bfa19c CW |
4720 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4721 | ||
de151cf6 | 4722 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4723 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4724 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4725 | |
42b5aeab VS |
4726 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4727 | dev_priv->num_fence_regs = 32; | |
4728 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4729 | dev_priv->num_fence_regs = 16; |
4730 | else | |
4731 | dev_priv->num_fence_regs = 8; | |
4732 | ||
b5aa8a0f | 4733 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4734 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4735 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4736 | |
673a394b | 4737 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4738 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4739 | |
ce453d81 CW |
4740 | dev_priv->mm.interruptible = true; |
4741 | ||
ceabbba5 CW |
4742 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
4743 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
4744 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
4745 | register_shrinker(&dev_priv->mm.shrinker); | |
673a394b | 4746 | } |
71acb5eb DA |
4747 | |
4748 | /* | |
4749 | * Create a physically contiguous memory object for this object | |
4750 | * e.g. for cursor + overlay regs | |
4751 | */ | |
995b6762 CW |
4752 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4753 | int id, int size, int align) | |
71acb5eb | 4754 | { |
3e31c6c0 | 4755 | struct drm_i915_private *dev_priv = dev->dev_private; |
71acb5eb DA |
4756 | struct drm_i915_gem_phys_object *phys_obj; |
4757 | int ret; | |
4758 | ||
4759 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4760 | return 0; | |
4761 | ||
b14c5679 | 4762 | phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL); |
71acb5eb DA |
4763 | if (!phys_obj) |
4764 | return -ENOMEM; | |
4765 | ||
4766 | phys_obj->id = id; | |
4767 | ||
6eeefaf3 | 4768 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4769 | if (!phys_obj->handle) { |
4770 | ret = -ENOMEM; | |
4771 | goto kfree_obj; | |
4772 | } | |
4773 | #ifdef CONFIG_X86 | |
4774 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4775 | #endif | |
4776 | ||
4777 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4778 | ||
4779 | return 0; | |
4780 | kfree_obj: | |
9a298b2a | 4781 | kfree(phys_obj); |
71acb5eb DA |
4782 | return ret; |
4783 | } | |
4784 | ||
995b6762 | 4785 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb | 4786 | { |
3e31c6c0 | 4787 | struct drm_i915_private *dev_priv = dev->dev_private; |
71acb5eb DA |
4788 | struct drm_i915_gem_phys_object *phys_obj; |
4789 | ||
4790 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4791 | return; | |
4792 | ||
4793 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4794 | if (phys_obj->cur_obj) { | |
4795 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4796 | } | |
4797 | ||
4798 | #ifdef CONFIG_X86 | |
4799 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4800 | #endif | |
4801 | drm_pci_free(dev, phys_obj->handle); | |
4802 | kfree(phys_obj); | |
4803 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4804 | } | |
4805 | ||
4806 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4807 | { | |
4808 | int i; | |
4809 | ||
260883c8 | 4810 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4811 | i915_gem_free_phys_object(dev, i); |
4812 | } | |
4813 | ||
4814 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4815 | struct drm_i915_gem_object *obj) |
71acb5eb | 4816 | { |
496ad9aa | 4817 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4818 | char *vaddr; |
71acb5eb | 4819 | int i; |
71acb5eb DA |
4820 | int page_count; |
4821 | ||
05394f39 | 4822 | if (!obj->phys_obj) |
71acb5eb | 4823 | return; |
05394f39 | 4824 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4825 | |
05394f39 | 4826 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4827 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4828 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4829 | if (!IS_ERR(page)) { |
4830 | char *dst = kmap_atomic(page); | |
4831 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4832 | kunmap_atomic(dst); | |
4833 | ||
4834 | drm_clflush_pages(&page, 1); | |
4835 | ||
4836 | set_page_dirty(page); | |
4837 | mark_page_accessed(page); | |
4838 | page_cache_release(page); | |
4839 | } | |
71acb5eb | 4840 | } |
e76e9aeb | 4841 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4842 | |
05394f39 CW |
4843 | obj->phys_obj->cur_obj = NULL; |
4844 | obj->phys_obj = NULL; | |
71acb5eb DA |
4845 | } |
4846 | ||
4847 | int | |
4848 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4849 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4850 | int id, |
4851 | int align) | |
71acb5eb | 4852 | { |
496ad9aa | 4853 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
3e31c6c0 | 4854 | struct drm_i915_private *dev_priv = dev->dev_private; |
71acb5eb DA |
4855 | int ret = 0; |
4856 | int page_count; | |
4857 | int i; | |
4858 | ||
4859 | if (id > I915_MAX_PHYS_OBJECT) | |
4860 | return -EINVAL; | |
4861 | ||
05394f39 CW |
4862 | if (obj->phys_obj) { |
4863 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4864 | return 0; |
4865 | i915_gem_detach_phys_object(dev, obj); | |
4866 | } | |
4867 | ||
71acb5eb DA |
4868 | /* create a new object */ |
4869 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4870 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4871 | obj->base.size, align); |
71acb5eb | 4872 | if (ret) { |
05394f39 CW |
4873 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4874 | id, obj->base.size); | |
e5281ccd | 4875 | return ret; |
71acb5eb DA |
4876 | } |
4877 | } | |
4878 | ||
4879 | /* bind to the object */ | |
05394f39 CW |
4880 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4881 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4882 | |
05394f39 | 4883 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4884 | |
4885 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4886 | struct page *page; |
4887 | char *dst, *src; | |
4888 | ||
5949eac4 | 4889 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4890 | if (IS_ERR(page)) |
4891 | return PTR_ERR(page); | |
71acb5eb | 4892 | |
ff75b9bc | 4893 | src = kmap_atomic(page); |
05394f39 | 4894 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4895 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4896 | kunmap_atomic(src); |
71acb5eb | 4897 | |
e5281ccd CW |
4898 | mark_page_accessed(page); |
4899 | page_cache_release(page); | |
4900 | } | |
d78b47b9 | 4901 | |
71acb5eb | 4902 | return 0; |
71acb5eb DA |
4903 | } |
4904 | ||
4905 | static int | |
05394f39 CW |
4906 | i915_gem_phys_pwrite(struct drm_device *dev, |
4907 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4908 | struct drm_i915_gem_pwrite *args, |
4909 | struct drm_file *file_priv) | |
4910 | { | |
05394f39 | 4911 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4912 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4913 | |
b47b30cc CW |
4914 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4915 | unsigned long unwritten; | |
4916 | ||
4917 | /* The physical object once assigned is fixed for the lifetime | |
4918 | * of the obj, so we can safely drop the lock and continue | |
4919 | * to access vaddr. | |
4920 | */ | |
4921 | mutex_unlock(&dev->struct_mutex); | |
4922 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4923 | mutex_lock(&dev->struct_mutex); | |
4924 | if (unwritten) | |
4925 | return -EFAULT; | |
4926 | } | |
71acb5eb | 4927 | |
e76e9aeb | 4928 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4929 | return 0; |
4930 | } | |
b962442e | 4931 | |
f787a5f5 | 4932 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4933 | { |
f787a5f5 | 4934 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4935 | |
b29c19b6 CW |
4936 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4937 | ||
b962442e EA |
4938 | /* Clean up our request list when the client is going away, so that |
4939 | * later retire_requests won't dereference our soon-to-be-gone | |
4940 | * file_priv. | |
4941 | */ | |
1c25595f | 4942 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4943 | while (!list_empty(&file_priv->mm.request_list)) { |
4944 | struct drm_i915_gem_request *request; | |
4945 | ||
4946 | request = list_first_entry(&file_priv->mm.request_list, | |
4947 | struct drm_i915_gem_request, | |
4948 | client_list); | |
4949 | list_del(&request->client_list); | |
4950 | request->file_priv = NULL; | |
4951 | } | |
1c25595f | 4952 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4953 | } |
31169714 | 4954 | |
b29c19b6 CW |
4955 | static void |
4956 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
4957 | { | |
4958 | struct drm_i915_file_private *file_priv = | |
4959 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
4960 | ||
4961 | atomic_set(&file_priv->rps_wait_boost, false); | |
4962 | } | |
4963 | ||
4964 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4965 | { | |
4966 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4967 | int ret; |
b29c19b6 CW |
4968 | |
4969 | DRM_DEBUG_DRIVER("\n"); | |
4970 | ||
4971 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4972 | if (!file_priv) | |
4973 | return -ENOMEM; | |
4974 | ||
4975 | file->driver_priv = file_priv; | |
4976 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 4977 | file_priv->file = file; |
b29c19b6 CW |
4978 | |
4979 | spin_lock_init(&file_priv->mm.lock); | |
4980 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4981 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
4982 | i915_gem_file_idle_work_handler); | |
4983 | ||
e422b888 BW |
4984 | ret = i915_gem_context_open(dev, file); |
4985 | if (ret) | |
4986 | kfree(file_priv); | |
b29c19b6 | 4987 | |
e422b888 | 4988 | return ret; |
b29c19b6 CW |
4989 | } |
4990 | ||
5774506f CW |
4991 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4992 | { | |
4993 | if (!mutex_is_locked(mutex)) | |
4994 | return false; | |
4995 | ||
4996 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4997 | return mutex->owner == task; | |
4998 | #else | |
4999 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5000 | return false; | |
5001 | #endif | |
5002 | } | |
5003 | ||
ceabbba5 CW |
5004 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5005 | { | |
5006 | struct i915_vma *vma; | |
5007 | int count = 0; | |
5008 | ||
5009 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5010 | if (drm_mm_node_allocated(&vma->node)) | |
5011 | count++; | |
5012 | ||
5013 | return count; | |
5014 | } | |
5015 | ||
7dc19d5a | 5016 | static unsigned long |
ceabbba5 | 5017 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5018 | { |
17250b71 | 5019 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5020 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5021 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5022 | struct drm_i915_gem_object *obj; |
5774506f | 5023 | bool unlock = true; |
7dc19d5a | 5024 | unsigned long count; |
17250b71 | 5025 | |
5774506f CW |
5026 | if (!mutex_trylock(&dev->struct_mutex)) { |
5027 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 5028 | return 0; |
5774506f | 5029 | |
677feac2 | 5030 | if (dev_priv->mm.shrinker_no_lock_stealing) |
d3227046 | 5031 | return 0; |
677feac2 | 5032 | |
5774506f CW |
5033 | unlock = false; |
5034 | } | |
31169714 | 5035 | |
7dc19d5a | 5036 | count = 0; |
35c20a60 | 5037 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5038 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5039 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5040 | |
5041 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5042 | if (!i915_gem_obj_is_pinned(obj) && |
5043 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5044 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5045 | } |
17250b71 | 5046 | |
5774506f CW |
5047 | if (unlock) |
5048 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5049 | |
7dc19d5a | 5050 | return count; |
31169714 | 5051 | } |
a70a3148 BW |
5052 | |
5053 | /* All the new VM stuff */ | |
5054 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5055 | struct i915_address_space *vm) | |
5056 | { | |
5057 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5058 | struct i915_vma *vma; | |
5059 | ||
6f425321 BW |
5060 | if (!dev_priv->mm.aliasing_ppgtt || |
5061 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5062 | vm = &dev_priv->gtt.base; |
5063 | ||
5064 | BUG_ON(list_empty(&o->vma_list)); | |
5065 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
5066 | if (vma->vm == vm) | |
5067 | return vma->node.start; | |
5068 | ||
5069 | } | |
5070 | return -1; | |
5071 | } | |
5072 | ||
5073 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5074 | struct i915_address_space *vm) | |
5075 | { | |
5076 | struct i915_vma *vma; | |
5077 | ||
5078 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5079 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5080 | return true; |
5081 | ||
5082 | return false; | |
5083 | } | |
5084 | ||
5085 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5086 | { | |
5a1d5eb0 | 5087 | struct i915_vma *vma; |
a70a3148 | 5088 | |
5a1d5eb0 CW |
5089 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5090 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5091 | return true; |
5092 | ||
5093 | return false; | |
5094 | } | |
5095 | ||
5096 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5097 | struct i915_address_space *vm) | |
5098 | { | |
5099 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5100 | struct i915_vma *vma; | |
5101 | ||
6f425321 BW |
5102 | if (!dev_priv->mm.aliasing_ppgtt || |
5103 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5104 | vm = &dev_priv->gtt.base; |
5105 | ||
5106 | BUG_ON(list_empty(&o->vma_list)); | |
5107 | ||
5108 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5109 | if (vma->vm == vm) | |
5110 | return vma->node.size; | |
5111 | ||
5112 | return 0; | |
5113 | } | |
5114 | ||
7dc19d5a | 5115 | static unsigned long |
ceabbba5 | 5116 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5117 | { |
5118 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5119 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5120 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a DC |
5121 | unsigned long freed; |
5122 | bool unlock = true; | |
5123 | ||
5124 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5125 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 5126 | return SHRINK_STOP; |
7dc19d5a DC |
5127 | |
5128 | if (dev_priv->mm.shrinker_no_lock_stealing) | |
d3227046 | 5129 | return SHRINK_STOP; |
7dc19d5a DC |
5130 | |
5131 | unlock = false; | |
5132 | } | |
5133 | ||
d9973b43 CW |
5134 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
5135 | if (freed < sc->nr_to_scan) | |
5136 | freed += __i915_gem_shrink(dev_priv, | |
5137 | sc->nr_to_scan - freed, | |
5138 | false); | |
5139 | if (freed < sc->nr_to_scan) | |
7dc19d5a DC |
5140 | freed += i915_gem_shrink_all(dev_priv); |
5141 | ||
5142 | if (unlock) | |
5143 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5144 | |
7dc19d5a DC |
5145 | return freed; |
5146 | } | |
5c2abbea BW |
5147 | |
5148 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
5149 | { | |
5150 | struct i915_vma *vma; | |
5151 | ||
19656430 OM |
5152 | /* This WARN has probably outlived its usefulness (callers already |
5153 | * WARN if they don't find the GGTT vma they expect). When removing, | |
5154 | * remember to remove the pre-check in is_pin_display() as well */ | |
5c2abbea BW |
5155 | if (WARN_ON(list_empty(&obj->vma_list))) |
5156 | return NULL; | |
5157 | ||
5158 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
6e164c33 | 5159 | if (vma->vm != obj_to_ggtt(obj)) |
5c2abbea BW |
5160 | return NULL; |
5161 | ||
5162 | return vma; | |
5163 | } |