Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
673a394b | 37 | |
88241785 | 38 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
42 | bool write); | |
43 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, | |
44 | uint64_t offset, | |
45 | uint64_t size); | |
05394f39 | 46 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
88241785 CW |
47 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
48 | unsigned alignment, | |
49 | bool map_and_fenceable); | |
d9e86c0e CW |
50 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
51 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
53 | struct drm_i915_gem_object *obj, | |
71acb5eb | 54 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
55 | struct drm_file *file); |
56 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 57 | |
17250b71 CW |
58 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
59 | int nr_to_scan, | |
60 | gfp_t gfp_mask); | |
61 | ||
31169714 | 62 | |
73aa808f CW |
63 | /* some bookkeeping */ |
64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
65 | size_t size) | |
66 | { | |
67 | dev_priv->mm.object_count++; | |
68 | dev_priv->mm.object_memory += size; | |
69 | } | |
70 | ||
71 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
72 | size_t size) | |
73 | { | |
74 | dev_priv->mm.object_count--; | |
75 | dev_priv->mm.object_memory -= size; | |
76 | } | |
77 | ||
21dd3734 CW |
78 | static int |
79 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
80 | { |
81 | struct drm_i915_private *dev_priv = dev->dev_private; | |
82 | struct completion *x = &dev_priv->error_completion; | |
83 | unsigned long flags; | |
84 | int ret; | |
85 | ||
86 | if (!atomic_read(&dev_priv->mm.wedged)) | |
87 | return 0; | |
88 | ||
89 | ret = wait_for_completion_interruptible(x); | |
90 | if (ret) | |
91 | return ret; | |
92 | ||
21dd3734 CW |
93 | if (atomic_read(&dev_priv->mm.wedged)) { |
94 | /* GPU is hung, bump the completion count to account for | |
95 | * the token we just consumed so that we never hit zero and | |
96 | * end up waiting upon a subsequent completion event that | |
97 | * will never happen. | |
98 | */ | |
99 | spin_lock_irqsave(&x->wait.lock, flags); | |
100 | x->done++; | |
101 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
102 | } | |
103 | return 0; | |
30dbf0c0 CW |
104 | } |
105 | ||
54cf91dc | 106 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 107 | { |
76c1dec1 CW |
108 | int ret; |
109 | ||
21dd3734 | 110 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
111 | if (ret) |
112 | return ret; | |
113 | ||
114 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
115 | if (ret) | |
116 | return ret; | |
117 | ||
23bc5982 | 118 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
119 | return 0; |
120 | } | |
30dbf0c0 | 121 | |
7d1c4804 | 122 | static inline bool |
05394f39 | 123 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 124 | { |
05394f39 | 125 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
126 | } |
127 | ||
2021746e CW |
128 | void i915_gem_do_init(struct drm_device *dev, |
129 | unsigned long start, | |
130 | unsigned long mappable_end, | |
131 | unsigned long end) | |
673a394b EA |
132 | { |
133 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 134 | |
bee4a186 | 135 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
673a394b | 136 | |
bee4a186 CW |
137 | dev_priv->mm.gtt_start = start; |
138 | dev_priv->mm.gtt_mappable_end = mappable_end; | |
139 | dev_priv->mm.gtt_end = end; | |
73aa808f | 140 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 141 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
bee4a186 CW |
142 | |
143 | /* Take over this portion of the GTT */ | |
144 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); | |
79e53945 | 145 | } |
673a394b | 146 | |
79e53945 JB |
147 | int |
148 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 149 | struct drm_file *file) |
79e53945 JB |
150 | { |
151 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
152 | |
153 | if (args->gtt_start >= args->gtt_end || | |
154 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
155 | return -EINVAL; | |
79e53945 JB |
156 | |
157 | mutex_lock(&dev->struct_mutex); | |
2021746e | 158 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
159 | mutex_unlock(&dev->struct_mutex); |
160 | ||
2021746e | 161 | return 0; |
673a394b EA |
162 | } |
163 | ||
5a125c3c EA |
164 | int |
165 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 166 | struct drm_file *file) |
5a125c3c | 167 | { |
73aa808f | 168 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 169 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
170 | struct drm_i915_gem_object *obj; |
171 | size_t pinned; | |
5a125c3c EA |
172 | |
173 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
174 | return -ENODEV; | |
175 | ||
6299f992 | 176 | pinned = 0; |
73aa808f | 177 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
178 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
179 | pinned += obj->gtt_space->size; | |
73aa808f | 180 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 181 | |
6299f992 CW |
182 | args->aper_size = dev_priv->mm.gtt_total; |
183 | args->aper_available_size = args->aper_size -pinned; | |
184 | ||
5a125c3c EA |
185 | return 0; |
186 | } | |
187 | ||
ff72145b DA |
188 | static int |
189 | i915_gem_create(struct drm_file *file, | |
190 | struct drm_device *dev, | |
191 | uint64_t size, | |
192 | uint32_t *handle_p) | |
673a394b | 193 | { |
05394f39 | 194 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
195 | int ret; |
196 | u32 handle; | |
673a394b | 197 | |
ff72145b | 198 | size = roundup(size, PAGE_SIZE); |
673a394b EA |
199 | |
200 | /* Allocate the new object */ | |
ff72145b | 201 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
202 | if (obj == NULL) |
203 | return -ENOMEM; | |
204 | ||
05394f39 | 205 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 206 | if (ret) { |
05394f39 CW |
207 | drm_gem_object_release(&obj->base); |
208 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 209 | kfree(obj); |
673a394b | 210 | return ret; |
1dfd9754 | 211 | } |
673a394b | 212 | |
202f2fef | 213 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 214 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
215 | trace_i915_gem_object_create(obj); |
216 | ||
ff72145b | 217 | *handle_p = handle; |
673a394b EA |
218 | return 0; |
219 | } | |
220 | ||
ff72145b DA |
221 | int |
222 | i915_gem_dumb_create(struct drm_file *file, | |
223 | struct drm_device *dev, | |
224 | struct drm_mode_create_dumb *args) | |
225 | { | |
226 | /* have to work out size/pitch and return them */ | |
ed0291fd | 227 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
228 | args->size = args->pitch * args->height; |
229 | return i915_gem_create(file, dev, | |
230 | args->size, &args->handle); | |
231 | } | |
232 | ||
233 | int i915_gem_dumb_destroy(struct drm_file *file, | |
234 | struct drm_device *dev, | |
235 | uint32_t handle) | |
236 | { | |
237 | return drm_gem_handle_delete(file, handle); | |
238 | } | |
239 | ||
240 | /** | |
241 | * Creates a new mm object and returns a handle to it. | |
242 | */ | |
243 | int | |
244 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
245 | struct drm_file *file) | |
246 | { | |
247 | struct drm_i915_gem_create *args = data; | |
248 | return i915_gem_create(file, dev, | |
249 | args->size, &args->handle); | |
250 | } | |
251 | ||
05394f39 | 252 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 253 | { |
05394f39 | 254 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
255 | |
256 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 257 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
258 | } |
259 | ||
99a03df5 | 260 | static inline void |
40123c1f EA |
261 | slow_shmem_copy(struct page *dst_page, |
262 | int dst_offset, | |
263 | struct page *src_page, | |
264 | int src_offset, | |
265 | int length) | |
266 | { | |
267 | char *dst_vaddr, *src_vaddr; | |
268 | ||
99a03df5 CW |
269 | dst_vaddr = kmap(dst_page); |
270 | src_vaddr = kmap(src_page); | |
40123c1f EA |
271 | |
272 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
273 | ||
99a03df5 CW |
274 | kunmap(src_page); |
275 | kunmap(dst_page); | |
40123c1f EA |
276 | } |
277 | ||
99a03df5 | 278 | static inline void |
280b713b EA |
279 | slow_shmem_bit17_copy(struct page *gpu_page, |
280 | int gpu_offset, | |
281 | struct page *cpu_page, | |
282 | int cpu_offset, | |
283 | int length, | |
284 | int is_read) | |
285 | { | |
286 | char *gpu_vaddr, *cpu_vaddr; | |
287 | ||
288 | /* Use the unswizzled path if this page isn't affected. */ | |
289 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
290 | if (is_read) | |
291 | return slow_shmem_copy(cpu_page, cpu_offset, | |
292 | gpu_page, gpu_offset, length); | |
293 | else | |
294 | return slow_shmem_copy(gpu_page, gpu_offset, | |
295 | cpu_page, cpu_offset, length); | |
296 | } | |
297 | ||
99a03df5 CW |
298 | gpu_vaddr = kmap(gpu_page); |
299 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
300 | |
301 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
302 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
303 | */ | |
304 | while (length > 0) { | |
305 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
306 | int this_length = min(cacheline_end - gpu_offset, length); | |
307 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
308 | ||
309 | if (is_read) { | |
310 | memcpy(cpu_vaddr + cpu_offset, | |
311 | gpu_vaddr + swizzled_gpu_offset, | |
312 | this_length); | |
313 | } else { | |
314 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
315 | cpu_vaddr + cpu_offset, | |
316 | this_length); | |
317 | } | |
318 | cpu_offset += this_length; | |
319 | gpu_offset += this_length; | |
320 | length -= this_length; | |
321 | } | |
322 | ||
99a03df5 CW |
323 | kunmap(cpu_page); |
324 | kunmap(gpu_page); | |
280b713b EA |
325 | } |
326 | ||
eb01459f EA |
327 | /** |
328 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
329 | * from the backing pages of the object to the user's address space. On a | |
330 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
331 | */ | |
332 | static int | |
05394f39 CW |
333 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
334 | struct drm_i915_gem_object *obj, | |
eb01459f | 335 | struct drm_i915_gem_pread *args, |
05394f39 | 336 | struct drm_file *file) |
eb01459f | 337 | { |
05394f39 | 338 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 339 | ssize_t remain; |
e5281ccd | 340 | loff_t offset; |
eb01459f EA |
341 | char __user *user_data; |
342 | int page_offset, page_length; | |
eb01459f EA |
343 | |
344 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
345 | remain = args->size; | |
346 | ||
eb01459f EA |
347 | offset = args->offset; |
348 | ||
349 | while (remain > 0) { | |
e5281ccd CW |
350 | struct page *page; |
351 | char *vaddr; | |
352 | int ret; | |
353 | ||
eb01459f EA |
354 | /* Operation in this page |
355 | * | |
eb01459f EA |
356 | * page_offset = offset within page |
357 | * page_length = bytes to copy for this page | |
358 | */ | |
eb01459f EA |
359 | page_offset = offset & (PAGE_SIZE-1); |
360 | page_length = remain; | |
361 | if ((page_offset + remain) > PAGE_SIZE) | |
362 | page_length = PAGE_SIZE - page_offset; | |
363 | ||
e5281ccd CW |
364 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
365 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
366 | if (IS_ERR(page)) | |
367 | return PTR_ERR(page); | |
368 | ||
369 | vaddr = kmap_atomic(page); | |
370 | ret = __copy_to_user_inatomic(user_data, | |
371 | vaddr + page_offset, | |
372 | page_length); | |
373 | kunmap_atomic(vaddr); | |
374 | ||
375 | mark_page_accessed(page); | |
376 | page_cache_release(page); | |
377 | if (ret) | |
4f27b75d | 378 | return -EFAULT; |
eb01459f EA |
379 | |
380 | remain -= page_length; | |
381 | user_data += page_length; | |
382 | offset += page_length; | |
383 | } | |
384 | ||
4f27b75d | 385 | return 0; |
eb01459f EA |
386 | } |
387 | ||
388 | /** | |
389 | * This is the fallback shmem pread path, which allocates temporary storage | |
390 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
391 | * can copy out of the object's backing pages while holding the struct mutex | |
392 | * and not take page faults. | |
393 | */ | |
394 | static int | |
05394f39 CW |
395 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
396 | struct drm_i915_gem_object *obj, | |
eb01459f | 397 | struct drm_i915_gem_pread *args, |
05394f39 | 398 | struct drm_file *file) |
eb01459f | 399 | { |
05394f39 | 400 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f EA |
401 | struct mm_struct *mm = current->mm; |
402 | struct page **user_pages; | |
403 | ssize_t remain; | |
404 | loff_t offset, pinned_pages, i; | |
405 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
406 | int shmem_page_offset; |
407 | int data_page_index, data_page_offset; | |
eb01459f EA |
408 | int page_length; |
409 | int ret; | |
410 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 411 | int do_bit17_swizzling; |
eb01459f EA |
412 | |
413 | remain = args->size; | |
414 | ||
415 | /* Pin the user pages containing the data. We can't fault while | |
416 | * holding the struct mutex, yet we want to hold it while | |
417 | * dereferencing the user data. | |
418 | */ | |
419 | first_data_page = data_ptr / PAGE_SIZE; | |
420 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
421 | num_pages = last_data_page - first_data_page + 1; | |
422 | ||
4f27b75d | 423 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
424 | if (user_pages == NULL) |
425 | return -ENOMEM; | |
426 | ||
4f27b75d | 427 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
428 | down_read(&mm->mmap_sem); |
429 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 430 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 431 | up_read(&mm->mmap_sem); |
4f27b75d | 432 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
433 | if (pinned_pages < num_pages) { |
434 | ret = -EFAULT; | |
4f27b75d | 435 | goto out; |
eb01459f EA |
436 | } |
437 | ||
4f27b75d CW |
438 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
439 | args->offset, | |
440 | args->size); | |
07f73f69 | 441 | if (ret) |
4f27b75d | 442 | goto out; |
eb01459f | 443 | |
4f27b75d | 444 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 445 | |
eb01459f EA |
446 | offset = args->offset; |
447 | ||
448 | while (remain > 0) { | |
e5281ccd CW |
449 | struct page *page; |
450 | ||
eb01459f EA |
451 | /* Operation in this page |
452 | * | |
eb01459f EA |
453 | * shmem_page_offset = offset within page in shmem file |
454 | * data_page_index = page number in get_user_pages return | |
455 | * data_page_offset = offset with data_page_index page. | |
456 | * page_length = bytes to copy for this page | |
457 | */ | |
eb01459f EA |
458 | shmem_page_offset = offset & ~PAGE_MASK; |
459 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
460 | data_page_offset = data_ptr & ~PAGE_MASK; | |
461 | ||
462 | page_length = remain; | |
463 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
464 | page_length = PAGE_SIZE - shmem_page_offset; | |
465 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
466 | page_length = PAGE_SIZE - data_page_offset; | |
467 | ||
e5281ccd CW |
468 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
469 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
470 | if (IS_ERR(page)) | |
471 | return PTR_ERR(page); | |
472 | ||
280b713b | 473 | if (do_bit17_swizzling) { |
e5281ccd | 474 | slow_shmem_bit17_copy(page, |
280b713b | 475 | shmem_page_offset, |
99a03df5 CW |
476 | user_pages[data_page_index], |
477 | data_page_offset, | |
478 | page_length, | |
479 | 1); | |
480 | } else { | |
481 | slow_shmem_copy(user_pages[data_page_index], | |
482 | data_page_offset, | |
e5281ccd | 483 | page, |
99a03df5 CW |
484 | shmem_page_offset, |
485 | page_length); | |
280b713b | 486 | } |
eb01459f | 487 | |
e5281ccd CW |
488 | mark_page_accessed(page); |
489 | page_cache_release(page); | |
490 | ||
eb01459f EA |
491 | remain -= page_length; |
492 | data_ptr += page_length; | |
493 | offset += page_length; | |
494 | } | |
495 | ||
4f27b75d | 496 | out: |
eb01459f EA |
497 | for (i = 0; i < pinned_pages; i++) { |
498 | SetPageDirty(user_pages[i]); | |
e5281ccd | 499 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
500 | page_cache_release(user_pages[i]); |
501 | } | |
8e7d2b2c | 502 | drm_free_large(user_pages); |
eb01459f EA |
503 | |
504 | return ret; | |
505 | } | |
506 | ||
673a394b EA |
507 | /** |
508 | * Reads data from the object referenced by handle. | |
509 | * | |
510 | * On error, the contents of *data are undefined. | |
511 | */ | |
512 | int | |
513 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 514 | struct drm_file *file) |
673a394b EA |
515 | { |
516 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 517 | struct drm_i915_gem_object *obj; |
35b62a89 | 518 | int ret = 0; |
673a394b | 519 | |
51311d0a CW |
520 | if (args->size == 0) |
521 | return 0; | |
522 | ||
523 | if (!access_ok(VERIFY_WRITE, | |
524 | (char __user *)(uintptr_t)args->data_ptr, | |
525 | args->size)) | |
526 | return -EFAULT; | |
527 | ||
528 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
529 | args->size); | |
530 | if (ret) | |
531 | return -EFAULT; | |
532 | ||
4f27b75d | 533 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 534 | if (ret) |
4f27b75d | 535 | return ret; |
673a394b | 536 | |
05394f39 | 537 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 538 | if (&obj->base == NULL) { |
1d7cfea1 CW |
539 | ret = -ENOENT; |
540 | goto unlock; | |
4f27b75d | 541 | } |
673a394b | 542 | |
7dcd2499 | 543 | /* Bounds check source. */ |
05394f39 CW |
544 | if (args->offset > obj->base.size || |
545 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 546 | ret = -EINVAL; |
35b62a89 | 547 | goto out; |
ce9d419d CW |
548 | } |
549 | ||
db53a302 CW |
550 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
551 | ||
4f27b75d CW |
552 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
553 | args->offset, | |
554 | args->size); | |
555 | if (ret) | |
e5281ccd | 556 | goto out; |
4f27b75d CW |
557 | |
558 | ret = -EFAULT; | |
559 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 560 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 561 | if (ret == -EFAULT) |
05394f39 | 562 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 563 | |
35b62a89 | 564 | out: |
05394f39 | 565 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 566 | unlock: |
4f27b75d | 567 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 568 | return ret; |
673a394b EA |
569 | } |
570 | ||
0839ccb8 KP |
571 | /* This is the fast write path which cannot handle |
572 | * page faults in the source data | |
9b7530cc | 573 | */ |
0839ccb8 KP |
574 | |
575 | static inline int | |
576 | fast_user_write(struct io_mapping *mapping, | |
577 | loff_t page_base, int page_offset, | |
578 | char __user *user_data, | |
579 | int length) | |
9b7530cc | 580 | { |
9b7530cc | 581 | char *vaddr_atomic; |
0839ccb8 | 582 | unsigned long unwritten; |
9b7530cc | 583 | |
3e4d3af5 | 584 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
585 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
586 | user_data, length); | |
3e4d3af5 | 587 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 588 | return unwritten; |
0839ccb8 KP |
589 | } |
590 | ||
591 | /* Here's the write path which can sleep for | |
592 | * page faults | |
593 | */ | |
594 | ||
ab34c226 | 595 | static inline void |
3de09aa3 EA |
596 | slow_kernel_write(struct io_mapping *mapping, |
597 | loff_t gtt_base, int gtt_offset, | |
598 | struct page *user_page, int user_offset, | |
599 | int length) | |
0839ccb8 | 600 | { |
ab34c226 CW |
601 | char __iomem *dst_vaddr; |
602 | char *src_vaddr; | |
0839ccb8 | 603 | |
ab34c226 CW |
604 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
605 | src_vaddr = kmap(user_page); | |
606 | ||
607 | memcpy_toio(dst_vaddr + gtt_offset, | |
608 | src_vaddr + user_offset, | |
609 | length); | |
610 | ||
611 | kunmap(user_page); | |
612 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
613 | } |
614 | ||
3de09aa3 EA |
615 | /** |
616 | * This is the fast pwrite path, where we copy the data directly from the | |
617 | * user into the GTT, uncached. | |
618 | */ | |
673a394b | 619 | static int |
05394f39 CW |
620 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
621 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 622 | struct drm_i915_gem_pwrite *args, |
05394f39 | 623 | struct drm_file *file) |
673a394b | 624 | { |
0839ccb8 | 625 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 626 | ssize_t remain; |
0839ccb8 | 627 | loff_t offset, page_base; |
673a394b | 628 | char __user *user_data; |
0839ccb8 | 629 | int page_offset, page_length; |
673a394b EA |
630 | |
631 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
632 | remain = args->size; | |
673a394b | 633 | |
05394f39 | 634 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
635 | |
636 | while (remain > 0) { | |
637 | /* Operation in this page | |
638 | * | |
0839ccb8 KP |
639 | * page_base = page offset within aperture |
640 | * page_offset = offset within page | |
641 | * page_length = bytes to copy for this page | |
673a394b | 642 | */ |
0839ccb8 KP |
643 | page_base = (offset & ~(PAGE_SIZE-1)); |
644 | page_offset = offset & (PAGE_SIZE-1); | |
645 | page_length = remain; | |
646 | if ((page_offset + remain) > PAGE_SIZE) | |
647 | page_length = PAGE_SIZE - page_offset; | |
648 | ||
0839ccb8 | 649 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
650 | * source page isn't available. Return the error and we'll |
651 | * retry in the slow path. | |
0839ccb8 | 652 | */ |
fbd5a26d CW |
653 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
654 | page_offset, user_data, page_length)) | |
655 | ||
656 | return -EFAULT; | |
673a394b | 657 | |
0839ccb8 KP |
658 | remain -= page_length; |
659 | user_data += page_length; | |
660 | offset += page_length; | |
673a394b | 661 | } |
673a394b | 662 | |
fbd5a26d | 663 | return 0; |
673a394b EA |
664 | } |
665 | ||
3de09aa3 EA |
666 | /** |
667 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
668 | * the memory and maps it using kmap_atomic for copying. | |
669 | * | |
670 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
671 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
672 | */ | |
3043c60c | 673 | static int |
05394f39 CW |
674 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
675 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 676 | struct drm_i915_gem_pwrite *args, |
05394f39 | 677 | struct drm_file *file) |
673a394b | 678 | { |
3de09aa3 EA |
679 | drm_i915_private_t *dev_priv = dev->dev_private; |
680 | ssize_t remain; | |
681 | loff_t gtt_page_base, offset; | |
682 | loff_t first_data_page, last_data_page, num_pages; | |
683 | loff_t pinned_pages, i; | |
684 | struct page **user_pages; | |
685 | struct mm_struct *mm = current->mm; | |
686 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 687 | int ret; |
3de09aa3 EA |
688 | uint64_t data_ptr = args->data_ptr; |
689 | ||
690 | remain = args->size; | |
691 | ||
692 | /* Pin the user pages containing the data. We can't fault while | |
693 | * holding the struct mutex, and all of the pwrite implementations | |
694 | * want to hold it while dereferencing the user data. | |
695 | */ | |
696 | first_data_page = data_ptr / PAGE_SIZE; | |
697 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
698 | num_pages = last_data_page - first_data_page + 1; | |
699 | ||
fbd5a26d | 700 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
701 | if (user_pages == NULL) |
702 | return -ENOMEM; | |
703 | ||
fbd5a26d | 704 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
705 | down_read(&mm->mmap_sem); |
706 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
707 | num_pages, 0, 0, user_pages, NULL); | |
708 | up_read(&mm->mmap_sem); | |
fbd5a26d | 709 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
710 | if (pinned_pages < num_pages) { |
711 | ret = -EFAULT; | |
712 | goto out_unpin_pages; | |
713 | } | |
673a394b | 714 | |
d9e86c0e CW |
715 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
716 | if (ret) | |
717 | goto out_unpin_pages; | |
718 | ||
719 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 720 | if (ret) |
fbd5a26d | 721 | goto out_unpin_pages; |
3de09aa3 | 722 | |
05394f39 | 723 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
724 | |
725 | while (remain > 0) { | |
726 | /* Operation in this page | |
727 | * | |
728 | * gtt_page_base = page offset within aperture | |
729 | * gtt_page_offset = offset within page in aperture | |
730 | * data_page_index = page number in get_user_pages return | |
731 | * data_page_offset = offset with data_page_index page. | |
732 | * page_length = bytes to copy for this page | |
733 | */ | |
734 | gtt_page_base = offset & PAGE_MASK; | |
735 | gtt_page_offset = offset & ~PAGE_MASK; | |
736 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
737 | data_page_offset = data_ptr & ~PAGE_MASK; | |
738 | ||
739 | page_length = remain; | |
740 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
741 | page_length = PAGE_SIZE - gtt_page_offset; | |
742 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
743 | page_length = PAGE_SIZE - data_page_offset; | |
744 | ||
ab34c226 CW |
745 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
746 | gtt_page_base, gtt_page_offset, | |
747 | user_pages[data_page_index], | |
748 | data_page_offset, | |
749 | page_length); | |
3de09aa3 EA |
750 | |
751 | remain -= page_length; | |
752 | offset += page_length; | |
753 | data_ptr += page_length; | |
754 | } | |
755 | ||
3de09aa3 EA |
756 | out_unpin_pages: |
757 | for (i = 0; i < pinned_pages; i++) | |
758 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 759 | drm_free_large(user_pages); |
3de09aa3 EA |
760 | |
761 | return ret; | |
762 | } | |
763 | ||
40123c1f EA |
764 | /** |
765 | * This is the fast shmem pwrite path, which attempts to directly | |
766 | * copy_from_user into the kmapped pages backing the object. | |
767 | */ | |
3043c60c | 768 | static int |
05394f39 CW |
769 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
770 | struct drm_i915_gem_object *obj, | |
40123c1f | 771 | struct drm_i915_gem_pwrite *args, |
05394f39 | 772 | struct drm_file *file) |
673a394b | 773 | { |
05394f39 | 774 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 775 | ssize_t remain; |
e5281ccd | 776 | loff_t offset; |
40123c1f EA |
777 | char __user *user_data; |
778 | int page_offset, page_length; | |
40123c1f EA |
779 | |
780 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
781 | remain = args->size; | |
673a394b | 782 | |
40123c1f | 783 | offset = args->offset; |
05394f39 | 784 | obj->dirty = 1; |
40123c1f EA |
785 | |
786 | while (remain > 0) { | |
e5281ccd CW |
787 | struct page *page; |
788 | char *vaddr; | |
789 | int ret; | |
790 | ||
40123c1f EA |
791 | /* Operation in this page |
792 | * | |
40123c1f EA |
793 | * page_offset = offset within page |
794 | * page_length = bytes to copy for this page | |
795 | */ | |
40123c1f EA |
796 | page_offset = offset & (PAGE_SIZE-1); |
797 | page_length = remain; | |
798 | if ((page_offset + remain) > PAGE_SIZE) | |
799 | page_length = PAGE_SIZE - page_offset; | |
800 | ||
e5281ccd CW |
801 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
802 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
803 | if (IS_ERR(page)) | |
804 | return PTR_ERR(page); | |
805 | ||
806 | vaddr = kmap_atomic(page, KM_USER0); | |
807 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
808 | user_data, | |
809 | page_length); | |
810 | kunmap_atomic(vaddr, KM_USER0); | |
811 | ||
812 | set_page_dirty(page); | |
813 | mark_page_accessed(page); | |
814 | page_cache_release(page); | |
815 | ||
816 | /* If we get a fault while copying data, then (presumably) our | |
817 | * source page isn't available. Return the error and we'll | |
818 | * retry in the slow path. | |
819 | */ | |
820 | if (ret) | |
fbd5a26d | 821 | return -EFAULT; |
40123c1f EA |
822 | |
823 | remain -= page_length; | |
824 | user_data += page_length; | |
825 | offset += page_length; | |
826 | } | |
827 | ||
fbd5a26d | 828 | return 0; |
40123c1f EA |
829 | } |
830 | ||
831 | /** | |
832 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
833 | * the memory and maps it using kmap_atomic for copying. | |
834 | * | |
835 | * This avoids taking mmap_sem for faulting on the user's address while the | |
836 | * struct_mutex is held. | |
837 | */ | |
838 | static int | |
05394f39 CW |
839 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
840 | struct drm_i915_gem_object *obj, | |
40123c1f | 841 | struct drm_i915_gem_pwrite *args, |
05394f39 | 842 | struct drm_file *file) |
40123c1f | 843 | { |
05394f39 | 844 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f EA |
845 | struct mm_struct *mm = current->mm; |
846 | struct page **user_pages; | |
847 | ssize_t remain; | |
848 | loff_t offset, pinned_pages, i; | |
849 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 850 | int shmem_page_offset; |
40123c1f EA |
851 | int data_page_index, data_page_offset; |
852 | int page_length; | |
853 | int ret; | |
854 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 855 | int do_bit17_swizzling; |
40123c1f EA |
856 | |
857 | remain = args->size; | |
858 | ||
859 | /* Pin the user pages containing the data. We can't fault while | |
860 | * holding the struct mutex, and all of the pwrite implementations | |
861 | * want to hold it while dereferencing the user data. | |
862 | */ | |
863 | first_data_page = data_ptr / PAGE_SIZE; | |
864 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
865 | num_pages = last_data_page - first_data_page + 1; | |
866 | ||
4f27b75d | 867 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
868 | if (user_pages == NULL) |
869 | return -ENOMEM; | |
870 | ||
fbd5a26d | 871 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
872 | down_read(&mm->mmap_sem); |
873 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
874 | num_pages, 0, 0, user_pages, NULL); | |
875 | up_read(&mm->mmap_sem); | |
fbd5a26d | 876 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
877 | if (pinned_pages < num_pages) { |
878 | ret = -EFAULT; | |
fbd5a26d | 879 | goto out; |
673a394b EA |
880 | } |
881 | ||
fbd5a26d | 882 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 883 | if (ret) |
fbd5a26d | 884 | goto out; |
40123c1f | 885 | |
fbd5a26d | 886 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 887 | |
673a394b | 888 | offset = args->offset; |
05394f39 | 889 | obj->dirty = 1; |
673a394b | 890 | |
40123c1f | 891 | while (remain > 0) { |
e5281ccd CW |
892 | struct page *page; |
893 | ||
40123c1f EA |
894 | /* Operation in this page |
895 | * | |
40123c1f EA |
896 | * shmem_page_offset = offset within page in shmem file |
897 | * data_page_index = page number in get_user_pages return | |
898 | * data_page_offset = offset with data_page_index page. | |
899 | * page_length = bytes to copy for this page | |
900 | */ | |
40123c1f EA |
901 | shmem_page_offset = offset & ~PAGE_MASK; |
902 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
903 | data_page_offset = data_ptr & ~PAGE_MASK; | |
904 | ||
905 | page_length = remain; | |
906 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
907 | page_length = PAGE_SIZE - shmem_page_offset; | |
908 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
909 | page_length = PAGE_SIZE - data_page_offset; | |
910 | ||
e5281ccd CW |
911 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
912 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
913 | if (IS_ERR(page)) { | |
914 | ret = PTR_ERR(page); | |
915 | goto out; | |
916 | } | |
917 | ||
280b713b | 918 | if (do_bit17_swizzling) { |
e5281ccd | 919 | slow_shmem_bit17_copy(page, |
280b713b EA |
920 | shmem_page_offset, |
921 | user_pages[data_page_index], | |
922 | data_page_offset, | |
99a03df5 CW |
923 | page_length, |
924 | 0); | |
925 | } else { | |
e5281ccd | 926 | slow_shmem_copy(page, |
99a03df5 CW |
927 | shmem_page_offset, |
928 | user_pages[data_page_index], | |
929 | data_page_offset, | |
930 | page_length); | |
280b713b | 931 | } |
40123c1f | 932 | |
e5281ccd CW |
933 | set_page_dirty(page); |
934 | mark_page_accessed(page); | |
935 | page_cache_release(page); | |
936 | ||
40123c1f EA |
937 | remain -= page_length; |
938 | data_ptr += page_length; | |
939 | offset += page_length; | |
673a394b EA |
940 | } |
941 | ||
fbd5a26d | 942 | out: |
40123c1f EA |
943 | for (i = 0; i < pinned_pages; i++) |
944 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 945 | drm_free_large(user_pages); |
673a394b | 946 | |
40123c1f | 947 | return ret; |
673a394b EA |
948 | } |
949 | ||
950 | /** | |
951 | * Writes data to the object referenced by handle. | |
952 | * | |
953 | * On error, the contents of the buffer that were to be modified are undefined. | |
954 | */ | |
955 | int | |
956 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 957 | struct drm_file *file) |
673a394b EA |
958 | { |
959 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 960 | struct drm_i915_gem_object *obj; |
51311d0a CW |
961 | int ret; |
962 | ||
963 | if (args->size == 0) | |
964 | return 0; | |
965 | ||
966 | if (!access_ok(VERIFY_READ, | |
967 | (char __user *)(uintptr_t)args->data_ptr, | |
968 | args->size)) | |
969 | return -EFAULT; | |
970 | ||
971 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
972 | args->size); | |
973 | if (ret) | |
974 | return -EFAULT; | |
673a394b | 975 | |
fbd5a26d | 976 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 977 | if (ret) |
fbd5a26d | 978 | return ret; |
1d7cfea1 | 979 | |
05394f39 | 980 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 981 | if (&obj->base == NULL) { |
1d7cfea1 CW |
982 | ret = -ENOENT; |
983 | goto unlock; | |
fbd5a26d | 984 | } |
673a394b | 985 | |
7dcd2499 | 986 | /* Bounds check destination. */ |
05394f39 CW |
987 | if (args->offset > obj->base.size || |
988 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 989 | ret = -EINVAL; |
35b62a89 | 990 | goto out; |
ce9d419d CW |
991 | } |
992 | ||
db53a302 CW |
993 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
994 | ||
673a394b EA |
995 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
996 | * it would end up going through the fenced access, and we'll get | |
997 | * different detiling behavior between reading and writing. | |
998 | * pread/pwrite currently are reading and writing from the CPU | |
999 | * perspective, requiring manual detiling by the client. | |
1000 | */ | |
05394f39 | 1001 | if (obj->phys_obj) |
fbd5a26d | 1002 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
d9e86c0e | 1003 | else if (obj->gtt_space && |
05394f39 | 1004 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 1005 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1006 | if (ret) |
1007 | goto out; | |
1008 | ||
d9e86c0e CW |
1009 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1010 | if (ret) | |
1011 | goto out_unpin; | |
1012 | ||
1013 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
1014 | if (ret) |
1015 | goto out_unpin; | |
1016 | ||
1017 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1018 | if (ret == -EFAULT) | |
1019 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1020 | ||
1021 | out_unpin: | |
1022 | i915_gem_object_unpin(obj); | |
40123c1f | 1023 | } else { |
fbd5a26d CW |
1024 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1025 | if (ret) | |
e5281ccd | 1026 | goto out; |
673a394b | 1027 | |
fbd5a26d CW |
1028 | ret = -EFAULT; |
1029 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1030 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1031 | if (ret == -EFAULT) | |
1032 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1033 | } |
673a394b | 1034 | |
35b62a89 | 1035 | out: |
05394f39 | 1036 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1037 | unlock: |
fbd5a26d | 1038 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1039 | return ret; |
1040 | } | |
1041 | ||
1042 | /** | |
2ef7eeaa EA |
1043 | * Called when user space prepares to use an object with the CPU, either |
1044 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1045 | */ |
1046 | int | |
1047 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1048 | struct drm_file *file) |
673a394b EA |
1049 | { |
1050 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1051 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1052 | uint32_t read_domains = args->read_domains; |
1053 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1054 | int ret; |
1055 | ||
1056 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1057 | return -ENODEV; | |
1058 | ||
2ef7eeaa | 1059 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1060 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1061 | return -EINVAL; |
1062 | ||
21d509e3 | 1063 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1064 | return -EINVAL; |
1065 | ||
1066 | /* Having something in the write domain implies it's in the read | |
1067 | * domain, and only that read domain. Enforce that in the request. | |
1068 | */ | |
1069 | if (write_domain != 0 && read_domains != write_domain) | |
1070 | return -EINVAL; | |
1071 | ||
76c1dec1 | 1072 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1073 | if (ret) |
76c1dec1 | 1074 | return ret; |
1d7cfea1 | 1075 | |
05394f39 | 1076 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1077 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1078 | ret = -ENOENT; |
1079 | goto unlock; | |
76c1dec1 | 1080 | } |
673a394b | 1081 | |
2ef7eeaa EA |
1082 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1083 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1084 | |
1085 | /* Silently promote "you're not bound, there was nothing to do" | |
1086 | * to success, since the client was just asking us to | |
1087 | * make sure everything was done. | |
1088 | */ | |
1089 | if (ret == -EINVAL) | |
1090 | ret = 0; | |
2ef7eeaa | 1091 | } else { |
e47c68e9 | 1092 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1093 | } |
1094 | ||
05394f39 | 1095 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1096 | unlock: |
673a394b EA |
1097 | mutex_unlock(&dev->struct_mutex); |
1098 | return ret; | |
1099 | } | |
1100 | ||
1101 | /** | |
1102 | * Called when user space has done writes to this buffer | |
1103 | */ | |
1104 | int | |
1105 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1106 | struct drm_file *file) |
673a394b EA |
1107 | { |
1108 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1109 | struct drm_i915_gem_object *obj; |
673a394b EA |
1110 | int ret = 0; |
1111 | ||
1112 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1113 | return -ENODEV; | |
1114 | ||
76c1dec1 | 1115 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1116 | if (ret) |
76c1dec1 | 1117 | return ret; |
1d7cfea1 | 1118 | |
05394f39 | 1119 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1120 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1121 | ret = -ENOENT; |
1122 | goto unlock; | |
673a394b EA |
1123 | } |
1124 | ||
673a394b | 1125 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1126 | if (obj->pin_count) |
e47c68e9 EA |
1127 | i915_gem_object_flush_cpu_write_domain(obj); |
1128 | ||
05394f39 | 1129 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1130 | unlock: |
673a394b EA |
1131 | mutex_unlock(&dev->struct_mutex); |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | /** | |
1136 | * Maps the contents of an object, returning the address it is mapped | |
1137 | * into. | |
1138 | * | |
1139 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1140 | * imply a ref on the object itself. | |
1141 | */ | |
1142 | int | |
1143 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1144 | struct drm_file *file) |
673a394b | 1145 | { |
da761a6e | 1146 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1147 | struct drm_i915_gem_mmap *args = data; |
1148 | struct drm_gem_object *obj; | |
673a394b EA |
1149 | unsigned long addr; |
1150 | ||
1151 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1152 | return -ENODEV; | |
1153 | ||
05394f39 | 1154 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1155 | if (obj == NULL) |
bf79cb91 | 1156 | return -ENOENT; |
673a394b | 1157 | |
da761a6e CW |
1158 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1159 | drm_gem_object_unreference_unlocked(obj); | |
1160 | return -E2BIG; | |
1161 | } | |
1162 | ||
673a394b EA |
1163 | down_write(¤t->mm->mmap_sem); |
1164 | addr = do_mmap(obj->filp, 0, args->size, | |
1165 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1166 | args->offset); | |
1167 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1168 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1169 | if (IS_ERR((void *)addr)) |
1170 | return addr; | |
1171 | ||
1172 | args->addr_ptr = (uint64_t) addr; | |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | ||
de151cf6 JB |
1177 | /** |
1178 | * i915_gem_fault - fault a page into the GTT | |
1179 | * vma: VMA in question | |
1180 | * vmf: fault info | |
1181 | * | |
1182 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1183 | * from userspace. The fault handler takes care of binding the object to | |
1184 | * the GTT (if needed), allocating and programming a fence register (again, | |
1185 | * only if needed based on whether the old reg is still valid or the object | |
1186 | * is tiled) and inserting a new PTE into the faulting process. | |
1187 | * | |
1188 | * Note that the faulting process may involve evicting existing objects | |
1189 | * from the GTT and/or fence registers to make room. So performance may | |
1190 | * suffer if the GTT working set is large or there are few fence registers | |
1191 | * left. | |
1192 | */ | |
1193 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1194 | { | |
05394f39 CW |
1195 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1196 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1197 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1198 | pgoff_t page_offset; |
1199 | unsigned long pfn; | |
1200 | int ret = 0; | |
0f973f27 | 1201 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1202 | |
1203 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1204 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1205 | PAGE_SHIFT; | |
1206 | ||
d9bc7e9f CW |
1207 | ret = i915_mutex_lock_interruptible(dev); |
1208 | if (ret) | |
1209 | goto out; | |
a00b10c3 | 1210 | |
db53a302 CW |
1211 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1212 | ||
d9bc7e9f | 1213 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1214 | if (!obj->map_and_fenceable) { |
1215 | ret = i915_gem_object_unbind(obj); | |
1216 | if (ret) | |
1217 | goto unlock; | |
a00b10c3 | 1218 | } |
05394f39 | 1219 | if (!obj->gtt_space) { |
75e9e915 | 1220 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1221 | if (ret) |
1222 | goto unlock; | |
de151cf6 JB |
1223 | } |
1224 | ||
4a684a41 CW |
1225 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1226 | if (ret) | |
1227 | goto unlock; | |
1228 | ||
d9e86c0e CW |
1229 | if (obj->tiling_mode == I915_TILING_NONE) |
1230 | ret = i915_gem_object_put_fence(obj); | |
1231 | else | |
ce453d81 | 1232 | ret = i915_gem_object_get_fence(obj, NULL); |
d9e86c0e CW |
1233 | if (ret) |
1234 | goto unlock; | |
de151cf6 | 1235 | |
05394f39 CW |
1236 | if (i915_gem_object_is_inactive(obj)) |
1237 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1238 | |
6299f992 CW |
1239 | obj->fault_mappable = true; |
1240 | ||
05394f39 | 1241 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1242 | page_offset; |
1243 | ||
1244 | /* Finally, remap it using the new GTT offset */ | |
1245 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1246 | unlock: |
de151cf6 | 1247 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1248 | out: |
de151cf6 | 1249 | switch (ret) { |
d9bc7e9f | 1250 | case -EIO: |
045e769a | 1251 | case -EAGAIN: |
d9bc7e9f CW |
1252 | /* Give the error handler a chance to run and move the |
1253 | * objects off the GPU active list. Next time we service the | |
1254 | * fault, we should be able to transition the page into the | |
1255 | * GTT without touching the GPU (and so avoid further | |
1256 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1257 | * with coherency, just lost writes. | |
1258 | */ | |
045e769a | 1259 | set_need_resched(); |
c715089f CW |
1260 | case 0: |
1261 | case -ERESTARTSYS: | |
bed636ab | 1262 | case -EINTR: |
c715089f | 1263 | return VM_FAULT_NOPAGE; |
de151cf6 | 1264 | case -ENOMEM: |
de151cf6 | 1265 | return VM_FAULT_OOM; |
de151cf6 | 1266 | default: |
c715089f | 1267 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1268 | } |
1269 | } | |
1270 | ||
1271 | /** | |
1272 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1273 | * @obj: obj in question | |
1274 | * | |
1275 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1276 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1277 | * up the object based on the offset and sets up the various memory mapping | |
1278 | * structures. | |
1279 | * | |
1280 | * This routine allocates and attaches a fake offset for @obj. | |
1281 | */ | |
1282 | static int | |
05394f39 | 1283 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
de151cf6 | 1284 | { |
05394f39 | 1285 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 1286 | struct drm_gem_mm *mm = dev->mm_private; |
de151cf6 | 1287 | struct drm_map_list *list; |
f77d390c | 1288 | struct drm_local_map *map; |
de151cf6 JB |
1289 | int ret = 0; |
1290 | ||
1291 | /* Set the object up for mmap'ing */ | |
05394f39 | 1292 | list = &obj->base.map_list; |
9a298b2a | 1293 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1294 | if (!list->map) |
1295 | return -ENOMEM; | |
1296 | ||
1297 | map = list->map; | |
1298 | map->type = _DRM_GEM; | |
05394f39 | 1299 | map->size = obj->base.size; |
de151cf6 JB |
1300 | map->handle = obj; |
1301 | ||
1302 | /* Get a DRM GEM mmap offset allocated... */ | |
1303 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
05394f39 CW |
1304 | obj->base.size / PAGE_SIZE, |
1305 | 0, 0); | |
de151cf6 | 1306 | if (!list->file_offset_node) { |
05394f39 CW |
1307 | DRM_ERROR("failed to allocate offset for bo %d\n", |
1308 | obj->base.name); | |
9e0ae534 | 1309 | ret = -ENOSPC; |
de151cf6 JB |
1310 | goto out_free_list; |
1311 | } | |
1312 | ||
1313 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
05394f39 CW |
1314 | obj->base.size / PAGE_SIZE, |
1315 | 0); | |
de151cf6 JB |
1316 | if (!list->file_offset_node) { |
1317 | ret = -ENOMEM; | |
1318 | goto out_free_list; | |
1319 | } | |
1320 | ||
1321 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1322 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1323 | if (ret) { | |
de151cf6 JB |
1324 | DRM_ERROR("failed to add to map hash\n"); |
1325 | goto out_free_mm; | |
1326 | } | |
1327 | ||
de151cf6 JB |
1328 | return 0; |
1329 | ||
1330 | out_free_mm: | |
1331 | drm_mm_put_block(list->file_offset_node); | |
1332 | out_free_list: | |
9a298b2a | 1333 | kfree(list->map); |
39a01d1f | 1334 | list->map = NULL; |
de151cf6 JB |
1335 | |
1336 | return ret; | |
1337 | } | |
1338 | ||
901782b2 CW |
1339 | /** |
1340 | * i915_gem_release_mmap - remove physical page mappings | |
1341 | * @obj: obj in question | |
1342 | * | |
af901ca1 | 1343 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1344 | * relinquish ownership of the pages back to the system. |
1345 | * | |
1346 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1347 | * object through the GTT and then lose the fence register due to | |
1348 | * resource pressure. Similarly if the object has been moved out of the | |
1349 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1350 | * mapping will then trigger a page fault on the next user access, allowing | |
1351 | * fixup by i915_gem_fault(). | |
1352 | */ | |
d05ca301 | 1353 | void |
05394f39 | 1354 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1355 | { |
6299f992 CW |
1356 | if (!obj->fault_mappable) |
1357 | return; | |
901782b2 | 1358 | |
6299f992 CW |
1359 | unmap_mapping_range(obj->base.dev->dev_mapping, |
1360 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1361 | obj->base.size, 1); | |
fb7d516a | 1362 | |
6299f992 | 1363 | obj->fault_mappable = false; |
901782b2 CW |
1364 | } |
1365 | ||
ab00b3e5 | 1366 | static void |
05394f39 | 1367 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
ab00b3e5 | 1368 | { |
05394f39 | 1369 | struct drm_device *dev = obj->base.dev; |
ab00b3e5 | 1370 | struct drm_gem_mm *mm = dev->mm_private; |
05394f39 | 1371 | struct drm_map_list *list = &obj->base.map_list; |
ab00b3e5 | 1372 | |
ab00b3e5 | 1373 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1374 | drm_mm_put_block(list->file_offset_node); |
1375 | kfree(list->map); | |
1376 | list->map = NULL; | |
ab00b3e5 JB |
1377 | } |
1378 | ||
92b88aeb CW |
1379 | static uint32_t |
1380 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) | |
1381 | { | |
1382 | struct drm_device *dev = obj->base.dev; | |
1383 | uint32_t size; | |
1384 | ||
1385 | if (INTEL_INFO(dev)->gen >= 4 || | |
1386 | obj->tiling_mode == I915_TILING_NONE) | |
1387 | return obj->base.size; | |
1388 | ||
1389 | /* Previous chips need a power-of-two fence region when tiling */ | |
1390 | if (INTEL_INFO(dev)->gen == 3) | |
1391 | size = 1024*1024; | |
1392 | else | |
1393 | size = 512*1024; | |
1394 | ||
1395 | while (size < obj->base.size) | |
1396 | size <<= 1; | |
1397 | ||
1398 | return size; | |
1399 | } | |
1400 | ||
de151cf6 JB |
1401 | /** |
1402 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1403 | * @obj: object to check | |
1404 | * | |
1405 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1406 | * potential fence register mapping. |
de151cf6 JB |
1407 | */ |
1408 | static uint32_t | |
05394f39 | 1409 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
de151cf6 | 1410 | { |
05394f39 | 1411 | struct drm_device *dev = obj->base.dev; |
de151cf6 JB |
1412 | |
1413 | /* | |
1414 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1415 | * if a fence register is needed for the object. | |
1416 | */ | |
a00b10c3 | 1417 | if (INTEL_INFO(dev)->gen >= 4 || |
05394f39 | 1418 | obj->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1419 | return 4096; |
1420 | ||
a00b10c3 CW |
1421 | /* |
1422 | * Previous chips need to be aligned to the size of the smallest | |
1423 | * fence register that can contain the object. | |
1424 | */ | |
05394f39 | 1425 | return i915_gem_get_gtt_size(obj); |
a00b10c3 CW |
1426 | } |
1427 | ||
5e783301 DV |
1428 | /** |
1429 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1430 | * unfenced object | |
1431 | * @obj: object to check | |
1432 | * | |
1433 | * Return the required GTT alignment for an object, only taking into account | |
1434 | * unfenced tiled surface requirements. | |
1435 | */ | |
467cffba | 1436 | uint32_t |
05394f39 | 1437 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
5e783301 | 1438 | { |
05394f39 | 1439 | struct drm_device *dev = obj->base.dev; |
5e783301 DV |
1440 | int tile_height; |
1441 | ||
1442 | /* | |
1443 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1444 | */ | |
1445 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
05394f39 | 1446 | obj->tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1447 | return 4096; |
1448 | ||
1449 | /* | |
1450 | * Older chips need unfenced tiled buffers to be aligned to the left | |
1451 | * edge of an even tile row (where tile rows are counted as if the bo is | |
1452 | * placed in a fenced gtt region). | |
1453 | */ | |
1454 | if (IS_GEN2(dev) || | |
05394f39 | 1455 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
5e783301 DV |
1456 | tile_height = 32; |
1457 | else | |
1458 | tile_height = 8; | |
1459 | ||
05394f39 | 1460 | return tile_height * obj->stride * 2; |
5e783301 DV |
1461 | } |
1462 | ||
de151cf6 | 1463 | int |
ff72145b DA |
1464 | i915_gem_mmap_gtt(struct drm_file *file, |
1465 | struct drm_device *dev, | |
1466 | uint32_t handle, | |
1467 | uint64_t *offset) | |
de151cf6 | 1468 | { |
da761a6e | 1469 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1470 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1471 | int ret; |
1472 | ||
1473 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1474 | return -ENODEV; | |
1475 | ||
76c1dec1 | 1476 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1477 | if (ret) |
76c1dec1 | 1478 | return ret; |
de151cf6 | 1479 | |
ff72145b | 1480 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1481 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1482 | ret = -ENOENT; |
1483 | goto unlock; | |
1484 | } | |
de151cf6 | 1485 | |
05394f39 | 1486 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e CW |
1487 | ret = -E2BIG; |
1488 | goto unlock; | |
1489 | } | |
1490 | ||
05394f39 | 1491 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1492 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1493 | ret = -EINVAL; |
1494 | goto out; | |
ab18282d CW |
1495 | } |
1496 | ||
05394f39 | 1497 | if (!obj->base.map_list.map) { |
de151cf6 | 1498 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1499 | if (ret) |
1500 | goto out; | |
de151cf6 JB |
1501 | } |
1502 | ||
ff72145b | 1503 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1504 | |
1d7cfea1 | 1505 | out: |
05394f39 | 1506 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1507 | unlock: |
de151cf6 | 1508 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1509 | return ret; |
de151cf6 JB |
1510 | } |
1511 | ||
ff72145b DA |
1512 | /** |
1513 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1514 | * @dev: DRM device | |
1515 | * @data: GTT mapping ioctl data | |
1516 | * @file: GEM object info | |
1517 | * | |
1518 | * Simply returns the fake offset to userspace so it can mmap it. | |
1519 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1520 | * up so we can get faults in the handler above. | |
1521 | * | |
1522 | * The fault handler will take care of binding the object into the GTT | |
1523 | * (since it may have been evicted to make room for something), allocating | |
1524 | * a fence register, and mapping the appropriate aperture address into | |
1525 | * userspace. | |
1526 | */ | |
1527 | int | |
1528 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1529 | struct drm_file *file) | |
1530 | { | |
1531 | struct drm_i915_gem_mmap_gtt *args = data; | |
1532 | ||
1533 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1534 | return -ENODEV; | |
1535 | ||
1536 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1537 | } | |
1538 | ||
1539 | ||
e5281ccd | 1540 | static int |
05394f39 | 1541 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1542 | gfp_t gfpmask) |
1543 | { | |
e5281ccd CW |
1544 | int page_count, i; |
1545 | struct address_space *mapping; | |
1546 | struct inode *inode; | |
1547 | struct page *page; | |
1548 | ||
1549 | /* Get the list of pages out of our struct file. They'll be pinned | |
1550 | * at this point until we release them. | |
1551 | */ | |
05394f39 CW |
1552 | page_count = obj->base.size / PAGE_SIZE; |
1553 | BUG_ON(obj->pages != NULL); | |
1554 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1555 | if (obj->pages == NULL) | |
e5281ccd CW |
1556 | return -ENOMEM; |
1557 | ||
05394f39 | 1558 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd CW |
1559 | mapping = inode->i_mapping; |
1560 | for (i = 0; i < page_count; i++) { | |
1561 | page = read_cache_page_gfp(mapping, i, | |
1562 | GFP_HIGHUSER | | |
1563 | __GFP_COLD | | |
1564 | __GFP_RECLAIMABLE | | |
1565 | gfpmask); | |
1566 | if (IS_ERR(page)) | |
1567 | goto err_pages; | |
1568 | ||
05394f39 | 1569 | obj->pages[i] = page; |
e5281ccd CW |
1570 | } |
1571 | ||
05394f39 | 1572 | if (obj->tiling_mode != I915_TILING_NONE) |
e5281ccd CW |
1573 | i915_gem_object_do_bit_17_swizzle(obj); |
1574 | ||
1575 | return 0; | |
1576 | ||
1577 | err_pages: | |
1578 | while (i--) | |
05394f39 | 1579 | page_cache_release(obj->pages[i]); |
e5281ccd | 1580 | |
05394f39 CW |
1581 | drm_free_large(obj->pages); |
1582 | obj->pages = NULL; | |
e5281ccd CW |
1583 | return PTR_ERR(page); |
1584 | } | |
1585 | ||
5cdf5881 | 1586 | static void |
05394f39 | 1587 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1588 | { |
05394f39 | 1589 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1590 | int i; |
1591 | ||
05394f39 | 1592 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1593 | |
05394f39 | 1594 | if (obj->tiling_mode != I915_TILING_NONE) |
280b713b EA |
1595 | i915_gem_object_save_bit_17_swizzle(obj); |
1596 | ||
05394f39 CW |
1597 | if (obj->madv == I915_MADV_DONTNEED) |
1598 | obj->dirty = 0; | |
3ef94daa CW |
1599 | |
1600 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1601 | if (obj->dirty) |
1602 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1603 | |
05394f39 CW |
1604 | if (obj->madv == I915_MADV_WILLNEED) |
1605 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1606 | |
05394f39 | 1607 | page_cache_release(obj->pages[i]); |
3ef94daa | 1608 | } |
05394f39 | 1609 | obj->dirty = 0; |
673a394b | 1610 | |
05394f39 CW |
1611 | drm_free_large(obj->pages); |
1612 | obj->pages = NULL; | |
673a394b EA |
1613 | } |
1614 | ||
54cf91dc | 1615 | void |
05394f39 | 1616 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1617 | struct intel_ring_buffer *ring, |
1618 | u32 seqno) | |
673a394b | 1619 | { |
05394f39 | 1620 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1621 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1622 | |
852835f3 | 1623 | BUG_ON(ring == NULL); |
05394f39 | 1624 | obj->ring = ring; |
673a394b EA |
1625 | |
1626 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1627 | if (!obj->active) { |
1628 | drm_gem_object_reference(&obj->base); | |
1629 | obj->active = 1; | |
673a394b | 1630 | } |
e35a41de | 1631 | |
673a394b | 1632 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1633 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1634 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1635 | |
05394f39 | 1636 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1637 | if (obj->fenced_gpu_access) { |
1638 | struct drm_i915_fence_reg *reg; | |
1639 | ||
1640 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1641 | ||
1642 | obj->last_fenced_seqno = seqno; | |
1643 | obj->last_fenced_ring = ring; | |
1644 | ||
1645 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1646 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1647 | } | |
1648 | } | |
1649 | ||
1650 | static void | |
1651 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1652 | { | |
1653 | list_del_init(&obj->ring_list); | |
1654 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1655 | } |
1656 | ||
ce44b0ea | 1657 | static void |
05394f39 | 1658 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1659 | { |
05394f39 | 1660 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1661 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1662 | |
05394f39 CW |
1663 | BUG_ON(!obj->active); |
1664 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1665 | |
1666 | i915_gem_object_move_off_active(obj); | |
1667 | } | |
1668 | ||
1669 | static void | |
1670 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1671 | { | |
1672 | struct drm_device *dev = obj->base.dev; | |
1673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1674 | ||
1675 | if (obj->pin_count != 0) | |
1676 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1677 | else | |
1678 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1679 | ||
1680 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1681 | BUG_ON(!obj->active); | |
1682 | obj->ring = NULL; | |
1683 | ||
1684 | i915_gem_object_move_off_active(obj); | |
1685 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1686 | |
1687 | obj->active = 0; | |
87ca9c8a | 1688 | obj->pending_gpu_write = false; |
caea7476 CW |
1689 | drm_gem_object_unreference(&obj->base); |
1690 | ||
1691 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1692 | } |
673a394b | 1693 | |
963b4836 CW |
1694 | /* Immediately discard the backing storage */ |
1695 | static void | |
05394f39 | 1696 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1697 | { |
bb6baf76 | 1698 | struct inode *inode; |
963b4836 | 1699 | |
ae9fed6b CW |
1700 | /* Our goal here is to return as much of the memory as |
1701 | * is possible back to the system as we are called from OOM. | |
1702 | * To do this we must instruct the shmfs to drop all of its | |
1703 | * backing pages, *now*. Here we mirror the actions taken | |
1704 | * when by shmem_delete_inode() to release the backing store. | |
1705 | */ | |
05394f39 | 1706 | inode = obj->base.filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1707 | truncate_inode_pages(inode->i_mapping, 0); |
1708 | if (inode->i_op->truncate_range) | |
1709 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 | 1710 | |
05394f39 | 1711 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1712 | } |
1713 | ||
1714 | static inline int | |
05394f39 | 1715 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1716 | { |
05394f39 | 1717 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1718 | } |
1719 | ||
63560396 | 1720 | static void |
db53a302 CW |
1721 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1722 | uint32_t flush_domains) | |
63560396 | 1723 | { |
05394f39 | 1724 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1725 | |
05394f39 | 1726 | list_for_each_entry_safe(obj, next, |
64193406 | 1727 | &ring->gpu_write_list, |
63560396 | 1728 | gpu_write_list) { |
05394f39 CW |
1729 | if (obj->base.write_domain & flush_domains) { |
1730 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1731 | |
05394f39 CW |
1732 | obj->base.write_domain = 0; |
1733 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1734 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1735 | i915_gem_next_request_seqno(ring)); |
63560396 | 1736 | |
63560396 | 1737 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1738 | obj->base.read_domains, |
63560396 DV |
1739 | old_write_domain); |
1740 | } | |
1741 | } | |
1742 | } | |
8187a2b7 | 1743 | |
3cce469c | 1744 | int |
db53a302 | 1745 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1746 | struct drm_file *file, |
db53a302 | 1747 | struct drm_i915_gem_request *request) |
673a394b | 1748 | { |
db53a302 | 1749 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b EA |
1750 | uint32_t seqno; |
1751 | int was_empty; | |
3cce469c CW |
1752 | int ret; |
1753 | ||
1754 | BUG_ON(request == NULL); | |
673a394b | 1755 | |
3cce469c CW |
1756 | ret = ring->add_request(ring, &seqno); |
1757 | if (ret) | |
1758 | return ret; | |
673a394b | 1759 | |
db53a302 | 1760 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1761 | |
1762 | request->seqno = seqno; | |
852835f3 | 1763 | request->ring = ring; |
673a394b | 1764 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1765 | was_empty = list_empty(&ring->request_list); |
1766 | list_add_tail(&request->list, &ring->request_list); | |
1767 | ||
db53a302 CW |
1768 | if (file) { |
1769 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1770 | ||
1c25595f | 1771 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1772 | request->file_priv = file_priv; |
b962442e | 1773 | list_add_tail(&request->client_list, |
f787a5f5 | 1774 | &file_priv->mm.request_list); |
1c25595f | 1775 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1776 | } |
673a394b | 1777 | |
db53a302 CW |
1778 | ring->outstanding_lazy_request = false; |
1779 | ||
f65d9421 | 1780 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1781 | mod_timer(&dev_priv->hangcheck_timer, |
1782 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1783 | if (was_empty) |
b3b079db CW |
1784 | queue_delayed_work(dev_priv->wq, |
1785 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1786 | } |
3cce469c | 1787 | return 0; |
673a394b EA |
1788 | } |
1789 | ||
f787a5f5 CW |
1790 | static inline void |
1791 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1792 | { |
1c25595f | 1793 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1794 | |
1c25595f CW |
1795 | if (!file_priv) |
1796 | return; | |
1c5d22f7 | 1797 | |
1c25595f | 1798 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1799 | if (request->file_priv) { |
1800 | list_del(&request->client_list); | |
1801 | request->file_priv = NULL; | |
1802 | } | |
1c25595f | 1803 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1804 | } |
673a394b | 1805 | |
dfaae392 CW |
1806 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1807 | struct intel_ring_buffer *ring) | |
9375e446 | 1808 | { |
dfaae392 CW |
1809 | while (!list_empty(&ring->request_list)) { |
1810 | struct drm_i915_gem_request *request; | |
673a394b | 1811 | |
dfaae392 CW |
1812 | request = list_first_entry(&ring->request_list, |
1813 | struct drm_i915_gem_request, | |
1814 | list); | |
de151cf6 | 1815 | |
dfaae392 | 1816 | list_del(&request->list); |
f787a5f5 | 1817 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1818 | kfree(request); |
1819 | } | |
673a394b | 1820 | |
dfaae392 | 1821 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1822 | struct drm_i915_gem_object *obj; |
9375e446 | 1823 | |
05394f39 CW |
1824 | obj = list_first_entry(&ring->active_list, |
1825 | struct drm_i915_gem_object, | |
1826 | ring_list); | |
9375e446 | 1827 | |
05394f39 CW |
1828 | obj->base.write_domain = 0; |
1829 | list_del_init(&obj->gpu_write_list); | |
1830 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1831 | } |
1832 | } | |
1833 | ||
312817a3 CW |
1834 | static void i915_gem_reset_fences(struct drm_device *dev) |
1835 | { | |
1836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1837 | int i; | |
1838 | ||
1839 | for (i = 0; i < 16; i++) { | |
1840 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
7d2cb39c CW |
1841 | struct drm_i915_gem_object *obj = reg->obj; |
1842 | ||
1843 | if (!obj) | |
1844 | continue; | |
1845 | ||
1846 | if (obj->tiling_mode) | |
1847 | i915_gem_release_mmap(obj); | |
1848 | ||
d9e86c0e CW |
1849 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1850 | reg->obj->fenced_gpu_access = false; | |
1851 | reg->obj->last_fenced_seqno = 0; | |
1852 | reg->obj->last_fenced_ring = NULL; | |
1853 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1854 | } |
1855 | } | |
1856 | ||
069efc1d | 1857 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1858 | { |
77f01230 | 1859 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1860 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1861 | int i; |
673a394b | 1862 | |
1ec14ad3 CW |
1863 | for (i = 0; i < I915_NUM_RINGS; i++) |
1864 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1865 | |
1866 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1867 | * to be lost on reset along with the data, so simply move the | |
1868 | * lost bo to the inactive list. | |
1869 | */ | |
1870 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
05394f39 CW |
1871 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
1872 | struct drm_i915_gem_object, | |
1873 | mm_list); | |
dfaae392 | 1874 | |
05394f39 CW |
1875 | obj->base.write_domain = 0; |
1876 | list_del_init(&obj->gpu_write_list); | |
1877 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1878 | } |
1879 | ||
1880 | /* Move everything out of the GPU domains to ensure we do any | |
1881 | * necessary invalidation upon reuse. | |
1882 | */ | |
05394f39 | 1883 | list_for_each_entry(obj, |
77f01230 | 1884 | &dev_priv->mm.inactive_list, |
69dc4987 | 1885 | mm_list) |
77f01230 | 1886 | { |
05394f39 | 1887 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1888 | } |
069efc1d CW |
1889 | |
1890 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1891 | i915_gem_reset_fences(dev); |
673a394b EA |
1892 | } |
1893 | ||
1894 | /** | |
1895 | * This function clears the request list as sequence numbers are passed. | |
1896 | */ | |
b09a1fec | 1897 | static void |
db53a302 | 1898 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1899 | { |
673a394b | 1900 | uint32_t seqno; |
1ec14ad3 | 1901 | int i; |
673a394b | 1902 | |
db53a302 | 1903 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1904 | return; |
1905 | ||
db53a302 | 1906 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1907 | |
78501eac | 1908 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1909 | |
076e2c0e | 1910 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1911 | if (seqno >= ring->sync_seqno[i]) |
1912 | ring->sync_seqno[i] = 0; | |
1913 | ||
852835f3 | 1914 | while (!list_empty(&ring->request_list)) { |
673a394b | 1915 | struct drm_i915_gem_request *request; |
673a394b | 1916 | |
852835f3 | 1917 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1918 | struct drm_i915_gem_request, |
1919 | list); | |
673a394b | 1920 | |
dfaae392 | 1921 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1922 | break; |
1923 | ||
db53a302 | 1924 | trace_i915_gem_request_retire(ring, request->seqno); |
b84d5f0c CW |
1925 | |
1926 | list_del(&request->list); | |
f787a5f5 | 1927 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1928 | kfree(request); |
1929 | } | |
673a394b | 1930 | |
b84d5f0c CW |
1931 | /* Move any buffers on the active list that are no longer referenced |
1932 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1933 | */ | |
1934 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1935 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1936 | |
05394f39 CW |
1937 | obj= list_first_entry(&ring->active_list, |
1938 | struct drm_i915_gem_object, | |
1939 | ring_list); | |
673a394b | 1940 | |
05394f39 | 1941 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1942 | break; |
b84d5f0c | 1943 | |
05394f39 | 1944 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1945 | i915_gem_object_move_to_flushing(obj); |
1946 | else | |
1947 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1948 | } |
9d34e5db | 1949 | |
db53a302 CW |
1950 | if (unlikely(ring->trace_irq_seqno && |
1951 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1952 | ring->irq_put(ring); |
db53a302 | 1953 | ring->trace_irq_seqno = 0; |
9d34e5db | 1954 | } |
23bc5982 | 1955 | |
db53a302 | 1956 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1957 | } |
1958 | ||
b09a1fec CW |
1959 | void |
1960 | i915_gem_retire_requests(struct drm_device *dev) | |
1961 | { | |
1962 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1963 | int i; |
b09a1fec | 1964 | |
be72615b | 1965 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1966 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1967 | |
1968 | /* We must be careful that during unbind() we do not | |
1969 | * accidentally infinitely recurse into retire requests. | |
1970 | * Currently: | |
1971 | * retire -> free -> unbind -> wait -> retire_ring | |
1972 | */ | |
05394f39 | 1973 | list_for_each_entry_safe(obj, next, |
be72615b | 1974 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1975 | mm_list) |
05394f39 | 1976 | i915_gem_free_object_tail(obj); |
be72615b CW |
1977 | } |
1978 | ||
1ec14ad3 | 1979 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1980 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1981 | } |
1982 | ||
75ef9da2 | 1983 | static void |
673a394b EA |
1984 | i915_gem_retire_work_handler(struct work_struct *work) |
1985 | { | |
1986 | drm_i915_private_t *dev_priv; | |
1987 | struct drm_device *dev; | |
0a58705b CW |
1988 | bool idle; |
1989 | int i; | |
673a394b EA |
1990 | |
1991 | dev_priv = container_of(work, drm_i915_private_t, | |
1992 | mm.retire_work.work); | |
1993 | dev = dev_priv->dev; | |
1994 | ||
891b48cf CW |
1995 | /* Come back later if the device is busy... */ |
1996 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1997 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1998 | return; | |
1999 | } | |
2000 | ||
b09a1fec | 2001 | i915_gem_retire_requests(dev); |
d1b851fc | 2002 | |
0a58705b CW |
2003 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2004 | * objects indefinitely. | |
2005 | */ | |
2006 | idle = true; | |
2007 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
2008 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
2009 | ||
2010 | if (!list_empty(&ring->gpu_write_list)) { | |
2011 | struct drm_i915_gem_request *request; | |
2012 | int ret; | |
2013 | ||
db53a302 CW |
2014 | ret = i915_gem_flush_ring(ring, |
2015 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
2016 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
2017 | if (ret || request == NULL || | |
db53a302 | 2018 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
2019 | kfree(request); |
2020 | } | |
2021 | ||
2022 | idle &= list_empty(&ring->request_list); | |
2023 | } | |
2024 | ||
2025 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 2026 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 2027 | |
673a394b EA |
2028 | mutex_unlock(&dev->struct_mutex); |
2029 | } | |
2030 | ||
db53a302 CW |
2031 | /** |
2032 | * Waits for a sequence number to be signaled, and cleans up the | |
2033 | * request and object lists appropriately for that event. | |
2034 | */ | |
5a5a0c64 | 2035 | int |
db53a302 | 2036 | i915_wait_request(struct intel_ring_buffer *ring, |
ce453d81 | 2037 | uint32_t seqno) |
673a394b | 2038 | { |
db53a302 | 2039 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 2040 | u32 ier; |
673a394b EA |
2041 | int ret = 0; |
2042 | ||
2043 | BUG_ON(seqno == 0); | |
2044 | ||
d9bc7e9f CW |
2045 | if (atomic_read(&dev_priv->mm.wedged)) { |
2046 | struct completion *x = &dev_priv->error_completion; | |
2047 | bool recovery_complete; | |
2048 | unsigned long flags; | |
2049 | ||
2050 | /* Give the error handler a chance to run. */ | |
2051 | spin_lock_irqsave(&x->wait.lock, flags); | |
2052 | recovery_complete = x->done > 0; | |
2053 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
2054 | ||
2055 | return recovery_complete ? -EIO : -EAGAIN; | |
2056 | } | |
30dbf0c0 | 2057 | |
5d97eb69 | 2058 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
2059 | struct drm_i915_gem_request *request; |
2060 | ||
2061 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2062 | if (request == NULL) | |
e35a41de | 2063 | return -ENOMEM; |
3cce469c | 2064 | |
db53a302 | 2065 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
2066 | if (ret) { |
2067 | kfree(request); | |
2068 | return ret; | |
2069 | } | |
2070 | ||
2071 | seqno = request->seqno; | |
e35a41de | 2072 | } |
ffed1d09 | 2073 | |
78501eac | 2074 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 2075 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
2076 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2077 | else | |
2078 | ier = I915_READ(IER); | |
802c7eb6 JB |
2079 | if (!ier) { |
2080 | DRM_ERROR("something (likely vbetool) disabled " | |
2081 | "interrupts, re-enabling\n"); | |
db53a302 CW |
2082 | i915_driver_irq_preinstall(ring->dev); |
2083 | i915_driver_irq_postinstall(ring->dev); | |
802c7eb6 JB |
2084 | } |
2085 | ||
db53a302 | 2086 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 2087 | |
b2223497 | 2088 | ring->waiting_seqno = seqno; |
b13c2b96 | 2089 | if (ring->irq_get(ring)) { |
ce453d81 | 2090 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
2091 | ret = wait_event_interruptible(ring->irq_queue, |
2092 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2093 | || atomic_read(&dev_priv->mm.wedged)); | |
2094 | else | |
2095 | wait_event(ring->irq_queue, | |
2096 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2097 | || atomic_read(&dev_priv->mm.wedged)); | |
2098 | ||
2099 | ring->irq_put(ring); | |
b5ba177d CW |
2100 | } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring), |
2101 | seqno) || | |
2102 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
2103 | ret = -EBUSY; | |
b2223497 | 2104 | ring->waiting_seqno = 0; |
1c5d22f7 | 2105 | |
db53a302 | 2106 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 2107 | } |
ba1234d1 | 2108 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2109 | ret = -EAGAIN; |
673a394b EA |
2110 | |
2111 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2112 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2113 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2114 | dev_priv->next_seqno); |
673a394b EA |
2115 | |
2116 | /* Directly dispatch request retiring. While we have the work queue | |
2117 | * to handle this, the waiter on a request often wants an associated | |
2118 | * buffer to have made it to the inactive list, and we would need | |
2119 | * a separate wait queue to handle that. | |
2120 | */ | |
2121 | if (ret == 0) | |
db53a302 | 2122 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
2123 | |
2124 | return ret; | |
2125 | } | |
2126 | ||
673a394b EA |
2127 | /** |
2128 | * Ensures that all rendering to the object has completed and the object is | |
2129 | * safe to unbind from the GTT or access from the CPU. | |
2130 | */ | |
54cf91dc | 2131 | int |
ce453d81 | 2132 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 2133 | { |
673a394b EA |
2134 | int ret; |
2135 | ||
e47c68e9 EA |
2136 | /* This function only exists to support waiting for existing rendering, |
2137 | * not for emitting required flushes. | |
673a394b | 2138 | */ |
05394f39 | 2139 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2140 | |
2141 | /* If there is rendering queued on the buffer being evicted, wait for | |
2142 | * it. | |
2143 | */ | |
05394f39 | 2144 | if (obj->active) { |
ce453d81 | 2145 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno); |
2cf34d7b | 2146 | if (ret) |
673a394b EA |
2147 | return ret; |
2148 | } | |
2149 | ||
2150 | return 0; | |
2151 | } | |
2152 | ||
2153 | /** | |
2154 | * Unbinds an object from the GTT aperture. | |
2155 | */ | |
0f973f27 | 2156 | int |
05394f39 | 2157 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2158 | { |
673a394b EA |
2159 | int ret = 0; |
2160 | ||
05394f39 | 2161 | if (obj->gtt_space == NULL) |
673a394b EA |
2162 | return 0; |
2163 | ||
05394f39 | 2164 | if (obj->pin_count != 0) { |
673a394b EA |
2165 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2166 | return -EINVAL; | |
2167 | } | |
2168 | ||
5323fd04 EA |
2169 | /* blow away mappings if mapped through GTT */ |
2170 | i915_gem_release_mmap(obj); | |
2171 | ||
673a394b EA |
2172 | /* Move the object to the CPU domain to ensure that |
2173 | * any possible CPU writes while it's not in the GTT | |
2174 | * are flushed when we go to remap it. This will | |
2175 | * also ensure that all pending GPU writes are finished | |
2176 | * before we unbind. | |
2177 | */ | |
e47c68e9 | 2178 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2179 | if (ret == -ERESTARTSYS) |
673a394b | 2180 | return ret; |
8dc1775d CW |
2181 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2182 | * should be safe and we need to cleanup or else we might | |
2183 | * cause memory corruption through use-after-free. | |
2184 | */ | |
812ed492 CW |
2185 | if (ret) { |
2186 | i915_gem_clflush_object(obj); | |
05394f39 | 2187 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2188 | } |
673a394b | 2189 | |
96b47b65 | 2190 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2191 | ret = i915_gem_object_put_fence(obj); |
2192 | if (ret == -ERESTARTSYS) | |
2193 | return ret; | |
96b47b65 | 2194 | |
db53a302 CW |
2195 | trace_i915_gem_object_unbind(obj); |
2196 | ||
7c2e6fdf | 2197 | i915_gem_gtt_unbind_object(obj); |
e5281ccd | 2198 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2199 | |
6299f992 | 2200 | list_del_init(&obj->gtt_list); |
05394f39 | 2201 | list_del_init(&obj->mm_list); |
75e9e915 | 2202 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2203 | obj->map_and_fenceable = true; |
673a394b | 2204 | |
05394f39 CW |
2205 | drm_mm_put_block(obj->gtt_space); |
2206 | obj->gtt_space = NULL; | |
2207 | obj->gtt_offset = 0; | |
673a394b | 2208 | |
05394f39 | 2209 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2210 | i915_gem_object_truncate(obj); |
2211 | ||
8dc1775d | 2212 | return ret; |
673a394b EA |
2213 | } |
2214 | ||
88241785 | 2215 | int |
db53a302 | 2216 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2217 | uint32_t invalidate_domains, |
2218 | uint32_t flush_domains) | |
2219 | { | |
88241785 CW |
2220 | int ret; |
2221 | ||
db53a302 CW |
2222 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2223 | ||
88241785 CW |
2224 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2225 | if (ret) | |
2226 | return ret; | |
2227 | ||
db53a302 | 2228 | i915_gem_process_flushing_list(ring, flush_domains); |
88241785 | 2229 | return 0; |
54cf91dc CW |
2230 | } |
2231 | ||
db53a302 | 2232 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2233 | { |
88241785 CW |
2234 | int ret; |
2235 | ||
395b70be | 2236 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2237 | return 0; |
2238 | ||
88241785 | 2239 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2240 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2241 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2242 | if (ret) |
2243 | return ret; | |
2244 | } | |
2245 | ||
ce453d81 | 2246 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2247 | } |
2248 | ||
b47eb4a2 | 2249 | int |
4df2faf4 DV |
2250 | i915_gpu_idle(struct drm_device *dev) |
2251 | { | |
2252 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2253 | bool lists_empty; | |
1ec14ad3 | 2254 | int ret, i; |
4df2faf4 | 2255 | |
d1b851fc | 2256 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2257 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2258 | if (lists_empty) |
2259 | return 0; | |
2260 | ||
2261 | /* Flush everything onto the inactive list. */ | |
1ec14ad3 | 2262 | for (i = 0; i < I915_NUM_RINGS; i++) { |
db53a302 | 2263 | ret = i915_ring_idle(&dev_priv->ring[i]); |
1ec14ad3 CW |
2264 | if (ret) |
2265 | return ret; | |
2266 | } | |
4df2faf4 | 2267 | |
8a1a49f9 | 2268 | return 0; |
4df2faf4 DV |
2269 | } |
2270 | ||
c6642782 DV |
2271 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2272 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2273 | { |
05394f39 | 2274 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2275 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2276 | u32 size = obj->gtt_space->size; |
2277 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2278 | uint64_t val; |
2279 | ||
05394f39 | 2280 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2281 | 0xfffff000) << 32; |
05394f39 CW |
2282 | val |= obj->gtt_offset & 0xfffff000; |
2283 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2284 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2285 | ||
05394f39 | 2286 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2287 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2288 | val |= I965_FENCE_REG_VALID; | |
2289 | ||
c6642782 DV |
2290 | if (pipelined) { |
2291 | int ret = intel_ring_begin(pipelined, 6); | |
2292 | if (ret) | |
2293 | return ret; | |
2294 | ||
2295 | intel_ring_emit(pipelined, MI_NOOP); | |
2296 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2297 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2298 | intel_ring_emit(pipelined, (u32)val); | |
2299 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2300 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2301 | intel_ring_advance(pipelined); | |
2302 | } else | |
2303 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2304 | ||
2305 | return 0; | |
4e901fdc EA |
2306 | } |
2307 | ||
c6642782 DV |
2308 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2309 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2310 | { |
05394f39 | 2311 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2312 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2313 | u32 size = obj->gtt_space->size; |
2314 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2315 | uint64_t val; |
2316 | ||
05394f39 | 2317 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2318 | 0xfffff000) << 32; |
05394f39 CW |
2319 | val |= obj->gtt_offset & 0xfffff000; |
2320 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2321 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2322 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2323 | val |= I965_FENCE_REG_VALID; | |
2324 | ||
c6642782 DV |
2325 | if (pipelined) { |
2326 | int ret = intel_ring_begin(pipelined, 6); | |
2327 | if (ret) | |
2328 | return ret; | |
2329 | ||
2330 | intel_ring_emit(pipelined, MI_NOOP); | |
2331 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2332 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2333 | intel_ring_emit(pipelined, (u32)val); | |
2334 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2335 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2336 | intel_ring_advance(pipelined); | |
2337 | } else | |
2338 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2339 | ||
2340 | return 0; | |
de151cf6 JB |
2341 | } |
2342 | ||
c6642782 DV |
2343 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2344 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2345 | { |
05394f39 | 2346 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2347 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2348 | u32 size = obj->gtt_space->size; |
c6642782 | 2349 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2350 | int tile_width; |
de151cf6 | 2351 | |
c6642782 DV |
2352 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2353 | (size & -size) != size || | |
2354 | (obj->gtt_offset & (size - 1)), | |
2355 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2356 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2357 | return -EINVAL; | |
de151cf6 | 2358 | |
c6642782 | 2359 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2360 | tile_width = 128; |
de151cf6 | 2361 | else |
0f973f27 JB |
2362 | tile_width = 512; |
2363 | ||
2364 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2365 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2366 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2367 | |
05394f39 CW |
2368 | val = obj->gtt_offset; |
2369 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2370 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2371 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2372 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2373 | val |= I830_FENCE_REG_VALID; | |
2374 | ||
05394f39 | 2375 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2376 | if (fence_reg < 8) |
2377 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2378 | else |
a00b10c3 | 2379 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2380 | |
2381 | if (pipelined) { | |
2382 | int ret = intel_ring_begin(pipelined, 4); | |
2383 | if (ret) | |
2384 | return ret; | |
2385 | ||
2386 | intel_ring_emit(pipelined, MI_NOOP); | |
2387 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2388 | intel_ring_emit(pipelined, fence_reg); | |
2389 | intel_ring_emit(pipelined, val); | |
2390 | intel_ring_advance(pipelined); | |
2391 | } else | |
2392 | I915_WRITE(fence_reg, val); | |
2393 | ||
2394 | return 0; | |
de151cf6 JB |
2395 | } |
2396 | ||
c6642782 DV |
2397 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2398 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2399 | { |
05394f39 | 2400 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2401 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2402 | u32 size = obj->gtt_space->size; |
2403 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2404 | uint32_t val; |
2405 | uint32_t pitch_val; | |
2406 | ||
c6642782 DV |
2407 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2408 | (size & -size) != size || | |
2409 | (obj->gtt_offset & (size - 1)), | |
2410 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2411 | obj->gtt_offset, size)) | |
2412 | return -EINVAL; | |
de151cf6 | 2413 | |
05394f39 | 2414 | pitch_val = obj->stride / 128; |
e76a16de | 2415 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2416 | |
05394f39 CW |
2417 | val = obj->gtt_offset; |
2418 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2419 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2420 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2421 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2422 | val |= I830_FENCE_REG_VALID; | |
2423 | ||
c6642782 DV |
2424 | if (pipelined) { |
2425 | int ret = intel_ring_begin(pipelined, 4); | |
2426 | if (ret) | |
2427 | return ret; | |
2428 | ||
2429 | intel_ring_emit(pipelined, MI_NOOP); | |
2430 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2431 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2432 | intel_ring_emit(pipelined, val); | |
2433 | intel_ring_advance(pipelined); | |
2434 | } else | |
2435 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2436 | ||
2437 | return 0; | |
de151cf6 JB |
2438 | } |
2439 | ||
d9e86c0e CW |
2440 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2441 | { | |
2442 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2443 | } | |
2444 | ||
2445 | static int | |
2446 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
ce453d81 | 2447 | struct intel_ring_buffer *pipelined) |
d9e86c0e CW |
2448 | { |
2449 | int ret; | |
2450 | ||
2451 | if (obj->fenced_gpu_access) { | |
88241785 | 2452 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2453 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2454 | 0, obj->base.write_domain); |
2455 | if (ret) | |
2456 | return ret; | |
2457 | } | |
d9e86c0e CW |
2458 | |
2459 | obj->fenced_gpu_access = false; | |
2460 | } | |
2461 | ||
2462 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2463 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2464 | obj->last_fenced_seqno)) { | |
db53a302 | 2465 | ret = i915_wait_request(obj->last_fenced_ring, |
ce453d81 | 2466 | obj->last_fenced_seqno); |
d9e86c0e CW |
2467 | if (ret) |
2468 | return ret; | |
2469 | } | |
2470 | ||
2471 | obj->last_fenced_seqno = 0; | |
2472 | obj->last_fenced_ring = NULL; | |
2473 | } | |
2474 | ||
63256ec5 CW |
2475 | /* Ensure that all CPU reads are completed before installing a fence |
2476 | * and all writes before removing the fence. | |
2477 | */ | |
2478 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2479 | mb(); | |
2480 | ||
d9e86c0e CW |
2481 | return 0; |
2482 | } | |
2483 | ||
2484 | int | |
2485 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2486 | { | |
2487 | int ret; | |
2488 | ||
2489 | if (obj->tiling_mode) | |
2490 | i915_gem_release_mmap(obj); | |
2491 | ||
ce453d81 | 2492 | ret = i915_gem_object_flush_fence(obj, NULL); |
d9e86c0e CW |
2493 | if (ret) |
2494 | return ret; | |
2495 | ||
2496 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2497 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2498 | i915_gem_clear_fence_reg(obj->base.dev, | |
2499 | &dev_priv->fence_regs[obj->fence_reg]); | |
2500 | ||
2501 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2502 | } | |
2503 | ||
2504 | return 0; | |
2505 | } | |
2506 | ||
2507 | static struct drm_i915_fence_reg * | |
2508 | i915_find_fence_reg(struct drm_device *dev, | |
2509 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2510 | { |
ae3db24a | 2511 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2512 | struct drm_i915_fence_reg *reg, *first, *avail; |
2513 | int i; | |
ae3db24a DV |
2514 | |
2515 | /* First try to find a free reg */ | |
d9e86c0e | 2516 | avail = NULL; |
ae3db24a DV |
2517 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2518 | reg = &dev_priv->fence_regs[i]; | |
2519 | if (!reg->obj) | |
d9e86c0e | 2520 | return reg; |
ae3db24a | 2521 | |
05394f39 | 2522 | if (!reg->obj->pin_count) |
d9e86c0e | 2523 | avail = reg; |
ae3db24a DV |
2524 | } |
2525 | ||
d9e86c0e CW |
2526 | if (avail == NULL) |
2527 | return NULL; | |
ae3db24a DV |
2528 | |
2529 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2530 | avail = first = NULL; |
2531 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
2532 | if (reg->obj->pin_count) | |
ae3db24a DV |
2533 | continue; |
2534 | ||
d9e86c0e CW |
2535 | if (first == NULL) |
2536 | first = reg; | |
2537 | ||
2538 | if (!pipelined || | |
2539 | !reg->obj->last_fenced_ring || | |
2540 | reg->obj->last_fenced_ring == pipelined) { | |
2541 | avail = reg; | |
2542 | break; | |
2543 | } | |
ae3db24a DV |
2544 | } |
2545 | ||
d9e86c0e CW |
2546 | if (avail == NULL) |
2547 | avail = first; | |
ae3db24a | 2548 | |
a00b10c3 | 2549 | return avail; |
ae3db24a DV |
2550 | } |
2551 | ||
de151cf6 | 2552 | /** |
d9e86c0e | 2553 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2554 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2555 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2556 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2557 | * |
2558 | * When mapping objects through the GTT, userspace wants to be able to write | |
2559 | * to them without having to worry about swizzling if the object is tiled. | |
2560 | * | |
2561 | * This function walks the fence regs looking for a free one for @obj, | |
2562 | * stealing one if it can't find any. | |
2563 | * | |
2564 | * It then sets up the reg based on the object's properties: address, pitch | |
2565 | * and tiling format. | |
2566 | */ | |
8c4b8c3f | 2567 | int |
d9e86c0e | 2568 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 2569 | struct intel_ring_buffer *pipelined) |
de151cf6 | 2570 | { |
05394f39 | 2571 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2572 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2573 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2574 | int ret; |
de151cf6 | 2575 | |
6bda10d1 CW |
2576 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2577 | pipelined = NULL; | |
2578 | ||
d9e86c0e | 2579 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2580 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2581 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2582 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e | 2583 | |
29c5a587 CW |
2584 | if (obj->tiling_changed) { |
2585 | ret = i915_gem_object_flush_fence(obj, pipelined); | |
2586 | if (ret) | |
2587 | return ret; | |
2588 | ||
2589 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2590 | pipelined = NULL; | |
2591 | ||
2592 | if (pipelined) { | |
2593 | reg->setup_seqno = | |
2594 | i915_gem_next_request_seqno(pipelined); | |
2595 | obj->last_fenced_seqno = reg->setup_seqno; | |
2596 | obj->last_fenced_ring = pipelined; | |
2597 | } | |
2598 | ||
2599 | goto update; | |
2600 | } | |
d9e86c0e CW |
2601 | |
2602 | if (!pipelined) { | |
2603 | if (reg->setup_seqno) { | |
2604 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2605 | reg->setup_seqno)) { | |
db53a302 | 2606 | ret = i915_wait_request(obj->last_fenced_ring, |
ce453d81 | 2607 | reg->setup_seqno); |
d9e86c0e CW |
2608 | if (ret) |
2609 | return ret; | |
2610 | } | |
2611 | ||
2612 | reg->setup_seqno = 0; | |
2613 | } | |
2614 | } else if (obj->last_fenced_ring && | |
2615 | obj->last_fenced_ring != pipelined) { | |
ce453d81 | 2616 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e CW |
2617 | if (ret) |
2618 | return ret; | |
d9e86c0e CW |
2619 | } |
2620 | ||
a09ba7fa EA |
2621 | return 0; |
2622 | } | |
2623 | ||
d9e86c0e CW |
2624 | reg = i915_find_fence_reg(dev, pipelined); |
2625 | if (reg == NULL) | |
2626 | return -ENOSPC; | |
de151cf6 | 2627 | |
ce453d81 | 2628 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e | 2629 | if (ret) |
ae3db24a | 2630 | return ret; |
de151cf6 | 2631 | |
d9e86c0e CW |
2632 | if (reg->obj) { |
2633 | struct drm_i915_gem_object *old = reg->obj; | |
2634 | ||
2635 | drm_gem_object_reference(&old->base); | |
2636 | ||
2637 | if (old->tiling_mode) | |
2638 | i915_gem_release_mmap(old); | |
2639 | ||
ce453d81 | 2640 | ret = i915_gem_object_flush_fence(old, pipelined); |
d9e86c0e CW |
2641 | if (ret) { |
2642 | drm_gem_object_unreference(&old->base); | |
2643 | return ret; | |
2644 | } | |
2645 | ||
2646 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2647 | pipelined = NULL; | |
2648 | ||
2649 | old->fence_reg = I915_FENCE_REG_NONE; | |
2650 | old->last_fenced_ring = pipelined; | |
2651 | old->last_fenced_seqno = | |
db53a302 | 2652 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2653 | |
2654 | drm_gem_object_unreference(&old->base); | |
2655 | } else if (obj->last_fenced_seqno == 0) | |
2656 | pipelined = NULL; | |
a09ba7fa | 2657 | |
de151cf6 | 2658 | reg->obj = obj; |
d9e86c0e CW |
2659 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2660 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2661 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2662 | |
d9e86c0e | 2663 | reg->setup_seqno = |
db53a302 | 2664 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2665 | obj->last_fenced_seqno = reg->setup_seqno; |
2666 | ||
2667 | update: | |
2668 | obj->tiling_changed = false; | |
e259befd CW |
2669 | switch (INTEL_INFO(dev)->gen) { |
2670 | case 6: | |
c6642782 | 2671 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2672 | break; |
2673 | case 5: | |
2674 | case 4: | |
c6642782 | 2675 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2676 | break; |
2677 | case 3: | |
c6642782 | 2678 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2679 | break; |
2680 | case 2: | |
c6642782 | 2681 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2682 | break; |
2683 | } | |
d9ddcb96 | 2684 | |
c6642782 | 2685 | return ret; |
de151cf6 JB |
2686 | } |
2687 | ||
2688 | /** | |
2689 | * i915_gem_clear_fence_reg - clear out fence register info | |
2690 | * @obj: object to clear | |
2691 | * | |
2692 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2693 | * data structures in dev_priv and obj. |
de151cf6 JB |
2694 | */ |
2695 | static void | |
d9e86c0e CW |
2696 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2697 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2698 | { |
79e53945 | 2699 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2700 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2701 | |
e259befd CW |
2702 | switch (INTEL_INFO(dev)->gen) { |
2703 | case 6: | |
d9e86c0e | 2704 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2705 | break; |
2706 | case 5: | |
2707 | case 4: | |
d9e86c0e | 2708 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2709 | break; |
2710 | case 3: | |
d9e86c0e CW |
2711 | if (fence_reg >= 8) |
2712 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2713 | else |
e259befd | 2714 | case 2: |
d9e86c0e | 2715 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2716 | |
2717 | I915_WRITE(fence_reg, 0); | |
e259befd | 2718 | break; |
dc529a4f | 2719 | } |
de151cf6 | 2720 | |
007cc8ac | 2721 | list_del_init(®->lru_list); |
d9e86c0e CW |
2722 | reg->obj = NULL; |
2723 | reg->setup_seqno = 0; | |
52dc7d32 CW |
2724 | } |
2725 | ||
673a394b EA |
2726 | /** |
2727 | * Finds free space in the GTT aperture and binds the object there. | |
2728 | */ | |
2729 | static int | |
05394f39 | 2730 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2731 | unsigned alignment, |
75e9e915 | 2732 | bool map_and_fenceable) |
673a394b | 2733 | { |
05394f39 | 2734 | struct drm_device *dev = obj->base.dev; |
673a394b | 2735 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2736 | struct drm_mm_node *free_space; |
a00b10c3 | 2737 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2738 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2739 | bool mappable, fenceable; |
07f73f69 | 2740 | int ret; |
673a394b | 2741 | |
05394f39 | 2742 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2743 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2744 | return -EINVAL; | |
2745 | } | |
2746 | ||
05394f39 CW |
2747 | fence_size = i915_gem_get_gtt_size(obj); |
2748 | fence_alignment = i915_gem_get_gtt_alignment(obj); | |
2749 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); | |
a00b10c3 | 2750 | |
673a394b | 2751 | if (alignment == 0) |
5e783301 DV |
2752 | alignment = map_and_fenceable ? fence_alignment : |
2753 | unfenced_alignment; | |
75e9e915 | 2754 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2755 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2756 | return -EINVAL; | |
2757 | } | |
2758 | ||
05394f39 | 2759 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2760 | |
654fc607 CW |
2761 | /* If the object is bigger than the entire aperture, reject it early |
2762 | * before evicting everything in a vain attempt to find space. | |
2763 | */ | |
05394f39 | 2764 | if (obj->base.size > |
75e9e915 | 2765 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2766 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2767 | return -E2BIG; | |
2768 | } | |
2769 | ||
673a394b | 2770 | search_free: |
75e9e915 | 2771 | if (map_and_fenceable) |
920afa77 DV |
2772 | free_space = |
2773 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2774 | size, alignment, 0, |
920afa77 DV |
2775 | dev_priv->mm.gtt_mappable_end, |
2776 | 0); | |
2777 | else | |
2778 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2779 | size, alignment, 0); |
920afa77 DV |
2780 | |
2781 | if (free_space != NULL) { | |
75e9e915 | 2782 | if (map_and_fenceable) |
05394f39 | 2783 | obj->gtt_space = |
920afa77 | 2784 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2785 | size, alignment, 0, |
920afa77 DV |
2786 | dev_priv->mm.gtt_mappable_end, |
2787 | 0); | |
2788 | else | |
05394f39 | 2789 | obj->gtt_space = |
a00b10c3 | 2790 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2791 | } |
05394f39 | 2792 | if (obj->gtt_space == NULL) { |
673a394b EA |
2793 | /* If the gtt is empty and we're still having trouble |
2794 | * fitting our object in, we're out of memory. | |
2795 | */ | |
75e9e915 DV |
2796 | ret = i915_gem_evict_something(dev, size, alignment, |
2797 | map_and_fenceable); | |
9731129c | 2798 | if (ret) |
673a394b | 2799 | return ret; |
9731129c | 2800 | |
673a394b EA |
2801 | goto search_free; |
2802 | } | |
2803 | ||
e5281ccd | 2804 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2805 | if (ret) { |
05394f39 CW |
2806 | drm_mm_put_block(obj->gtt_space); |
2807 | obj->gtt_space = NULL; | |
07f73f69 CW |
2808 | |
2809 | if (ret == -ENOMEM) { | |
809b6334 CW |
2810 | /* first try to reclaim some memory by clearing the GTT */ |
2811 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2812 | if (ret) { |
07f73f69 | 2813 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2814 | if (gfpmask) { |
2815 | gfpmask = 0; | |
2816 | goto search_free; | |
07f73f69 CW |
2817 | } |
2818 | ||
809b6334 | 2819 | return -ENOMEM; |
07f73f69 CW |
2820 | } |
2821 | ||
2822 | goto search_free; | |
2823 | } | |
2824 | ||
673a394b EA |
2825 | return ret; |
2826 | } | |
2827 | ||
7c2e6fdf DV |
2828 | ret = i915_gem_gtt_bind_object(obj); |
2829 | if (ret) { | |
e5281ccd | 2830 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2831 | drm_mm_put_block(obj->gtt_space); |
2832 | obj->gtt_space = NULL; | |
07f73f69 | 2833 | |
809b6334 | 2834 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2835 | return ret; |
07f73f69 CW |
2836 | |
2837 | goto search_free; | |
673a394b | 2838 | } |
673a394b | 2839 | |
6299f992 | 2840 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2841 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2842 | |
673a394b EA |
2843 | /* Assert that the object is not currently in any GPU domain. As it |
2844 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2845 | * a GPU cache | |
2846 | */ | |
05394f39 CW |
2847 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2848 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2849 | |
6299f992 | 2850 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2851 | |
75e9e915 | 2852 | fenceable = |
05394f39 CW |
2853 | obj->gtt_space->size == fence_size && |
2854 | (obj->gtt_space->start & (fence_alignment -1)) == 0; | |
a00b10c3 | 2855 | |
75e9e915 | 2856 | mappable = |
05394f39 | 2857 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2858 | |
05394f39 | 2859 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2860 | |
db53a302 | 2861 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2862 | return 0; |
2863 | } | |
2864 | ||
2865 | void | |
05394f39 | 2866 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2867 | { |
673a394b EA |
2868 | /* If we don't have a page list set up, then we're not pinned |
2869 | * to GPU, and we can ignore the cache flush because it'll happen | |
2870 | * again at bind time. | |
2871 | */ | |
05394f39 | 2872 | if (obj->pages == NULL) |
673a394b EA |
2873 | return; |
2874 | ||
1c5d22f7 | 2875 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2876 | |
05394f39 | 2877 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2878 | } |
2879 | ||
e47c68e9 | 2880 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2881 | static int |
3619df03 | 2882 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2883 | { |
05394f39 | 2884 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2885 | return 0; |
e47c68e9 EA |
2886 | |
2887 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2888 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2889 | } |
2890 | ||
2891 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2892 | static void | |
05394f39 | 2893 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2894 | { |
1c5d22f7 CW |
2895 | uint32_t old_write_domain; |
2896 | ||
05394f39 | 2897 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2898 | return; |
2899 | ||
63256ec5 | 2900 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2901 | * to it immediately go to main memory as far as we know, so there's |
2902 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2903 | * |
2904 | * However, we do have to enforce the order so that all writes through | |
2905 | * the GTT land before any writes to the device, such as updates to | |
2906 | * the GATT itself. | |
e47c68e9 | 2907 | */ |
63256ec5 CW |
2908 | wmb(); |
2909 | ||
4a684a41 CW |
2910 | i915_gem_release_mmap(obj); |
2911 | ||
05394f39 CW |
2912 | old_write_domain = obj->base.write_domain; |
2913 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2914 | |
2915 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2916 | obj->base.read_domains, |
1c5d22f7 | 2917 | old_write_domain); |
e47c68e9 EA |
2918 | } |
2919 | ||
2920 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2921 | static void | |
05394f39 | 2922 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2923 | { |
1c5d22f7 | 2924 | uint32_t old_write_domain; |
e47c68e9 | 2925 | |
05394f39 | 2926 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2927 | return; |
2928 | ||
2929 | i915_gem_clflush_object(obj); | |
40ce6575 | 2930 | intel_gtt_chipset_flush(); |
05394f39 CW |
2931 | old_write_domain = obj->base.write_domain; |
2932 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2933 | |
2934 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2935 | obj->base.read_domains, |
1c5d22f7 | 2936 | old_write_domain); |
e47c68e9 EA |
2937 | } |
2938 | ||
2ef7eeaa EA |
2939 | /** |
2940 | * Moves a single object to the GTT read, and possibly write domain. | |
2941 | * | |
2942 | * This function returns when the move is complete, including waiting on | |
2943 | * flushes to occur. | |
2944 | */ | |
79e53945 | 2945 | int |
2021746e | 2946 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2947 | { |
1c5d22f7 | 2948 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2949 | int ret; |
2ef7eeaa | 2950 | |
02354392 | 2951 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2952 | if (obj->gtt_space == NULL) |
02354392 EA |
2953 | return -EINVAL; |
2954 | ||
8d7e3de1 CW |
2955 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2956 | return 0; | |
2957 | ||
88241785 CW |
2958 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2959 | if (ret) | |
2960 | return ret; | |
2961 | ||
87ca9c8a | 2962 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2963 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2964 | if (ret) |
2965 | return ret; | |
2966 | } | |
2dafb1e0 | 2967 | |
7213342d | 2968 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2969 | |
05394f39 CW |
2970 | old_write_domain = obj->base.write_domain; |
2971 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2972 | |
e47c68e9 EA |
2973 | /* It should now be out of any other write domains, and we can update |
2974 | * the domain values for our changes. | |
2975 | */ | |
05394f39 CW |
2976 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2977 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2978 | if (write) { |
05394f39 CW |
2979 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2980 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2981 | obj->dirty = 1; | |
2ef7eeaa EA |
2982 | } |
2983 | ||
1c5d22f7 CW |
2984 | trace_i915_gem_object_change_domain(obj, |
2985 | old_read_domains, | |
2986 | old_write_domain); | |
2987 | ||
e47c68e9 EA |
2988 | return 0; |
2989 | } | |
2990 | ||
b9241ea3 ZW |
2991 | /* |
2992 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2993 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2994 | */ | |
2995 | int | |
05394f39 | 2996 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
919926ae | 2997 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2998 | { |
ba3d8d74 | 2999 | uint32_t old_read_domains; |
b9241ea3 ZW |
3000 | int ret; |
3001 | ||
3002 | /* Not valid to be called on unbound objects. */ | |
05394f39 | 3003 | if (obj->gtt_space == NULL) |
b9241ea3 ZW |
3004 | return -EINVAL; |
3005 | ||
88241785 CW |
3006 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3007 | if (ret) | |
3008 | return ret; | |
3009 | ||
b9241ea3 | 3010 | |
ced270fa | 3011 | /* Currently, we are always called from an non-interruptible context. */ |
0be73284 | 3012 | if (pipelined != obj->ring) { |
ce453d81 | 3013 | ret = i915_gem_object_wait_rendering(obj); |
ced270fa | 3014 | if (ret) |
b9241ea3 ZW |
3015 | return ret; |
3016 | } | |
3017 | ||
b118c1e3 CW |
3018 | i915_gem_object_flush_cpu_write_domain(obj); |
3019 | ||
05394f39 CW |
3020 | old_read_domains = obj->base.read_domains; |
3021 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
b9241ea3 ZW |
3022 | |
3023 | trace_i915_gem_object_change_domain(obj, | |
3024 | old_read_domains, | |
05394f39 | 3025 | obj->base.write_domain); |
b9241ea3 ZW |
3026 | |
3027 | return 0; | |
3028 | } | |
3029 | ||
85345517 | 3030 | int |
ce453d81 | 3031 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3032 | { |
88241785 CW |
3033 | int ret; |
3034 | ||
85345517 CW |
3035 | if (!obj->active) |
3036 | return 0; | |
3037 | ||
88241785 | 3038 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3039 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
3040 | if (ret) |
3041 | return ret; | |
3042 | } | |
85345517 | 3043 | |
ce453d81 | 3044 | return i915_gem_object_wait_rendering(obj); |
85345517 CW |
3045 | } |
3046 | ||
e47c68e9 EA |
3047 | /** |
3048 | * Moves a single object to the CPU read, and possibly write domain. | |
3049 | * | |
3050 | * This function returns when the move is complete, including waiting on | |
3051 | * flushes to occur. | |
3052 | */ | |
3053 | static int | |
919926ae | 3054 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3055 | { |
1c5d22f7 | 3056 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3057 | int ret; |
3058 | ||
8d7e3de1 CW |
3059 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3060 | return 0; | |
3061 | ||
88241785 CW |
3062 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3063 | if (ret) | |
3064 | return ret; | |
3065 | ||
ce453d81 | 3066 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3067 | if (ret) |
e47c68e9 | 3068 | return ret; |
2ef7eeaa | 3069 | |
e47c68e9 | 3070 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3071 | |
e47c68e9 EA |
3072 | /* If we have a partially-valid cache of the object in the CPU, |
3073 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3074 | */ |
e47c68e9 | 3075 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3076 | |
05394f39 CW |
3077 | old_write_domain = obj->base.write_domain; |
3078 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3079 | |
e47c68e9 | 3080 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3081 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3082 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3083 | |
05394f39 | 3084 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3085 | } |
3086 | ||
3087 | /* It should now be out of any other write domains, and we can update | |
3088 | * the domain values for our changes. | |
3089 | */ | |
05394f39 | 3090 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3091 | |
3092 | /* If we're writing through the CPU, then the GPU read domains will | |
3093 | * need to be invalidated at next use. | |
3094 | */ | |
3095 | if (write) { | |
05394f39 CW |
3096 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3097 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3098 | } |
2ef7eeaa | 3099 | |
1c5d22f7 CW |
3100 | trace_i915_gem_object_change_domain(obj, |
3101 | old_read_domains, | |
3102 | old_write_domain); | |
3103 | ||
2ef7eeaa EA |
3104 | return 0; |
3105 | } | |
3106 | ||
673a394b | 3107 | /** |
e47c68e9 | 3108 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3109 | * |
e47c68e9 EA |
3110 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3111 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3112 | */ |
e47c68e9 | 3113 | static void |
05394f39 | 3114 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3115 | { |
05394f39 | 3116 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3117 | return; |
3118 | ||
3119 | /* If we're partially in the CPU read domain, finish moving it in. | |
3120 | */ | |
05394f39 | 3121 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3122 | int i; |
3123 | ||
05394f39 CW |
3124 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3125 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3126 | continue; |
05394f39 | 3127 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3128 | } |
e47c68e9 EA |
3129 | } |
3130 | ||
3131 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3132 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3133 | */ | |
05394f39 CW |
3134 | kfree(obj->page_cpu_valid); |
3135 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3136 | } |
3137 | ||
3138 | /** | |
3139 | * Set the CPU read domain on a range of the object. | |
3140 | * | |
3141 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3142 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3143 | * pages have been flushed, and will be respected by | |
3144 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3145 | * of the whole object. | |
3146 | * | |
3147 | * This function returns when the move is complete, including waiting on | |
3148 | * flushes to occur. | |
3149 | */ | |
3150 | static int | |
05394f39 | 3151 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3152 | uint64_t offset, uint64_t size) |
3153 | { | |
1c5d22f7 | 3154 | uint32_t old_read_domains; |
e47c68e9 | 3155 | int i, ret; |
673a394b | 3156 | |
05394f39 | 3157 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3158 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3159 | |
88241785 CW |
3160 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3161 | if (ret) | |
3162 | return ret; | |
3163 | ||
ce453d81 | 3164 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3165 | if (ret) |
6a47baa6 | 3166 | return ret; |
de18a29e | 3167 | |
e47c68e9 EA |
3168 | i915_gem_object_flush_gtt_write_domain(obj); |
3169 | ||
3170 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3171 | if (obj->page_cpu_valid == NULL && |
3172 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3173 | return 0; |
673a394b | 3174 | |
e47c68e9 EA |
3175 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3176 | * newly adding I915_GEM_DOMAIN_CPU | |
3177 | */ | |
05394f39 CW |
3178 | if (obj->page_cpu_valid == NULL) { |
3179 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3180 | GFP_KERNEL); | |
3181 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3182 | return -ENOMEM; |
05394f39 CW |
3183 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3184 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3185 | |
3186 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3187 | * perspective. | |
3188 | */ | |
e47c68e9 EA |
3189 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3190 | i++) { | |
05394f39 | 3191 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3192 | continue; |
3193 | ||
05394f39 | 3194 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3195 | |
05394f39 | 3196 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3197 | } |
3198 | ||
e47c68e9 EA |
3199 | /* It should now be out of any other write domains, and we can update |
3200 | * the domain values for our changes. | |
3201 | */ | |
05394f39 | 3202 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3203 | |
05394f39 CW |
3204 | old_read_domains = obj->base.read_domains; |
3205 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3206 | |
1c5d22f7 CW |
3207 | trace_i915_gem_object_change_domain(obj, |
3208 | old_read_domains, | |
05394f39 | 3209 | obj->base.write_domain); |
1c5d22f7 | 3210 | |
673a394b EA |
3211 | return 0; |
3212 | } | |
3213 | ||
673a394b EA |
3214 | /* Throttle our rendering by waiting until the ring has completed our requests |
3215 | * emitted over 20 msec ago. | |
3216 | * | |
b962442e EA |
3217 | * Note that if we were to use the current jiffies each time around the loop, |
3218 | * we wouldn't escape the function with any frames outstanding if the time to | |
3219 | * render a frame was over 20ms. | |
3220 | * | |
673a394b EA |
3221 | * This should get us reasonable parallelism between CPU and GPU but also |
3222 | * relatively low latency when blocking on a particular request to finish. | |
3223 | */ | |
40a5f0de | 3224 | static int |
f787a5f5 | 3225 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3226 | { |
f787a5f5 CW |
3227 | struct drm_i915_private *dev_priv = dev->dev_private; |
3228 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3229 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3230 | struct drm_i915_gem_request *request; |
3231 | struct intel_ring_buffer *ring = NULL; | |
3232 | u32 seqno = 0; | |
3233 | int ret; | |
93533c29 | 3234 | |
e110e8d6 CW |
3235 | if (atomic_read(&dev_priv->mm.wedged)) |
3236 | return -EIO; | |
3237 | ||
1c25595f | 3238 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3239 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3240 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3241 | break; | |
40a5f0de | 3242 | |
f787a5f5 CW |
3243 | ring = request->ring; |
3244 | seqno = request->seqno; | |
b962442e | 3245 | } |
1c25595f | 3246 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3247 | |
f787a5f5 CW |
3248 | if (seqno == 0) |
3249 | return 0; | |
2bc43b5c | 3250 | |
f787a5f5 | 3251 | ret = 0; |
78501eac | 3252 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3253 | /* And wait for the seqno passing without holding any locks and |
3254 | * causing extra latency for others. This is safe as the irq | |
3255 | * generation is designed to be run atomically and so is | |
3256 | * lockless. | |
3257 | */ | |
b13c2b96 CW |
3258 | if (ring->irq_get(ring)) { |
3259 | ret = wait_event_interruptible(ring->irq_queue, | |
3260 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3261 | || atomic_read(&dev_priv->mm.wedged)); | |
3262 | ring->irq_put(ring); | |
40a5f0de | 3263 | |
b13c2b96 CW |
3264 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3265 | ret = -EIO; | |
3266 | } | |
40a5f0de EA |
3267 | } |
3268 | ||
f787a5f5 CW |
3269 | if (ret == 0) |
3270 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3271 | |
3272 | return ret; | |
3273 | } | |
3274 | ||
673a394b | 3275 | int |
05394f39 CW |
3276 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3277 | uint32_t alignment, | |
75e9e915 | 3278 | bool map_and_fenceable) |
673a394b | 3279 | { |
05394f39 | 3280 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3281 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3282 | int ret; |
3283 | ||
05394f39 | 3284 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3285 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3286 | |
05394f39 CW |
3287 | if (obj->gtt_space != NULL) { |
3288 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3289 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3290 | WARN(obj->pin_count, | |
ae7d49d8 | 3291 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3292 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3293 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3294 | obj->gtt_offset, alignment, |
75e9e915 | 3295 | map_and_fenceable, |
05394f39 | 3296 | obj->map_and_fenceable); |
ac0c6b5a CW |
3297 | ret = i915_gem_object_unbind(obj); |
3298 | if (ret) | |
3299 | return ret; | |
3300 | } | |
3301 | } | |
3302 | ||
05394f39 | 3303 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3304 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3305 | map_and_fenceable); |
9731129c | 3306 | if (ret) |
673a394b | 3307 | return ret; |
22c344e9 | 3308 | } |
76446cac | 3309 | |
05394f39 | 3310 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3311 | if (!obj->active) |
3312 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3313 | &dev_priv->mm.pinned_list); |
673a394b | 3314 | } |
6299f992 | 3315 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3316 | |
23bc5982 | 3317 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3318 | return 0; |
3319 | } | |
3320 | ||
3321 | void | |
05394f39 | 3322 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3323 | { |
05394f39 | 3324 | struct drm_device *dev = obj->base.dev; |
673a394b | 3325 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3326 | |
23bc5982 | 3327 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3328 | BUG_ON(obj->pin_count == 0); |
3329 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3330 | |
05394f39 CW |
3331 | if (--obj->pin_count == 0) { |
3332 | if (!obj->active) | |
3333 | list_move_tail(&obj->mm_list, | |
673a394b | 3334 | &dev_priv->mm.inactive_list); |
6299f992 | 3335 | obj->pin_mappable = false; |
673a394b | 3336 | } |
23bc5982 | 3337 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3338 | } |
3339 | ||
3340 | int | |
3341 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3342 | struct drm_file *file) |
673a394b EA |
3343 | { |
3344 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3345 | struct drm_i915_gem_object *obj; |
673a394b EA |
3346 | int ret; |
3347 | ||
1d7cfea1 CW |
3348 | ret = i915_mutex_lock_interruptible(dev); |
3349 | if (ret) | |
3350 | return ret; | |
673a394b | 3351 | |
05394f39 | 3352 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3353 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3354 | ret = -ENOENT; |
3355 | goto unlock; | |
673a394b | 3356 | } |
673a394b | 3357 | |
05394f39 | 3358 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3359 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3360 | ret = -EINVAL; |
3361 | goto out; | |
3ef94daa CW |
3362 | } |
3363 | ||
05394f39 | 3364 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3365 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3366 | args->handle); | |
1d7cfea1 CW |
3367 | ret = -EINVAL; |
3368 | goto out; | |
79e53945 JB |
3369 | } |
3370 | ||
05394f39 CW |
3371 | obj->user_pin_count++; |
3372 | obj->pin_filp = file; | |
3373 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3374 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3375 | if (ret) |
3376 | goto out; | |
673a394b EA |
3377 | } |
3378 | ||
3379 | /* XXX - flush the CPU caches for pinned objects | |
3380 | * as the X server doesn't manage domains yet | |
3381 | */ | |
e47c68e9 | 3382 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3383 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3384 | out: |
05394f39 | 3385 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3386 | unlock: |
673a394b | 3387 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3388 | return ret; |
673a394b EA |
3389 | } |
3390 | ||
3391 | int | |
3392 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3393 | struct drm_file *file) |
673a394b EA |
3394 | { |
3395 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3396 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3397 | int ret; |
673a394b | 3398 | |
1d7cfea1 CW |
3399 | ret = i915_mutex_lock_interruptible(dev); |
3400 | if (ret) | |
3401 | return ret; | |
673a394b | 3402 | |
05394f39 | 3403 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3404 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3405 | ret = -ENOENT; |
3406 | goto unlock; | |
673a394b | 3407 | } |
76c1dec1 | 3408 | |
05394f39 | 3409 | if (obj->pin_filp != file) { |
79e53945 JB |
3410 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3411 | args->handle); | |
1d7cfea1 CW |
3412 | ret = -EINVAL; |
3413 | goto out; | |
79e53945 | 3414 | } |
05394f39 CW |
3415 | obj->user_pin_count--; |
3416 | if (obj->user_pin_count == 0) { | |
3417 | obj->pin_filp = NULL; | |
79e53945 JB |
3418 | i915_gem_object_unpin(obj); |
3419 | } | |
673a394b | 3420 | |
1d7cfea1 | 3421 | out: |
05394f39 | 3422 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3423 | unlock: |
673a394b | 3424 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3425 | return ret; |
673a394b EA |
3426 | } |
3427 | ||
3428 | int | |
3429 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3430 | struct drm_file *file) |
673a394b EA |
3431 | { |
3432 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3433 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3434 | int ret; |
3435 | ||
76c1dec1 | 3436 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3437 | if (ret) |
76c1dec1 | 3438 | return ret; |
673a394b | 3439 | |
05394f39 | 3440 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3441 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3442 | ret = -ENOENT; |
3443 | goto unlock; | |
673a394b | 3444 | } |
d1b851fc | 3445 | |
0be555b6 CW |
3446 | /* Count all active objects as busy, even if they are currently not used |
3447 | * by the gpu. Users of this interface expect objects to eventually | |
3448 | * become non-busy without any further actions, therefore emit any | |
3449 | * necessary flushes here. | |
c4de0a5d | 3450 | */ |
05394f39 | 3451 | args->busy = obj->active; |
0be555b6 CW |
3452 | if (args->busy) { |
3453 | /* Unconditionally flush objects, even when the gpu still uses this | |
3454 | * object. Userspace calling this function indicates that it wants to | |
3455 | * use this buffer rather sooner than later, so issuing the required | |
3456 | * flush earlier is beneficial. | |
3457 | */ | |
1a1c6976 | 3458 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3459 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3460 | 0, obj->base.write_domain); |
1a1c6976 CW |
3461 | } else if (obj->ring->outstanding_lazy_request == |
3462 | obj->last_rendering_seqno) { | |
3463 | struct drm_i915_gem_request *request; | |
3464 | ||
7a194876 CW |
3465 | /* This ring is not being cleared by active usage, |
3466 | * so emit a request to do so. | |
3467 | */ | |
1a1c6976 CW |
3468 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3469 | if (request) | |
db53a302 | 3470 | ret = i915_add_request(obj->ring, NULL,request); |
1a1c6976 | 3471 | else |
7a194876 CW |
3472 | ret = -ENOMEM; |
3473 | } | |
0be555b6 CW |
3474 | |
3475 | /* Update the active list for the hardware's current position. | |
3476 | * Otherwise this only updates on a delayed timer or when irqs | |
3477 | * are actually unmasked, and our working set ends up being | |
3478 | * larger than required. | |
3479 | */ | |
db53a302 | 3480 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3481 | |
05394f39 | 3482 | args->busy = obj->active; |
0be555b6 | 3483 | } |
673a394b | 3484 | |
05394f39 | 3485 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3486 | unlock: |
673a394b | 3487 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3488 | return ret; |
673a394b EA |
3489 | } |
3490 | ||
3491 | int | |
3492 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3493 | struct drm_file *file_priv) | |
3494 | { | |
3495 | return i915_gem_ring_throttle(dev, file_priv); | |
3496 | } | |
3497 | ||
3ef94daa CW |
3498 | int |
3499 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3500 | struct drm_file *file_priv) | |
3501 | { | |
3502 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3503 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3504 | int ret; |
3ef94daa CW |
3505 | |
3506 | switch (args->madv) { | |
3507 | case I915_MADV_DONTNEED: | |
3508 | case I915_MADV_WILLNEED: | |
3509 | break; | |
3510 | default: | |
3511 | return -EINVAL; | |
3512 | } | |
3513 | ||
1d7cfea1 CW |
3514 | ret = i915_mutex_lock_interruptible(dev); |
3515 | if (ret) | |
3516 | return ret; | |
3517 | ||
05394f39 | 3518 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3519 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3520 | ret = -ENOENT; |
3521 | goto unlock; | |
3ef94daa | 3522 | } |
3ef94daa | 3523 | |
05394f39 | 3524 | if (obj->pin_count) { |
1d7cfea1 CW |
3525 | ret = -EINVAL; |
3526 | goto out; | |
3ef94daa CW |
3527 | } |
3528 | ||
05394f39 CW |
3529 | if (obj->madv != __I915_MADV_PURGED) |
3530 | obj->madv = args->madv; | |
3ef94daa | 3531 | |
2d7ef395 | 3532 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3533 | if (i915_gem_object_is_purgeable(obj) && |
3534 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3535 | i915_gem_object_truncate(obj); |
3536 | ||
05394f39 | 3537 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3538 | |
1d7cfea1 | 3539 | out: |
05394f39 | 3540 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3541 | unlock: |
3ef94daa | 3542 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3543 | return ret; |
3ef94daa CW |
3544 | } |
3545 | ||
05394f39 CW |
3546 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3547 | size_t size) | |
ac52bc56 | 3548 | { |
73aa808f | 3549 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3550 | struct drm_i915_gem_object *obj; |
ac52bc56 | 3551 | |
c397b908 DV |
3552 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3553 | if (obj == NULL) | |
3554 | return NULL; | |
673a394b | 3555 | |
c397b908 DV |
3556 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3557 | kfree(obj); | |
3558 | return NULL; | |
3559 | } | |
673a394b | 3560 | |
73aa808f CW |
3561 | i915_gem_info_add_obj(dev_priv, size); |
3562 | ||
c397b908 DV |
3563 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3564 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3565 | |
c397b908 | 3566 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 3567 | obj->base.driver_private = NULL; |
c397b908 | 3568 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3569 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3570 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3571 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3572 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3573 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3574 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3575 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3576 | obj->map_and_fenceable = true; | |
de151cf6 | 3577 | |
05394f39 | 3578 | return obj; |
c397b908 DV |
3579 | } |
3580 | ||
3581 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3582 | { | |
3583 | BUG(); | |
de151cf6 | 3584 | |
673a394b EA |
3585 | return 0; |
3586 | } | |
3587 | ||
05394f39 | 3588 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3589 | { |
05394f39 | 3590 | struct drm_device *dev = obj->base.dev; |
be72615b | 3591 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3592 | int ret; |
673a394b | 3593 | |
be72615b CW |
3594 | ret = i915_gem_object_unbind(obj); |
3595 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3596 | list_move(&obj->mm_list, |
be72615b CW |
3597 | &dev_priv->mm.deferred_free_list); |
3598 | return; | |
3599 | } | |
673a394b | 3600 | |
05394f39 | 3601 | if (obj->base.map_list.map) |
7e616158 | 3602 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 3603 | |
05394f39 CW |
3604 | drm_gem_object_release(&obj->base); |
3605 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3606 | |
05394f39 CW |
3607 | kfree(obj->page_cpu_valid); |
3608 | kfree(obj->bit_17); | |
3609 | kfree(obj); | |
db53a302 CW |
3610 | |
3611 | trace_i915_gem_object_destroy(obj); | |
673a394b EA |
3612 | } |
3613 | ||
05394f39 | 3614 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3615 | { |
05394f39 CW |
3616 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3617 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3618 | |
05394f39 | 3619 | while (obj->pin_count > 0) |
be72615b CW |
3620 | i915_gem_object_unpin(obj); |
3621 | ||
05394f39 | 3622 | if (obj->phys_obj) |
be72615b CW |
3623 | i915_gem_detach_phys_object(dev, obj); |
3624 | ||
3625 | i915_gem_free_object_tail(obj); | |
3626 | } | |
3627 | ||
29105ccc CW |
3628 | int |
3629 | i915_gem_idle(struct drm_device *dev) | |
3630 | { | |
3631 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3632 | int ret; | |
28dfe52a | 3633 | |
29105ccc | 3634 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3635 | |
87acb0a5 | 3636 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3637 | mutex_unlock(&dev->struct_mutex); |
3638 | return 0; | |
28dfe52a EA |
3639 | } |
3640 | ||
29105ccc | 3641 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3642 | if (ret) { |
3643 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3644 | return ret; |
6dbe2772 | 3645 | } |
673a394b | 3646 | |
29105ccc CW |
3647 | /* Under UMS, be paranoid and evict. */ |
3648 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3649 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3650 | if (ret) { |
3651 | mutex_unlock(&dev->struct_mutex); | |
3652 | return ret; | |
3653 | } | |
3654 | } | |
3655 | ||
312817a3 CW |
3656 | i915_gem_reset_fences(dev); |
3657 | ||
29105ccc CW |
3658 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3659 | * We need to replace this with a semaphore, or something. | |
3660 | * And not confound mm.suspended! | |
3661 | */ | |
3662 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3663 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3664 | |
3665 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3666 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3667 | |
6dbe2772 KP |
3668 | mutex_unlock(&dev->struct_mutex); |
3669 | ||
29105ccc CW |
3670 | /* Cancel the retire work handler, which should be idle now. */ |
3671 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3672 | ||
673a394b EA |
3673 | return 0; |
3674 | } | |
3675 | ||
8187a2b7 ZN |
3676 | int |
3677 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
3678 | { | |
3679 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3680 | int ret; | |
68f95ba9 | 3681 | |
5c1143bb | 3682 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3683 | if (ret) |
b6913e4b | 3684 | return ret; |
68f95ba9 CW |
3685 | |
3686 | if (HAS_BSD(dev)) { | |
5c1143bb | 3687 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3688 | if (ret) |
3689 | goto cleanup_render_ring; | |
d1b851fc | 3690 | } |
68f95ba9 | 3691 | |
549f7365 CW |
3692 | if (HAS_BLT(dev)) { |
3693 | ret = intel_init_blt_ring_buffer(dev); | |
3694 | if (ret) | |
3695 | goto cleanup_bsd_ring; | |
3696 | } | |
3697 | ||
6f392d54 CW |
3698 | dev_priv->next_seqno = 1; |
3699 | ||
68f95ba9 CW |
3700 | return 0; |
3701 | ||
549f7365 | 3702 | cleanup_bsd_ring: |
1ec14ad3 | 3703 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3704 | cleanup_render_ring: |
1ec14ad3 | 3705 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3706 | return ret; |
3707 | } | |
3708 | ||
3709 | void | |
3710 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3711 | { | |
3712 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3713 | int i; |
8187a2b7 | 3714 | |
1ec14ad3 CW |
3715 | for (i = 0; i < I915_NUM_RINGS; i++) |
3716 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3717 | } |
3718 | ||
673a394b EA |
3719 | int |
3720 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3721 | struct drm_file *file_priv) | |
3722 | { | |
3723 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3724 | int ret, i; |
673a394b | 3725 | |
79e53945 JB |
3726 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3727 | return 0; | |
3728 | ||
ba1234d1 | 3729 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3730 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3731 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3732 | } |
3733 | ||
673a394b | 3734 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3735 | dev_priv->mm.suspended = 0; |
3736 | ||
3737 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
3738 | if (ret != 0) { |
3739 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3740 | return ret; |
d816f6ac | 3741 | } |
9bb2d6f9 | 3742 | |
69dc4987 | 3743 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3744 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3745 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3746 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3747 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3748 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3749 | } | |
673a394b | 3750 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3751 | |
5f35308b CW |
3752 | ret = drm_irq_install(dev); |
3753 | if (ret) | |
3754 | goto cleanup_ringbuffer; | |
dbb19d30 | 3755 | |
673a394b | 3756 | return 0; |
5f35308b CW |
3757 | |
3758 | cleanup_ringbuffer: | |
3759 | mutex_lock(&dev->struct_mutex); | |
3760 | i915_gem_cleanup_ringbuffer(dev); | |
3761 | dev_priv->mm.suspended = 1; | |
3762 | mutex_unlock(&dev->struct_mutex); | |
3763 | ||
3764 | return ret; | |
673a394b EA |
3765 | } |
3766 | ||
3767 | int | |
3768 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3769 | struct drm_file *file_priv) | |
3770 | { | |
79e53945 JB |
3771 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3772 | return 0; | |
3773 | ||
dbb19d30 | 3774 | drm_irq_uninstall(dev); |
e6890f6f | 3775 | return i915_gem_idle(dev); |
673a394b EA |
3776 | } |
3777 | ||
3778 | void | |
3779 | i915_gem_lastclose(struct drm_device *dev) | |
3780 | { | |
3781 | int ret; | |
673a394b | 3782 | |
e806b495 EA |
3783 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3784 | return; | |
3785 | ||
6dbe2772 KP |
3786 | ret = i915_gem_idle(dev); |
3787 | if (ret) | |
3788 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3789 | } |
3790 | ||
64193406 CW |
3791 | static void |
3792 | init_ring_lists(struct intel_ring_buffer *ring) | |
3793 | { | |
3794 | INIT_LIST_HEAD(&ring->active_list); | |
3795 | INIT_LIST_HEAD(&ring->request_list); | |
3796 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3797 | } | |
3798 | ||
673a394b EA |
3799 | void |
3800 | i915_gem_load(struct drm_device *dev) | |
3801 | { | |
b5aa8a0f | 3802 | int i; |
673a394b EA |
3803 | drm_i915_private_t *dev_priv = dev->dev_private; |
3804 | ||
69dc4987 | 3805 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3806 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3807 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3808 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3809 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3810 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3811 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3812 | for (i = 0; i < I915_NUM_RINGS; i++) |
3813 | init_ring_lists(&dev_priv->ring[i]); | |
007cc8ac DV |
3814 | for (i = 0; i < 16; i++) |
3815 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
3816 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3817 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3818 | init_completion(&dev_priv->error_completion); |
31169714 | 3819 | |
94400120 DA |
3820 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3821 | if (IS_GEN3(dev)) { | |
3822 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3823 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3824 | /* arb state is a masked write, so set bit + bit in mask */ | |
3825 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3826 | I915_WRITE(MI_ARB_STATE, tmp); | |
3827 | } | |
3828 | } | |
3829 | ||
72bfa19c CW |
3830 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3831 | ||
de151cf6 | 3832 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3833 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3834 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3835 | |
a6c45cf0 | 3836 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3837 | dev_priv->num_fence_regs = 16; |
3838 | else | |
3839 | dev_priv->num_fence_regs = 8; | |
3840 | ||
b5aa8a0f | 3841 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
3842 | switch (INTEL_INFO(dev)->gen) { |
3843 | case 6: | |
3844 | for (i = 0; i < 16; i++) | |
3845 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
3846 | break; | |
3847 | case 5: | |
3848 | case 4: | |
b5aa8a0f GH |
3849 | for (i = 0; i < 16; i++) |
3850 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
3851 | break; |
3852 | case 3: | |
b5aa8a0f GH |
3853 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
3854 | for (i = 0; i < 8; i++) | |
3855 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
3856 | case 2: |
3857 | for (i = 0; i < 8; i++) | |
3858 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
3859 | break; | |
b5aa8a0f | 3860 | } |
673a394b | 3861 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3862 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3863 | |
ce453d81 CW |
3864 | dev_priv->mm.interruptible = true; |
3865 | ||
17250b71 CW |
3866 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3867 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3868 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3869 | } |
71acb5eb DA |
3870 | |
3871 | /* | |
3872 | * Create a physically contiguous memory object for this object | |
3873 | * e.g. for cursor + overlay regs | |
3874 | */ | |
995b6762 CW |
3875 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3876 | int id, int size, int align) | |
71acb5eb DA |
3877 | { |
3878 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3879 | struct drm_i915_gem_phys_object *phys_obj; | |
3880 | int ret; | |
3881 | ||
3882 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3883 | return 0; | |
3884 | ||
9a298b2a | 3885 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3886 | if (!phys_obj) |
3887 | return -ENOMEM; | |
3888 | ||
3889 | phys_obj->id = id; | |
3890 | ||
6eeefaf3 | 3891 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3892 | if (!phys_obj->handle) { |
3893 | ret = -ENOMEM; | |
3894 | goto kfree_obj; | |
3895 | } | |
3896 | #ifdef CONFIG_X86 | |
3897 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3898 | #endif | |
3899 | ||
3900 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3901 | ||
3902 | return 0; | |
3903 | kfree_obj: | |
9a298b2a | 3904 | kfree(phys_obj); |
71acb5eb DA |
3905 | return ret; |
3906 | } | |
3907 | ||
995b6762 | 3908 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3909 | { |
3910 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3911 | struct drm_i915_gem_phys_object *phys_obj; | |
3912 | ||
3913 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3914 | return; | |
3915 | ||
3916 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3917 | if (phys_obj->cur_obj) { | |
3918 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3919 | } | |
3920 | ||
3921 | #ifdef CONFIG_X86 | |
3922 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3923 | #endif | |
3924 | drm_pci_free(dev, phys_obj->handle); | |
3925 | kfree(phys_obj); | |
3926 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3927 | } | |
3928 | ||
3929 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3930 | { | |
3931 | int i; | |
3932 | ||
260883c8 | 3933 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3934 | i915_gem_free_phys_object(dev, i); |
3935 | } | |
3936 | ||
3937 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3938 | struct drm_i915_gem_object *obj) |
71acb5eb | 3939 | { |
05394f39 | 3940 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3941 | char *vaddr; |
71acb5eb | 3942 | int i; |
71acb5eb DA |
3943 | int page_count; |
3944 | ||
05394f39 | 3945 | if (!obj->phys_obj) |
71acb5eb | 3946 | return; |
05394f39 | 3947 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3948 | |
05394f39 | 3949 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3950 | for (i = 0; i < page_count; i++) { |
e5281ccd CW |
3951 | struct page *page = read_cache_page_gfp(mapping, i, |
3952 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3953 | if (!IS_ERR(page)) { | |
3954 | char *dst = kmap_atomic(page); | |
3955 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3956 | kunmap_atomic(dst); | |
3957 | ||
3958 | drm_clflush_pages(&page, 1); | |
3959 | ||
3960 | set_page_dirty(page); | |
3961 | mark_page_accessed(page); | |
3962 | page_cache_release(page); | |
3963 | } | |
71acb5eb | 3964 | } |
40ce6575 | 3965 | intel_gtt_chipset_flush(); |
d78b47b9 | 3966 | |
05394f39 CW |
3967 | obj->phys_obj->cur_obj = NULL; |
3968 | obj->phys_obj = NULL; | |
71acb5eb DA |
3969 | } |
3970 | ||
3971 | int | |
3972 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3973 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3974 | int id, |
3975 | int align) | |
71acb5eb | 3976 | { |
05394f39 | 3977 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3978 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3979 | int ret = 0; |
3980 | int page_count; | |
3981 | int i; | |
3982 | ||
3983 | if (id > I915_MAX_PHYS_OBJECT) | |
3984 | return -EINVAL; | |
3985 | ||
05394f39 CW |
3986 | if (obj->phys_obj) { |
3987 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
3988 | return 0; |
3989 | i915_gem_detach_phys_object(dev, obj); | |
3990 | } | |
3991 | ||
71acb5eb DA |
3992 | /* create a new object */ |
3993 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
3994 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 3995 | obj->base.size, align); |
71acb5eb | 3996 | if (ret) { |
05394f39 CW |
3997 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
3998 | id, obj->base.size); | |
e5281ccd | 3999 | return ret; |
71acb5eb DA |
4000 | } |
4001 | } | |
4002 | ||
4003 | /* bind to the object */ | |
05394f39 CW |
4004 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4005 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4006 | |
05394f39 | 4007 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4008 | |
4009 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4010 | struct page *page; |
4011 | char *dst, *src; | |
4012 | ||
4013 | page = read_cache_page_gfp(mapping, i, | |
4014 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4015 | if (IS_ERR(page)) | |
4016 | return PTR_ERR(page); | |
71acb5eb | 4017 | |
ff75b9bc | 4018 | src = kmap_atomic(page); |
05394f39 | 4019 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4020 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4021 | kunmap_atomic(src); |
71acb5eb | 4022 | |
e5281ccd CW |
4023 | mark_page_accessed(page); |
4024 | page_cache_release(page); | |
4025 | } | |
d78b47b9 | 4026 | |
71acb5eb | 4027 | return 0; |
71acb5eb DA |
4028 | } |
4029 | ||
4030 | static int | |
05394f39 CW |
4031 | i915_gem_phys_pwrite(struct drm_device *dev, |
4032 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4033 | struct drm_i915_gem_pwrite *args, |
4034 | struct drm_file *file_priv) | |
4035 | { | |
05394f39 | 4036 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4037 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4038 | |
b47b30cc CW |
4039 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4040 | unsigned long unwritten; | |
4041 | ||
4042 | /* The physical object once assigned is fixed for the lifetime | |
4043 | * of the obj, so we can safely drop the lock and continue | |
4044 | * to access vaddr. | |
4045 | */ | |
4046 | mutex_unlock(&dev->struct_mutex); | |
4047 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4048 | mutex_lock(&dev->struct_mutex); | |
4049 | if (unwritten) | |
4050 | return -EFAULT; | |
4051 | } | |
71acb5eb | 4052 | |
40ce6575 | 4053 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4054 | return 0; |
4055 | } | |
b962442e | 4056 | |
f787a5f5 | 4057 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4058 | { |
f787a5f5 | 4059 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4060 | |
4061 | /* Clean up our request list when the client is going away, so that | |
4062 | * later retire_requests won't dereference our soon-to-be-gone | |
4063 | * file_priv. | |
4064 | */ | |
1c25595f | 4065 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4066 | while (!list_empty(&file_priv->mm.request_list)) { |
4067 | struct drm_i915_gem_request *request; | |
4068 | ||
4069 | request = list_first_entry(&file_priv->mm.request_list, | |
4070 | struct drm_i915_gem_request, | |
4071 | client_list); | |
4072 | list_del(&request->client_list); | |
4073 | request->file_priv = NULL; | |
4074 | } | |
1c25595f | 4075 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4076 | } |
31169714 | 4077 | |
1637ef41 CW |
4078 | static int |
4079 | i915_gpu_is_active(struct drm_device *dev) | |
4080 | { | |
4081 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4082 | int lists_empty; | |
4083 | ||
1637ef41 | 4084 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4085 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4086 | |
4087 | return !lists_empty; | |
4088 | } | |
4089 | ||
31169714 | 4090 | static int |
17250b71 CW |
4091 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
4092 | int nr_to_scan, | |
4093 | gfp_t gfp_mask) | |
31169714 | 4094 | { |
17250b71 CW |
4095 | struct drm_i915_private *dev_priv = |
4096 | container_of(shrinker, | |
4097 | struct drm_i915_private, | |
4098 | mm.inactive_shrinker); | |
4099 | struct drm_device *dev = dev_priv->dev; | |
4100 | struct drm_i915_gem_object *obj, *next; | |
4101 | int cnt; | |
4102 | ||
4103 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4104 | return 0; |
31169714 CW |
4105 | |
4106 | /* "fast-path" to count number of available objects */ | |
4107 | if (nr_to_scan == 0) { | |
17250b71 CW |
4108 | cnt = 0; |
4109 | list_for_each_entry(obj, | |
4110 | &dev_priv->mm.inactive_list, | |
4111 | mm_list) | |
4112 | cnt++; | |
4113 | mutex_unlock(&dev->struct_mutex); | |
4114 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4115 | } |
4116 | ||
1637ef41 | 4117 | rescan: |
31169714 | 4118 | /* first scan for clean buffers */ |
17250b71 | 4119 | i915_gem_retire_requests(dev); |
31169714 | 4120 | |
17250b71 CW |
4121 | list_for_each_entry_safe(obj, next, |
4122 | &dev_priv->mm.inactive_list, | |
4123 | mm_list) { | |
4124 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4125 | if (i915_gem_object_unbind(obj) == 0 && |
4126 | --nr_to_scan == 0) | |
17250b71 | 4127 | break; |
31169714 | 4128 | } |
31169714 CW |
4129 | } |
4130 | ||
4131 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4132 | cnt = 0; |
4133 | list_for_each_entry_safe(obj, next, | |
4134 | &dev_priv->mm.inactive_list, | |
4135 | mm_list) { | |
2021746e CW |
4136 | if (nr_to_scan && |
4137 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4138 | nr_to_scan--; |
2021746e | 4139 | else |
17250b71 CW |
4140 | cnt++; |
4141 | } | |
4142 | ||
4143 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4144 | /* |
4145 | * We are desperate for pages, so as a last resort, wait | |
4146 | * for the GPU to finish and discard whatever we can. | |
4147 | * This has a dramatic impact to reduce the number of | |
4148 | * OOM-killer events whilst running the GPU aggressively. | |
4149 | */ | |
17250b71 | 4150 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
4151 | goto rescan; |
4152 | } | |
17250b71 CW |
4153 | mutex_unlock(&dev->struct_mutex); |
4154 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4155 | } |