Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
b4716185 CW |
41 | #define RQ_BUG_ON(expr) |
42 | ||
05394f39 | 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
c8725f3d | 45 | static void |
b4716185 CW |
46 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
47 | static void | |
48 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); | |
61050808 | 49 | |
c76ce038 CW |
50 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
51 | enum i915_cache_level level) | |
52 | { | |
53 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
54 | } | |
55 | ||
2c22569b CW |
56 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
57 | { | |
58 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
59 | return true; | |
60 | ||
61 | return obj->pin_display; | |
62 | } | |
63 | ||
73aa808f CW |
64 | /* some bookkeeping */ |
65 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
66 | size_t size) | |
67 | { | |
c20e8355 | 68 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
69 | dev_priv->mm.object_count++; |
70 | dev_priv->mm.object_memory += size; | |
c20e8355 | 71 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
72 | } |
73 | ||
74 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
c20e8355 | 77 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
78 | dev_priv->mm.object_count--; |
79 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 80 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
81 | } |
82 | ||
21dd3734 | 83 | static int |
33196ded | 84 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 85 | { |
30dbf0c0 CW |
86 | int ret; |
87 | ||
7abb690a DV |
88 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
89 | i915_terminally_wedged(error)) | |
1f83fee0 | 90 | if (EXIT_COND) |
30dbf0c0 CW |
91 | return 0; |
92 | ||
0a6759c6 DV |
93 | /* |
94 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
95 | * userspace. If it takes that long something really bad is going on and | |
96 | * we should simply try to bail out and fail as gracefully as possible. | |
97 | */ | |
1f83fee0 DV |
98 | ret = wait_event_interruptible_timeout(error->reset_queue, |
99 | EXIT_COND, | |
100 | 10*HZ); | |
0a6759c6 DV |
101 | if (ret == 0) { |
102 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
103 | return -EIO; | |
104 | } else if (ret < 0) { | |
30dbf0c0 | 105 | return ret; |
0a6759c6 | 106 | } |
1f83fee0 | 107 | #undef EXIT_COND |
30dbf0c0 | 108 | |
21dd3734 | 109 | return 0; |
30dbf0c0 CW |
110 | } |
111 | ||
54cf91dc | 112 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 113 | { |
33196ded | 114 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
115 | int ret; |
116 | ||
33196ded | 117 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
118 | if (ret) |
119 | return ret; | |
120 | ||
121 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
122 | if (ret) | |
123 | return ret; | |
124 | ||
23bc5982 | 125 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
126 | return 0; |
127 | } | |
30dbf0c0 | 128 | |
5a125c3c EA |
129 | int |
130 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 131 | struct drm_file *file) |
5a125c3c | 132 | { |
73aa808f | 133 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 134 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be TU |
135 | struct i915_gtt *ggtt = &dev_priv->gtt; |
136 | struct i915_vma *vma; | |
6299f992 | 137 | size_t pinned; |
5a125c3c | 138 | |
6299f992 | 139 | pinned = 0; |
73aa808f | 140 | mutex_lock(&dev->struct_mutex); |
ca1543be TU |
141 | list_for_each_entry(vma, &ggtt->base.active_list, mm_list) |
142 | if (vma->pin_count) | |
143 | pinned += vma->node.size; | |
144 | list_for_each_entry(vma, &ggtt->base.inactive_list, mm_list) | |
145 | if (vma->pin_count) | |
146 | pinned += vma->node.size; | |
73aa808f | 147 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 148 | |
853ba5d2 | 149 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 150 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 151 | |
5a125c3c EA |
152 | return 0; |
153 | } | |
154 | ||
6a2c4232 CW |
155 | static int |
156 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 157 | { |
6a2c4232 CW |
158 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
159 | char *vaddr = obj->phys_handle->vaddr; | |
160 | struct sg_table *st; | |
161 | struct scatterlist *sg; | |
162 | int i; | |
00731155 | 163 | |
6a2c4232 CW |
164 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
165 | return -EINVAL; | |
166 | ||
167 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
168 | struct page *page; | |
169 | char *src; | |
170 | ||
171 | page = shmem_read_mapping_page(mapping, i); | |
172 | if (IS_ERR(page)) | |
173 | return PTR_ERR(page); | |
174 | ||
175 | src = kmap_atomic(page); | |
176 | memcpy(vaddr, src, PAGE_SIZE); | |
177 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
178 | kunmap_atomic(src); | |
179 | ||
180 | page_cache_release(page); | |
181 | vaddr += PAGE_SIZE; | |
182 | } | |
183 | ||
184 | i915_gem_chipset_flush(obj->base.dev); | |
185 | ||
186 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
187 | if (st == NULL) | |
188 | return -ENOMEM; | |
189 | ||
190 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
191 | kfree(st); | |
192 | return -ENOMEM; | |
193 | } | |
194 | ||
195 | sg = st->sgl; | |
196 | sg->offset = 0; | |
197 | sg->length = obj->base.size; | |
00731155 | 198 | |
6a2c4232 CW |
199 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
200 | sg_dma_len(sg) = obj->base.size; | |
201 | ||
202 | obj->pages = st; | |
6a2c4232 CW |
203 | return 0; |
204 | } | |
205 | ||
206 | static void | |
207 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
208 | { | |
209 | int ret; | |
210 | ||
211 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 212 | |
6a2c4232 CW |
213 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
214 | if (ret) { | |
215 | /* In the event of a disaster, abandon all caches and | |
216 | * hope for the best. | |
217 | */ | |
218 | WARN_ON(ret != -EIO); | |
219 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
220 | } | |
221 | ||
222 | if (obj->madv == I915_MADV_DONTNEED) | |
223 | obj->dirty = 0; | |
224 | ||
225 | if (obj->dirty) { | |
00731155 | 226 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 227 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
228 | int i; |
229 | ||
230 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
231 | struct page *page; |
232 | char *dst; | |
233 | ||
234 | page = shmem_read_mapping_page(mapping, i); | |
235 | if (IS_ERR(page)) | |
236 | continue; | |
237 | ||
238 | dst = kmap_atomic(page); | |
239 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
240 | memcpy(dst, vaddr, PAGE_SIZE); | |
241 | kunmap_atomic(dst); | |
242 | ||
243 | set_page_dirty(page); | |
244 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 245 | mark_page_accessed(page); |
6a2c4232 | 246 | page_cache_release(page); |
00731155 CW |
247 | vaddr += PAGE_SIZE; |
248 | } | |
6a2c4232 | 249 | obj->dirty = 0; |
00731155 CW |
250 | } |
251 | ||
6a2c4232 CW |
252 | sg_free_table(obj->pages); |
253 | kfree(obj->pages); | |
6a2c4232 CW |
254 | } |
255 | ||
256 | static void | |
257 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
258 | { | |
259 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
260 | } | |
261 | ||
262 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
263 | .get_pages = i915_gem_object_get_pages_phys, | |
264 | .put_pages = i915_gem_object_put_pages_phys, | |
265 | .release = i915_gem_object_release_phys, | |
266 | }; | |
267 | ||
268 | static int | |
269 | drop_pages(struct drm_i915_gem_object *obj) | |
270 | { | |
271 | struct i915_vma *vma, *next; | |
272 | int ret; | |
273 | ||
274 | drm_gem_object_reference(&obj->base); | |
275 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) | |
276 | if (i915_vma_unbind(vma)) | |
277 | break; | |
278 | ||
279 | ret = i915_gem_object_put_pages(obj); | |
280 | drm_gem_object_unreference(&obj->base); | |
281 | ||
282 | return ret; | |
00731155 CW |
283 | } |
284 | ||
285 | int | |
286 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
287 | int align) | |
288 | { | |
289 | drm_dma_handle_t *phys; | |
6a2c4232 | 290 | int ret; |
00731155 CW |
291 | |
292 | if (obj->phys_handle) { | |
293 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
294 | return -EBUSY; | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | if (obj->madv != I915_MADV_WILLNEED) | |
300 | return -EFAULT; | |
301 | ||
302 | if (obj->base.filp == NULL) | |
303 | return -EINVAL; | |
304 | ||
6a2c4232 CW |
305 | ret = drop_pages(obj); |
306 | if (ret) | |
307 | return ret; | |
308 | ||
00731155 CW |
309 | /* create a new object */ |
310 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
311 | if (!phys) | |
312 | return -ENOMEM; | |
313 | ||
00731155 | 314 | obj->phys_handle = phys; |
6a2c4232 CW |
315 | obj->ops = &i915_gem_phys_ops; |
316 | ||
317 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
318 | } |
319 | ||
320 | static int | |
321 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
322 | struct drm_i915_gem_pwrite *args, | |
323 | struct drm_file *file_priv) | |
324 | { | |
325 | struct drm_device *dev = obj->base.dev; | |
326 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
327 | char __user *user_data = to_user_ptr(args->data_ptr); | |
063e4e6b | 328 | int ret = 0; |
6a2c4232 CW |
329 | |
330 | /* We manually control the domain here and pretend that it | |
331 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
332 | */ | |
333 | ret = i915_gem_object_wait_rendering(obj, false); | |
334 | if (ret) | |
335 | return ret; | |
00731155 | 336 | |
77a0d1ca | 337 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
338 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
339 | unsigned long unwritten; | |
340 | ||
341 | /* The physical object once assigned is fixed for the lifetime | |
342 | * of the obj, so we can safely drop the lock and continue | |
343 | * to access vaddr. | |
344 | */ | |
345 | mutex_unlock(&dev->struct_mutex); | |
346 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
347 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
348 | if (unwritten) { |
349 | ret = -EFAULT; | |
350 | goto out; | |
351 | } | |
00731155 CW |
352 | } |
353 | ||
6a2c4232 | 354 | drm_clflush_virt_range(vaddr, args->size); |
00731155 | 355 | i915_gem_chipset_flush(dev); |
063e4e6b PZ |
356 | |
357 | out: | |
de152b62 | 358 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 359 | return ret; |
00731155 CW |
360 | } |
361 | ||
42dcedd4 CW |
362 | void *i915_gem_object_alloc(struct drm_device *dev) |
363 | { | |
364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
efab6d8d | 365 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
366 | } |
367 | ||
368 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
369 | { | |
370 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
efab6d8d | 371 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
372 | } |
373 | ||
ff72145b DA |
374 | static int |
375 | i915_gem_create(struct drm_file *file, | |
376 | struct drm_device *dev, | |
377 | uint64_t size, | |
378 | uint32_t *handle_p) | |
673a394b | 379 | { |
05394f39 | 380 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
381 | int ret; |
382 | u32 handle; | |
673a394b | 383 | |
ff72145b | 384 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
385 | if (size == 0) |
386 | return -EINVAL; | |
673a394b EA |
387 | |
388 | /* Allocate the new object */ | |
ff72145b | 389 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
390 | if (obj == NULL) |
391 | return -ENOMEM; | |
392 | ||
05394f39 | 393 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 394 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
395 | drm_gem_object_unreference_unlocked(&obj->base); |
396 | if (ret) | |
397 | return ret; | |
202f2fef | 398 | |
ff72145b | 399 | *handle_p = handle; |
673a394b EA |
400 | return 0; |
401 | } | |
402 | ||
ff72145b DA |
403 | int |
404 | i915_gem_dumb_create(struct drm_file *file, | |
405 | struct drm_device *dev, | |
406 | struct drm_mode_create_dumb *args) | |
407 | { | |
408 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 409 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
410 | args->size = args->pitch * args->height; |
411 | return i915_gem_create(file, dev, | |
da6b51d0 | 412 | args->size, &args->handle); |
ff72145b DA |
413 | } |
414 | ||
ff72145b DA |
415 | /** |
416 | * Creates a new mm object and returns a handle to it. | |
417 | */ | |
418 | int | |
419 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
420 | struct drm_file *file) | |
421 | { | |
422 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 423 | |
ff72145b | 424 | return i915_gem_create(file, dev, |
da6b51d0 | 425 | args->size, &args->handle); |
ff72145b DA |
426 | } |
427 | ||
8461d226 DV |
428 | static inline int |
429 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
430 | const char *gpu_vaddr, int gpu_offset, | |
431 | int length) | |
432 | { | |
433 | int ret, cpu_offset = 0; | |
434 | ||
435 | while (length > 0) { | |
436 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
437 | int this_length = min(cacheline_end - gpu_offset, length); | |
438 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
439 | ||
440 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
441 | gpu_vaddr + swizzled_gpu_offset, | |
442 | this_length); | |
443 | if (ret) | |
444 | return ret + length; | |
445 | ||
446 | cpu_offset += this_length; | |
447 | gpu_offset += this_length; | |
448 | length -= this_length; | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
8c59967c | 454 | static inline int |
4f0c7cfb BW |
455 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
456 | const char __user *cpu_vaddr, | |
8c59967c DV |
457 | int length) |
458 | { | |
459 | int ret, cpu_offset = 0; | |
460 | ||
461 | while (length > 0) { | |
462 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
463 | int this_length = min(cacheline_end - gpu_offset, length); | |
464 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
465 | ||
466 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
467 | cpu_vaddr + cpu_offset, | |
468 | this_length); | |
469 | if (ret) | |
470 | return ret + length; | |
471 | ||
472 | cpu_offset += this_length; | |
473 | gpu_offset += this_length; | |
474 | length -= this_length; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
4c914c0c BV |
480 | /* |
481 | * Pins the specified object's pages and synchronizes the object with | |
482 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
483 | * flush the object from the CPU cache. | |
484 | */ | |
485 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
486 | int *needs_clflush) | |
487 | { | |
488 | int ret; | |
489 | ||
490 | *needs_clflush = 0; | |
491 | ||
492 | if (!obj->base.filp) | |
493 | return -EINVAL; | |
494 | ||
495 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
496 | /* If we're not in the cpu read domain, set ourself into the gtt | |
497 | * read domain and manually flush cachelines (if required). This | |
498 | * optimizes for the case when the gpu will dirty the data | |
499 | * anyway again before the next pread happens. */ | |
500 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
501 | obj->cache_level); | |
502 | ret = i915_gem_object_wait_rendering(obj, true); | |
503 | if (ret) | |
504 | return ret; | |
505 | } | |
506 | ||
507 | ret = i915_gem_object_get_pages(obj); | |
508 | if (ret) | |
509 | return ret; | |
510 | ||
511 | i915_gem_object_pin_pages(obj); | |
512 | ||
513 | return ret; | |
514 | } | |
515 | ||
d174bd64 DV |
516 | /* Per-page copy function for the shmem pread fastpath. |
517 | * Flushes invalid cachelines before reading the target if | |
518 | * needs_clflush is set. */ | |
eb01459f | 519 | static int |
d174bd64 DV |
520 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
521 | char __user *user_data, | |
522 | bool page_do_bit17_swizzling, bool needs_clflush) | |
523 | { | |
524 | char *vaddr; | |
525 | int ret; | |
526 | ||
e7e58eb5 | 527 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
528 | return -EINVAL; |
529 | ||
530 | vaddr = kmap_atomic(page); | |
531 | if (needs_clflush) | |
532 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
533 | page_length); | |
534 | ret = __copy_to_user_inatomic(user_data, | |
535 | vaddr + shmem_page_offset, | |
536 | page_length); | |
537 | kunmap_atomic(vaddr); | |
538 | ||
f60d7f0c | 539 | return ret ? -EFAULT : 0; |
d174bd64 DV |
540 | } |
541 | ||
23c18c71 DV |
542 | static void |
543 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
544 | bool swizzled) | |
545 | { | |
e7e58eb5 | 546 | if (unlikely(swizzled)) { |
23c18c71 DV |
547 | unsigned long start = (unsigned long) addr; |
548 | unsigned long end = (unsigned long) addr + length; | |
549 | ||
550 | /* For swizzling simply ensure that we always flush both | |
551 | * channels. Lame, but simple and it works. Swizzled | |
552 | * pwrite/pread is far from a hotpath - current userspace | |
553 | * doesn't use it at all. */ | |
554 | start = round_down(start, 128); | |
555 | end = round_up(end, 128); | |
556 | ||
557 | drm_clflush_virt_range((void *)start, end - start); | |
558 | } else { | |
559 | drm_clflush_virt_range(addr, length); | |
560 | } | |
561 | ||
562 | } | |
563 | ||
d174bd64 DV |
564 | /* Only difference to the fast-path function is that this can handle bit17 |
565 | * and uses non-atomic copy and kmap functions. */ | |
566 | static int | |
567 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
568 | char __user *user_data, | |
569 | bool page_do_bit17_swizzling, bool needs_clflush) | |
570 | { | |
571 | char *vaddr; | |
572 | int ret; | |
573 | ||
574 | vaddr = kmap(page); | |
575 | if (needs_clflush) | |
23c18c71 DV |
576 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
577 | page_length, | |
578 | page_do_bit17_swizzling); | |
d174bd64 DV |
579 | |
580 | if (page_do_bit17_swizzling) | |
581 | ret = __copy_to_user_swizzled(user_data, | |
582 | vaddr, shmem_page_offset, | |
583 | page_length); | |
584 | else | |
585 | ret = __copy_to_user(user_data, | |
586 | vaddr + shmem_page_offset, | |
587 | page_length); | |
588 | kunmap(page); | |
589 | ||
f60d7f0c | 590 | return ret ? - EFAULT : 0; |
d174bd64 DV |
591 | } |
592 | ||
eb01459f | 593 | static int |
dbf7bff0 DV |
594 | i915_gem_shmem_pread(struct drm_device *dev, |
595 | struct drm_i915_gem_object *obj, | |
596 | struct drm_i915_gem_pread *args, | |
597 | struct drm_file *file) | |
eb01459f | 598 | { |
8461d226 | 599 | char __user *user_data; |
eb01459f | 600 | ssize_t remain; |
8461d226 | 601 | loff_t offset; |
eb2c0c81 | 602 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 603 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 604 | int prefaulted = 0; |
8489731c | 605 | int needs_clflush = 0; |
67d5a50c | 606 | struct sg_page_iter sg_iter; |
eb01459f | 607 | |
2bb4629a | 608 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
609 | remain = args->size; |
610 | ||
8461d226 | 611 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 612 | |
4c914c0c | 613 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
614 | if (ret) |
615 | return ret; | |
616 | ||
8461d226 | 617 | offset = args->offset; |
eb01459f | 618 | |
67d5a50c ID |
619 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
620 | offset >> PAGE_SHIFT) { | |
2db76d7c | 621 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
622 | |
623 | if (remain <= 0) | |
624 | break; | |
625 | ||
eb01459f EA |
626 | /* Operation in this page |
627 | * | |
eb01459f | 628 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
629 | * page_length = bytes to copy for this page |
630 | */ | |
c8cbbb8b | 631 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
632 | page_length = remain; |
633 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
634 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 635 | |
8461d226 DV |
636 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
637 | (page_to_phys(page) & (1 << 17)) != 0; | |
638 | ||
d174bd64 DV |
639 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
640 | user_data, page_do_bit17_swizzling, | |
641 | needs_clflush); | |
642 | if (ret == 0) | |
643 | goto next_page; | |
dbf7bff0 | 644 | |
dbf7bff0 DV |
645 | mutex_unlock(&dev->struct_mutex); |
646 | ||
d330a953 | 647 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 648 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
649 | /* Userspace is tricking us, but we've already clobbered |
650 | * its pages with the prefault and promised to write the | |
651 | * data up to the first fault. Hence ignore any errors | |
652 | * and just continue. */ | |
653 | (void)ret; | |
654 | prefaulted = 1; | |
655 | } | |
eb01459f | 656 | |
d174bd64 DV |
657 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
658 | user_data, page_do_bit17_swizzling, | |
659 | needs_clflush); | |
eb01459f | 660 | |
dbf7bff0 | 661 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 662 | |
f60d7f0c | 663 | if (ret) |
8461d226 | 664 | goto out; |
8461d226 | 665 | |
17793c9a | 666 | next_page: |
eb01459f | 667 | remain -= page_length; |
8461d226 | 668 | user_data += page_length; |
eb01459f EA |
669 | offset += page_length; |
670 | } | |
671 | ||
4f27b75d | 672 | out: |
f60d7f0c CW |
673 | i915_gem_object_unpin_pages(obj); |
674 | ||
eb01459f EA |
675 | return ret; |
676 | } | |
677 | ||
673a394b EA |
678 | /** |
679 | * Reads data from the object referenced by handle. | |
680 | * | |
681 | * On error, the contents of *data are undefined. | |
682 | */ | |
683 | int | |
684 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 685 | struct drm_file *file) |
673a394b EA |
686 | { |
687 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 688 | struct drm_i915_gem_object *obj; |
35b62a89 | 689 | int ret = 0; |
673a394b | 690 | |
51311d0a CW |
691 | if (args->size == 0) |
692 | return 0; | |
693 | ||
694 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 695 | to_user_ptr(args->data_ptr), |
51311d0a CW |
696 | args->size)) |
697 | return -EFAULT; | |
698 | ||
4f27b75d | 699 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 700 | if (ret) |
4f27b75d | 701 | return ret; |
673a394b | 702 | |
05394f39 | 703 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 704 | if (&obj->base == NULL) { |
1d7cfea1 CW |
705 | ret = -ENOENT; |
706 | goto unlock; | |
4f27b75d | 707 | } |
673a394b | 708 | |
7dcd2499 | 709 | /* Bounds check source. */ |
05394f39 CW |
710 | if (args->offset > obj->base.size || |
711 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 712 | ret = -EINVAL; |
35b62a89 | 713 | goto out; |
ce9d419d CW |
714 | } |
715 | ||
1286ff73 DV |
716 | /* prime objects have no backing filp to GEM pread/pwrite |
717 | * pages from. | |
718 | */ | |
719 | if (!obj->base.filp) { | |
720 | ret = -EINVAL; | |
721 | goto out; | |
722 | } | |
723 | ||
db53a302 CW |
724 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
725 | ||
dbf7bff0 | 726 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 727 | |
35b62a89 | 728 | out: |
05394f39 | 729 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 730 | unlock: |
4f27b75d | 731 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 732 | return ret; |
673a394b EA |
733 | } |
734 | ||
0839ccb8 KP |
735 | /* This is the fast write path which cannot handle |
736 | * page faults in the source data | |
9b7530cc | 737 | */ |
0839ccb8 KP |
738 | |
739 | static inline int | |
740 | fast_user_write(struct io_mapping *mapping, | |
741 | loff_t page_base, int page_offset, | |
742 | char __user *user_data, | |
743 | int length) | |
9b7530cc | 744 | { |
4f0c7cfb BW |
745 | void __iomem *vaddr_atomic; |
746 | void *vaddr; | |
0839ccb8 | 747 | unsigned long unwritten; |
9b7530cc | 748 | |
3e4d3af5 | 749 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
750 | /* We can use the cpu mem copy function because this is X86. */ |
751 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
752 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 753 | user_data, length); |
3e4d3af5 | 754 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 755 | return unwritten; |
0839ccb8 KP |
756 | } |
757 | ||
3de09aa3 EA |
758 | /** |
759 | * This is the fast pwrite path, where we copy the data directly from the | |
760 | * user into the GTT, uncached. | |
761 | */ | |
673a394b | 762 | static int |
05394f39 CW |
763 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
764 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 765 | struct drm_i915_gem_pwrite *args, |
05394f39 | 766 | struct drm_file *file) |
673a394b | 767 | { |
3e31c6c0 | 768 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 769 | ssize_t remain; |
0839ccb8 | 770 | loff_t offset, page_base; |
673a394b | 771 | char __user *user_data; |
935aaa69 DV |
772 | int page_offset, page_length, ret; |
773 | ||
1ec9e26d | 774 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
775 | if (ret) |
776 | goto out; | |
777 | ||
778 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
779 | if (ret) | |
780 | goto out_unpin; | |
781 | ||
782 | ret = i915_gem_object_put_fence(obj); | |
783 | if (ret) | |
784 | goto out_unpin; | |
673a394b | 785 | |
2bb4629a | 786 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 787 | remain = args->size; |
673a394b | 788 | |
f343c5f6 | 789 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b | 790 | |
77a0d1ca | 791 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
063e4e6b | 792 | |
673a394b EA |
793 | while (remain > 0) { |
794 | /* Operation in this page | |
795 | * | |
0839ccb8 KP |
796 | * page_base = page offset within aperture |
797 | * page_offset = offset within page | |
798 | * page_length = bytes to copy for this page | |
673a394b | 799 | */ |
c8cbbb8b CW |
800 | page_base = offset & PAGE_MASK; |
801 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
802 | page_length = remain; |
803 | if ((page_offset + remain) > PAGE_SIZE) | |
804 | page_length = PAGE_SIZE - page_offset; | |
805 | ||
0839ccb8 | 806 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
807 | * source page isn't available. Return the error and we'll |
808 | * retry in the slow path. | |
0839ccb8 | 809 | */ |
5d4545ae | 810 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
811 | page_offset, user_data, page_length)) { |
812 | ret = -EFAULT; | |
063e4e6b | 813 | goto out_flush; |
935aaa69 | 814 | } |
673a394b | 815 | |
0839ccb8 KP |
816 | remain -= page_length; |
817 | user_data += page_length; | |
818 | offset += page_length; | |
673a394b | 819 | } |
673a394b | 820 | |
063e4e6b | 821 | out_flush: |
de152b62 | 822 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 823 | out_unpin: |
d7f46fc4 | 824 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 825 | out: |
3de09aa3 | 826 | return ret; |
673a394b EA |
827 | } |
828 | ||
d174bd64 DV |
829 | /* Per-page copy function for the shmem pwrite fastpath. |
830 | * Flushes invalid cachelines before writing to the target if | |
831 | * needs_clflush_before is set and flushes out any written cachelines after | |
832 | * writing if needs_clflush is set. */ | |
3043c60c | 833 | static int |
d174bd64 DV |
834 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
835 | char __user *user_data, | |
836 | bool page_do_bit17_swizzling, | |
837 | bool needs_clflush_before, | |
838 | bool needs_clflush_after) | |
673a394b | 839 | { |
d174bd64 | 840 | char *vaddr; |
673a394b | 841 | int ret; |
3de09aa3 | 842 | |
e7e58eb5 | 843 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 844 | return -EINVAL; |
3de09aa3 | 845 | |
d174bd64 DV |
846 | vaddr = kmap_atomic(page); |
847 | if (needs_clflush_before) | |
848 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
849 | page_length); | |
c2831a94 CW |
850 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
851 | user_data, page_length); | |
d174bd64 DV |
852 | if (needs_clflush_after) |
853 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
854 | page_length); | |
855 | kunmap_atomic(vaddr); | |
3de09aa3 | 856 | |
755d2218 | 857 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
858 | } |
859 | ||
d174bd64 DV |
860 | /* Only difference to the fast-path function is that this can handle bit17 |
861 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 862 | static int |
d174bd64 DV |
863 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
864 | char __user *user_data, | |
865 | bool page_do_bit17_swizzling, | |
866 | bool needs_clflush_before, | |
867 | bool needs_clflush_after) | |
673a394b | 868 | { |
d174bd64 DV |
869 | char *vaddr; |
870 | int ret; | |
e5281ccd | 871 | |
d174bd64 | 872 | vaddr = kmap(page); |
e7e58eb5 | 873 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
874 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
875 | page_length, | |
876 | page_do_bit17_swizzling); | |
d174bd64 DV |
877 | if (page_do_bit17_swizzling) |
878 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
879 | user_data, |
880 | page_length); | |
d174bd64 DV |
881 | else |
882 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
883 | user_data, | |
884 | page_length); | |
885 | if (needs_clflush_after) | |
23c18c71 DV |
886 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
887 | page_length, | |
888 | page_do_bit17_swizzling); | |
d174bd64 | 889 | kunmap(page); |
40123c1f | 890 | |
755d2218 | 891 | return ret ? -EFAULT : 0; |
40123c1f EA |
892 | } |
893 | ||
40123c1f | 894 | static int |
e244a443 DV |
895 | i915_gem_shmem_pwrite(struct drm_device *dev, |
896 | struct drm_i915_gem_object *obj, | |
897 | struct drm_i915_gem_pwrite *args, | |
898 | struct drm_file *file) | |
40123c1f | 899 | { |
40123c1f | 900 | ssize_t remain; |
8c59967c DV |
901 | loff_t offset; |
902 | char __user *user_data; | |
eb2c0c81 | 903 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 904 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 905 | int hit_slowpath = 0; |
58642885 DV |
906 | int needs_clflush_after = 0; |
907 | int needs_clflush_before = 0; | |
67d5a50c | 908 | struct sg_page_iter sg_iter; |
40123c1f | 909 | |
2bb4629a | 910 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
911 | remain = args->size; |
912 | ||
8c59967c | 913 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 914 | |
58642885 DV |
915 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
916 | /* If we're not in the cpu write domain, set ourself into the gtt | |
917 | * write domain and manually flush cachelines (if required). This | |
918 | * optimizes for the case when the gpu will use the data | |
919 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 920 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
921 | ret = i915_gem_object_wait_rendering(obj, false); |
922 | if (ret) | |
923 | return ret; | |
58642885 | 924 | } |
c76ce038 CW |
925 | /* Same trick applies to invalidate partially written cachelines read |
926 | * before writing. */ | |
927 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
928 | needs_clflush_before = | |
929 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 930 | |
755d2218 CW |
931 | ret = i915_gem_object_get_pages(obj); |
932 | if (ret) | |
933 | return ret; | |
934 | ||
77a0d1ca | 935 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 936 | |
755d2218 CW |
937 | i915_gem_object_pin_pages(obj); |
938 | ||
673a394b | 939 | offset = args->offset; |
05394f39 | 940 | obj->dirty = 1; |
673a394b | 941 | |
67d5a50c ID |
942 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
943 | offset >> PAGE_SHIFT) { | |
2db76d7c | 944 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 945 | int partial_cacheline_write; |
e5281ccd | 946 | |
9da3da66 CW |
947 | if (remain <= 0) |
948 | break; | |
949 | ||
40123c1f EA |
950 | /* Operation in this page |
951 | * | |
40123c1f | 952 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
953 | * page_length = bytes to copy for this page |
954 | */ | |
c8cbbb8b | 955 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
956 | |
957 | page_length = remain; | |
958 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
959 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 960 | |
58642885 DV |
961 | /* If we don't overwrite a cacheline completely we need to be |
962 | * careful to have up-to-date data by first clflushing. Don't | |
963 | * overcomplicate things and flush the entire patch. */ | |
964 | partial_cacheline_write = needs_clflush_before && | |
965 | ((shmem_page_offset | page_length) | |
966 | & (boot_cpu_data.x86_clflush_size - 1)); | |
967 | ||
8c59967c DV |
968 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
969 | (page_to_phys(page) & (1 << 17)) != 0; | |
970 | ||
d174bd64 DV |
971 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
972 | user_data, page_do_bit17_swizzling, | |
973 | partial_cacheline_write, | |
974 | needs_clflush_after); | |
975 | if (ret == 0) | |
976 | goto next_page; | |
e244a443 DV |
977 | |
978 | hit_slowpath = 1; | |
e244a443 | 979 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
980 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
981 | user_data, page_do_bit17_swizzling, | |
982 | partial_cacheline_write, | |
983 | needs_clflush_after); | |
40123c1f | 984 | |
e244a443 | 985 | mutex_lock(&dev->struct_mutex); |
755d2218 | 986 | |
755d2218 | 987 | if (ret) |
8c59967c | 988 | goto out; |
8c59967c | 989 | |
17793c9a | 990 | next_page: |
40123c1f | 991 | remain -= page_length; |
8c59967c | 992 | user_data += page_length; |
40123c1f | 993 | offset += page_length; |
673a394b EA |
994 | } |
995 | ||
fbd5a26d | 996 | out: |
755d2218 CW |
997 | i915_gem_object_unpin_pages(obj); |
998 | ||
e244a443 | 999 | if (hit_slowpath) { |
8dcf015e DV |
1000 | /* |
1001 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1002 | * cachelines in-line while writing and the object moved | |
1003 | * out of the cpu write domain while we've dropped the lock. | |
1004 | */ | |
1005 | if (!needs_clflush_after && | |
1006 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1007 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1008 | needs_clflush_after = true; |
e244a443 | 1009 | } |
8c59967c | 1010 | } |
673a394b | 1011 | |
58642885 | 1012 | if (needs_clflush_after) |
e76e9aeb | 1013 | i915_gem_chipset_flush(dev); |
ed75a55b VS |
1014 | else |
1015 | obj->cache_dirty = true; | |
58642885 | 1016 | |
de152b62 | 1017 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1018 | return ret; |
673a394b EA |
1019 | } |
1020 | ||
1021 | /** | |
1022 | * Writes data to the object referenced by handle. | |
1023 | * | |
1024 | * On error, the contents of the buffer that were to be modified are undefined. | |
1025 | */ | |
1026 | int | |
1027 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1028 | struct drm_file *file) |
673a394b | 1029 | { |
5d77d9c5 | 1030 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1031 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1032 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1033 | int ret; |
1034 | ||
1035 | if (args->size == 0) | |
1036 | return 0; | |
1037 | ||
1038 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1039 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1040 | args->size)) |
1041 | return -EFAULT; | |
1042 | ||
d330a953 | 1043 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1044 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1045 | args->size); | |
1046 | if (ret) | |
1047 | return -EFAULT; | |
1048 | } | |
673a394b | 1049 | |
5d77d9c5 ID |
1050 | intel_runtime_pm_get(dev_priv); |
1051 | ||
fbd5a26d | 1052 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1053 | if (ret) |
5d77d9c5 | 1054 | goto put_rpm; |
1d7cfea1 | 1055 | |
05394f39 | 1056 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1057 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1058 | ret = -ENOENT; |
1059 | goto unlock; | |
fbd5a26d | 1060 | } |
673a394b | 1061 | |
7dcd2499 | 1062 | /* Bounds check destination. */ |
05394f39 CW |
1063 | if (args->offset > obj->base.size || |
1064 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1065 | ret = -EINVAL; |
35b62a89 | 1066 | goto out; |
ce9d419d CW |
1067 | } |
1068 | ||
1286ff73 DV |
1069 | /* prime objects have no backing filp to GEM pread/pwrite |
1070 | * pages from. | |
1071 | */ | |
1072 | if (!obj->base.filp) { | |
1073 | ret = -EINVAL; | |
1074 | goto out; | |
1075 | } | |
1076 | ||
db53a302 CW |
1077 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1078 | ||
935aaa69 | 1079 | ret = -EFAULT; |
673a394b EA |
1080 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1081 | * it would end up going through the fenced access, and we'll get | |
1082 | * different detiling behavior between reading and writing. | |
1083 | * pread/pwrite currently are reading and writing from the CPU | |
1084 | * perspective, requiring manual detiling by the client. | |
1085 | */ | |
2c22569b CW |
1086 | if (obj->tiling_mode == I915_TILING_NONE && |
1087 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1088 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1089 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1090 | /* Note that the gtt paths might fail with non-page-backed user |
1091 | * pointers (e.g. gtt mappings when moving data between | |
1092 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1093 | } |
673a394b | 1094 | |
6a2c4232 CW |
1095 | if (ret == -EFAULT || ret == -ENOSPC) { |
1096 | if (obj->phys_handle) | |
1097 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1098 | else | |
1099 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1100 | } | |
5c0480f2 | 1101 | |
35b62a89 | 1102 | out: |
05394f39 | 1103 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1104 | unlock: |
fbd5a26d | 1105 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1106 | put_rpm: |
1107 | intel_runtime_pm_put(dev_priv); | |
1108 | ||
673a394b EA |
1109 | return ret; |
1110 | } | |
1111 | ||
b361237b | 1112 | int |
33196ded | 1113 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1114 | bool interruptible) |
1115 | { | |
1f83fee0 | 1116 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1117 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1118 | * -EIO unconditionally for these. */ | |
1119 | if (!interruptible) | |
1120 | return -EIO; | |
1121 | ||
1f83fee0 DV |
1122 | /* Recovery complete, but the reset failed ... */ |
1123 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1124 | return -EIO; |
1125 | ||
6689c167 MA |
1126 | /* |
1127 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1128 | * to work properly to reinit the hw state while the gpu is | |
1129 | * still marked as reset-in-progress. Handle this with a flag. | |
1130 | */ | |
1131 | if (!error->reload_in_reset) | |
1132 | return -EAGAIN; | |
b361237b CW |
1133 | } |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
094f9a54 CW |
1138 | static void fake_irq(unsigned long data) |
1139 | { | |
1140 | wake_up_process((struct task_struct *)data); | |
1141 | } | |
1142 | ||
1143 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1144 | struct intel_engine_cs *ring) |
094f9a54 CW |
1145 | { |
1146 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1147 | } | |
1148 | ||
eed29a5b | 1149 | static int __i915_spin_request(struct drm_i915_gem_request *req) |
b29c19b6 | 1150 | { |
2def4ad9 CW |
1151 | unsigned long timeout; |
1152 | ||
eed29a5b | 1153 | if (i915_gem_request_get_ring(req)->irq_refcount) |
2def4ad9 CW |
1154 | return -EBUSY; |
1155 | ||
1156 | timeout = jiffies + 1; | |
1157 | while (!need_resched()) { | |
eed29a5b | 1158 | if (i915_gem_request_completed(req, true)) |
2def4ad9 CW |
1159 | return 0; |
1160 | ||
1161 | if (time_after_eq(jiffies, timeout)) | |
1162 | break; | |
b29c19b6 | 1163 | |
2def4ad9 CW |
1164 | cpu_relax_lowlatency(); |
1165 | } | |
eed29a5b | 1166 | if (i915_gem_request_completed(req, false)) |
2def4ad9 CW |
1167 | return 0; |
1168 | ||
1169 | return -EAGAIN; | |
b29c19b6 CW |
1170 | } |
1171 | ||
b361237b | 1172 | /** |
9c654818 JH |
1173 | * __i915_wait_request - wait until execution of request has finished |
1174 | * @req: duh! | |
1175 | * @reset_counter: reset sequence associated with the given request | |
b361237b CW |
1176 | * @interruptible: do an interruptible wait (normally yes) |
1177 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1178 | * | |
f69061be DV |
1179 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1180 | * values have been read by the caller in an smp safe manner. Where read-side | |
1181 | * locks are involved, it is sufficient to read the reset_counter before | |
1182 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1183 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1184 | * inserted. | |
1185 | * | |
9c654818 | 1186 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1187 | * errno with remaining time filled in timeout argument. |
1188 | */ | |
9c654818 | 1189 | int __i915_wait_request(struct drm_i915_gem_request *req, |
f69061be | 1190 | unsigned reset_counter, |
b29c19b6 | 1191 | bool interruptible, |
5ed0bdf2 | 1192 | s64 *timeout, |
2e1b8730 | 1193 | struct intel_rps_client *rps) |
b361237b | 1194 | { |
9c654818 | 1195 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
3d13ef2e | 1196 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1197 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1198 | const bool irq_test_in_progress = |
1199 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 | 1200 | DEFINE_WAIT(wait); |
47e9766d | 1201 | unsigned long timeout_expire; |
5ed0bdf2 | 1202 | s64 before, now; |
b361237b CW |
1203 | int ret; |
1204 | ||
9df7575f | 1205 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1206 | |
b4716185 CW |
1207 | if (list_empty(&req->list)) |
1208 | return 0; | |
1209 | ||
1b5a433a | 1210 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1211 | return 0; |
1212 | ||
7bd0e226 DV |
1213 | timeout_expire = timeout ? |
1214 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; | |
b361237b | 1215 | |
2e1b8730 | 1216 | if (INTEL_INFO(dev_priv)->gen >= 6) |
e61b9958 | 1217 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
b361237b | 1218 | |
094f9a54 | 1219 | /* Record current time in case interrupted by signal, or wedged */ |
74328ee5 | 1220 | trace_i915_gem_request_wait_begin(req); |
5ed0bdf2 | 1221 | before = ktime_get_raw_ns(); |
2def4ad9 CW |
1222 | |
1223 | /* Optimistic spin for the next jiffie before touching IRQs */ | |
1224 | ret = __i915_spin_request(req); | |
1225 | if (ret == 0) | |
1226 | goto out; | |
1227 | ||
1228 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) { | |
1229 | ret = -ENODEV; | |
1230 | goto out; | |
1231 | } | |
1232 | ||
094f9a54 CW |
1233 | for (;;) { |
1234 | struct timer_list timer; | |
b361237b | 1235 | |
094f9a54 CW |
1236 | prepare_to_wait(&ring->irq_queue, &wait, |
1237 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1238 | |
f69061be DV |
1239 | /* We need to check whether any gpu reset happened in between |
1240 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1241 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1242 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1243 | * is truely gone. */ | |
1244 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1245 | if (ret == 0) | |
1246 | ret = -EAGAIN; | |
1247 | break; | |
1248 | } | |
f69061be | 1249 | |
1b5a433a | 1250 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1251 | ret = 0; |
1252 | break; | |
1253 | } | |
b361237b | 1254 | |
094f9a54 CW |
1255 | if (interruptible && signal_pending(current)) { |
1256 | ret = -ERESTARTSYS; | |
1257 | break; | |
1258 | } | |
1259 | ||
47e9766d | 1260 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1261 | ret = -ETIME; |
1262 | break; | |
1263 | } | |
1264 | ||
1265 | timer.function = NULL; | |
1266 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1267 | unsigned long expire; |
1268 | ||
094f9a54 | 1269 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1270 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1271 | mod_timer(&timer, expire); |
1272 | } | |
1273 | ||
5035c275 | 1274 | io_schedule(); |
094f9a54 | 1275 | |
094f9a54 CW |
1276 | if (timer.function) { |
1277 | del_singleshot_timer_sync(&timer); | |
1278 | destroy_timer_on_stack(&timer); | |
1279 | } | |
1280 | } | |
168c3f21 MK |
1281 | if (!irq_test_in_progress) |
1282 | ring->irq_put(ring); | |
094f9a54 CW |
1283 | |
1284 | finish_wait(&ring->irq_queue, &wait); | |
b361237b | 1285 | |
2def4ad9 CW |
1286 | out: |
1287 | now = ktime_get_raw_ns(); | |
1288 | trace_i915_gem_request_wait_end(req); | |
1289 | ||
b361237b | 1290 | if (timeout) { |
5ed0bdf2 TG |
1291 | s64 tres = *timeout - (now - before); |
1292 | ||
1293 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1294 | |
1295 | /* | |
1296 | * Apparently ktime isn't accurate enough and occasionally has a | |
1297 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1298 | * things up to make the test happy. We allow up to 1 jiffy. | |
1299 | * | |
1300 | * This is a regrssion from the timespec->ktime conversion. | |
1301 | */ | |
1302 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1303 | *timeout = 0; | |
b361237b CW |
1304 | } |
1305 | ||
094f9a54 | 1306 | return ret; |
b361237b CW |
1307 | } |
1308 | ||
fcfa423c JH |
1309 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
1310 | struct drm_file *file) | |
1311 | { | |
1312 | struct drm_i915_private *dev_private; | |
1313 | struct drm_i915_file_private *file_priv; | |
1314 | ||
1315 | WARN_ON(!req || !file || req->file_priv); | |
1316 | ||
1317 | if (!req || !file) | |
1318 | return -EINVAL; | |
1319 | ||
1320 | if (req->file_priv) | |
1321 | return -EINVAL; | |
1322 | ||
1323 | dev_private = req->ring->dev->dev_private; | |
1324 | file_priv = file->driver_priv; | |
1325 | ||
1326 | spin_lock(&file_priv->mm.lock); | |
1327 | req->file_priv = file_priv; | |
1328 | list_add_tail(&req->client_list, &file_priv->mm.request_list); | |
1329 | spin_unlock(&file_priv->mm.lock); | |
1330 | ||
1331 | req->pid = get_pid(task_pid(current)); | |
1332 | ||
1333 | return 0; | |
1334 | } | |
1335 | ||
b4716185 CW |
1336 | static inline void |
1337 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
1338 | { | |
1339 | struct drm_i915_file_private *file_priv = request->file_priv; | |
1340 | ||
1341 | if (!file_priv) | |
1342 | return; | |
1343 | ||
1344 | spin_lock(&file_priv->mm.lock); | |
1345 | list_del(&request->client_list); | |
1346 | request->file_priv = NULL; | |
1347 | spin_unlock(&file_priv->mm.lock); | |
fcfa423c JH |
1348 | |
1349 | put_pid(request->pid); | |
1350 | request->pid = NULL; | |
b4716185 CW |
1351 | } |
1352 | ||
1353 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) | |
1354 | { | |
1355 | trace_i915_gem_request_retire(request); | |
1356 | ||
6d65ba94 NH |
1357 | if (i915.enable_execlists) |
1358 | intel_lr_context_complete_check(request); | |
1359 | ||
b4716185 CW |
1360 | /* We know the GPU must have read the request to have |
1361 | * sent us the seqno + interrupt, so use the position | |
1362 | * of tail of the request to update the last known position | |
1363 | * of the GPU head. | |
1364 | * | |
1365 | * Note this requires that we are always called in request | |
1366 | * completion order. | |
1367 | */ | |
1368 | request->ringbuf->last_retired_head = request->postfix; | |
1369 | ||
1370 | list_del_init(&request->list); | |
1371 | i915_gem_request_remove_from_client(request); | |
1372 | ||
b4716185 CW |
1373 | i915_gem_request_unreference(request); |
1374 | } | |
1375 | ||
1376 | static void | |
1377 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) | |
1378 | { | |
1379 | struct intel_engine_cs *engine = req->ring; | |
1380 | struct drm_i915_gem_request *tmp; | |
1381 | ||
1382 | lockdep_assert_held(&engine->dev->struct_mutex); | |
1383 | ||
1384 | if (list_empty(&req->list)) | |
1385 | return; | |
1386 | ||
1387 | do { | |
1388 | tmp = list_first_entry(&engine->request_list, | |
1389 | typeof(*tmp), list); | |
1390 | ||
1391 | i915_gem_request_retire(tmp); | |
1392 | } while (tmp != req); | |
1393 | ||
1394 | WARN_ON(i915_verify_lists(engine->dev)); | |
1395 | } | |
1396 | ||
b361237b | 1397 | /** |
a4b3a571 | 1398 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1399 | * request and object lists appropriately for that event. |
1400 | */ | |
1401 | int | |
a4b3a571 | 1402 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1403 | { |
a4b3a571 DV |
1404 | struct drm_device *dev; |
1405 | struct drm_i915_private *dev_priv; | |
1406 | bool interruptible; | |
b361237b CW |
1407 | int ret; |
1408 | ||
a4b3a571 DV |
1409 | BUG_ON(req == NULL); |
1410 | ||
1411 | dev = req->ring->dev; | |
1412 | dev_priv = dev->dev_private; | |
1413 | interruptible = dev_priv->mm.interruptible; | |
1414 | ||
b361237b | 1415 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1416 | |
33196ded | 1417 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1418 | if (ret) |
1419 | return ret; | |
1420 | ||
b4716185 CW |
1421 | ret = __i915_wait_request(req, |
1422 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
9c654818 | 1423 | interruptible, NULL, NULL); |
b4716185 CW |
1424 | if (ret) |
1425 | return ret; | |
d26e3af8 | 1426 | |
b4716185 | 1427 | __i915_gem_request_retire__upto(req); |
d26e3af8 CW |
1428 | return 0; |
1429 | } | |
1430 | ||
b361237b CW |
1431 | /** |
1432 | * Ensures that all rendering to the object has completed and the object is | |
1433 | * safe to unbind from the GTT or access from the CPU. | |
1434 | */ | |
2e2f351d | 1435 | int |
b361237b CW |
1436 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1437 | bool readonly) | |
1438 | { | |
b4716185 | 1439 | int ret, i; |
b361237b | 1440 | |
b4716185 | 1441 | if (!obj->active) |
b361237b CW |
1442 | return 0; |
1443 | ||
b4716185 CW |
1444 | if (readonly) { |
1445 | if (obj->last_write_req != NULL) { | |
1446 | ret = i915_wait_request(obj->last_write_req); | |
1447 | if (ret) | |
1448 | return ret; | |
b361237b | 1449 | |
b4716185 CW |
1450 | i = obj->last_write_req->ring->id; |
1451 | if (obj->last_read_req[i] == obj->last_write_req) | |
1452 | i915_gem_object_retire__read(obj, i); | |
1453 | else | |
1454 | i915_gem_object_retire__write(obj); | |
1455 | } | |
1456 | } else { | |
1457 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1458 | if (obj->last_read_req[i] == NULL) | |
1459 | continue; | |
1460 | ||
1461 | ret = i915_wait_request(obj->last_read_req[i]); | |
1462 | if (ret) | |
1463 | return ret; | |
1464 | ||
1465 | i915_gem_object_retire__read(obj, i); | |
1466 | } | |
1467 | RQ_BUG_ON(obj->active); | |
1468 | } | |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | static void | |
1474 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, | |
1475 | struct drm_i915_gem_request *req) | |
1476 | { | |
1477 | int ring = req->ring->id; | |
1478 | ||
1479 | if (obj->last_read_req[ring] == req) | |
1480 | i915_gem_object_retire__read(obj, ring); | |
1481 | else if (obj->last_write_req == req) | |
1482 | i915_gem_object_retire__write(obj); | |
1483 | ||
1484 | __i915_gem_request_retire__upto(req); | |
b361237b CW |
1485 | } |
1486 | ||
3236f57a CW |
1487 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1488 | * as the object state may change during this call. | |
1489 | */ | |
1490 | static __must_check int | |
1491 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
2e1b8730 | 1492 | struct intel_rps_client *rps, |
3236f57a CW |
1493 | bool readonly) |
1494 | { | |
1495 | struct drm_device *dev = obj->base.dev; | |
1496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b4716185 | 1497 | struct drm_i915_gem_request *requests[I915_NUM_RINGS]; |
f69061be | 1498 | unsigned reset_counter; |
b4716185 | 1499 | int ret, i, n = 0; |
3236f57a CW |
1500 | |
1501 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1502 | BUG_ON(!dev_priv->mm.interruptible); | |
1503 | ||
b4716185 | 1504 | if (!obj->active) |
3236f57a CW |
1505 | return 0; |
1506 | ||
33196ded | 1507 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1508 | if (ret) |
1509 | return ret; | |
1510 | ||
f69061be | 1511 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
b4716185 CW |
1512 | |
1513 | if (readonly) { | |
1514 | struct drm_i915_gem_request *req; | |
1515 | ||
1516 | req = obj->last_write_req; | |
1517 | if (req == NULL) | |
1518 | return 0; | |
1519 | ||
b4716185 CW |
1520 | requests[n++] = i915_gem_request_reference(req); |
1521 | } else { | |
1522 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1523 | struct drm_i915_gem_request *req; | |
1524 | ||
1525 | req = obj->last_read_req[i]; | |
1526 | if (req == NULL) | |
1527 | continue; | |
1528 | ||
b4716185 CW |
1529 | requests[n++] = i915_gem_request_reference(req); |
1530 | } | |
1531 | } | |
1532 | ||
3236f57a | 1533 | mutex_unlock(&dev->struct_mutex); |
b4716185 CW |
1534 | for (i = 0; ret == 0 && i < n; i++) |
1535 | ret = __i915_wait_request(requests[i], reset_counter, true, | |
2e1b8730 | 1536 | NULL, rps); |
3236f57a CW |
1537 | mutex_lock(&dev->struct_mutex); |
1538 | ||
b4716185 CW |
1539 | for (i = 0; i < n; i++) { |
1540 | if (ret == 0) | |
1541 | i915_gem_object_retire_request(obj, requests[i]); | |
1542 | i915_gem_request_unreference(requests[i]); | |
1543 | } | |
1544 | ||
1545 | return ret; | |
3236f57a CW |
1546 | } |
1547 | ||
2e1b8730 CW |
1548 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
1549 | { | |
1550 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1551 | return &fpriv->rps; | |
1552 | } | |
1553 | ||
673a394b | 1554 | /** |
2ef7eeaa EA |
1555 | * Called when user space prepares to use an object with the CPU, either |
1556 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1557 | */ |
1558 | int | |
1559 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1560 | struct drm_file *file) |
673a394b EA |
1561 | { |
1562 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1563 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1564 | uint32_t read_domains = args->read_domains; |
1565 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1566 | int ret; |
1567 | ||
2ef7eeaa | 1568 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1569 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1570 | return -EINVAL; |
1571 | ||
21d509e3 | 1572 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1573 | return -EINVAL; |
1574 | ||
1575 | /* Having something in the write domain implies it's in the read | |
1576 | * domain, and only that read domain. Enforce that in the request. | |
1577 | */ | |
1578 | if (write_domain != 0 && read_domains != write_domain) | |
1579 | return -EINVAL; | |
1580 | ||
76c1dec1 | 1581 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1582 | if (ret) |
76c1dec1 | 1583 | return ret; |
1d7cfea1 | 1584 | |
05394f39 | 1585 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1586 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1587 | ret = -ENOENT; |
1588 | goto unlock; | |
76c1dec1 | 1589 | } |
673a394b | 1590 | |
3236f57a CW |
1591 | /* Try to flush the object off the GPU without holding the lock. |
1592 | * We will repeat the flush holding the lock in the normal manner | |
1593 | * to catch cases where we are gazumped. | |
1594 | */ | |
6e4930f6 | 1595 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
2e1b8730 | 1596 | to_rps_client(file), |
6e4930f6 | 1597 | !write_domain); |
3236f57a CW |
1598 | if (ret) |
1599 | goto unref; | |
1600 | ||
43566ded | 1601 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1602 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1603 | else |
e47c68e9 | 1604 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1605 | |
031b698a DV |
1606 | if (write_domain != 0) |
1607 | intel_fb_obj_invalidate(obj, | |
1608 | write_domain == I915_GEM_DOMAIN_GTT ? | |
1609 | ORIGIN_GTT : ORIGIN_CPU); | |
1610 | ||
3236f57a | 1611 | unref: |
05394f39 | 1612 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1613 | unlock: |
673a394b EA |
1614 | mutex_unlock(&dev->struct_mutex); |
1615 | return ret; | |
1616 | } | |
1617 | ||
1618 | /** | |
1619 | * Called when user space has done writes to this buffer | |
1620 | */ | |
1621 | int | |
1622 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1623 | struct drm_file *file) |
673a394b EA |
1624 | { |
1625 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1626 | struct drm_i915_gem_object *obj; |
673a394b EA |
1627 | int ret = 0; |
1628 | ||
76c1dec1 | 1629 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1630 | if (ret) |
76c1dec1 | 1631 | return ret; |
1d7cfea1 | 1632 | |
05394f39 | 1633 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1634 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1635 | ret = -ENOENT; |
1636 | goto unlock; | |
673a394b EA |
1637 | } |
1638 | ||
673a394b | 1639 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1640 | if (obj->pin_display) |
e62b59e4 | 1641 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1642 | |
05394f39 | 1643 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1644 | unlock: |
673a394b EA |
1645 | mutex_unlock(&dev->struct_mutex); |
1646 | return ret; | |
1647 | } | |
1648 | ||
1649 | /** | |
1650 | * Maps the contents of an object, returning the address it is mapped | |
1651 | * into. | |
1652 | * | |
1653 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1654 | * imply a ref on the object itself. | |
34367381 DV |
1655 | * |
1656 | * IMPORTANT: | |
1657 | * | |
1658 | * DRM driver writers who look a this function as an example for how to do GEM | |
1659 | * mmap support, please don't implement mmap support like here. The modern way | |
1660 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1661 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1662 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1663 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1664 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1665 | */ |
1666 | int | |
1667 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1668 | struct drm_file *file) |
673a394b EA |
1669 | { |
1670 | struct drm_i915_gem_mmap *args = data; | |
1671 | struct drm_gem_object *obj; | |
673a394b EA |
1672 | unsigned long addr; |
1673 | ||
1816f923 AG |
1674 | if (args->flags & ~(I915_MMAP_WC)) |
1675 | return -EINVAL; | |
1676 | ||
1677 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) | |
1678 | return -ENODEV; | |
1679 | ||
05394f39 | 1680 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1681 | if (obj == NULL) |
bf79cb91 | 1682 | return -ENOENT; |
673a394b | 1683 | |
1286ff73 DV |
1684 | /* prime objects have no backing filp to GEM mmap |
1685 | * pages from. | |
1686 | */ | |
1687 | if (!obj->filp) { | |
1688 | drm_gem_object_unreference_unlocked(obj); | |
1689 | return -EINVAL; | |
1690 | } | |
1691 | ||
6be5ceb0 | 1692 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1693 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1694 | args->offset); | |
1816f923 AG |
1695 | if (args->flags & I915_MMAP_WC) { |
1696 | struct mm_struct *mm = current->mm; | |
1697 | struct vm_area_struct *vma; | |
1698 | ||
1699 | down_write(&mm->mmap_sem); | |
1700 | vma = find_vma(mm, addr); | |
1701 | if (vma) | |
1702 | vma->vm_page_prot = | |
1703 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1704 | else | |
1705 | addr = -ENOMEM; | |
1706 | up_write(&mm->mmap_sem); | |
1707 | } | |
bc9025bd | 1708 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1709 | if (IS_ERR((void *)addr)) |
1710 | return addr; | |
1711 | ||
1712 | args->addr_ptr = (uint64_t) addr; | |
1713 | ||
1714 | return 0; | |
1715 | } | |
1716 | ||
de151cf6 JB |
1717 | /** |
1718 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
1719 | * @vma: VMA in question |
1720 | * @vmf: fault info | |
de151cf6 JB |
1721 | * |
1722 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1723 | * from userspace. The fault handler takes care of binding the object to | |
1724 | * the GTT (if needed), allocating and programming a fence register (again, | |
1725 | * only if needed based on whether the old reg is still valid or the object | |
1726 | * is tiled) and inserting a new PTE into the faulting process. | |
1727 | * | |
1728 | * Note that the faulting process may involve evicting existing objects | |
1729 | * from the GTT and/or fence registers to make room. So performance may | |
1730 | * suffer if the GTT working set is large or there are few fence registers | |
1731 | * left. | |
1732 | */ | |
1733 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1734 | { | |
05394f39 CW |
1735 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1736 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1737 | struct drm_i915_private *dev_priv = dev->dev_private; |
c5ad54cf | 1738 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
de151cf6 JB |
1739 | pgoff_t page_offset; |
1740 | unsigned long pfn; | |
1741 | int ret = 0; | |
0f973f27 | 1742 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1743 | |
f65c9168 PZ |
1744 | intel_runtime_pm_get(dev_priv); |
1745 | ||
de151cf6 JB |
1746 | /* We don't use vmf->pgoff since that has the fake offset */ |
1747 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1748 | PAGE_SHIFT; | |
1749 | ||
d9bc7e9f CW |
1750 | ret = i915_mutex_lock_interruptible(dev); |
1751 | if (ret) | |
1752 | goto out; | |
a00b10c3 | 1753 | |
db53a302 CW |
1754 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1755 | ||
6e4930f6 CW |
1756 | /* Try to flush the object off the GPU first without holding the lock. |
1757 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1758 | * repeat the flush holding the lock in the normal manner to catch cases | |
1759 | * where we are gazumped. | |
1760 | */ | |
1761 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1762 | if (ret) | |
1763 | goto unlock; | |
1764 | ||
eb119bd6 CW |
1765 | /* Access to snoopable pages through the GTT is incoherent. */ |
1766 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1767 | ret = -EFAULT; |
eb119bd6 CW |
1768 | goto unlock; |
1769 | } | |
1770 | ||
c5ad54cf | 1771 | /* Use a partial view if the object is bigger than the aperture. */ |
e7ded2d7 JL |
1772 | if (obj->base.size >= dev_priv->gtt.mappable_end && |
1773 | obj->tiling_mode == I915_TILING_NONE) { | |
c5ad54cf | 1774 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1775 | |
c5ad54cf JL |
1776 | memset(&view, 0, sizeof(view)); |
1777 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1778 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1779 | view.params.partial.size = | |
1780 | min_t(unsigned int, | |
1781 | chunk_size, | |
1782 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1783 | view.params.partial.offset); | |
1784 | } | |
1785 | ||
1786 | /* Now pin it into the GTT if needed */ | |
1787 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); | |
c9839303 CW |
1788 | if (ret) |
1789 | goto unlock; | |
4a684a41 | 1790 | |
c9839303 CW |
1791 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1792 | if (ret) | |
1793 | goto unpin; | |
74898d7e | 1794 | |
06d98131 | 1795 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1796 | if (ret) |
c9839303 | 1797 | goto unpin; |
7d1c4804 | 1798 | |
b90b91d8 | 1799 | /* Finally, remap it using the new GTT offset */ |
c5ad54cf JL |
1800 | pfn = dev_priv->gtt.mappable_base + |
1801 | i915_gem_obj_ggtt_offset_view(obj, &view); | |
f343c5f6 | 1802 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1803 | |
c5ad54cf JL |
1804 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1805 | /* Overriding existing pages in partial view does not cause | |
1806 | * us any trouble as TLBs are still valid because the fault | |
1807 | * is due to userspace losing part of the mapping or never | |
1808 | * having accessed it before (at this partials' range). | |
1809 | */ | |
1810 | unsigned long base = vma->vm_start + | |
1811 | (view.params.partial.offset << PAGE_SHIFT); | |
1812 | unsigned int i; | |
b90b91d8 | 1813 | |
c5ad54cf JL |
1814 | for (i = 0; i < view.params.partial.size; i++) { |
1815 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1816 | if (ret) |
1817 | break; | |
1818 | } | |
1819 | ||
1820 | obj->fault_mappable = true; | |
c5ad54cf JL |
1821 | } else { |
1822 | if (!obj->fault_mappable) { | |
1823 | unsigned long size = min_t(unsigned long, | |
1824 | vma->vm_end - vma->vm_start, | |
1825 | obj->base.size); | |
1826 | int i; | |
1827 | ||
1828 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1829 | ret = vm_insert_pfn(vma, | |
1830 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1831 | pfn + i); | |
1832 | if (ret) | |
1833 | break; | |
1834 | } | |
1835 | ||
1836 | obj->fault_mappable = true; | |
1837 | } else | |
1838 | ret = vm_insert_pfn(vma, | |
1839 | (unsigned long)vmf->virtual_address, | |
1840 | pfn + page_offset); | |
1841 | } | |
c9839303 | 1842 | unpin: |
c5ad54cf | 1843 | i915_gem_object_ggtt_unpin_view(obj, &view); |
c715089f | 1844 | unlock: |
de151cf6 | 1845 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1846 | out: |
de151cf6 | 1847 | switch (ret) { |
d9bc7e9f | 1848 | case -EIO: |
2232f031 DV |
1849 | /* |
1850 | * We eat errors when the gpu is terminally wedged to avoid | |
1851 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1852 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1853 | * and so needs to be reported. | |
1854 | */ | |
1855 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1856 | ret = VM_FAULT_SIGBUS; |
1857 | break; | |
1858 | } | |
045e769a | 1859 | case -EAGAIN: |
571c608d DV |
1860 | /* |
1861 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1862 | * handler to reset everything when re-faulting in | |
1863 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1864 | */ |
c715089f CW |
1865 | case 0: |
1866 | case -ERESTARTSYS: | |
bed636ab | 1867 | case -EINTR: |
e79e0fe3 DR |
1868 | case -EBUSY: |
1869 | /* | |
1870 | * EBUSY is ok: this just means that another thread | |
1871 | * already did the job. | |
1872 | */ | |
f65c9168 PZ |
1873 | ret = VM_FAULT_NOPAGE; |
1874 | break; | |
de151cf6 | 1875 | case -ENOMEM: |
f65c9168 PZ |
1876 | ret = VM_FAULT_OOM; |
1877 | break; | |
a7c2e1aa | 1878 | case -ENOSPC: |
45d67817 | 1879 | case -EFAULT: |
f65c9168 PZ |
1880 | ret = VM_FAULT_SIGBUS; |
1881 | break; | |
de151cf6 | 1882 | default: |
a7c2e1aa | 1883 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1884 | ret = VM_FAULT_SIGBUS; |
1885 | break; | |
de151cf6 | 1886 | } |
f65c9168 PZ |
1887 | |
1888 | intel_runtime_pm_put(dev_priv); | |
1889 | return ret; | |
de151cf6 JB |
1890 | } |
1891 | ||
901782b2 CW |
1892 | /** |
1893 | * i915_gem_release_mmap - remove physical page mappings | |
1894 | * @obj: obj in question | |
1895 | * | |
af901ca1 | 1896 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1897 | * relinquish ownership of the pages back to the system. |
1898 | * | |
1899 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1900 | * object through the GTT and then lose the fence register due to | |
1901 | * resource pressure. Similarly if the object has been moved out of the | |
1902 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1903 | * mapping will then trigger a page fault on the next user access, allowing | |
1904 | * fixup by i915_gem_fault(). | |
1905 | */ | |
d05ca301 | 1906 | void |
05394f39 | 1907 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1908 | { |
6299f992 CW |
1909 | if (!obj->fault_mappable) |
1910 | return; | |
901782b2 | 1911 | |
6796cb16 DH |
1912 | drm_vma_node_unmap(&obj->base.vma_node, |
1913 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1914 | obj->fault_mappable = false; |
901782b2 CW |
1915 | } |
1916 | ||
eedd10f4 CW |
1917 | void |
1918 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1919 | { | |
1920 | struct drm_i915_gem_object *obj; | |
1921 | ||
1922 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1923 | i915_gem_release_mmap(obj); | |
1924 | } | |
1925 | ||
0fa87796 | 1926 | uint32_t |
e28f8711 | 1927 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1928 | { |
e28f8711 | 1929 | uint32_t gtt_size; |
92b88aeb CW |
1930 | |
1931 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1932 | tiling_mode == I915_TILING_NONE) |
1933 | return size; | |
92b88aeb CW |
1934 | |
1935 | /* Previous chips need a power-of-two fence region when tiling */ | |
1936 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1937 | gtt_size = 1024*1024; |
92b88aeb | 1938 | else |
e28f8711 | 1939 | gtt_size = 512*1024; |
92b88aeb | 1940 | |
e28f8711 CW |
1941 | while (gtt_size < size) |
1942 | gtt_size <<= 1; | |
92b88aeb | 1943 | |
e28f8711 | 1944 | return gtt_size; |
92b88aeb CW |
1945 | } |
1946 | ||
de151cf6 JB |
1947 | /** |
1948 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1949 | * @obj: object to check | |
1950 | * | |
1951 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1952 | * potential fence register mapping. |
de151cf6 | 1953 | */ |
d865110c ID |
1954 | uint32_t |
1955 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1956 | int tiling_mode, bool fenced) | |
de151cf6 | 1957 | { |
de151cf6 JB |
1958 | /* |
1959 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1960 | * if a fence register is needed for the object. | |
1961 | */ | |
d865110c | 1962 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1963 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1964 | return 4096; |
1965 | ||
a00b10c3 CW |
1966 | /* |
1967 | * Previous chips need to be aligned to the size of the smallest | |
1968 | * fence register that can contain the object. | |
1969 | */ | |
e28f8711 | 1970 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1971 | } |
1972 | ||
d8cb5086 CW |
1973 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1974 | { | |
1975 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1976 | int ret; | |
1977 | ||
0de23977 | 1978 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1979 | return 0; |
1980 | ||
da494d7c DV |
1981 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1982 | ||
d8cb5086 CW |
1983 | ret = drm_gem_create_mmap_offset(&obj->base); |
1984 | if (ret != -ENOSPC) | |
da494d7c | 1985 | goto out; |
d8cb5086 CW |
1986 | |
1987 | /* Badly fragmented mmap space? The only way we can recover | |
1988 | * space is by destroying unwanted objects. We can't randomly release | |
1989 | * mmap_offsets as userspace expects them to be persistent for the | |
1990 | * lifetime of the objects. The closest we can is to release the | |
1991 | * offsets on purgeable objects by truncating it and marking it purged, | |
1992 | * which prevents userspace from ever using that object again. | |
1993 | */ | |
21ab4e74 CW |
1994 | i915_gem_shrink(dev_priv, |
1995 | obj->base.size >> PAGE_SHIFT, | |
1996 | I915_SHRINK_BOUND | | |
1997 | I915_SHRINK_UNBOUND | | |
1998 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1999 | ret = drm_gem_create_mmap_offset(&obj->base); |
2000 | if (ret != -ENOSPC) | |
da494d7c | 2001 | goto out; |
d8cb5086 CW |
2002 | |
2003 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
2004 | ret = drm_gem_create_mmap_offset(&obj->base); |
2005 | out: | |
2006 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
2007 | ||
2008 | return ret; | |
d8cb5086 CW |
2009 | } |
2010 | ||
2011 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2012 | { | |
d8cb5086 CW |
2013 | drm_gem_free_mmap_offset(&obj->base); |
2014 | } | |
2015 | ||
da6b51d0 | 2016 | int |
ff72145b DA |
2017 | i915_gem_mmap_gtt(struct drm_file *file, |
2018 | struct drm_device *dev, | |
da6b51d0 | 2019 | uint32_t handle, |
ff72145b | 2020 | uint64_t *offset) |
de151cf6 | 2021 | { |
05394f39 | 2022 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2023 | int ret; |
2024 | ||
76c1dec1 | 2025 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 2026 | if (ret) |
76c1dec1 | 2027 | return ret; |
de151cf6 | 2028 | |
ff72145b | 2029 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 2030 | if (&obj->base == NULL) { |
1d7cfea1 CW |
2031 | ret = -ENOENT; |
2032 | goto unlock; | |
2033 | } | |
de151cf6 | 2034 | |
05394f39 | 2035 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2036 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 2037 | ret = -EFAULT; |
1d7cfea1 | 2038 | goto out; |
ab18282d CW |
2039 | } |
2040 | ||
d8cb5086 CW |
2041 | ret = i915_gem_object_create_mmap_offset(obj); |
2042 | if (ret) | |
2043 | goto out; | |
de151cf6 | 2044 | |
0de23977 | 2045 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 2046 | |
1d7cfea1 | 2047 | out: |
05394f39 | 2048 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 2049 | unlock: |
de151cf6 | 2050 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 2051 | return ret; |
de151cf6 JB |
2052 | } |
2053 | ||
ff72145b DA |
2054 | /** |
2055 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2056 | * @dev: DRM device | |
2057 | * @data: GTT mapping ioctl data | |
2058 | * @file: GEM object info | |
2059 | * | |
2060 | * Simply returns the fake offset to userspace so it can mmap it. | |
2061 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2062 | * up so we can get faults in the handler above. | |
2063 | * | |
2064 | * The fault handler will take care of binding the object into the GTT | |
2065 | * (since it may have been evicted to make room for something), allocating | |
2066 | * a fence register, and mapping the appropriate aperture address into | |
2067 | * userspace. | |
2068 | */ | |
2069 | int | |
2070 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2071 | struct drm_file *file) | |
2072 | { | |
2073 | struct drm_i915_gem_mmap_gtt *args = data; | |
2074 | ||
da6b51d0 | 2075 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2076 | } |
2077 | ||
225067ee DV |
2078 | /* Immediately discard the backing storage */ |
2079 | static void | |
2080 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2081 | { |
4d6294bf | 2082 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2083 | |
4d6294bf CW |
2084 | if (obj->base.filp == NULL) |
2085 | return; | |
e5281ccd | 2086 | |
225067ee DV |
2087 | /* Our goal here is to return as much of the memory as |
2088 | * is possible back to the system as we are called from OOM. | |
2089 | * To do this we must instruct the shmfs to drop all of its | |
2090 | * backing pages, *now*. | |
2091 | */ | |
5537252b | 2092 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2093 | obj->madv = __I915_MADV_PURGED; |
2094 | } | |
e5281ccd | 2095 | |
5537252b CW |
2096 | /* Try to discard unwanted pages */ |
2097 | static void | |
2098 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2099 | { |
5537252b CW |
2100 | struct address_space *mapping; |
2101 | ||
2102 | switch (obj->madv) { | |
2103 | case I915_MADV_DONTNEED: | |
2104 | i915_gem_object_truncate(obj); | |
2105 | case __I915_MADV_PURGED: | |
2106 | return; | |
2107 | } | |
2108 | ||
2109 | if (obj->base.filp == NULL) | |
2110 | return; | |
2111 | ||
2112 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2113 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2114 | } |
2115 | ||
5cdf5881 | 2116 | static void |
05394f39 | 2117 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2118 | { |
90797e6d ID |
2119 | struct sg_page_iter sg_iter; |
2120 | int ret; | |
1286ff73 | 2121 | |
05394f39 | 2122 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2123 | |
6c085a72 CW |
2124 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
2125 | if (ret) { | |
2126 | /* In the event of a disaster, abandon all caches and | |
2127 | * hope for the best. | |
2128 | */ | |
2129 | WARN_ON(ret != -EIO); | |
2c22569b | 2130 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2131 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2132 | } | |
2133 | ||
e2273302 ID |
2134 | i915_gem_gtt_finish_object(obj); |
2135 | ||
6dacfd2f | 2136 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2137 | i915_gem_object_save_bit_17_swizzle(obj); |
2138 | ||
05394f39 CW |
2139 | if (obj->madv == I915_MADV_DONTNEED) |
2140 | obj->dirty = 0; | |
3ef94daa | 2141 | |
90797e6d | 2142 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 2143 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 2144 | |
05394f39 | 2145 | if (obj->dirty) |
9da3da66 | 2146 | set_page_dirty(page); |
3ef94daa | 2147 | |
05394f39 | 2148 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2149 | mark_page_accessed(page); |
3ef94daa | 2150 | |
9da3da66 | 2151 | page_cache_release(page); |
3ef94daa | 2152 | } |
05394f39 | 2153 | obj->dirty = 0; |
673a394b | 2154 | |
9da3da66 CW |
2155 | sg_free_table(obj->pages); |
2156 | kfree(obj->pages); | |
37e680a1 | 2157 | } |
6c085a72 | 2158 | |
dd624afd | 2159 | int |
37e680a1 CW |
2160 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2161 | { | |
2162 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2163 | ||
2f745ad3 | 2164 | if (obj->pages == NULL) |
37e680a1 CW |
2165 | return 0; |
2166 | ||
a5570178 CW |
2167 | if (obj->pages_pin_count) |
2168 | return -EBUSY; | |
2169 | ||
9843877d | 2170 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2171 | |
a2165e31 CW |
2172 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2173 | * array, hence protect them from being reaped by removing them from gtt | |
2174 | * lists early. */ | |
35c20a60 | 2175 | list_del(&obj->global_list); |
a2165e31 | 2176 | |
37e680a1 | 2177 | ops->put_pages(obj); |
05394f39 | 2178 | obj->pages = NULL; |
37e680a1 | 2179 | |
5537252b | 2180 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2181 | |
2182 | return 0; | |
2183 | } | |
2184 | ||
37e680a1 | 2185 | static int |
6c085a72 | 2186 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2187 | { |
6c085a72 | 2188 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2189 | int page_count, i; |
2190 | struct address_space *mapping; | |
9da3da66 CW |
2191 | struct sg_table *st; |
2192 | struct scatterlist *sg; | |
90797e6d | 2193 | struct sg_page_iter sg_iter; |
e5281ccd | 2194 | struct page *page; |
90797e6d | 2195 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2196 | int ret; |
6c085a72 | 2197 | gfp_t gfp; |
e5281ccd | 2198 | |
6c085a72 CW |
2199 | /* Assert that the object is not currently in any GPU domain. As it |
2200 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2201 | * a GPU cache | |
2202 | */ | |
2203 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2204 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2205 | ||
9da3da66 CW |
2206 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2207 | if (st == NULL) | |
2208 | return -ENOMEM; | |
2209 | ||
05394f39 | 2210 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2211 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2212 | kfree(st); |
e5281ccd | 2213 | return -ENOMEM; |
9da3da66 | 2214 | } |
e5281ccd | 2215 | |
9da3da66 CW |
2216 | /* Get the list of pages out of our struct file. They'll be pinned |
2217 | * at this point until we release them. | |
2218 | * | |
2219 | * Fail silently without starting the shrinker | |
2220 | */ | |
496ad9aa | 2221 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2222 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2223 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2224 | sg = st->sgl; |
2225 | st->nents = 0; | |
2226 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2227 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2228 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2229 | i915_gem_shrink(dev_priv, |
2230 | page_count, | |
2231 | I915_SHRINK_BOUND | | |
2232 | I915_SHRINK_UNBOUND | | |
2233 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2234 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2235 | } | |
2236 | if (IS_ERR(page)) { | |
2237 | /* We've tried hard to allocate the memory by reaping | |
2238 | * our own buffer, now let the real VM do its job and | |
2239 | * go down in flames if truly OOM. | |
2240 | */ | |
6c085a72 | 2241 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2242 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2243 | if (IS_ERR(page)) { |
2244 | ret = PTR_ERR(page); | |
6c085a72 | 2245 | goto err_pages; |
e2273302 | 2246 | } |
6c085a72 | 2247 | } |
426729dc KRW |
2248 | #ifdef CONFIG_SWIOTLB |
2249 | if (swiotlb_nr_tbl()) { | |
2250 | st->nents++; | |
2251 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2252 | sg = sg_next(sg); | |
2253 | continue; | |
2254 | } | |
2255 | #endif | |
90797e6d ID |
2256 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2257 | if (i) | |
2258 | sg = sg_next(sg); | |
2259 | st->nents++; | |
2260 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2261 | } else { | |
2262 | sg->length += PAGE_SIZE; | |
2263 | } | |
2264 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2265 | |
2266 | /* Check that the i965g/gm workaround works. */ | |
2267 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2268 | } |
426729dc KRW |
2269 | #ifdef CONFIG_SWIOTLB |
2270 | if (!swiotlb_nr_tbl()) | |
2271 | #endif | |
2272 | sg_mark_end(sg); | |
74ce6b6c CW |
2273 | obj->pages = st; |
2274 | ||
e2273302 ID |
2275 | ret = i915_gem_gtt_prepare_object(obj); |
2276 | if (ret) | |
2277 | goto err_pages; | |
2278 | ||
6dacfd2f | 2279 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2280 | i915_gem_object_do_bit_17_swizzle(obj); |
2281 | ||
656bfa3a DV |
2282 | if (obj->tiling_mode != I915_TILING_NONE && |
2283 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2284 | i915_gem_object_pin_pages(obj); | |
2285 | ||
e5281ccd CW |
2286 | return 0; |
2287 | ||
2288 | err_pages: | |
90797e6d ID |
2289 | sg_mark_end(sg); |
2290 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2291 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2292 | sg_free_table(st); |
2293 | kfree(st); | |
0820baf3 CW |
2294 | |
2295 | /* shmemfs first checks if there is enough memory to allocate the page | |
2296 | * and reports ENOSPC should there be insufficient, along with the usual | |
2297 | * ENOMEM for a genuine allocation failure. | |
2298 | * | |
2299 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2300 | * space and so want to translate the error from shmemfs back to our | |
2301 | * usual understanding of ENOMEM. | |
2302 | */ | |
e2273302 ID |
2303 | if (ret == -ENOSPC) |
2304 | ret = -ENOMEM; | |
2305 | ||
2306 | return ret; | |
673a394b EA |
2307 | } |
2308 | ||
37e680a1 CW |
2309 | /* Ensure that the associated pages are gathered from the backing storage |
2310 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2311 | * multiple times before they are released by a single call to | |
2312 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2313 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2314 | * or as the object is itself released. | |
2315 | */ | |
2316 | int | |
2317 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2318 | { | |
2319 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2320 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2321 | int ret; | |
2322 | ||
2f745ad3 | 2323 | if (obj->pages) |
37e680a1 CW |
2324 | return 0; |
2325 | ||
43e28f09 | 2326 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2327 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2328 | return -EFAULT; |
43e28f09 CW |
2329 | } |
2330 | ||
a5570178 CW |
2331 | BUG_ON(obj->pages_pin_count); |
2332 | ||
37e680a1 CW |
2333 | ret = ops->get_pages(obj); |
2334 | if (ret) | |
2335 | return ret; | |
2336 | ||
35c20a60 | 2337 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2338 | |
2339 | obj->get_page.sg = obj->pages->sgl; | |
2340 | obj->get_page.last = 0; | |
2341 | ||
37e680a1 | 2342 | return 0; |
673a394b EA |
2343 | } |
2344 | ||
b4716185 | 2345 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2346 | struct drm_i915_gem_request *req) |
673a394b | 2347 | { |
b4716185 | 2348 | struct drm_i915_gem_object *obj = vma->obj; |
b2af0376 JH |
2349 | struct intel_engine_cs *ring; |
2350 | ||
2351 | ring = i915_gem_request_get_ring(req); | |
673a394b EA |
2352 | |
2353 | /* Add a reference if we're newly entering the active list. */ | |
b4716185 | 2354 | if (obj->active == 0) |
05394f39 | 2355 | drm_gem_object_reference(&obj->base); |
b4716185 | 2356 | obj->active |= intel_ring_flag(ring); |
e35a41de | 2357 | |
b4716185 | 2358 | list_move_tail(&obj->ring_list[ring->id], &ring->active_list); |
b2af0376 | 2359 | i915_gem_request_assign(&obj->last_read_req[ring->id], req); |
caea7476 | 2360 | |
b4716185 | 2361 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
caea7476 CW |
2362 | } |
2363 | ||
b4716185 CW |
2364 | static void |
2365 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) | |
e2d05a8b | 2366 | { |
b4716185 CW |
2367 | RQ_BUG_ON(obj->last_write_req == NULL); |
2368 | RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring))); | |
2369 | ||
2370 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
de152b62 | 2371 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2372 | } |
2373 | ||
caea7476 | 2374 | static void |
b4716185 | 2375 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
ce44b0ea | 2376 | { |
feb822cf | 2377 | struct i915_vma *vma; |
ce44b0ea | 2378 | |
b4716185 CW |
2379 | RQ_BUG_ON(obj->last_read_req[ring] == NULL); |
2380 | RQ_BUG_ON(!(obj->active & (1 << ring))); | |
2381 | ||
2382 | list_del_init(&obj->ring_list[ring]); | |
2383 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); | |
2384 | ||
2385 | if (obj->last_write_req && obj->last_write_req->ring->id == ring) | |
2386 | i915_gem_object_retire__write(obj); | |
2387 | ||
2388 | obj->active &= ~(1 << ring); | |
2389 | if (obj->active) | |
2390 | return; | |
caea7476 | 2391 | |
6c246959 CW |
2392 | /* Bump our place on the bound list to keep it roughly in LRU order |
2393 | * so that we don't steal from recently used but inactive objects | |
2394 | * (unless we are forced to ofc!) | |
2395 | */ | |
2396 | list_move_tail(&obj->global_list, | |
2397 | &to_i915(obj->base.dev)->mm.bound_list); | |
2398 | ||
fe14d5f4 TU |
2399 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
2400 | if (!list_empty(&vma->mm_list)) | |
2401 | list_move_tail(&vma->mm_list, &vma->vm->inactive_list); | |
feb822cf | 2402 | } |
caea7476 | 2403 | |
97b2a6a1 | 2404 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 | 2405 | drm_gem_object_unreference(&obj->base); |
c8725f3d CW |
2406 | } |
2407 | ||
9d773091 | 2408 | static int |
fca26bb4 | 2409 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2410 | { |
9d773091 | 2411 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2412 | struct intel_engine_cs *ring; |
9d773091 | 2413 | int ret, i, j; |
53d227f2 | 2414 | |
107f27a5 | 2415 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2416 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2417 | ret = intel_ring_idle(ring); |
2418 | if (ret) | |
2419 | return ret; | |
9d773091 | 2420 | } |
9d773091 | 2421 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2422 | |
2423 | /* Finally reset hw state */ | |
9d773091 | 2424 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2425 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2426 | |
ebc348b2 BW |
2427 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2428 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2429 | } |
53d227f2 | 2430 | |
9d773091 | 2431 | return 0; |
53d227f2 DV |
2432 | } |
2433 | ||
fca26bb4 MK |
2434 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2435 | { | |
2436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2437 | int ret; | |
2438 | ||
2439 | if (seqno == 0) | |
2440 | return -EINVAL; | |
2441 | ||
2442 | /* HWS page needs to be set less than what we | |
2443 | * will inject to ring | |
2444 | */ | |
2445 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2446 | if (ret) | |
2447 | return ret; | |
2448 | ||
2449 | /* Carefully set the last_seqno value so that wrap | |
2450 | * detection still works | |
2451 | */ | |
2452 | dev_priv->next_seqno = seqno; | |
2453 | dev_priv->last_seqno = seqno - 1; | |
2454 | if (dev_priv->last_seqno == 0) | |
2455 | dev_priv->last_seqno--; | |
2456 | ||
2457 | return 0; | |
2458 | } | |
2459 | ||
9d773091 CW |
2460 | int |
2461 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2462 | { |
9d773091 CW |
2463 | struct drm_i915_private *dev_priv = dev->dev_private; |
2464 | ||
2465 | /* reserve 0 for non-seqno */ | |
2466 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2467 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2468 | if (ret) |
2469 | return ret; | |
53d227f2 | 2470 | |
9d773091 CW |
2471 | dev_priv->next_seqno = 1; |
2472 | } | |
53d227f2 | 2473 | |
f72b3435 | 2474 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2475 | return 0; |
53d227f2 DV |
2476 | } |
2477 | ||
bf7dc5b7 JH |
2478 | /* |
2479 | * NB: This function is not allowed to fail. Doing so would mean the the | |
2480 | * request is not being tracked for completion but the work itself is | |
2481 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
2482 | */ | |
75289874 | 2483 | void __i915_add_request(struct drm_i915_gem_request *request, |
5b4a60c2 JH |
2484 | struct drm_i915_gem_object *obj, |
2485 | bool flush_caches) | |
673a394b | 2486 | { |
75289874 JH |
2487 | struct intel_engine_cs *ring; |
2488 | struct drm_i915_private *dev_priv; | |
48e29f55 | 2489 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2490 | u32 request_start; |
3cce469c CW |
2491 | int ret; |
2492 | ||
48e29f55 | 2493 | if (WARN_ON(request == NULL)) |
bf7dc5b7 | 2494 | return; |
48e29f55 | 2495 | |
75289874 JH |
2496 | ring = request->ring; |
2497 | dev_priv = ring->dev->dev_private; | |
2498 | ringbuf = request->ringbuf; | |
2499 | ||
29b1b415 JH |
2500 | /* |
2501 | * To ensure that this call will not fail, space for its emissions | |
2502 | * should already have been reserved in the ring buffer. Let the ring | |
2503 | * know that it is time to use that space up. | |
2504 | */ | |
2505 | intel_ring_reserved_space_use(ringbuf); | |
2506 | ||
48e29f55 | 2507 | request_start = intel_ring_get_tail(ringbuf); |
cc889e0f DV |
2508 | /* |
2509 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2510 | * after having emitted the batchbuffer command. Hence we need to fix | |
2511 | * things up similar to emitting the lazy request. The difference here | |
2512 | * is that the flush _must_ happen before the next request, no matter | |
2513 | * what. | |
2514 | */ | |
5b4a60c2 JH |
2515 | if (flush_caches) { |
2516 | if (i915.enable_execlists) | |
4866d729 | 2517 | ret = logical_ring_flush_all_caches(request); |
5b4a60c2 | 2518 | else |
4866d729 | 2519 | ret = intel_ring_flush_all_caches(request); |
5b4a60c2 JH |
2520 | /* Not allowed to fail! */ |
2521 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); | |
2522 | } | |
cc889e0f | 2523 | |
a71d8d94 CW |
2524 | /* Record the position of the start of the request so that |
2525 | * should we detect the updated seqno part-way through the | |
2526 | * GPU processing the request, we never over-estimate the | |
2527 | * position of the head. | |
2528 | */ | |
6d3d8274 | 2529 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2530 | |
bf7dc5b7 | 2531 | if (i915.enable_execlists) |
c4e76638 | 2532 | ret = ring->emit_request(request); |
bf7dc5b7 | 2533 | else { |
ee044a88 | 2534 | ret = ring->add_request(request); |
53292cdb MT |
2535 | |
2536 | request->tail = intel_ring_get_tail(ringbuf); | |
48e29f55 | 2537 | } |
bf7dc5b7 JH |
2538 | /* Not allowed to fail! */ |
2539 | WARN(ret, "emit|add_request failed: %d!\n", ret); | |
673a394b | 2540 | |
7d736f4f | 2541 | request->head = request_start; |
7d736f4f MK |
2542 | |
2543 | /* Whilst this request exists, batch_obj will be on the | |
2544 | * active_list, and so will hold the active reference. Only when this | |
2545 | * request is retired will the the batch_obj be moved onto the | |
2546 | * inactive_list and lose its active reference. Hence we do not need | |
2547 | * to explicitly hold another reference here. | |
2548 | */ | |
9a7e0c2a | 2549 | request->batch_obj = obj; |
0e50e96b | 2550 | |
673a394b | 2551 | request->emitted_jiffies = jiffies; |
94f7bbe1 | 2552 | ring->last_submitted_seqno = request->seqno; |
852835f3 | 2553 | list_add_tail(&request->list, &ring->request_list); |
673a394b | 2554 | |
74328ee5 | 2555 | trace_i915_gem_request_add(request); |
db53a302 | 2556 | |
87255483 | 2557 | i915_queue_hangcheck(ring->dev); |
10cd45b6 | 2558 | |
87255483 DV |
2559 | queue_delayed_work(dev_priv->wq, |
2560 | &dev_priv->mm.retire_work, | |
2561 | round_jiffies_up_relative(HZ)); | |
2562 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2563 | |
29b1b415 JH |
2564 | /* Sanity check that the reserved size was large enough. */ |
2565 | intel_ring_reserved_space_end(ringbuf); | |
673a394b EA |
2566 | } |
2567 | ||
939fd762 | 2568 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2569 | const struct intel_context *ctx) |
be62acb4 | 2570 | { |
44e2c070 | 2571 | unsigned long elapsed; |
be62acb4 | 2572 | |
44e2c070 MK |
2573 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2574 | ||
2575 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2576 | return true; |
2577 | ||
676fa572 CW |
2578 | if (ctx->hang_stats.ban_period_seconds && |
2579 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
ccc7bed0 | 2580 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2581 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2582 | return true; |
88b4aa87 MK |
2583 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2584 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2585 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2586 | return true; |
3fac8978 | 2587 | } |
be62acb4 MK |
2588 | } |
2589 | ||
2590 | return false; | |
2591 | } | |
2592 | ||
939fd762 | 2593 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2594 | struct intel_context *ctx, |
b6b0fac0 | 2595 | const bool guilty) |
aa60c664 | 2596 | { |
44e2c070 MK |
2597 | struct i915_ctx_hang_stats *hs; |
2598 | ||
2599 | if (WARN_ON(!ctx)) | |
2600 | return; | |
aa60c664 | 2601 | |
44e2c070 MK |
2602 | hs = &ctx->hang_stats; |
2603 | ||
2604 | if (guilty) { | |
939fd762 | 2605 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2606 | hs->batch_active++; |
2607 | hs->guilty_ts = get_seconds(); | |
2608 | } else { | |
2609 | hs->batch_pending++; | |
aa60c664 MK |
2610 | } |
2611 | } | |
2612 | ||
abfe262a JH |
2613 | void i915_gem_request_free(struct kref *req_ref) |
2614 | { | |
2615 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2616 | typeof(*req), ref); | |
2617 | struct intel_context *ctx = req->ctx; | |
2618 | ||
fcfa423c JH |
2619 | if (req->file_priv) |
2620 | i915_gem_request_remove_from_client(req); | |
2621 | ||
0794aed3 TD |
2622 | if (ctx) { |
2623 | if (i915.enable_execlists) { | |
8ba319da MK |
2624 | if (ctx != req->ring->default_context) |
2625 | intel_lr_context_unpin(req); | |
0794aed3 | 2626 | } |
abfe262a | 2627 | |
dcb4c12a OM |
2628 | i915_gem_context_unreference(ctx); |
2629 | } | |
abfe262a | 2630 | |
efab6d8d | 2631 | kmem_cache_free(req->i915->requests, req); |
0e50e96b MK |
2632 | } |
2633 | ||
6689cb2b | 2634 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
217e46b5 JH |
2635 | struct intel_context *ctx, |
2636 | struct drm_i915_gem_request **req_out) | |
6689cb2b | 2637 | { |
efab6d8d | 2638 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
eed29a5b | 2639 | struct drm_i915_gem_request *req; |
6689cb2b | 2640 | int ret; |
6689cb2b | 2641 | |
217e46b5 JH |
2642 | if (!req_out) |
2643 | return -EINVAL; | |
2644 | ||
bccca494 | 2645 | *req_out = NULL; |
6689cb2b | 2646 | |
eed29a5b DV |
2647 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
2648 | if (req == NULL) | |
6689cb2b JH |
2649 | return -ENOMEM; |
2650 | ||
eed29a5b | 2651 | ret = i915_gem_get_seqno(ring->dev, &req->seqno); |
9a0c1e27 CW |
2652 | if (ret) |
2653 | goto err; | |
6689cb2b | 2654 | |
40e895ce JH |
2655 | kref_init(&req->ref); |
2656 | req->i915 = dev_priv; | |
eed29a5b | 2657 | req->ring = ring; |
40e895ce JH |
2658 | req->ctx = ctx; |
2659 | i915_gem_context_reference(req->ctx); | |
6689cb2b JH |
2660 | |
2661 | if (i915.enable_execlists) | |
40e895ce | 2662 | ret = intel_logical_ring_alloc_request_extras(req); |
6689cb2b | 2663 | else |
eed29a5b | 2664 | ret = intel_ring_alloc_request_extras(req); |
40e895ce JH |
2665 | if (ret) { |
2666 | i915_gem_context_unreference(req->ctx); | |
9a0c1e27 | 2667 | goto err; |
40e895ce | 2668 | } |
6689cb2b | 2669 | |
29b1b415 JH |
2670 | /* |
2671 | * Reserve space in the ring buffer for all the commands required to | |
2672 | * eventually emit this request. This is to guarantee that the | |
2673 | * i915_add_request() call can't fail. Note that the reserve may need | |
2674 | * to be redone if the request is not actually submitted straight | |
2675 | * away, e.g. because a GPU scheduler has deferred it. | |
29b1b415 | 2676 | */ |
ccd98fe4 JH |
2677 | if (i915.enable_execlists) |
2678 | ret = intel_logical_ring_reserve_space(req); | |
2679 | else | |
2680 | ret = intel_ring_reserve_space(req); | |
2681 | if (ret) { | |
2682 | /* | |
2683 | * At this point, the request is fully allocated even if not | |
2684 | * fully prepared. Thus it can be cleaned up using the proper | |
2685 | * free code. | |
2686 | */ | |
2687 | i915_gem_request_cancel(req); | |
2688 | return ret; | |
2689 | } | |
29b1b415 | 2690 | |
bccca494 | 2691 | *req_out = req; |
6689cb2b | 2692 | return 0; |
9a0c1e27 CW |
2693 | |
2694 | err: | |
2695 | kmem_cache_free(dev_priv->requests, req); | |
2696 | return ret; | |
0e50e96b MK |
2697 | } |
2698 | ||
29b1b415 JH |
2699 | void i915_gem_request_cancel(struct drm_i915_gem_request *req) |
2700 | { | |
2701 | intel_ring_reserved_space_cancel(req->ringbuf); | |
2702 | ||
2703 | i915_gem_request_unreference(req); | |
2704 | } | |
2705 | ||
8d9fc7fd | 2706 | struct drm_i915_gem_request * |
a4872ba6 | 2707 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2708 | { |
4db080f9 CW |
2709 | struct drm_i915_gem_request *request; |
2710 | ||
2711 | list_for_each_entry(request, &ring->request_list, list) { | |
1b5a433a | 2712 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2713 | continue; |
aa60c664 | 2714 | |
b6b0fac0 | 2715 | return request; |
4db080f9 | 2716 | } |
b6b0fac0 MK |
2717 | |
2718 | return NULL; | |
2719 | } | |
2720 | ||
2721 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2722 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2723 | { |
2724 | struct drm_i915_gem_request *request; | |
2725 | bool ring_hung; | |
2726 | ||
8d9fc7fd | 2727 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2728 | |
2729 | if (request == NULL) | |
2730 | return; | |
2731 | ||
2732 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2733 | ||
939fd762 | 2734 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2735 | |
2736 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2737 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2738 | } |
aa60c664 | 2739 | |
4db080f9 | 2740 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2741 | struct intel_engine_cs *ring) |
4db080f9 | 2742 | { |
608c1a52 CW |
2743 | struct intel_ringbuffer *buffer; |
2744 | ||
dfaae392 | 2745 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2746 | struct drm_i915_gem_object *obj; |
9375e446 | 2747 | |
05394f39 CW |
2748 | obj = list_first_entry(&ring->active_list, |
2749 | struct drm_i915_gem_object, | |
b4716185 | 2750 | ring_list[ring->id]); |
9375e446 | 2751 | |
b4716185 | 2752 | i915_gem_object_retire__read(obj, ring->id); |
673a394b | 2753 | } |
1d62beea | 2754 | |
dcb4c12a OM |
2755 | /* |
2756 | * Clear the execlists queue up before freeing the requests, as those | |
2757 | * are the ones that keep the context and ringbuffer backing objects | |
2758 | * pinned in place. | |
2759 | */ | |
dcb4c12a | 2760 | |
7de1691a TE |
2761 | if (i915.enable_execlists) { |
2762 | spin_lock_irq(&ring->execlist_lock); | |
2763 | while (!list_empty(&ring->execlist_queue)) { | |
2764 | struct drm_i915_gem_request *submit_req; | |
1197b4f2 | 2765 | |
7de1691a TE |
2766 | submit_req = list_first_entry(&ring->execlist_queue, |
2767 | struct drm_i915_gem_request, | |
2768 | execlist_link); | |
2769 | list_del(&submit_req->execlist_link); | |
7de1691a TE |
2770 | i915_gem_request_unreference(submit_req); |
2771 | } | |
2772 | spin_unlock_irq(&ring->execlist_lock); | |
dcb4c12a OM |
2773 | } |
2774 | ||
1d62beea BW |
2775 | /* |
2776 | * We must free the requests after all the corresponding objects have | |
2777 | * been moved off active lists. Which is the same order as the normal | |
2778 | * retire_requests function does. This is important if object hold | |
2779 | * implicit references on things like e.g. ppgtt address spaces through | |
2780 | * the request. | |
2781 | */ | |
2782 | while (!list_empty(&ring->request_list)) { | |
2783 | struct drm_i915_gem_request *request; | |
2784 | ||
2785 | request = list_first_entry(&ring->request_list, | |
2786 | struct drm_i915_gem_request, | |
2787 | list); | |
2788 | ||
b4716185 | 2789 | i915_gem_request_retire(request); |
1d62beea | 2790 | } |
608c1a52 CW |
2791 | |
2792 | /* Having flushed all requests from all queues, we know that all | |
2793 | * ringbuffers must now be empty. However, since we do not reclaim | |
2794 | * all space when retiring the request (to prevent HEADs colliding | |
2795 | * with rapid ringbuffer wraparound) the amount of available space | |
2796 | * upon reset is less than when we start. Do one more pass over | |
2797 | * all the ringbuffers to reset last_retired_head. | |
2798 | */ | |
2799 | list_for_each_entry(buffer, &ring->buffers, link) { | |
2800 | buffer->last_retired_head = buffer->tail; | |
2801 | intel_ring_update_space(buffer); | |
2802 | } | |
673a394b EA |
2803 | } |
2804 | ||
069efc1d | 2805 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2806 | { |
77f01230 | 2807 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2808 | struct intel_engine_cs *ring; |
1ec14ad3 | 2809 | int i; |
673a394b | 2810 | |
4db080f9 CW |
2811 | /* |
2812 | * Before we free the objects from the requests, we need to inspect | |
2813 | * them for finding the guilty party. As the requests only borrow | |
2814 | * their reference to the objects, the inspection must be done first. | |
2815 | */ | |
2816 | for_each_ring(ring, dev_priv, i) | |
2817 | i915_gem_reset_ring_status(dev_priv, ring); | |
2818 | ||
b4519513 | 2819 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2820 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2821 | |
acce9ffa BW |
2822 | i915_gem_context_reset(dev); |
2823 | ||
19b2dbde | 2824 | i915_gem_restore_fences(dev); |
b4716185 CW |
2825 | |
2826 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2827 | } |
2828 | ||
2829 | /** | |
2830 | * This function clears the request list as sequence numbers are passed. | |
2831 | */ | |
1cf0ba14 | 2832 | void |
a4872ba6 | 2833 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2834 | { |
db53a302 | 2835 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2836 | |
832a3aad CW |
2837 | /* Retire requests first as we use it above for the early return. |
2838 | * If we retire requests last, we may use a later seqno and so clear | |
2839 | * the requests lists without clearing the active list, leading to | |
2840 | * confusion. | |
e9103038 | 2841 | */ |
852835f3 | 2842 | while (!list_empty(&ring->request_list)) { |
673a394b | 2843 | struct drm_i915_gem_request *request; |
673a394b | 2844 | |
852835f3 | 2845 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2846 | struct drm_i915_gem_request, |
2847 | list); | |
673a394b | 2848 | |
1b5a433a | 2849 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
2850 | break; |
2851 | ||
b4716185 | 2852 | i915_gem_request_retire(request); |
b84d5f0c | 2853 | } |
673a394b | 2854 | |
832a3aad CW |
2855 | /* Move any buffers on the active list that are no longer referenced |
2856 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2857 | * before we free the context associated with the requests. | |
2858 | */ | |
2859 | while (!list_empty(&ring->active_list)) { | |
2860 | struct drm_i915_gem_object *obj; | |
2861 | ||
2862 | obj = list_first_entry(&ring->active_list, | |
2863 | struct drm_i915_gem_object, | |
b4716185 | 2864 | ring_list[ring->id]); |
832a3aad | 2865 | |
b4716185 | 2866 | if (!list_empty(&obj->last_read_req[ring->id]->list)) |
832a3aad CW |
2867 | break; |
2868 | ||
b4716185 | 2869 | i915_gem_object_retire__read(obj, ring->id); |
832a3aad CW |
2870 | } |
2871 | ||
581c26e8 JH |
2872 | if (unlikely(ring->trace_irq_req && |
2873 | i915_gem_request_completed(ring->trace_irq_req, true))) { | |
1ec14ad3 | 2874 | ring->irq_put(ring); |
581c26e8 | 2875 | i915_gem_request_assign(&ring->trace_irq_req, NULL); |
9d34e5db | 2876 | } |
23bc5982 | 2877 | |
db53a302 | 2878 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2879 | } |
2880 | ||
b29c19b6 | 2881 | bool |
b09a1fec CW |
2882 | i915_gem_retire_requests(struct drm_device *dev) |
2883 | { | |
3e31c6c0 | 2884 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2885 | struct intel_engine_cs *ring; |
b29c19b6 | 2886 | bool idle = true; |
1ec14ad3 | 2887 | int i; |
b09a1fec | 2888 | |
b29c19b6 | 2889 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2890 | i915_gem_retire_requests_ring(ring); |
b29c19b6 | 2891 | idle &= list_empty(&ring->request_list); |
c86ee3a9 TD |
2892 | if (i915.enable_execlists) { |
2893 | unsigned long flags; | |
2894 | ||
2895 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2896 | idle &= list_empty(&ring->execlist_queue); | |
2897 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
2898 | ||
2899 | intel_execlists_retire_requests(ring); | |
2900 | } | |
b29c19b6 CW |
2901 | } |
2902 | ||
2903 | if (idle) | |
2904 | mod_delayed_work(dev_priv->wq, | |
2905 | &dev_priv->mm.idle_work, | |
2906 | msecs_to_jiffies(100)); | |
2907 | ||
2908 | return idle; | |
b09a1fec CW |
2909 | } |
2910 | ||
75ef9da2 | 2911 | static void |
673a394b EA |
2912 | i915_gem_retire_work_handler(struct work_struct *work) |
2913 | { | |
b29c19b6 CW |
2914 | struct drm_i915_private *dev_priv = |
2915 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2916 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2917 | bool idle; |
673a394b | 2918 | |
891b48cf | 2919 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2920 | idle = false; |
2921 | if (mutex_trylock(&dev->struct_mutex)) { | |
2922 | idle = i915_gem_retire_requests(dev); | |
2923 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2924 | } |
b29c19b6 | 2925 | if (!idle) |
bcb45086 CW |
2926 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2927 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2928 | } |
0a58705b | 2929 | |
b29c19b6 CW |
2930 | static void |
2931 | i915_gem_idle_work_handler(struct work_struct *work) | |
2932 | { | |
2933 | struct drm_i915_private *dev_priv = | |
2934 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
35c94185 | 2935 | struct drm_device *dev = dev_priv->dev; |
423795cb CW |
2936 | struct intel_engine_cs *ring; |
2937 | int i; | |
b29c19b6 | 2938 | |
423795cb CW |
2939 | for_each_ring(ring, dev_priv, i) |
2940 | if (!list_empty(&ring->request_list)) | |
2941 | return; | |
35c94185 CW |
2942 | |
2943 | intel_mark_idle(dev); | |
2944 | ||
2945 | if (mutex_trylock(&dev->struct_mutex)) { | |
2946 | struct intel_engine_cs *ring; | |
2947 | int i; | |
2948 | ||
2949 | for_each_ring(ring, dev_priv, i) | |
2950 | i915_gem_batch_pool_fini(&ring->batch_pool); | |
b29c19b6 | 2951 | |
35c94185 CW |
2952 | mutex_unlock(&dev->struct_mutex); |
2953 | } | |
673a394b EA |
2954 | } |
2955 | ||
30dfebf3 DV |
2956 | /** |
2957 | * Ensures that an object will eventually get non-busy by flushing any required | |
2958 | * write domains, emitting any outstanding lazy request and retiring and | |
2959 | * completed requests. | |
2960 | */ | |
2961 | static int | |
2962 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2963 | { | |
a5ac0f90 | 2964 | int i; |
b4716185 CW |
2965 | |
2966 | if (!obj->active) | |
2967 | return 0; | |
30dfebf3 | 2968 | |
b4716185 CW |
2969 | for (i = 0; i < I915_NUM_RINGS; i++) { |
2970 | struct drm_i915_gem_request *req; | |
41c52415 | 2971 | |
b4716185 CW |
2972 | req = obj->last_read_req[i]; |
2973 | if (req == NULL) | |
2974 | continue; | |
2975 | ||
2976 | if (list_empty(&req->list)) | |
2977 | goto retire; | |
2978 | ||
b4716185 CW |
2979 | if (i915_gem_request_completed(req, true)) { |
2980 | __i915_gem_request_retire__upto(req); | |
2981 | retire: | |
2982 | i915_gem_object_retire__read(obj, i); | |
2983 | } | |
30dfebf3 DV |
2984 | } |
2985 | ||
2986 | return 0; | |
2987 | } | |
2988 | ||
23ba4fd0 BW |
2989 | /** |
2990 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2991 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2992 | * | |
2993 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2994 | * the timeout parameter. | |
2995 | * -ETIME: object is still busy after timeout | |
2996 | * -ERESTARTSYS: signal interrupted the wait | |
2997 | * -ENONENT: object doesn't exist | |
2998 | * Also possible, but rare: | |
2999 | * -EAGAIN: GPU wedged | |
3000 | * -ENOMEM: damn | |
3001 | * -ENODEV: Internal IRQ fail | |
3002 | * -E?: The add request failed | |
3003 | * | |
3004 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3005 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3006 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3007 | * without holding struct_mutex the object may become re-busied before this | |
3008 | * function completes. A similar but shorter * race condition exists in the busy | |
3009 | * ioctl | |
3010 | */ | |
3011 | int | |
3012 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3013 | { | |
3e31c6c0 | 3014 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
3015 | struct drm_i915_gem_wait *args = data; |
3016 | struct drm_i915_gem_object *obj; | |
b4716185 | 3017 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; |
f69061be | 3018 | unsigned reset_counter; |
b4716185 CW |
3019 | int i, n = 0; |
3020 | int ret; | |
23ba4fd0 | 3021 | |
11b5d511 DV |
3022 | if (args->flags != 0) |
3023 | return -EINVAL; | |
3024 | ||
23ba4fd0 BW |
3025 | ret = i915_mutex_lock_interruptible(dev); |
3026 | if (ret) | |
3027 | return ret; | |
3028 | ||
3029 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
3030 | if (&obj->base == NULL) { | |
3031 | mutex_unlock(&dev->struct_mutex); | |
3032 | return -ENOENT; | |
3033 | } | |
3034 | ||
30dfebf3 DV |
3035 | /* Need to make sure the object gets inactive eventually. */ |
3036 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
3037 | if (ret) |
3038 | goto out; | |
3039 | ||
b4716185 | 3040 | if (!obj->active) |
97b2a6a1 | 3041 | goto out; |
23ba4fd0 | 3042 | |
23ba4fd0 | 3043 | /* Do this after OLR check to make sure we make forward progress polling |
762e4583 | 3044 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
23ba4fd0 | 3045 | */ |
762e4583 | 3046 | if (args->timeout_ns == 0) { |
23ba4fd0 BW |
3047 | ret = -ETIME; |
3048 | goto out; | |
3049 | } | |
3050 | ||
3051 | drm_gem_object_unreference(&obj->base); | |
f69061be | 3052 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
b4716185 CW |
3053 | |
3054 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3055 | if (obj->last_read_req[i] == NULL) | |
3056 | continue; | |
3057 | ||
3058 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); | |
3059 | } | |
3060 | ||
23ba4fd0 BW |
3061 | mutex_unlock(&dev->struct_mutex); |
3062 | ||
b4716185 CW |
3063 | for (i = 0; i < n; i++) { |
3064 | if (ret == 0) | |
3065 | ret = __i915_wait_request(req[i], reset_counter, true, | |
3066 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, | |
3067 | file->driver_priv); | |
3068 | i915_gem_request_unreference__unlocked(req[i]); | |
3069 | } | |
ff865885 | 3070 | return ret; |
23ba4fd0 BW |
3071 | |
3072 | out: | |
3073 | drm_gem_object_unreference(&obj->base); | |
3074 | mutex_unlock(&dev->struct_mutex); | |
3075 | return ret; | |
3076 | } | |
3077 | ||
b4716185 CW |
3078 | static int |
3079 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3080 | struct intel_engine_cs *to, | |
91af127f JH |
3081 | struct drm_i915_gem_request *from_req, |
3082 | struct drm_i915_gem_request **to_req) | |
b4716185 CW |
3083 | { |
3084 | struct intel_engine_cs *from; | |
3085 | int ret; | |
3086 | ||
91af127f | 3087 | from = i915_gem_request_get_ring(from_req); |
b4716185 CW |
3088 | if (to == from) |
3089 | return 0; | |
3090 | ||
91af127f | 3091 | if (i915_gem_request_completed(from_req, true)) |
b4716185 CW |
3092 | return 0; |
3093 | ||
b4716185 | 3094 | if (!i915_semaphore_is_enabled(obj->base.dev)) { |
a6f766f3 | 3095 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
91af127f | 3096 | ret = __i915_wait_request(from_req, |
a6f766f3 CW |
3097 | atomic_read(&i915->gpu_error.reset_counter), |
3098 | i915->mm.interruptible, | |
3099 | NULL, | |
3100 | &i915->rps.semaphores); | |
b4716185 CW |
3101 | if (ret) |
3102 | return ret; | |
3103 | ||
91af127f | 3104 | i915_gem_object_retire_request(obj, from_req); |
b4716185 CW |
3105 | } else { |
3106 | int idx = intel_ring_sync_index(from, to); | |
91af127f JH |
3107 | u32 seqno = i915_gem_request_get_seqno(from_req); |
3108 | ||
3109 | WARN_ON(!to_req); | |
b4716185 CW |
3110 | |
3111 | if (seqno <= from->semaphore.sync_seqno[idx]) | |
3112 | return 0; | |
3113 | ||
91af127f JH |
3114 | if (*to_req == NULL) { |
3115 | ret = i915_gem_request_alloc(to, to->default_context, to_req); | |
3116 | if (ret) | |
3117 | return ret; | |
3118 | } | |
3119 | ||
599d924c JH |
3120 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
3121 | ret = to->semaphore.sync_to(*to_req, from, seqno); | |
b4716185 CW |
3122 | if (ret) |
3123 | return ret; | |
3124 | ||
3125 | /* We use last_read_req because sync_to() | |
3126 | * might have just caused seqno wrap under | |
3127 | * the radar. | |
3128 | */ | |
3129 | from->semaphore.sync_seqno[idx] = | |
3130 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); | |
3131 | } | |
3132 | ||
3133 | return 0; | |
3134 | } | |
3135 | ||
5816d648 BW |
3136 | /** |
3137 | * i915_gem_object_sync - sync an object to a ring. | |
3138 | * | |
3139 | * @obj: object which may be in use on another ring. | |
3140 | * @to: ring we wish to use the object on. May be NULL. | |
91af127f JH |
3141 | * @to_req: request we wish to use the object for. See below. |
3142 | * This will be allocated and returned if a request is | |
3143 | * required but not passed in. | |
5816d648 BW |
3144 | * |
3145 | * This code is meant to abstract object synchronization with the GPU. | |
3146 | * Calling with NULL implies synchronizing the object with the CPU | |
b4716185 | 3147 | * rather than a particular GPU ring. Conceptually we serialise writes |
91af127f | 3148 | * between engines inside the GPU. We only allow one engine to write |
b4716185 CW |
3149 | * into a buffer at any time, but multiple readers. To ensure each has |
3150 | * a coherent view of memory, we must: | |
3151 | * | |
3152 | * - If there is an outstanding write request to the object, the new | |
3153 | * request must wait for it to complete (either CPU or in hw, requests | |
3154 | * on the same ring will be naturally ordered). | |
3155 | * | |
3156 | * - If we are a write request (pending_write_domain is set), the new | |
3157 | * request must wait for outstanding read requests to complete. | |
5816d648 | 3158 | * |
91af127f JH |
3159 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
3160 | * rings to_req must be non-NULL. However, a request does not have to be | |
3161 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a | |
3162 | * request will be allocated automatically and returned through *to_req. Note | |
3163 | * that it is not guaranteed that commands will be emitted (because the system | |
3164 | * might already be idle). Hence there is no need to create a request that | |
3165 | * might never have any work submitted. Note further that if a request is | |
3166 | * returned in *to_req, it is the responsibility of the caller to submit | |
3167 | * that request (after potentially adding more work to it). | |
3168 | * | |
5816d648 BW |
3169 | * Returns 0 if successful, else propagates up the lower layer error. |
3170 | */ | |
2911a35b BW |
3171 | int |
3172 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
91af127f JH |
3173 | struct intel_engine_cs *to, |
3174 | struct drm_i915_gem_request **to_req) | |
2911a35b | 3175 | { |
b4716185 CW |
3176 | const bool readonly = obj->base.pending_write_domain == 0; |
3177 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; | |
3178 | int ret, i, n; | |
41c52415 | 3179 | |
b4716185 | 3180 | if (!obj->active) |
2911a35b BW |
3181 | return 0; |
3182 | ||
b4716185 CW |
3183 | if (to == NULL) |
3184 | return i915_gem_object_wait_rendering(obj, readonly); | |
2911a35b | 3185 | |
b4716185 CW |
3186 | n = 0; |
3187 | if (readonly) { | |
3188 | if (obj->last_write_req) | |
3189 | req[n++] = obj->last_write_req; | |
3190 | } else { | |
3191 | for (i = 0; i < I915_NUM_RINGS; i++) | |
3192 | if (obj->last_read_req[i]) | |
3193 | req[n++] = obj->last_read_req[i]; | |
3194 | } | |
3195 | for (i = 0; i < n; i++) { | |
91af127f | 3196 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
b4716185 CW |
3197 | if (ret) |
3198 | return ret; | |
3199 | } | |
2911a35b | 3200 | |
b4716185 | 3201 | return 0; |
2911a35b BW |
3202 | } |
3203 | ||
b5ffc9bc CW |
3204 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3205 | { | |
3206 | u32 old_write_domain, old_read_domains; | |
3207 | ||
b5ffc9bc CW |
3208 | /* Force a pagefault for domain tracking on next user access */ |
3209 | i915_gem_release_mmap(obj); | |
3210 | ||
b97c3d9c KP |
3211 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3212 | return; | |
3213 | ||
97c809fd CW |
3214 | /* Wait for any direct GTT access to complete */ |
3215 | mb(); | |
3216 | ||
b5ffc9bc CW |
3217 | old_read_domains = obj->base.read_domains; |
3218 | old_write_domain = obj->base.write_domain; | |
3219 | ||
3220 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3221 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3222 | ||
3223 | trace_i915_gem_object_change_domain(obj, | |
3224 | old_read_domains, | |
3225 | old_write_domain); | |
3226 | } | |
3227 | ||
e9f24d5f | 3228 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
673a394b | 3229 | { |
07fe0b12 | 3230 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3231 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3232 | int ret; |
673a394b | 3233 | |
07fe0b12 | 3234 | if (list_empty(&vma->vma_link)) |
673a394b EA |
3235 | return 0; |
3236 | ||
0ff501cb DV |
3237 | if (!drm_mm_node_allocated(&vma->node)) { |
3238 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3239 | return 0; |
3240 | } | |
433544bd | 3241 | |
d7f46fc4 | 3242 | if (vma->pin_count) |
31d8d651 | 3243 | return -EBUSY; |
673a394b | 3244 | |
c4670ad0 CW |
3245 | BUG_ON(obj->pages == NULL); |
3246 | ||
e9f24d5f TU |
3247 | if (wait) { |
3248 | ret = i915_gem_object_wait_rendering(obj, false); | |
3249 | if (ret) | |
3250 | return ret; | |
3251 | } | |
a8198eea | 3252 | |
fe14d5f4 TU |
3253 | if (i915_is_ggtt(vma->vm) && |
3254 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
8b1bc9b4 | 3255 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3256 | |
8b1bc9b4 DV |
3257 | /* release the fence reg _after_ flushing */ |
3258 | ret = i915_gem_object_put_fence(obj); | |
3259 | if (ret) | |
3260 | return ret; | |
3261 | } | |
96b47b65 | 3262 | |
07fe0b12 | 3263 | trace_i915_vma_unbind(vma); |
db53a302 | 3264 | |
777dc5bb | 3265 | vma->vm->unbind_vma(vma); |
5e562f1d | 3266 | vma->bound = 0; |
6f65e29a | 3267 | |
64bf9303 | 3268 | list_del_init(&vma->mm_list); |
fe14d5f4 TU |
3269 | if (i915_is_ggtt(vma->vm)) { |
3270 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
3271 | obj->map_and_fenceable = false; | |
3272 | } else if (vma->ggtt_view.pages) { | |
3273 | sg_free_table(vma->ggtt_view.pages); | |
3274 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 3275 | } |
016a65a3 | 3276 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 3277 | } |
673a394b | 3278 | |
2f633156 BW |
3279 | drm_mm_remove_node(&vma->node); |
3280 | i915_gem_vma_destroy(vma); | |
3281 | ||
3282 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3283 | * no more VMAs exist. */ |
e2273302 | 3284 | if (list_empty(&obj->vma_list)) |
2f633156 | 3285 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
673a394b | 3286 | |
70903c3b CW |
3287 | /* And finally now the object is completely decoupled from this vma, |
3288 | * we can drop its hold on the backing storage and allow it to be | |
3289 | * reaped by the shrinker. | |
3290 | */ | |
3291 | i915_gem_object_unpin_pages(obj); | |
3292 | ||
88241785 | 3293 | return 0; |
54cf91dc CW |
3294 | } |
3295 | ||
e9f24d5f TU |
3296 | int i915_vma_unbind(struct i915_vma *vma) |
3297 | { | |
3298 | return __i915_vma_unbind(vma, true); | |
3299 | } | |
3300 | ||
3301 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) | |
3302 | { | |
3303 | return __i915_vma_unbind(vma, false); | |
3304 | } | |
3305 | ||
b2da9fe5 | 3306 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3307 | { |
3e31c6c0 | 3308 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3309 | struct intel_engine_cs *ring; |
1ec14ad3 | 3310 | int ret, i; |
4df2faf4 | 3311 | |
4df2faf4 | 3312 | /* Flush everything onto the inactive list. */ |
b4519513 | 3313 | for_each_ring(ring, dev_priv, i) { |
ecdb5fd8 | 3314 | if (!i915.enable_execlists) { |
73cfa865 JH |
3315 | struct drm_i915_gem_request *req; |
3316 | ||
3317 | ret = i915_gem_request_alloc(ring, ring->default_context, &req); | |
ecdb5fd8 TD |
3318 | if (ret) |
3319 | return ret; | |
73cfa865 | 3320 | |
ba01cc93 | 3321 | ret = i915_switch_context(req); |
73cfa865 JH |
3322 | if (ret) { |
3323 | i915_gem_request_cancel(req); | |
3324 | return ret; | |
3325 | } | |
3326 | ||
75289874 | 3327 | i915_add_request_no_flush(req); |
ecdb5fd8 | 3328 | } |
b6c7488d | 3329 | |
3e960501 | 3330 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
3331 | if (ret) |
3332 | return ret; | |
3333 | } | |
4df2faf4 | 3334 | |
b4716185 | 3335 | WARN_ON(i915_verify_lists(dev)); |
8a1a49f9 | 3336 | return 0; |
4df2faf4 DV |
3337 | } |
3338 | ||
4144f9b5 | 3339 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3340 | unsigned long cache_level) |
3341 | { | |
4144f9b5 | 3342 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3343 | struct drm_mm_node *other; |
3344 | ||
4144f9b5 CW |
3345 | /* |
3346 | * On some machines we have to be careful when putting differing types | |
3347 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3348 | * domains and dying. During vm initialisation, we decide whether or not | |
3349 | * these constraints apply and set the drm_mm.color_adjust | |
3350 | * appropriately. | |
42d6ab48 | 3351 | */ |
4144f9b5 | 3352 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3353 | return true; |
3354 | ||
c6cfb325 | 3355 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3356 | return true; |
3357 | ||
3358 | if (list_empty(>t_space->node_list)) | |
3359 | return true; | |
3360 | ||
3361 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3362 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3363 | return false; | |
3364 | ||
3365 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3366 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3367 | return false; | |
3368 | ||
3369 | return true; | |
3370 | } | |
3371 | ||
673a394b | 3372 | /** |
91e6711e JL |
3373 | * Finds free space in the GTT aperture and binds the object or a view of it |
3374 | * there. | |
673a394b | 3375 | */ |
262de145 | 3376 | static struct i915_vma * |
07fe0b12 BW |
3377 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3378 | struct i915_address_space *vm, | |
ec7adb6e | 3379 | const struct i915_ggtt_view *ggtt_view, |
07fe0b12 | 3380 | unsigned alignment, |
ec7adb6e | 3381 | uint64_t flags) |
673a394b | 3382 | { |
05394f39 | 3383 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3384 | struct drm_i915_private *dev_priv = dev->dev_private; |
65bd342f | 3385 | u32 fence_alignment, unfenced_alignment; |
101b506a MT |
3386 | u32 search_flag, alloc_flag; |
3387 | u64 start, end; | |
65bd342f | 3388 | u64 size, fence_size; |
2f633156 | 3389 | struct i915_vma *vma; |
07f73f69 | 3390 | int ret; |
673a394b | 3391 | |
91e6711e JL |
3392 | if (i915_is_ggtt(vm)) { |
3393 | u32 view_size; | |
3394 | ||
3395 | if (WARN_ON(!ggtt_view)) | |
3396 | return ERR_PTR(-EINVAL); | |
ec7adb6e | 3397 | |
91e6711e JL |
3398 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
3399 | ||
3400 | fence_size = i915_gem_get_gtt_size(dev, | |
3401 | view_size, | |
3402 | obj->tiling_mode); | |
3403 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3404 | view_size, | |
3405 | obj->tiling_mode, | |
3406 | true); | |
3407 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, | |
3408 | view_size, | |
3409 | obj->tiling_mode, | |
3410 | false); | |
3411 | size = flags & PIN_MAPPABLE ? fence_size : view_size; | |
3412 | } else { | |
3413 | fence_size = i915_gem_get_gtt_size(dev, | |
3414 | obj->base.size, | |
3415 | obj->tiling_mode); | |
3416 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3417 | obj->base.size, | |
3418 | obj->tiling_mode, | |
3419 | true); | |
3420 | unfenced_alignment = | |
3421 | i915_gem_get_gtt_alignment(dev, | |
3422 | obj->base.size, | |
3423 | obj->tiling_mode, | |
3424 | false); | |
3425 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; | |
3426 | } | |
a00b10c3 | 3427 | |
101b506a MT |
3428 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
3429 | end = vm->total; | |
3430 | if (flags & PIN_MAPPABLE) | |
3431 | end = min_t(u64, end, dev_priv->gtt.mappable_end); | |
3432 | if (flags & PIN_ZONE_4G) | |
3433 | end = min_t(u64, end, (1ULL << 32)); | |
3434 | ||
673a394b | 3435 | if (alignment == 0) |
1ec9e26d | 3436 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3437 | unfenced_alignment; |
1ec9e26d | 3438 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
91e6711e JL |
3439 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
3440 | ggtt_view ? ggtt_view->type : 0, | |
3441 | alignment); | |
262de145 | 3442 | return ERR_PTR(-EINVAL); |
673a394b EA |
3443 | } |
3444 | ||
91e6711e JL |
3445 | /* If binding the object/GGTT view requires more space than the entire |
3446 | * aperture has, reject it early before evicting everything in a vain | |
3447 | * attempt to find space. | |
654fc607 | 3448 | */ |
91e6711e | 3449 | if (size > end) { |
65bd342f | 3450 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
91e6711e JL |
3451 | ggtt_view ? ggtt_view->type : 0, |
3452 | size, | |
1ec9e26d | 3453 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3454 | end); |
262de145 | 3455 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3456 | } |
3457 | ||
37e680a1 | 3458 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3459 | if (ret) |
262de145 | 3460 | return ERR_PTR(ret); |
6c085a72 | 3461 | |
fbdda6fb CW |
3462 | i915_gem_object_pin_pages(obj); |
3463 | ||
ec7adb6e JL |
3464 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
3465 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3466 | ||
262de145 | 3467 | if (IS_ERR(vma)) |
bc6bc15b | 3468 | goto err_unpin; |
2f633156 | 3469 | |
101b506a MT |
3470 | if (flags & PIN_HIGH) { |
3471 | search_flag = DRM_MM_SEARCH_BELOW; | |
3472 | alloc_flag = DRM_MM_CREATE_TOP; | |
3473 | } else { | |
3474 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3475 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3476 | } | |
3477 | ||
0a9ae0d7 | 3478 | search_free: |
07fe0b12 | 3479 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3480 | size, alignment, |
d23db88c CW |
3481 | obj->cache_level, |
3482 | start, end, | |
101b506a MT |
3483 | search_flag, |
3484 | alloc_flag); | |
dc9dd7a2 | 3485 | if (ret) { |
f6cd1f15 | 3486 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3487 | obj->cache_level, |
3488 | start, end, | |
3489 | flags); | |
dc9dd7a2 CW |
3490 | if (ret == 0) |
3491 | goto search_free; | |
9731129c | 3492 | |
bc6bc15b | 3493 | goto err_free_vma; |
673a394b | 3494 | } |
4144f9b5 | 3495 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3496 | ret = -EINVAL; |
bc6bc15b | 3497 | goto err_remove_node; |
673a394b EA |
3498 | } |
3499 | ||
fe14d5f4 | 3500 | trace_i915_vma_bind(vma, flags); |
0875546c | 3501 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
fe14d5f4 | 3502 | if (ret) |
e2273302 | 3503 | goto err_remove_node; |
fe14d5f4 | 3504 | |
35c20a60 | 3505 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3506 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3507 | |
262de145 | 3508 | return vma; |
2f633156 | 3509 | |
bc6bc15b | 3510 | err_remove_node: |
6286ef9b | 3511 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3512 | err_free_vma: |
2f633156 | 3513 | i915_gem_vma_destroy(vma); |
262de145 | 3514 | vma = ERR_PTR(ret); |
bc6bc15b | 3515 | err_unpin: |
2f633156 | 3516 | i915_gem_object_unpin_pages(obj); |
262de145 | 3517 | return vma; |
673a394b EA |
3518 | } |
3519 | ||
000433b6 | 3520 | bool |
2c22569b CW |
3521 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3522 | bool force) | |
673a394b | 3523 | { |
673a394b EA |
3524 | /* If we don't have a page list set up, then we're not pinned |
3525 | * to GPU, and we can ignore the cache flush because it'll happen | |
3526 | * again at bind time. | |
3527 | */ | |
05394f39 | 3528 | if (obj->pages == NULL) |
000433b6 | 3529 | return false; |
673a394b | 3530 | |
769ce464 ID |
3531 | /* |
3532 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3533 | * marked as wc by the system, or the system is cache-coherent. | |
3534 | */ | |
6a2c4232 | 3535 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3536 | return false; |
769ce464 | 3537 | |
9c23f7fc CW |
3538 | /* If the GPU is snooping the contents of the CPU cache, |
3539 | * we do not need to manually clear the CPU cache lines. However, | |
3540 | * the caches are only snooped when the render cache is | |
3541 | * flushed/invalidated. As we always have to emit invalidations | |
3542 | * and flushes when moving into and out of the RENDER domain, correct | |
3543 | * snooping behaviour occurs naturally as the result of our domain | |
3544 | * tracking. | |
3545 | */ | |
0f71979a CW |
3546 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3547 | obj->cache_dirty = true; | |
000433b6 | 3548 | return false; |
0f71979a | 3549 | } |
9c23f7fc | 3550 | |
1c5d22f7 | 3551 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3552 | drm_clflush_sg(obj->pages); |
0f71979a | 3553 | obj->cache_dirty = false; |
000433b6 CW |
3554 | |
3555 | return true; | |
e47c68e9 EA |
3556 | } |
3557 | ||
3558 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3559 | static void | |
05394f39 | 3560 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3561 | { |
1c5d22f7 CW |
3562 | uint32_t old_write_domain; |
3563 | ||
05394f39 | 3564 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3565 | return; |
3566 | ||
63256ec5 | 3567 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3568 | * to it immediately go to main memory as far as we know, so there's |
3569 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3570 | * |
3571 | * However, we do have to enforce the order so that all writes through | |
3572 | * the GTT land before any writes to the device, such as updates to | |
3573 | * the GATT itself. | |
e47c68e9 | 3574 | */ |
63256ec5 CW |
3575 | wmb(); |
3576 | ||
05394f39 CW |
3577 | old_write_domain = obj->base.write_domain; |
3578 | obj->base.write_domain = 0; | |
1c5d22f7 | 3579 | |
de152b62 | 3580 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3581 | |
1c5d22f7 | 3582 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3583 | obj->base.read_domains, |
1c5d22f7 | 3584 | old_write_domain); |
e47c68e9 EA |
3585 | } |
3586 | ||
3587 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3588 | static void | |
e62b59e4 | 3589 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3590 | { |
1c5d22f7 | 3591 | uint32_t old_write_domain; |
e47c68e9 | 3592 | |
05394f39 | 3593 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3594 | return; |
3595 | ||
e62b59e4 | 3596 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
000433b6 CW |
3597 | i915_gem_chipset_flush(obj->base.dev); |
3598 | ||
05394f39 CW |
3599 | old_write_domain = obj->base.write_domain; |
3600 | obj->base.write_domain = 0; | |
1c5d22f7 | 3601 | |
de152b62 | 3602 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3603 | |
1c5d22f7 | 3604 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3605 | obj->base.read_domains, |
1c5d22f7 | 3606 | old_write_domain); |
e47c68e9 EA |
3607 | } |
3608 | ||
2ef7eeaa EA |
3609 | /** |
3610 | * Moves a single object to the GTT read, and possibly write domain. | |
3611 | * | |
3612 | * This function returns when the move is complete, including waiting on | |
3613 | * flushes to occur. | |
3614 | */ | |
79e53945 | 3615 | int |
2021746e | 3616 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3617 | { |
1c5d22f7 | 3618 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3619 | struct i915_vma *vma; |
e47c68e9 | 3620 | int ret; |
2ef7eeaa | 3621 | |
8d7e3de1 CW |
3622 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3623 | return 0; | |
3624 | ||
0201f1ec | 3625 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3626 | if (ret) |
3627 | return ret; | |
3628 | ||
43566ded CW |
3629 | /* Flush and acquire obj->pages so that we are coherent through |
3630 | * direct access in memory with previous cached writes through | |
3631 | * shmemfs and that our cache domain tracking remains valid. | |
3632 | * For example, if the obj->filp was moved to swap without us | |
3633 | * being notified and releasing the pages, we would mistakenly | |
3634 | * continue to assume that the obj remained out of the CPU cached | |
3635 | * domain. | |
3636 | */ | |
3637 | ret = i915_gem_object_get_pages(obj); | |
3638 | if (ret) | |
3639 | return ret; | |
3640 | ||
e62b59e4 | 3641 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3642 | |
d0a57789 CW |
3643 | /* Serialise direct access to this object with the barriers for |
3644 | * coherent writes from the GPU, by effectively invalidating the | |
3645 | * GTT domain upon first access. | |
3646 | */ | |
3647 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3648 | mb(); | |
3649 | ||
05394f39 CW |
3650 | old_write_domain = obj->base.write_domain; |
3651 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3652 | |
e47c68e9 EA |
3653 | /* It should now be out of any other write domains, and we can update |
3654 | * the domain values for our changes. | |
3655 | */ | |
05394f39 CW |
3656 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3657 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3658 | if (write) { |
05394f39 CW |
3659 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3660 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3661 | obj->dirty = 1; | |
2ef7eeaa EA |
3662 | } |
3663 | ||
1c5d22f7 CW |
3664 | trace_i915_gem_object_change_domain(obj, |
3665 | old_read_domains, | |
3666 | old_write_domain); | |
3667 | ||
8325a09d | 3668 | /* And bump the LRU for this access */ |
43566ded CW |
3669 | vma = i915_gem_obj_to_ggtt(obj); |
3670 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
dc8cd1e7 | 3671 | list_move_tail(&vma->mm_list, |
43566ded | 3672 | &to_i915(obj->base.dev)->gtt.base.inactive_list); |
8325a09d | 3673 | |
e47c68e9 EA |
3674 | return 0; |
3675 | } | |
3676 | ||
ef55f92a CW |
3677 | /** |
3678 | * Changes the cache-level of an object across all VMA. | |
3679 | * | |
3680 | * After this function returns, the object will be in the new cache-level | |
3681 | * across all GTT and the contents of the backing storage will be coherent, | |
3682 | * with respect to the new cache-level. In order to keep the backing storage | |
3683 | * coherent for all users, we only allow a single cache level to be set | |
3684 | * globally on the object and prevent it from being changed whilst the | |
3685 | * hardware is reading from the object. That is if the object is currently | |
3686 | * on the scanout it will be set to uncached (or equivalent display | |
3687 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3688 | * that all direct access to the scanout remains coherent. | |
3689 | */ | |
e4ffd173 CW |
3690 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3691 | enum i915_cache_level cache_level) | |
3692 | { | |
7bddb01f | 3693 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3694 | struct i915_vma *vma, *next; |
ef55f92a | 3695 | bool bound = false; |
ed75a55b | 3696 | int ret = 0; |
e4ffd173 CW |
3697 | |
3698 | if (obj->cache_level == cache_level) | |
ed75a55b | 3699 | goto out; |
e4ffd173 | 3700 | |
ef55f92a CW |
3701 | /* Inspect the list of currently bound VMA and unbind any that would |
3702 | * be invalid given the new cache-level. This is principally to | |
3703 | * catch the issue of the CS prefetch crossing page boundaries and | |
3704 | * reading an invalid PTE on older architectures. | |
3705 | */ | |
df6f783a | 3706 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
ef55f92a CW |
3707 | if (!drm_mm_node_allocated(&vma->node)) |
3708 | continue; | |
3709 | ||
3710 | if (vma->pin_count) { | |
3711 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3712 | return -EBUSY; | |
3713 | } | |
3714 | ||
4144f9b5 | 3715 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3716 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3717 | if (ret) |
3718 | return ret; | |
ef55f92a CW |
3719 | } else |
3720 | bound = true; | |
42d6ab48 CW |
3721 | } |
3722 | ||
ef55f92a CW |
3723 | /* We can reuse the existing drm_mm nodes but need to change the |
3724 | * cache-level on the PTE. We could simply unbind them all and | |
3725 | * rebind with the correct cache-level on next use. However since | |
3726 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3727 | * rewrite the PTE in the belief that doing so tramples upon less | |
3728 | * state and so involves less work. | |
3729 | */ | |
3730 | if (bound) { | |
3731 | /* Before we change the PTE, the GPU must not be accessing it. | |
3732 | * If we wait upon the object, we know that all the bound | |
3733 | * VMA are no longer active. | |
3734 | */ | |
2e2f351d | 3735 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3736 | if (ret) |
3737 | return ret; | |
3738 | ||
ef55f92a CW |
3739 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
3740 | /* Access to snoopable pages through the GTT is | |
3741 | * incoherent and on some machines causes a hard | |
3742 | * lockup. Relinquish the CPU mmaping to force | |
3743 | * userspace to refault in the pages and we can | |
3744 | * then double check if the GTT mapping is still | |
3745 | * valid for that pointer access. | |
3746 | */ | |
3747 | i915_gem_release_mmap(obj); | |
3748 | ||
3749 | /* As we no longer need a fence for GTT access, | |
3750 | * we can relinquish it now (and so prevent having | |
3751 | * to steal a fence from someone else on the next | |
3752 | * fence request). Note GPU activity would have | |
3753 | * dropped the fence as all snoopable access is | |
3754 | * supposed to be linear. | |
3755 | */ | |
e4ffd173 CW |
3756 | ret = i915_gem_object_put_fence(obj); |
3757 | if (ret) | |
3758 | return ret; | |
ef55f92a CW |
3759 | } else { |
3760 | /* We either have incoherent backing store and | |
3761 | * so no GTT access or the architecture is fully | |
3762 | * coherent. In such cases, existing GTT mmaps | |
3763 | * ignore the cache bit in the PTE and we can | |
3764 | * rewrite it without confusing the GPU or having | |
3765 | * to force userspace to fault back in its mmaps. | |
3766 | */ | |
e4ffd173 CW |
3767 | } |
3768 | ||
ef55f92a CW |
3769 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3770 | if (!drm_mm_node_allocated(&vma->node)) | |
3771 | continue; | |
3772 | ||
3773 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3774 | if (ret) | |
3775 | return ret; | |
3776 | } | |
e4ffd173 CW |
3777 | } |
3778 | ||
2c22569b CW |
3779 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3780 | vma->node.color = cache_level; | |
3781 | obj->cache_level = cache_level; | |
3782 | ||
ed75a55b | 3783 | out: |
ef55f92a CW |
3784 | /* Flush the dirty CPU caches to the backing storage so that the |
3785 | * object is now coherent at its new cache level (with respect | |
3786 | * to the access domain). | |
3787 | */ | |
0f71979a CW |
3788 | if (obj->cache_dirty && |
3789 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
3790 | cpu_write_needs_clflush(obj)) { | |
3791 | if (i915_gem_clflush_object(obj, true)) | |
3792 | i915_gem_chipset_flush(obj->base.dev); | |
e4ffd173 CW |
3793 | } |
3794 | ||
e4ffd173 CW |
3795 | return 0; |
3796 | } | |
3797 | ||
199adf40 BW |
3798 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3799 | struct drm_file *file) | |
e6994aee | 3800 | { |
199adf40 | 3801 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3802 | struct drm_i915_gem_object *obj; |
e6994aee CW |
3803 | |
3804 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
432be69d CW |
3805 | if (&obj->base == NULL) |
3806 | return -ENOENT; | |
e6994aee | 3807 | |
651d794f CW |
3808 | switch (obj->cache_level) { |
3809 | case I915_CACHE_LLC: | |
3810 | case I915_CACHE_L3_LLC: | |
3811 | args->caching = I915_CACHING_CACHED; | |
3812 | break; | |
3813 | ||
4257d3ba CW |
3814 | case I915_CACHE_WT: |
3815 | args->caching = I915_CACHING_DISPLAY; | |
3816 | break; | |
3817 | ||
651d794f CW |
3818 | default: |
3819 | args->caching = I915_CACHING_NONE; | |
3820 | break; | |
3821 | } | |
e6994aee | 3822 | |
432be69d CW |
3823 | drm_gem_object_unreference_unlocked(&obj->base); |
3824 | return 0; | |
e6994aee CW |
3825 | } |
3826 | ||
199adf40 BW |
3827 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3828 | struct drm_file *file) | |
e6994aee | 3829 | { |
fd0fe6ac | 3830 | struct drm_i915_private *dev_priv = dev->dev_private; |
199adf40 | 3831 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3832 | struct drm_i915_gem_object *obj; |
3833 | enum i915_cache_level level; | |
3834 | int ret; | |
3835 | ||
199adf40 BW |
3836 | switch (args->caching) { |
3837 | case I915_CACHING_NONE: | |
e6994aee CW |
3838 | level = I915_CACHE_NONE; |
3839 | break; | |
199adf40 | 3840 | case I915_CACHING_CACHED: |
e5756c10 ID |
3841 | /* |
3842 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3843 | * snooped mapping may leave stale data in a corresponding CPU | |
3844 | * cacheline, whereas normally such cachelines would get | |
3845 | * invalidated. | |
3846 | */ | |
e87a005d | 3847 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
e5756c10 ID |
3848 | return -ENODEV; |
3849 | ||
e6994aee CW |
3850 | level = I915_CACHE_LLC; |
3851 | break; | |
4257d3ba CW |
3852 | case I915_CACHING_DISPLAY: |
3853 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3854 | break; | |
e6994aee CW |
3855 | default: |
3856 | return -EINVAL; | |
3857 | } | |
3858 | ||
fd0fe6ac ID |
3859 | intel_runtime_pm_get(dev_priv); |
3860 | ||
3bc2913e BW |
3861 | ret = i915_mutex_lock_interruptible(dev); |
3862 | if (ret) | |
fd0fe6ac | 3863 | goto rpm_put; |
3bc2913e | 3864 | |
e6994aee CW |
3865 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3866 | if (&obj->base == NULL) { | |
3867 | ret = -ENOENT; | |
3868 | goto unlock; | |
3869 | } | |
3870 | ||
3871 | ret = i915_gem_object_set_cache_level(obj, level); | |
3872 | ||
3873 | drm_gem_object_unreference(&obj->base); | |
3874 | unlock: | |
3875 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
3876 | rpm_put: |
3877 | intel_runtime_pm_put(dev_priv); | |
3878 | ||
e6994aee CW |
3879 | return ret; |
3880 | } | |
3881 | ||
b9241ea3 | 3882 | /* |
2da3b9b9 CW |
3883 | * Prepare buffer for display plane (scanout, cursors, etc). |
3884 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3885 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3886 | */ |
3887 | int | |
2da3b9b9 CW |
3888 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3889 | u32 alignment, | |
e6617330 | 3890 | const struct i915_ggtt_view *view) |
b9241ea3 | 3891 | { |
2da3b9b9 | 3892 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3893 | int ret; |
3894 | ||
cc98b413 CW |
3895 | /* Mark the pin_display early so that we account for the |
3896 | * display coherency whilst setting up the cache domains. | |
3897 | */ | |
8a0c39b1 | 3898 | obj->pin_display++; |
cc98b413 | 3899 | |
a7ef0640 EA |
3900 | /* The display engine is not coherent with the LLC cache on gen6. As |
3901 | * a result, we make sure that the pinning that is about to occur is | |
3902 | * done with uncached PTEs. This is lowest common denominator for all | |
3903 | * chipsets. | |
3904 | * | |
3905 | * However for gen6+, we could do better by using the GFDT bit instead | |
3906 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3907 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3908 | */ | |
651d794f CW |
3909 | ret = i915_gem_object_set_cache_level(obj, |
3910 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3911 | if (ret) |
cc98b413 | 3912 | goto err_unpin_display; |
a7ef0640 | 3913 | |
2da3b9b9 CW |
3914 | /* As the user may map the buffer once pinned in the display plane |
3915 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3916 | * always use map_and_fenceable for all scanout buffers. | |
3917 | */ | |
50470bb0 TU |
3918 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
3919 | view->type == I915_GGTT_VIEW_NORMAL ? | |
3920 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 3921 | if (ret) |
cc98b413 | 3922 | goto err_unpin_display; |
2da3b9b9 | 3923 | |
e62b59e4 | 3924 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3925 | |
2da3b9b9 | 3926 | old_write_domain = obj->base.write_domain; |
05394f39 | 3927 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3928 | |
3929 | /* It should now be out of any other write domains, and we can update | |
3930 | * the domain values for our changes. | |
3931 | */ | |
e5f1d962 | 3932 | obj->base.write_domain = 0; |
05394f39 | 3933 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3934 | |
3935 | trace_i915_gem_object_change_domain(obj, | |
3936 | old_read_domains, | |
2da3b9b9 | 3937 | old_write_domain); |
b9241ea3 ZW |
3938 | |
3939 | return 0; | |
cc98b413 CW |
3940 | |
3941 | err_unpin_display: | |
8a0c39b1 | 3942 | obj->pin_display--; |
cc98b413 CW |
3943 | return ret; |
3944 | } | |
3945 | ||
3946 | void | |
e6617330 TU |
3947 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3948 | const struct i915_ggtt_view *view) | |
cc98b413 | 3949 | { |
8a0c39b1 TU |
3950 | if (WARN_ON(obj->pin_display == 0)) |
3951 | return; | |
3952 | ||
e6617330 TU |
3953 | i915_gem_object_ggtt_unpin_view(obj, view); |
3954 | ||
8a0c39b1 | 3955 | obj->pin_display--; |
b9241ea3 ZW |
3956 | } |
3957 | ||
e47c68e9 EA |
3958 | /** |
3959 | * Moves a single object to the CPU read, and possibly write domain. | |
3960 | * | |
3961 | * This function returns when the move is complete, including waiting on | |
3962 | * flushes to occur. | |
3963 | */ | |
dabdfe02 | 3964 | int |
919926ae | 3965 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3966 | { |
1c5d22f7 | 3967 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3968 | int ret; |
3969 | ||
8d7e3de1 CW |
3970 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3971 | return 0; | |
3972 | ||
0201f1ec | 3973 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3974 | if (ret) |
3975 | return ret; | |
3976 | ||
e47c68e9 | 3977 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3978 | |
05394f39 CW |
3979 | old_write_domain = obj->base.write_domain; |
3980 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3981 | |
e47c68e9 | 3982 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3983 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3984 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3985 | |
05394f39 | 3986 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3987 | } |
3988 | ||
3989 | /* It should now be out of any other write domains, and we can update | |
3990 | * the domain values for our changes. | |
3991 | */ | |
05394f39 | 3992 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3993 | |
3994 | /* If we're writing through the CPU, then the GPU read domains will | |
3995 | * need to be invalidated at next use. | |
3996 | */ | |
3997 | if (write) { | |
05394f39 CW |
3998 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3999 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4000 | } |
2ef7eeaa | 4001 | |
1c5d22f7 CW |
4002 | trace_i915_gem_object_change_domain(obj, |
4003 | old_read_domains, | |
4004 | old_write_domain); | |
4005 | ||
2ef7eeaa EA |
4006 | return 0; |
4007 | } | |
4008 | ||
673a394b EA |
4009 | /* Throttle our rendering by waiting until the ring has completed our requests |
4010 | * emitted over 20 msec ago. | |
4011 | * | |
b962442e EA |
4012 | * Note that if we were to use the current jiffies each time around the loop, |
4013 | * we wouldn't escape the function with any frames outstanding if the time to | |
4014 | * render a frame was over 20ms. | |
4015 | * | |
673a394b EA |
4016 | * This should get us reasonable parallelism between CPU and GPU but also |
4017 | * relatively low latency when blocking on a particular request to finish. | |
4018 | */ | |
40a5f0de | 4019 | static int |
f787a5f5 | 4020 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4021 | { |
f787a5f5 CW |
4022 | struct drm_i915_private *dev_priv = dev->dev_private; |
4023 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
d0bc54f2 | 4024 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 4025 | struct drm_i915_gem_request *request, *target = NULL; |
f69061be | 4026 | unsigned reset_counter; |
f787a5f5 | 4027 | int ret; |
93533c29 | 4028 | |
308887aa DV |
4029 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4030 | if (ret) | |
4031 | return ret; | |
4032 | ||
4033 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4034 | if (ret) | |
4035 | return ret; | |
e110e8d6 | 4036 | |
1c25595f | 4037 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4038 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4039 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4040 | break; | |
40a5f0de | 4041 | |
fcfa423c JH |
4042 | /* |
4043 | * Note that the request might not have been submitted yet. | |
4044 | * In which case emitted_jiffies will be zero. | |
4045 | */ | |
4046 | if (!request->emitted_jiffies) | |
4047 | continue; | |
4048 | ||
54fb2411 | 4049 | target = request; |
b962442e | 4050 | } |
f69061be | 4051 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 JH |
4052 | if (target) |
4053 | i915_gem_request_reference(target); | |
1c25595f | 4054 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4055 | |
54fb2411 | 4056 | if (target == NULL) |
f787a5f5 | 4057 | return 0; |
2bc43b5c | 4058 | |
9c654818 | 4059 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4060 | if (ret == 0) |
4061 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4062 | |
41037f9f | 4063 | i915_gem_request_unreference__unlocked(target); |
ff865885 | 4064 | |
40a5f0de EA |
4065 | return ret; |
4066 | } | |
4067 | ||
d23db88c CW |
4068 | static bool |
4069 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4070 | { | |
4071 | struct drm_i915_gem_object *obj = vma->obj; | |
4072 | ||
4073 | if (alignment && | |
4074 | vma->node.start & (alignment - 1)) | |
4075 | return true; | |
4076 | ||
4077 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4078 | return true; | |
4079 | ||
4080 | if (flags & PIN_OFFSET_BIAS && | |
4081 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4082 | return true; | |
4083 | ||
4084 | return false; | |
4085 | } | |
4086 | ||
ec7adb6e JL |
4087 | static int |
4088 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
4089 | struct i915_address_space *vm, | |
4090 | const struct i915_ggtt_view *ggtt_view, | |
4091 | uint32_t alignment, | |
4092 | uint64_t flags) | |
673a394b | 4093 | { |
6e7186af | 4094 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4095 | struct i915_vma *vma; |
ef79e17c | 4096 | unsigned bound; |
673a394b EA |
4097 | int ret; |
4098 | ||
6e7186af BW |
4099 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4100 | return -ENODEV; | |
4101 | ||
bf3d149b | 4102 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4103 | return -EINVAL; |
07fe0b12 | 4104 | |
c826c449 CW |
4105 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4106 | return -EINVAL; | |
4107 | ||
ec7adb6e JL |
4108 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
4109 | return -EINVAL; | |
4110 | ||
4111 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
4112 | i915_gem_obj_to_vma(obj, vm); | |
4113 | ||
4114 | if (IS_ERR(vma)) | |
4115 | return PTR_ERR(vma); | |
4116 | ||
07fe0b12 | 4117 | if (vma) { |
d7f46fc4 BW |
4118 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4119 | return -EBUSY; | |
4120 | ||
d23db88c | 4121 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4122 | WARN(vma->pin_count, |
ec7adb6e | 4123 | "bo is already pinned in %s with incorrect alignment:" |
088e0df4 | 4124 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4125 | " obj->map_and_fenceable=%d\n", |
ec7adb6e | 4126 | ggtt_view ? "ggtt" : "ppgtt", |
088e0df4 MT |
4127 | upper_32_bits(vma->node.start), |
4128 | lower_32_bits(vma->node.start), | |
fe14d5f4 | 4129 | alignment, |
d23db88c | 4130 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4131 | obj->map_and_fenceable); |
07fe0b12 | 4132 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4133 | if (ret) |
4134 | return ret; | |
8ea99c92 DV |
4135 | |
4136 | vma = NULL; | |
ac0c6b5a CW |
4137 | } |
4138 | } | |
4139 | ||
ef79e17c | 4140 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4141 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
ec7adb6e JL |
4142 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
4143 | flags); | |
262de145 DV |
4144 | if (IS_ERR(vma)) |
4145 | return PTR_ERR(vma); | |
0875546c DV |
4146 | } else { |
4147 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
fe14d5f4 TU |
4148 | if (ret) |
4149 | return ret; | |
4150 | } | |
74898d7e | 4151 | |
91e6711e JL |
4152 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
4153 | (bound ^ vma->bound) & GLOBAL_BIND) { | |
ef79e17c CW |
4154 | bool mappable, fenceable; |
4155 | u32 fence_size, fence_alignment; | |
4156 | ||
4157 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4158 | obj->base.size, | |
4159 | obj->tiling_mode); | |
4160 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4161 | obj->base.size, | |
4162 | obj->tiling_mode, | |
4163 | true); | |
4164 | ||
4165 | fenceable = (vma->node.size == fence_size && | |
4166 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4167 | ||
e8dec1dd | 4168 | mappable = (vma->node.start + fence_size <= |
ef79e17c CW |
4169 | dev_priv->gtt.mappable_end); |
4170 | ||
4171 | obj->map_and_fenceable = mappable && fenceable; | |
ef79e17c | 4172 | |
91e6711e JL |
4173 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
4174 | } | |
ef79e17c | 4175 | |
8ea99c92 | 4176 | vma->pin_count++; |
673a394b EA |
4177 | return 0; |
4178 | } | |
4179 | ||
ec7adb6e JL |
4180 | int |
4181 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
4182 | struct i915_address_space *vm, | |
4183 | uint32_t alignment, | |
4184 | uint64_t flags) | |
4185 | { | |
4186 | return i915_gem_object_do_pin(obj, vm, | |
4187 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
4188 | alignment, flags); | |
4189 | } | |
4190 | ||
4191 | int | |
4192 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
4193 | const struct i915_ggtt_view *view, | |
4194 | uint32_t alignment, | |
4195 | uint64_t flags) | |
4196 | { | |
4197 | if (WARN_ONCE(!view, "no view specified")) | |
4198 | return -EINVAL; | |
4199 | ||
4200 | return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view, | |
6fafab76 | 4201 | alignment, flags | PIN_GLOBAL); |
ec7adb6e JL |
4202 | } |
4203 | ||
673a394b | 4204 | void |
e6617330 TU |
4205 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
4206 | const struct i915_ggtt_view *view) | |
673a394b | 4207 | { |
e6617330 | 4208 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 4209 | |
d7f46fc4 | 4210 | BUG_ON(!vma); |
e6617330 | 4211 | WARN_ON(vma->pin_count == 0); |
9abc4648 | 4212 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 4213 | |
30154650 | 4214 | --vma->pin_count; |
673a394b EA |
4215 | } |
4216 | ||
673a394b EA |
4217 | int |
4218 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4219 | struct drm_file *file) |
673a394b EA |
4220 | { |
4221 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4222 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4223 | int ret; |
4224 | ||
76c1dec1 | 4225 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4226 | if (ret) |
76c1dec1 | 4227 | return ret; |
673a394b | 4228 | |
05394f39 | 4229 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4230 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4231 | ret = -ENOENT; |
4232 | goto unlock; | |
673a394b | 4233 | } |
d1b851fc | 4234 | |
0be555b6 CW |
4235 | /* Count all active objects as busy, even if they are currently not used |
4236 | * by the gpu. Users of this interface expect objects to eventually | |
4237 | * become non-busy without any further actions, therefore emit any | |
4238 | * necessary flushes here. | |
c4de0a5d | 4239 | */ |
30dfebf3 | 4240 | ret = i915_gem_object_flush_active(obj); |
b4716185 CW |
4241 | if (ret) |
4242 | goto unref; | |
0be555b6 | 4243 | |
b4716185 CW |
4244 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
4245 | args->busy = obj->active << 16; | |
4246 | if (obj->last_write_req) | |
4247 | args->busy |= obj->last_write_req->ring->id; | |
673a394b | 4248 | |
b4716185 | 4249 | unref: |
05394f39 | 4250 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4251 | unlock: |
673a394b | 4252 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4253 | return ret; |
673a394b EA |
4254 | } |
4255 | ||
4256 | int | |
4257 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4258 | struct drm_file *file_priv) | |
4259 | { | |
0206e353 | 4260 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4261 | } |
4262 | ||
3ef94daa CW |
4263 | int |
4264 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4265 | struct drm_file *file_priv) | |
4266 | { | |
656bfa3a | 4267 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4268 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4269 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4270 | int ret; |
3ef94daa CW |
4271 | |
4272 | switch (args->madv) { | |
4273 | case I915_MADV_DONTNEED: | |
4274 | case I915_MADV_WILLNEED: | |
4275 | break; | |
4276 | default: | |
4277 | return -EINVAL; | |
4278 | } | |
4279 | ||
1d7cfea1 CW |
4280 | ret = i915_mutex_lock_interruptible(dev); |
4281 | if (ret) | |
4282 | return ret; | |
4283 | ||
05394f39 | 4284 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4285 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4286 | ret = -ENOENT; |
4287 | goto unlock; | |
3ef94daa | 4288 | } |
3ef94daa | 4289 | |
d7f46fc4 | 4290 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4291 | ret = -EINVAL; |
4292 | goto out; | |
3ef94daa CW |
4293 | } |
4294 | ||
656bfa3a DV |
4295 | if (obj->pages && |
4296 | obj->tiling_mode != I915_TILING_NONE && | |
4297 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4298 | if (obj->madv == I915_MADV_WILLNEED) | |
4299 | i915_gem_object_unpin_pages(obj); | |
4300 | if (args->madv == I915_MADV_WILLNEED) | |
4301 | i915_gem_object_pin_pages(obj); | |
4302 | } | |
4303 | ||
05394f39 CW |
4304 | if (obj->madv != __I915_MADV_PURGED) |
4305 | obj->madv = args->madv; | |
3ef94daa | 4306 | |
6c085a72 | 4307 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4308 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4309 | i915_gem_object_truncate(obj); |
4310 | ||
05394f39 | 4311 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4312 | |
1d7cfea1 | 4313 | out: |
05394f39 | 4314 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4315 | unlock: |
3ef94daa | 4316 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4317 | return ret; |
3ef94daa CW |
4318 | } |
4319 | ||
37e680a1 CW |
4320 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4321 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4322 | { |
b4716185 CW |
4323 | int i; |
4324 | ||
35c20a60 | 4325 | INIT_LIST_HEAD(&obj->global_list); |
b4716185 CW |
4326 | for (i = 0; i < I915_NUM_RINGS; i++) |
4327 | INIT_LIST_HEAD(&obj->ring_list[i]); | |
b25cb2f8 | 4328 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4329 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4330 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4331 | |
37e680a1 CW |
4332 | obj->ops = ops; |
4333 | ||
0327d6ba CW |
4334 | obj->fence_reg = I915_FENCE_REG_NONE; |
4335 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4336 | |
4337 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4338 | } | |
4339 | ||
37e680a1 CW |
4340 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4341 | .get_pages = i915_gem_object_get_pages_gtt, | |
4342 | .put_pages = i915_gem_object_put_pages_gtt, | |
4343 | }; | |
4344 | ||
05394f39 CW |
4345 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4346 | size_t size) | |
ac52bc56 | 4347 | { |
c397b908 | 4348 | struct drm_i915_gem_object *obj; |
5949eac4 | 4349 | struct address_space *mapping; |
1a240d4d | 4350 | gfp_t mask; |
ac52bc56 | 4351 | |
42dcedd4 | 4352 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4353 | if (obj == NULL) |
4354 | return NULL; | |
673a394b | 4355 | |
c397b908 | 4356 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4357 | i915_gem_object_free(obj); |
c397b908 DV |
4358 | return NULL; |
4359 | } | |
673a394b | 4360 | |
bed1ea95 CW |
4361 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4362 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4363 | /* 965gm cannot relocate objects above 4GiB. */ | |
4364 | mask &= ~__GFP_HIGHMEM; | |
4365 | mask |= __GFP_DMA32; | |
4366 | } | |
4367 | ||
496ad9aa | 4368 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4369 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4370 | |
37e680a1 | 4371 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4372 | |
c397b908 DV |
4373 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4374 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4375 | |
3d29b842 ED |
4376 | if (HAS_LLC(dev)) { |
4377 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4378 | * cache) for about a 10% performance improvement |
4379 | * compared to uncached. Graphics requests other than | |
4380 | * display scanout are coherent with the CPU in | |
4381 | * accessing this cache. This means in this mode we | |
4382 | * don't need to clflush on the CPU side, and on the | |
4383 | * GPU side we only need to flush internal caches to | |
4384 | * get data visible to the CPU. | |
4385 | * | |
4386 | * However, we maintain the display planes as UC, and so | |
4387 | * need to rebind when first used as such. | |
4388 | */ | |
4389 | obj->cache_level = I915_CACHE_LLC; | |
4390 | } else | |
4391 | obj->cache_level = I915_CACHE_NONE; | |
4392 | ||
d861e338 DV |
4393 | trace_i915_gem_object_create(obj); |
4394 | ||
05394f39 | 4395 | return obj; |
c397b908 DV |
4396 | } |
4397 | ||
340fbd8c CW |
4398 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4399 | { | |
4400 | /* If we are the last user of the backing storage (be it shmemfs | |
4401 | * pages or stolen etc), we know that the pages are going to be | |
4402 | * immediately released. In this case, we can then skip copying | |
4403 | * back the contents from the GPU. | |
4404 | */ | |
4405 | ||
4406 | if (obj->madv != I915_MADV_WILLNEED) | |
4407 | return false; | |
4408 | ||
4409 | if (obj->base.filp == NULL) | |
4410 | return true; | |
4411 | ||
4412 | /* At first glance, this looks racy, but then again so would be | |
4413 | * userspace racing mmap against close. However, the first external | |
4414 | * reference to the filp can only be obtained through the | |
4415 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4416 | * acquiring such a reference whilst we are in the middle of | |
4417 | * freeing the object. | |
4418 | */ | |
4419 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4420 | } | |
4421 | ||
1488fc08 | 4422 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4423 | { |
1488fc08 | 4424 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4425 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4426 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4427 | struct i915_vma *vma, *next; |
673a394b | 4428 | |
f65c9168 PZ |
4429 | intel_runtime_pm_get(dev_priv); |
4430 | ||
26e12f89 CW |
4431 | trace_i915_gem_object_destroy(obj); |
4432 | ||
07fe0b12 | 4433 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4434 | int ret; |
4435 | ||
4436 | vma->pin_count = 0; | |
4437 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4438 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4439 | bool was_interruptible; | |
1488fc08 | 4440 | |
07fe0b12 BW |
4441 | was_interruptible = dev_priv->mm.interruptible; |
4442 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4443 | |
07fe0b12 | 4444 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4445 | |
07fe0b12 BW |
4446 | dev_priv->mm.interruptible = was_interruptible; |
4447 | } | |
1488fc08 CW |
4448 | } |
4449 | ||
1d64ae71 BW |
4450 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4451 | * before progressing. */ | |
4452 | if (obj->stolen) | |
4453 | i915_gem_object_unpin_pages(obj); | |
4454 | ||
a071fa00 DV |
4455 | WARN_ON(obj->frontbuffer_bits); |
4456 | ||
656bfa3a DV |
4457 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4458 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4459 | obj->tiling_mode != I915_TILING_NONE) | |
4460 | i915_gem_object_unpin_pages(obj); | |
4461 | ||
401c29f6 BW |
4462 | if (WARN_ON(obj->pages_pin_count)) |
4463 | obj->pages_pin_count = 0; | |
340fbd8c | 4464 | if (discard_backing_storage(obj)) |
5537252b | 4465 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4466 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4467 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4468 | |
9da3da66 CW |
4469 | BUG_ON(obj->pages); |
4470 | ||
2f745ad3 CW |
4471 | if (obj->base.import_attach) |
4472 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4473 | |
5cc9ed4b CW |
4474 | if (obj->ops->release) |
4475 | obj->ops->release(obj); | |
4476 | ||
05394f39 CW |
4477 | drm_gem_object_release(&obj->base); |
4478 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4479 | |
05394f39 | 4480 | kfree(obj->bit_17); |
42dcedd4 | 4481 | i915_gem_object_free(obj); |
f65c9168 PZ |
4482 | |
4483 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4484 | } |
4485 | ||
ec7adb6e JL |
4486 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4487 | struct i915_address_space *vm) | |
e656a6cb DV |
4488 | { |
4489 | struct i915_vma *vma; | |
ec7adb6e | 4490 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
1b683729 TU |
4491 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4492 | vma->vm == vm) | |
e656a6cb | 4493 | return vma; |
ec7adb6e JL |
4494 | } |
4495 | return NULL; | |
4496 | } | |
4497 | ||
4498 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4499 | const struct i915_ggtt_view *view) | |
4500 | { | |
4501 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); | |
4502 | struct i915_vma *vma; | |
e656a6cb | 4503 | |
ec7adb6e JL |
4504 | if (WARN_ONCE(!view, "no view specified")) |
4505 | return ERR_PTR(-EINVAL); | |
4506 | ||
4507 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
9abc4648 JL |
4508 | if (vma->vm == ggtt && |
4509 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e | 4510 | return vma; |
e656a6cb DV |
4511 | return NULL; |
4512 | } | |
4513 | ||
2f633156 BW |
4514 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4515 | { | |
b9d06dd9 | 4516 | struct i915_address_space *vm = NULL; |
2f633156 | 4517 | WARN_ON(vma->node.allocated); |
aaa05667 CW |
4518 | |
4519 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4520 | if (!list_empty(&vma->exec_list)) | |
4521 | return; | |
4522 | ||
b9d06dd9 | 4523 | vm = vma->vm; |
b9d06dd9 | 4524 | |
841cd773 DV |
4525 | if (!i915_is_ggtt(vm)) |
4526 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 4527 | |
8b9c2b94 | 4528 | list_del(&vma->vma_link); |
b93dab6e | 4529 | |
e20d2ab7 | 4530 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
2f633156 BW |
4531 | } |
4532 | ||
e3efda49 CW |
4533 | static void |
4534 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4535 | { | |
4536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4537 | struct intel_engine_cs *ring; |
e3efda49 CW |
4538 | int i; |
4539 | ||
4540 | for_each_ring(ring, dev_priv, i) | |
a83014d3 | 4541 | dev_priv->gt.stop_ring(ring); |
e3efda49 CW |
4542 | } |
4543 | ||
29105ccc | 4544 | int |
45c5f202 | 4545 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4546 | { |
3e31c6c0 | 4547 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4548 | int ret = 0; |
28dfe52a | 4549 | |
45c5f202 | 4550 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4551 | ret = i915_gpu_idle(dev); |
f7403347 | 4552 | if (ret) |
45c5f202 | 4553 | goto err; |
f7403347 | 4554 | |
b2da9fe5 | 4555 | i915_gem_retire_requests(dev); |
673a394b | 4556 | |
e3efda49 | 4557 | i915_gem_stop_ringbuffers(dev); |
45c5f202 CW |
4558 | mutex_unlock(&dev->struct_mutex); |
4559 | ||
737b1506 | 4560 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
29105ccc | 4561 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4562 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4563 | |
bdcf120b CW |
4564 | /* Assert that we sucessfully flushed all the work and |
4565 | * reset the GPU back to its idle, low power state. | |
4566 | */ | |
4567 | WARN_ON(dev_priv->mm.busy); | |
4568 | ||
673a394b | 4569 | return 0; |
45c5f202 CW |
4570 | |
4571 | err: | |
4572 | mutex_unlock(&dev->struct_mutex); | |
4573 | return ret; | |
673a394b EA |
4574 | } |
4575 | ||
6909a666 | 4576 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) |
b9524a1e | 4577 | { |
6909a666 | 4578 | struct intel_engine_cs *ring = req->ring; |
c3787e2e | 4579 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4580 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4581 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
c3787e2e | 4582 | int i, ret; |
b9524a1e | 4583 | |
040d2baa | 4584 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4585 | return 0; |
b9524a1e | 4586 | |
5fb9de1a | 4587 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); |
c3787e2e BW |
4588 | if (ret) |
4589 | return ret; | |
b9524a1e | 4590 | |
c3787e2e BW |
4591 | /* |
4592 | * Note: We do not worry about the concurrent register cacheline hang | |
4593 | * here because no other code should access these registers other than | |
4594 | * at initialization time. | |
4595 | */ | |
6fa1c5f1 | 4596 | for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { |
c3787e2e | 4597 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 4598 | intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i)); |
6fa1c5f1 | 4599 | intel_ring_emit(ring, remap_info[i]); |
b9524a1e BW |
4600 | } |
4601 | ||
c3787e2e | 4602 | intel_ring_advance(ring); |
b9524a1e | 4603 | |
c3787e2e | 4604 | return ret; |
b9524a1e BW |
4605 | } |
4606 | ||
f691e2f4 DV |
4607 | void i915_gem_init_swizzling(struct drm_device *dev) |
4608 | { | |
3e31c6c0 | 4609 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4610 | |
11782b02 | 4611 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4612 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4613 | return; | |
4614 | ||
4615 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4616 | DISP_TILE_SURFACE_SWIZZLING); | |
4617 | ||
11782b02 DV |
4618 | if (IS_GEN5(dev)) |
4619 | return; | |
4620 | ||
f691e2f4 DV |
4621 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4622 | if (IS_GEN6(dev)) | |
6b26c86d | 4623 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4624 | else if (IS_GEN7(dev)) |
6b26c86d | 4625 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4626 | else if (IS_GEN8(dev)) |
4627 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4628 | else |
4629 | BUG(); | |
f691e2f4 | 4630 | } |
e21af88d | 4631 | |
81e7f200 VS |
4632 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4633 | { | |
4634 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4635 | ||
4636 | I915_WRITE(RING_CTL(base), 0); | |
4637 | I915_WRITE(RING_HEAD(base), 0); | |
4638 | I915_WRITE(RING_TAIL(base), 0); | |
4639 | I915_WRITE(RING_START(base), 0); | |
4640 | } | |
4641 | ||
4642 | static void init_unused_rings(struct drm_device *dev) | |
4643 | { | |
4644 | if (IS_I830(dev)) { | |
4645 | init_unused_ring(dev, PRB1_BASE); | |
4646 | init_unused_ring(dev, SRB0_BASE); | |
4647 | init_unused_ring(dev, SRB1_BASE); | |
4648 | init_unused_ring(dev, SRB2_BASE); | |
4649 | init_unused_ring(dev, SRB3_BASE); | |
4650 | } else if (IS_GEN2(dev)) { | |
4651 | init_unused_ring(dev, SRB0_BASE); | |
4652 | init_unused_ring(dev, SRB1_BASE); | |
4653 | } else if (IS_GEN3(dev)) { | |
4654 | init_unused_ring(dev, PRB1_BASE); | |
4655 | init_unused_ring(dev, PRB2_BASE); | |
4656 | } | |
4657 | } | |
4658 | ||
a83014d3 | 4659 | int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4660 | { |
4fc7c971 | 4661 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4662 | int ret; |
68f95ba9 | 4663 | |
5c1143bb | 4664 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4665 | if (ret) |
b6913e4b | 4666 | return ret; |
68f95ba9 CW |
4667 | |
4668 | if (HAS_BSD(dev)) { | |
5c1143bb | 4669 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4670 | if (ret) |
4671 | goto cleanup_render_ring; | |
d1b851fc | 4672 | } |
68f95ba9 | 4673 | |
d39398f5 | 4674 | if (HAS_BLT(dev)) { |
549f7365 CW |
4675 | ret = intel_init_blt_ring_buffer(dev); |
4676 | if (ret) | |
4677 | goto cleanup_bsd_ring; | |
4678 | } | |
4679 | ||
9a8a2213 BW |
4680 | if (HAS_VEBOX(dev)) { |
4681 | ret = intel_init_vebox_ring_buffer(dev); | |
4682 | if (ret) | |
4683 | goto cleanup_blt_ring; | |
4684 | } | |
4685 | ||
845f74a7 ZY |
4686 | if (HAS_BSD2(dev)) { |
4687 | ret = intel_init_bsd2_ring_buffer(dev); | |
4688 | if (ret) | |
4689 | goto cleanup_vebox_ring; | |
4690 | } | |
9a8a2213 | 4691 | |
4fc7c971 BW |
4692 | return 0; |
4693 | ||
9a8a2213 BW |
4694 | cleanup_vebox_ring: |
4695 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4696 | cleanup_blt_ring: |
4697 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4698 | cleanup_bsd_ring: | |
4699 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4700 | cleanup_render_ring: | |
4701 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4702 | ||
4703 | return ret; | |
4704 | } | |
4705 | ||
4706 | int | |
4707 | i915_gem_init_hw(struct drm_device *dev) | |
4708 | { | |
3e31c6c0 | 4709 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a57ffb | 4710 | struct intel_engine_cs *ring; |
4ad2fd88 | 4711 | int ret, i, j; |
4fc7c971 BW |
4712 | |
4713 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4714 | return -EIO; | |
4715 | ||
5e4f5189 CW |
4716 | /* Double layer security blanket, see i915_gem_init() */ |
4717 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4718 | ||
59124506 | 4719 | if (dev_priv->ellc_size) |
05e21cc4 | 4720 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4721 | |
0bf21347 VS |
4722 | if (IS_HASWELL(dev)) |
4723 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4724 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4725 | |
88a2b2a3 | 4726 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4727 | if (IS_IVYBRIDGE(dev)) { |
4728 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4729 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4730 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4731 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4732 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4733 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4734 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4735 | } | |
88a2b2a3 BW |
4736 | } |
4737 | ||
4fc7c971 BW |
4738 | i915_gem_init_swizzling(dev); |
4739 | ||
d5abdfda DV |
4740 | /* |
4741 | * At least 830 can leave some of the unused rings | |
4742 | * "active" (ie. head != tail) after resume which | |
4743 | * will prevent c3 entry. Makes sure all unused rings | |
4744 | * are totally idle. | |
4745 | */ | |
4746 | init_unused_rings(dev); | |
4747 | ||
90638cc1 JH |
4748 | BUG_ON(!dev_priv->ring[RCS].default_context); |
4749 | ||
4ad2fd88 JH |
4750 | ret = i915_ppgtt_init_hw(dev); |
4751 | if (ret) { | |
4752 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4753 | goto out; | |
4754 | } | |
4755 | ||
4756 | /* Need to do basic initialisation of all rings first: */ | |
35a57ffb DV |
4757 | for_each_ring(ring, dev_priv, i) { |
4758 | ret = ring->init_hw(ring); | |
4759 | if (ret) | |
5e4f5189 | 4760 | goto out; |
35a57ffb | 4761 | } |
99433931 | 4762 | |
33a732f4 | 4763 | /* We can't enable contexts until all firmware is loaded */ |
87bcdd2e JB |
4764 | if (HAS_GUC_UCODE(dev)) { |
4765 | ret = intel_guc_ucode_load(dev); | |
4766 | if (ret) { | |
9f9e539f DV |
4767 | DRM_ERROR("Failed to initialize GuC, error %d\n", ret); |
4768 | ret = -EIO; | |
4769 | goto out; | |
87bcdd2e | 4770 | } |
33a732f4 AD |
4771 | } |
4772 | ||
e84fe803 NH |
4773 | /* |
4774 | * Increment the next seqno by 0x100 so we have a visible break | |
4775 | * on re-initialisation | |
4776 | */ | |
4777 | ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100); | |
4778 | if (ret) | |
4779 | goto out; | |
4780 | ||
4ad2fd88 JH |
4781 | /* Now it is safe to go back round and do everything else: */ |
4782 | for_each_ring(ring, dev_priv, i) { | |
dc4be607 JH |
4783 | struct drm_i915_gem_request *req; |
4784 | ||
90638cc1 JH |
4785 | WARN_ON(!ring->default_context); |
4786 | ||
dc4be607 JH |
4787 | ret = i915_gem_request_alloc(ring, ring->default_context, &req); |
4788 | if (ret) { | |
4789 | i915_gem_cleanup_ringbuffer(dev); | |
4790 | goto out; | |
4791 | } | |
4792 | ||
4ad2fd88 JH |
4793 | if (ring->id == RCS) { |
4794 | for (j = 0; j < NUM_L3_SLICES(dev); j++) | |
6909a666 | 4795 | i915_gem_l3_remap(req, j); |
4ad2fd88 | 4796 | } |
c3787e2e | 4797 | |
b3dd6b96 | 4798 | ret = i915_ppgtt_init_ring(req); |
4ad2fd88 JH |
4799 | if (ret && ret != -EIO) { |
4800 | DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret); | |
dc4be607 | 4801 | i915_gem_request_cancel(req); |
4ad2fd88 JH |
4802 | i915_gem_cleanup_ringbuffer(dev); |
4803 | goto out; | |
4804 | } | |
82460d97 | 4805 | |
b3dd6b96 | 4806 | ret = i915_gem_context_enable(req); |
90638cc1 JH |
4807 | if (ret && ret != -EIO) { |
4808 | DRM_ERROR("Context enable ring #%d failed %d\n", i, ret); | |
dc4be607 | 4809 | i915_gem_request_cancel(req); |
90638cc1 JH |
4810 | i915_gem_cleanup_ringbuffer(dev); |
4811 | goto out; | |
4812 | } | |
dc4be607 | 4813 | |
75289874 | 4814 | i915_add_request_no_flush(req); |
b7c36d25 | 4815 | } |
e21af88d | 4816 | |
5e4f5189 CW |
4817 | out: |
4818 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4819 | return ret; |
8187a2b7 ZN |
4820 | } |
4821 | ||
1070a42b CW |
4822 | int i915_gem_init(struct drm_device *dev) |
4823 | { | |
4824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4825 | int ret; |
4826 | ||
127f1003 OM |
4827 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4828 | i915.enable_execlists); | |
4829 | ||
1070a42b | 4830 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4831 | |
4832 | if (IS_VALLEYVIEW(dev)) { | |
4833 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4834 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4835 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4836 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4837 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4838 | } | |
4839 | ||
a83014d3 | 4840 | if (!i915.enable_execlists) { |
f3dc74c0 | 4841 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
a83014d3 OM |
4842 | dev_priv->gt.init_rings = i915_gem_init_rings; |
4843 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
4844 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
454afebd | 4845 | } else { |
f3dc74c0 | 4846 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
454afebd OM |
4847 | dev_priv->gt.init_rings = intel_logical_rings_init; |
4848 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
4849 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
a83014d3 OM |
4850 | } |
4851 | ||
5e4f5189 CW |
4852 | /* This is just a security blanket to placate dragons. |
4853 | * On some systems, we very sporadically observe that the first TLBs | |
4854 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4855 | * we hold the forcewake during initialisation these problems | |
4856 | * just magically go away. | |
4857 | */ | |
4858 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4859 | ||
6c5566a8 | 4860 | ret = i915_gem_init_userptr(dev); |
7bcc3777 JN |
4861 | if (ret) |
4862 | goto out_unlock; | |
6c5566a8 | 4863 | |
d7e5008f | 4864 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4865 | |
2fa48d8d | 4866 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4867 | if (ret) |
4868 | goto out_unlock; | |
2fa48d8d | 4869 | |
35a57ffb DV |
4870 | ret = dev_priv->gt.init_rings(dev); |
4871 | if (ret) | |
7bcc3777 | 4872 | goto out_unlock; |
2fa48d8d | 4873 | |
1070a42b | 4874 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4875 | if (ret == -EIO) { |
4876 | /* Allow ring initialisation to fail by marking the GPU as | |
4877 | * wedged. But we only want to do this where the GPU is angry, | |
4878 | * for all other failure, such as an allocation failure, bail. | |
4879 | */ | |
4880 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 4881 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 4882 | ret = 0; |
1070a42b | 4883 | } |
7bcc3777 JN |
4884 | |
4885 | out_unlock: | |
5e4f5189 | 4886 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4887 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4888 | |
60990320 | 4889 | return ret; |
1070a42b CW |
4890 | } |
4891 | ||
8187a2b7 ZN |
4892 | void |
4893 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4894 | { | |
3e31c6c0 | 4895 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4896 | struct intel_engine_cs *ring; |
1ec14ad3 | 4897 | int i; |
8187a2b7 | 4898 | |
b4519513 | 4899 | for_each_ring(ring, dev_priv, i) |
a83014d3 | 4900 | dev_priv->gt.cleanup_ring(ring); |
a647828a NB |
4901 | |
4902 | if (i915.enable_execlists) | |
4903 | /* | |
4904 | * Neither the BIOS, ourselves or any other kernel | |
4905 | * expects the system to be in execlists mode on startup, | |
4906 | * so we need to reset the GPU back to legacy mode. | |
4907 | */ | |
4908 | intel_gpu_reset(dev); | |
8187a2b7 ZN |
4909 | } |
4910 | ||
64193406 | 4911 | static void |
a4872ba6 | 4912 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4913 | { |
4914 | INIT_LIST_HEAD(&ring->active_list); | |
4915 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4916 | } |
4917 | ||
673a394b EA |
4918 | void |
4919 | i915_gem_load(struct drm_device *dev) | |
4920 | { | |
3e31c6c0 | 4921 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4922 | int i; |
4923 | ||
efab6d8d | 4924 | dev_priv->objects = |
42dcedd4 CW |
4925 | kmem_cache_create("i915_gem_object", |
4926 | sizeof(struct drm_i915_gem_object), 0, | |
4927 | SLAB_HWCACHE_ALIGN, | |
4928 | NULL); | |
e20d2ab7 CW |
4929 | dev_priv->vmas = |
4930 | kmem_cache_create("i915_gem_vma", | |
4931 | sizeof(struct i915_vma), 0, | |
4932 | SLAB_HWCACHE_ALIGN, | |
4933 | NULL); | |
efab6d8d CW |
4934 | dev_priv->requests = |
4935 | kmem_cache_create("i915_gem_request", | |
4936 | sizeof(struct drm_i915_gem_request), 0, | |
4937 | SLAB_HWCACHE_ALIGN, | |
4938 | NULL); | |
673a394b | 4939 | |
fc8c067e | 4940 | INIT_LIST_HEAD(&dev_priv->vm_list); |
a33afea5 | 4941 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4942 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4943 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4944 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4945 | for (i = 0; i < I915_NUM_RINGS; i++) |
4946 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4947 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4948 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4949 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4950 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4951 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4952 | i915_gem_idle_work_handler); | |
1f83fee0 | 4953 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4954 | |
72bfa19c CW |
4955 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4956 | ||
42b5aeab VS |
4957 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4958 | dev_priv->num_fence_regs = 32; | |
4959 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4960 | dev_priv->num_fence_regs = 16; |
4961 | else | |
4962 | dev_priv->num_fence_regs = 8; | |
4963 | ||
eb82289a YZ |
4964 | if (intel_vgpu_active(dev)) |
4965 | dev_priv->num_fence_regs = | |
4966 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4967 | ||
e84fe803 NH |
4968 | /* |
4969 | * Set initial sequence number for requests. | |
4970 | * Using this number allows the wraparound to happen early, | |
4971 | * catching any obvious problems. | |
4972 | */ | |
4973 | dev_priv->next_seqno = ((u32)~0 - 0x1100); | |
4974 | dev_priv->last_seqno = ((u32)~0 - 0x1101); | |
4975 | ||
b5aa8a0f | 4976 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4977 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4978 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4979 | |
673a394b | 4980 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4981 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4982 | |
ce453d81 CW |
4983 | dev_priv->mm.interruptible = true; |
4984 | ||
be6a0376 | 4985 | i915_gem_shrinker_init(dev_priv); |
f99d7069 DV |
4986 | |
4987 | mutex_init(&dev_priv->fb_tracking.lock); | |
673a394b | 4988 | } |
71acb5eb | 4989 | |
f787a5f5 | 4990 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4991 | { |
f787a5f5 | 4992 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4993 | |
4994 | /* Clean up our request list when the client is going away, so that | |
4995 | * later retire_requests won't dereference our soon-to-be-gone | |
4996 | * file_priv. | |
4997 | */ | |
1c25595f | 4998 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4999 | while (!list_empty(&file_priv->mm.request_list)) { |
5000 | struct drm_i915_gem_request *request; | |
5001 | ||
5002 | request = list_first_entry(&file_priv->mm.request_list, | |
5003 | struct drm_i915_gem_request, | |
5004 | client_list); | |
5005 | list_del(&request->client_list); | |
5006 | request->file_priv = NULL; | |
5007 | } | |
1c25595f | 5008 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 5009 | |
2e1b8730 | 5010 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 5011 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 5012 | list_del(&file_priv->rps.link); |
8d3afd7d | 5013 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 5014 | } |
b29c19b6 CW |
5015 | } |
5016 | ||
5017 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5018 | { | |
5019 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5020 | int ret; |
b29c19b6 CW |
5021 | |
5022 | DRM_DEBUG_DRIVER("\n"); | |
5023 | ||
5024 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5025 | if (!file_priv) | |
5026 | return -ENOMEM; | |
5027 | ||
5028 | file->driver_priv = file_priv; | |
5029 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5030 | file_priv->file = file; |
2e1b8730 | 5031 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
5032 | |
5033 | spin_lock_init(&file_priv->mm.lock); | |
5034 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5035 | |
e422b888 BW |
5036 | ret = i915_gem_context_open(dev, file); |
5037 | if (ret) | |
5038 | kfree(file_priv); | |
b29c19b6 | 5039 | |
e422b888 | 5040 | return ret; |
b29c19b6 CW |
5041 | } |
5042 | ||
b680c37a DV |
5043 | /** |
5044 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5045 | * @old: current GEM buffer for the frontbuffer slots |
5046 | * @new: new GEM buffer for the frontbuffer slots | |
5047 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5048 | * |
5049 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5050 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5051 | */ | |
a071fa00 DV |
5052 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5053 | struct drm_i915_gem_object *new, | |
5054 | unsigned frontbuffer_bits) | |
5055 | { | |
5056 | if (old) { | |
5057 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5058 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5059 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5060 | } | |
5061 | ||
5062 | if (new) { | |
5063 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5064 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5065 | new->frontbuffer_bits |= frontbuffer_bits; | |
5066 | } | |
5067 | } | |
5068 | ||
a70a3148 | 5069 | /* All the new VM stuff */ |
088e0df4 MT |
5070 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
5071 | struct i915_address_space *vm) | |
a70a3148 BW |
5072 | { |
5073 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5074 | struct i915_vma *vma; | |
5075 | ||
896ab1a5 | 5076 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5077 | |
a70a3148 | 5078 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
ec7adb6e JL |
5079 | if (i915_is_ggtt(vma->vm) && |
5080 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5081 | continue; | |
5082 | if (vma->vm == vm) | |
a70a3148 | 5083 | return vma->node.start; |
a70a3148 | 5084 | } |
ec7adb6e | 5085 | |
f25748ea DV |
5086 | WARN(1, "%s vma for this object not found.\n", |
5087 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5088 | return -1; |
5089 | } | |
5090 | ||
088e0df4 MT |
5091 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
5092 | const struct i915_ggtt_view *view) | |
a70a3148 | 5093 | { |
ec7adb6e | 5094 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); |
a70a3148 BW |
5095 | struct i915_vma *vma; |
5096 | ||
5097 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
9abc4648 JL |
5098 | if (vma->vm == ggtt && |
5099 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e JL |
5100 | return vma->node.start; |
5101 | ||
5678ad73 | 5102 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
5103 | return -1; |
5104 | } | |
5105 | ||
5106 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5107 | struct i915_address_space *vm) | |
5108 | { | |
5109 | struct i915_vma *vma; | |
5110 | ||
5111 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
5112 | if (i915_is_ggtt(vma->vm) && | |
5113 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5114 | continue; | |
5115 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
5116 | return true; | |
5117 | } | |
5118 | ||
5119 | return false; | |
5120 | } | |
5121 | ||
5122 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5123 | const struct i915_ggtt_view *view) |
ec7adb6e JL |
5124 | { |
5125 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); | |
5126 | struct i915_vma *vma; | |
5127 | ||
5128 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5129 | if (vma->vm == ggtt && | |
9abc4648 | 5130 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 5131 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5132 | return true; |
5133 | ||
5134 | return false; | |
5135 | } | |
5136 | ||
5137 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5138 | { | |
5a1d5eb0 | 5139 | struct i915_vma *vma; |
a70a3148 | 5140 | |
5a1d5eb0 CW |
5141 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5142 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5143 | return true; |
5144 | ||
5145 | return false; | |
5146 | } | |
5147 | ||
5148 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5149 | struct i915_address_space *vm) | |
5150 | { | |
5151 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5152 | struct i915_vma *vma; | |
5153 | ||
896ab1a5 | 5154 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5155 | |
5156 | BUG_ON(list_empty(&o->vma_list)); | |
5157 | ||
ec7adb6e JL |
5158 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
5159 | if (i915_is_ggtt(vma->vm) && | |
5160 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5161 | continue; | |
a70a3148 BW |
5162 | if (vma->vm == vm) |
5163 | return vma->node.size; | |
ec7adb6e | 5164 | } |
a70a3148 BW |
5165 | return 0; |
5166 | } | |
5167 | ||
ec7adb6e | 5168 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
5169 | { |
5170 | struct i915_vma *vma; | |
a6631ae1 | 5171 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
ec7adb6e JL |
5172 | if (vma->pin_count > 0) |
5173 | return true; | |
a6631ae1 | 5174 | |
ec7adb6e | 5175 | return false; |
5c2abbea | 5176 | } |
ea70299d DG |
5177 | |
5178 | /* Allocate a new GEM object and fill it with the supplied data */ | |
5179 | struct drm_i915_gem_object * | |
5180 | i915_gem_object_create_from_data(struct drm_device *dev, | |
5181 | const void *data, size_t size) | |
5182 | { | |
5183 | struct drm_i915_gem_object *obj; | |
5184 | struct sg_table *sg; | |
5185 | size_t bytes; | |
5186 | int ret; | |
5187 | ||
5188 | obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE)); | |
5189 | if (IS_ERR_OR_NULL(obj)) | |
5190 | return obj; | |
5191 | ||
5192 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
5193 | if (ret) | |
5194 | goto fail; | |
5195 | ||
5196 | ret = i915_gem_object_get_pages(obj); | |
5197 | if (ret) | |
5198 | goto fail; | |
5199 | ||
5200 | i915_gem_object_pin_pages(obj); | |
5201 | sg = obj->pages; | |
5202 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
5203 | i915_gem_object_unpin_pages(obj); | |
5204 | ||
5205 | if (WARN_ON(bytes != size)) { | |
5206 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
5207 | ret = -EFAULT; | |
5208 | goto fail; | |
5209 | } | |
5210 | ||
5211 | return obj; | |
5212 | ||
5213 | fail: | |
5214 | drm_gem_object_unreference(&obj->base); | |
5215 | return ERR_PTR(ret); | |
5216 | } |