Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 | 53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
920afa77 | 54 | unsigned alignment, bool mappable); |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
5cdf5881 CW |
61 | static int |
62 | i915_gem_object_get_pages(struct drm_gem_object *obj, | |
63 | gfp_t gfpmask); | |
64 | ||
65 | static void | |
66 | i915_gem_object_put_pages(struct drm_gem_object *obj); | |
67 | ||
31169714 CW |
68 | static LIST_HEAD(shrink_list); |
69 | static DEFINE_SPINLOCK(shrink_list_lock); | |
70 | ||
73aa808f CW |
71 | /* some bookkeeping */ |
72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
73 | size_t size) | |
74 | { | |
75 | dev_priv->mm.object_count++; | |
76 | dev_priv->mm.object_memory += size; | |
77 | } | |
78 | ||
79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
80 | size_t size) | |
81 | { | |
82 | dev_priv->mm.object_count--; | |
83 | dev_priv->mm.object_memory -= size; | |
84 | } | |
85 | ||
86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
87 | size_t size) | |
88 | { | |
89 | dev_priv->mm.gtt_count++; | |
90 | dev_priv->mm.gtt_memory += size; | |
91 | } | |
92 | ||
93 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
96 | dev_priv->mm.gtt_count--; | |
97 | dev_priv->mm.gtt_memory -= size; | |
98 | } | |
99 | ||
100 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
101 | size_t size) | |
102 | { | |
103 | dev_priv->mm.pin_count++; | |
104 | dev_priv->mm.pin_memory += size; | |
105 | } | |
106 | ||
107 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
108 | size_t size) | |
109 | { | |
110 | dev_priv->mm.pin_count--; | |
111 | dev_priv->mm.pin_memory -= size; | |
112 | } | |
113 | ||
30dbf0c0 CW |
114 | int |
115 | i915_gem_check_is_wedged(struct drm_device *dev) | |
116 | { | |
117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
118 | struct completion *x = &dev_priv->error_completion; | |
119 | unsigned long flags; | |
120 | int ret; | |
121 | ||
122 | if (!atomic_read(&dev_priv->mm.wedged)) | |
123 | return 0; | |
124 | ||
125 | ret = wait_for_completion_interruptible(x); | |
126 | if (ret) | |
127 | return ret; | |
128 | ||
129 | /* Success, we reset the GPU! */ | |
130 | if (!atomic_read(&dev_priv->mm.wedged)) | |
131 | return 0; | |
132 | ||
133 | /* GPU is hung, bump the completion count to account for | |
134 | * the token we just consumed so that we never hit zero and | |
135 | * end up waiting upon a subsequent completion event that | |
136 | * will never happen. | |
137 | */ | |
138 | spin_lock_irqsave(&x->wait.lock, flags); | |
139 | x->done++; | |
140 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
141 | return -EIO; | |
142 | } | |
143 | ||
76c1dec1 CW |
144 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
145 | { | |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | int ret; | |
148 | ||
149 | ret = i915_gem_check_is_wedged(dev); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
153 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
154 | if (ret) | |
155 | return ret; | |
156 | ||
157 | if (atomic_read(&dev_priv->mm.wedged)) { | |
158 | mutex_unlock(&dev->struct_mutex); | |
159 | return -EAGAIN; | |
160 | } | |
161 | ||
23bc5982 | 162 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
163 | return 0; |
164 | } | |
30dbf0c0 | 165 | |
7d1c4804 CW |
166 | static inline bool |
167 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
168 | { | |
169 | return obj_priv->gtt_space && | |
170 | !obj_priv->active && | |
171 | obj_priv->pin_count == 0; | |
172 | } | |
173 | ||
73aa808f CW |
174 | int i915_gem_do_init(struct drm_device *dev, |
175 | unsigned long start, | |
53984635 | 176 | unsigned long mappable_end, |
79e53945 | 177 | unsigned long end) |
673a394b EA |
178 | { |
179 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 180 | |
79e53945 JB |
181 | if (start >= end || |
182 | (start & (PAGE_SIZE - 1)) != 0 || | |
183 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
184 | return -EINVAL; |
185 | } | |
186 | ||
79e53945 JB |
187 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
188 | end - start); | |
673a394b | 189 | |
73aa808f | 190 | dev_priv->mm.gtt_total = end - start; |
53984635 | 191 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 JB |
192 | |
193 | return 0; | |
194 | } | |
673a394b | 195 | |
79e53945 JB |
196 | int |
197 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
198 | struct drm_file *file_priv) | |
199 | { | |
200 | struct drm_i915_gem_init *args = data; | |
201 | int ret; | |
202 | ||
203 | mutex_lock(&dev->struct_mutex); | |
53984635 | 204 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
205 | mutex_unlock(&dev->struct_mutex); |
206 | ||
79e53945 | 207 | return ret; |
673a394b EA |
208 | } |
209 | ||
5a125c3c EA |
210 | int |
211 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
212 | struct drm_file *file_priv) | |
213 | { | |
73aa808f | 214 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 215 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
216 | |
217 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
218 | return -ENODEV; | |
219 | ||
73aa808f CW |
220 | mutex_lock(&dev->struct_mutex); |
221 | args->aper_size = dev_priv->mm.gtt_total; | |
222 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
223 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
224 | |
225 | return 0; | |
226 | } | |
227 | ||
673a394b EA |
228 | |
229 | /** | |
230 | * Creates a new mm object and returns a handle to it. | |
231 | */ | |
232 | int | |
233 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
234 | struct drm_file *file_priv) | |
235 | { | |
236 | struct drm_i915_gem_create *args = data; | |
237 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
238 | int ret; |
239 | u32 handle; | |
673a394b EA |
240 | |
241 | args->size = roundup(args->size, PAGE_SIZE); | |
242 | ||
243 | /* Allocate the new object */ | |
ac52bc56 | 244 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
245 | if (obj == NULL) |
246 | return -ENOMEM; | |
247 | ||
248 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 249 | if (ret) { |
202f2fef CW |
250 | drm_gem_object_release(obj); |
251 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
252 | kfree(obj); | |
673a394b | 253 | return ret; |
1dfd9754 | 254 | } |
673a394b | 255 | |
202f2fef CW |
256 | /* drop reference from allocate - handle holds it now */ |
257 | drm_gem_object_unreference(obj); | |
258 | trace_i915_gem_object_create(obj); | |
259 | ||
1dfd9754 | 260 | args->handle = handle; |
673a394b EA |
261 | return 0; |
262 | } | |
263 | ||
16e809ac DV |
264 | static bool |
265 | i915_gem_object_cpu_accessible(struct drm_i915_gem_object *obj) | |
266 | { | |
267 | struct drm_device *dev = obj->base.dev; | |
268 | drm_i915_private_t *dev_priv = dev->dev_private; | |
269 | ||
270 | return obj->gtt_space == NULL || | |
271 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; | |
272 | } | |
273 | ||
eb01459f EA |
274 | static inline int |
275 | fast_shmem_read(struct page **pages, | |
276 | loff_t page_base, int page_offset, | |
277 | char __user *data, | |
278 | int length) | |
279 | { | |
b5e4feb6 | 280 | char *vaddr; |
4f27b75d | 281 | int ret; |
eb01459f | 282 | |
3e4d3af5 | 283 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
4f27b75d | 284 | ret = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
3e4d3af5 | 285 | kunmap_atomic(vaddr); |
eb01459f | 286 | |
4f27b75d | 287 | return ret; |
eb01459f EA |
288 | } |
289 | ||
280b713b EA |
290 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
291 | { | |
292 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 293 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
294 | |
295 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
296 | obj_priv->tiling_mode != I915_TILING_NONE; | |
297 | } | |
298 | ||
99a03df5 | 299 | static inline void |
40123c1f EA |
300 | slow_shmem_copy(struct page *dst_page, |
301 | int dst_offset, | |
302 | struct page *src_page, | |
303 | int src_offset, | |
304 | int length) | |
305 | { | |
306 | char *dst_vaddr, *src_vaddr; | |
307 | ||
99a03df5 CW |
308 | dst_vaddr = kmap(dst_page); |
309 | src_vaddr = kmap(src_page); | |
40123c1f EA |
310 | |
311 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
312 | ||
99a03df5 CW |
313 | kunmap(src_page); |
314 | kunmap(dst_page); | |
40123c1f EA |
315 | } |
316 | ||
99a03df5 | 317 | static inline void |
280b713b EA |
318 | slow_shmem_bit17_copy(struct page *gpu_page, |
319 | int gpu_offset, | |
320 | struct page *cpu_page, | |
321 | int cpu_offset, | |
322 | int length, | |
323 | int is_read) | |
324 | { | |
325 | char *gpu_vaddr, *cpu_vaddr; | |
326 | ||
327 | /* Use the unswizzled path if this page isn't affected. */ | |
328 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
329 | if (is_read) | |
330 | return slow_shmem_copy(cpu_page, cpu_offset, | |
331 | gpu_page, gpu_offset, length); | |
332 | else | |
333 | return slow_shmem_copy(gpu_page, gpu_offset, | |
334 | cpu_page, cpu_offset, length); | |
335 | } | |
336 | ||
99a03df5 CW |
337 | gpu_vaddr = kmap(gpu_page); |
338 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
339 | |
340 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
341 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
342 | */ | |
343 | while (length > 0) { | |
344 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
345 | int this_length = min(cacheline_end - gpu_offset, length); | |
346 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
347 | ||
348 | if (is_read) { | |
349 | memcpy(cpu_vaddr + cpu_offset, | |
350 | gpu_vaddr + swizzled_gpu_offset, | |
351 | this_length); | |
352 | } else { | |
353 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
354 | cpu_vaddr + cpu_offset, | |
355 | this_length); | |
356 | } | |
357 | cpu_offset += this_length; | |
358 | gpu_offset += this_length; | |
359 | length -= this_length; | |
360 | } | |
361 | ||
99a03df5 CW |
362 | kunmap(cpu_page); |
363 | kunmap(gpu_page); | |
280b713b EA |
364 | } |
365 | ||
eb01459f EA |
366 | /** |
367 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
368 | * from the backing pages of the object to the user's address space. On a | |
369 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
370 | */ | |
371 | static int | |
372 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
373 | struct drm_i915_gem_pread *args, | |
374 | struct drm_file *file_priv) | |
375 | { | |
23010e43 | 376 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
377 | ssize_t remain; |
378 | loff_t offset, page_base; | |
379 | char __user *user_data; | |
380 | int page_offset, page_length; | |
eb01459f EA |
381 | |
382 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
383 | remain = args->size; | |
384 | ||
23010e43 | 385 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
386 | offset = args->offset; |
387 | ||
388 | while (remain > 0) { | |
389 | /* Operation in this page | |
390 | * | |
391 | * page_base = page offset within aperture | |
392 | * page_offset = offset within page | |
393 | * page_length = bytes to copy for this page | |
394 | */ | |
395 | page_base = (offset & ~(PAGE_SIZE-1)); | |
396 | page_offset = offset & (PAGE_SIZE-1); | |
397 | page_length = remain; | |
398 | if ((page_offset + remain) > PAGE_SIZE) | |
399 | page_length = PAGE_SIZE - page_offset; | |
400 | ||
4f27b75d CW |
401 | if (fast_shmem_read(obj_priv->pages, |
402 | page_base, page_offset, | |
403 | user_data, page_length)) | |
404 | return -EFAULT; | |
eb01459f EA |
405 | |
406 | remain -= page_length; | |
407 | user_data += page_length; | |
408 | offset += page_length; | |
409 | } | |
410 | ||
4f27b75d | 411 | return 0; |
eb01459f EA |
412 | } |
413 | ||
07f73f69 CW |
414 | static int |
415 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
416 | { | |
417 | int ret; | |
418 | ||
4bdadb97 | 419 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
420 | |
421 | /* If we've insufficient memory to map in the pages, attempt | |
422 | * to make some space by throwing out some old buffers. | |
423 | */ | |
424 | if (ret == -ENOMEM) { | |
425 | struct drm_device *dev = obj->dev; | |
07f73f69 | 426 | |
0108a3ed | 427 | ret = i915_gem_evict_something(dev, obj->size, |
a6e0aa42 DV |
428 | i915_gem_get_gtt_alignment(obj), |
429 | false); | |
07f73f69 CW |
430 | if (ret) |
431 | return ret; | |
432 | ||
4bdadb97 | 433 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
434 | } |
435 | ||
436 | return ret; | |
437 | } | |
438 | ||
eb01459f EA |
439 | /** |
440 | * This is the fallback shmem pread path, which allocates temporary storage | |
441 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
442 | * can copy out of the object's backing pages while holding the struct mutex | |
443 | * and not take page faults. | |
444 | */ | |
445 | static int | |
446 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
447 | struct drm_i915_gem_pread *args, | |
448 | struct drm_file *file_priv) | |
449 | { | |
23010e43 | 450 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
451 | struct mm_struct *mm = current->mm; |
452 | struct page **user_pages; | |
453 | ssize_t remain; | |
454 | loff_t offset, pinned_pages, i; | |
455 | loff_t first_data_page, last_data_page, num_pages; | |
456 | int shmem_page_index, shmem_page_offset; | |
457 | int data_page_index, data_page_offset; | |
458 | int page_length; | |
459 | int ret; | |
460 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 461 | int do_bit17_swizzling; |
eb01459f EA |
462 | |
463 | remain = args->size; | |
464 | ||
465 | /* Pin the user pages containing the data. We can't fault while | |
466 | * holding the struct mutex, yet we want to hold it while | |
467 | * dereferencing the user data. | |
468 | */ | |
469 | first_data_page = data_ptr / PAGE_SIZE; | |
470 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
471 | num_pages = last_data_page - first_data_page + 1; | |
472 | ||
4f27b75d | 473 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
474 | if (user_pages == NULL) |
475 | return -ENOMEM; | |
476 | ||
4f27b75d | 477 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
478 | down_read(&mm->mmap_sem); |
479 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 480 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 481 | up_read(&mm->mmap_sem); |
4f27b75d | 482 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
483 | if (pinned_pages < num_pages) { |
484 | ret = -EFAULT; | |
4f27b75d | 485 | goto out; |
eb01459f EA |
486 | } |
487 | ||
4f27b75d CW |
488 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
489 | args->offset, | |
490 | args->size); | |
07f73f69 | 491 | if (ret) |
4f27b75d | 492 | goto out; |
eb01459f | 493 | |
4f27b75d | 494 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 495 | |
23010e43 | 496 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
497 | offset = args->offset; |
498 | ||
499 | while (remain > 0) { | |
500 | /* Operation in this page | |
501 | * | |
502 | * shmem_page_index = page number within shmem file | |
503 | * shmem_page_offset = offset within page in shmem file | |
504 | * data_page_index = page number in get_user_pages return | |
505 | * data_page_offset = offset with data_page_index page. | |
506 | * page_length = bytes to copy for this page | |
507 | */ | |
508 | shmem_page_index = offset / PAGE_SIZE; | |
509 | shmem_page_offset = offset & ~PAGE_MASK; | |
510 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
511 | data_page_offset = data_ptr & ~PAGE_MASK; | |
512 | ||
513 | page_length = remain; | |
514 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
515 | page_length = PAGE_SIZE - shmem_page_offset; | |
516 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
517 | page_length = PAGE_SIZE - data_page_offset; | |
518 | ||
280b713b | 519 | if (do_bit17_swizzling) { |
99a03df5 | 520 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 521 | shmem_page_offset, |
99a03df5 CW |
522 | user_pages[data_page_index], |
523 | data_page_offset, | |
524 | page_length, | |
525 | 1); | |
526 | } else { | |
527 | slow_shmem_copy(user_pages[data_page_index], | |
528 | data_page_offset, | |
529 | obj_priv->pages[shmem_page_index], | |
530 | shmem_page_offset, | |
531 | page_length); | |
280b713b | 532 | } |
eb01459f EA |
533 | |
534 | remain -= page_length; | |
535 | data_ptr += page_length; | |
536 | offset += page_length; | |
537 | } | |
538 | ||
4f27b75d | 539 | out: |
eb01459f EA |
540 | for (i = 0; i < pinned_pages; i++) { |
541 | SetPageDirty(user_pages[i]); | |
542 | page_cache_release(user_pages[i]); | |
543 | } | |
8e7d2b2c | 544 | drm_free_large(user_pages); |
eb01459f EA |
545 | |
546 | return ret; | |
547 | } | |
548 | ||
673a394b EA |
549 | /** |
550 | * Reads data from the object referenced by handle. | |
551 | * | |
552 | * On error, the contents of *data are undefined. | |
553 | */ | |
554 | int | |
555 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
556 | struct drm_file *file_priv) | |
557 | { | |
558 | struct drm_i915_gem_pread *args = data; | |
559 | struct drm_gem_object *obj; | |
560 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 561 | int ret = 0; |
673a394b | 562 | |
4f27b75d | 563 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 564 | if (ret) |
4f27b75d | 565 | return ret; |
673a394b EA |
566 | |
567 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1d7cfea1 CW |
568 | if (obj == NULL) { |
569 | ret = -ENOENT; | |
570 | goto unlock; | |
4f27b75d | 571 | } |
23010e43 | 572 | obj_priv = to_intel_bo(obj); |
673a394b | 573 | |
7dcd2499 CW |
574 | /* Bounds check source. */ |
575 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 576 | ret = -EINVAL; |
35b62a89 | 577 | goto out; |
ce9d419d CW |
578 | } |
579 | ||
35b62a89 CW |
580 | if (args->size == 0) |
581 | goto out; | |
582 | ||
ce9d419d CW |
583 | if (!access_ok(VERIFY_WRITE, |
584 | (char __user *)(uintptr_t)args->data_ptr, | |
585 | args->size)) { | |
586 | ret = -EFAULT; | |
35b62a89 | 587 | goto out; |
673a394b EA |
588 | } |
589 | ||
b5e4feb6 CW |
590 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
591 | args->size); | |
592 | if (ret) { | |
593 | ret = -EFAULT; | |
594 | goto out; | |
280b713b | 595 | } |
673a394b | 596 | |
4f27b75d CW |
597 | ret = i915_gem_object_get_pages_or_evict(obj); |
598 | if (ret) | |
599 | goto out; | |
600 | ||
601 | ret = i915_gem_object_set_cpu_read_domain_range(obj, | |
602 | args->offset, | |
603 | args->size); | |
604 | if (ret) | |
605 | goto out_put; | |
606 | ||
607 | ret = -EFAULT; | |
608 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
280b713b | 609 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
4f27b75d CW |
610 | if (ret == -EFAULT) |
611 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); | |
673a394b | 612 | |
4f27b75d CW |
613 | out_put: |
614 | i915_gem_object_put_pages(obj); | |
35b62a89 | 615 | out: |
4f27b75d | 616 | drm_gem_object_unreference(obj); |
1d7cfea1 | 617 | unlock: |
4f27b75d | 618 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 619 | return ret; |
673a394b EA |
620 | } |
621 | ||
0839ccb8 KP |
622 | /* This is the fast write path which cannot handle |
623 | * page faults in the source data | |
9b7530cc | 624 | */ |
0839ccb8 KP |
625 | |
626 | static inline int | |
627 | fast_user_write(struct io_mapping *mapping, | |
628 | loff_t page_base, int page_offset, | |
629 | char __user *user_data, | |
630 | int length) | |
9b7530cc | 631 | { |
9b7530cc | 632 | char *vaddr_atomic; |
0839ccb8 | 633 | unsigned long unwritten; |
9b7530cc | 634 | |
3e4d3af5 | 635 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
636 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
637 | user_data, length); | |
3e4d3af5 | 638 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 639 | return unwritten; |
0839ccb8 KP |
640 | } |
641 | ||
642 | /* Here's the write path which can sleep for | |
643 | * page faults | |
644 | */ | |
645 | ||
ab34c226 | 646 | static inline void |
3de09aa3 EA |
647 | slow_kernel_write(struct io_mapping *mapping, |
648 | loff_t gtt_base, int gtt_offset, | |
649 | struct page *user_page, int user_offset, | |
650 | int length) | |
0839ccb8 | 651 | { |
ab34c226 CW |
652 | char __iomem *dst_vaddr; |
653 | char *src_vaddr; | |
0839ccb8 | 654 | |
ab34c226 CW |
655 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
656 | src_vaddr = kmap(user_page); | |
657 | ||
658 | memcpy_toio(dst_vaddr + gtt_offset, | |
659 | src_vaddr + user_offset, | |
660 | length); | |
661 | ||
662 | kunmap(user_page); | |
663 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
664 | } |
665 | ||
40123c1f EA |
666 | static inline int |
667 | fast_shmem_write(struct page **pages, | |
668 | loff_t page_base, int page_offset, | |
669 | char __user *data, | |
670 | int length) | |
671 | { | |
b5e4feb6 | 672 | char *vaddr; |
fbd5a26d | 673 | int ret; |
40123c1f | 674 | |
3e4d3af5 | 675 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
fbd5a26d | 676 | ret = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
3e4d3af5 | 677 | kunmap_atomic(vaddr); |
40123c1f | 678 | |
fbd5a26d | 679 | return ret; |
40123c1f EA |
680 | } |
681 | ||
3de09aa3 EA |
682 | /** |
683 | * This is the fast pwrite path, where we copy the data directly from the | |
684 | * user into the GTT, uncached. | |
685 | */ | |
673a394b | 686 | static int |
3de09aa3 EA |
687 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
688 | struct drm_i915_gem_pwrite *args, | |
689 | struct drm_file *file_priv) | |
673a394b | 690 | { |
23010e43 | 691 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 692 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 693 | ssize_t remain; |
0839ccb8 | 694 | loff_t offset, page_base; |
673a394b | 695 | char __user *user_data; |
0839ccb8 | 696 | int page_offset, page_length; |
673a394b EA |
697 | |
698 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
699 | remain = args->size; | |
673a394b | 700 | |
23010e43 | 701 | obj_priv = to_intel_bo(obj); |
673a394b | 702 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
703 | |
704 | while (remain > 0) { | |
705 | /* Operation in this page | |
706 | * | |
0839ccb8 KP |
707 | * page_base = page offset within aperture |
708 | * page_offset = offset within page | |
709 | * page_length = bytes to copy for this page | |
673a394b | 710 | */ |
0839ccb8 KP |
711 | page_base = (offset & ~(PAGE_SIZE-1)); |
712 | page_offset = offset & (PAGE_SIZE-1); | |
713 | page_length = remain; | |
714 | if ((page_offset + remain) > PAGE_SIZE) | |
715 | page_length = PAGE_SIZE - page_offset; | |
716 | ||
0839ccb8 | 717 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
718 | * source page isn't available. Return the error and we'll |
719 | * retry in the slow path. | |
0839ccb8 | 720 | */ |
fbd5a26d CW |
721 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
722 | page_offset, user_data, page_length)) | |
723 | ||
724 | return -EFAULT; | |
673a394b | 725 | |
0839ccb8 KP |
726 | remain -= page_length; |
727 | user_data += page_length; | |
728 | offset += page_length; | |
673a394b | 729 | } |
673a394b | 730 | |
fbd5a26d | 731 | return 0; |
673a394b EA |
732 | } |
733 | ||
3de09aa3 EA |
734 | /** |
735 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
736 | * the memory and maps it using kmap_atomic for copying. | |
737 | * | |
738 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
739 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
740 | */ | |
3043c60c | 741 | static int |
3de09aa3 EA |
742 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
743 | struct drm_i915_gem_pwrite *args, | |
744 | struct drm_file *file_priv) | |
673a394b | 745 | { |
23010e43 | 746 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
747 | drm_i915_private_t *dev_priv = dev->dev_private; |
748 | ssize_t remain; | |
749 | loff_t gtt_page_base, offset; | |
750 | loff_t first_data_page, last_data_page, num_pages; | |
751 | loff_t pinned_pages, i; | |
752 | struct page **user_pages; | |
753 | struct mm_struct *mm = current->mm; | |
754 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 755 | int ret; |
3de09aa3 EA |
756 | uint64_t data_ptr = args->data_ptr; |
757 | ||
758 | remain = args->size; | |
759 | ||
760 | /* Pin the user pages containing the data. We can't fault while | |
761 | * holding the struct mutex, and all of the pwrite implementations | |
762 | * want to hold it while dereferencing the user data. | |
763 | */ | |
764 | first_data_page = data_ptr / PAGE_SIZE; | |
765 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
766 | num_pages = last_data_page - first_data_page + 1; | |
767 | ||
fbd5a26d | 768 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
769 | if (user_pages == NULL) |
770 | return -ENOMEM; | |
771 | ||
fbd5a26d | 772 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
773 | down_read(&mm->mmap_sem); |
774 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
775 | num_pages, 0, 0, user_pages, NULL); | |
776 | up_read(&mm->mmap_sem); | |
fbd5a26d | 777 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
778 | if (pinned_pages < num_pages) { |
779 | ret = -EFAULT; | |
780 | goto out_unpin_pages; | |
781 | } | |
673a394b | 782 | |
3de09aa3 EA |
783 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
784 | if (ret) | |
fbd5a26d | 785 | goto out_unpin_pages; |
3de09aa3 | 786 | |
23010e43 | 787 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
788 | offset = obj_priv->gtt_offset + args->offset; |
789 | ||
790 | while (remain > 0) { | |
791 | /* Operation in this page | |
792 | * | |
793 | * gtt_page_base = page offset within aperture | |
794 | * gtt_page_offset = offset within page in aperture | |
795 | * data_page_index = page number in get_user_pages return | |
796 | * data_page_offset = offset with data_page_index page. | |
797 | * page_length = bytes to copy for this page | |
798 | */ | |
799 | gtt_page_base = offset & PAGE_MASK; | |
800 | gtt_page_offset = offset & ~PAGE_MASK; | |
801 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
802 | data_page_offset = data_ptr & ~PAGE_MASK; | |
803 | ||
804 | page_length = remain; | |
805 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
806 | page_length = PAGE_SIZE - gtt_page_offset; | |
807 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
808 | page_length = PAGE_SIZE - data_page_offset; | |
809 | ||
ab34c226 CW |
810 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
811 | gtt_page_base, gtt_page_offset, | |
812 | user_pages[data_page_index], | |
813 | data_page_offset, | |
814 | page_length); | |
3de09aa3 EA |
815 | |
816 | remain -= page_length; | |
817 | offset += page_length; | |
818 | data_ptr += page_length; | |
819 | } | |
820 | ||
3de09aa3 EA |
821 | out_unpin_pages: |
822 | for (i = 0; i < pinned_pages; i++) | |
823 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 824 | drm_free_large(user_pages); |
3de09aa3 EA |
825 | |
826 | return ret; | |
827 | } | |
828 | ||
40123c1f EA |
829 | /** |
830 | * This is the fast shmem pwrite path, which attempts to directly | |
831 | * copy_from_user into the kmapped pages backing the object. | |
832 | */ | |
3043c60c | 833 | static int |
40123c1f EA |
834 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
835 | struct drm_i915_gem_pwrite *args, | |
836 | struct drm_file *file_priv) | |
673a394b | 837 | { |
23010e43 | 838 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
839 | ssize_t remain; |
840 | loff_t offset, page_base; | |
841 | char __user *user_data; | |
842 | int page_offset, page_length; | |
40123c1f EA |
843 | |
844 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
845 | remain = args->size; | |
673a394b | 846 | |
23010e43 | 847 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
848 | offset = args->offset; |
849 | obj_priv->dirty = 1; | |
850 | ||
851 | while (remain > 0) { | |
852 | /* Operation in this page | |
853 | * | |
854 | * page_base = page offset within aperture | |
855 | * page_offset = offset within page | |
856 | * page_length = bytes to copy for this page | |
857 | */ | |
858 | page_base = (offset & ~(PAGE_SIZE-1)); | |
859 | page_offset = offset & (PAGE_SIZE-1); | |
860 | page_length = remain; | |
861 | if ((page_offset + remain) > PAGE_SIZE) | |
862 | page_length = PAGE_SIZE - page_offset; | |
863 | ||
fbd5a26d | 864 | if (fast_shmem_write(obj_priv->pages, |
40123c1f | 865 | page_base, page_offset, |
fbd5a26d CW |
866 | user_data, page_length)) |
867 | return -EFAULT; | |
40123c1f EA |
868 | |
869 | remain -= page_length; | |
870 | user_data += page_length; | |
871 | offset += page_length; | |
872 | } | |
873 | ||
fbd5a26d | 874 | return 0; |
40123c1f EA |
875 | } |
876 | ||
877 | /** | |
878 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
879 | * the memory and maps it using kmap_atomic for copying. | |
880 | * | |
881 | * This avoids taking mmap_sem for faulting on the user's address while the | |
882 | * struct_mutex is held. | |
883 | */ | |
884 | static int | |
885 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
886 | struct drm_i915_gem_pwrite *args, | |
887 | struct drm_file *file_priv) | |
888 | { | |
23010e43 | 889 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
890 | struct mm_struct *mm = current->mm; |
891 | struct page **user_pages; | |
892 | ssize_t remain; | |
893 | loff_t offset, pinned_pages, i; | |
894 | loff_t first_data_page, last_data_page, num_pages; | |
895 | int shmem_page_index, shmem_page_offset; | |
896 | int data_page_index, data_page_offset; | |
897 | int page_length; | |
898 | int ret; | |
899 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 900 | int do_bit17_swizzling; |
40123c1f EA |
901 | |
902 | remain = args->size; | |
903 | ||
904 | /* Pin the user pages containing the data. We can't fault while | |
905 | * holding the struct mutex, and all of the pwrite implementations | |
906 | * want to hold it while dereferencing the user data. | |
907 | */ | |
908 | first_data_page = data_ptr / PAGE_SIZE; | |
909 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
910 | num_pages = last_data_page - first_data_page + 1; | |
911 | ||
4f27b75d | 912 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
913 | if (user_pages == NULL) |
914 | return -ENOMEM; | |
915 | ||
fbd5a26d | 916 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
917 | down_read(&mm->mmap_sem); |
918 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
919 | num_pages, 0, 0, user_pages, NULL); | |
920 | up_read(&mm->mmap_sem); | |
fbd5a26d | 921 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
922 | if (pinned_pages < num_pages) { |
923 | ret = -EFAULT; | |
fbd5a26d | 924 | goto out; |
673a394b EA |
925 | } |
926 | ||
fbd5a26d | 927 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 928 | if (ret) |
fbd5a26d | 929 | goto out; |
40123c1f | 930 | |
fbd5a26d | 931 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 932 | |
23010e43 | 933 | obj_priv = to_intel_bo(obj); |
673a394b | 934 | offset = args->offset; |
40123c1f | 935 | obj_priv->dirty = 1; |
673a394b | 936 | |
40123c1f EA |
937 | while (remain > 0) { |
938 | /* Operation in this page | |
939 | * | |
940 | * shmem_page_index = page number within shmem file | |
941 | * shmem_page_offset = offset within page in shmem file | |
942 | * data_page_index = page number in get_user_pages return | |
943 | * data_page_offset = offset with data_page_index page. | |
944 | * page_length = bytes to copy for this page | |
945 | */ | |
946 | shmem_page_index = offset / PAGE_SIZE; | |
947 | shmem_page_offset = offset & ~PAGE_MASK; | |
948 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
949 | data_page_offset = data_ptr & ~PAGE_MASK; | |
950 | ||
951 | page_length = remain; | |
952 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
953 | page_length = PAGE_SIZE - shmem_page_offset; | |
954 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
955 | page_length = PAGE_SIZE - data_page_offset; | |
956 | ||
280b713b | 957 | if (do_bit17_swizzling) { |
99a03df5 | 958 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
959 | shmem_page_offset, |
960 | user_pages[data_page_index], | |
961 | data_page_offset, | |
99a03df5 CW |
962 | page_length, |
963 | 0); | |
964 | } else { | |
965 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
966 | shmem_page_offset, | |
967 | user_pages[data_page_index], | |
968 | data_page_offset, | |
969 | page_length); | |
280b713b | 970 | } |
40123c1f EA |
971 | |
972 | remain -= page_length; | |
973 | data_ptr += page_length; | |
974 | offset += page_length; | |
673a394b EA |
975 | } |
976 | ||
fbd5a26d | 977 | out: |
40123c1f EA |
978 | for (i = 0; i < pinned_pages; i++) |
979 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 980 | drm_free_large(user_pages); |
673a394b | 981 | |
40123c1f | 982 | return ret; |
673a394b EA |
983 | } |
984 | ||
985 | /** | |
986 | * Writes data to the object referenced by handle. | |
987 | * | |
988 | * On error, the contents of the buffer that were to be modified are undefined. | |
989 | */ | |
990 | int | |
991 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 992 | struct drm_file *file) |
673a394b EA |
993 | { |
994 | struct drm_i915_gem_pwrite *args = data; | |
995 | struct drm_gem_object *obj; | |
996 | struct drm_i915_gem_object *obj_priv; | |
997 | int ret = 0; | |
998 | ||
fbd5a26d | 999 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1000 | if (ret) |
fbd5a26d | 1001 | return ret; |
1d7cfea1 CW |
1002 | |
1003 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
1004 | if (obj == NULL) { | |
1005 | ret = -ENOENT; | |
1006 | goto unlock; | |
fbd5a26d | 1007 | } |
23010e43 | 1008 | obj_priv = to_intel_bo(obj); |
673a394b | 1009 | |
fbd5a26d | 1010 | |
7dcd2499 CW |
1011 | /* Bounds check destination. */ |
1012 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1013 | ret = -EINVAL; |
35b62a89 | 1014 | goto out; |
ce9d419d CW |
1015 | } |
1016 | ||
35b62a89 CW |
1017 | if (args->size == 0) |
1018 | goto out; | |
1019 | ||
ce9d419d CW |
1020 | if (!access_ok(VERIFY_READ, |
1021 | (char __user *)(uintptr_t)args->data_ptr, | |
1022 | args->size)) { | |
1023 | ret = -EFAULT; | |
35b62a89 | 1024 | goto out; |
673a394b EA |
1025 | } |
1026 | ||
b5e4feb6 CW |
1027 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
1028 | args->size); | |
1029 | if (ret) { | |
1030 | ret = -EFAULT; | |
1031 | goto out; | |
673a394b EA |
1032 | } |
1033 | ||
1034 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1035 | * it would end up going through the fenced access, and we'll get | |
1036 | * different detiling behavior between reading and writing. | |
1037 | * pread/pwrite currently are reading and writing from the CPU | |
1038 | * perspective, requiring manual detiling by the client. | |
1039 | */ | |
71acb5eb | 1040 | if (obj_priv->phys_obj) |
fbd5a26d | 1041 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1042 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1043 | obj_priv->gtt_space && |
9b8c4a0b | 1044 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
920afa77 | 1045 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1046 | if (ret) |
1047 | goto out; | |
1048 | ||
1049 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1050 | if (ret) | |
1051 | goto out_unpin; | |
1052 | ||
1053 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1054 | if (ret == -EFAULT) | |
1055 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1056 | ||
1057 | out_unpin: | |
1058 | i915_gem_object_unpin(obj); | |
40123c1f | 1059 | } else { |
fbd5a26d CW |
1060 | ret = i915_gem_object_get_pages_or_evict(obj); |
1061 | if (ret) | |
1062 | goto out; | |
673a394b | 1063 | |
fbd5a26d CW |
1064 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1065 | if (ret) | |
1066 | goto out_put; | |
673a394b | 1067 | |
fbd5a26d CW |
1068 | ret = -EFAULT; |
1069 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1070 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1071 | if (ret == -EFAULT) | |
1072 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
1073 | ||
1074 | out_put: | |
1075 | i915_gem_object_put_pages(obj); | |
1076 | } | |
673a394b | 1077 | |
35b62a89 | 1078 | out: |
fbd5a26d | 1079 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1080 | unlock: |
fbd5a26d | 1081 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1082 | return ret; |
1083 | } | |
1084 | ||
1085 | /** | |
2ef7eeaa EA |
1086 | * Called when user space prepares to use an object with the CPU, either |
1087 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1088 | */ |
1089 | int | |
1090 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1091 | struct drm_file *file_priv) | |
1092 | { | |
a09ba7fa | 1093 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1094 | struct drm_i915_gem_set_domain *args = data; |
1095 | struct drm_gem_object *obj; | |
652c393a | 1096 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1097 | uint32_t read_domains = args->read_domains; |
1098 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1099 | int ret; |
1100 | ||
1101 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1102 | return -ENODEV; | |
1103 | ||
2ef7eeaa | 1104 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1105 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1106 | return -EINVAL; |
1107 | ||
21d509e3 | 1108 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1109 | return -EINVAL; |
1110 | ||
1111 | /* Having something in the write domain implies it's in the read | |
1112 | * domain, and only that read domain. Enforce that in the request. | |
1113 | */ | |
1114 | if (write_domain != 0 && read_domains != write_domain) | |
1115 | return -EINVAL; | |
1116 | ||
76c1dec1 | 1117 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1118 | if (ret) |
76c1dec1 | 1119 | return ret; |
1d7cfea1 | 1120 | |
673a394b | 1121 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1d7cfea1 CW |
1122 | if (obj == NULL) { |
1123 | ret = -ENOENT; | |
1124 | goto unlock; | |
76c1dec1 | 1125 | } |
23010e43 | 1126 | obj_priv = to_intel_bo(obj); |
673a394b | 1127 | |
652c393a JB |
1128 | intel_mark_busy(dev, obj); |
1129 | ||
2ef7eeaa EA |
1130 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1131 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1132 | |
a09ba7fa EA |
1133 | /* Update the LRU on the fence for the CPU access that's |
1134 | * about to occur. | |
1135 | */ | |
1136 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1137 | struct drm_i915_fence_reg *reg = |
1138 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1139 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1140 | &dev_priv->mm.fence_list); |
1141 | } | |
1142 | ||
02354392 EA |
1143 | /* Silently promote "you're not bound, there was nothing to do" |
1144 | * to success, since the client was just asking us to | |
1145 | * make sure everything was done. | |
1146 | */ | |
1147 | if (ret == -EINVAL) | |
1148 | ret = 0; | |
2ef7eeaa | 1149 | } else { |
e47c68e9 | 1150 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1151 | } |
1152 | ||
7d1c4804 CW |
1153 | /* Maintain LRU order of "inactive" objects */ |
1154 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
69dc4987 | 1155 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1156 | |
673a394b | 1157 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1158 | unlock: |
673a394b EA |
1159 | mutex_unlock(&dev->struct_mutex); |
1160 | return ret; | |
1161 | } | |
1162 | ||
1163 | /** | |
1164 | * Called when user space has done writes to this buffer | |
1165 | */ | |
1166 | int | |
1167 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1168 | struct drm_file *file_priv) | |
1169 | { | |
1170 | struct drm_i915_gem_sw_finish *args = data; | |
1171 | struct drm_gem_object *obj; | |
673a394b EA |
1172 | int ret = 0; |
1173 | ||
1174 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1175 | return -ENODEV; | |
1176 | ||
76c1dec1 | 1177 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1178 | if (ret) |
76c1dec1 | 1179 | return ret; |
1d7cfea1 | 1180 | |
673a394b EA |
1181 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1182 | if (obj == NULL) { | |
1d7cfea1 CW |
1183 | ret = -ENOENT; |
1184 | goto unlock; | |
673a394b EA |
1185 | } |
1186 | ||
673a394b | 1187 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1188 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1189 | i915_gem_object_flush_cpu_write_domain(obj); |
1190 | ||
673a394b | 1191 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1192 | unlock: |
673a394b EA |
1193 | mutex_unlock(&dev->struct_mutex); |
1194 | return ret; | |
1195 | } | |
1196 | ||
1197 | /** | |
1198 | * Maps the contents of an object, returning the address it is mapped | |
1199 | * into. | |
1200 | * | |
1201 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1202 | * imply a ref on the object itself. | |
1203 | */ | |
1204 | int | |
1205 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1206 | struct drm_file *file_priv) | |
1207 | { | |
1208 | struct drm_i915_gem_mmap *args = data; | |
1209 | struct drm_gem_object *obj; | |
1210 | loff_t offset; | |
1211 | unsigned long addr; | |
1212 | ||
1213 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1214 | return -ENODEV; | |
1215 | ||
1216 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1217 | if (obj == NULL) | |
bf79cb91 | 1218 | return -ENOENT; |
673a394b EA |
1219 | |
1220 | offset = args->offset; | |
1221 | ||
1222 | down_write(¤t->mm->mmap_sem); | |
1223 | addr = do_mmap(obj->filp, 0, args->size, | |
1224 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1225 | args->offset); | |
1226 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1227 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1228 | if (IS_ERR((void *)addr)) |
1229 | return addr; | |
1230 | ||
1231 | args->addr_ptr = (uint64_t) addr; | |
1232 | ||
1233 | return 0; | |
1234 | } | |
1235 | ||
de151cf6 JB |
1236 | /** |
1237 | * i915_gem_fault - fault a page into the GTT | |
1238 | * vma: VMA in question | |
1239 | * vmf: fault info | |
1240 | * | |
1241 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1242 | * from userspace. The fault handler takes care of binding the object to | |
1243 | * the GTT (if needed), allocating and programming a fence register (again, | |
1244 | * only if needed based on whether the old reg is still valid or the object | |
1245 | * is tiled) and inserting a new PTE into the faulting process. | |
1246 | * | |
1247 | * Note that the faulting process may involve evicting existing objects | |
1248 | * from the GTT and/or fence registers to make room. So performance may | |
1249 | * suffer if the GTT working set is large or there are few fence registers | |
1250 | * left. | |
1251 | */ | |
1252 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1253 | { | |
1254 | struct drm_gem_object *obj = vma->vm_private_data; | |
1255 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1256 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1257 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1258 | pgoff_t page_offset; |
1259 | unsigned long pfn; | |
1260 | int ret = 0; | |
0f973f27 | 1261 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1262 | |
1263 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1264 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1265 | PAGE_SHIFT; | |
1266 | ||
1267 | /* Now bind it into the GTT if needed */ | |
1268 | mutex_lock(&dev->struct_mutex); | |
16e809ac DV |
1269 | if (!i915_gem_object_cpu_accessible(obj_priv)) |
1270 | i915_gem_object_unbind(obj); | |
1271 | ||
de151cf6 | 1272 | if (!obj_priv->gtt_space) { |
920afa77 | 1273 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1274 | if (ret) |
1275 | goto unlock; | |
07f4f3e8 | 1276 | |
07f4f3e8 | 1277 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1278 | if (ret) |
1279 | goto unlock; | |
de151cf6 JB |
1280 | } |
1281 | ||
1282 | /* Need a new fence register? */ | |
a09ba7fa | 1283 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1284 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1285 | if (ret) |
1286 | goto unlock; | |
d9ddcb96 | 1287 | } |
de151cf6 | 1288 | |
7d1c4804 | 1289 | if (i915_gem_object_is_inactive(obj_priv)) |
69dc4987 | 1290 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1291 | |
de151cf6 JB |
1292 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1293 | page_offset; | |
1294 | ||
1295 | /* Finally, remap it using the new GTT offset */ | |
1296 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1297 | unlock: |
de151cf6 JB |
1298 | mutex_unlock(&dev->struct_mutex); |
1299 | ||
1300 | switch (ret) { | |
c715089f CW |
1301 | case 0: |
1302 | case -ERESTARTSYS: | |
1303 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1304 | case -ENOMEM: |
1305 | case -EAGAIN: | |
1306 | return VM_FAULT_OOM; | |
de151cf6 | 1307 | default: |
c715089f | 1308 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1309 | } |
1310 | } | |
1311 | ||
1312 | /** | |
1313 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1314 | * @obj: obj in question | |
1315 | * | |
1316 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1317 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1318 | * up the object based on the offset and sets up the various memory mapping | |
1319 | * structures. | |
1320 | * | |
1321 | * This routine allocates and attaches a fake offset for @obj. | |
1322 | */ | |
1323 | static int | |
1324 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1325 | { | |
1326 | struct drm_device *dev = obj->dev; | |
1327 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1328 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1329 | struct drm_map_list *list; |
f77d390c | 1330 | struct drm_local_map *map; |
de151cf6 JB |
1331 | int ret = 0; |
1332 | ||
1333 | /* Set the object up for mmap'ing */ | |
1334 | list = &obj->map_list; | |
9a298b2a | 1335 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1336 | if (!list->map) |
1337 | return -ENOMEM; | |
1338 | ||
1339 | map = list->map; | |
1340 | map->type = _DRM_GEM; | |
1341 | map->size = obj->size; | |
1342 | map->handle = obj; | |
1343 | ||
1344 | /* Get a DRM GEM mmap offset allocated... */ | |
1345 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1346 | obj->size / PAGE_SIZE, 0, 0); | |
1347 | if (!list->file_offset_node) { | |
1348 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1349 | ret = -ENOSPC; |
de151cf6 JB |
1350 | goto out_free_list; |
1351 | } | |
1352 | ||
1353 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1354 | obj->size / PAGE_SIZE, 0); | |
1355 | if (!list->file_offset_node) { | |
1356 | ret = -ENOMEM; | |
1357 | goto out_free_list; | |
1358 | } | |
1359 | ||
1360 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1361 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1362 | if (ret) { | |
de151cf6 JB |
1363 | DRM_ERROR("failed to add to map hash\n"); |
1364 | goto out_free_mm; | |
1365 | } | |
1366 | ||
1367 | /* By now we should be all set, any drm_mmap request on the offset | |
1368 | * below will get to our mmap & fault handler */ | |
1369 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1370 | ||
1371 | return 0; | |
1372 | ||
1373 | out_free_mm: | |
1374 | drm_mm_put_block(list->file_offset_node); | |
1375 | out_free_list: | |
9a298b2a | 1376 | kfree(list->map); |
de151cf6 JB |
1377 | |
1378 | return ret; | |
1379 | } | |
1380 | ||
901782b2 CW |
1381 | /** |
1382 | * i915_gem_release_mmap - remove physical page mappings | |
1383 | * @obj: obj in question | |
1384 | * | |
af901ca1 | 1385 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1386 | * relinquish ownership of the pages back to the system. |
1387 | * | |
1388 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1389 | * object through the GTT and then lose the fence register due to | |
1390 | * resource pressure. Similarly if the object has been moved out of the | |
1391 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1392 | * mapping will then trigger a page fault on the next user access, allowing | |
1393 | * fixup by i915_gem_fault(). | |
1394 | */ | |
d05ca301 | 1395 | void |
901782b2 CW |
1396 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1397 | { | |
1398 | struct drm_device *dev = obj->dev; | |
23010e43 | 1399 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1400 | |
1401 | if (dev->dev_mapping) | |
1402 | unmap_mapping_range(dev->dev_mapping, | |
1403 | obj_priv->mmap_offset, obj->size, 1); | |
1404 | } | |
1405 | ||
ab00b3e5 JB |
1406 | static void |
1407 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1408 | { | |
1409 | struct drm_device *dev = obj->dev; | |
23010e43 | 1410 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1411 | struct drm_gem_mm *mm = dev->mm_private; |
1412 | struct drm_map_list *list; | |
1413 | ||
1414 | list = &obj->map_list; | |
1415 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1416 | ||
1417 | if (list->file_offset_node) { | |
1418 | drm_mm_put_block(list->file_offset_node); | |
1419 | list->file_offset_node = NULL; | |
1420 | } | |
1421 | ||
1422 | if (list->map) { | |
9a298b2a | 1423 | kfree(list->map); |
ab00b3e5 JB |
1424 | list->map = NULL; |
1425 | } | |
1426 | ||
1427 | obj_priv->mmap_offset = 0; | |
1428 | } | |
1429 | ||
de151cf6 JB |
1430 | /** |
1431 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1432 | * @obj: object to check | |
1433 | * | |
1434 | * Return the required GTT alignment for an object, taking into account | |
1435 | * potential fence register mapping if needed. | |
1436 | */ | |
1437 | static uint32_t | |
1438 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1439 | { | |
1440 | struct drm_device *dev = obj->dev; | |
23010e43 | 1441 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1442 | int start, i; |
1443 | ||
1444 | /* | |
1445 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1446 | * if a fence register is needed for the object. | |
1447 | */ | |
a6c45cf0 | 1448 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1449 | return 4096; |
1450 | ||
1451 | /* | |
1452 | * Previous chips need to be aligned to the size of the smallest | |
1453 | * fence register that can contain the object. | |
1454 | */ | |
a6c45cf0 | 1455 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1456 | start = 1024*1024; |
1457 | else | |
1458 | start = 512*1024; | |
1459 | ||
1460 | for (i = start; i < obj->size; i <<= 1) | |
1461 | ; | |
1462 | ||
1463 | return i; | |
1464 | } | |
1465 | ||
1466 | /** | |
1467 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1468 | * @dev: DRM device | |
1469 | * @data: GTT mapping ioctl data | |
1470 | * @file_priv: GEM object info | |
1471 | * | |
1472 | * Simply returns the fake offset to userspace so it can mmap it. | |
1473 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1474 | * up so we can get faults in the handler above. | |
1475 | * | |
1476 | * The fault handler will take care of binding the object into the GTT | |
1477 | * (since it may have been evicted to make room for something), allocating | |
1478 | * a fence register, and mapping the appropriate aperture address into | |
1479 | * userspace. | |
1480 | */ | |
1481 | int | |
1482 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1483 | struct drm_file *file_priv) | |
1484 | { | |
1485 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1486 | struct drm_gem_object *obj; |
1487 | struct drm_i915_gem_object *obj_priv; | |
1488 | int ret; | |
1489 | ||
1490 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1491 | return -ENODEV; | |
1492 | ||
76c1dec1 | 1493 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1494 | if (ret) |
76c1dec1 | 1495 | return ret; |
de151cf6 | 1496 | |
1d7cfea1 CW |
1497 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1498 | if (obj == NULL) { | |
1499 | ret = -ENOENT; | |
1500 | goto unlock; | |
1501 | } | |
23010e43 | 1502 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1503 | |
ab18282d CW |
1504 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1505 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1d7cfea1 CW |
1506 | ret = -EINVAL; |
1507 | goto out; | |
ab18282d CW |
1508 | } |
1509 | ||
de151cf6 JB |
1510 | if (!obj_priv->mmap_offset) { |
1511 | ret = i915_gem_create_mmap_offset(obj); | |
1d7cfea1 CW |
1512 | if (ret) |
1513 | goto out; | |
de151cf6 JB |
1514 | } |
1515 | ||
1516 | args->offset = obj_priv->mmap_offset; | |
1517 | ||
de151cf6 JB |
1518 | /* |
1519 | * Pull it into the GTT so that we have a page list (makes the | |
1520 | * initial fault faster and any subsequent flushing possible). | |
1521 | */ | |
1522 | if (!obj_priv->agp_mem) { | |
920afa77 | 1523 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
1d7cfea1 CW |
1524 | if (ret) |
1525 | goto out; | |
de151cf6 JB |
1526 | } |
1527 | ||
1d7cfea1 | 1528 | out: |
de151cf6 | 1529 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1530 | unlock: |
de151cf6 | 1531 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1532 | return ret; |
de151cf6 JB |
1533 | } |
1534 | ||
5cdf5881 | 1535 | static void |
856fa198 | 1536 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1537 | { |
23010e43 | 1538 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1539 | int page_count = obj->size / PAGE_SIZE; |
1540 | int i; | |
1541 | ||
856fa198 | 1542 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1543 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1544 | |
856fa198 EA |
1545 | if (--obj_priv->pages_refcount != 0) |
1546 | return; | |
673a394b | 1547 | |
280b713b EA |
1548 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1549 | i915_gem_object_save_bit_17_swizzle(obj); | |
1550 | ||
3ef94daa | 1551 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1552 | obj_priv->dirty = 0; |
3ef94daa CW |
1553 | |
1554 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1555 | if (obj_priv->dirty) |
1556 | set_page_dirty(obj_priv->pages[i]); | |
1557 | ||
1558 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1559 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1560 | |
1561 | page_cache_release(obj_priv->pages[i]); | |
1562 | } | |
673a394b EA |
1563 | obj_priv->dirty = 0; |
1564 | ||
8e7d2b2c | 1565 | drm_free_large(obj_priv->pages); |
856fa198 | 1566 | obj_priv->pages = NULL; |
673a394b EA |
1567 | } |
1568 | ||
a56ba56c CW |
1569 | static uint32_t |
1570 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1571 | struct intel_ring_buffer *ring) | |
1572 | { | |
1573 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1574 | ||
1575 | ring->outstanding_lazy_request = true; | |
1576 | return dev_priv->next_seqno; | |
1577 | } | |
1578 | ||
673a394b | 1579 | static void |
617dbe27 | 1580 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1581 | struct intel_ring_buffer *ring) |
673a394b EA |
1582 | { |
1583 | struct drm_device *dev = obj->dev; | |
69dc4987 | 1584 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1585 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1586 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1587 | |
852835f3 ZN |
1588 | BUG_ON(ring == NULL); |
1589 | obj_priv->ring = ring; | |
673a394b EA |
1590 | |
1591 | /* Add a reference if we're newly entering the active list. */ | |
1592 | if (!obj_priv->active) { | |
1593 | drm_gem_object_reference(obj); | |
1594 | obj_priv->active = 1; | |
1595 | } | |
e35a41de | 1596 | |
673a394b | 1597 | /* Move from whatever list we were on to the tail of execution. */ |
69dc4987 CW |
1598 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
1599 | list_move_tail(&obj_priv->ring_list, &ring->active_list); | |
ce44b0ea | 1600 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1601 | } |
1602 | ||
ce44b0ea EA |
1603 | static void |
1604 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1605 | { | |
1606 | struct drm_device *dev = obj->dev; | |
1607 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1608 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1609 | |
1610 | BUG_ON(!obj_priv->active); | |
69dc4987 CW |
1611 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
1612 | list_del_init(&obj_priv->ring_list); | |
ce44b0ea EA |
1613 | obj_priv->last_rendering_seqno = 0; |
1614 | } | |
673a394b | 1615 | |
963b4836 CW |
1616 | /* Immediately discard the backing storage */ |
1617 | static void | |
1618 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1619 | { | |
23010e43 | 1620 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1621 | struct inode *inode; |
963b4836 | 1622 | |
ae9fed6b CW |
1623 | /* Our goal here is to return as much of the memory as |
1624 | * is possible back to the system as we are called from OOM. | |
1625 | * To do this we must instruct the shmfs to drop all of its | |
1626 | * backing pages, *now*. Here we mirror the actions taken | |
1627 | * when by shmem_delete_inode() to release the backing store. | |
1628 | */ | |
bb6baf76 | 1629 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1630 | truncate_inode_pages(inode->i_mapping, 0); |
1631 | if (inode->i_op->truncate_range) | |
1632 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1633 | |
1634 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1635 | } |
1636 | ||
1637 | static inline int | |
1638 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1639 | { | |
1640 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1641 | } | |
1642 | ||
673a394b EA |
1643 | static void |
1644 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1645 | { | |
1646 | struct drm_device *dev = obj->dev; | |
1647 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1648 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1649 | |
673a394b | 1650 | if (obj_priv->pin_count != 0) |
69dc4987 | 1651 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
673a394b | 1652 | else |
69dc4987 CW |
1653 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
1654 | list_del_init(&obj_priv->ring_list); | |
673a394b | 1655 | |
99fcb766 DV |
1656 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1657 | ||
ce44b0ea | 1658 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1659 | obj_priv->ring = NULL; |
673a394b EA |
1660 | if (obj_priv->active) { |
1661 | obj_priv->active = 0; | |
1662 | drm_gem_object_unreference(obj); | |
1663 | } | |
23bc5982 | 1664 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1665 | } |
1666 | ||
63560396 DV |
1667 | static void |
1668 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1669 | uint32_t flush_domains, |
852835f3 | 1670 | struct intel_ring_buffer *ring) |
63560396 DV |
1671 | { |
1672 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1673 | struct drm_i915_gem_object *obj_priv, *next; | |
1674 | ||
1675 | list_for_each_entry_safe(obj_priv, next, | |
64193406 | 1676 | &ring->gpu_write_list, |
63560396 | 1677 | gpu_write_list) { |
a8089e84 | 1678 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1679 | |
64193406 | 1680 | if (obj->write_domain & flush_domains) { |
63560396 DV |
1681 | uint32_t old_write_domain = obj->write_domain; |
1682 | ||
1683 | obj->write_domain = 0; | |
1684 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1685 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1686 | |
1687 | /* update the fence lru list */ | |
007cc8ac DV |
1688 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1689 | struct drm_i915_fence_reg *reg = | |
1690 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1691 | list_move_tail(®->lru_list, | |
63560396 | 1692 | &dev_priv->mm.fence_list); |
007cc8ac | 1693 | } |
63560396 DV |
1694 | |
1695 | trace_i915_gem_object_change_domain(obj, | |
1696 | obj->read_domains, | |
1697 | old_write_domain); | |
1698 | } | |
1699 | } | |
1700 | } | |
8187a2b7 | 1701 | |
3cce469c | 1702 | int |
8a1a49f9 | 1703 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1704 | struct drm_file *file, |
8dc5d147 | 1705 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1706 | struct intel_ring_buffer *ring) |
673a394b EA |
1707 | { |
1708 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1709 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1710 | uint32_t seqno; |
1711 | int was_empty; | |
3cce469c CW |
1712 | int ret; |
1713 | ||
1714 | BUG_ON(request == NULL); | |
673a394b | 1715 | |
f787a5f5 CW |
1716 | if (file != NULL) |
1717 | file_priv = file->driver_priv; | |
b962442e | 1718 | |
3cce469c CW |
1719 | ret = ring->add_request(ring, &seqno); |
1720 | if (ret) | |
1721 | return ret; | |
673a394b | 1722 | |
a56ba56c | 1723 | ring->outstanding_lazy_request = false; |
673a394b EA |
1724 | |
1725 | request->seqno = seqno; | |
852835f3 | 1726 | request->ring = ring; |
673a394b | 1727 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1728 | was_empty = list_empty(&ring->request_list); |
1729 | list_add_tail(&request->list, &ring->request_list); | |
1730 | ||
f787a5f5 | 1731 | if (file_priv) { |
1c25595f | 1732 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1733 | request->file_priv = file_priv; |
b962442e | 1734 | list_add_tail(&request->client_list, |
f787a5f5 | 1735 | &file_priv->mm.request_list); |
1c25595f | 1736 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1737 | } |
673a394b | 1738 | |
f65d9421 | 1739 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1740 | mod_timer(&dev_priv->hangcheck_timer, |
1741 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1742 | if (was_empty) |
b3b079db CW |
1743 | queue_delayed_work(dev_priv->wq, |
1744 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1745 | } |
3cce469c | 1746 | return 0; |
673a394b EA |
1747 | } |
1748 | ||
1749 | /** | |
1750 | * Command execution barrier | |
1751 | * | |
1752 | * Ensures that all commands in the ring are finished | |
1753 | * before signalling the CPU | |
1754 | */ | |
8a1a49f9 | 1755 | static void |
852835f3 | 1756 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1757 | { |
673a394b | 1758 | uint32_t flush_domains = 0; |
673a394b EA |
1759 | |
1760 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1761 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1762 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1763 | |
78501eac | 1764 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1765 | } |
1766 | ||
f787a5f5 CW |
1767 | static inline void |
1768 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1769 | { |
1c25595f | 1770 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1771 | |
1c25595f CW |
1772 | if (!file_priv) |
1773 | return; | |
1c5d22f7 | 1774 | |
1c25595f CW |
1775 | spin_lock(&file_priv->mm.lock); |
1776 | list_del(&request->client_list); | |
1777 | request->file_priv = NULL; | |
1778 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1779 | } |
673a394b | 1780 | |
dfaae392 CW |
1781 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1782 | struct intel_ring_buffer *ring) | |
9375e446 | 1783 | { |
dfaae392 CW |
1784 | while (!list_empty(&ring->request_list)) { |
1785 | struct drm_i915_gem_request *request; | |
673a394b | 1786 | |
dfaae392 CW |
1787 | request = list_first_entry(&ring->request_list, |
1788 | struct drm_i915_gem_request, | |
1789 | list); | |
de151cf6 | 1790 | |
dfaae392 | 1791 | list_del(&request->list); |
f787a5f5 | 1792 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1793 | kfree(request); |
1794 | } | |
673a394b | 1795 | |
dfaae392 | 1796 | while (!list_empty(&ring->active_list)) { |
9375e446 CW |
1797 | struct drm_i915_gem_object *obj_priv; |
1798 | ||
dfaae392 | 1799 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 | 1800 | struct drm_i915_gem_object, |
69dc4987 | 1801 | ring_list); |
9375e446 CW |
1802 | |
1803 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1804 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 | 1805 | i915_gem_object_move_to_inactive(&obj_priv->base); |
673a394b EA |
1806 | } |
1807 | } | |
1808 | ||
069efc1d | 1809 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1810 | { |
77f01230 CW |
1811 | struct drm_i915_private *dev_priv = dev->dev_private; |
1812 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1813 | int i; |
673a394b | 1814 | |
dfaae392 | 1815 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1816 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1817 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1818 | |
1819 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1820 | * to be lost on reset along with the data, so simply move the | |
1821 | * lost bo to the inactive list. | |
1822 | */ | |
1823 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1824 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1825 | struct drm_i915_gem_object, | |
69dc4987 | 1826 | mm_list); |
dfaae392 CW |
1827 | |
1828 | obj_priv->base.write_domain = 0; | |
1829 | list_del_init(&obj_priv->gpu_write_list); | |
1830 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1831 | } | |
1832 | ||
1833 | /* Move everything out of the GPU domains to ensure we do any | |
1834 | * necessary invalidation upon reuse. | |
1835 | */ | |
77f01230 CW |
1836 | list_for_each_entry(obj_priv, |
1837 | &dev_priv->mm.inactive_list, | |
69dc4987 | 1838 | mm_list) |
77f01230 CW |
1839 | { |
1840 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1841 | } | |
069efc1d CW |
1842 | |
1843 | /* The fence registers are invalidated so clear them out */ | |
1844 | for (i = 0; i < 16; i++) { | |
1845 | struct drm_i915_fence_reg *reg; | |
1846 | ||
1847 | reg = &dev_priv->fence_regs[i]; | |
1848 | if (!reg->obj) | |
1849 | continue; | |
1850 | ||
1851 | i915_gem_clear_fence_reg(reg->obj); | |
1852 | } | |
673a394b EA |
1853 | } |
1854 | ||
1855 | /** | |
1856 | * This function clears the request list as sequence numbers are passed. | |
1857 | */ | |
b09a1fec CW |
1858 | static void |
1859 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1860 | struct intel_ring_buffer *ring) | |
673a394b EA |
1861 | { |
1862 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1863 | uint32_t seqno; | |
1864 | ||
b84d5f0c CW |
1865 | if (!ring->status_page.page_addr || |
1866 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1867 | return; |
1868 | ||
23bc5982 | 1869 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1870 | |
78501eac | 1871 | seqno = ring->get_seqno(ring); |
852835f3 | 1872 | while (!list_empty(&ring->request_list)) { |
673a394b | 1873 | struct drm_i915_gem_request *request; |
673a394b | 1874 | |
852835f3 | 1875 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1876 | struct drm_i915_gem_request, |
1877 | list); | |
673a394b | 1878 | |
dfaae392 | 1879 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1880 | break; |
1881 | ||
1882 | trace_i915_gem_request_retire(dev, request->seqno); | |
1883 | ||
1884 | list_del(&request->list); | |
f787a5f5 | 1885 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1886 | kfree(request); |
1887 | } | |
673a394b | 1888 | |
b84d5f0c CW |
1889 | /* Move any buffers on the active list that are no longer referenced |
1890 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1891 | */ | |
1892 | while (!list_empty(&ring->active_list)) { | |
1893 | struct drm_gem_object *obj; | |
1894 | struct drm_i915_gem_object *obj_priv; | |
1895 | ||
1896 | obj_priv = list_first_entry(&ring->active_list, | |
1897 | struct drm_i915_gem_object, | |
69dc4987 | 1898 | ring_list); |
673a394b | 1899 | |
dfaae392 | 1900 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1901 | break; |
b84d5f0c CW |
1902 | |
1903 | obj = &obj_priv->base; | |
b84d5f0c CW |
1904 | if (obj->write_domain != 0) |
1905 | i915_gem_object_move_to_flushing(obj); | |
1906 | else | |
1907 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1908 | } |
9d34e5db CW |
1909 | |
1910 | if (unlikely (dev_priv->trace_irq_seqno && | |
1911 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 1912 | ring->user_irq_put(ring); |
9d34e5db CW |
1913 | dev_priv->trace_irq_seqno = 0; |
1914 | } | |
23bc5982 CW |
1915 | |
1916 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1917 | } |
1918 | ||
b09a1fec CW |
1919 | void |
1920 | i915_gem_retire_requests(struct drm_device *dev) | |
1921 | { | |
1922 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1923 | ||
be72615b CW |
1924 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1925 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1926 | ||
1927 | /* We must be careful that during unbind() we do not | |
1928 | * accidentally infinitely recurse into retire requests. | |
1929 | * Currently: | |
1930 | * retire -> free -> unbind -> wait -> retire_ring | |
1931 | */ | |
1932 | list_for_each_entry_safe(obj_priv, tmp, | |
1933 | &dev_priv->mm.deferred_free_list, | |
69dc4987 | 1934 | mm_list) |
be72615b CW |
1935 | i915_gem_free_object_tail(&obj_priv->base); |
1936 | } | |
1937 | ||
b09a1fec | 1938 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 1939 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 1940 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
1941 | } |
1942 | ||
75ef9da2 | 1943 | static void |
673a394b EA |
1944 | i915_gem_retire_work_handler(struct work_struct *work) |
1945 | { | |
1946 | drm_i915_private_t *dev_priv; | |
1947 | struct drm_device *dev; | |
1948 | ||
1949 | dev_priv = container_of(work, drm_i915_private_t, | |
1950 | mm.retire_work.work); | |
1951 | dev = dev_priv->dev; | |
1952 | ||
891b48cf CW |
1953 | /* Come back later if the device is busy... */ |
1954 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1955 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1956 | return; | |
1957 | } | |
1958 | ||
b09a1fec | 1959 | i915_gem_retire_requests(dev); |
d1b851fc | 1960 | |
6dbe2772 | 1961 | if (!dev_priv->mm.suspended && |
d1b851fc | 1962 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
1963 | !list_empty(&dev_priv->bsd_ring.request_list) || |
1964 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 1965 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1966 | mutex_unlock(&dev->struct_mutex); |
1967 | } | |
1968 | ||
5a5a0c64 | 1969 | int |
852835f3 | 1970 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1971 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1972 | { |
1973 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1974 | u32 ier; |
673a394b EA |
1975 | int ret = 0; |
1976 | ||
1977 | BUG_ON(seqno == 0); | |
1978 | ||
ba1234d1 | 1979 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
1980 | return -EAGAIN; |
1981 | ||
a56ba56c | 1982 | if (ring->outstanding_lazy_request) { |
3cce469c CW |
1983 | struct drm_i915_gem_request *request; |
1984 | ||
1985 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1986 | if (request == NULL) | |
e35a41de | 1987 | return -ENOMEM; |
3cce469c CW |
1988 | |
1989 | ret = i915_add_request(dev, NULL, request, ring); | |
1990 | if (ret) { | |
1991 | kfree(request); | |
1992 | return ret; | |
1993 | } | |
1994 | ||
1995 | seqno = request->seqno; | |
e35a41de | 1996 | } |
a56ba56c | 1997 | BUG_ON(seqno == dev_priv->next_seqno); |
ffed1d09 | 1998 | |
78501eac | 1999 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2000 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2001 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2002 | else | |
2003 | ier = I915_READ(IER); | |
802c7eb6 JB |
2004 | if (!ier) { |
2005 | DRM_ERROR("something (likely vbetool) disabled " | |
2006 | "interrupts, re-enabling\n"); | |
2007 | i915_driver_irq_preinstall(dev); | |
2008 | i915_driver_irq_postinstall(dev); | |
2009 | } | |
2010 | ||
1c5d22f7 CW |
2011 | trace_i915_gem_request_wait_begin(dev, seqno); |
2012 | ||
b2223497 | 2013 | ring->waiting_seqno = seqno; |
78501eac | 2014 | ring->user_irq_get(ring); |
48764bf4 | 2015 | if (interruptible) |
852835f3 | 2016 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2017 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2018 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2019 | else |
852835f3 | 2020 | wait_event(ring->irq_queue, |
78501eac | 2021 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2022 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2023 | |
78501eac | 2024 | ring->user_irq_put(ring); |
b2223497 | 2025 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2026 | |
2027 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2028 | } |
ba1234d1 | 2029 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2030 | ret = -EAGAIN; |
673a394b EA |
2031 | |
2032 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2033 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2034 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2035 | dev_priv->next_seqno); |
673a394b EA |
2036 | |
2037 | /* Directly dispatch request retiring. While we have the work queue | |
2038 | * to handle this, the waiter on a request often wants an associated | |
2039 | * buffer to have made it to the inactive list, and we would need | |
2040 | * a separate wait queue to handle that. | |
2041 | */ | |
2042 | if (ret == 0) | |
b09a1fec | 2043 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2044 | |
2045 | return ret; | |
2046 | } | |
2047 | ||
48764bf4 DV |
2048 | /** |
2049 | * Waits for a sequence number to be signaled, and cleans up the | |
2050 | * request and object lists appropriately for that event. | |
2051 | */ | |
2052 | static int | |
852835f3 | 2053 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2054 | struct intel_ring_buffer *ring) |
48764bf4 | 2055 | { |
852835f3 | 2056 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2057 | } |
2058 | ||
20f0cd55 | 2059 | static void |
9220434a | 2060 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2061 | struct drm_file *file_priv, |
9220434a CW |
2062 | struct intel_ring_buffer *ring, |
2063 | uint32_t invalidate_domains, | |
2064 | uint32_t flush_domains) | |
2065 | { | |
78501eac | 2066 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2067 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2068 | } | |
2069 | ||
8187a2b7 ZN |
2070 | static void |
2071 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2072 | struct drm_file *file_priv, |
8187a2b7 | 2073 | uint32_t invalidate_domains, |
9220434a CW |
2074 | uint32_t flush_domains, |
2075 | uint32_t flush_rings) | |
8187a2b7 ZN |
2076 | { |
2077 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2078 | |
8187a2b7 ZN |
2079 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2080 | drm_agp_chipset_flush(dev); | |
8bff917c | 2081 | |
9220434a CW |
2082 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2083 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2084 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2085 | &dev_priv->render_ring, |
2086 | invalidate_domains, flush_domains); | |
2087 | if (flush_rings & RING_BSD) | |
c78ec30b | 2088 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2089 | &dev_priv->bsd_ring, |
2090 | invalidate_domains, flush_domains); | |
549f7365 CW |
2091 | if (flush_rings & RING_BLT) |
2092 | i915_gem_flush_ring(dev, file_priv, | |
2093 | &dev_priv->blt_ring, | |
2094 | invalidate_domains, flush_domains); | |
9220434a | 2095 | } |
8187a2b7 ZN |
2096 | } |
2097 | ||
673a394b EA |
2098 | /** |
2099 | * Ensures that all rendering to the object has completed and the object is | |
2100 | * safe to unbind from the GTT or access from the CPU. | |
2101 | */ | |
2102 | static int | |
2cf34d7b CW |
2103 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2104 | bool interruptible) | |
673a394b EA |
2105 | { |
2106 | struct drm_device *dev = obj->dev; | |
23010e43 | 2107 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2108 | int ret; |
2109 | ||
e47c68e9 EA |
2110 | /* This function only exists to support waiting for existing rendering, |
2111 | * not for emitting required flushes. | |
673a394b | 2112 | */ |
e47c68e9 | 2113 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2114 | |
2115 | /* If there is rendering queued on the buffer being evicted, wait for | |
2116 | * it. | |
2117 | */ | |
2118 | if (obj_priv->active) { | |
2cf34d7b CW |
2119 | ret = i915_do_wait_request(dev, |
2120 | obj_priv->last_rendering_seqno, | |
2121 | interruptible, | |
2122 | obj_priv->ring); | |
2123 | if (ret) | |
673a394b EA |
2124 | return ret; |
2125 | } | |
2126 | ||
2127 | return 0; | |
2128 | } | |
2129 | ||
2130 | /** | |
2131 | * Unbinds an object from the GTT aperture. | |
2132 | */ | |
0f973f27 | 2133 | int |
673a394b EA |
2134 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2135 | { | |
2136 | struct drm_device *dev = obj->dev; | |
73aa808f | 2137 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2138 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2139 | int ret = 0; |
2140 | ||
673a394b EA |
2141 | if (obj_priv->gtt_space == NULL) |
2142 | return 0; | |
2143 | ||
2144 | if (obj_priv->pin_count != 0) { | |
2145 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2146 | return -EINVAL; | |
2147 | } | |
2148 | ||
5323fd04 EA |
2149 | /* blow away mappings if mapped through GTT */ |
2150 | i915_gem_release_mmap(obj); | |
2151 | ||
673a394b EA |
2152 | /* Move the object to the CPU domain to ensure that |
2153 | * any possible CPU writes while it's not in the GTT | |
2154 | * are flushed when we go to remap it. This will | |
2155 | * also ensure that all pending GPU writes are finished | |
2156 | * before we unbind. | |
2157 | */ | |
e47c68e9 | 2158 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2159 | if (ret == -ERESTARTSYS) |
673a394b | 2160 | return ret; |
8dc1775d CW |
2161 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2162 | * should be safe and we need to cleanup or else we might | |
2163 | * cause memory corruption through use-after-free. | |
2164 | */ | |
812ed492 CW |
2165 | if (ret) { |
2166 | i915_gem_clflush_object(obj); | |
2167 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2168 | } | |
673a394b | 2169 | |
96b47b65 DV |
2170 | /* release the fence reg _after_ flushing */ |
2171 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2172 | i915_gem_clear_fence_reg(obj); | |
2173 | ||
73aa808f CW |
2174 | drm_unbind_agp(obj_priv->agp_mem); |
2175 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2176 | |
856fa198 | 2177 | i915_gem_object_put_pages(obj); |
a32808c0 | 2178 | BUG_ON(obj_priv->pages_refcount); |
673a394b | 2179 | |
73aa808f | 2180 | i915_gem_info_remove_gtt(dev_priv, obj->size); |
69dc4987 | 2181 | list_del_init(&obj_priv->mm_list); |
673a394b | 2182 | |
73aa808f CW |
2183 | drm_mm_put_block(obj_priv->gtt_space); |
2184 | obj_priv->gtt_space = NULL; | |
9af90d19 | 2185 | obj_priv->gtt_offset = 0; |
673a394b | 2186 | |
963b4836 CW |
2187 | if (i915_gem_object_is_purgeable(obj_priv)) |
2188 | i915_gem_object_truncate(obj); | |
2189 | ||
1c5d22f7 CW |
2190 | trace_i915_gem_object_unbind(obj); |
2191 | ||
8dc1775d | 2192 | return ret; |
673a394b EA |
2193 | } |
2194 | ||
a56ba56c CW |
2195 | static int i915_ring_idle(struct drm_device *dev, |
2196 | struct intel_ring_buffer *ring) | |
2197 | { | |
64193406 CW |
2198 | if (list_empty(&ring->gpu_write_list)) |
2199 | return 0; | |
2200 | ||
a56ba56c CW |
2201 | i915_gem_flush_ring(dev, NULL, ring, |
2202 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2203 | return i915_wait_request(dev, | |
2204 | i915_gem_next_request_seqno(dev, ring), | |
2205 | ring); | |
2206 | } | |
2207 | ||
b47eb4a2 | 2208 | int |
4df2faf4 DV |
2209 | i915_gpu_idle(struct drm_device *dev) |
2210 | { | |
2211 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2212 | bool lists_empty; | |
852835f3 | 2213 | int ret; |
4df2faf4 | 2214 | |
d1b851fc ZN |
2215 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2216 | list_empty(&dev_priv->render_ring.active_list) && | |
549f7365 CW |
2217 | list_empty(&dev_priv->bsd_ring.active_list) && |
2218 | list_empty(&dev_priv->blt_ring.active_list)); | |
4df2faf4 DV |
2219 | if (lists_empty) |
2220 | return 0; | |
2221 | ||
2222 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2223 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2224 | if (ret) |
2225 | return ret; | |
d1b851fc | 2226 | |
87acb0a5 CW |
2227 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2228 | if (ret) | |
2229 | return ret; | |
d1b851fc | 2230 | |
549f7365 CW |
2231 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2232 | if (ret) | |
2233 | return ret; | |
4df2faf4 | 2234 | |
8a1a49f9 | 2235 | return 0; |
4df2faf4 DV |
2236 | } |
2237 | ||
5cdf5881 | 2238 | static int |
4bdadb97 CW |
2239 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2240 | gfp_t gfpmask) | |
673a394b | 2241 | { |
23010e43 | 2242 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2243 | int page_count, i; |
2244 | struct address_space *mapping; | |
2245 | struct inode *inode; | |
2246 | struct page *page; | |
673a394b | 2247 | |
778c3544 DV |
2248 | BUG_ON(obj_priv->pages_refcount |
2249 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2250 | ||
856fa198 | 2251 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2252 | return 0; |
2253 | ||
2254 | /* Get the list of pages out of our struct file. They'll be pinned | |
2255 | * at this point until we release them. | |
2256 | */ | |
2257 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2258 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2259 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2260 | if (obj_priv->pages == NULL) { |
856fa198 | 2261 | obj_priv->pages_refcount--; |
673a394b EA |
2262 | return -ENOMEM; |
2263 | } | |
2264 | ||
2265 | inode = obj->filp->f_path.dentry->d_inode; | |
2266 | mapping = inode->i_mapping; | |
2267 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2268 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2269 | GFP_HIGHUSER | |
4bdadb97 | 2270 | __GFP_COLD | |
cd9f040d | 2271 | __GFP_RECLAIMABLE | |
4bdadb97 | 2272 | gfpmask); |
1f2b1013 CW |
2273 | if (IS_ERR(page)) |
2274 | goto err_pages; | |
2275 | ||
856fa198 | 2276 | obj_priv->pages[i] = page; |
673a394b | 2277 | } |
280b713b EA |
2278 | |
2279 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2280 | i915_gem_object_do_bit_17_swizzle(obj); | |
2281 | ||
673a394b | 2282 | return 0; |
1f2b1013 CW |
2283 | |
2284 | err_pages: | |
2285 | while (i--) | |
2286 | page_cache_release(obj_priv->pages[i]); | |
2287 | ||
2288 | drm_free_large(obj_priv->pages); | |
2289 | obj_priv->pages = NULL; | |
2290 | obj_priv->pages_refcount--; | |
2291 | return PTR_ERR(page); | |
673a394b EA |
2292 | } |
2293 | ||
4e901fdc EA |
2294 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2295 | { | |
2296 | struct drm_gem_object *obj = reg->obj; | |
2297 | struct drm_device *dev = obj->dev; | |
2298 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2299 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2300 | int regnum = obj_priv->fence_reg; |
2301 | uint64_t val; | |
2302 | ||
2303 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2304 | 0xfffff000) << 32; | |
2305 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2306 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2307 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2308 | ||
2309 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2310 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2311 | val |= I965_FENCE_REG_VALID; | |
2312 | ||
2313 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2314 | } | |
2315 | ||
de151cf6 JB |
2316 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2317 | { | |
2318 | struct drm_gem_object *obj = reg->obj; | |
2319 | struct drm_device *dev = obj->dev; | |
2320 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2321 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2322 | int regnum = obj_priv->fence_reg; |
2323 | uint64_t val; | |
2324 | ||
2325 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2326 | 0xfffff000) << 32; | |
2327 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2328 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2329 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2330 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2331 | val |= I965_FENCE_REG_VALID; | |
2332 | ||
2333 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2334 | } | |
2335 | ||
2336 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2337 | { | |
2338 | struct drm_gem_object *obj = reg->obj; | |
2339 | struct drm_device *dev = obj->dev; | |
2340 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2341 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2342 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2343 | int tile_width; |
dc529a4f | 2344 | uint32_t fence_reg, val; |
de151cf6 JB |
2345 | uint32_t pitch_val; |
2346 | ||
2347 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2348 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2349 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2350 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2351 | return; |
2352 | } | |
2353 | ||
0f973f27 JB |
2354 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2355 | HAS_128_BYTE_Y_TILING(dev)) | |
2356 | tile_width = 128; | |
de151cf6 | 2357 | else |
0f973f27 JB |
2358 | tile_width = 512; |
2359 | ||
2360 | /* Note: pitch better be a power of two tile widths */ | |
2361 | pitch_val = obj_priv->stride / tile_width; | |
2362 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2363 | |
c36a2a6d DV |
2364 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2365 | HAS_128_BYTE_Y_TILING(dev)) | |
2366 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2367 | else | |
2368 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2369 | ||
de151cf6 JB |
2370 | val = obj_priv->gtt_offset; |
2371 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2372 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2373 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2374 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2375 | val |= I830_FENCE_REG_VALID; | |
2376 | ||
dc529a4f EA |
2377 | if (regnum < 8) |
2378 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2379 | else | |
2380 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2381 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2382 | } |
2383 | ||
2384 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2385 | { | |
2386 | struct drm_gem_object *obj = reg->obj; | |
2387 | struct drm_device *dev = obj->dev; | |
2388 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2389 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2390 | int regnum = obj_priv->fence_reg; |
2391 | uint32_t val; | |
2392 | uint32_t pitch_val; | |
8d7773a3 | 2393 | uint32_t fence_size_bits; |
de151cf6 | 2394 | |
8d7773a3 | 2395 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2396 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2397 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2398 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2399 | return; |
2400 | } | |
2401 | ||
e76a16de EA |
2402 | pitch_val = obj_priv->stride / 128; |
2403 | pitch_val = ffs(pitch_val) - 1; | |
2404 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2405 | ||
de151cf6 JB |
2406 | val = obj_priv->gtt_offset; |
2407 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2408 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2409 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2410 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2411 | val |= fence_size_bits; | |
de151cf6 JB |
2412 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2413 | val |= I830_FENCE_REG_VALID; | |
2414 | ||
2415 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2416 | } |
2417 | ||
2cf34d7b CW |
2418 | static int i915_find_fence_reg(struct drm_device *dev, |
2419 | bool interruptible) | |
ae3db24a DV |
2420 | { |
2421 | struct drm_i915_fence_reg *reg = NULL; | |
2422 | struct drm_i915_gem_object *obj_priv = NULL; | |
2423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2424 | struct drm_gem_object *obj = NULL; | |
2425 | int i, avail, ret; | |
2426 | ||
2427 | /* First try to find a free reg */ | |
2428 | avail = 0; | |
2429 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2430 | reg = &dev_priv->fence_regs[i]; | |
2431 | if (!reg->obj) | |
2432 | return i; | |
2433 | ||
23010e43 | 2434 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2435 | if (!obj_priv->pin_count) |
2436 | avail++; | |
2437 | } | |
2438 | ||
2439 | if (avail == 0) | |
2440 | return -ENOSPC; | |
2441 | ||
2442 | /* None available, try to steal one or wait for a user to finish */ | |
2443 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2444 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2445 | lru_list) { | |
2446 | obj = reg->obj; | |
2447 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2448 | |
2449 | if (obj_priv->pin_count) | |
2450 | continue; | |
2451 | ||
2452 | /* found one! */ | |
2453 | i = obj_priv->fence_reg; | |
2454 | break; | |
2455 | } | |
2456 | ||
2457 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2458 | ||
2459 | /* We only have a reference on obj from the active list. put_fence_reg | |
2460 | * might drop that one, causing a use-after-free in it. So hold a | |
2461 | * private reference to obj like the other callers of put_fence_reg | |
2462 | * (set_tiling ioctl) do. */ | |
2463 | drm_gem_object_reference(obj); | |
2cf34d7b | 2464 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2465 | drm_gem_object_unreference(obj); |
2466 | if (ret != 0) | |
2467 | return ret; | |
2468 | ||
2469 | return i; | |
2470 | } | |
2471 | ||
de151cf6 JB |
2472 | /** |
2473 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2474 | * @obj: object to map through a fence reg | |
2475 | * | |
2476 | * When mapping objects through the GTT, userspace wants to be able to write | |
2477 | * to them without having to worry about swizzling if the object is tiled. | |
2478 | * | |
2479 | * This function walks the fence regs looking for a free one for @obj, | |
2480 | * stealing one if it can't find any. | |
2481 | * | |
2482 | * It then sets up the reg based on the object's properties: address, pitch | |
2483 | * and tiling format. | |
2484 | */ | |
8c4b8c3f | 2485 | int |
2cf34d7b CW |
2486 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2487 | bool interruptible) | |
de151cf6 JB |
2488 | { |
2489 | struct drm_device *dev = obj->dev; | |
79e53945 | 2490 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2491 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2492 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2493 | int ret; |
de151cf6 | 2494 | |
a09ba7fa EA |
2495 | /* Just update our place in the LRU if our fence is getting used. */ |
2496 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2497 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2498 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2499 | return 0; |
2500 | } | |
2501 | ||
de151cf6 JB |
2502 | switch (obj_priv->tiling_mode) { |
2503 | case I915_TILING_NONE: | |
2504 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2505 | break; | |
2506 | case I915_TILING_X: | |
0f973f27 JB |
2507 | if (!obj_priv->stride) |
2508 | return -EINVAL; | |
2509 | WARN((obj_priv->stride & (512 - 1)), | |
2510 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2511 | obj_priv->gtt_offset); | |
de151cf6 JB |
2512 | break; |
2513 | case I915_TILING_Y: | |
0f973f27 JB |
2514 | if (!obj_priv->stride) |
2515 | return -EINVAL; | |
2516 | WARN((obj_priv->stride & (128 - 1)), | |
2517 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2518 | obj_priv->gtt_offset); | |
de151cf6 JB |
2519 | break; |
2520 | } | |
2521 | ||
2cf34d7b | 2522 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2523 | if (ret < 0) |
2524 | return ret; | |
de151cf6 | 2525 | |
ae3db24a DV |
2526 | obj_priv->fence_reg = ret; |
2527 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2528 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2529 | |
de151cf6 JB |
2530 | reg->obj = obj; |
2531 | ||
e259befd CW |
2532 | switch (INTEL_INFO(dev)->gen) { |
2533 | case 6: | |
4e901fdc | 2534 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2535 | break; |
2536 | case 5: | |
2537 | case 4: | |
de151cf6 | 2538 | i965_write_fence_reg(reg); |
e259befd CW |
2539 | break; |
2540 | case 3: | |
de151cf6 | 2541 | i915_write_fence_reg(reg); |
e259befd CW |
2542 | break; |
2543 | case 2: | |
de151cf6 | 2544 | i830_write_fence_reg(reg); |
e259befd CW |
2545 | break; |
2546 | } | |
d9ddcb96 | 2547 | |
ae3db24a DV |
2548 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2549 | obj_priv->tiling_mode); | |
1c5d22f7 | 2550 | |
d9ddcb96 | 2551 | return 0; |
de151cf6 JB |
2552 | } |
2553 | ||
2554 | /** | |
2555 | * i915_gem_clear_fence_reg - clear out fence register info | |
2556 | * @obj: object to clear | |
2557 | * | |
2558 | * Zeroes out the fence register itself and clears out the associated | |
2559 | * data structures in dev_priv and obj_priv. | |
2560 | */ | |
2561 | static void | |
2562 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2563 | { | |
2564 | struct drm_device *dev = obj->dev; | |
79e53945 | 2565 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2566 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2567 | struct drm_i915_fence_reg *reg = |
2568 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2569 | uint32_t fence_reg; |
de151cf6 | 2570 | |
e259befd CW |
2571 | switch (INTEL_INFO(dev)->gen) { |
2572 | case 6: | |
4e901fdc EA |
2573 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2574 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2575 | break; |
2576 | case 5: | |
2577 | case 4: | |
de151cf6 | 2578 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2579 | break; |
2580 | case 3: | |
9b74f734 | 2581 | if (obj_priv->fence_reg >= 8) |
e259befd | 2582 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2583 | else |
e259befd CW |
2584 | case 2: |
2585 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2586 | |
2587 | I915_WRITE(fence_reg, 0); | |
e259befd | 2588 | break; |
dc529a4f | 2589 | } |
de151cf6 | 2590 | |
007cc8ac | 2591 | reg->obj = NULL; |
de151cf6 | 2592 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2593 | list_del_init(®->lru_list); |
de151cf6 JB |
2594 | } |
2595 | ||
52dc7d32 CW |
2596 | /** |
2597 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2598 | * to the buffer to finish, and then resets the fence register. | |
2599 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2600 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2601 | * |
2602 | * Zeroes out the fence register itself and clears out the associated | |
2603 | * data structures in dev_priv and obj_priv. | |
2604 | */ | |
2605 | int | |
2cf34d7b CW |
2606 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2607 | bool interruptible) | |
52dc7d32 CW |
2608 | { |
2609 | struct drm_device *dev = obj->dev; | |
53640e1d | 2610 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2611 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2612 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2613 | |
2614 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2615 | return 0; | |
2616 | ||
10ae9bd2 DV |
2617 | /* If we've changed tiling, GTT-mappings of the object |
2618 | * need to re-fault to ensure that the correct fence register | |
2619 | * setup is in place. | |
2620 | */ | |
2621 | i915_gem_release_mmap(obj); | |
2622 | ||
52dc7d32 CW |
2623 | /* On the i915, GPU access to tiled buffers is via a fence, |
2624 | * therefore we must wait for any outstanding access to complete | |
2625 | * before clearing the fence. | |
2626 | */ | |
53640e1d CW |
2627 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2628 | if (reg->gpu) { | |
52dc7d32 CW |
2629 | int ret; |
2630 | ||
2cf34d7b | 2631 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad | 2632 | if (ret) |
2dafb1e0 CW |
2633 | return ret; |
2634 | ||
2cf34d7b | 2635 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2636 | if (ret) |
52dc7d32 | 2637 | return ret; |
53640e1d CW |
2638 | |
2639 | reg->gpu = false; | |
52dc7d32 CW |
2640 | } |
2641 | ||
4a726612 | 2642 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2643 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2644 | |
2645 | return 0; | |
2646 | } | |
2647 | ||
673a394b EA |
2648 | /** |
2649 | * Finds free space in the GTT aperture and binds the object there. | |
2650 | */ | |
2651 | static int | |
920afa77 DV |
2652 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
2653 | unsigned alignment, | |
2654 | bool mappable) | |
673a394b EA |
2655 | { |
2656 | struct drm_device *dev = obj->dev; | |
2657 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2658 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2659 | struct drm_mm_node *free_space; |
4bdadb97 | 2660 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2661 | int ret; |
673a394b | 2662 | |
bb6baf76 | 2663 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2664 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2665 | return -EINVAL; | |
2666 | } | |
2667 | ||
673a394b | 2668 | if (alignment == 0) |
0f973f27 | 2669 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2670 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2671 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2672 | return -EINVAL; | |
2673 | } | |
2674 | ||
654fc607 CW |
2675 | /* If the object is bigger than the entire aperture, reject it early |
2676 | * before evicting everything in a vain attempt to find space. | |
2677 | */ | |
920afa77 DV |
2678 | if (obj->size > |
2679 | (mappable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { | |
654fc607 CW |
2680 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2681 | return -E2BIG; | |
2682 | } | |
2683 | ||
673a394b | 2684 | search_free: |
920afa77 DV |
2685 | if (mappable) |
2686 | free_space = | |
2687 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
2688 | obj->size, alignment, 0, | |
2689 | dev_priv->mm.gtt_mappable_end, | |
2690 | 0); | |
2691 | else | |
2692 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2693 | obj->size, alignment, 0); | |
2694 | ||
2695 | if (free_space != NULL) { | |
2696 | if (mappable) | |
2697 | obj_priv->gtt_space = | |
2698 | drm_mm_get_block_range_generic(free_space, | |
2699 | obj->size, | |
2700 | alignment, 0, | |
2701 | dev_priv->mm.gtt_mappable_end, | |
2702 | 0); | |
2703 | else | |
2704 | obj_priv->gtt_space = | |
2705 | drm_mm_get_block(free_space, obj->size, | |
2706 | alignment); | |
2707 | } | |
673a394b EA |
2708 | if (obj_priv->gtt_space == NULL) { |
2709 | /* If the gtt is empty and we're still having trouble | |
2710 | * fitting our object in, we're out of memory. | |
2711 | */ | |
920afa77 DV |
2712 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
2713 | mappable); | |
9731129c | 2714 | if (ret) |
673a394b | 2715 | return ret; |
9731129c | 2716 | |
673a394b EA |
2717 | goto search_free; |
2718 | } | |
2719 | ||
4bdadb97 | 2720 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2721 | if (ret) { |
2722 | drm_mm_put_block(obj_priv->gtt_space); | |
2723 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2724 | |
2725 | if (ret == -ENOMEM) { | |
2726 | /* first try to clear up some space from the GTT */ | |
0108a3ed | 2727 | ret = i915_gem_evict_something(dev, obj->size, |
920afa77 | 2728 | alignment, mappable); |
07f73f69 | 2729 | if (ret) { |
07f73f69 | 2730 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2731 | if (gfpmask) { |
2732 | gfpmask = 0; | |
2733 | goto search_free; | |
07f73f69 CW |
2734 | } |
2735 | ||
2736 | return ret; | |
2737 | } | |
2738 | ||
2739 | goto search_free; | |
2740 | } | |
2741 | ||
673a394b EA |
2742 | return ret; |
2743 | } | |
2744 | ||
673a394b EA |
2745 | /* Create an AGP memory structure pointing at our pages, and bind it |
2746 | * into the GTT. | |
2747 | */ | |
2748 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2749 | obj_priv->pages, |
07f73f69 | 2750 | obj->size >> PAGE_SHIFT, |
9af90d19 | 2751 | obj_priv->gtt_space->start, |
ba1eb1d8 | 2752 | obj_priv->agp_type); |
673a394b | 2753 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2754 | i915_gem_object_put_pages(obj); |
673a394b EA |
2755 | drm_mm_put_block(obj_priv->gtt_space); |
2756 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2757 | |
920afa77 DV |
2758 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
2759 | mappable); | |
9731129c | 2760 | if (ret) |
07f73f69 | 2761 | return ret; |
07f73f69 CW |
2762 | |
2763 | goto search_free; | |
673a394b | 2764 | } |
673a394b | 2765 | |
bf1a1092 | 2766 | /* keep track of bounds object by adding it to the inactive list */ |
69dc4987 | 2767 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
73aa808f | 2768 | i915_gem_info_add_gtt(dev_priv, obj->size); |
bf1a1092 | 2769 | |
673a394b EA |
2770 | /* Assert that the object is not currently in any GPU domain. As it |
2771 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2772 | * a GPU cache | |
2773 | */ | |
21d509e3 CW |
2774 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2775 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2776 | |
9af90d19 | 2777 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
ec57d260 | 2778 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, mappable); |
1c5d22f7 | 2779 | |
673a394b EA |
2780 | return 0; |
2781 | } | |
2782 | ||
2783 | void | |
2784 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2785 | { | |
23010e43 | 2786 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2787 | |
2788 | /* If we don't have a page list set up, then we're not pinned | |
2789 | * to GPU, and we can ignore the cache flush because it'll happen | |
2790 | * again at bind time. | |
2791 | */ | |
856fa198 | 2792 | if (obj_priv->pages == NULL) |
673a394b EA |
2793 | return; |
2794 | ||
1c5d22f7 | 2795 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2796 | |
856fa198 | 2797 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2798 | } |
2799 | ||
e47c68e9 | 2800 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2801 | static int |
ba3d8d74 DV |
2802 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2803 | bool pipelined) | |
e47c68e9 EA |
2804 | { |
2805 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2806 | uint32_t old_write_domain; |
e47c68e9 EA |
2807 | |
2808 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2809 | return 0; |
e47c68e9 EA |
2810 | |
2811 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2812 | old_write_domain = obj->write_domain; |
c78ec30b | 2813 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2814 | to_intel_bo(obj)->ring, |
2815 | 0, obj->write_domain); | |
48b956c5 | 2816 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2817 | |
2818 | trace_i915_gem_object_change_domain(obj, | |
2819 | obj->read_domains, | |
2820 | old_write_domain); | |
ba3d8d74 DV |
2821 | |
2822 | if (pipelined) | |
2823 | return 0; | |
2824 | ||
2cf34d7b | 2825 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2826 | } |
2827 | ||
2828 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2829 | static void | |
2830 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2831 | { | |
1c5d22f7 CW |
2832 | uint32_t old_write_domain; |
2833 | ||
e47c68e9 EA |
2834 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2835 | return; | |
2836 | ||
2837 | /* No actual flushing is required for the GTT write domain. Writes | |
2838 | * to it immediately go to main memory as far as we know, so there's | |
2839 | * no chipset flush. It also doesn't land in render cache. | |
2840 | */ | |
1c5d22f7 | 2841 | old_write_domain = obj->write_domain; |
e47c68e9 | 2842 | obj->write_domain = 0; |
1c5d22f7 CW |
2843 | |
2844 | trace_i915_gem_object_change_domain(obj, | |
2845 | obj->read_domains, | |
2846 | old_write_domain); | |
e47c68e9 EA |
2847 | } |
2848 | ||
2849 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2850 | static void | |
2851 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2852 | { | |
2853 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2854 | uint32_t old_write_domain; |
e47c68e9 EA |
2855 | |
2856 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2857 | return; | |
2858 | ||
2859 | i915_gem_clflush_object(obj); | |
2860 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2861 | old_write_domain = obj->write_domain; |
e47c68e9 | 2862 | obj->write_domain = 0; |
1c5d22f7 CW |
2863 | |
2864 | trace_i915_gem_object_change_domain(obj, | |
2865 | obj->read_domains, | |
2866 | old_write_domain); | |
e47c68e9 EA |
2867 | } |
2868 | ||
2ef7eeaa EA |
2869 | /** |
2870 | * Moves a single object to the GTT read, and possibly write domain. | |
2871 | * | |
2872 | * This function returns when the move is complete, including waiting on | |
2873 | * flushes to occur. | |
2874 | */ | |
79e53945 | 2875 | int |
2ef7eeaa EA |
2876 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2877 | { | |
23010e43 | 2878 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2879 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2880 | int ret; |
2ef7eeaa | 2881 | |
02354392 EA |
2882 | /* Not valid to be called on unbound objects. */ |
2883 | if (obj_priv->gtt_space == NULL) | |
2884 | return -EINVAL; | |
2885 | ||
ba3d8d74 | 2886 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
2dafb1e0 CW |
2887 | if (ret != 0) |
2888 | return ret; | |
2889 | ||
7213342d | 2890 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2891 | |
ba3d8d74 | 2892 | if (write) { |
2cf34d7b | 2893 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2894 | if (ret) |
2895 | return ret; | |
ba3d8d74 | 2896 | } |
e47c68e9 | 2897 | |
1c5d22f7 CW |
2898 | old_write_domain = obj->write_domain; |
2899 | old_read_domains = obj->read_domains; | |
2900 | ||
e47c68e9 EA |
2901 | /* It should now be out of any other write domains, and we can update |
2902 | * the domain values for our changes. | |
2903 | */ | |
2904 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2905 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2906 | if (write) { | |
7213342d | 2907 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2908 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2909 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2910 | } |
2911 | ||
1c5d22f7 CW |
2912 | trace_i915_gem_object_change_domain(obj, |
2913 | old_read_domains, | |
2914 | old_write_domain); | |
2915 | ||
e47c68e9 EA |
2916 | return 0; |
2917 | } | |
2918 | ||
b9241ea3 ZW |
2919 | /* |
2920 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2921 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2922 | */ | |
2923 | int | |
48b956c5 CW |
2924 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2925 | bool pipelined) | |
b9241ea3 | 2926 | { |
23010e43 | 2927 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2928 | uint32_t old_read_domains; |
b9241ea3 ZW |
2929 | int ret; |
2930 | ||
2931 | /* Not valid to be called on unbound objects. */ | |
2932 | if (obj_priv->gtt_space == NULL) | |
2933 | return -EINVAL; | |
2934 | ||
ced270fa | 2935 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
2dafb1e0 CW |
2936 | if (ret) |
2937 | return ret; | |
b9241ea3 | 2938 | |
ced270fa CW |
2939 | /* Currently, we are always called from an non-interruptible context. */ |
2940 | if (!pipelined) { | |
2941 | ret = i915_gem_object_wait_rendering(obj, false); | |
2942 | if (ret) | |
b9241ea3 ZW |
2943 | return ret; |
2944 | } | |
2945 | ||
b118c1e3 CW |
2946 | i915_gem_object_flush_cpu_write_domain(obj); |
2947 | ||
b9241ea3 | 2948 | old_read_domains = obj->read_domains; |
c78ec30b | 2949 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2950 | |
2951 | trace_i915_gem_object_change_domain(obj, | |
2952 | old_read_domains, | |
ba3d8d74 | 2953 | obj->write_domain); |
b9241ea3 ZW |
2954 | |
2955 | return 0; | |
2956 | } | |
2957 | ||
e47c68e9 EA |
2958 | /** |
2959 | * Moves a single object to the CPU read, and possibly write domain. | |
2960 | * | |
2961 | * This function returns when the move is complete, including waiting on | |
2962 | * flushes to occur. | |
2963 | */ | |
2964 | static int | |
2965 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2966 | { | |
1c5d22f7 | 2967 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2968 | int ret; |
2969 | ||
ba3d8d74 | 2970 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2971 | if (ret != 0) |
2972 | return ret; | |
2ef7eeaa | 2973 | |
e47c68e9 | 2974 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2975 | |
e47c68e9 EA |
2976 | /* If we have a partially-valid cache of the object in the CPU, |
2977 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2978 | */ |
e47c68e9 | 2979 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2980 | |
7213342d | 2981 | if (write) { |
2cf34d7b | 2982 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
2983 | if (ret) |
2984 | return ret; | |
2985 | } | |
2986 | ||
1c5d22f7 CW |
2987 | old_write_domain = obj->write_domain; |
2988 | old_read_domains = obj->read_domains; | |
2989 | ||
e47c68e9 EA |
2990 | /* Flush the CPU cache if it's still invalid. */ |
2991 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2992 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2993 | |
e47c68e9 | 2994 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2995 | } |
2996 | ||
2997 | /* It should now be out of any other write domains, and we can update | |
2998 | * the domain values for our changes. | |
2999 | */ | |
e47c68e9 EA |
3000 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3001 | ||
3002 | /* If we're writing through the CPU, then the GPU read domains will | |
3003 | * need to be invalidated at next use. | |
3004 | */ | |
3005 | if (write) { | |
c78ec30b | 3006 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
3007 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
3008 | } | |
2ef7eeaa | 3009 | |
1c5d22f7 CW |
3010 | trace_i915_gem_object_change_domain(obj, |
3011 | old_read_domains, | |
3012 | old_write_domain); | |
3013 | ||
2ef7eeaa EA |
3014 | return 0; |
3015 | } | |
3016 | ||
673a394b EA |
3017 | /* |
3018 | * Set the next domain for the specified object. This | |
3019 | * may not actually perform the necessary flushing/invaliding though, | |
3020 | * as that may want to be batched with other set_domain operations | |
3021 | * | |
3022 | * This is (we hope) the only really tricky part of gem. The goal | |
3023 | * is fairly simple -- track which caches hold bits of the object | |
3024 | * and make sure they remain coherent. A few concrete examples may | |
3025 | * help to explain how it works. For shorthand, we use the notation | |
3026 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3027 | * a pair of read and write domain masks. | |
3028 | * | |
3029 | * Case 1: the batch buffer | |
3030 | * | |
3031 | * 1. Allocated | |
3032 | * 2. Written by CPU | |
3033 | * 3. Mapped to GTT | |
3034 | * 4. Read by GPU | |
3035 | * 5. Unmapped from GTT | |
3036 | * 6. Freed | |
3037 | * | |
3038 | * Let's take these a step at a time | |
3039 | * | |
3040 | * 1. Allocated | |
3041 | * Pages allocated from the kernel may still have | |
3042 | * cache contents, so we set them to (CPU, CPU) always. | |
3043 | * 2. Written by CPU (using pwrite) | |
3044 | * The pwrite function calls set_domain (CPU, CPU) and | |
3045 | * this function does nothing (as nothing changes) | |
3046 | * 3. Mapped by GTT | |
3047 | * This function asserts that the object is not | |
3048 | * currently in any GPU-based read or write domains | |
3049 | * 4. Read by GPU | |
3050 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3051 | * As write_domain is zero, this function adds in the | |
3052 | * current read domains (CPU+COMMAND, 0). | |
3053 | * flush_domains is set to CPU. | |
3054 | * invalidate_domains is set to COMMAND | |
3055 | * clflush is run to get data out of the CPU caches | |
3056 | * then i915_dev_set_domain calls i915_gem_flush to | |
3057 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3058 | * 5. Unmapped from GTT | |
3059 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3060 | * flush_domains and invalidate_domains end up both zero | |
3061 | * so no flushing/invalidating happens | |
3062 | * 6. Freed | |
3063 | * yay, done | |
3064 | * | |
3065 | * Case 2: The shared render buffer | |
3066 | * | |
3067 | * 1. Allocated | |
3068 | * 2. Mapped to GTT | |
3069 | * 3. Read/written by GPU | |
3070 | * 4. set_domain to (CPU,CPU) | |
3071 | * 5. Read/written by CPU | |
3072 | * 6. Read/written by GPU | |
3073 | * | |
3074 | * 1. Allocated | |
3075 | * Same as last example, (CPU, CPU) | |
3076 | * 2. Mapped to GTT | |
3077 | * Nothing changes (assertions find that it is not in the GPU) | |
3078 | * 3. Read/written by GPU | |
3079 | * execbuffer calls set_domain (RENDER, RENDER) | |
3080 | * flush_domains gets CPU | |
3081 | * invalidate_domains gets GPU | |
3082 | * clflush (obj) | |
3083 | * MI_FLUSH and drm_agp_chipset_flush | |
3084 | * 4. set_domain (CPU, CPU) | |
3085 | * flush_domains gets GPU | |
3086 | * invalidate_domains gets CPU | |
3087 | * wait_rendering (obj) to make sure all drawing is complete. | |
3088 | * This will include an MI_FLUSH to get the data from GPU | |
3089 | * to memory | |
3090 | * clflush (obj) to invalidate the CPU cache | |
3091 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3092 | * 5. Read/written by CPU | |
3093 | * cache lines are loaded and dirtied | |
3094 | * 6. Read written by GPU | |
3095 | * Same as last GPU access | |
3096 | * | |
3097 | * Case 3: The constant buffer | |
3098 | * | |
3099 | * 1. Allocated | |
3100 | * 2. Written by CPU | |
3101 | * 3. Read by GPU | |
3102 | * 4. Updated (written) by CPU again | |
3103 | * 5. Read by GPU | |
3104 | * | |
3105 | * 1. Allocated | |
3106 | * (CPU, CPU) | |
3107 | * 2. Written by CPU | |
3108 | * (CPU, CPU) | |
3109 | * 3. Read by GPU | |
3110 | * (CPU+RENDER, 0) | |
3111 | * flush_domains = CPU | |
3112 | * invalidate_domains = RENDER | |
3113 | * clflush (obj) | |
3114 | * MI_FLUSH | |
3115 | * drm_agp_chipset_flush | |
3116 | * 4. Updated (written) by CPU again | |
3117 | * (CPU, CPU) | |
3118 | * flush_domains = 0 (no previous write domain) | |
3119 | * invalidate_domains = 0 (no new read domains) | |
3120 | * 5. Read by GPU | |
3121 | * (CPU+RENDER, 0) | |
3122 | * flush_domains = CPU | |
3123 | * invalidate_domains = RENDER | |
3124 | * clflush (obj) | |
3125 | * MI_FLUSH | |
3126 | * drm_agp_chipset_flush | |
3127 | */ | |
c0d90829 | 3128 | static void |
b6651458 CW |
3129 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
3130 | struct intel_ring_buffer *ring) | |
673a394b EA |
3131 | { |
3132 | struct drm_device *dev = obj->dev; | |
9220434a | 3133 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 3134 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3135 | uint32_t invalidate_domains = 0; |
3136 | uint32_t flush_domains = 0; | |
652c393a | 3137 | |
673a394b EA |
3138 | /* |
3139 | * If the object isn't moving to a new write domain, | |
3140 | * let the object stay in multiple read domains | |
3141 | */ | |
8b0e378a EA |
3142 | if (obj->pending_write_domain == 0) |
3143 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3144 | |
3145 | /* | |
3146 | * Flush the current write domain if | |
3147 | * the new read domains don't match. Invalidate | |
3148 | * any read domains which differ from the old | |
3149 | * write domain | |
3150 | */ | |
8b0e378a EA |
3151 | if (obj->write_domain && |
3152 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3153 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3154 | invalidate_domains |= |
3155 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3156 | } |
3157 | /* | |
3158 | * Invalidate any read caches which may have | |
3159 | * stale data. That is, any new read domains. | |
3160 | */ | |
8b0e378a | 3161 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3162 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3163 | i915_gem_clflush_object(obj); |
673a394b | 3164 | |
efbeed96 EA |
3165 | /* The actual obj->write_domain will be updated with |
3166 | * pending_write_domain after we emit the accumulated flush for all | |
3167 | * of our domain changes in execbuffers (which clears objects' | |
3168 | * write_domains). So if we have a current write domain that we | |
3169 | * aren't changing, set pending_write_domain to that. | |
3170 | */ | |
3171 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3172 | obj->pending_write_domain = obj->write_domain; | |
673a394b EA |
3173 | |
3174 | dev->invalidate_domains |= invalidate_domains; | |
3175 | dev->flush_domains |= flush_domains; | |
b6651458 | 3176 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
9220434a | 3177 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
b6651458 CW |
3178 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
3179 | dev_priv->mm.flush_rings |= ring->id; | |
673a394b EA |
3180 | } |
3181 | ||
3182 | /** | |
e47c68e9 | 3183 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3184 | * |
e47c68e9 EA |
3185 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3186 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3187 | */ |
e47c68e9 EA |
3188 | static void |
3189 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3190 | { |
23010e43 | 3191 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3192 | |
e47c68e9 EA |
3193 | if (!obj_priv->page_cpu_valid) |
3194 | return; | |
3195 | ||
3196 | /* If we're partially in the CPU read domain, finish moving it in. | |
3197 | */ | |
3198 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3199 | int i; | |
3200 | ||
3201 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3202 | if (obj_priv->page_cpu_valid[i]) | |
3203 | continue; | |
856fa198 | 3204 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3205 | } |
e47c68e9 EA |
3206 | } |
3207 | ||
3208 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3209 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3210 | */ | |
9a298b2a | 3211 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3212 | obj_priv->page_cpu_valid = NULL; |
3213 | } | |
3214 | ||
3215 | /** | |
3216 | * Set the CPU read domain on a range of the object. | |
3217 | * | |
3218 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3219 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3220 | * pages have been flushed, and will be respected by | |
3221 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3222 | * of the whole object. | |
3223 | * | |
3224 | * This function returns when the move is complete, including waiting on | |
3225 | * flushes to occur. | |
3226 | */ | |
3227 | static int | |
3228 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3229 | uint64_t offset, uint64_t size) | |
3230 | { | |
23010e43 | 3231 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3232 | uint32_t old_read_domains; |
e47c68e9 | 3233 | int i, ret; |
673a394b | 3234 | |
e47c68e9 EA |
3235 | if (offset == 0 && size == obj->size) |
3236 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3237 | |
ba3d8d74 | 3238 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3239 | if (ret != 0) |
6a47baa6 | 3240 | return ret; |
e47c68e9 EA |
3241 | i915_gem_object_flush_gtt_write_domain(obj); |
3242 | ||
3243 | /* If we're already fully in the CPU read domain, we're done. */ | |
3244 | if (obj_priv->page_cpu_valid == NULL && | |
3245 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3246 | return 0; | |
673a394b | 3247 | |
e47c68e9 EA |
3248 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3249 | * newly adding I915_GEM_DOMAIN_CPU | |
3250 | */ | |
673a394b | 3251 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3252 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3253 | GFP_KERNEL); | |
e47c68e9 EA |
3254 | if (obj_priv->page_cpu_valid == NULL) |
3255 | return -ENOMEM; | |
3256 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3257 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3258 | |
3259 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3260 | * perspective. | |
3261 | */ | |
e47c68e9 EA |
3262 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3263 | i++) { | |
673a394b EA |
3264 | if (obj_priv->page_cpu_valid[i]) |
3265 | continue; | |
3266 | ||
856fa198 | 3267 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3268 | |
3269 | obj_priv->page_cpu_valid[i] = 1; | |
3270 | } | |
3271 | ||
e47c68e9 EA |
3272 | /* It should now be out of any other write domains, and we can update |
3273 | * the domain values for our changes. | |
3274 | */ | |
3275 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3276 | ||
1c5d22f7 | 3277 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3278 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3279 | ||
1c5d22f7 CW |
3280 | trace_i915_gem_object_change_domain(obj, |
3281 | old_read_domains, | |
3282 | obj->write_domain); | |
3283 | ||
673a394b EA |
3284 | return 0; |
3285 | } | |
3286 | ||
673a394b EA |
3287 | /** |
3288 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3289 | */ | |
3290 | static int | |
9af90d19 CW |
3291 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
3292 | struct drm_file *file_priv, | |
3293 | struct drm_i915_gem_exec_object2 *entry) | |
673a394b | 3294 | { |
9af90d19 | 3295 | struct drm_device *dev = obj->base.dev; |
0839ccb8 | 3296 | drm_i915_private_t *dev_priv = dev->dev_private; |
2549d6c2 | 3297 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
9af90d19 CW |
3298 | struct drm_gem_object *target_obj = NULL; |
3299 | uint32_t target_handle = 0; | |
3300 | int i, ret = 0; | |
673a394b | 3301 | |
2549d6c2 | 3302 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
673a394b | 3303 | for (i = 0; i < entry->relocation_count; i++) { |
2549d6c2 | 3304 | struct drm_i915_gem_relocation_entry reloc; |
9af90d19 | 3305 | uint32_t target_offset; |
673a394b | 3306 | |
9af90d19 CW |
3307 | if (__copy_from_user_inatomic(&reloc, |
3308 | user_relocs+i, | |
3309 | sizeof(reloc))) { | |
3310 | ret = -EFAULT; | |
3311 | break; | |
76446cac | 3312 | } |
76446cac | 3313 | |
9af90d19 CW |
3314 | if (reloc.target_handle != target_handle) { |
3315 | drm_gem_object_unreference(target_obj); | |
673a394b | 3316 | |
9af90d19 CW |
3317 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3318 | reloc.target_handle); | |
3319 | if (target_obj == NULL) { | |
3320 | ret = -ENOENT; | |
3321 | break; | |
3322 | } | |
3323 | ||
3324 | target_handle = reloc.target_handle; | |
673a394b | 3325 | } |
9af90d19 | 3326 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
673a394b | 3327 | |
8542a0bb CW |
3328 | #if WATCH_RELOC |
3329 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3330 | "read %08x write %08x gtt %08x " | |
3331 | "presumed %08x delta %08x\n", | |
3332 | __func__, | |
3333 | obj, | |
2549d6c2 CW |
3334 | (int) reloc.offset, |
3335 | (int) reloc.target_handle, | |
3336 | (int) reloc.read_domains, | |
3337 | (int) reloc.write_domain, | |
9af90d19 | 3338 | (int) target_offset, |
2549d6c2 CW |
3339 | (int) reloc.presumed_offset, |
3340 | reloc.delta); | |
8542a0bb CW |
3341 | #endif |
3342 | ||
673a394b EA |
3343 | /* The target buffer should have appeared before us in the |
3344 | * exec_object list, so it should have a GTT space bound by now. | |
3345 | */ | |
9af90d19 | 3346 | if (target_offset == 0) { |
673a394b | 3347 | DRM_ERROR("No GTT space found for object %d\n", |
2549d6c2 | 3348 | reloc.target_handle); |
9af90d19 CW |
3349 | ret = -EINVAL; |
3350 | break; | |
673a394b EA |
3351 | } |
3352 | ||
8542a0bb | 3353 | /* Validate that the target is in a valid r/w GPU domain */ |
2549d6c2 | 3354 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
16edd550 DV |
3355 | DRM_ERROR("reloc with multiple write domains: " |
3356 | "obj %p target %d offset %d " | |
3357 | "read %08x write %08x", | |
2549d6c2 CW |
3358 | obj, reloc.target_handle, |
3359 | (int) reloc.offset, | |
3360 | reloc.read_domains, | |
3361 | reloc.write_domain); | |
9af90d19 CW |
3362 | ret = -EINVAL; |
3363 | break; | |
16edd550 | 3364 | } |
2549d6c2 CW |
3365 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
3366 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3367 | DRM_ERROR("reloc with read/write CPU domains: " |
3368 | "obj %p target %d offset %d " | |
3369 | "read %08x write %08x", | |
2549d6c2 CW |
3370 | obj, reloc.target_handle, |
3371 | (int) reloc.offset, | |
3372 | reloc.read_domains, | |
3373 | reloc.write_domain); | |
9af90d19 CW |
3374 | ret = -EINVAL; |
3375 | break; | |
e47c68e9 | 3376 | } |
2549d6c2 CW |
3377 | if (reloc.write_domain && target_obj->pending_write_domain && |
3378 | reloc.write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3379 | DRM_ERROR("Write domain conflict: " |
3380 | "obj %p target %d offset %d " | |
3381 | "new %08x old %08x\n", | |
2549d6c2 CW |
3382 | obj, reloc.target_handle, |
3383 | (int) reloc.offset, | |
3384 | reloc.write_domain, | |
673a394b | 3385 | target_obj->pending_write_domain); |
9af90d19 CW |
3386 | ret = -EINVAL; |
3387 | break; | |
673a394b EA |
3388 | } |
3389 | ||
2549d6c2 | 3390 | target_obj->pending_read_domains |= reloc.read_domains; |
878a3c37 | 3391 | target_obj->pending_write_domain |= reloc.write_domain; |
673a394b EA |
3392 | |
3393 | /* If the relocation already has the right value in it, no | |
3394 | * more work needs to be done. | |
3395 | */ | |
9af90d19 | 3396 | if (target_offset == reloc.presumed_offset) |
673a394b | 3397 | continue; |
673a394b | 3398 | |
8542a0bb | 3399 | /* Check that the relocation address is valid... */ |
9af90d19 | 3400 | if (reloc.offset > obj->base.size - 4) { |
8542a0bb CW |
3401 | DRM_ERROR("Relocation beyond object bounds: " |
3402 | "obj %p target %d offset %d size %d.\n", | |
2549d6c2 | 3403 | obj, reloc.target_handle, |
9af90d19 CW |
3404 | (int) reloc.offset, (int) obj->base.size); |
3405 | ret = -EINVAL; | |
3406 | break; | |
8542a0bb | 3407 | } |
2549d6c2 | 3408 | if (reloc.offset & 3) { |
8542a0bb CW |
3409 | DRM_ERROR("Relocation not 4-byte aligned: " |
3410 | "obj %p target %d offset %d.\n", | |
2549d6c2 CW |
3411 | obj, reloc.target_handle, |
3412 | (int) reloc.offset); | |
9af90d19 CW |
3413 | ret = -EINVAL; |
3414 | break; | |
8542a0bb CW |
3415 | } |
3416 | ||
3417 | /* and points to somewhere within the target object. */ | |
2549d6c2 | 3418 | if (reloc.delta >= target_obj->size) { |
8542a0bb CW |
3419 | DRM_ERROR("Relocation beyond target object bounds: " |
3420 | "obj %p target %d delta %d size %d.\n", | |
2549d6c2 CW |
3421 | obj, reloc.target_handle, |
3422 | (int) reloc.delta, (int) target_obj->size); | |
9af90d19 CW |
3423 | ret = -EINVAL; |
3424 | break; | |
673a394b EA |
3425 | } |
3426 | ||
9af90d19 CW |
3427 | reloc.delta += target_offset; |
3428 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
f0c43d9b CW |
3429 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
3430 | char *vaddr; | |
673a394b | 3431 | |
c48c43e4 | 3432 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
f0c43d9b | 3433 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
c48c43e4 | 3434 | kunmap_atomic(vaddr); |
f0c43d9b CW |
3435 | } else { |
3436 | uint32_t __iomem *reloc_entry; | |
3437 | void __iomem *reloc_page; | |
b962442e | 3438 | |
9af90d19 CW |
3439 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
3440 | if (ret) | |
3441 | break; | |
b962442e | 3442 | |
f0c43d9b | 3443 | /* Map the page containing the relocation we're going to perform. */ |
9af90d19 | 3444 | reloc.offset += obj->gtt_offset; |
f0c43d9b | 3445 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
c48c43e4 | 3446 | reloc.offset & PAGE_MASK); |
f0c43d9b CW |
3447 | reloc_entry = (uint32_t __iomem *) |
3448 | (reloc_page + (reloc.offset & ~PAGE_MASK)); | |
3449 | iowrite32(reloc.delta, reloc_entry); | |
c48c43e4 | 3450 | io_mapping_unmap_atomic(reloc_page); |
f0c43d9b | 3451 | } |
b962442e | 3452 | |
b5dc608c CW |
3453 | /* and update the user's relocation entry */ |
3454 | reloc.presumed_offset = target_offset; | |
3455 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
3456 | &reloc.presumed_offset, | |
3457 | sizeof(reloc.presumed_offset))) { | |
3458 | ret = -EFAULT; | |
3459 | break; | |
3460 | } | |
b962442e | 3461 | } |
b962442e | 3462 | |
9af90d19 | 3463 | drm_gem_object_unreference(target_obj); |
673a394b EA |
3464 | return ret; |
3465 | } | |
3466 | ||
40a5f0de | 3467 | static int |
9af90d19 CW |
3468 | i915_gem_execbuffer_pin(struct drm_device *dev, |
3469 | struct drm_file *file, | |
3470 | struct drm_gem_object **object_list, | |
3471 | struct drm_i915_gem_exec_object2 *exec_list, | |
3472 | int count) | |
40a5f0de | 3473 | { |
9af90d19 CW |
3474 | struct drm_i915_private *dev_priv = dev->dev_private; |
3475 | int ret, i, retry; | |
40a5f0de | 3476 | |
9af90d19 CW |
3477 | /* attempt to pin all of the buffers into the GTT */ |
3478 | for (retry = 0; retry < 2; retry++) { | |
3479 | ret = 0; | |
3480 | for (i = 0; i < count; i++) { | |
3481 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
16e809ac | 3482 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
9af90d19 CW |
3483 | bool need_fence = |
3484 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3485 | obj->tiling_mode != I915_TILING_NONE; | |
3486 | ||
16e809ac DV |
3487 | /* g33/pnv can't fence buffers in the unmappable part */ |
3488 | bool need_mappable = | |
3489 | entry->relocation_count ? true : need_fence; | |
3490 | ||
9af90d19 CW |
3491 | /* Check fence reg constraints and rebind if necessary */ |
3492 | if (need_fence && | |
3493 | !i915_gem_object_fence_offset_ok(&obj->base, | |
3494 | obj->tiling_mode)) { | |
3495 | ret = i915_gem_object_unbind(&obj->base); | |
3496 | if (ret) | |
3497 | break; | |
3498 | } | |
40a5f0de | 3499 | |
920afa77 | 3500 | ret = i915_gem_object_pin(&obj->base, |
16e809ac DV |
3501 | entry->alignment, |
3502 | need_mappable); | |
9af90d19 CW |
3503 | if (ret) |
3504 | break; | |
40a5f0de | 3505 | |
9af90d19 CW |
3506 | /* |
3507 | * Pre-965 chips need a fence register set up in order | |
3508 | * to properly handle blits to/from tiled surfaces. | |
3509 | */ | |
3510 | if (need_fence) { | |
3511 | ret = i915_gem_object_get_fence_reg(&obj->base, true); | |
3512 | if (ret) { | |
3513 | i915_gem_object_unpin(&obj->base); | |
3514 | break; | |
3515 | } | |
40a5f0de | 3516 | |
9af90d19 CW |
3517 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
3518 | } | |
40a5f0de | 3519 | |
9af90d19 | 3520 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3521 | } |
3522 | ||
9af90d19 CW |
3523 | while (i--) |
3524 | i915_gem_object_unpin(object_list[i]); | |
3525 | ||
3526 | if (ret == 0) | |
3527 | break; | |
673a394b | 3528 | |
9af90d19 CW |
3529 | if (ret != -ENOSPC || retry) |
3530 | return ret; | |
3531 | ||
3532 | ret = i915_gem_evict_everything(dev); | |
3533 | if (ret) | |
3534 | return ret; | |
40a5f0de EA |
3535 | } |
3536 | ||
2bc43b5c | 3537 | return 0; |
40a5f0de EA |
3538 | } |
3539 | ||
673a394b EA |
3540 | /* Throttle our rendering by waiting until the ring has completed our requests |
3541 | * emitted over 20 msec ago. | |
3542 | * | |
b962442e EA |
3543 | * Note that if we were to use the current jiffies each time around the loop, |
3544 | * we wouldn't escape the function with any frames outstanding if the time to | |
3545 | * render a frame was over 20ms. | |
3546 | * | |
673a394b EA |
3547 | * This should get us reasonable parallelism between CPU and GPU but also |
3548 | * relatively low latency when blocking on a particular request to finish. | |
3549 | */ | |
40a5f0de | 3550 | static int |
f787a5f5 | 3551 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3552 | { |
f787a5f5 CW |
3553 | struct drm_i915_private *dev_priv = dev->dev_private; |
3554 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3555 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3556 | struct drm_i915_gem_request *request; |
3557 | struct intel_ring_buffer *ring = NULL; | |
3558 | u32 seqno = 0; | |
3559 | int ret; | |
93533c29 | 3560 | |
1c25595f | 3561 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3562 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3563 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3564 | break; | |
40a5f0de | 3565 | |
f787a5f5 CW |
3566 | ring = request->ring; |
3567 | seqno = request->seqno; | |
b962442e | 3568 | } |
1c25595f | 3569 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3570 | |
f787a5f5 CW |
3571 | if (seqno == 0) |
3572 | return 0; | |
2bc43b5c | 3573 | |
f787a5f5 | 3574 | ret = 0; |
78501eac | 3575 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3576 | /* And wait for the seqno passing without holding any locks and |
3577 | * causing extra latency for others. This is safe as the irq | |
3578 | * generation is designed to be run atomically and so is | |
3579 | * lockless. | |
3580 | */ | |
78501eac | 3581 | ring->user_irq_get(ring); |
f787a5f5 | 3582 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3583 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3584 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3585 | ring->user_irq_put(ring); |
40a5f0de | 3586 | |
f787a5f5 CW |
3587 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3588 | ret = -EIO; | |
40a5f0de EA |
3589 | } |
3590 | ||
f787a5f5 CW |
3591 | if (ret == 0) |
3592 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3593 | |
3594 | return ret; | |
3595 | } | |
3596 | ||
83d60795 | 3597 | static int |
2549d6c2 CW |
3598 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3599 | uint64_t exec_offset) | |
83d60795 CW |
3600 | { |
3601 | uint32_t exec_start, exec_len; | |
3602 | ||
3603 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3604 | exec_len = (uint32_t) exec->batch_len; | |
3605 | ||
3606 | if ((exec_start | exec_len) & 0x7) | |
3607 | return -EINVAL; | |
3608 | ||
3609 | if (!exec_start) | |
3610 | return -EINVAL; | |
3611 | ||
3612 | return 0; | |
3613 | } | |
3614 | ||
6b95a207 | 3615 | static int |
2549d6c2 CW |
3616 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3617 | int count) | |
6b95a207 | 3618 | { |
2549d6c2 | 3619 | int i; |
6b95a207 | 3620 | |
2549d6c2 CW |
3621 | for (i = 0; i < count; i++) { |
3622 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
3623 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); | |
6b95a207 | 3624 | |
2549d6c2 CW |
3625 | if (!access_ok(VERIFY_READ, ptr, length)) |
3626 | return -EFAULT; | |
40a5f0de | 3627 | |
b5dc608c CW |
3628 | /* we may also need to update the presumed offsets */ |
3629 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3630 | return -EFAULT; | |
3631 | ||
2549d6c2 CW |
3632 | if (fault_in_pages_readable(ptr, length)) |
3633 | return -EFAULT; | |
6b95a207 | 3634 | } |
6b95a207 | 3635 | |
83d60795 | 3636 | return 0; |
6b95a207 KH |
3637 | } |
3638 | ||
8dc5d147 | 3639 | static int |
76446cac | 3640 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3641 | struct drm_file *file, |
76446cac JB |
3642 | struct drm_i915_gem_execbuffer2 *args, |
3643 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3644 | { |
3645 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3646 | struct drm_gem_object **object_list = NULL; |
3647 | struct drm_gem_object *batch_obj; | |
201361a5 | 3648 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3649 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3650 | int ret, i, flips; |
673a394b | 3651 | uint64_t exec_offset; |
673a394b | 3652 | |
852835f3 ZN |
3653 | struct intel_ring_buffer *ring = NULL; |
3654 | ||
30dbf0c0 CW |
3655 | ret = i915_gem_check_is_wedged(dev); |
3656 | if (ret) | |
3657 | return ret; | |
3658 | ||
2549d6c2 CW |
3659 | ret = validate_exec_list(exec_list, args->buffer_count); |
3660 | if (ret) | |
3661 | return ret; | |
3662 | ||
673a394b EA |
3663 | #if WATCH_EXEC |
3664 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3665 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3666 | #endif | |
549f7365 CW |
3667 | switch (args->flags & I915_EXEC_RING_MASK) { |
3668 | case I915_EXEC_DEFAULT: | |
3669 | case I915_EXEC_RENDER: | |
3670 | ring = &dev_priv->render_ring; | |
3671 | break; | |
3672 | case I915_EXEC_BSD: | |
d1b851fc | 3673 | if (!HAS_BSD(dev)) { |
549f7365 | 3674 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3675 | return -EINVAL; |
3676 | } | |
3677 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3678 | break; |
3679 | case I915_EXEC_BLT: | |
3680 | if (!HAS_BLT(dev)) { | |
3681 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3682 | return -EINVAL; | |
3683 | } | |
3684 | ring = &dev_priv->blt_ring; | |
3685 | break; | |
3686 | default: | |
3687 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3688 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3689 | return -EINVAL; | |
d1b851fc ZN |
3690 | } |
3691 | ||
4f481ed2 EA |
3692 | if (args->buffer_count < 1) { |
3693 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3694 | return -EINVAL; | |
3695 | } | |
c8e0f93a | 3696 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3697 | if (object_list == NULL) { |
3698 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3699 | args->buffer_count); |
3700 | ret = -ENOMEM; | |
3701 | goto pre_mutex_err; | |
3702 | } | |
673a394b | 3703 | |
201361a5 | 3704 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3705 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3706 | GFP_KERNEL); | |
a40e8d31 OA |
3707 | if (cliprects == NULL) { |
3708 | ret = -ENOMEM; | |
201361a5 | 3709 | goto pre_mutex_err; |
a40e8d31 | 3710 | } |
201361a5 EA |
3711 | |
3712 | ret = copy_from_user(cliprects, | |
3713 | (struct drm_clip_rect __user *) | |
3714 | (uintptr_t) args->cliprects_ptr, | |
3715 | sizeof(*cliprects) * args->num_cliprects); | |
3716 | if (ret != 0) { | |
3717 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3718 | args->num_cliprects, ret); | |
c877cdce | 3719 | ret = -EFAULT; |
201361a5 EA |
3720 | goto pre_mutex_err; |
3721 | } | |
3722 | } | |
3723 | ||
8dc5d147 CW |
3724 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3725 | if (request == NULL) { | |
3726 | ret = -ENOMEM; | |
40a5f0de | 3727 | goto pre_mutex_err; |
8dc5d147 | 3728 | } |
40a5f0de | 3729 | |
76c1dec1 CW |
3730 | ret = i915_mutex_lock_interruptible(dev); |
3731 | if (ret) | |
a198bc80 | 3732 | goto pre_mutex_err; |
673a394b EA |
3733 | |
3734 | if (dev_priv->mm.suspended) { | |
673a394b | 3735 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3736 | ret = -EBUSY; |
3737 | goto pre_mutex_err; | |
673a394b EA |
3738 | } |
3739 | ||
ac94a962 | 3740 | /* Look up object handles */ |
673a394b | 3741 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3742 | struct drm_i915_gem_object *obj_priv; |
3743 | ||
9af90d19 | 3744 | object_list[i] = drm_gem_object_lookup(dev, file, |
673a394b EA |
3745 | exec_list[i].handle); |
3746 | if (object_list[i] == NULL) { | |
3747 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3748 | exec_list[i].handle, i); | |
0ce907f8 CW |
3749 | /* prevent error path from reading uninitialized data */ |
3750 | args->buffer_count = i + 1; | |
bf79cb91 | 3751 | ret = -ENOENT; |
673a394b EA |
3752 | goto err; |
3753 | } | |
b70d11da | 3754 | |
23010e43 | 3755 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3756 | if (obj_priv->in_execbuffer) { |
3757 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3758 | object_list[i]); | |
0ce907f8 CW |
3759 | /* prevent error path from reading uninitialized data */ |
3760 | args->buffer_count = i + 1; | |
bf79cb91 | 3761 | ret = -EINVAL; |
b70d11da KH |
3762 | goto err; |
3763 | } | |
3764 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3765 | } |
673a394b | 3766 | |
9af90d19 CW |
3767 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
3768 | ret = i915_gem_execbuffer_pin(dev, file, | |
3769 | object_list, exec_list, | |
3770 | args->buffer_count); | |
3771 | if (ret) | |
3772 | goto err; | |
ac94a962 | 3773 | |
9af90d19 CW |
3774 | /* The objects are in their final locations, apply the relocations. */ |
3775 | for (i = 0; i < args->buffer_count; i++) { | |
3776 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3777 | obj->base.pending_read_domains = 0; | |
3778 | obj->base.pending_write_domain = 0; | |
3779 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); | |
3780 | if (ret) | |
ac94a962 | 3781 | goto err; |
673a394b EA |
3782 | } |
3783 | ||
3784 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3785 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3786 | if (batch_obj->pending_write_domain) { |
3787 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3788 | ret = -EINVAL; | |
3789 | goto err; | |
3790 | } | |
3791 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3792 | |
9af90d19 CW |
3793 | /* Sanity check the batch buffer */ |
3794 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; | |
3795 | ret = i915_gem_check_execbuffer(args, exec_offset); | |
83d60795 CW |
3796 | if (ret != 0) { |
3797 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3798 | goto err; | |
3799 | } | |
3800 | ||
646f0f6e KP |
3801 | /* Zero the global flush/invalidate flags. These |
3802 | * will be modified as new domains are computed | |
3803 | * for each object | |
3804 | */ | |
3805 | dev->invalidate_domains = 0; | |
3806 | dev->flush_domains = 0; | |
9220434a | 3807 | dev_priv->mm.flush_rings = 0; |
7e318e18 CW |
3808 | for (i = 0; i < args->buffer_count; i++) |
3809 | i915_gem_object_set_to_gpu_domain(object_list[i], ring); | |
673a394b | 3810 | |
646f0f6e KP |
3811 | if (dev->invalidate_domains | dev->flush_domains) { |
3812 | #if WATCH_EXEC | |
3813 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3814 | __func__, | |
3815 | dev->invalidate_domains, | |
3816 | dev->flush_domains); | |
3817 | #endif | |
9af90d19 | 3818 | i915_gem_flush(dev, file, |
646f0f6e | 3819 | dev->invalidate_domains, |
9220434a CW |
3820 | dev->flush_domains, |
3821 | dev_priv->mm.flush_rings); | |
646f0f6e | 3822 | } |
673a394b | 3823 | |
673a394b EA |
3824 | #if WATCH_COHERENCY |
3825 | for (i = 0; i < args->buffer_count; i++) { | |
3826 | i915_gem_object_check_coherency(object_list[i], | |
3827 | exec_list[i].handle); | |
3828 | } | |
3829 | #endif | |
3830 | ||
673a394b | 3831 | #if WATCH_EXEC |
6911a9b8 | 3832 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3833 | args->batch_len, |
3834 | __func__, | |
3835 | ~0); | |
3836 | #endif | |
3837 | ||
e59f2bac CW |
3838 | /* Check for any pending flips. As we only maintain a flip queue depth |
3839 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3840 | * to executing the batch and avoid stalling the CPU. | |
3841 | */ | |
3842 | flips = 0; | |
3843 | for (i = 0; i < args->buffer_count; i++) { | |
3844 | if (object_list[i]->write_domain) | |
3845 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3846 | } | |
3847 | if (flips) { | |
3848 | int plane, flip_mask; | |
3849 | ||
3850 | for (plane = 0; flips >> plane; plane++) { | |
3851 | if (((flips >> plane) & 1) == 0) | |
3852 | continue; | |
3853 | ||
3854 | if (plane) | |
3855 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3856 | else | |
3857 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3858 | ||
e1f99ce6 CW |
3859 | ret = intel_ring_begin(ring, 2); |
3860 | if (ret) | |
3861 | goto err; | |
3862 | ||
78501eac CW |
3863 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
3864 | intel_ring_emit(ring, MI_NOOP); | |
3865 | intel_ring_advance(ring); | |
e59f2bac CW |
3866 | } |
3867 | } | |
3868 | ||
673a394b | 3869 | /* Exec the batchbuffer */ |
78501eac | 3870 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
3871 | if (ret) { |
3872 | DRM_ERROR("dispatch failed %d\n", ret); | |
3873 | goto err; | |
3874 | } | |
3875 | ||
673a394b EA |
3876 | for (i = 0; i < args->buffer_count; i++) { |
3877 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3878 | |
7e318e18 CW |
3879 | obj->read_domains = obj->pending_read_domains; |
3880 | obj->write_domain = obj->pending_write_domain; | |
3881 | ||
617dbe27 | 3882 | i915_gem_object_move_to_active(obj, ring); |
7e318e18 CW |
3883 | if (obj->write_domain) { |
3884 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
3885 | obj_priv->dirty = 1; | |
3886 | list_move_tail(&obj_priv->gpu_write_list, | |
64193406 | 3887 | &ring->gpu_write_list); |
7e318e18 CW |
3888 | intel_mark_busy(dev, obj); |
3889 | } | |
3890 | ||
3891 | trace_i915_gem_object_change_domain(obj, | |
3892 | obj->read_domains, | |
3893 | obj->write_domain); | |
673a394b | 3894 | } |
673a394b | 3895 | |
7e318e18 CW |
3896 | /* |
3897 | * Ensure that the commands in the batch buffer are | |
3898 | * finished before the interrupt fires | |
3899 | */ | |
3900 | i915_retire_commands(dev, ring); | |
3901 | ||
3cce469c CW |
3902 | if (i915_add_request(dev, file, request, ring)) |
3903 | ring->outstanding_lazy_request = true; | |
3904 | else | |
3905 | request = NULL; | |
673a394b | 3906 | |
673a394b | 3907 | err: |
b70d11da | 3908 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3909 | if (object_list[i] == NULL) |
3910 | break; | |
3911 | ||
3912 | to_intel_bo(object_list[i])->in_execbuffer = false; | |
aad87dff | 3913 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3914 | } |
673a394b | 3915 | |
673a394b EA |
3916 | mutex_unlock(&dev->struct_mutex); |
3917 | ||
93533c29 | 3918 | pre_mutex_err: |
8e7d2b2c | 3919 | drm_free_large(object_list); |
9a298b2a | 3920 | kfree(cliprects); |
8dc5d147 | 3921 | kfree(request); |
673a394b EA |
3922 | |
3923 | return ret; | |
3924 | } | |
3925 | ||
76446cac JB |
3926 | /* |
3927 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3928 | * list array and passes it to the real function. | |
3929 | */ | |
3930 | int | |
3931 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3932 | struct drm_file *file_priv) | |
3933 | { | |
3934 | struct drm_i915_gem_execbuffer *args = data; | |
3935 | struct drm_i915_gem_execbuffer2 exec2; | |
3936 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3937 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3938 | int ret, i; | |
3939 | ||
3940 | #if WATCH_EXEC | |
3941 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3942 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3943 | #endif | |
3944 | ||
3945 | if (args->buffer_count < 1) { | |
3946 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3947 | return -EINVAL; | |
3948 | } | |
3949 | ||
3950 | /* Copy in the exec list from userland */ | |
3951 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3952 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3953 | if (exec_list == NULL || exec2_list == NULL) { | |
3954 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3955 | args->buffer_count); | |
3956 | drm_free_large(exec_list); | |
3957 | drm_free_large(exec2_list); | |
3958 | return -ENOMEM; | |
3959 | } | |
3960 | ret = copy_from_user(exec_list, | |
3961 | (struct drm_i915_relocation_entry __user *) | |
3962 | (uintptr_t) args->buffers_ptr, | |
3963 | sizeof(*exec_list) * args->buffer_count); | |
3964 | if (ret != 0) { | |
3965 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3966 | args->buffer_count, ret); | |
3967 | drm_free_large(exec_list); | |
3968 | drm_free_large(exec2_list); | |
3969 | return -EFAULT; | |
3970 | } | |
3971 | ||
3972 | for (i = 0; i < args->buffer_count; i++) { | |
3973 | exec2_list[i].handle = exec_list[i].handle; | |
3974 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3975 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3976 | exec2_list[i].alignment = exec_list[i].alignment; | |
3977 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 3978 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
3979 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
3980 | else | |
3981 | exec2_list[i].flags = 0; | |
3982 | } | |
3983 | ||
3984 | exec2.buffers_ptr = args->buffers_ptr; | |
3985 | exec2.buffer_count = args->buffer_count; | |
3986 | exec2.batch_start_offset = args->batch_start_offset; | |
3987 | exec2.batch_len = args->batch_len; | |
3988 | exec2.DR1 = args->DR1; | |
3989 | exec2.DR4 = args->DR4; | |
3990 | exec2.num_cliprects = args->num_cliprects; | |
3991 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 3992 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
3993 | |
3994 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
3995 | if (!ret) { | |
3996 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3997 | for (i = 0; i < args->buffer_count; i++) | |
3998 | exec_list[i].offset = exec2_list[i].offset; | |
3999 | /* ... and back out to userspace */ | |
4000 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4001 | (uintptr_t) args->buffers_ptr, | |
4002 | exec_list, | |
4003 | sizeof(*exec_list) * args->buffer_count); | |
4004 | if (ret) { | |
4005 | ret = -EFAULT; | |
4006 | DRM_ERROR("failed to copy %d exec entries " | |
4007 | "back to user (%d)\n", | |
4008 | args->buffer_count, ret); | |
4009 | } | |
76446cac JB |
4010 | } |
4011 | ||
4012 | drm_free_large(exec_list); | |
4013 | drm_free_large(exec2_list); | |
4014 | return ret; | |
4015 | } | |
4016 | ||
4017 | int | |
4018 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4019 | struct drm_file *file_priv) | |
4020 | { | |
4021 | struct drm_i915_gem_execbuffer2 *args = data; | |
4022 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4023 | int ret; | |
4024 | ||
4025 | #if WATCH_EXEC | |
4026 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4027 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4028 | #endif | |
4029 | ||
4030 | if (args->buffer_count < 1) { | |
4031 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4032 | return -EINVAL; | |
4033 | } | |
4034 | ||
4035 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4036 | if (exec2_list == NULL) { | |
4037 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4038 | args->buffer_count); | |
4039 | return -ENOMEM; | |
4040 | } | |
4041 | ret = copy_from_user(exec2_list, | |
4042 | (struct drm_i915_relocation_entry __user *) | |
4043 | (uintptr_t) args->buffers_ptr, | |
4044 | sizeof(*exec2_list) * args->buffer_count); | |
4045 | if (ret != 0) { | |
4046 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4047 | args->buffer_count, ret); | |
4048 | drm_free_large(exec2_list); | |
4049 | return -EFAULT; | |
4050 | } | |
4051 | ||
4052 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4053 | if (!ret) { | |
4054 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4055 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4056 | (uintptr_t) args->buffers_ptr, | |
4057 | exec2_list, | |
4058 | sizeof(*exec2_list) * args->buffer_count); | |
4059 | if (ret) { | |
4060 | ret = -EFAULT; | |
4061 | DRM_ERROR("failed to copy %d exec entries " | |
4062 | "back to user (%d)\n", | |
4063 | args->buffer_count, ret); | |
4064 | } | |
4065 | } | |
4066 | ||
4067 | drm_free_large(exec2_list); | |
4068 | return ret; | |
4069 | } | |
4070 | ||
673a394b | 4071 | int |
920afa77 DV |
4072 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
4073 | bool mappable) | |
673a394b EA |
4074 | { |
4075 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4076 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4077 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4078 | int ret; |
4079 | ||
778c3544 | 4080 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4081 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4082 | |
4083 | if (obj_priv->gtt_space != NULL) { | |
4084 | if (alignment == 0) | |
4085 | alignment = i915_gem_get_gtt_alignment(obj); | |
16e809ac DV |
4086 | if (obj_priv->gtt_offset & (alignment - 1) || |
4087 | (mappable && !i915_gem_object_cpu_accessible(obj_priv))) { | |
ae7d49d8 CW |
4088 | WARN(obj_priv->pin_count, |
4089 | "bo is already pinned with incorrect alignment:" | |
4090 | " offset=%x, req.alignment=%x\n", | |
4091 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4092 | ret = i915_gem_object_unbind(obj); |
4093 | if (ret) | |
4094 | return ret; | |
4095 | } | |
4096 | } | |
4097 | ||
673a394b | 4098 | if (obj_priv->gtt_space == NULL) { |
920afa77 | 4099 | ret = i915_gem_object_bind_to_gtt(obj, alignment, mappable); |
9731129c | 4100 | if (ret) |
673a394b | 4101 | return ret; |
22c344e9 | 4102 | } |
76446cac | 4103 | |
673a394b EA |
4104 | obj_priv->pin_count++; |
4105 | ||
4106 | /* If the object is not active and not pending a flush, | |
4107 | * remove it from the inactive list | |
4108 | */ | |
4109 | if (obj_priv->pin_count == 1) { | |
73aa808f | 4110 | i915_gem_info_add_pin(dev_priv, obj->size); |
f13d3f73 | 4111 | if (!obj_priv->active) |
69dc4987 | 4112 | list_move_tail(&obj_priv->mm_list, |
f13d3f73 | 4113 | &dev_priv->mm.pinned_list); |
673a394b | 4114 | } |
673a394b | 4115 | |
23bc5982 | 4116 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4117 | return 0; |
4118 | } | |
4119 | ||
4120 | void | |
4121 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4122 | { | |
4123 | struct drm_device *dev = obj->dev; | |
4124 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4125 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4126 | |
23bc5982 | 4127 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4128 | obj_priv->pin_count--; |
4129 | BUG_ON(obj_priv->pin_count < 0); | |
4130 | BUG_ON(obj_priv->gtt_space == NULL); | |
4131 | ||
4132 | /* If the object is no longer pinned, and is | |
4133 | * neither active nor being flushed, then stick it on | |
4134 | * the inactive list | |
4135 | */ | |
4136 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4137 | if (!obj_priv->active) |
69dc4987 | 4138 | list_move_tail(&obj_priv->mm_list, |
673a394b | 4139 | &dev_priv->mm.inactive_list); |
73aa808f | 4140 | i915_gem_info_remove_pin(dev_priv, obj->size); |
673a394b | 4141 | } |
23bc5982 | 4142 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4143 | } |
4144 | ||
4145 | int | |
4146 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4147 | struct drm_file *file_priv) | |
4148 | { | |
4149 | struct drm_i915_gem_pin *args = data; | |
4150 | struct drm_gem_object *obj; | |
4151 | struct drm_i915_gem_object *obj_priv; | |
4152 | int ret; | |
4153 | ||
1d7cfea1 CW |
4154 | ret = i915_mutex_lock_interruptible(dev); |
4155 | if (ret) | |
4156 | return ret; | |
673a394b EA |
4157 | |
4158 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4159 | if (obj == NULL) { | |
1d7cfea1 CW |
4160 | ret = -ENOENT; |
4161 | goto unlock; | |
673a394b | 4162 | } |
23010e43 | 4163 | obj_priv = to_intel_bo(obj); |
673a394b | 4164 | |
bb6baf76 CW |
4165 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4166 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
1d7cfea1 CW |
4167 | ret = -EINVAL; |
4168 | goto out; | |
3ef94daa CW |
4169 | } |
4170 | ||
79e53945 JB |
4171 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4172 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4173 | args->handle); | |
1d7cfea1 CW |
4174 | ret = -EINVAL; |
4175 | goto out; | |
79e53945 JB |
4176 | } |
4177 | ||
4178 | obj_priv->user_pin_count++; | |
4179 | obj_priv->pin_filp = file_priv; | |
4180 | if (obj_priv->user_pin_count == 1) { | |
920afa77 | 4181 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
4182 | if (ret) |
4183 | goto out; | |
673a394b EA |
4184 | } |
4185 | ||
4186 | /* XXX - flush the CPU caches for pinned objects | |
4187 | * as the X server doesn't manage domains yet | |
4188 | */ | |
e47c68e9 | 4189 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b | 4190 | args->offset = obj_priv->gtt_offset; |
1d7cfea1 | 4191 | out: |
673a394b | 4192 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4193 | unlock: |
673a394b | 4194 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4195 | return ret; |
673a394b EA |
4196 | } |
4197 | ||
4198 | int | |
4199 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4200 | struct drm_file *file_priv) | |
4201 | { | |
4202 | struct drm_i915_gem_pin *args = data; | |
4203 | struct drm_gem_object *obj; | |
79e53945 | 4204 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4205 | int ret; |
673a394b | 4206 | |
1d7cfea1 CW |
4207 | ret = i915_mutex_lock_interruptible(dev); |
4208 | if (ret) | |
4209 | return ret; | |
673a394b EA |
4210 | |
4211 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4212 | if (obj == NULL) { | |
1d7cfea1 CW |
4213 | ret = -ENOENT; |
4214 | goto unlock; | |
673a394b | 4215 | } |
23010e43 | 4216 | obj_priv = to_intel_bo(obj); |
76c1dec1 | 4217 | |
79e53945 JB |
4218 | if (obj_priv->pin_filp != file_priv) { |
4219 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4220 | args->handle); | |
1d7cfea1 CW |
4221 | ret = -EINVAL; |
4222 | goto out; | |
79e53945 JB |
4223 | } |
4224 | obj_priv->user_pin_count--; | |
4225 | if (obj_priv->user_pin_count == 0) { | |
4226 | obj_priv->pin_filp = NULL; | |
4227 | i915_gem_object_unpin(obj); | |
4228 | } | |
673a394b | 4229 | |
1d7cfea1 | 4230 | out: |
673a394b | 4231 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4232 | unlock: |
673a394b | 4233 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4234 | return ret; |
673a394b EA |
4235 | } |
4236 | ||
4237 | int | |
4238 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4239 | struct drm_file *file_priv) | |
4240 | { | |
4241 | struct drm_i915_gem_busy *args = data; | |
4242 | struct drm_gem_object *obj; | |
4243 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4244 | int ret; |
4245 | ||
76c1dec1 | 4246 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4247 | if (ret) |
76c1dec1 | 4248 | return ret; |
673a394b | 4249 | |
673a394b EA |
4250 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4251 | if (obj == NULL) { | |
1d7cfea1 CW |
4252 | ret = -ENOENT; |
4253 | goto unlock; | |
673a394b | 4254 | } |
1d7cfea1 | 4255 | obj_priv = to_intel_bo(obj); |
d1b851fc | 4256 | |
0be555b6 CW |
4257 | /* Count all active objects as busy, even if they are currently not used |
4258 | * by the gpu. Users of this interface expect objects to eventually | |
4259 | * become non-busy without any further actions, therefore emit any | |
4260 | * necessary flushes here. | |
c4de0a5d | 4261 | */ |
0be555b6 CW |
4262 | args->busy = obj_priv->active; |
4263 | if (args->busy) { | |
4264 | /* Unconditionally flush objects, even when the gpu still uses this | |
4265 | * object. Userspace calling this function indicates that it wants to | |
4266 | * use this buffer rather sooner than later, so issuing the required | |
4267 | * flush earlier is beneficial. | |
4268 | */ | |
c78ec30b CW |
4269 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4270 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4271 | obj_priv->ring, |
4272 | 0, obj->write_domain); | |
0be555b6 CW |
4273 | |
4274 | /* Update the active list for the hardware's current position. | |
4275 | * Otherwise this only updates on a delayed timer or when irqs | |
4276 | * are actually unmasked, and our working set ends up being | |
4277 | * larger than required. | |
4278 | */ | |
4279 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4280 | ||
4281 | args->busy = obj_priv->active; | |
4282 | } | |
673a394b EA |
4283 | |
4284 | drm_gem_object_unreference(obj); | |
1d7cfea1 | 4285 | unlock: |
673a394b | 4286 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4287 | return ret; |
673a394b EA |
4288 | } |
4289 | ||
4290 | int | |
4291 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4292 | struct drm_file *file_priv) | |
4293 | { | |
4294 | return i915_gem_ring_throttle(dev, file_priv); | |
4295 | } | |
4296 | ||
3ef94daa CW |
4297 | int |
4298 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4299 | struct drm_file *file_priv) | |
4300 | { | |
4301 | struct drm_i915_gem_madvise *args = data; | |
4302 | struct drm_gem_object *obj; | |
4303 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4304 | int ret; |
3ef94daa CW |
4305 | |
4306 | switch (args->madv) { | |
4307 | case I915_MADV_DONTNEED: | |
4308 | case I915_MADV_WILLNEED: | |
4309 | break; | |
4310 | default: | |
4311 | return -EINVAL; | |
4312 | } | |
4313 | ||
1d7cfea1 CW |
4314 | ret = i915_mutex_lock_interruptible(dev); |
4315 | if (ret) | |
4316 | return ret; | |
4317 | ||
3ef94daa CW |
4318 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4319 | if (obj == NULL) { | |
1d7cfea1 CW |
4320 | ret = -ENOENT; |
4321 | goto unlock; | |
3ef94daa | 4322 | } |
23010e43 | 4323 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4324 | |
4325 | if (obj_priv->pin_count) { | |
1d7cfea1 CW |
4326 | ret = -EINVAL; |
4327 | goto out; | |
3ef94daa CW |
4328 | } |
4329 | ||
bb6baf76 CW |
4330 | if (obj_priv->madv != __I915_MADV_PURGED) |
4331 | obj_priv->madv = args->madv; | |
3ef94daa | 4332 | |
2d7ef395 CW |
4333 | /* if the object is no longer bound, discard its backing storage */ |
4334 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4335 | obj_priv->gtt_space == NULL) | |
4336 | i915_gem_object_truncate(obj); | |
4337 | ||
bb6baf76 CW |
4338 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4339 | ||
1d7cfea1 | 4340 | out: |
3ef94daa | 4341 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4342 | unlock: |
3ef94daa | 4343 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4344 | return ret; |
3ef94daa CW |
4345 | } |
4346 | ||
ac52bc56 DV |
4347 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4348 | size_t size) | |
4349 | { | |
73aa808f | 4350 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4351 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4352 | |
c397b908 DV |
4353 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4354 | if (obj == NULL) | |
4355 | return NULL; | |
673a394b | 4356 | |
c397b908 DV |
4357 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4358 | kfree(obj); | |
4359 | return NULL; | |
4360 | } | |
673a394b | 4361 | |
73aa808f CW |
4362 | i915_gem_info_add_obj(dev_priv, size); |
4363 | ||
c397b908 DV |
4364 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4365 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4366 | |
c397b908 | 4367 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4368 | obj->base.driver_private = NULL; |
c397b908 | 4369 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 CW |
4370 | INIT_LIST_HEAD(&obj->mm_list); |
4371 | INIT_LIST_HEAD(&obj->ring_list); | |
c397b908 | 4372 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4373 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4374 | |
c397b908 DV |
4375 | return &obj->base; |
4376 | } | |
4377 | ||
4378 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4379 | { | |
4380 | BUG(); | |
de151cf6 | 4381 | |
673a394b EA |
4382 | return 0; |
4383 | } | |
4384 | ||
be72615b | 4385 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4386 | { |
de151cf6 | 4387 | struct drm_device *dev = obj->dev; |
be72615b | 4388 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4389 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4390 | int ret; |
673a394b | 4391 | |
be72615b CW |
4392 | ret = i915_gem_object_unbind(obj); |
4393 | if (ret == -ERESTARTSYS) { | |
69dc4987 | 4394 | list_move(&obj_priv->mm_list, |
be72615b CW |
4395 | &dev_priv->mm.deferred_free_list); |
4396 | return; | |
4397 | } | |
673a394b | 4398 | |
7e616158 CW |
4399 | if (obj_priv->mmap_offset) |
4400 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4401 | |
c397b908 | 4402 | drm_gem_object_release(obj); |
73aa808f | 4403 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4404 | |
9a298b2a | 4405 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4406 | kfree(obj_priv->bit_17); |
c397b908 | 4407 | kfree(obj_priv); |
673a394b EA |
4408 | } |
4409 | ||
be72615b CW |
4410 | void i915_gem_free_object(struct drm_gem_object *obj) |
4411 | { | |
4412 | struct drm_device *dev = obj->dev; | |
4413 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4414 | ||
4415 | trace_i915_gem_object_destroy(obj); | |
4416 | ||
4417 | while (obj_priv->pin_count > 0) | |
4418 | i915_gem_object_unpin(obj); | |
4419 | ||
4420 | if (obj_priv->phys_obj) | |
4421 | i915_gem_detach_phys_object(dev, obj); | |
4422 | ||
4423 | i915_gem_free_object_tail(obj); | |
4424 | } | |
4425 | ||
29105ccc CW |
4426 | int |
4427 | i915_gem_idle(struct drm_device *dev) | |
4428 | { | |
4429 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4430 | int ret; | |
28dfe52a | 4431 | |
29105ccc | 4432 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4433 | |
87acb0a5 | 4434 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4435 | mutex_unlock(&dev->struct_mutex); |
4436 | return 0; | |
28dfe52a EA |
4437 | } |
4438 | ||
29105ccc | 4439 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4440 | if (ret) { |
4441 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4442 | return ret; |
6dbe2772 | 4443 | } |
673a394b | 4444 | |
29105ccc CW |
4445 | /* Under UMS, be paranoid and evict. */ |
4446 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4447 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4448 | if (ret) { |
4449 | mutex_unlock(&dev->struct_mutex); | |
4450 | return ret; | |
4451 | } | |
4452 | } | |
4453 | ||
4454 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4455 | * We need to replace this with a semaphore, or something. | |
4456 | * And not confound mm.suspended! | |
4457 | */ | |
4458 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4459 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4460 | |
4461 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4462 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4463 | |
6dbe2772 KP |
4464 | mutex_unlock(&dev->struct_mutex); |
4465 | ||
29105ccc CW |
4466 | /* Cancel the retire work handler, which should be idle now. */ |
4467 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4468 | ||
673a394b EA |
4469 | return 0; |
4470 | } | |
4471 | ||
e552eb70 JB |
4472 | /* |
4473 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4474 | * over cache flushing. | |
4475 | */ | |
8187a2b7 | 4476 | static int |
e552eb70 JB |
4477 | i915_gem_init_pipe_control(struct drm_device *dev) |
4478 | { | |
4479 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4480 | struct drm_gem_object *obj; | |
4481 | struct drm_i915_gem_object *obj_priv; | |
4482 | int ret; | |
4483 | ||
34dc4d44 | 4484 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4485 | if (obj == NULL) { |
4486 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4487 | ret = -ENOMEM; | |
4488 | goto err; | |
4489 | } | |
4490 | obj_priv = to_intel_bo(obj); | |
4491 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4492 | ||
920afa77 | 4493 | ret = i915_gem_object_pin(obj, 4096, true); |
e552eb70 JB |
4494 | if (ret) |
4495 | goto err_unref; | |
4496 | ||
4497 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4498 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4499 | if (dev_priv->seqno_page == NULL) | |
4500 | goto err_unpin; | |
4501 | ||
4502 | dev_priv->seqno_obj = obj; | |
4503 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4504 | ||
4505 | return 0; | |
4506 | ||
4507 | err_unpin: | |
4508 | i915_gem_object_unpin(obj); | |
4509 | err_unref: | |
4510 | drm_gem_object_unreference(obj); | |
4511 | err: | |
4512 | return ret; | |
4513 | } | |
4514 | ||
8187a2b7 ZN |
4515 | |
4516 | static void | |
e552eb70 JB |
4517 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4518 | { | |
4519 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4520 | struct drm_gem_object *obj; | |
4521 | struct drm_i915_gem_object *obj_priv; | |
4522 | ||
4523 | obj = dev_priv->seqno_obj; | |
4524 | obj_priv = to_intel_bo(obj); | |
4525 | kunmap(obj_priv->pages[0]); | |
4526 | i915_gem_object_unpin(obj); | |
4527 | drm_gem_object_unreference(obj); | |
4528 | dev_priv->seqno_obj = NULL; | |
4529 | ||
4530 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4531 | } |
4532 | ||
8187a2b7 ZN |
4533 | int |
4534 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4535 | { | |
4536 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4537 | int ret; | |
68f95ba9 | 4538 | |
8187a2b7 ZN |
4539 | if (HAS_PIPE_CONTROL(dev)) { |
4540 | ret = i915_gem_init_pipe_control(dev); | |
4541 | if (ret) | |
4542 | return ret; | |
4543 | } | |
68f95ba9 | 4544 | |
5c1143bb | 4545 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4546 | if (ret) |
4547 | goto cleanup_pipe_control; | |
4548 | ||
4549 | if (HAS_BSD(dev)) { | |
5c1143bb | 4550 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4551 | if (ret) |
4552 | goto cleanup_render_ring; | |
d1b851fc | 4553 | } |
68f95ba9 | 4554 | |
549f7365 CW |
4555 | if (HAS_BLT(dev)) { |
4556 | ret = intel_init_blt_ring_buffer(dev); | |
4557 | if (ret) | |
4558 | goto cleanup_bsd_ring; | |
4559 | } | |
4560 | ||
6f392d54 CW |
4561 | dev_priv->next_seqno = 1; |
4562 | ||
68f95ba9 CW |
4563 | return 0; |
4564 | ||
549f7365 | 4565 | cleanup_bsd_ring: |
78501eac | 4566 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4567 | cleanup_render_ring: |
78501eac | 4568 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
68f95ba9 CW |
4569 | cleanup_pipe_control: |
4570 | if (HAS_PIPE_CONTROL(dev)) | |
4571 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4572 | return ret; |
4573 | } | |
4574 | ||
4575 | void | |
4576 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4577 | { | |
4578 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4579 | ||
78501eac CW |
4580 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4581 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4582 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4583 | if (HAS_PIPE_CONTROL(dev)) |
4584 | i915_gem_cleanup_pipe_control(dev); | |
4585 | } | |
4586 | ||
673a394b EA |
4587 | int |
4588 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4589 | struct drm_file *file_priv) | |
4590 | { | |
4591 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4592 | int ret; | |
4593 | ||
79e53945 JB |
4594 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4595 | return 0; | |
4596 | ||
ba1234d1 | 4597 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4598 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4599 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4600 | } |
4601 | ||
673a394b | 4602 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4603 | dev_priv->mm.suspended = 0; |
4604 | ||
4605 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4606 | if (ret != 0) { |
4607 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4608 | return ret; |
d816f6ac | 4609 | } |
9bb2d6f9 | 4610 | |
69dc4987 | 4611 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4612 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4613 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4614 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4615 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4616 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4617 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4618 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4619 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4620 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4621 | |
5f35308b CW |
4622 | ret = drm_irq_install(dev); |
4623 | if (ret) | |
4624 | goto cleanup_ringbuffer; | |
dbb19d30 | 4625 | |
673a394b | 4626 | return 0; |
5f35308b CW |
4627 | |
4628 | cleanup_ringbuffer: | |
4629 | mutex_lock(&dev->struct_mutex); | |
4630 | i915_gem_cleanup_ringbuffer(dev); | |
4631 | dev_priv->mm.suspended = 1; | |
4632 | mutex_unlock(&dev->struct_mutex); | |
4633 | ||
4634 | return ret; | |
673a394b EA |
4635 | } |
4636 | ||
4637 | int | |
4638 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4639 | struct drm_file *file_priv) | |
4640 | { | |
79e53945 JB |
4641 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4642 | return 0; | |
4643 | ||
dbb19d30 | 4644 | drm_irq_uninstall(dev); |
e6890f6f | 4645 | return i915_gem_idle(dev); |
673a394b EA |
4646 | } |
4647 | ||
4648 | void | |
4649 | i915_gem_lastclose(struct drm_device *dev) | |
4650 | { | |
4651 | int ret; | |
673a394b | 4652 | |
e806b495 EA |
4653 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4654 | return; | |
4655 | ||
6dbe2772 KP |
4656 | ret = i915_gem_idle(dev); |
4657 | if (ret) | |
4658 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4659 | } |
4660 | ||
64193406 CW |
4661 | static void |
4662 | init_ring_lists(struct intel_ring_buffer *ring) | |
4663 | { | |
4664 | INIT_LIST_HEAD(&ring->active_list); | |
4665 | INIT_LIST_HEAD(&ring->request_list); | |
4666 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4667 | } | |
4668 | ||
673a394b EA |
4669 | void |
4670 | i915_gem_load(struct drm_device *dev) | |
4671 | { | |
b5aa8a0f | 4672 | int i; |
673a394b EA |
4673 | drm_i915_private_t *dev_priv = dev->dev_private; |
4674 | ||
69dc4987 | 4675 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4676 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4677 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4678 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4679 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4680 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
64193406 CW |
4681 | init_ring_lists(&dev_priv->render_ring); |
4682 | init_ring_lists(&dev_priv->bsd_ring); | |
4683 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4684 | for (i = 0; i < 16; i++) |
4685 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4686 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4687 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4688 | init_completion(&dev_priv->error_completion); |
31169714 CW |
4689 | spin_lock(&shrink_list_lock); |
4690 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4691 | spin_unlock(&shrink_list_lock); | |
4692 | ||
94400120 DA |
4693 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4694 | if (IS_GEN3(dev)) { | |
4695 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4696 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4697 | /* arb state is a masked write, so set bit + bit in mask */ | |
4698 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4699 | I915_WRITE(MI_ARB_STATE, tmp); | |
4700 | } | |
4701 | } | |
4702 | ||
de151cf6 | 4703 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4704 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4705 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4706 | |
a6c45cf0 | 4707 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4708 | dev_priv->num_fence_regs = 16; |
4709 | else | |
4710 | dev_priv->num_fence_regs = 8; | |
4711 | ||
b5aa8a0f | 4712 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4713 | switch (INTEL_INFO(dev)->gen) { |
4714 | case 6: | |
4715 | for (i = 0; i < 16; i++) | |
4716 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4717 | break; | |
4718 | case 5: | |
4719 | case 4: | |
b5aa8a0f GH |
4720 | for (i = 0; i < 16; i++) |
4721 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4722 | break; |
4723 | case 3: | |
b5aa8a0f GH |
4724 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4725 | for (i = 0; i < 8; i++) | |
4726 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4727 | case 2: |
4728 | for (i = 0; i < 8; i++) | |
4729 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4730 | break; | |
b5aa8a0f | 4731 | } |
673a394b | 4732 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4733 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4734 | } |
71acb5eb DA |
4735 | |
4736 | /* | |
4737 | * Create a physically contiguous memory object for this object | |
4738 | * e.g. for cursor + overlay regs | |
4739 | */ | |
995b6762 CW |
4740 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4741 | int id, int size, int align) | |
71acb5eb DA |
4742 | { |
4743 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4744 | struct drm_i915_gem_phys_object *phys_obj; | |
4745 | int ret; | |
4746 | ||
4747 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4748 | return 0; | |
4749 | ||
9a298b2a | 4750 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4751 | if (!phys_obj) |
4752 | return -ENOMEM; | |
4753 | ||
4754 | phys_obj->id = id; | |
4755 | ||
6eeefaf3 | 4756 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4757 | if (!phys_obj->handle) { |
4758 | ret = -ENOMEM; | |
4759 | goto kfree_obj; | |
4760 | } | |
4761 | #ifdef CONFIG_X86 | |
4762 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4763 | #endif | |
4764 | ||
4765 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4766 | ||
4767 | return 0; | |
4768 | kfree_obj: | |
9a298b2a | 4769 | kfree(phys_obj); |
71acb5eb DA |
4770 | return ret; |
4771 | } | |
4772 | ||
995b6762 | 4773 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4774 | { |
4775 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4776 | struct drm_i915_gem_phys_object *phys_obj; | |
4777 | ||
4778 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4779 | return; | |
4780 | ||
4781 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4782 | if (phys_obj->cur_obj) { | |
4783 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4784 | } | |
4785 | ||
4786 | #ifdef CONFIG_X86 | |
4787 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4788 | #endif | |
4789 | drm_pci_free(dev, phys_obj->handle); | |
4790 | kfree(phys_obj); | |
4791 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4792 | } | |
4793 | ||
4794 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4795 | { | |
4796 | int i; | |
4797 | ||
260883c8 | 4798 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4799 | i915_gem_free_phys_object(dev, i); |
4800 | } | |
4801 | ||
4802 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4803 | struct drm_gem_object *obj) | |
4804 | { | |
4805 | struct drm_i915_gem_object *obj_priv; | |
4806 | int i; | |
4807 | int ret; | |
4808 | int page_count; | |
4809 | ||
23010e43 | 4810 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4811 | if (!obj_priv->phys_obj) |
4812 | return; | |
4813 | ||
4bdadb97 | 4814 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4815 | if (ret) |
4816 | goto out; | |
4817 | ||
4818 | page_count = obj->size / PAGE_SIZE; | |
4819 | ||
4820 | for (i = 0; i < page_count; i++) { | |
3e4d3af5 | 4821 | char *dst = kmap_atomic(obj_priv->pages[i]); |
71acb5eb DA |
4822 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4823 | ||
4824 | memcpy(dst, src, PAGE_SIZE); | |
3e4d3af5 | 4825 | kunmap_atomic(dst); |
71acb5eb | 4826 | } |
856fa198 | 4827 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4828 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4829 | |
4830 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4831 | out: |
4832 | obj_priv->phys_obj->cur_obj = NULL; | |
4833 | obj_priv->phys_obj = NULL; | |
4834 | } | |
4835 | ||
4836 | int | |
4837 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4838 | struct drm_gem_object *obj, |
4839 | int id, | |
4840 | int align) | |
71acb5eb DA |
4841 | { |
4842 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4843 | struct drm_i915_gem_object *obj_priv; | |
4844 | int ret = 0; | |
4845 | int page_count; | |
4846 | int i; | |
4847 | ||
4848 | if (id > I915_MAX_PHYS_OBJECT) | |
4849 | return -EINVAL; | |
4850 | ||
23010e43 | 4851 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4852 | |
4853 | if (obj_priv->phys_obj) { | |
4854 | if (obj_priv->phys_obj->id == id) | |
4855 | return 0; | |
4856 | i915_gem_detach_phys_object(dev, obj); | |
4857 | } | |
4858 | ||
71acb5eb DA |
4859 | /* create a new object */ |
4860 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4861 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4862 | obj->size, align); |
71acb5eb | 4863 | if (ret) { |
aeb565df | 4864 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4865 | goto out; |
4866 | } | |
4867 | } | |
4868 | ||
4869 | /* bind to the object */ | |
4870 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4871 | obj_priv->phys_obj->cur_obj = obj; | |
4872 | ||
4bdadb97 | 4873 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4874 | if (ret) { |
4875 | DRM_ERROR("failed to get page list\n"); | |
4876 | goto out; | |
4877 | } | |
4878 | ||
4879 | page_count = obj->size / PAGE_SIZE; | |
4880 | ||
4881 | for (i = 0; i < page_count; i++) { | |
3e4d3af5 | 4882 | char *src = kmap_atomic(obj_priv->pages[i]); |
71acb5eb DA |
4883 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4884 | ||
4885 | memcpy(dst, src, PAGE_SIZE); | |
3e4d3af5 | 4886 | kunmap_atomic(src); |
71acb5eb DA |
4887 | } |
4888 | ||
d78b47b9 CW |
4889 | i915_gem_object_put_pages(obj); |
4890 | ||
71acb5eb DA |
4891 | return 0; |
4892 | out: | |
4893 | return ret; | |
4894 | } | |
4895 | ||
4896 | static int | |
4897 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4898 | struct drm_i915_gem_pwrite *args, | |
4899 | struct drm_file *file_priv) | |
4900 | { | |
23010e43 | 4901 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4902 | void *obj_addr; |
4903 | int ret; | |
4904 | char __user *user_data; | |
4905 | ||
4906 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4907 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4908 | ||
44d98a61 | 4909 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4910 | ret = copy_from_user(obj_addr, user_data, args->size); |
4911 | if (ret) | |
4912 | return -EFAULT; | |
4913 | ||
4914 | drm_agp_chipset_flush(dev); | |
4915 | return 0; | |
4916 | } | |
b962442e | 4917 | |
f787a5f5 | 4918 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4919 | { |
f787a5f5 | 4920 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4921 | |
4922 | /* Clean up our request list when the client is going away, so that | |
4923 | * later retire_requests won't dereference our soon-to-be-gone | |
4924 | * file_priv. | |
4925 | */ | |
1c25595f | 4926 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4927 | while (!list_empty(&file_priv->mm.request_list)) { |
4928 | struct drm_i915_gem_request *request; | |
4929 | ||
4930 | request = list_first_entry(&file_priv->mm.request_list, | |
4931 | struct drm_i915_gem_request, | |
4932 | client_list); | |
4933 | list_del(&request->client_list); | |
4934 | request->file_priv = NULL; | |
4935 | } | |
1c25595f | 4936 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4937 | } |
31169714 | 4938 | |
1637ef41 CW |
4939 | static int |
4940 | i915_gpu_is_active(struct drm_device *dev) | |
4941 | { | |
4942 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4943 | int lists_empty; | |
4944 | ||
1637ef41 | 4945 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
87acb0a5 | 4946 | list_empty(&dev_priv->render_ring.active_list) && |
549f7365 CW |
4947 | list_empty(&dev_priv->bsd_ring.active_list) && |
4948 | list_empty(&dev_priv->blt_ring.active_list); | |
1637ef41 CW |
4949 | |
4950 | return !lists_empty; | |
4951 | } | |
4952 | ||
31169714 | 4953 | static int |
7f8275d0 | 4954 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
4955 | { |
4956 | drm_i915_private_t *dev_priv, *next_dev; | |
4957 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4958 | int cnt = 0; | |
4959 | int would_deadlock = 1; | |
4960 | ||
4961 | /* "fast-path" to count number of available objects */ | |
4962 | if (nr_to_scan == 0) { | |
4963 | spin_lock(&shrink_list_lock); | |
4964 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4965 | struct drm_device *dev = dev_priv->dev; | |
4966 | ||
4967 | if (mutex_trylock(&dev->struct_mutex)) { | |
4968 | list_for_each_entry(obj_priv, | |
4969 | &dev_priv->mm.inactive_list, | |
69dc4987 | 4970 | mm_list) |
31169714 CW |
4971 | cnt++; |
4972 | mutex_unlock(&dev->struct_mutex); | |
4973 | } | |
4974 | } | |
4975 | spin_unlock(&shrink_list_lock); | |
4976 | ||
4977 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4978 | } | |
4979 | ||
4980 | spin_lock(&shrink_list_lock); | |
4981 | ||
1637ef41 | 4982 | rescan: |
31169714 CW |
4983 | /* first scan for clean buffers */ |
4984 | list_for_each_entry_safe(dev_priv, next_dev, | |
4985 | &shrink_list, mm.shrink_list) { | |
4986 | struct drm_device *dev = dev_priv->dev; | |
4987 | ||
4988 | if (! mutex_trylock(&dev->struct_mutex)) | |
4989 | continue; | |
4990 | ||
4991 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 4992 | i915_gem_retire_requests(dev); |
31169714 CW |
4993 | |
4994 | list_for_each_entry_safe(obj_priv, next_obj, | |
4995 | &dev_priv->mm.inactive_list, | |
69dc4987 | 4996 | mm_list) { |
31169714 | 4997 | if (i915_gem_object_is_purgeable(obj_priv)) { |
a8089e84 | 4998 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4999 | if (--nr_to_scan <= 0) |
5000 | break; | |
5001 | } | |
5002 | } | |
5003 | ||
5004 | spin_lock(&shrink_list_lock); | |
5005 | mutex_unlock(&dev->struct_mutex); | |
5006 | ||
963b4836 CW |
5007 | would_deadlock = 0; |
5008 | ||
31169714 CW |
5009 | if (nr_to_scan <= 0) |
5010 | break; | |
5011 | } | |
5012 | ||
5013 | /* second pass, evict/count anything still on the inactive list */ | |
5014 | list_for_each_entry_safe(dev_priv, next_dev, | |
5015 | &shrink_list, mm.shrink_list) { | |
5016 | struct drm_device *dev = dev_priv->dev; | |
5017 | ||
5018 | if (! mutex_trylock(&dev->struct_mutex)) | |
5019 | continue; | |
5020 | ||
5021 | spin_unlock(&shrink_list_lock); | |
5022 | ||
5023 | list_for_each_entry_safe(obj_priv, next_obj, | |
5024 | &dev_priv->mm.inactive_list, | |
69dc4987 | 5025 | mm_list) { |
31169714 | 5026 | if (nr_to_scan > 0) { |
a8089e84 | 5027 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5028 | nr_to_scan--; |
5029 | } else | |
5030 | cnt++; | |
5031 | } | |
5032 | ||
5033 | spin_lock(&shrink_list_lock); | |
5034 | mutex_unlock(&dev->struct_mutex); | |
5035 | ||
5036 | would_deadlock = 0; | |
5037 | } | |
5038 | ||
1637ef41 CW |
5039 | if (nr_to_scan) { |
5040 | int active = 0; | |
5041 | ||
5042 | /* | |
5043 | * We are desperate for pages, so as a last resort, wait | |
5044 | * for the GPU to finish and discard whatever we can. | |
5045 | * This has a dramatic impact to reduce the number of | |
5046 | * OOM-killer events whilst running the GPU aggressively. | |
5047 | */ | |
5048 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5049 | struct drm_device *dev = dev_priv->dev; | |
5050 | ||
5051 | if (!mutex_trylock(&dev->struct_mutex)) | |
5052 | continue; | |
5053 | ||
5054 | spin_unlock(&shrink_list_lock); | |
5055 | ||
5056 | if (i915_gpu_is_active(dev)) { | |
5057 | i915_gpu_idle(dev); | |
5058 | active++; | |
5059 | } | |
5060 | ||
5061 | spin_lock(&shrink_list_lock); | |
5062 | mutex_unlock(&dev->struct_mutex); | |
5063 | } | |
5064 | ||
5065 | if (active) | |
5066 | goto rescan; | |
5067 | } | |
5068 | ||
31169714 CW |
5069 | spin_unlock(&shrink_list_lock); |
5070 | ||
5071 | if (would_deadlock) | |
5072 | return -1; | |
5073 | else if (cnt > 0) | |
5074 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5075 | else | |
5076 | return 0; | |
5077 | } | |
5078 | ||
5079 | static struct shrinker shrinker = { | |
5080 | .shrink = i915_gem_shrink, | |
5081 | .seeks = DEFAULT_SEEKS, | |
5082 | }; | |
5083 | ||
5084 | __init void | |
5085 | i915_gem_shrinker_init(void) | |
5086 | { | |
5087 | register_shrinker(&shrinker); | |
5088 | } | |
5089 | ||
5090 | __exit void | |
5091 | i915_gem_shrinker_exit(void) | |
5092 | { | |
5093 | unregister_shrinker(&shrinker); | |
5094 | } |