Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 | 53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
920afa77 | 54 | unsigned alignment, bool mappable); |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
5cdf5881 CW |
61 | static int |
62 | i915_gem_object_get_pages(struct drm_gem_object *obj, | |
63 | gfp_t gfpmask); | |
64 | ||
65 | static void | |
66 | i915_gem_object_put_pages(struct drm_gem_object *obj); | |
67 | ||
31169714 CW |
68 | static LIST_HEAD(shrink_list); |
69 | static DEFINE_SPINLOCK(shrink_list_lock); | |
70 | ||
73aa808f CW |
71 | /* some bookkeeping */ |
72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
73 | size_t size) | |
74 | { | |
75 | dev_priv->mm.object_count++; | |
76 | dev_priv->mm.object_memory += size; | |
77 | } | |
78 | ||
79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
80 | size_t size) | |
81 | { | |
82 | dev_priv->mm.object_count--; | |
83 | dev_priv->mm.object_memory -= size; | |
84 | } | |
85 | ||
86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
fb7d516a | 87 | struct drm_gem_object *obj) |
73aa808f | 88 | { |
fb7d516a | 89 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 90 | dev_priv->mm.gtt_count++; |
fb7d516a DV |
91 | dev_priv->mm.gtt_memory += obj->size; |
92 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
93 | dev_priv->mm.mappable_gtt_used += | |
94 | min_t(size_t, obj->size, | |
95 | dev_priv->mm.gtt_mappable_end | |
96 | - obj_priv->gtt_offset); | |
97 | } | |
73aa808f CW |
98 | } |
99 | ||
100 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
fb7d516a | 101 | struct drm_gem_object *obj) |
73aa808f | 102 | { |
fb7d516a | 103 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 104 | dev_priv->mm.gtt_count--; |
fb7d516a DV |
105 | dev_priv->mm.gtt_memory -= obj->size; |
106 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
107 | dev_priv->mm.mappable_gtt_used -= | |
108 | min_t(size_t, obj->size, | |
109 | dev_priv->mm.gtt_mappable_end | |
110 | - obj_priv->gtt_offset); | |
111 | } | |
112 | } | |
113 | ||
114 | /** | |
115 | * Update the mappable working set counters. Call _only_ when there is a change | |
116 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. | |
117 | * @mappable: new state the changed mappable flag (either pin_ or fault_). | |
118 | */ | |
119 | static void | |
120 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, | |
121 | struct drm_gem_object *obj, | |
122 | bool mappable) | |
123 | { | |
124 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
125 | ||
126 | if (mappable) { | |
127 | if (obj_priv->pin_mappable && obj_priv->fault_mappable) | |
128 | /* Combined state was already mappable. */ | |
129 | return; | |
130 | dev_priv->mm.gtt_mappable_count++; | |
131 | dev_priv->mm.gtt_mappable_memory += obj->size; | |
132 | } else { | |
133 | if (obj_priv->pin_mappable || obj_priv->fault_mappable) | |
134 | /* Combined state still mappable. */ | |
135 | return; | |
136 | dev_priv->mm.gtt_mappable_count--; | |
137 | dev_priv->mm.gtt_mappable_memory -= obj->size; | |
138 | } | |
73aa808f CW |
139 | } |
140 | ||
141 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
fb7d516a DV |
142 | struct drm_gem_object *obj, |
143 | bool mappable) | |
73aa808f | 144 | { |
fb7d516a | 145 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 146 | dev_priv->mm.pin_count++; |
fb7d516a DV |
147 | dev_priv->mm.pin_memory += obj->size; |
148 | if (mappable) { | |
149 | obj_priv->pin_mappable = true; | |
150 | i915_gem_info_update_mappable(dev_priv, obj, true); | |
151 | } | |
73aa808f CW |
152 | } |
153 | ||
154 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
fb7d516a | 155 | struct drm_gem_object *obj) |
73aa808f | 156 | { |
fb7d516a | 157 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
73aa808f | 158 | dev_priv->mm.pin_count--; |
fb7d516a DV |
159 | dev_priv->mm.pin_memory -= obj->size; |
160 | if (obj_priv->pin_mappable) { | |
161 | obj_priv->pin_mappable = false; | |
162 | i915_gem_info_update_mappable(dev_priv, obj, false); | |
163 | } | |
73aa808f CW |
164 | } |
165 | ||
30dbf0c0 CW |
166 | int |
167 | i915_gem_check_is_wedged(struct drm_device *dev) | |
168 | { | |
169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
170 | struct completion *x = &dev_priv->error_completion; | |
171 | unsigned long flags; | |
172 | int ret; | |
173 | ||
174 | if (!atomic_read(&dev_priv->mm.wedged)) | |
175 | return 0; | |
176 | ||
177 | ret = wait_for_completion_interruptible(x); | |
178 | if (ret) | |
179 | return ret; | |
180 | ||
181 | /* Success, we reset the GPU! */ | |
182 | if (!atomic_read(&dev_priv->mm.wedged)) | |
183 | return 0; | |
184 | ||
185 | /* GPU is hung, bump the completion count to account for | |
186 | * the token we just consumed so that we never hit zero and | |
187 | * end up waiting upon a subsequent completion event that | |
188 | * will never happen. | |
189 | */ | |
190 | spin_lock_irqsave(&x->wait.lock, flags); | |
191 | x->done++; | |
192 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
193 | return -EIO; | |
194 | } | |
195 | ||
76c1dec1 CW |
196 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
197 | { | |
198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
199 | int ret; | |
200 | ||
201 | ret = i915_gem_check_is_wedged(dev); | |
202 | if (ret) | |
203 | return ret; | |
204 | ||
205 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
206 | if (ret) | |
207 | return ret; | |
208 | ||
209 | if (atomic_read(&dev_priv->mm.wedged)) { | |
210 | mutex_unlock(&dev->struct_mutex); | |
211 | return -EAGAIN; | |
212 | } | |
213 | ||
23bc5982 | 214 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
215 | return 0; |
216 | } | |
30dbf0c0 | 217 | |
7d1c4804 CW |
218 | static inline bool |
219 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
220 | { | |
221 | return obj_priv->gtt_space && | |
222 | !obj_priv->active && | |
223 | obj_priv->pin_count == 0; | |
224 | } | |
225 | ||
73aa808f CW |
226 | int i915_gem_do_init(struct drm_device *dev, |
227 | unsigned long start, | |
53984635 | 228 | unsigned long mappable_end, |
79e53945 | 229 | unsigned long end) |
673a394b EA |
230 | { |
231 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 232 | |
79e53945 JB |
233 | if (start >= end || |
234 | (start & (PAGE_SIZE - 1)) != 0 || | |
235 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
236 | return -EINVAL; |
237 | } | |
238 | ||
79e53945 JB |
239 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
240 | end - start); | |
673a394b | 241 | |
73aa808f | 242 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 243 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 244 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 JB |
245 | |
246 | return 0; | |
247 | } | |
673a394b | 248 | |
79e53945 JB |
249 | int |
250 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
251 | struct drm_file *file_priv) | |
252 | { | |
253 | struct drm_i915_gem_init *args = data; | |
254 | int ret; | |
255 | ||
256 | mutex_lock(&dev->struct_mutex); | |
53984635 | 257 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
258 | mutex_unlock(&dev->struct_mutex); |
259 | ||
79e53945 | 260 | return ret; |
673a394b EA |
261 | } |
262 | ||
5a125c3c EA |
263 | int |
264 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
265 | struct drm_file *file_priv) | |
266 | { | |
73aa808f | 267 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 268 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
269 | |
270 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
271 | return -ENODEV; | |
272 | ||
73aa808f CW |
273 | mutex_lock(&dev->struct_mutex); |
274 | args->aper_size = dev_priv->mm.gtt_total; | |
275 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
276 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
277 | |
278 | return 0; | |
279 | } | |
280 | ||
673a394b EA |
281 | |
282 | /** | |
283 | * Creates a new mm object and returns a handle to it. | |
284 | */ | |
285 | int | |
286 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
287 | struct drm_file *file_priv) | |
288 | { | |
289 | struct drm_i915_gem_create *args = data; | |
290 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
291 | int ret; |
292 | u32 handle; | |
673a394b EA |
293 | |
294 | args->size = roundup(args->size, PAGE_SIZE); | |
295 | ||
296 | /* Allocate the new object */ | |
ac52bc56 | 297 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
298 | if (obj == NULL) |
299 | return -ENOMEM; | |
300 | ||
301 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 302 | if (ret) { |
202f2fef CW |
303 | drm_gem_object_release(obj); |
304 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
305 | kfree(obj); | |
673a394b | 306 | return ret; |
1dfd9754 | 307 | } |
673a394b | 308 | |
202f2fef CW |
309 | /* drop reference from allocate - handle holds it now */ |
310 | drm_gem_object_unreference(obj); | |
311 | trace_i915_gem_object_create(obj); | |
312 | ||
1dfd9754 | 313 | args->handle = handle; |
673a394b EA |
314 | return 0; |
315 | } | |
316 | ||
16e809ac DV |
317 | static bool |
318 | i915_gem_object_cpu_accessible(struct drm_i915_gem_object *obj) | |
319 | { | |
320 | struct drm_device *dev = obj->base.dev; | |
321 | drm_i915_private_t *dev_priv = dev->dev_private; | |
322 | ||
323 | return obj->gtt_space == NULL || | |
324 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; | |
325 | } | |
326 | ||
eb01459f EA |
327 | static inline int |
328 | fast_shmem_read(struct page **pages, | |
329 | loff_t page_base, int page_offset, | |
330 | char __user *data, | |
331 | int length) | |
332 | { | |
b5e4feb6 | 333 | char *vaddr; |
4f27b75d | 334 | int ret; |
eb01459f | 335 | |
3e4d3af5 | 336 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
4f27b75d | 337 | ret = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
3e4d3af5 | 338 | kunmap_atomic(vaddr); |
eb01459f | 339 | |
4f27b75d | 340 | return ret; |
eb01459f EA |
341 | } |
342 | ||
280b713b EA |
343 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
344 | { | |
345 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 346 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
347 | |
348 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
349 | obj_priv->tiling_mode != I915_TILING_NONE; | |
350 | } | |
351 | ||
99a03df5 | 352 | static inline void |
40123c1f EA |
353 | slow_shmem_copy(struct page *dst_page, |
354 | int dst_offset, | |
355 | struct page *src_page, | |
356 | int src_offset, | |
357 | int length) | |
358 | { | |
359 | char *dst_vaddr, *src_vaddr; | |
360 | ||
99a03df5 CW |
361 | dst_vaddr = kmap(dst_page); |
362 | src_vaddr = kmap(src_page); | |
40123c1f EA |
363 | |
364 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
365 | ||
99a03df5 CW |
366 | kunmap(src_page); |
367 | kunmap(dst_page); | |
40123c1f EA |
368 | } |
369 | ||
99a03df5 | 370 | static inline void |
280b713b EA |
371 | slow_shmem_bit17_copy(struct page *gpu_page, |
372 | int gpu_offset, | |
373 | struct page *cpu_page, | |
374 | int cpu_offset, | |
375 | int length, | |
376 | int is_read) | |
377 | { | |
378 | char *gpu_vaddr, *cpu_vaddr; | |
379 | ||
380 | /* Use the unswizzled path if this page isn't affected. */ | |
381 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
382 | if (is_read) | |
383 | return slow_shmem_copy(cpu_page, cpu_offset, | |
384 | gpu_page, gpu_offset, length); | |
385 | else | |
386 | return slow_shmem_copy(gpu_page, gpu_offset, | |
387 | cpu_page, cpu_offset, length); | |
388 | } | |
389 | ||
99a03df5 CW |
390 | gpu_vaddr = kmap(gpu_page); |
391 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
392 | |
393 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
394 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
395 | */ | |
396 | while (length > 0) { | |
397 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
398 | int this_length = min(cacheline_end - gpu_offset, length); | |
399 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
400 | ||
401 | if (is_read) { | |
402 | memcpy(cpu_vaddr + cpu_offset, | |
403 | gpu_vaddr + swizzled_gpu_offset, | |
404 | this_length); | |
405 | } else { | |
406 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
407 | cpu_vaddr + cpu_offset, | |
408 | this_length); | |
409 | } | |
410 | cpu_offset += this_length; | |
411 | gpu_offset += this_length; | |
412 | length -= this_length; | |
413 | } | |
414 | ||
99a03df5 CW |
415 | kunmap(cpu_page); |
416 | kunmap(gpu_page); | |
280b713b EA |
417 | } |
418 | ||
eb01459f EA |
419 | /** |
420 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
421 | * from the backing pages of the object to the user's address space. On a | |
422 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
423 | */ | |
424 | static int | |
425 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
426 | struct drm_i915_gem_pread *args, | |
427 | struct drm_file *file_priv) | |
428 | { | |
23010e43 | 429 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
430 | ssize_t remain; |
431 | loff_t offset, page_base; | |
432 | char __user *user_data; | |
433 | int page_offset, page_length; | |
eb01459f EA |
434 | |
435 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
436 | remain = args->size; | |
437 | ||
23010e43 | 438 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
439 | offset = args->offset; |
440 | ||
441 | while (remain > 0) { | |
442 | /* Operation in this page | |
443 | * | |
444 | * page_base = page offset within aperture | |
445 | * page_offset = offset within page | |
446 | * page_length = bytes to copy for this page | |
447 | */ | |
448 | page_base = (offset & ~(PAGE_SIZE-1)); | |
449 | page_offset = offset & (PAGE_SIZE-1); | |
450 | page_length = remain; | |
451 | if ((page_offset + remain) > PAGE_SIZE) | |
452 | page_length = PAGE_SIZE - page_offset; | |
453 | ||
4f27b75d CW |
454 | if (fast_shmem_read(obj_priv->pages, |
455 | page_base, page_offset, | |
456 | user_data, page_length)) | |
457 | return -EFAULT; | |
eb01459f EA |
458 | |
459 | remain -= page_length; | |
460 | user_data += page_length; | |
461 | offset += page_length; | |
462 | } | |
463 | ||
4f27b75d | 464 | return 0; |
eb01459f EA |
465 | } |
466 | ||
07f73f69 CW |
467 | static int |
468 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
469 | { | |
470 | int ret; | |
471 | ||
4bdadb97 | 472 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
473 | |
474 | /* If we've insufficient memory to map in the pages, attempt | |
475 | * to make some space by throwing out some old buffers. | |
476 | */ | |
477 | if (ret == -ENOMEM) { | |
478 | struct drm_device *dev = obj->dev; | |
07f73f69 | 479 | |
0108a3ed | 480 | ret = i915_gem_evict_something(dev, obj->size, |
a6e0aa42 DV |
481 | i915_gem_get_gtt_alignment(obj), |
482 | false); | |
07f73f69 CW |
483 | if (ret) |
484 | return ret; | |
485 | ||
4bdadb97 | 486 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
487 | } |
488 | ||
489 | return ret; | |
490 | } | |
491 | ||
eb01459f EA |
492 | /** |
493 | * This is the fallback shmem pread path, which allocates temporary storage | |
494 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
495 | * can copy out of the object's backing pages while holding the struct mutex | |
496 | * and not take page faults. | |
497 | */ | |
498 | static int | |
499 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
500 | struct drm_i915_gem_pread *args, | |
501 | struct drm_file *file_priv) | |
502 | { | |
23010e43 | 503 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
504 | struct mm_struct *mm = current->mm; |
505 | struct page **user_pages; | |
506 | ssize_t remain; | |
507 | loff_t offset, pinned_pages, i; | |
508 | loff_t first_data_page, last_data_page, num_pages; | |
509 | int shmem_page_index, shmem_page_offset; | |
510 | int data_page_index, data_page_offset; | |
511 | int page_length; | |
512 | int ret; | |
513 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 514 | int do_bit17_swizzling; |
eb01459f EA |
515 | |
516 | remain = args->size; | |
517 | ||
518 | /* Pin the user pages containing the data. We can't fault while | |
519 | * holding the struct mutex, yet we want to hold it while | |
520 | * dereferencing the user data. | |
521 | */ | |
522 | first_data_page = data_ptr / PAGE_SIZE; | |
523 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
524 | num_pages = last_data_page - first_data_page + 1; | |
525 | ||
4f27b75d | 526 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
527 | if (user_pages == NULL) |
528 | return -ENOMEM; | |
529 | ||
4f27b75d | 530 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
531 | down_read(&mm->mmap_sem); |
532 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 533 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 534 | up_read(&mm->mmap_sem); |
4f27b75d | 535 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
536 | if (pinned_pages < num_pages) { |
537 | ret = -EFAULT; | |
4f27b75d | 538 | goto out; |
eb01459f EA |
539 | } |
540 | ||
4f27b75d CW |
541 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
542 | args->offset, | |
543 | args->size); | |
07f73f69 | 544 | if (ret) |
4f27b75d | 545 | goto out; |
eb01459f | 546 | |
4f27b75d | 547 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 548 | |
23010e43 | 549 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
550 | offset = args->offset; |
551 | ||
552 | while (remain > 0) { | |
553 | /* Operation in this page | |
554 | * | |
555 | * shmem_page_index = page number within shmem file | |
556 | * shmem_page_offset = offset within page in shmem file | |
557 | * data_page_index = page number in get_user_pages return | |
558 | * data_page_offset = offset with data_page_index page. | |
559 | * page_length = bytes to copy for this page | |
560 | */ | |
561 | shmem_page_index = offset / PAGE_SIZE; | |
562 | shmem_page_offset = offset & ~PAGE_MASK; | |
563 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
564 | data_page_offset = data_ptr & ~PAGE_MASK; | |
565 | ||
566 | page_length = remain; | |
567 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
568 | page_length = PAGE_SIZE - shmem_page_offset; | |
569 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
570 | page_length = PAGE_SIZE - data_page_offset; | |
571 | ||
280b713b | 572 | if (do_bit17_swizzling) { |
99a03df5 | 573 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 574 | shmem_page_offset, |
99a03df5 CW |
575 | user_pages[data_page_index], |
576 | data_page_offset, | |
577 | page_length, | |
578 | 1); | |
579 | } else { | |
580 | slow_shmem_copy(user_pages[data_page_index], | |
581 | data_page_offset, | |
582 | obj_priv->pages[shmem_page_index], | |
583 | shmem_page_offset, | |
584 | page_length); | |
280b713b | 585 | } |
eb01459f EA |
586 | |
587 | remain -= page_length; | |
588 | data_ptr += page_length; | |
589 | offset += page_length; | |
590 | } | |
591 | ||
4f27b75d | 592 | out: |
eb01459f EA |
593 | for (i = 0; i < pinned_pages; i++) { |
594 | SetPageDirty(user_pages[i]); | |
595 | page_cache_release(user_pages[i]); | |
596 | } | |
8e7d2b2c | 597 | drm_free_large(user_pages); |
eb01459f EA |
598 | |
599 | return ret; | |
600 | } | |
601 | ||
673a394b EA |
602 | /** |
603 | * Reads data from the object referenced by handle. | |
604 | * | |
605 | * On error, the contents of *data are undefined. | |
606 | */ | |
607 | int | |
608 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
609 | struct drm_file *file_priv) | |
610 | { | |
611 | struct drm_i915_gem_pread *args = data; | |
612 | struct drm_gem_object *obj; | |
613 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 614 | int ret = 0; |
673a394b | 615 | |
4f27b75d | 616 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 617 | if (ret) |
4f27b75d | 618 | return ret; |
673a394b EA |
619 | |
620 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1d7cfea1 CW |
621 | if (obj == NULL) { |
622 | ret = -ENOENT; | |
623 | goto unlock; | |
4f27b75d | 624 | } |
23010e43 | 625 | obj_priv = to_intel_bo(obj); |
673a394b | 626 | |
7dcd2499 CW |
627 | /* Bounds check source. */ |
628 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 629 | ret = -EINVAL; |
35b62a89 | 630 | goto out; |
ce9d419d CW |
631 | } |
632 | ||
35b62a89 CW |
633 | if (args->size == 0) |
634 | goto out; | |
635 | ||
ce9d419d CW |
636 | if (!access_ok(VERIFY_WRITE, |
637 | (char __user *)(uintptr_t)args->data_ptr, | |
638 | args->size)) { | |
639 | ret = -EFAULT; | |
35b62a89 | 640 | goto out; |
673a394b EA |
641 | } |
642 | ||
b5e4feb6 CW |
643 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
644 | args->size); | |
645 | if (ret) { | |
646 | ret = -EFAULT; | |
647 | goto out; | |
280b713b | 648 | } |
673a394b | 649 | |
4f27b75d CW |
650 | ret = i915_gem_object_get_pages_or_evict(obj); |
651 | if (ret) | |
652 | goto out; | |
653 | ||
654 | ret = i915_gem_object_set_cpu_read_domain_range(obj, | |
655 | args->offset, | |
656 | args->size); | |
657 | if (ret) | |
658 | goto out_put; | |
659 | ||
660 | ret = -EFAULT; | |
661 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
280b713b | 662 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
4f27b75d CW |
663 | if (ret == -EFAULT) |
664 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); | |
673a394b | 665 | |
4f27b75d CW |
666 | out_put: |
667 | i915_gem_object_put_pages(obj); | |
35b62a89 | 668 | out: |
4f27b75d | 669 | drm_gem_object_unreference(obj); |
1d7cfea1 | 670 | unlock: |
4f27b75d | 671 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 672 | return ret; |
673a394b EA |
673 | } |
674 | ||
0839ccb8 KP |
675 | /* This is the fast write path which cannot handle |
676 | * page faults in the source data | |
9b7530cc | 677 | */ |
0839ccb8 KP |
678 | |
679 | static inline int | |
680 | fast_user_write(struct io_mapping *mapping, | |
681 | loff_t page_base, int page_offset, | |
682 | char __user *user_data, | |
683 | int length) | |
9b7530cc | 684 | { |
9b7530cc | 685 | char *vaddr_atomic; |
0839ccb8 | 686 | unsigned long unwritten; |
9b7530cc | 687 | |
3e4d3af5 | 688 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
689 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
690 | user_data, length); | |
3e4d3af5 | 691 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 692 | return unwritten; |
0839ccb8 KP |
693 | } |
694 | ||
695 | /* Here's the write path which can sleep for | |
696 | * page faults | |
697 | */ | |
698 | ||
ab34c226 | 699 | static inline void |
3de09aa3 EA |
700 | slow_kernel_write(struct io_mapping *mapping, |
701 | loff_t gtt_base, int gtt_offset, | |
702 | struct page *user_page, int user_offset, | |
703 | int length) | |
0839ccb8 | 704 | { |
ab34c226 CW |
705 | char __iomem *dst_vaddr; |
706 | char *src_vaddr; | |
0839ccb8 | 707 | |
ab34c226 CW |
708 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
709 | src_vaddr = kmap(user_page); | |
710 | ||
711 | memcpy_toio(dst_vaddr + gtt_offset, | |
712 | src_vaddr + user_offset, | |
713 | length); | |
714 | ||
715 | kunmap(user_page); | |
716 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
717 | } |
718 | ||
40123c1f EA |
719 | static inline int |
720 | fast_shmem_write(struct page **pages, | |
721 | loff_t page_base, int page_offset, | |
722 | char __user *data, | |
723 | int length) | |
724 | { | |
b5e4feb6 | 725 | char *vaddr; |
fbd5a26d | 726 | int ret; |
40123c1f | 727 | |
3e4d3af5 | 728 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
fbd5a26d | 729 | ret = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
3e4d3af5 | 730 | kunmap_atomic(vaddr); |
40123c1f | 731 | |
fbd5a26d | 732 | return ret; |
40123c1f EA |
733 | } |
734 | ||
3de09aa3 EA |
735 | /** |
736 | * This is the fast pwrite path, where we copy the data directly from the | |
737 | * user into the GTT, uncached. | |
738 | */ | |
673a394b | 739 | static int |
3de09aa3 EA |
740 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
741 | struct drm_i915_gem_pwrite *args, | |
742 | struct drm_file *file_priv) | |
673a394b | 743 | { |
23010e43 | 744 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 745 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 746 | ssize_t remain; |
0839ccb8 | 747 | loff_t offset, page_base; |
673a394b | 748 | char __user *user_data; |
0839ccb8 | 749 | int page_offset, page_length; |
673a394b EA |
750 | |
751 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
752 | remain = args->size; | |
673a394b | 753 | |
23010e43 | 754 | obj_priv = to_intel_bo(obj); |
673a394b | 755 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
756 | |
757 | while (remain > 0) { | |
758 | /* Operation in this page | |
759 | * | |
0839ccb8 KP |
760 | * page_base = page offset within aperture |
761 | * page_offset = offset within page | |
762 | * page_length = bytes to copy for this page | |
673a394b | 763 | */ |
0839ccb8 KP |
764 | page_base = (offset & ~(PAGE_SIZE-1)); |
765 | page_offset = offset & (PAGE_SIZE-1); | |
766 | page_length = remain; | |
767 | if ((page_offset + remain) > PAGE_SIZE) | |
768 | page_length = PAGE_SIZE - page_offset; | |
769 | ||
0839ccb8 | 770 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
771 | * source page isn't available. Return the error and we'll |
772 | * retry in the slow path. | |
0839ccb8 | 773 | */ |
fbd5a26d CW |
774 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
775 | page_offset, user_data, page_length)) | |
776 | ||
777 | return -EFAULT; | |
673a394b | 778 | |
0839ccb8 KP |
779 | remain -= page_length; |
780 | user_data += page_length; | |
781 | offset += page_length; | |
673a394b | 782 | } |
673a394b | 783 | |
fbd5a26d | 784 | return 0; |
673a394b EA |
785 | } |
786 | ||
3de09aa3 EA |
787 | /** |
788 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
789 | * the memory and maps it using kmap_atomic for copying. | |
790 | * | |
791 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
792 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
793 | */ | |
3043c60c | 794 | static int |
3de09aa3 EA |
795 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
796 | struct drm_i915_gem_pwrite *args, | |
797 | struct drm_file *file_priv) | |
673a394b | 798 | { |
23010e43 | 799 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
800 | drm_i915_private_t *dev_priv = dev->dev_private; |
801 | ssize_t remain; | |
802 | loff_t gtt_page_base, offset; | |
803 | loff_t first_data_page, last_data_page, num_pages; | |
804 | loff_t pinned_pages, i; | |
805 | struct page **user_pages; | |
806 | struct mm_struct *mm = current->mm; | |
807 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 808 | int ret; |
3de09aa3 EA |
809 | uint64_t data_ptr = args->data_ptr; |
810 | ||
811 | remain = args->size; | |
812 | ||
813 | /* Pin the user pages containing the data. We can't fault while | |
814 | * holding the struct mutex, and all of the pwrite implementations | |
815 | * want to hold it while dereferencing the user data. | |
816 | */ | |
817 | first_data_page = data_ptr / PAGE_SIZE; | |
818 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
819 | num_pages = last_data_page - first_data_page + 1; | |
820 | ||
fbd5a26d | 821 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
822 | if (user_pages == NULL) |
823 | return -ENOMEM; | |
824 | ||
fbd5a26d | 825 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
826 | down_read(&mm->mmap_sem); |
827 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
828 | num_pages, 0, 0, user_pages, NULL); | |
829 | up_read(&mm->mmap_sem); | |
fbd5a26d | 830 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
831 | if (pinned_pages < num_pages) { |
832 | ret = -EFAULT; | |
833 | goto out_unpin_pages; | |
834 | } | |
673a394b | 835 | |
3de09aa3 EA |
836 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
837 | if (ret) | |
fbd5a26d | 838 | goto out_unpin_pages; |
3de09aa3 | 839 | |
23010e43 | 840 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
841 | offset = obj_priv->gtt_offset + args->offset; |
842 | ||
843 | while (remain > 0) { | |
844 | /* Operation in this page | |
845 | * | |
846 | * gtt_page_base = page offset within aperture | |
847 | * gtt_page_offset = offset within page in aperture | |
848 | * data_page_index = page number in get_user_pages return | |
849 | * data_page_offset = offset with data_page_index page. | |
850 | * page_length = bytes to copy for this page | |
851 | */ | |
852 | gtt_page_base = offset & PAGE_MASK; | |
853 | gtt_page_offset = offset & ~PAGE_MASK; | |
854 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
855 | data_page_offset = data_ptr & ~PAGE_MASK; | |
856 | ||
857 | page_length = remain; | |
858 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
859 | page_length = PAGE_SIZE - gtt_page_offset; | |
860 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
861 | page_length = PAGE_SIZE - data_page_offset; | |
862 | ||
ab34c226 CW |
863 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
864 | gtt_page_base, gtt_page_offset, | |
865 | user_pages[data_page_index], | |
866 | data_page_offset, | |
867 | page_length); | |
3de09aa3 EA |
868 | |
869 | remain -= page_length; | |
870 | offset += page_length; | |
871 | data_ptr += page_length; | |
872 | } | |
873 | ||
3de09aa3 EA |
874 | out_unpin_pages: |
875 | for (i = 0; i < pinned_pages; i++) | |
876 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 877 | drm_free_large(user_pages); |
3de09aa3 EA |
878 | |
879 | return ret; | |
880 | } | |
881 | ||
40123c1f EA |
882 | /** |
883 | * This is the fast shmem pwrite path, which attempts to directly | |
884 | * copy_from_user into the kmapped pages backing the object. | |
885 | */ | |
3043c60c | 886 | static int |
40123c1f EA |
887 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
888 | struct drm_i915_gem_pwrite *args, | |
889 | struct drm_file *file_priv) | |
673a394b | 890 | { |
23010e43 | 891 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
892 | ssize_t remain; |
893 | loff_t offset, page_base; | |
894 | char __user *user_data; | |
895 | int page_offset, page_length; | |
40123c1f EA |
896 | |
897 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
898 | remain = args->size; | |
673a394b | 899 | |
23010e43 | 900 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
901 | offset = args->offset; |
902 | obj_priv->dirty = 1; | |
903 | ||
904 | while (remain > 0) { | |
905 | /* Operation in this page | |
906 | * | |
907 | * page_base = page offset within aperture | |
908 | * page_offset = offset within page | |
909 | * page_length = bytes to copy for this page | |
910 | */ | |
911 | page_base = (offset & ~(PAGE_SIZE-1)); | |
912 | page_offset = offset & (PAGE_SIZE-1); | |
913 | page_length = remain; | |
914 | if ((page_offset + remain) > PAGE_SIZE) | |
915 | page_length = PAGE_SIZE - page_offset; | |
916 | ||
fbd5a26d | 917 | if (fast_shmem_write(obj_priv->pages, |
40123c1f | 918 | page_base, page_offset, |
fbd5a26d CW |
919 | user_data, page_length)) |
920 | return -EFAULT; | |
40123c1f EA |
921 | |
922 | remain -= page_length; | |
923 | user_data += page_length; | |
924 | offset += page_length; | |
925 | } | |
926 | ||
fbd5a26d | 927 | return 0; |
40123c1f EA |
928 | } |
929 | ||
930 | /** | |
931 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
932 | * the memory and maps it using kmap_atomic for copying. | |
933 | * | |
934 | * This avoids taking mmap_sem for faulting on the user's address while the | |
935 | * struct_mutex is held. | |
936 | */ | |
937 | static int | |
938 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
939 | struct drm_i915_gem_pwrite *args, | |
940 | struct drm_file *file_priv) | |
941 | { | |
23010e43 | 942 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
943 | struct mm_struct *mm = current->mm; |
944 | struct page **user_pages; | |
945 | ssize_t remain; | |
946 | loff_t offset, pinned_pages, i; | |
947 | loff_t first_data_page, last_data_page, num_pages; | |
948 | int shmem_page_index, shmem_page_offset; | |
949 | int data_page_index, data_page_offset; | |
950 | int page_length; | |
951 | int ret; | |
952 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 953 | int do_bit17_swizzling; |
40123c1f EA |
954 | |
955 | remain = args->size; | |
956 | ||
957 | /* Pin the user pages containing the data. We can't fault while | |
958 | * holding the struct mutex, and all of the pwrite implementations | |
959 | * want to hold it while dereferencing the user data. | |
960 | */ | |
961 | first_data_page = data_ptr / PAGE_SIZE; | |
962 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
963 | num_pages = last_data_page - first_data_page + 1; | |
964 | ||
4f27b75d | 965 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
966 | if (user_pages == NULL) |
967 | return -ENOMEM; | |
968 | ||
fbd5a26d | 969 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
970 | down_read(&mm->mmap_sem); |
971 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
972 | num_pages, 0, 0, user_pages, NULL); | |
973 | up_read(&mm->mmap_sem); | |
fbd5a26d | 974 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
975 | if (pinned_pages < num_pages) { |
976 | ret = -EFAULT; | |
fbd5a26d | 977 | goto out; |
673a394b EA |
978 | } |
979 | ||
fbd5a26d | 980 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 981 | if (ret) |
fbd5a26d | 982 | goto out; |
40123c1f | 983 | |
fbd5a26d | 984 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 985 | |
23010e43 | 986 | obj_priv = to_intel_bo(obj); |
673a394b | 987 | offset = args->offset; |
40123c1f | 988 | obj_priv->dirty = 1; |
673a394b | 989 | |
40123c1f EA |
990 | while (remain > 0) { |
991 | /* Operation in this page | |
992 | * | |
993 | * shmem_page_index = page number within shmem file | |
994 | * shmem_page_offset = offset within page in shmem file | |
995 | * data_page_index = page number in get_user_pages return | |
996 | * data_page_offset = offset with data_page_index page. | |
997 | * page_length = bytes to copy for this page | |
998 | */ | |
999 | shmem_page_index = offset / PAGE_SIZE; | |
1000 | shmem_page_offset = offset & ~PAGE_MASK; | |
1001 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
1002 | data_page_offset = data_ptr & ~PAGE_MASK; | |
1003 | ||
1004 | page_length = remain; | |
1005 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1006 | page_length = PAGE_SIZE - shmem_page_offset; | |
1007 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
1008 | page_length = PAGE_SIZE - data_page_offset; | |
1009 | ||
280b713b | 1010 | if (do_bit17_swizzling) { |
99a03df5 | 1011 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
1012 | shmem_page_offset, |
1013 | user_pages[data_page_index], | |
1014 | data_page_offset, | |
99a03df5 CW |
1015 | page_length, |
1016 | 0); | |
1017 | } else { | |
1018 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
1019 | shmem_page_offset, | |
1020 | user_pages[data_page_index], | |
1021 | data_page_offset, | |
1022 | page_length); | |
280b713b | 1023 | } |
40123c1f EA |
1024 | |
1025 | remain -= page_length; | |
1026 | data_ptr += page_length; | |
1027 | offset += page_length; | |
673a394b EA |
1028 | } |
1029 | ||
fbd5a26d | 1030 | out: |
40123c1f EA |
1031 | for (i = 0; i < pinned_pages; i++) |
1032 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 1033 | drm_free_large(user_pages); |
673a394b | 1034 | |
40123c1f | 1035 | return ret; |
673a394b EA |
1036 | } |
1037 | ||
1038 | /** | |
1039 | * Writes data to the object referenced by handle. | |
1040 | * | |
1041 | * On error, the contents of the buffer that were to be modified are undefined. | |
1042 | */ | |
1043 | int | |
1044 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1045 | struct drm_file *file) |
673a394b EA |
1046 | { |
1047 | struct drm_i915_gem_pwrite *args = data; | |
1048 | struct drm_gem_object *obj; | |
1049 | struct drm_i915_gem_object *obj_priv; | |
1050 | int ret = 0; | |
1051 | ||
fbd5a26d | 1052 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1053 | if (ret) |
fbd5a26d | 1054 | return ret; |
1d7cfea1 CW |
1055 | |
1056 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
1057 | if (obj == NULL) { | |
1058 | ret = -ENOENT; | |
1059 | goto unlock; | |
fbd5a26d | 1060 | } |
23010e43 | 1061 | obj_priv = to_intel_bo(obj); |
673a394b | 1062 | |
fbd5a26d | 1063 | |
7dcd2499 CW |
1064 | /* Bounds check destination. */ |
1065 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1066 | ret = -EINVAL; |
35b62a89 | 1067 | goto out; |
ce9d419d CW |
1068 | } |
1069 | ||
35b62a89 CW |
1070 | if (args->size == 0) |
1071 | goto out; | |
1072 | ||
ce9d419d CW |
1073 | if (!access_ok(VERIFY_READ, |
1074 | (char __user *)(uintptr_t)args->data_ptr, | |
1075 | args->size)) { | |
1076 | ret = -EFAULT; | |
35b62a89 | 1077 | goto out; |
673a394b EA |
1078 | } |
1079 | ||
b5e4feb6 CW |
1080 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
1081 | args->size); | |
1082 | if (ret) { | |
1083 | ret = -EFAULT; | |
1084 | goto out; | |
673a394b EA |
1085 | } |
1086 | ||
1087 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1088 | * it would end up going through the fenced access, and we'll get | |
1089 | * different detiling behavior between reading and writing. | |
1090 | * pread/pwrite currently are reading and writing from the CPU | |
1091 | * perspective, requiring manual detiling by the client. | |
1092 | */ | |
71acb5eb | 1093 | if (obj_priv->phys_obj) |
fbd5a26d | 1094 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1095 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1096 | obj_priv->gtt_space && |
9b8c4a0b | 1097 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
920afa77 | 1098 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1099 | if (ret) |
1100 | goto out; | |
1101 | ||
1102 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1103 | if (ret) | |
1104 | goto out_unpin; | |
1105 | ||
1106 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1107 | if (ret == -EFAULT) | |
1108 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1109 | ||
1110 | out_unpin: | |
1111 | i915_gem_object_unpin(obj); | |
40123c1f | 1112 | } else { |
fbd5a26d CW |
1113 | ret = i915_gem_object_get_pages_or_evict(obj); |
1114 | if (ret) | |
1115 | goto out; | |
673a394b | 1116 | |
fbd5a26d CW |
1117 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1118 | if (ret) | |
1119 | goto out_put; | |
673a394b | 1120 | |
fbd5a26d CW |
1121 | ret = -EFAULT; |
1122 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1123 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1124 | if (ret == -EFAULT) | |
1125 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
1126 | ||
1127 | out_put: | |
1128 | i915_gem_object_put_pages(obj); | |
1129 | } | |
673a394b | 1130 | |
35b62a89 | 1131 | out: |
fbd5a26d | 1132 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1133 | unlock: |
fbd5a26d | 1134 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1135 | return ret; |
1136 | } | |
1137 | ||
1138 | /** | |
2ef7eeaa EA |
1139 | * Called when user space prepares to use an object with the CPU, either |
1140 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1141 | */ |
1142 | int | |
1143 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1144 | struct drm_file *file_priv) | |
1145 | { | |
a09ba7fa | 1146 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1147 | struct drm_i915_gem_set_domain *args = data; |
1148 | struct drm_gem_object *obj; | |
652c393a | 1149 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1150 | uint32_t read_domains = args->read_domains; |
1151 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1152 | int ret; |
1153 | ||
1154 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1155 | return -ENODEV; | |
1156 | ||
2ef7eeaa | 1157 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1158 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1159 | return -EINVAL; |
1160 | ||
21d509e3 | 1161 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1162 | return -EINVAL; |
1163 | ||
1164 | /* Having something in the write domain implies it's in the read | |
1165 | * domain, and only that read domain. Enforce that in the request. | |
1166 | */ | |
1167 | if (write_domain != 0 && read_domains != write_domain) | |
1168 | return -EINVAL; | |
1169 | ||
76c1dec1 | 1170 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1171 | if (ret) |
76c1dec1 | 1172 | return ret; |
1d7cfea1 | 1173 | |
673a394b | 1174 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1d7cfea1 CW |
1175 | if (obj == NULL) { |
1176 | ret = -ENOENT; | |
1177 | goto unlock; | |
76c1dec1 | 1178 | } |
23010e43 | 1179 | obj_priv = to_intel_bo(obj); |
673a394b | 1180 | |
652c393a JB |
1181 | intel_mark_busy(dev, obj); |
1182 | ||
2ef7eeaa EA |
1183 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1184 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1185 | |
a09ba7fa EA |
1186 | /* Update the LRU on the fence for the CPU access that's |
1187 | * about to occur. | |
1188 | */ | |
1189 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1190 | struct drm_i915_fence_reg *reg = |
1191 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1192 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1193 | &dev_priv->mm.fence_list); |
1194 | } | |
1195 | ||
02354392 EA |
1196 | /* Silently promote "you're not bound, there was nothing to do" |
1197 | * to success, since the client was just asking us to | |
1198 | * make sure everything was done. | |
1199 | */ | |
1200 | if (ret == -EINVAL) | |
1201 | ret = 0; | |
2ef7eeaa | 1202 | } else { |
e47c68e9 | 1203 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1204 | } |
1205 | ||
7d1c4804 CW |
1206 | /* Maintain LRU order of "inactive" objects */ |
1207 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
69dc4987 | 1208 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1209 | |
673a394b | 1210 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1211 | unlock: |
673a394b EA |
1212 | mutex_unlock(&dev->struct_mutex); |
1213 | return ret; | |
1214 | } | |
1215 | ||
1216 | /** | |
1217 | * Called when user space has done writes to this buffer | |
1218 | */ | |
1219 | int | |
1220 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1221 | struct drm_file *file_priv) | |
1222 | { | |
1223 | struct drm_i915_gem_sw_finish *args = data; | |
1224 | struct drm_gem_object *obj; | |
673a394b EA |
1225 | int ret = 0; |
1226 | ||
1227 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1228 | return -ENODEV; | |
1229 | ||
76c1dec1 | 1230 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1231 | if (ret) |
76c1dec1 | 1232 | return ret; |
1d7cfea1 | 1233 | |
673a394b EA |
1234 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1235 | if (obj == NULL) { | |
1d7cfea1 CW |
1236 | ret = -ENOENT; |
1237 | goto unlock; | |
673a394b EA |
1238 | } |
1239 | ||
673a394b | 1240 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1241 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1242 | i915_gem_object_flush_cpu_write_domain(obj); |
1243 | ||
673a394b | 1244 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1245 | unlock: |
673a394b EA |
1246 | mutex_unlock(&dev->struct_mutex); |
1247 | return ret; | |
1248 | } | |
1249 | ||
1250 | /** | |
1251 | * Maps the contents of an object, returning the address it is mapped | |
1252 | * into. | |
1253 | * | |
1254 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1255 | * imply a ref on the object itself. | |
1256 | */ | |
1257 | int | |
1258 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1259 | struct drm_file *file_priv) | |
1260 | { | |
1261 | struct drm_i915_gem_mmap *args = data; | |
1262 | struct drm_gem_object *obj; | |
1263 | loff_t offset; | |
1264 | unsigned long addr; | |
1265 | ||
1266 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1267 | return -ENODEV; | |
1268 | ||
1269 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1270 | if (obj == NULL) | |
bf79cb91 | 1271 | return -ENOENT; |
673a394b EA |
1272 | |
1273 | offset = args->offset; | |
1274 | ||
1275 | down_write(¤t->mm->mmap_sem); | |
1276 | addr = do_mmap(obj->filp, 0, args->size, | |
1277 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1278 | args->offset); | |
1279 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1280 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1281 | if (IS_ERR((void *)addr)) |
1282 | return addr; | |
1283 | ||
1284 | args->addr_ptr = (uint64_t) addr; | |
1285 | ||
1286 | return 0; | |
1287 | } | |
1288 | ||
de151cf6 JB |
1289 | /** |
1290 | * i915_gem_fault - fault a page into the GTT | |
1291 | * vma: VMA in question | |
1292 | * vmf: fault info | |
1293 | * | |
1294 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1295 | * from userspace. The fault handler takes care of binding the object to | |
1296 | * the GTT (if needed), allocating and programming a fence register (again, | |
1297 | * only if needed based on whether the old reg is still valid or the object | |
1298 | * is tiled) and inserting a new PTE into the faulting process. | |
1299 | * | |
1300 | * Note that the faulting process may involve evicting existing objects | |
1301 | * from the GTT and/or fence registers to make room. So performance may | |
1302 | * suffer if the GTT working set is large or there are few fence registers | |
1303 | * left. | |
1304 | */ | |
1305 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1306 | { | |
1307 | struct drm_gem_object *obj = vma->vm_private_data; | |
1308 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1309 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1310 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1311 | pgoff_t page_offset; |
1312 | unsigned long pfn; | |
1313 | int ret = 0; | |
0f973f27 | 1314 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1315 | |
1316 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1317 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1318 | PAGE_SHIFT; | |
1319 | ||
1320 | /* Now bind it into the GTT if needed */ | |
1321 | mutex_lock(&dev->struct_mutex); | |
fb7d516a | 1322 | BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable); |
16e809ac DV |
1323 | if (!i915_gem_object_cpu_accessible(obj_priv)) |
1324 | i915_gem_object_unbind(obj); | |
1325 | ||
de151cf6 | 1326 | if (!obj_priv->gtt_space) { |
920afa77 | 1327 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1328 | if (ret) |
1329 | goto unlock; | |
07f4f3e8 | 1330 | |
07f4f3e8 | 1331 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1332 | if (ret) |
1333 | goto unlock; | |
de151cf6 JB |
1334 | } |
1335 | ||
fb7d516a DV |
1336 | if (!obj_priv->fault_mappable) { |
1337 | obj_priv->fault_mappable = true; | |
1338 | i915_gem_info_update_mappable(dev_priv, obj, true); | |
1339 | } | |
1340 | ||
de151cf6 | 1341 | /* Need a new fence register? */ |
a09ba7fa | 1342 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1343 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1344 | if (ret) |
1345 | goto unlock; | |
d9ddcb96 | 1346 | } |
de151cf6 | 1347 | |
7d1c4804 | 1348 | if (i915_gem_object_is_inactive(obj_priv)) |
69dc4987 | 1349 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1350 | |
de151cf6 JB |
1351 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1352 | page_offset; | |
1353 | ||
1354 | /* Finally, remap it using the new GTT offset */ | |
1355 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1356 | unlock: |
de151cf6 JB |
1357 | mutex_unlock(&dev->struct_mutex); |
1358 | ||
1359 | switch (ret) { | |
c715089f CW |
1360 | case 0: |
1361 | case -ERESTARTSYS: | |
1362 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1363 | case -ENOMEM: |
1364 | case -EAGAIN: | |
1365 | return VM_FAULT_OOM; | |
de151cf6 | 1366 | default: |
c715089f | 1367 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1368 | } |
1369 | } | |
1370 | ||
1371 | /** | |
1372 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1373 | * @obj: obj in question | |
1374 | * | |
1375 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1376 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1377 | * up the object based on the offset and sets up the various memory mapping | |
1378 | * structures. | |
1379 | * | |
1380 | * This routine allocates and attaches a fake offset for @obj. | |
1381 | */ | |
1382 | static int | |
1383 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1384 | { | |
1385 | struct drm_device *dev = obj->dev; | |
1386 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1387 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1388 | struct drm_map_list *list; |
f77d390c | 1389 | struct drm_local_map *map; |
de151cf6 JB |
1390 | int ret = 0; |
1391 | ||
1392 | /* Set the object up for mmap'ing */ | |
1393 | list = &obj->map_list; | |
9a298b2a | 1394 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1395 | if (!list->map) |
1396 | return -ENOMEM; | |
1397 | ||
1398 | map = list->map; | |
1399 | map->type = _DRM_GEM; | |
1400 | map->size = obj->size; | |
1401 | map->handle = obj; | |
1402 | ||
1403 | /* Get a DRM GEM mmap offset allocated... */ | |
1404 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1405 | obj->size / PAGE_SIZE, 0, 0); | |
1406 | if (!list->file_offset_node) { | |
1407 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1408 | ret = -ENOSPC; |
de151cf6 JB |
1409 | goto out_free_list; |
1410 | } | |
1411 | ||
1412 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1413 | obj->size / PAGE_SIZE, 0); | |
1414 | if (!list->file_offset_node) { | |
1415 | ret = -ENOMEM; | |
1416 | goto out_free_list; | |
1417 | } | |
1418 | ||
1419 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1420 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1421 | if (ret) { | |
de151cf6 JB |
1422 | DRM_ERROR("failed to add to map hash\n"); |
1423 | goto out_free_mm; | |
1424 | } | |
1425 | ||
1426 | /* By now we should be all set, any drm_mmap request on the offset | |
1427 | * below will get to our mmap & fault handler */ | |
1428 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1429 | ||
1430 | return 0; | |
1431 | ||
1432 | out_free_mm: | |
1433 | drm_mm_put_block(list->file_offset_node); | |
1434 | out_free_list: | |
9a298b2a | 1435 | kfree(list->map); |
de151cf6 JB |
1436 | |
1437 | return ret; | |
1438 | } | |
1439 | ||
901782b2 CW |
1440 | /** |
1441 | * i915_gem_release_mmap - remove physical page mappings | |
1442 | * @obj: obj in question | |
1443 | * | |
af901ca1 | 1444 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1445 | * relinquish ownership of the pages back to the system. |
1446 | * | |
1447 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1448 | * object through the GTT and then lose the fence register due to | |
1449 | * resource pressure. Similarly if the object has been moved out of the | |
1450 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1451 | * mapping will then trigger a page fault on the next user access, allowing | |
1452 | * fixup by i915_gem_fault(). | |
1453 | */ | |
d05ca301 | 1454 | void |
901782b2 CW |
1455 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1456 | { | |
1457 | struct drm_device *dev = obj->dev; | |
fb7d516a | 1458 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1459 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1460 | |
1461 | if (dev->dev_mapping) | |
1462 | unmap_mapping_range(dev->dev_mapping, | |
1463 | obj_priv->mmap_offset, obj->size, 1); | |
fb7d516a DV |
1464 | |
1465 | if (obj_priv->fault_mappable) { | |
1466 | obj_priv->fault_mappable = false; | |
1467 | i915_gem_info_update_mappable(dev_priv, obj, false); | |
1468 | } | |
901782b2 CW |
1469 | } |
1470 | ||
ab00b3e5 JB |
1471 | static void |
1472 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1473 | { | |
1474 | struct drm_device *dev = obj->dev; | |
23010e43 | 1475 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1476 | struct drm_gem_mm *mm = dev->mm_private; |
1477 | struct drm_map_list *list; | |
1478 | ||
1479 | list = &obj->map_list; | |
1480 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1481 | ||
1482 | if (list->file_offset_node) { | |
1483 | drm_mm_put_block(list->file_offset_node); | |
1484 | list->file_offset_node = NULL; | |
1485 | } | |
1486 | ||
1487 | if (list->map) { | |
9a298b2a | 1488 | kfree(list->map); |
ab00b3e5 JB |
1489 | list->map = NULL; |
1490 | } | |
1491 | ||
1492 | obj_priv->mmap_offset = 0; | |
1493 | } | |
1494 | ||
de151cf6 JB |
1495 | /** |
1496 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1497 | * @obj: object to check | |
1498 | * | |
1499 | * Return the required GTT alignment for an object, taking into account | |
1500 | * potential fence register mapping if needed. | |
1501 | */ | |
1502 | static uint32_t | |
1503 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1504 | { | |
1505 | struct drm_device *dev = obj->dev; | |
23010e43 | 1506 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1507 | int start, i; |
1508 | ||
1509 | /* | |
1510 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1511 | * if a fence register is needed for the object. | |
1512 | */ | |
a6c45cf0 | 1513 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1514 | return 4096; |
1515 | ||
1516 | /* | |
1517 | * Previous chips need to be aligned to the size of the smallest | |
1518 | * fence register that can contain the object. | |
1519 | */ | |
a6c45cf0 | 1520 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1521 | start = 1024*1024; |
1522 | else | |
1523 | start = 512*1024; | |
1524 | ||
1525 | for (i = start; i < obj->size; i <<= 1) | |
1526 | ; | |
1527 | ||
1528 | return i; | |
1529 | } | |
1530 | ||
1531 | /** | |
1532 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1533 | * @dev: DRM device | |
1534 | * @data: GTT mapping ioctl data | |
1535 | * @file_priv: GEM object info | |
1536 | * | |
1537 | * Simply returns the fake offset to userspace so it can mmap it. | |
1538 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1539 | * up so we can get faults in the handler above. | |
1540 | * | |
1541 | * The fault handler will take care of binding the object into the GTT | |
1542 | * (since it may have been evicted to make room for something), allocating | |
1543 | * a fence register, and mapping the appropriate aperture address into | |
1544 | * userspace. | |
1545 | */ | |
1546 | int | |
1547 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1548 | struct drm_file *file_priv) | |
1549 | { | |
1550 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1551 | struct drm_gem_object *obj; |
1552 | struct drm_i915_gem_object *obj_priv; | |
1553 | int ret; | |
1554 | ||
1555 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1556 | return -ENODEV; | |
1557 | ||
76c1dec1 | 1558 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1559 | if (ret) |
76c1dec1 | 1560 | return ret; |
de151cf6 | 1561 | |
1d7cfea1 CW |
1562 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1563 | if (obj == NULL) { | |
1564 | ret = -ENOENT; | |
1565 | goto unlock; | |
1566 | } | |
23010e43 | 1567 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1568 | |
ab18282d CW |
1569 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1570 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1d7cfea1 CW |
1571 | ret = -EINVAL; |
1572 | goto out; | |
ab18282d CW |
1573 | } |
1574 | ||
de151cf6 JB |
1575 | if (!obj_priv->mmap_offset) { |
1576 | ret = i915_gem_create_mmap_offset(obj); | |
1d7cfea1 CW |
1577 | if (ret) |
1578 | goto out; | |
de151cf6 JB |
1579 | } |
1580 | ||
1581 | args->offset = obj_priv->mmap_offset; | |
1582 | ||
de151cf6 JB |
1583 | /* |
1584 | * Pull it into the GTT so that we have a page list (makes the | |
1585 | * initial fault faster and any subsequent flushing possible). | |
1586 | */ | |
1587 | if (!obj_priv->agp_mem) { | |
920afa77 | 1588 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
1d7cfea1 CW |
1589 | if (ret) |
1590 | goto out; | |
de151cf6 JB |
1591 | } |
1592 | ||
1d7cfea1 | 1593 | out: |
de151cf6 | 1594 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1595 | unlock: |
de151cf6 | 1596 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1597 | return ret; |
de151cf6 JB |
1598 | } |
1599 | ||
5cdf5881 | 1600 | static void |
856fa198 | 1601 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1602 | { |
23010e43 | 1603 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1604 | int page_count = obj->size / PAGE_SIZE; |
1605 | int i; | |
1606 | ||
856fa198 | 1607 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1608 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1609 | |
856fa198 EA |
1610 | if (--obj_priv->pages_refcount != 0) |
1611 | return; | |
673a394b | 1612 | |
280b713b EA |
1613 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1614 | i915_gem_object_save_bit_17_swizzle(obj); | |
1615 | ||
3ef94daa | 1616 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1617 | obj_priv->dirty = 0; |
3ef94daa CW |
1618 | |
1619 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1620 | if (obj_priv->dirty) |
1621 | set_page_dirty(obj_priv->pages[i]); | |
1622 | ||
1623 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1624 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1625 | |
1626 | page_cache_release(obj_priv->pages[i]); | |
1627 | } | |
673a394b EA |
1628 | obj_priv->dirty = 0; |
1629 | ||
8e7d2b2c | 1630 | drm_free_large(obj_priv->pages); |
856fa198 | 1631 | obj_priv->pages = NULL; |
673a394b EA |
1632 | } |
1633 | ||
a56ba56c CW |
1634 | static uint32_t |
1635 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1636 | struct intel_ring_buffer *ring) | |
1637 | { | |
1638 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1639 | ||
1640 | ring->outstanding_lazy_request = true; | |
1641 | return dev_priv->next_seqno; | |
1642 | } | |
1643 | ||
673a394b | 1644 | static void |
617dbe27 | 1645 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1646 | struct intel_ring_buffer *ring) |
673a394b EA |
1647 | { |
1648 | struct drm_device *dev = obj->dev; | |
69dc4987 | 1649 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1650 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1651 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1652 | |
852835f3 ZN |
1653 | BUG_ON(ring == NULL); |
1654 | obj_priv->ring = ring; | |
673a394b EA |
1655 | |
1656 | /* Add a reference if we're newly entering the active list. */ | |
1657 | if (!obj_priv->active) { | |
1658 | drm_gem_object_reference(obj); | |
1659 | obj_priv->active = 1; | |
1660 | } | |
e35a41de | 1661 | |
673a394b | 1662 | /* Move from whatever list we were on to the tail of execution. */ |
69dc4987 CW |
1663 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
1664 | list_move_tail(&obj_priv->ring_list, &ring->active_list); | |
ce44b0ea | 1665 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1666 | } |
1667 | ||
ce44b0ea EA |
1668 | static void |
1669 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1670 | { | |
1671 | struct drm_device *dev = obj->dev; | |
1672 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1673 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1674 | |
1675 | BUG_ON(!obj_priv->active); | |
69dc4987 CW |
1676 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
1677 | list_del_init(&obj_priv->ring_list); | |
ce44b0ea EA |
1678 | obj_priv->last_rendering_seqno = 0; |
1679 | } | |
673a394b | 1680 | |
963b4836 CW |
1681 | /* Immediately discard the backing storage */ |
1682 | static void | |
1683 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1684 | { | |
23010e43 | 1685 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1686 | struct inode *inode; |
963b4836 | 1687 | |
ae9fed6b CW |
1688 | /* Our goal here is to return as much of the memory as |
1689 | * is possible back to the system as we are called from OOM. | |
1690 | * To do this we must instruct the shmfs to drop all of its | |
1691 | * backing pages, *now*. Here we mirror the actions taken | |
1692 | * when by shmem_delete_inode() to release the backing store. | |
1693 | */ | |
bb6baf76 | 1694 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1695 | truncate_inode_pages(inode->i_mapping, 0); |
1696 | if (inode->i_op->truncate_range) | |
1697 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1698 | |
1699 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1700 | } |
1701 | ||
1702 | static inline int | |
1703 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1704 | { | |
1705 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1706 | } | |
1707 | ||
673a394b EA |
1708 | static void |
1709 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1710 | { | |
1711 | struct drm_device *dev = obj->dev; | |
1712 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1713 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1714 | |
673a394b | 1715 | if (obj_priv->pin_count != 0) |
69dc4987 | 1716 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
673a394b | 1717 | else |
69dc4987 CW |
1718 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
1719 | list_del_init(&obj_priv->ring_list); | |
673a394b | 1720 | |
99fcb766 DV |
1721 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1722 | ||
ce44b0ea | 1723 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1724 | obj_priv->ring = NULL; |
673a394b EA |
1725 | if (obj_priv->active) { |
1726 | obj_priv->active = 0; | |
1727 | drm_gem_object_unreference(obj); | |
1728 | } | |
23bc5982 | 1729 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1730 | } |
1731 | ||
63560396 DV |
1732 | static void |
1733 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1734 | uint32_t flush_domains, |
852835f3 | 1735 | struct intel_ring_buffer *ring) |
63560396 DV |
1736 | { |
1737 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1738 | struct drm_i915_gem_object *obj_priv, *next; | |
1739 | ||
1740 | list_for_each_entry_safe(obj_priv, next, | |
64193406 | 1741 | &ring->gpu_write_list, |
63560396 | 1742 | gpu_write_list) { |
a8089e84 | 1743 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1744 | |
64193406 | 1745 | if (obj->write_domain & flush_domains) { |
63560396 DV |
1746 | uint32_t old_write_domain = obj->write_domain; |
1747 | ||
1748 | obj->write_domain = 0; | |
1749 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1750 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1751 | |
1752 | /* update the fence lru list */ | |
007cc8ac DV |
1753 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1754 | struct drm_i915_fence_reg *reg = | |
1755 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1756 | list_move_tail(®->lru_list, | |
63560396 | 1757 | &dev_priv->mm.fence_list); |
007cc8ac | 1758 | } |
63560396 DV |
1759 | |
1760 | trace_i915_gem_object_change_domain(obj, | |
1761 | obj->read_domains, | |
1762 | old_write_domain); | |
1763 | } | |
1764 | } | |
1765 | } | |
8187a2b7 | 1766 | |
3cce469c | 1767 | int |
8a1a49f9 | 1768 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1769 | struct drm_file *file, |
8dc5d147 | 1770 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1771 | struct intel_ring_buffer *ring) |
673a394b EA |
1772 | { |
1773 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1774 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1775 | uint32_t seqno; |
1776 | int was_empty; | |
3cce469c CW |
1777 | int ret; |
1778 | ||
1779 | BUG_ON(request == NULL); | |
673a394b | 1780 | |
f787a5f5 CW |
1781 | if (file != NULL) |
1782 | file_priv = file->driver_priv; | |
b962442e | 1783 | |
3cce469c CW |
1784 | ret = ring->add_request(ring, &seqno); |
1785 | if (ret) | |
1786 | return ret; | |
673a394b | 1787 | |
a56ba56c | 1788 | ring->outstanding_lazy_request = false; |
673a394b EA |
1789 | |
1790 | request->seqno = seqno; | |
852835f3 | 1791 | request->ring = ring; |
673a394b | 1792 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1793 | was_empty = list_empty(&ring->request_list); |
1794 | list_add_tail(&request->list, &ring->request_list); | |
1795 | ||
f787a5f5 | 1796 | if (file_priv) { |
1c25595f | 1797 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1798 | request->file_priv = file_priv; |
b962442e | 1799 | list_add_tail(&request->client_list, |
f787a5f5 | 1800 | &file_priv->mm.request_list); |
1c25595f | 1801 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1802 | } |
673a394b | 1803 | |
f65d9421 | 1804 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1805 | mod_timer(&dev_priv->hangcheck_timer, |
1806 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1807 | if (was_empty) |
b3b079db CW |
1808 | queue_delayed_work(dev_priv->wq, |
1809 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1810 | } |
3cce469c | 1811 | return 0; |
673a394b EA |
1812 | } |
1813 | ||
1814 | /** | |
1815 | * Command execution barrier | |
1816 | * | |
1817 | * Ensures that all commands in the ring are finished | |
1818 | * before signalling the CPU | |
1819 | */ | |
8a1a49f9 | 1820 | static void |
852835f3 | 1821 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1822 | { |
673a394b | 1823 | uint32_t flush_domains = 0; |
673a394b EA |
1824 | |
1825 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1826 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1827 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1828 | |
78501eac | 1829 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1830 | } |
1831 | ||
f787a5f5 CW |
1832 | static inline void |
1833 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1834 | { |
1c25595f | 1835 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1836 | |
1c25595f CW |
1837 | if (!file_priv) |
1838 | return; | |
1c5d22f7 | 1839 | |
1c25595f CW |
1840 | spin_lock(&file_priv->mm.lock); |
1841 | list_del(&request->client_list); | |
1842 | request->file_priv = NULL; | |
1843 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1844 | } |
673a394b | 1845 | |
dfaae392 CW |
1846 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1847 | struct intel_ring_buffer *ring) | |
9375e446 | 1848 | { |
dfaae392 CW |
1849 | while (!list_empty(&ring->request_list)) { |
1850 | struct drm_i915_gem_request *request; | |
673a394b | 1851 | |
dfaae392 CW |
1852 | request = list_first_entry(&ring->request_list, |
1853 | struct drm_i915_gem_request, | |
1854 | list); | |
de151cf6 | 1855 | |
dfaae392 | 1856 | list_del(&request->list); |
f787a5f5 | 1857 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1858 | kfree(request); |
1859 | } | |
673a394b | 1860 | |
dfaae392 | 1861 | while (!list_empty(&ring->active_list)) { |
9375e446 CW |
1862 | struct drm_i915_gem_object *obj_priv; |
1863 | ||
dfaae392 | 1864 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 | 1865 | struct drm_i915_gem_object, |
69dc4987 | 1866 | ring_list); |
9375e446 CW |
1867 | |
1868 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1869 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 | 1870 | i915_gem_object_move_to_inactive(&obj_priv->base); |
673a394b EA |
1871 | } |
1872 | } | |
1873 | ||
069efc1d | 1874 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1875 | { |
77f01230 CW |
1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
1877 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1878 | int i; |
673a394b | 1879 | |
dfaae392 | 1880 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1881 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1882 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1883 | |
1884 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1885 | * to be lost on reset along with the data, so simply move the | |
1886 | * lost bo to the inactive list. | |
1887 | */ | |
1888 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1889 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1890 | struct drm_i915_gem_object, | |
69dc4987 | 1891 | mm_list); |
dfaae392 CW |
1892 | |
1893 | obj_priv->base.write_domain = 0; | |
1894 | list_del_init(&obj_priv->gpu_write_list); | |
1895 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1896 | } | |
1897 | ||
1898 | /* Move everything out of the GPU domains to ensure we do any | |
1899 | * necessary invalidation upon reuse. | |
1900 | */ | |
77f01230 CW |
1901 | list_for_each_entry(obj_priv, |
1902 | &dev_priv->mm.inactive_list, | |
69dc4987 | 1903 | mm_list) |
77f01230 CW |
1904 | { |
1905 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1906 | } | |
069efc1d CW |
1907 | |
1908 | /* The fence registers are invalidated so clear them out */ | |
1909 | for (i = 0; i < 16; i++) { | |
1910 | struct drm_i915_fence_reg *reg; | |
1911 | ||
1912 | reg = &dev_priv->fence_regs[i]; | |
1913 | if (!reg->obj) | |
1914 | continue; | |
1915 | ||
1916 | i915_gem_clear_fence_reg(reg->obj); | |
1917 | } | |
673a394b EA |
1918 | } |
1919 | ||
1920 | /** | |
1921 | * This function clears the request list as sequence numbers are passed. | |
1922 | */ | |
b09a1fec CW |
1923 | static void |
1924 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1925 | struct intel_ring_buffer *ring) | |
673a394b EA |
1926 | { |
1927 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1928 | uint32_t seqno; | |
1929 | ||
b84d5f0c CW |
1930 | if (!ring->status_page.page_addr || |
1931 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1932 | return; |
1933 | ||
23bc5982 | 1934 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1935 | |
78501eac | 1936 | seqno = ring->get_seqno(ring); |
852835f3 | 1937 | while (!list_empty(&ring->request_list)) { |
673a394b | 1938 | struct drm_i915_gem_request *request; |
673a394b | 1939 | |
852835f3 | 1940 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1941 | struct drm_i915_gem_request, |
1942 | list); | |
673a394b | 1943 | |
dfaae392 | 1944 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1945 | break; |
1946 | ||
1947 | trace_i915_gem_request_retire(dev, request->seqno); | |
1948 | ||
1949 | list_del(&request->list); | |
f787a5f5 | 1950 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1951 | kfree(request); |
1952 | } | |
673a394b | 1953 | |
b84d5f0c CW |
1954 | /* Move any buffers on the active list that are no longer referenced |
1955 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1956 | */ | |
1957 | while (!list_empty(&ring->active_list)) { | |
1958 | struct drm_gem_object *obj; | |
1959 | struct drm_i915_gem_object *obj_priv; | |
1960 | ||
1961 | obj_priv = list_first_entry(&ring->active_list, | |
1962 | struct drm_i915_gem_object, | |
69dc4987 | 1963 | ring_list); |
673a394b | 1964 | |
dfaae392 | 1965 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1966 | break; |
b84d5f0c CW |
1967 | |
1968 | obj = &obj_priv->base; | |
b84d5f0c CW |
1969 | if (obj->write_domain != 0) |
1970 | i915_gem_object_move_to_flushing(obj); | |
1971 | else | |
1972 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1973 | } |
9d34e5db CW |
1974 | |
1975 | if (unlikely (dev_priv->trace_irq_seqno && | |
1976 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 1977 | ring->user_irq_put(ring); |
9d34e5db CW |
1978 | dev_priv->trace_irq_seqno = 0; |
1979 | } | |
23bc5982 CW |
1980 | |
1981 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1982 | } |
1983 | ||
b09a1fec CW |
1984 | void |
1985 | i915_gem_retire_requests(struct drm_device *dev) | |
1986 | { | |
1987 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1988 | ||
be72615b CW |
1989 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1990 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1991 | ||
1992 | /* We must be careful that during unbind() we do not | |
1993 | * accidentally infinitely recurse into retire requests. | |
1994 | * Currently: | |
1995 | * retire -> free -> unbind -> wait -> retire_ring | |
1996 | */ | |
1997 | list_for_each_entry_safe(obj_priv, tmp, | |
1998 | &dev_priv->mm.deferred_free_list, | |
69dc4987 | 1999 | mm_list) |
be72615b CW |
2000 | i915_gem_free_object_tail(&obj_priv->base); |
2001 | } | |
2002 | ||
b09a1fec | 2003 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 2004 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 2005 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
2006 | } |
2007 | ||
75ef9da2 | 2008 | static void |
673a394b EA |
2009 | i915_gem_retire_work_handler(struct work_struct *work) |
2010 | { | |
2011 | drm_i915_private_t *dev_priv; | |
2012 | struct drm_device *dev; | |
2013 | ||
2014 | dev_priv = container_of(work, drm_i915_private_t, | |
2015 | mm.retire_work.work); | |
2016 | dev = dev_priv->dev; | |
2017 | ||
891b48cf CW |
2018 | /* Come back later if the device is busy... */ |
2019 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2020 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2021 | return; | |
2022 | } | |
2023 | ||
b09a1fec | 2024 | i915_gem_retire_requests(dev); |
d1b851fc | 2025 | |
6dbe2772 | 2026 | if (!dev_priv->mm.suspended && |
d1b851fc | 2027 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
2028 | !list_empty(&dev_priv->bsd_ring.request_list) || |
2029 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 2030 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
2031 | mutex_unlock(&dev->struct_mutex); |
2032 | } | |
2033 | ||
5a5a0c64 | 2034 | int |
852835f3 | 2035 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 2036 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2037 | { |
2038 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2039 | u32 ier; |
673a394b EA |
2040 | int ret = 0; |
2041 | ||
2042 | BUG_ON(seqno == 0); | |
2043 | ||
ba1234d1 | 2044 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
2045 | return -EAGAIN; |
2046 | ||
a56ba56c | 2047 | if (ring->outstanding_lazy_request) { |
3cce469c CW |
2048 | struct drm_i915_gem_request *request; |
2049 | ||
2050 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2051 | if (request == NULL) | |
e35a41de | 2052 | return -ENOMEM; |
3cce469c CW |
2053 | |
2054 | ret = i915_add_request(dev, NULL, request, ring); | |
2055 | if (ret) { | |
2056 | kfree(request); | |
2057 | return ret; | |
2058 | } | |
2059 | ||
2060 | seqno = request->seqno; | |
e35a41de | 2061 | } |
a56ba56c | 2062 | BUG_ON(seqno == dev_priv->next_seqno); |
ffed1d09 | 2063 | |
78501eac | 2064 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2065 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2066 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2067 | else | |
2068 | ier = I915_READ(IER); | |
802c7eb6 JB |
2069 | if (!ier) { |
2070 | DRM_ERROR("something (likely vbetool) disabled " | |
2071 | "interrupts, re-enabling\n"); | |
2072 | i915_driver_irq_preinstall(dev); | |
2073 | i915_driver_irq_postinstall(dev); | |
2074 | } | |
2075 | ||
1c5d22f7 CW |
2076 | trace_i915_gem_request_wait_begin(dev, seqno); |
2077 | ||
b2223497 | 2078 | ring->waiting_seqno = seqno; |
78501eac | 2079 | ring->user_irq_get(ring); |
48764bf4 | 2080 | if (interruptible) |
852835f3 | 2081 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2082 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2083 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2084 | else |
852835f3 | 2085 | wait_event(ring->irq_queue, |
78501eac | 2086 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2087 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2088 | |
78501eac | 2089 | ring->user_irq_put(ring); |
b2223497 | 2090 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2091 | |
2092 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2093 | } |
ba1234d1 | 2094 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2095 | ret = -EAGAIN; |
673a394b EA |
2096 | |
2097 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2098 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2099 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2100 | dev_priv->next_seqno); |
673a394b EA |
2101 | |
2102 | /* Directly dispatch request retiring. While we have the work queue | |
2103 | * to handle this, the waiter on a request often wants an associated | |
2104 | * buffer to have made it to the inactive list, and we would need | |
2105 | * a separate wait queue to handle that. | |
2106 | */ | |
2107 | if (ret == 0) | |
b09a1fec | 2108 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2109 | |
2110 | return ret; | |
2111 | } | |
2112 | ||
48764bf4 DV |
2113 | /** |
2114 | * Waits for a sequence number to be signaled, and cleans up the | |
2115 | * request and object lists appropriately for that event. | |
2116 | */ | |
2117 | static int | |
852835f3 | 2118 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2119 | struct intel_ring_buffer *ring) |
48764bf4 | 2120 | { |
852835f3 | 2121 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2122 | } |
2123 | ||
20f0cd55 | 2124 | static void |
9220434a | 2125 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2126 | struct drm_file *file_priv, |
9220434a CW |
2127 | struct intel_ring_buffer *ring, |
2128 | uint32_t invalidate_domains, | |
2129 | uint32_t flush_domains) | |
2130 | { | |
78501eac | 2131 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2132 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2133 | } | |
2134 | ||
8187a2b7 ZN |
2135 | static void |
2136 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2137 | struct drm_file *file_priv, |
8187a2b7 | 2138 | uint32_t invalidate_domains, |
9220434a CW |
2139 | uint32_t flush_domains, |
2140 | uint32_t flush_rings) | |
8187a2b7 ZN |
2141 | { |
2142 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2143 | |
8187a2b7 ZN |
2144 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2145 | drm_agp_chipset_flush(dev); | |
8bff917c | 2146 | |
9220434a CW |
2147 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2148 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2149 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2150 | &dev_priv->render_ring, |
2151 | invalidate_domains, flush_domains); | |
2152 | if (flush_rings & RING_BSD) | |
c78ec30b | 2153 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2154 | &dev_priv->bsd_ring, |
2155 | invalidate_domains, flush_domains); | |
549f7365 CW |
2156 | if (flush_rings & RING_BLT) |
2157 | i915_gem_flush_ring(dev, file_priv, | |
2158 | &dev_priv->blt_ring, | |
2159 | invalidate_domains, flush_domains); | |
9220434a | 2160 | } |
8187a2b7 ZN |
2161 | } |
2162 | ||
673a394b EA |
2163 | /** |
2164 | * Ensures that all rendering to the object has completed and the object is | |
2165 | * safe to unbind from the GTT or access from the CPU. | |
2166 | */ | |
2167 | static int | |
2cf34d7b CW |
2168 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2169 | bool interruptible) | |
673a394b EA |
2170 | { |
2171 | struct drm_device *dev = obj->dev; | |
23010e43 | 2172 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2173 | int ret; |
2174 | ||
e47c68e9 EA |
2175 | /* This function only exists to support waiting for existing rendering, |
2176 | * not for emitting required flushes. | |
673a394b | 2177 | */ |
e47c68e9 | 2178 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2179 | |
2180 | /* If there is rendering queued on the buffer being evicted, wait for | |
2181 | * it. | |
2182 | */ | |
2183 | if (obj_priv->active) { | |
2cf34d7b CW |
2184 | ret = i915_do_wait_request(dev, |
2185 | obj_priv->last_rendering_seqno, | |
2186 | interruptible, | |
2187 | obj_priv->ring); | |
2188 | if (ret) | |
673a394b EA |
2189 | return ret; |
2190 | } | |
2191 | ||
2192 | return 0; | |
2193 | } | |
2194 | ||
2195 | /** | |
2196 | * Unbinds an object from the GTT aperture. | |
2197 | */ | |
0f973f27 | 2198 | int |
673a394b EA |
2199 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2200 | { | |
2201 | struct drm_device *dev = obj->dev; | |
73aa808f | 2202 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2203 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2204 | int ret = 0; |
2205 | ||
673a394b EA |
2206 | if (obj_priv->gtt_space == NULL) |
2207 | return 0; | |
2208 | ||
2209 | if (obj_priv->pin_count != 0) { | |
2210 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2211 | return -EINVAL; | |
2212 | } | |
2213 | ||
5323fd04 EA |
2214 | /* blow away mappings if mapped through GTT */ |
2215 | i915_gem_release_mmap(obj); | |
2216 | ||
673a394b EA |
2217 | /* Move the object to the CPU domain to ensure that |
2218 | * any possible CPU writes while it's not in the GTT | |
2219 | * are flushed when we go to remap it. This will | |
2220 | * also ensure that all pending GPU writes are finished | |
2221 | * before we unbind. | |
2222 | */ | |
e47c68e9 | 2223 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2224 | if (ret == -ERESTARTSYS) |
673a394b | 2225 | return ret; |
8dc1775d CW |
2226 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2227 | * should be safe and we need to cleanup or else we might | |
2228 | * cause memory corruption through use-after-free. | |
2229 | */ | |
812ed492 CW |
2230 | if (ret) { |
2231 | i915_gem_clflush_object(obj); | |
2232 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2233 | } | |
673a394b | 2234 | |
96b47b65 DV |
2235 | /* release the fence reg _after_ flushing */ |
2236 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2237 | i915_gem_clear_fence_reg(obj); | |
2238 | ||
73aa808f CW |
2239 | drm_unbind_agp(obj_priv->agp_mem); |
2240 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2241 | |
856fa198 | 2242 | i915_gem_object_put_pages(obj); |
a32808c0 | 2243 | BUG_ON(obj_priv->pages_refcount); |
673a394b | 2244 | |
fb7d516a | 2245 | i915_gem_info_remove_gtt(dev_priv, obj); |
69dc4987 | 2246 | list_del_init(&obj_priv->mm_list); |
673a394b | 2247 | |
73aa808f CW |
2248 | drm_mm_put_block(obj_priv->gtt_space); |
2249 | obj_priv->gtt_space = NULL; | |
9af90d19 | 2250 | obj_priv->gtt_offset = 0; |
673a394b | 2251 | |
963b4836 CW |
2252 | if (i915_gem_object_is_purgeable(obj_priv)) |
2253 | i915_gem_object_truncate(obj); | |
2254 | ||
1c5d22f7 CW |
2255 | trace_i915_gem_object_unbind(obj); |
2256 | ||
8dc1775d | 2257 | return ret; |
673a394b EA |
2258 | } |
2259 | ||
a56ba56c CW |
2260 | static int i915_ring_idle(struct drm_device *dev, |
2261 | struct intel_ring_buffer *ring) | |
2262 | { | |
64193406 CW |
2263 | if (list_empty(&ring->gpu_write_list)) |
2264 | return 0; | |
2265 | ||
a56ba56c CW |
2266 | i915_gem_flush_ring(dev, NULL, ring, |
2267 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2268 | return i915_wait_request(dev, | |
2269 | i915_gem_next_request_seqno(dev, ring), | |
2270 | ring); | |
2271 | } | |
2272 | ||
b47eb4a2 | 2273 | int |
4df2faf4 DV |
2274 | i915_gpu_idle(struct drm_device *dev) |
2275 | { | |
2276 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2277 | bool lists_empty; | |
852835f3 | 2278 | int ret; |
4df2faf4 | 2279 | |
d1b851fc ZN |
2280 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2281 | list_empty(&dev_priv->render_ring.active_list) && | |
549f7365 CW |
2282 | list_empty(&dev_priv->bsd_ring.active_list) && |
2283 | list_empty(&dev_priv->blt_ring.active_list)); | |
4df2faf4 DV |
2284 | if (lists_empty) |
2285 | return 0; | |
2286 | ||
2287 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2288 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2289 | if (ret) |
2290 | return ret; | |
d1b851fc | 2291 | |
87acb0a5 CW |
2292 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2293 | if (ret) | |
2294 | return ret; | |
d1b851fc | 2295 | |
549f7365 CW |
2296 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2297 | if (ret) | |
2298 | return ret; | |
4df2faf4 | 2299 | |
8a1a49f9 | 2300 | return 0; |
4df2faf4 DV |
2301 | } |
2302 | ||
5cdf5881 | 2303 | static int |
4bdadb97 CW |
2304 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2305 | gfp_t gfpmask) | |
673a394b | 2306 | { |
23010e43 | 2307 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2308 | int page_count, i; |
2309 | struct address_space *mapping; | |
2310 | struct inode *inode; | |
2311 | struct page *page; | |
673a394b | 2312 | |
778c3544 DV |
2313 | BUG_ON(obj_priv->pages_refcount |
2314 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2315 | ||
856fa198 | 2316 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2317 | return 0; |
2318 | ||
2319 | /* Get the list of pages out of our struct file. They'll be pinned | |
2320 | * at this point until we release them. | |
2321 | */ | |
2322 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2323 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2324 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2325 | if (obj_priv->pages == NULL) { |
856fa198 | 2326 | obj_priv->pages_refcount--; |
673a394b EA |
2327 | return -ENOMEM; |
2328 | } | |
2329 | ||
2330 | inode = obj->filp->f_path.dentry->d_inode; | |
2331 | mapping = inode->i_mapping; | |
2332 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2333 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2334 | GFP_HIGHUSER | |
4bdadb97 | 2335 | __GFP_COLD | |
cd9f040d | 2336 | __GFP_RECLAIMABLE | |
4bdadb97 | 2337 | gfpmask); |
1f2b1013 CW |
2338 | if (IS_ERR(page)) |
2339 | goto err_pages; | |
2340 | ||
856fa198 | 2341 | obj_priv->pages[i] = page; |
673a394b | 2342 | } |
280b713b EA |
2343 | |
2344 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2345 | i915_gem_object_do_bit_17_swizzle(obj); | |
2346 | ||
673a394b | 2347 | return 0; |
1f2b1013 CW |
2348 | |
2349 | err_pages: | |
2350 | while (i--) | |
2351 | page_cache_release(obj_priv->pages[i]); | |
2352 | ||
2353 | drm_free_large(obj_priv->pages); | |
2354 | obj_priv->pages = NULL; | |
2355 | obj_priv->pages_refcount--; | |
2356 | return PTR_ERR(page); | |
673a394b EA |
2357 | } |
2358 | ||
4e901fdc EA |
2359 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2360 | { | |
2361 | struct drm_gem_object *obj = reg->obj; | |
2362 | struct drm_device *dev = obj->dev; | |
2363 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2364 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2365 | int regnum = obj_priv->fence_reg; |
2366 | uint64_t val; | |
2367 | ||
2368 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2369 | 0xfffff000) << 32; | |
2370 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2371 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2372 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2373 | ||
2374 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2375 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2376 | val |= I965_FENCE_REG_VALID; | |
2377 | ||
2378 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2379 | } | |
2380 | ||
de151cf6 JB |
2381 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2382 | { | |
2383 | struct drm_gem_object *obj = reg->obj; | |
2384 | struct drm_device *dev = obj->dev; | |
2385 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2386 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2387 | int regnum = obj_priv->fence_reg; |
2388 | uint64_t val; | |
2389 | ||
2390 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2391 | 0xfffff000) << 32; | |
2392 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2393 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2394 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2395 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2396 | val |= I965_FENCE_REG_VALID; | |
2397 | ||
2398 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2399 | } | |
2400 | ||
2401 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2402 | { | |
2403 | struct drm_gem_object *obj = reg->obj; | |
2404 | struct drm_device *dev = obj->dev; | |
2405 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2406 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2407 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2408 | int tile_width; |
dc529a4f | 2409 | uint32_t fence_reg, val; |
de151cf6 JB |
2410 | uint32_t pitch_val; |
2411 | ||
2412 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2413 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2414 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2415 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2416 | return; |
2417 | } | |
2418 | ||
0f973f27 JB |
2419 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2420 | HAS_128_BYTE_Y_TILING(dev)) | |
2421 | tile_width = 128; | |
de151cf6 | 2422 | else |
0f973f27 JB |
2423 | tile_width = 512; |
2424 | ||
2425 | /* Note: pitch better be a power of two tile widths */ | |
2426 | pitch_val = obj_priv->stride / tile_width; | |
2427 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2428 | |
c36a2a6d DV |
2429 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2430 | HAS_128_BYTE_Y_TILING(dev)) | |
2431 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2432 | else | |
2433 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2434 | ||
de151cf6 JB |
2435 | val = obj_priv->gtt_offset; |
2436 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2437 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2438 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2439 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2440 | val |= I830_FENCE_REG_VALID; | |
2441 | ||
dc529a4f EA |
2442 | if (regnum < 8) |
2443 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2444 | else | |
2445 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2446 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2447 | } |
2448 | ||
2449 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2450 | { | |
2451 | struct drm_gem_object *obj = reg->obj; | |
2452 | struct drm_device *dev = obj->dev; | |
2453 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2454 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2455 | int regnum = obj_priv->fence_reg; |
2456 | uint32_t val; | |
2457 | uint32_t pitch_val; | |
8d7773a3 | 2458 | uint32_t fence_size_bits; |
de151cf6 | 2459 | |
8d7773a3 | 2460 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2461 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2462 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2463 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2464 | return; |
2465 | } | |
2466 | ||
e76a16de EA |
2467 | pitch_val = obj_priv->stride / 128; |
2468 | pitch_val = ffs(pitch_val) - 1; | |
2469 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2470 | ||
de151cf6 JB |
2471 | val = obj_priv->gtt_offset; |
2472 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2473 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2474 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2475 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2476 | val |= fence_size_bits; | |
de151cf6 JB |
2477 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2478 | val |= I830_FENCE_REG_VALID; | |
2479 | ||
2480 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2481 | } |
2482 | ||
2cf34d7b CW |
2483 | static int i915_find_fence_reg(struct drm_device *dev, |
2484 | bool interruptible) | |
ae3db24a DV |
2485 | { |
2486 | struct drm_i915_fence_reg *reg = NULL; | |
2487 | struct drm_i915_gem_object *obj_priv = NULL; | |
2488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2489 | struct drm_gem_object *obj = NULL; | |
2490 | int i, avail, ret; | |
2491 | ||
2492 | /* First try to find a free reg */ | |
2493 | avail = 0; | |
2494 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2495 | reg = &dev_priv->fence_regs[i]; | |
2496 | if (!reg->obj) | |
2497 | return i; | |
2498 | ||
23010e43 | 2499 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2500 | if (!obj_priv->pin_count) |
2501 | avail++; | |
2502 | } | |
2503 | ||
2504 | if (avail == 0) | |
2505 | return -ENOSPC; | |
2506 | ||
2507 | /* None available, try to steal one or wait for a user to finish */ | |
2508 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2509 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2510 | lru_list) { | |
2511 | obj = reg->obj; | |
2512 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2513 | |
2514 | if (obj_priv->pin_count) | |
2515 | continue; | |
2516 | ||
2517 | /* found one! */ | |
2518 | i = obj_priv->fence_reg; | |
2519 | break; | |
2520 | } | |
2521 | ||
2522 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2523 | ||
2524 | /* We only have a reference on obj from the active list. put_fence_reg | |
2525 | * might drop that one, causing a use-after-free in it. So hold a | |
2526 | * private reference to obj like the other callers of put_fence_reg | |
2527 | * (set_tiling ioctl) do. */ | |
2528 | drm_gem_object_reference(obj); | |
2cf34d7b | 2529 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2530 | drm_gem_object_unreference(obj); |
2531 | if (ret != 0) | |
2532 | return ret; | |
2533 | ||
2534 | return i; | |
2535 | } | |
2536 | ||
de151cf6 JB |
2537 | /** |
2538 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2539 | * @obj: object to map through a fence reg | |
2540 | * | |
2541 | * When mapping objects through the GTT, userspace wants to be able to write | |
2542 | * to them without having to worry about swizzling if the object is tiled. | |
2543 | * | |
2544 | * This function walks the fence regs looking for a free one for @obj, | |
2545 | * stealing one if it can't find any. | |
2546 | * | |
2547 | * It then sets up the reg based on the object's properties: address, pitch | |
2548 | * and tiling format. | |
2549 | */ | |
8c4b8c3f | 2550 | int |
2cf34d7b CW |
2551 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2552 | bool interruptible) | |
de151cf6 JB |
2553 | { |
2554 | struct drm_device *dev = obj->dev; | |
79e53945 | 2555 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2556 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2557 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2558 | int ret; |
de151cf6 | 2559 | |
a09ba7fa EA |
2560 | /* Just update our place in the LRU if our fence is getting used. */ |
2561 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2562 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2563 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2564 | return 0; |
2565 | } | |
2566 | ||
de151cf6 JB |
2567 | switch (obj_priv->tiling_mode) { |
2568 | case I915_TILING_NONE: | |
2569 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2570 | break; | |
2571 | case I915_TILING_X: | |
0f973f27 JB |
2572 | if (!obj_priv->stride) |
2573 | return -EINVAL; | |
2574 | WARN((obj_priv->stride & (512 - 1)), | |
2575 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2576 | obj_priv->gtt_offset); | |
de151cf6 JB |
2577 | break; |
2578 | case I915_TILING_Y: | |
0f973f27 JB |
2579 | if (!obj_priv->stride) |
2580 | return -EINVAL; | |
2581 | WARN((obj_priv->stride & (128 - 1)), | |
2582 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2583 | obj_priv->gtt_offset); | |
de151cf6 JB |
2584 | break; |
2585 | } | |
2586 | ||
2cf34d7b | 2587 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2588 | if (ret < 0) |
2589 | return ret; | |
de151cf6 | 2590 | |
ae3db24a DV |
2591 | obj_priv->fence_reg = ret; |
2592 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2593 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2594 | |
de151cf6 JB |
2595 | reg->obj = obj; |
2596 | ||
e259befd CW |
2597 | switch (INTEL_INFO(dev)->gen) { |
2598 | case 6: | |
4e901fdc | 2599 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2600 | break; |
2601 | case 5: | |
2602 | case 4: | |
de151cf6 | 2603 | i965_write_fence_reg(reg); |
e259befd CW |
2604 | break; |
2605 | case 3: | |
de151cf6 | 2606 | i915_write_fence_reg(reg); |
e259befd CW |
2607 | break; |
2608 | case 2: | |
de151cf6 | 2609 | i830_write_fence_reg(reg); |
e259befd CW |
2610 | break; |
2611 | } | |
d9ddcb96 | 2612 | |
ae3db24a DV |
2613 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2614 | obj_priv->tiling_mode); | |
1c5d22f7 | 2615 | |
d9ddcb96 | 2616 | return 0; |
de151cf6 JB |
2617 | } |
2618 | ||
2619 | /** | |
2620 | * i915_gem_clear_fence_reg - clear out fence register info | |
2621 | * @obj: object to clear | |
2622 | * | |
2623 | * Zeroes out the fence register itself and clears out the associated | |
2624 | * data structures in dev_priv and obj_priv. | |
2625 | */ | |
2626 | static void | |
2627 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2628 | { | |
2629 | struct drm_device *dev = obj->dev; | |
79e53945 | 2630 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2631 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2632 | struct drm_i915_fence_reg *reg = |
2633 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2634 | uint32_t fence_reg; |
de151cf6 | 2635 | |
e259befd CW |
2636 | switch (INTEL_INFO(dev)->gen) { |
2637 | case 6: | |
4e901fdc EA |
2638 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2639 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2640 | break; |
2641 | case 5: | |
2642 | case 4: | |
de151cf6 | 2643 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2644 | break; |
2645 | case 3: | |
9b74f734 | 2646 | if (obj_priv->fence_reg >= 8) |
e259befd | 2647 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2648 | else |
e259befd CW |
2649 | case 2: |
2650 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2651 | |
2652 | I915_WRITE(fence_reg, 0); | |
e259befd | 2653 | break; |
dc529a4f | 2654 | } |
de151cf6 | 2655 | |
007cc8ac | 2656 | reg->obj = NULL; |
de151cf6 | 2657 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2658 | list_del_init(®->lru_list); |
de151cf6 JB |
2659 | } |
2660 | ||
52dc7d32 CW |
2661 | /** |
2662 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2663 | * to the buffer to finish, and then resets the fence register. | |
2664 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2665 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2666 | * |
2667 | * Zeroes out the fence register itself and clears out the associated | |
2668 | * data structures in dev_priv and obj_priv. | |
2669 | */ | |
2670 | int | |
2cf34d7b CW |
2671 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2672 | bool interruptible) | |
52dc7d32 CW |
2673 | { |
2674 | struct drm_device *dev = obj->dev; | |
53640e1d | 2675 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2676 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2677 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2678 | |
2679 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2680 | return 0; | |
2681 | ||
10ae9bd2 DV |
2682 | /* If we've changed tiling, GTT-mappings of the object |
2683 | * need to re-fault to ensure that the correct fence register | |
2684 | * setup is in place. | |
2685 | */ | |
2686 | i915_gem_release_mmap(obj); | |
2687 | ||
52dc7d32 CW |
2688 | /* On the i915, GPU access to tiled buffers is via a fence, |
2689 | * therefore we must wait for any outstanding access to complete | |
2690 | * before clearing the fence. | |
2691 | */ | |
53640e1d CW |
2692 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2693 | if (reg->gpu) { | |
52dc7d32 CW |
2694 | int ret; |
2695 | ||
2cf34d7b | 2696 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad | 2697 | if (ret) |
2dafb1e0 CW |
2698 | return ret; |
2699 | ||
2cf34d7b | 2700 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2701 | if (ret) |
52dc7d32 | 2702 | return ret; |
53640e1d CW |
2703 | |
2704 | reg->gpu = false; | |
52dc7d32 CW |
2705 | } |
2706 | ||
4a726612 | 2707 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2708 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2709 | |
2710 | return 0; | |
2711 | } | |
2712 | ||
673a394b EA |
2713 | /** |
2714 | * Finds free space in the GTT aperture and binds the object there. | |
2715 | */ | |
2716 | static int | |
920afa77 DV |
2717 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
2718 | unsigned alignment, | |
2719 | bool mappable) | |
673a394b EA |
2720 | { |
2721 | struct drm_device *dev = obj->dev; | |
2722 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2723 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2724 | struct drm_mm_node *free_space; |
4bdadb97 | 2725 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2726 | int ret; |
673a394b | 2727 | |
bb6baf76 | 2728 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2729 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2730 | return -EINVAL; | |
2731 | } | |
2732 | ||
673a394b | 2733 | if (alignment == 0) |
0f973f27 | 2734 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2735 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2736 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2737 | return -EINVAL; | |
2738 | } | |
2739 | ||
654fc607 CW |
2740 | /* If the object is bigger than the entire aperture, reject it early |
2741 | * before evicting everything in a vain attempt to find space. | |
2742 | */ | |
920afa77 DV |
2743 | if (obj->size > |
2744 | (mappable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { | |
654fc607 CW |
2745 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2746 | return -E2BIG; | |
2747 | } | |
2748 | ||
673a394b | 2749 | search_free: |
920afa77 DV |
2750 | if (mappable) |
2751 | free_space = | |
2752 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
2753 | obj->size, alignment, 0, | |
2754 | dev_priv->mm.gtt_mappable_end, | |
2755 | 0); | |
2756 | else | |
2757 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2758 | obj->size, alignment, 0); | |
2759 | ||
2760 | if (free_space != NULL) { | |
2761 | if (mappable) | |
2762 | obj_priv->gtt_space = | |
2763 | drm_mm_get_block_range_generic(free_space, | |
2764 | obj->size, | |
2765 | alignment, 0, | |
2766 | dev_priv->mm.gtt_mappable_end, | |
2767 | 0); | |
2768 | else | |
2769 | obj_priv->gtt_space = | |
2770 | drm_mm_get_block(free_space, obj->size, | |
2771 | alignment); | |
2772 | } | |
673a394b EA |
2773 | if (obj_priv->gtt_space == NULL) { |
2774 | /* If the gtt is empty and we're still having trouble | |
2775 | * fitting our object in, we're out of memory. | |
2776 | */ | |
920afa77 DV |
2777 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
2778 | mappable); | |
9731129c | 2779 | if (ret) |
673a394b | 2780 | return ret; |
9731129c | 2781 | |
673a394b EA |
2782 | goto search_free; |
2783 | } | |
2784 | ||
4bdadb97 | 2785 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2786 | if (ret) { |
2787 | drm_mm_put_block(obj_priv->gtt_space); | |
2788 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2789 | |
2790 | if (ret == -ENOMEM) { | |
2791 | /* first try to clear up some space from the GTT */ | |
0108a3ed | 2792 | ret = i915_gem_evict_something(dev, obj->size, |
920afa77 | 2793 | alignment, mappable); |
07f73f69 | 2794 | if (ret) { |
07f73f69 | 2795 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2796 | if (gfpmask) { |
2797 | gfpmask = 0; | |
2798 | goto search_free; | |
07f73f69 CW |
2799 | } |
2800 | ||
2801 | return ret; | |
2802 | } | |
2803 | ||
2804 | goto search_free; | |
2805 | } | |
2806 | ||
673a394b EA |
2807 | return ret; |
2808 | } | |
2809 | ||
673a394b EA |
2810 | /* Create an AGP memory structure pointing at our pages, and bind it |
2811 | * into the GTT. | |
2812 | */ | |
2813 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2814 | obj_priv->pages, |
07f73f69 | 2815 | obj->size >> PAGE_SHIFT, |
9af90d19 | 2816 | obj_priv->gtt_space->start, |
ba1eb1d8 | 2817 | obj_priv->agp_type); |
673a394b | 2818 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2819 | i915_gem_object_put_pages(obj); |
673a394b EA |
2820 | drm_mm_put_block(obj_priv->gtt_space); |
2821 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2822 | |
920afa77 DV |
2823 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
2824 | mappable); | |
9731129c | 2825 | if (ret) |
07f73f69 | 2826 | return ret; |
07f73f69 CW |
2827 | |
2828 | goto search_free; | |
673a394b | 2829 | } |
673a394b | 2830 | |
fb7d516a DV |
2831 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
2832 | ||
bf1a1092 | 2833 | /* keep track of bounds object by adding it to the inactive list */ |
69dc4987 | 2834 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
fb7d516a | 2835 | i915_gem_info_add_gtt(dev_priv, obj); |
bf1a1092 | 2836 | |
673a394b EA |
2837 | /* Assert that the object is not currently in any GPU domain. As it |
2838 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2839 | * a GPU cache | |
2840 | */ | |
21d509e3 CW |
2841 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2842 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2843 | |
ec57d260 | 2844 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, mappable); |
1c5d22f7 | 2845 | |
673a394b EA |
2846 | return 0; |
2847 | } | |
2848 | ||
2849 | void | |
2850 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2851 | { | |
23010e43 | 2852 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2853 | |
2854 | /* If we don't have a page list set up, then we're not pinned | |
2855 | * to GPU, and we can ignore the cache flush because it'll happen | |
2856 | * again at bind time. | |
2857 | */ | |
856fa198 | 2858 | if (obj_priv->pages == NULL) |
673a394b EA |
2859 | return; |
2860 | ||
1c5d22f7 | 2861 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2862 | |
856fa198 | 2863 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2864 | } |
2865 | ||
e47c68e9 | 2866 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2867 | static int |
ba3d8d74 DV |
2868 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2869 | bool pipelined) | |
e47c68e9 EA |
2870 | { |
2871 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2872 | uint32_t old_write_domain; |
e47c68e9 EA |
2873 | |
2874 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2875 | return 0; |
e47c68e9 EA |
2876 | |
2877 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2878 | old_write_domain = obj->write_domain; |
c78ec30b | 2879 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2880 | to_intel_bo(obj)->ring, |
2881 | 0, obj->write_domain); | |
48b956c5 | 2882 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2883 | |
2884 | trace_i915_gem_object_change_domain(obj, | |
2885 | obj->read_domains, | |
2886 | old_write_domain); | |
ba3d8d74 DV |
2887 | |
2888 | if (pipelined) | |
2889 | return 0; | |
2890 | ||
2cf34d7b | 2891 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2892 | } |
2893 | ||
2894 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2895 | static void | |
2896 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2897 | { | |
1c5d22f7 CW |
2898 | uint32_t old_write_domain; |
2899 | ||
e47c68e9 EA |
2900 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2901 | return; | |
2902 | ||
2903 | /* No actual flushing is required for the GTT write domain. Writes | |
2904 | * to it immediately go to main memory as far as we know, so there's | |
2905 | * no chipset flush. It also doesn't land in render cache. | |
2906 | */ | |
1c5d22f7 | 2907 | old_write_domain = obj->write_domain; |
e47c68e9 | 2908 | obj->write_domain = 0; |
1c5d22f7 CW |
2909 | |
2910 | trace_i915_gem_object_change_domain(obj, | |
2911 | obj->read_domains, | |
2912 | old_write_domain); | |
e47c68e9 EA |
2913 | } |
2914 | ||
2915 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2916 | static void | |
2917 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2918 | { | |
2919 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2920 | uint32_t old_write_domain; |
e47c68e9 EA |
2921 | |
2922 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2923 | return; | |
2924 | ||
2925 | i915_gem_clflush_object(obj); | |
2926 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2927 | old_write_domain = obj->write_domain; |
e47c68e9 | 2928 | obj->write_domain = 0; |
1c5d22f7 CW |
2929 | |
2930 | trace_i915_gem_object_change_domain(obj, | |
2931 | obj->read_domains, | |
2932 | old_write_domain); | |
e47c68e9 EA |
2933 | } |
2934 | ||
2ef7eeaa EA |
2935 | /** |
2936 | * Moves a single object to the GTT read, and possibly write domain. | |
2937 | * | |
2938 | * This function returns when the move is complete, including waiting on | |
2939 | * flushes to occur. | |
2940 | */ | |
79e53945 | 2941 | int |
2ef7eeaa EA |
2942 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2943 | { | |
23010e43 | 2944 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2945 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2946 | int ret; |
2ef7eeaa | 2947 | |
02354392 EA |
2948 | /* Not valid to be called on unbound objects. */ |
2949 | if (obj_priv->gtt_space == NULL) | |
2950 | return -EINVAL; | |
2951 | ||
ba3d8d74 | 2952 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
2dafb1e0 CW |
2953 | if (ret != 0) |
2954 | return ret; | |
2955 | ||
7213342d | 2956 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2957 | |
ba3d8d74 | 2958 | if (write) { |
2cf34d7b | 2959 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2960 | if (ret) |
2961 | return ret; | |
ba3d8d74 | 2962 | } |
e47c68e9 | 2963 | |
1c5d22f7 CW |
2964 | old_write_domain = obj->write_domain; |
2965 | old_read_domains = obj->read_domains; | |
2966 | ||
e47c68e9 EA |
2967 | /* It should now be out of any other write domains, and we can update |
2968 | * the domain values for our changes. | |
2969 | */ | |
2970 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2971 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2972 | if (write) { | |
7213342d | 2973 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2974 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2975 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2976 | } |
2977 | ||
1c5d22f7 CW |
2978 | trace_i915_gem_object_change_domain(obj, |
2979 | old_read_domains, | |
2980 | old_write_domain); | |
2981 | ||
e47c68e9 EA |
2982 | return 0; |
2983 | } | |
2984 | ||
b9241ea3 ZW |
2985 | /* |
2986 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2987 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2988 | */ | |
2989 | int | |
48b956c5 CW |
2990 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2991 | bool pipelined) | |
b9241ea3 | 2992 | { |
23010e43 | 2993 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2994 | uint32_t old_read_domains; |
b9241ea3 ZW |
2995 | int ret; |
2996 | ||
2997 | /* Not valid to be called on unbound objects. */ | |
2998 | if (obj_priv->gtt_space == NULL) | |
2999 | return -EINVAL; | |
3000 | ||
ced270fa | 3001 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
2dafb1e0 CW |
3002 | if (ret) |
3003 | return ret; | |
b9241ea3 | 3004 | |
ced270fa CW |
3005 | /* Currently, we are always called from an non-interruptible context. */ |
3006 | if (!pipelined) { | |
3007 | ret = i915_gem_object_wait_rendering(obj, false); | |
3008 | if (ret) | |
b9241ea3 ZW |
3009 | return ret; |
3010 | } | |
3011 | ||
b118c1e3 CW |
3012 | i915_gem_object_flush_cpu_write_domain(obj); |
3013 | ||
b9241ea3 | 3014 | old_read_domains = obj->read_domains; |
c78ec30b | 3015 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3016 | |
3017 | trace_i915_gem_object_change_domain(obj, | |
3018 | old_read_domains, | |
ba3d8d74 | 3019 | obj->write_domain); |
b9241ea3 ZW |
3020 | |
3021 | return 0; | |
3022 | } | |
3023 | ||
e47c68e9 EA |
3024 | /** |
3025 | * Moves a single object to the CPU read, and possibly write domain. | |
3026 | * | |
3027 | * This function returns when the move is complete, including waiting on | |
3028 | * flushes to occur. | |
3029 | */ | |
3030 | static int | |
3031 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
3032 | { | |
1c5d22f7 | 3033 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3034 | int ret; |
3035 | ||
ba3d8d74 | 3036 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
3037 | if (ret != 0) |
3038 | return ret; | |
2ef7eeaa | 3039 | |
e47c68e9 | 3040 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3041 | |
e47c68e9 EA |
3042 | /* If we have a partially-valid cache of the object in the CPU, |
3043 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3044 | */ |
e47c68e9 | 3045 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3046 | |
7213342d | 3047 | if (write) { |
2cf34d7b | 3048 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
3049 | if (ret) |
3050 | return ret; | |
3051 | } | |
3052 | ||
1c5d22f7 CW |
3053 | old_write_domain = obj->write_domain; |
3054 | old_read_domains = obj->read_domains; | |
3055 | ||
e47c68e9 EA |
3056 | /* Flush the CPU cache if it's still invalid. */ |
3057 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 3058 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3059 | |
e47c68e9 | 3060 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3061 | } |
3062 | ||
3063 | /* It should now be out of any other write domains, and we can update | |
3064 | * the domain values for our changes. | |
3065 | */ | |
e47c68e9 EA |
3066 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3067 | ||
3068 | /* If we're writing through the CPU, then the GPU read domains will | |
3069 | * need to be invalidated at next use. | |
3070 | */ | |
3071 | if (write) { | |
c78ec30b | 3072 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
3073 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
3074 | } | |
2ef7eeaa | 3075 | |
1c5d22f7 CW |
3076 | trace_i915_gem_object_change_domain(obj, |
3077 | old_read_domains, | |
3078 | old_write_domain); | |
3079 | ||
2ef7eeaa EA |
3080 | return 0; |
3081 | } | |
3082 | ||
673a394b EA |
3083 | /* |
3084 | * Set the next domain for the specified object. This | |
3085 | * may not actually perform the necessary flushing/invaliding though, | |
3086 | * as that may want to be batched with other set_domain operations | |
3087 | * | |
3088 | * This is (we hope) the only really tricky part of gem. The goal | |
3089 | * is fairly simple -- track which caches hold bits of the object | |
3090 | * and make sure they remain coherent. A few concrete examples may | |
3091 | * help to explain how it works. For shorthand, we use the notation | |
3092 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3093 | * a pair of read and write domain masks. | |
3094 | * | |
3095 | * Case 1: the batch buffer | |
3096 | * | |
3097 | * 1. Allocated | |
3098 | * 2. Written by CPU | |
3099 | * 3. Mapped to GTT | |
3100 | * 4. Read by GPU | |
3101 | * 5. Unmapped from GTT | |
3102 | * 6. Freed | |
3103 | * | |
3104 | * Let's take these a step at a time | |
3105 | * | |
3106 | * 1. Allocated | |
3107 | * Pages allocated from the kernel may still have | |
3108 | * cache contents, so we set them to (CPU, CPU) always. | |
3109 | * 2. Written by CPU (using pwrite) | |
3110 | * The pwrite function calls set_domain (CPU, CPU) and | |
3111 | * this function does nothing (as nothing changes) | |
3112 | * 3. Mapped by GTT | |
3113 | * This function asserts that the object is not | |
3114 | * currently in any GPU-based read or write domains | |
3115 | * 4. Read by GPU | |
3116 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3117 | * As write_domain is zero, this function adds in the | |
3118 | * current read domains (CPU+COMMAND, 0). | |
3119 | * flush_domains is set to CPU. | |
3120 | * invalidate_domains is set to COMMAND | |
3121 | * clflush is run to get data out of the CPU caches | |
3122 | * then i915_dev_set_domain calls i915_gem_flush to | |
3123 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3124 | * 5. Unmapped from GTT | |
3125 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3126 | * flush_domains and invalidate_domains end up both zero | |
3127 | * so no flushing/invalidating happens | |
3128 | * 6. Freed | |
3129 | * yay, done | |
3130 | * | |
3131 | * Case 2: The shared render buffer | |
3132 | * | |
3133 | * 1. Allocated | |
3134 | * 2. Mapped to GTT | |
3135 | * 3. Read/written by GPU | |
3136 | * 4. set_domain to (CPU,CPU) | |
3137 | * 5. Read/written by CPU | |
3138 | * 6. Read/written by GPU | |
3139 | * | |
3140 | * 1. Allocated | |
3141 | * Same as last example, (CPU, CPU) | |
3142 | * 2. Mapped to GTT | |
3143 | * Nothing changes (assertions find that it is not in the GPU) | |
3144 | * 3. Read/written by GPU | |
3145 | * execbuffer calls set_domain (RENDER, RENDER) | |
3146 | * flush_domains gets CPU | |
3147 | * invalidate_domains gets GPU | |
3148 | * clflush (obj) | |
3149 | * MI_FLUSH and drm_agp_chipset_flush | |
3150 | * 4. set_domain (CPU, CPU) | |
3151 | * flush_domains gets GPU | |
3152 | * invalidate_domains gets CPU | |
3153 | * wait_rendering (obj) to make sure all drawing is complete. | |
3154 | * This will include an MI_FLUSH to get the data from GPU | |
3155 | * to memory | |
3156 | * clflush (obj) to invalidate the CPU cache | |
3157 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3158 | * 5. Read/written by CPU | |
3159 | * cache lines are loaded and dirtied | |
3160 | * 6. Read written by GPU | |
3161 | * Same as last GPU access | |
3162 | * | |
3163 | * Case 3: The constant buffer | |
3164 | * | |
3165 | * 1. Allocated | |
3166 | * 2. Written by CPU | |
3167 | * 3. Read by GPU | |
3168 | * 4. Updated (written) by CPU again | |
3169 | * 5. Read by GPU | |
3170 | * | |
3171 | * 1. Allocated | |
3172 | * (CPU, CPU) | |
3173 | * 2. Written by CPU | |
3174 | * (CPU, CPU) | |
3175 | * 3. Read by GPU | |
3176 | * (CPU+RENDER, 0) | |
3177 | * flush_domains = CPU | |
3178 | * invalidate_domains = RENDER | |
3179 | * clflush (obj) | |
3180 | * MI_FLUSH | |
3181 | * drm_agp_chipset_flush | |
3182 | * 4. Updated (written) by CPU again | |
3183 | * (CPU, CPU) | |
3184 | * flush_domains = 0 (no previous write domain) | |
3185 | * invalidate_domains = 0 (no new read domains) | |
3186 | * 5. Read by GPU | |
3187 | * (CPU+RENDER, 0) | |
3188 | * flush_domains = CPU | |
3189 | * invalidate_domains = RENDER | |
3190 | * clflush (obj) | |
3191 | * MI_FLUSH | |
3192 | * drm_agp_chipset_flush | |
3193 | */ | |
c0d90829 | 3194 | static void |
b6651458 CW |
3195 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
3196 | struct intel_ring_buffer *ring) | |
673a394b EA |
3197 | { |
3198 | struct drm_device *dev = obj->dev; | |
9220434a | 3199 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 3200 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3201 | uint32_t invalidate_domains = 0; |
3202 | uint32_t flush_domains = 0; | |
652c393a | 3203 | |
673a394b EA |
3204 | /* |
3205 | * If the object isn't moving to a new write domain, | |
3206 | * let the object stay in multiple read domains | |
3207 | */ | |
8b0e378a EA |
3208 | if (obj->pending_write_domain == 0) |
3209 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3210 | |
3211 | /* | |
3212 | * Flush the current write domain if | |
3213 | * the new read domains don't match. Invalidate | |
3214 | * any read domains which differ from the old | |
3215 | * write domain | |
3216 | */ | |
8b0e378a EA |
3217 | if (obj->write_domain && |
3218 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3219 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3220 | invalidate_domains |= |
3221 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3222 | } |
3223 | /* | |
3224 | * Invalidate any read caches which may have | |
3225 | * stale data. That is, any new read domains. | |
3226 | */ | |
8b0e378a | 3227 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3228 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3229 | i915_gem_clflush_object(obj); |
673a394b | 3230 | |
efbeed96 EA |
3231 | /* The actual obj->write_domain will be updated with |
3232 | * pending_write_domain after we emit the accumulated flush for all | |
3233 | * of our domain changes in execbuffers (which clears objects' | |
3234 | * write_domains). So if we have a current write domain that we | |
3235 | * aren't changing, set pending_write_domain to that. | |
3236 | */ | |
3237 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3238 | obj->pending_write_domain = obj->write_domain; | |
673a394b EA |
3239 | |
3240 | dev->invalidate_domains |= invalidate_domains; | |
3241 | dev->flush_domains |= flush_domains; | |
b6651458 | 3242 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
9220434a | 3243 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
b6651458 CW |
3244 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
3245 | dev_priv->mm.flush_rings |= ring->id; | |
673a394b EA |
3246 | } |
3247 | ||
3248 | /** | |
e47c68e9 | 3249 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3250 | * |
e47c68e9 EA |
3251 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3252 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3253 | */ |
e47c68e9 EA |
3254 | static void |
3255 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3256 | { |
23010e43 | 3257 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3258 | |
e47c68e9 EA |
3259 | if (!obj_priv->page_cpu_valid) |
3260 | return; | |
3261 | ||
3262 | /* If we're partially in the CPU read domain, finish moving it in. | |
3263 | */ | |
3264 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3265 | int i; | |
3266 | ||
3267 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3268 | if (obj_priv->page_cpu_valid[i]) | |
3269 | continue; | |
856fa198 | 3270 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3271 | } |
e47c68e9 EA |
3272 | } |
3273 | ||
3274 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3275 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3276 | */ | |
9a298b2a | 3277 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3278 | obj_priv->page_cpu_valid = NULL; |
3279 | } | |
3280 | ||
3281 | /** | |
3282 | * Set the CPU read domain on a range of the object. | |
3283 | * | |
3284 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3285 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3286 | * pages have been flushed, and will be respected by | |
3287 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3288 | * of the whole object. | |
3289 | * | |
3290 | * This function returns when the move is complete, including waiting on | |
3291 | * flushes to occur. | |
3292 | */ | |
3293 | static int | |
3294 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3295 | uint64_t offset, uint64_t size) | |
3296 | { | |
23010e43 | 3297 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3298 | uint32_t old_read_domains; |
e47c68e9 | 3299 | int i, ret; |
673a394b | 3300 | |
e47c68e9 EA |
3301 | if (offset == 0 && size == obj->size) |
3302 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3303 | |
ba3d8d74 | 3304 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3305 | if (ret != 0) |
6a47baa6 | 3306 | return ret; |
e47c68e9 EA |
3307 | i915_gem_object_flush_gtt_write_domain(obj); |
3308 | ||
3309 | /* If we're already fully in the CPU read domain, we're done. */ | |
3310 | if (obj_priv->page_cpu_valid == NULL && | |
3311 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3312 | return 0; | |
673a394b | 3313 | |
e47c68e9 EA |
3314 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3315 | * newly adding I915_GEM_DOMAIN_CPU | |
3316 | */ | |
673a394b | 3317 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3318 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3319 | GFP_KERNEL); | |
e47c68e9 EA |
3320 | if (obj_priv->page_cpu_valid == NULL) |
3321 | return -ENOMEM; | |
3322 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3323 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3324 | |
3325 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3326 | * perspective. | |
3327 | */ | |
e47c68e9 EA |
3328 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3329 | i++) { | |
673a394b EA |
3330 | if (obj_priv->page_cpu_valid[i]) |
3331 | continue; | |
3332 | ||
856fa198 | 3333 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3334 | |
3335 | obj_priv->page_cpu_valid[i] = 1; | |
3336 | } | |
3337 | ||
e47c68e9 EA |
3338 | /* It should now be out of any other write domains, and we can update |
3339 | * the domain values for our changes. | |
3340 | */ | |
3341 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3342 | ||
1c5d22f7 | 3343 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3344 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3345 | ||
1c5d22f7 CW |
3346 | trace_i915_gem_object_change_domain(obj, |
3347 | old_read_domains, | |
3348 | obj->write_domain); | |
3349 | ||
673a394b EA |
3350 | return 0; |
3351 | } | |
3352 | ||
673a394b EA |
3353 | /** |
3354 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3355 | */ | |
3356 | static int | |
9af90d19 CW |
3357 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
3358 | struct drm_file *file_priv, | |
3359 | struct drm_i915_gem_exec_object2 *entry) | |
673a394b | 3360 | { |
9af90d19 | 3361 | struct drm_device *dev = obj->base.dev; |
0839ccb8 | 3362 | drm_i915_private_t *dev_priv = dev->dev_private; |
2549d6c2 | 3363 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
9af90d19 CW |
3364 | struct drm_gem_object *target_obj = NULL; |
3365 | uint32_t target_handle = 0; | |
3366 | int i, ret = 0; | |
673a394b | 3367 | |
2549d6c2 | 3368 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
673a394b | 3369 | for (i = 0; i < entry->relocation_count; i++) { |
2549d6c2 | 3370 | struct drm_i915_gem_relocation_entry reloc; |
9af90d19 | 3371 | uint32_t target_offset; |
673a394b | 3372 | |
9af90d19 CW |
3373 | if (__copy_from_user_inatomic(&reloc, |
3374 | user_relocs+i, | |
3375 | sizeof(reloc))) { | |
3376 | ret = -EFAULT; | |
3377 | break; | |
76446cac | 3378 | } |
76446cac | 3379 | |
9af90d19 CW |
3380 | if (reloc.target_handle != target_handle) { |
3381 | drm_gem_object_unreference(target_obj); | |
673a394b | 3382 | |
9af90d19 CW |
3383 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3384 | reloc.target_handle); | |
3385 | if (target_obj == NULL) { | |
3386 | ret = -ENOENT; | |
3387 | break; | |
3388 | } | |
3389 | ||
3390 | target_handle = reloc.target_handle; | |
673a394b | 3391 | } |
9af90d19 | 3392 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
673a394b | 3393 | |
8542a0bb CW |
3394 | #if WATCH_RELOC |
3395 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3396 | "read %08x write %08x gtt %08x " | |
3397 | "presumed %08x delta %08x\n", | |
3398 | __func__, | |
3399 | obj, | |
2549d6c2 CW |
3400 | (int) reloc.offset, |
3401 | (int) reloc.target_handle, | |
3402 | (int) reloc.read_domains, | |
3403 | (int) reloc.write_domain, | |
9af90d19 | 3404 | (int) target_offset, |
2549d6c2 CW |
3405 | (int) reloc.presumed_offset, |
3406 | reloc.delta); | |
8542a0bb CW |
3407 | #endif |
3408 | ||
673a394b EA |
3409 | /* The target buffer should have appeared before us in the |
3410 | * exec_object list, so it should have a GTT space bound by now. | |
3411 | */ | |
9af90d19 | 3412 | if (target_offset == 0) { |
673a394b | 3413 | DRM_ERROR("No GTT space found for object %d\n", |
2549d6c2 | 3414 | reloc.target_handle); |
9af90d19 CW |
3415 | ret = -EINVAL; |
3416 | break; | |
673a394b EA |
3417 | } |
3418 | ||
8542a0bb | 3419 | /* Validate that the target is in a valid r/w GPU domain */ |
2549d6c2 | 3420 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
16edd550 DV |
3421 | DRM_ERROR("reloc with multiple write domains: " |
3422 | "obj %p target %d offset %d " | |
3423 | "read %08x write %08x", | |
2549d6c2 CW |
3424 | obj, reloc.target_handle, |
3425 | (int) reloc.offset, | |
3426 | reloc.read_domains, | |
3427 | reloc.write_domain); | |
9af90d19 CW |
3428 | ret = -EINVAL; |
3429 | break; | |
16edd550 | 3430 | } |
2549d6c2 CW |
3431 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
3432 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3433 | DRM_ERROR("reloc with read/write CPU domains: " |
3434 | "obj %p target %d offset %d " | |
3435 | "read %08x write %08x", | |
2549d6c2 CW |
3436 | obj, reloc.target_handle, |
3437 | (int) reloc.offset, | |
3438 | reloc.read_domains, | |
3439 | reloc.write_domain); | |
9af90d19 CW |
3440 | ret = -EINVAL; |
3441 | break; | |
e47c68e9 | 3442 | } |
2549d6c2 CW |
3443 | if (reloc.write_domain && target_obj->pending_write_domain && |
3444 | reloc.write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3445 | DRM_ERROR("Write domain conflict: " |
3446 | "obj %p target %d offset %d " | |
3447 | "new %08x old %08x\n", | |
2549d6c2 CW |
3448 | obj, reloc.target_handle, |
3449 | (int) reloc.offset, | |
3450 | reloc.write_domain, | |
673a394b | 3451 | target_obj->pending_write_domain); |
9af90d19 CW |
3452 | ret = -EINVAL; |
3453 | break; | |
673a394b EA |
3454 | } |
3455 | ||
2549d6c2 | 3456 | target_obj->pending_read_domains |= reloc.read_domains; |
878a3c37 | 3457 | target_obj->pending_write_domain |= reloc.write_domain; |
673a394b EA |
3458 | |
3459 | /* If the relocation already has the right value in it, no | |
3460 | * more work needs to be done. | |
3461 | */ | |
9af90d19 | 3462 | if (target_offset == reloc.presumed_offset) |
673a394b | 3463 | continue; |
673a394b | 3464 | |
8542a0bb | 3465 | /* Check that the relocation address is valid... */ |
9af90d19 | 3466 | if (reloc.offset > obj->base.size - 4) { |
8542a0bb CW |
3467 | DRM_ERROR("Relocation beyond object bounds: " |
3468 | "obj %p target %d offset %d size %d.\n", | |
2549d6c2 | 3469 | obj, reloc.target_handle, |
9af90d19 CW |
3470 | (int) reloc.offset, (int) obj->base.size); |
3471 | ret = -EINVAL; | |
3472 | break; | |
8542a0bb | 3473 | } |
2549d6c2 | 3474 | if (reloc.offset & 3) { |
8542a0bb CW |
3475 | DRM_ERROR("Relocation not 4-byte aligned: " |
3476 | "obj %p target %d offset %d.\n", | |
2549d6c2 CW |
3477 | obj, reloc.target_handle, |
3478 | (int) reloc.offset); | |
9af90d19 CW |
3479 | ret = -EINVAL; |
3480 | break; | |
8542a0bb CW |
3481 | } |
3482 | ||
3483 | /* and points to somewhere within the target object. */ | |
2549d6c2 | 3484 | if (reloc.delta >= target_obj->size) { |
8542a0bb CW |
3485 | DRM_ERROR("Relocation beyond target object bounds: " |
3486 | "obj %p target %d delta %d size %d.\n", | |
2549d6c2 CW |
3487 | obj, reloc.target_handle, |
3488 | (int) reloc.delta, (int) target_obj->size); | |
9af90d19 CW |
3489 | ret = -EINVAL; |
3490 | break; | |
673a394b EA |
3491 | } |
3492 | ||
9af90d19 CW |
3493 | reloc.delta += target_offset; |
3494 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
f0c43d9b CW |
3495 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
3496 | char *vaddr; | |
673a394b | 3497 | |
c48c43e4 | 3498 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
f0c43d9b | 3499 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
c48c43e4 | 3500 | kunmap_atomic(vaddr); |
f0c43d9b CW |
3501 | } else { |
3502 | uint32_t __iomem *reloc_entry; | |
3503 | void __iomem *reloc_page; | |
b962442e | 3504 | |
9af90d19 CW |
3505 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
3506 | if (ret) | |
3507 | break; | |
b962442e | 3508 | |
f0c43d9b | 3509 | /* Map the page containing the relocation we're going to perform. */ |
9af90d19 | 3510 | reloc.offset += obj->gtt_offset; |
f0c43d9b | 3511 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
c48c43e4 | 3512 | reloc.offset & PAGE_MASK); |
f0c43d9b CW |
3513 | reloc_entry = (uint32_t __iomem *) |
3514 | (reloc_page + (reloc.offset & ~PAGE_MASK)); | |
3515 | iowrite32(reloc.delta, reloc_entry); | |
c48c43e4 | 3516 | io_mapping_unmap_atomic(reloc_page); |
f0c43d9b | 3517 | } |
b962442e | 3518 | |
b5dc608c CW |
3519 | /* and update the user's relocation entry */ |
3520 | reloc.presumed_offset = target_offset; | |
3521 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
3522 | &reloc.presumed_offset, | |
3523 | sizeof(reloc.presumed_offset))) { | |
3524 | ret = -EFAULT; | |
3525 | break; | |
3526 | } | |
b962442e | 3527 | } |
b962442e | 3528 | |
9af90d19 | 3529 | drm_gem_object_unreference(target_obj); |
673a394b EA |
3530 | return ret; |
3531 | } | |
3532 | ||
40a5f0de | 3533 | static int |
9af90d19 CW |
3534 | i915_gem_execbuffer_pin(struct drm_device *dev, |
3535 | struct drm_file *file, | |
3536 | struct drm_gem_object **object_list, | |
3537 | struct drm_i915_gem_exec_object2 *exec_list, | |
3538 | int count) | |
40a5f0de | 3539 | { |
9af90d19 CW |
3540 | struct drm_i915_private *dev_priv = dev->dev_private; |
3541 | int ret, i, retry; | |
40a5f0de | 3542 | |
9af90d19 CW |
3543 | /* attempt to pin all of the buffers into the GTT */ |
3544 | for (retry = 0; retry < 2; retry++) { | |
3545 | ret = 0; | |
3546 | for (i = 0; i < count; i++) { | |
3547 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
16e809ac | 3548 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
9af90d19 CW |
3549 | bool need_fence = |
3550 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3551 | obj->tiling_mode != I915_TILING_NONE; | |
3552 | ||
16e809ac DV |
3553 | /* g33/pnv can't fence buffers in the unmappable part */ |
3554 | bool need_mappable = | |
3555 | entry->relocation_count ? true : need_fence; | |
3556 | ||
9af90d19 CW |
3557 | /* Check fence reg constraints and rebind if necessary */ |
3558 | if (need_fence && | |
3559 | !i915_gem_object_fence_offset_ok(&obj->base, | |
3560 | obj->tiling_mode)) { | |
3561 | ret = i915_gem_object_unbind(&obj->base); | |
3562 | if (ret) | |
3563 | break; | |
3564 | } | |
40a5f0de | 3565 | |
920afa77 | 3566 | ret = i915_gem_object_pin(&obj->base, |
16e809ac DV |
3567 | entry->alignment, |
3568 | need_mappable); | |
9af90d19 CW |
3569 | if (ret) |
3570 | break; | |
40a5f0de | 3571 | |
9af90d19 CW |
3572 | /* |
3573 | * Pre-965 chips need a fence register set up in order | |
3574 | * to properly handle blits to/from tiled surfaces. | |
3575 | */ | |
3576 | if (need_fence) { | |
3577 | ret = i915_gem_object_get_fence_reg(&obj->base, true); | |
3578 | if (ret) { | |
3579 | i915_gem_object_unpin(&obj->base); | |
3580 | break; | |
3581 | } | |
40a5f0de | 3582 | |
9af90d19 CW |
3583 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
3584 | } | |
40a5f0de | 3585 | |
9af90d19 | 3586 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3587 | } |
3588 | ||
9af90d19 CW |
3589 | while (i--) |
3590 | i915_gem_object_unpin(object_list[i]); | |
3591 | ||
3592 | if (ret == 0) | |
3593 | break; | |
673a394b | 3594 | |
9af90d19 CW |
3595 | if (ret != -ENOSPC || retry) |
3596 | return ret; | |
3597 | ||
3598 | ret = i915_gem_evict_everything(dev); | |
3599 | if (ret) | |
3600 | return ret; | |
40a5f0de EA |
3601 | } |
3602 | ||
2bc43b5c | 3603 | return 0; |
40a5f0de EA |
3604 | } |
3605 | ||
673a394b EA |
3606 | /* Throttle our rendering by waiting until the ring has completed our requests |
3607 | * emitted over 20 msec ago. | |
3608 | * | |
b962442e EA |
3609 | * Note that if we were to use the current jiffies each time around the loop, |
3610 | * we wouldn't escape the function with any frames outstanding if the time to | |
3611 | * render a frame was over 20ms. | |
3612 | * | |
673a394b EA |
3613 | * This should get us reasonable parallelism between CPU and GPU but also |
3614 | * relatively low latency when blocking on a particular request to finish. | |
3615 | */ | |
40a5f0de | 3616 | static int |
f787a5f5 | 3617 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3618 | { |
f787a5f5 CW |
3619 | struct drm_i915_private *dev_priv = dev->dev_private; |
3620 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3621 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3622 | struct drm_i915_gem_request *request; |
3623 | struct intel_ring_buffer *ring = NULL; | |
3624 | u32 seqno = 0; | |
3625 | int ret; | |
93533c29 | 3626 | |
1c25595f | 3627 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3628 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3629 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3630 | break; | |
40a5f0de | 3631 | |
f787a5f5 CW |
3632 | ring = request->ring; |
3633 | seqno = request->seqno; | |
b962442e | 3634 | } |
1c25595f | 3635 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3636 | |
f787a5f5 CW |
3637 | if (seqno == 0) |
3638 | return 0; | |
2bc43b5c | 3639 | |
f787a5f5 | 3640 | ret = 0; |
78501eac | 3641 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3642 | /* And wait for the seqno passing without holding any locks and |
3643 | * causing extra latency for others. This is safe as the irq | |
3644 | * generation is designed to be run atomically and so is | |
3645 | * lockless. | |
3646 | */ | |
78501eac | 3647 | ring->user_irq_get(ring); |
f787a5f5 | 3648 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3649 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3650 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3651 | ring->user_irq_put(ring); |
40a5f0de | 3652 | |
f787a5f5 CW |
3653 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3654 | ret = -EIO; | |
40a5f0de EA |
3655 | } |
3656 | ||
f787a5f5 CW |
3657 | if (ret == 0) |
3658 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3659 | |
3660 | return ret; | |
3661 | } | |
3662 | ||
83d60795 | 3663 | static int |
2549d6c2 CW |
3664 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3665 | uint64_t exec_offset) | |
83d60795 CW |
3666 | { |
3667 | uint32_t exec_start, exec_len; | |
3668 | ||
3669 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3670 | exec_len = (uint32_t) exec->batch_len; | |
3671 | ||
3672 | if ((exec_start | exec_len) & 0x7) | |
3673 | return -EINVAL; | |
3674 | ||
3675 | if (!exec_start) | |
3676 | return -EINVAL; | |
3677 | ||
3678 | return 0; | |
3679 | } | |
3680 | ||
6b95a207 | 3681 | static int |
2549d6c2 CW |
3682 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3683 | int count) | |
6b95a207 | 3684 | { |
2549d6c2 | 3685 | int i; |
6b95a207 | 3686 | |
2549d6c2 CW |
3687 | for (i = 0; i < count; i++) { |
3688 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
3689 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); | |
6b95a207 | 3690 | |
2549d6c2 CW |
3691 | if (!access_ok(VERIFY_READ, ptr, length)) |
3692 | return -EFAULT; | |
40a5f0de | 3693 | |
b5dc608c CW |
3694 | /* we may also need to update the presumed offsets */ |
3695 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3696 | return -EFAULT; | |
3697 | ||
2549d6c2 CW |
3698 | if (fault_in_pages_readable(ptr, length)) |
3699 | return -EFAULT; | |
6b95a207 | 3700 | } |
6b95a207 | 3701 | |
83d60795 | 3702 | return 0; |
6b95a207 KH |
3703 | } |
3704 | ||
8dc5d147 | 3705 | static int |
76446cac | 3706 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3707 | struct drm_file *file, |
76446cac JB |
3708 | struct drm_i915_gem_execbuffer2 *args, |
3709 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3710 | { |
3711 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3712 | struct drm_gem_object **object_list = NULL; |
3713 | struct drm_gem_object *batch_obj; | |
201361a5 | 3714 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3715 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3716 | int ret, i, flips; |
673a394b | 3717 | uint64_t exec_offset; |
673a394b | 3718 | |
852835f3 ZN |
3719 | struct intel_ring_buffer *ring = NULL; |
3720 | ||
30dbf0c0 CW |
3721 | ret = i915_gem_check_is_wedged(dev); |
3722 | if (ret) | |
3723 | return ret; | |
3724 | ||
2549d6c2 CW |
3725 | ret = validate_exec_list(exec_list, args->buffer_count); |
3726 | if (ret) | |
3727 | return ret; | |
3728 | ||
673a394b EA |
3729 | #if WATCH_EXEC |
3730 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3731 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3732 | #endif | |
549f7365 CW |
3733 | switch (args->flags & I915_EXEC_RING_MASK) { |
3734 | case I915_EXEC_DEFAULT: | |
3735 | case I915_EXEC_RENDER: | |
3736 | ring = &dev_priv->render_ring; | |
3737 | break; | |
3738 | case I915_EXEC_BSD: | |
d1b851fc | 3739 | if (!HAS_BSD(dev)) { |
549f7365 | 3740 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3741 | return -EINVAL; |
3742 | } | |
3743 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3744 | break; |
3745 | case I915_EXEC_BLT: | |
3746 | if (!HAS_BLT(dev)) { | |
3747 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3748 | return -EINVAL; | |
3749 | } | |
3750 | ring = &dev_priv->blt_ring; | |
3751 | break; | |
3752 | default: | |
3753 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3754 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3755 | return -EINVAL; | |
d1b851fc ZN |
3756 | } |
3757 | ||
4f481ed2 EA |
3758 | if (args->buffer_count < 1) { |
3759 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3760 | return -EINVAL; | |
3761 | } | |
c8e0f93a | 3762 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3763 | if (object_list == NULL) { |
3764 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3765 | args->buffer_count); |
3766 | ret = -ENOMEM; | |
3767 | goto pre_mutex_err; | |
3768 | } | |
673a394b | 3769 | |
201361a5 | 3770 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3771 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3772 | GFP_KERNEL); | |
a40e8d31 OA |
3773 | if (cliprects == NULL) { |
3774 | ret = -ENOMEM; | |
201361a5 | 3775 | goto pre_mutex_err; |
a40e8d31 | 3776 | } |
201361a5 EA |
3777 | |
3778 | ret = copy_from_user(cliprects, | |
3779 | (struct drm_clip_rect __user *) | |
3780 | (uintptr_t) args->cliprects_ptr, | |
3781 | sizeof(*cliprects) * args->num_cliprects); | |
3782 | if (ret != 0) { | |
3783 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3784 | args->num_cliprects, ret); | |
c877cdce | 3785 | ret = -EFAULT; |
201361a5 EA |
3786 | goto pre_mutex_err; |
3787 | } | |
3788 | } | |
3789 | ||
8dc5d147 CW |
3790 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3791 | if (request == NULL) { | |
3792 | ret = -ENOMEM; | |
40a5f0de | 3793 | goto pre_mutex_err; |
8dc5d147 | 3794 | } |
40a5f0de | 3795 | |
76c1dec1 CW |
3796 | ret = i915_mutex_lock_interruptible(dev); |
3797 | if (ret) | |
a198bc80 | 3798 | goto pre_mutex_err; |
673a394b EA |
3799 | |
3800 | if (dev_priv->mm.suspended) { | |
673a394b | 3801 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3802 | ret = -EBUSY; |
3803 | goto pre_mutex_err; | |
673a394b EA |
3804 | } |
3805 | ||
ac94a962 | 3806 | /* Look up object handles */ |
673a394b | 3807 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3808 | struct drm_i915_gem_object *obj_priv; |
3809 | ||
9af90d19 | 3810 | object_list[i] = drm_gem_object_lookup(dev, file, |
673a394b EA |
3811 | exec_list[i].handle); |
3812 | if (object_list[i] == NULL) { | |
3813 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3814 | exec_list[i].handle, i); | |
0ce907f8 CW |
3815 | /* prevent error path from reading uninitialized data */ |
3816 | args->buffer_count = i + 1; | |
bf79cb91 | 3817 | ret = -ENOENT; |
673a394b EA |
3818 | goto err; |
3819 | } | |
b70d11da | 3820 | |
23010e43 | 3821 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3822 | if (obj_priv->in_execbuffer) { |
3823 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3824 | object_list[i]); | |
0ce907f8 CW |
3825 | /* prevent error path from reading uninitialized data */ |
3826 | args->buffer_count = i + 1; | |
bf79cb91 | 3827 | ret = -EINVAL; |
b70d11da KH |
3828 | goto err; |
3829 | } | |
3830 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3831 | } |
673a394b | 3832 | |
9af90d19 CW |
3833 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
3834 | ret = i915_gem_execbuffer_pin(dev, file, | |
3835 | object_list, exec_list, | |
3836 | args->buffer_count); | |
3837 | if (ret) | |
3838 | goto err; | |
ac94a962 | 3839 | |
9af90d19 CW |
3840 | /* The objects are in their final locations, apply the relocations. */ |
3841 | for (i = 0; i < args->buffer_count; i++) { | |
3842 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3843 | obj->base.pending_read_domains = 0; | |
3844 | obj->base.pending_write_domain = 0; | |
3845 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); | |
3846 | if (ret) | |
ac94a962 | 3847 | goto err; |
673a394b EA |
3848 | } |
3849 | ||
3850 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3851 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3852 | if (batch_obj->pending_write_domain) { |
3853 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3854 | ret = -EINVAL; | |
3855 | goto err; | |
3856 | } | |
3857 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3858 | |
9af90d19 CW |
3859 | /* Sanity check the batch buffer */ |
3860 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; | |
3861 | ret = i915_gem_check_execbuffer(args, exec_offset); | |
83d60795 CW |
3862 | if (ret != 0) { |
3863 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3864 | goto err; | |
3865 | } | |
3866 | ||
646f0f6e KP |
3867 | /* Zero the global flush/invalidate flags. These |
3868 | * will be modified as new domains are computed | |
3869 | * for each object | |
3870 | */ | |
3871 | dev->invalidate_domains = 0; | |
3872 | dev->flush_domains = 0; | |
9220434a | 3873 | dev_priv->mm.flush_rings = 0; |
7e318e18 CW |
3874 | for (i = 0; i < args->buffer_count; i++) |
3875 | i915_gem_object_set_to_gpu_domain(object_list[i], ring); | |
673a394b | 3876 | |
646f0f6e KP |
3877 | if (dev->invalidate_domains | dev->flush_domains) { |
3878 | #if WATCH_EXEC | |
3879 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3880 | __func__, | |
3881 | dev->invalidate_domains, | |
3882 | dev->flush_domains); | |
3883 | #endif | |
9af90d19 | 3884 | i915_gem_flush(dev, file, |
646f0f6e | 3885 | dev->invalidate_domains, |
9220434a CW |
3886 | dev->flush_domains, |
3887 | dev_priv->mm.flush_rings); | |
646f0f6e | 3888 | } |
673a394b | 3889 | |
673a394b EA |
3890 | #if WATCH_COHERENCY |
3891 | for (i = 0; i < args->buffer_count; i++) { | |
3892 | i915_gem_object_check_coherency(object_list[i], | |
3893 | exec_list[i].handle); | |
3894 | } | |
3895 | #endif | |
3896 | ||
673a394b | 3897 | #if WATCH_EXEC |
6911a9b8 | 3898 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3899 | args->batch_len, |
3900 | __func__, | |
3901 | ~0); | |
3902 | #endif | |
3903 | ||
e59f2bac CW |
3904 | /* Check for any pending flips. As we only maintain a flip queue depth |
3905 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3906 | * to executing the batch and avoid stalling the CPU. | |
3907 | */ | |
3908 | flips = 0; | |
3909 | for (i = 0; i < args->buffer_count; i++) { | |
3910 | if (object_list[i]->write_domain) | |
3911 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3912 | } | |
3913 | if (flips) { | |
3914 | int plane, flip_mask; | |
3915 | ||
3916 | for (plane = 0; flips >> plane; plane++) { | |
3917 | if (((flips >> plane) & 1) == 0) | |
3918 | continue; | |
3919 | ||
3920 | if (plane) | |
3921 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3922 | else | |
3923 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3924 | ||
e1f99ce6 CW |
3925 | ret = intel_ring_begin(ring, 2); |
3926 | if (ret) | |
3927 | goto err; | |
3928 | ||
78501eac CW |
3929 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
3930 | intel_ring_emit(ring, MI_NOOP); | |
3931 | intel_ring_advance(ring); | |
e59f2bac CW |
3932 | } |
3933 | } | |
3934 | ||
673a394b | 3935 | /* Exec the batchbuffer */ |
78501eac | 3936 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
3937 | if (ret) { |
3938 | DRM_ERROR("dispatch failed %d\n", ret); | |
3939 | goto err; | |
3940 | } | |
3941 | ||
673a394b EA |
3942 | for (i = 0; i < args->buffer_count; i++) { |
3943 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3944 | |
7e318e18 CW |
3945 | obj->read_domains = obj->pending_read_domains; |
3946 | obj->write_domain = obj->pending_write_domain; | |
3947 | ||
617dbe27 | 3948 | i915_gem_object_move_to_active(obj, ring); |
7e318e18 CW |
3949 | if (obj->write_domain) { |
3950 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
3951 | obj_priv->dirty = 1; | |
3952 | list_move_tail(&obj_priv->gpu_write_list, | |
64193406 | 3953 | &ring->gpu_write_list); |
7e318e18 CW |
3954 | intel_mark_busy(dev, obj); |
3955 | } | |
3956 | ||
3957 | trace_i915_gem_object_change_domain(obj, | |
3958 | obj->read_domains, | |
3959 | obj->write_domain); | |
673a394b | 3960 | } |
673a394b | 3961 | |
7e318e18 CW |
3962 | /* |
3963 | * Ensure that the commands in the batch buffer are | |
3964 | * finished before the interrupt fires | |
3965 | */ | |
3966 | i915_retire_commands(dev, ring); | |
3967 | ||
3cce469c CW |
3968 | if (i915_add_request(dev, file, request, ring)) |
3969 | ring->outstanding_lazy_request = true; | |
3970 | else | |
3971 | request = NULL; | |
673a394b | 3972 | |
673a394b | 3973 | err: |
b70d11da | 3974 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3975 | if (object_list[i] == NULL) |
3976 | break; | |
3977 | ||
3978 | to_intel_bo(object_list[i])->in_execbuffer = false; | |
aad87dff | 3979 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3980 | } |
673a394b | 3981 | |
673a394b EA |
3982 | mutex_unlock(&dev->struct_mutex); |
3983 | ||
93533c29 | 3984 | pre_mutex_err: |
8e7d2b2c | 3985 | drm_free_large(object_list); |
9a298b2a | 3986 | kfree(cliprects); |
8dc5d147 | 3987 | kfree(request); |
673a394b EA |
3988 | |
3989 | return ret; | |
3990 | } | |
3991 | ||
76446cac JB |
3992 | /* |
3993 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3994 | * list array and passes it to the real function. | |
3995 | */ | |
3996 | int | |
3997 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3998 | struct drm_file *file_priv) | |
3999 | { | |
4000 | struct drm_i915_gem_execbuffer *args = data; | |
4001 | struct drm_i915_gem_execbuffer2 exec2; | |
4002 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
4003 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4004 | int ret, i; | |
4005 | ||
4006 | #if WATCH_EXEC | |
4007 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4008 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4009 | #endif | |
4010 | ||
4011 | if (args->buffer_count < 1) { | |
4012 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4013 | return -EINVAL; | |
4014 | } | |
4015 | ||
4016 | /* Copy in the exec list from userland */ | |
4017 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4018 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4019 | if (exec_list == NULL || exec2_list == NULL) { | |
4020 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4021 | args->buffer_count); | |
4022 | drm_free_large(exec_list); | |
4023 | drm_free_large(exec2_list); | |
4024 | return -ENOMEM; | |
4025 | } | |
4026 | ret = copy_from_user(exec_list, | |
4027 | (struct drm_i915_relocation_entry __user *) | |
4028 | (uintptr_t) args->buffers_ptr, | |
4029 | sizeof(*exec_list) * args->buffer_count); | |
4030 | if (ret != 0) { | |
4031 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4032 | args->buffer_count, ret); | |
4033 | drm_free_large(exec_list); | |
4034 | drm_free_large(exec2_list); | |
4035 | return -EFAULT; | |
4036 | } | |
4037 | ||
4038 | for (i = 0; i < args->buffer_count; i++) { | |
4039 | exec2_list[i].handle = exec_list[i].handle; | |
4040 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4041 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4042 | exec2_list[i].alignment = exec_list[i].alignment; | |
4043 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 4044 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4045 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4046 | else | |
4047 | exec2_list[i].flags = 0; | |
4048 | } | |
4049 | ||
4050 | exec2.buffers_ptr = args->buffers_ptr; | |
4051 | exec2.buffer_count = args->buffer_count; | |
4052 | exec2.batch_start_offset = args->batch_start_offset; | |
4053 | exec2.batch_len = args->batch_len; | |
4054 | exec2.DR1 = args->DR1; | |
4055 | exec2.DR4 = args->DR4; | |
4056 | exec2.num_cliprects = args->num_cliprects; | |
4057 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4058 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4059 | |
4060 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4061 | if (!ret) { | |
4062 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4063 | for (i = 0; i < args->buffer_count; i++) | |
4064 | exec_list[i].offset = exec2_list[i].offset; | |
4065 | /* ... and back out to userspace */ | |
4066 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4067 | (uintptr_t) args->buffers_ptr, | |
4068 | exec_list, | |
4069 | sizeof(*exec_list) * args->buffer_count); | |
4070 | if (ret) { | |
4071 | ret = -EFAULT; | |
4072 | DRM_ERROR("failed to copy %d exec entries " | |
4073 | "back to user (%d)\n", | |
4074 | args->buffer_count, ret); | |
4075 | } | |
76446cac JB |
4076 | } |
4077 | ||
4078 | drm_free_large(exec_list); | |
4079 | drm_free_large(exec2_list); | |
4080 | return ret; | |
4081 | } | |
4082 | ||
4083 | int | |
4084 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4085 | struct drm_file *file_priv) | |
4086 | { | |
4087 | struct drm_i915_gem_execbuffer2 *args = data; | |
4088 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4089 | int ret; | |
4090 | ||
4091 | #if WATCH_EXEC | |
4092 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4093 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4094 | #endif | |
4095 | ||
4096 | if (args->buffer_count < 1) { | |
4097 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4098 | return -EINVAL; | |
4099 | } | |
4100 | ||
4101 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4102 | if (exec2_list == NULL) { | |
4103 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4104 | args->buffer_count); | |
4105 | return -ENOMEM; | |
4106 | } | |
4107 | ret = copy_from_user(exec2_list, | |
4108 | (struct drm_i915_relocation_entry __user *) | |
4109 | (uintptr_t) args->buffers_ptr, | |
4110 | sizeof(*exec2_list) * args->buffer_count); | |
4111 | if (ret != 0) { | |
4112 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4113 | args->buffer_count, ret); | |
4114 | drm_free_large(exec2_list); | |
4115 | return -EFAULT; | |
4116 | } | |
4117 | ||
4118 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4119 | if (!ret) { | |
4120 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4121 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4122 | (uintptr_t) args->buffers_ptr, | |
4123 | exec2_list, | |
4124 | sizeof(*exec2_list) * args->buffer_count); | |
4125 | if (ret) { | |
4126 | ret = -EFAULT; | |
4127 | DRM_ERROR("failed to copy %d exec entries " | |
4128 | "back to user (%d)\n", | |
4129 | args->buffer_count, ret); | |
4130 | } | |
4131 | } | |
4132 | ||
4133 | drm_free_large(exec2_list); | |
4134 | return ret; | |
4135 | } | |
4136 | ||
673a394b | 4137 | int |
920afa77 DV |
4138 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
4139 | bool mappable) | |
673a394b EA |
4140 | { |
4141 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4142 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4143 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4144 | int ret; |
4145 | ||
778c3544 | 4146 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4147 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4148 | |
4149 | if (obj_priv->gtt_space != NULL) { | |
4150 | if (alignment == 0) | |
4151 | alignment = i915_gem_get_gtt_alignment(obj); | |
16e809ac DV |
4152 | if (obj_priv->gtt_offset & (alignment - 1) || |
4153 | (mappable && !i915_gem_object_cpu_accessible(obj_priv))) { | |
ae7d49d8 CW |
4154 | WARN(obj_priv->pin_count, |
4155 | "bo is already pinned with incorrect alignment:" | |
4156 | " offset=%x, req.alignment=%x\n", | |
4157 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4158 | ret = i915_gem_object_unbind(obj); |
4159 | if (ret) | |
4160 | return ret; | |
4161 | } | |
4162 | } | |
4163 | ||
673a394b | 4164 | if (obj_priv->gtt_space == NULL) { |
920afa77 | 4165 | ret = i915_gem_object_bind_to_gtt(obj, alignment, mappable); |
9731129c | 4166 | if (ret) |
673a394b | 4167 | return ret; |
22c344e9 | 4168 | } |
76446cac | 4169 | |
673a394b EA |
4170 | obj_priv->pin_count++; |
4171 | ||
4172 | /* If the object is not active and not pending a flush, | |
4173 | * remove it from the inactive list | |
4174 | */ | |
4175 | if (obj_priv->pin_count == 1) { | |
fb7d516a | 4176 | i915_gem_info_add_pin(dev_priv, obj, mappable); |
f13d3f73 | 4177 | if (!obj_priv->active) |
69dc4987 | 4178 | list_move_tail(&obj_priv->mm_list, |
f13d3f73 | 4179 | &dev_priv->mm.pinned_list); |
673a394b | 4180 | } |
fb7d516a | 4181 | BUG_ON(!obj_priv->pin_mappable && mappable); |
673a394b | 4182 | |
23bc5982 | 4183 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4184 | return 0; |
4185 | } | |
4186 | ||
4187 | void | |
4188 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4189 | { | |
4190 | struct drm_device *dev = obj->dev; | |
4191 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4192 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4193 | |
23bc5982 | 4194 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4195 | obj_priv->pin_count--; |
4196 | BUG_ON(obj_priv->pin_count < 0); | |
4197 | BUG_ON(obj_priv->gtt_space == NULL); | |
4198 | ||
4199 | /* If the object is no longer pinned, and is | |
4200 | * neither active nor being flushed, then stick it on | |
4201 | * the inactive list | |
4202 | */ | |
4203 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4204 | if (!obj_priv->active) |
69dc4987 | 4205 | list_move_tail(&obj_priv->mm_list, |
673a394b | 4206 | &dev_priv->mm.inactive_list); |
fb7d516a | 4207 | i915_gem_info_remove_pin(dev_priv, obj); |
673a394b | 4208 | } |
23bc5982 | 4209 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4210 | } |
4211 | ||
4212 | int | |
4213 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4214 | struct drm_file *file_priv) | |
4215 | { | |
4216 | struct drm_i915_gem_pin *args = data; | |
4217 | struct drm_gem_object *obj; | |
4218 | struct drm_i915_gem_object *obj_priv; | |
4219 | int ret; | |
4220 | ||
1d7cfea1 CW |
4221 | ret = i915_mutex_lock_interruptible(dev); |
4222 | if (ret) | |
4223 | return ret; | |
673a394b EA |
4224 | |
4225 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4226 | if (obj == NULL) { | |
1d7cfea1 CW |
4227 | ret = -ENOENT; |
4228 | goto unlock; | |
673a394b | 4229 | } |
23010e43 | 4230 | obj_priv = to_intel_bo(obj); |
673a394b | 4231 | |
bb6baf76 CW |
4232 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4233 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
1d7cfea1 CW |
4234 | ret = -EINVAL; |
4235 | goto out; | |
3ef94daa CW |
4236 | } |
4237 | ||
79e53945 JB |
4238 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4239 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4240 | args->handle); | |
1d7cfea1 CW |
4241 | ret = -EINVAL; |
4242 | goto out; | |
79e53945 JB |
4243 | } |
4244 | ||
4245 | obj_priv->user_pin_count++; | |
4246 | obj_priv->pin_filp = file_priv; | |
4247 | if (obj_priv->user_pin_count == 1) { | |
920afa77 | 4248 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
4249 | if (ret) |
4250 | goto out; | |
673a394b EA |
4251 | } |
4252 | ||
4253 | /* XXX - flush the CPU caches for pinned objects | |
4254 | * as the X server doesn't manage domains yet | |
4255 | */ | |
e47c68e9 | 4256 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b | 4257 | args->offset = obj_priv->gtt_offset; |
1d7cfea1 | 4258 | out: |
673a394b | 4259 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4260 | unlock: |
673a394b | 4261 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4262 | return ret; |
673a394b EA |
4263 | } |
4264 | ||
4265 | int | |
4266 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4267 | struct drm_file *file_priv) | |
4268 | { | |
4269 | struct drm_i915_gem_pin *args = data; | |
4270 | struct drm_gem_object *obj; | |
79e53945 | 4271 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4272 | int ret; |
673a394b | 4273 | |
1d7cfea1 CW |
4274 | ret = i915_mutex_lock_interruptible(dev); |
4275 | if (ret) | |
4276 | return ret; | |
673a394b EA |
4277 | |
4278 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4279 | if (obj == NULL) { | |
1d7cfea1 CW |
4280 | ret = -ENOENT; |
4281 | goto unlock; | |
673a394b | 4282 | } |
23010e43 | 4283 | obj_priv = to_intel_bo(obj); |
76c1dec1 | 4284 | |
79e53945 JB |
4285 | if (obj_priv->pin_filp != file_priv) { |
4286 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4287 | args->handle); | |
1d7cfea1 CW |
4288 | ret = -EINVAL; |
4289 | goto out; | |
79e53945 JB |
4290 | } |
4291 | obj_priv->user_pin_count--; | |
4292 | if (obj_priv->user_pin_count == 0) { | |
4293 | obj_priv->pin_filp = NULL; | |
4294 | i915_gem_object_unpin(obj); | |
4295 | } | |
673a394b | 4296 | |
1d7cfea1 | 4297 | out: |
673a394b | 4298 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4299 | unlock: |
673a394b | 4300 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4301 | return ret; |
673a394b EA |
4302 | } |
4303 | ||
4304 | int | |
4305 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4306 | struct drm_file *file_priv) | |
4307 | { | |
4308 | struct drm_i915_gem_busy *args = data; | |
4309 | struct drm_gem_object *obj; | |
4310 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4311 | int ret; |
4312 | ||
76c1dec1 | 4313 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4314 | if (ret) |
76c1dec1 | 4315 | return ret; |
673a394b | 4316 | |
673a394b EA |
4317 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4318 | if (obj == NULL) { | |
1d7cfea1 CW |
4319 | ret = -ENOENT; |
4320 | goto unlock; | |
673a394b | 4321 | } |
1d7cfea1 | 4322 | obj_priv = to_intel_bo(obj); |
d1b851fc | 4323 | |
0be555b6 CW |
4324 | /* Count all active objects as busy, even if they are currently not used |
4325 | * by the gpu. Users of this interface expect objects to eventually | |
4326 | * become non-busy without any further actions, therefore emit any | |
4327 | * necessary flushes here. | |
c4de0a5d | 4328 | */ |
0be555b6 CW |
4329 | args->busy = obj_priv->active; |
4330 | if (args->busy) { | |
4331 | /* Unconditionally flush objects, even when the gpu still uses this | |
4332 | * object. Userspace calling this function indicates that it wants to | |
4333 | * use this buffer rather sooner than later, so issuing the required | |
4334 | * flush earlier is beneficial. | |
4335 | */ | |
c78ec30b CW |
4336 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4337 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4338 | obj_priv->ring, |
4339 | 0, obj->write_domain); | |
0be555b6 CW |
4340 | |
4341 | /* Update the active list for the hardware's current position. | |
4342 | * Otherwise this only updates on a delayed timer or when irqs | |
4343 | * are actually unmasked, and our working set ends up being | |
4344 | * larger than required. | |
4345 | */ | |
4346 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4347 | ||
4348 | args->busy = obj_priv->active; | |
4349 | } | |
673a394b EA |
4350 | |
4351 | drm_gem_object_unreference(obj); | |
1d7cfea1 | 4352 | unlock: |
673a394b | 4353 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4354 | return ret; |
673a394b EA |
4355 | } |
4356 | ||
4357 | int | |
4358 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4359 | struct drm_file *file_priv) | |
4360 | { | |
4361 | return i915_gem_ring_throttle(dev, file_priv); | |
4362 | } | |
4363 | ||
3ef94daa CW |
4364 | int |
4365 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4366 | struct drm_file *file_priv) | |
4367 | { | |
4368 | struct drm_i915_gem_madvise *args = data; | |
4369 | struct drm_gem_object *obj; | |
4370 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4371 | int ret; |
3ef94daa CW |
4372 | |
4373 | switch (args->madv) { | |
4374 | case I915_MADV_DONTNEED: | |
4375 | case I915_MADV_WILLNEED: | |
4376 | break; | |
4377 | default: | |
4378 | return -EINVAL; | |
4379 | } | |
4380 | ||
1d7cfea1 CW |
4381 | ret = i915_mutex_lock_interruptible(dev); |
4382 | if (ret) | |
4383 | return ret; | |
4384 | ||
3ef94daa CW |
4385 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4386 | if (obj == NULL) { | |
1d7cfea1 CW |
4387 | ret = -ENOENT; |
4388 | goto unlock; | |
3ef94daa | 4389 | } |
23010e43 | 4390 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4391 | |
4392 | if (obj_priv->pin_count) { | |
1d7cfea1 CW |
4393 | ret = -EINVAL; |
4394 | goto out; | |
3ef94daa CW |
4395 | } |
4396 | ||
bb6baf76 CW |
4397 | if (obj_priv->madv != __I915_MADV_PURGED) |
4398 | obj_priv->madv = args->madv; | |
3ef94daa | 4399 | |
2d7ef395 CW |
4400 | /* if the object is no longer bound, discard its backing storage */ |
4401 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4402 | obj_priv->gtt_space == NULL) | |
4403 | i915_gem_object_truncate(obj); | |
4404 | ||
bb6baf76 CW |
4405 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4406 | ||
1d7cfea1 | 4407 | out: |
3ef94daa | 4408 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4409 | unlock: |
3ef94daa | 4410 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4411 | return ret; |
3ef94daa CW |
4412 | } |
4413 | ||
ac52bc56 DV |
4414 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4415 | size_t size) | |
4416 | { | |
73aa808f | 4417 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4418 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4419 | |
c397b908 DV |
4420 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4421 | if (obj == NULL) | |
4422 | return NULL; | |
673a394b | 4423 | |
c397b908 DV |
4424 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4425 | kfree(obj); | |
4426 | return NULL; | |
4427 | } | |
673a394b | 4428 | |
73aa808f CW |
4429 | i915_gem_info_add_obj(dev_priv, size); |
4430 | ||
c397b908 DV |
4431 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4432 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4433 | |
c397b908 | 4434 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4435 | obj->base.driver_private = NULL; |
c397b908 | 4436 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 CW |
4437 | INIT_LIST_HEAD(&obj->mm_list); |
4438 | INIT_LIST_HEAD(&obj->ring_list); | |
c397b908 | 4439 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4440 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4441 | |
c397b908 DV |
4442 | return &obj->base; |
4443 | } | |
4444 | ||
4445 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4446 | { | |
4447 | BUG(); | |
de151cf6 | 4448 | |
673a394b EA |
4449 | return 0; |
4450 | } | |
4451 | ||
be72615b | 4452 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4453 | { |
de151cf6 | 4454 | struct drm_device *dev = obj->dev; |
be72615b | 4455 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4456 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4457 | int ret; |
673a394b | 4458 | |
be72615b CW |
4459 | ret = i915_gem_object_unbind(obj); |
4460 | if (ret == -ERESTARTSYS) { | |
69dc4987 | 4461 | list_move(&obj_priv->mm_list, |
be72615b CW |
4462 | &dev_priv->mm.deferred_free_list); |
4463 | return; | |
4464 | } | |
673a394b | 4465 | |
7e616158 CW |
4466 | if (obj_priv->mmap_offset) |
4467 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4468 | |
c397b908 | 4469 | drm_gem_object_release(obj); |
73aa808f | 4470 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4471 | |
9a298b2a | 4472 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4473 | kfree(obj_priv->bit_17); |
c397b908 | 4474 | kfree(obj_priv); |
673a394b EA |
4475 | } |
4476 | ||
be72615b CW |
4477 | void i915_gem_free_object(struct drm_gem_object *obj) |
4478 | { | |
4479 | struct drm_device *dev = obj->dev; | |
4480 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4481 | ||
4482 | trace_i915_gem_object_destroy(obj); | |
4483 | ||
4484 | while (obj_priv->pin_count > 0) | |
4485 | i915_gem_object_unpin(obj); | |
4486 | ||
4487 | if (obj_priv->phys_obj) | |
4488 | i915_gem_detach_phys_object(dev, obj); | |
4489 | ||
4490 | i915_gem_free_object_tail(obj); | |
4491 | } | |
4492 | ||
29105ccc CW |
4493 | int |
4494 | i915_gem_idle(struct drm_device *dev) | |
4495 | { | |
4496 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4497 | int ret; | |
28dfe52a | 4498 | |
29105ccc | 4499 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4500 | |
87acb0a5 | 4501 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4502 | mutex_unlock(&dev->struct_mutex); |
4503 | return 0; | |
28dfe52a EA |
4504 | } |
4505 | ||
29105ccc | 4506 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4507 | if (ret) { |
4508 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4509 | return ret; |
6dbe2772 | 4510 | } |
673a394b | 4511 | |
29105ccc CW |
4512 | /* Under UMS, be paranoid and evict. */ |
4513 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4514 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4515 | if (ret) { |
4516 | mutex_unlock(&dev->struct_mutex); | |
4517 | return ret; | |
4518 | } | |
4519 | } | |
4520 | ||
4521 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4522 | * We need to replace this with a semaphore, or something. | |
4523 | * And not confound mm.suspended! | |
4524 | */ | |
4525 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4526 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4527 | |
4528 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4529 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4530 | |
6dbe2772 KP |
4531 | mutex_unlock(&dev->struct_mutex); |
4532 | ||
29105ccc CW |
4533 | /* Cancel the retire work handler, which should be idle now. */ |
4534 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4535 | ||
673a394b EA |
4536 | return 0; |
4537 | } | |
4538 | ||
e552eb70 JB |
4539 | /* |
4540 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4541 | * over cache flushing. | |
4542 | */ | |
8187a2b7 | 4543 | static int |
e552eb70 JB |
4544 | i915_gem_init_pipe_control(struct drm_device *dev) |
4545 | { | |
4546 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4547 | struct drm_gem_object *obj; | |
4548 | struct drm_i915_gem_object *obj_priv; | |
4549 | int ret; | |
4550 | ||
34dc4d44 | 4551 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4552 | if (obj == NULL) { |
4553 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4554 | ret = -ENOMEM; | |
4555 | goto err; | |
4556 | } | |
4557 | obj_priv = to_intel_bo(obj); | |
4558 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4559 | ||
920afa77 | 4560 | ret = i915_gem_object_pin(obj, 4096, true); |
e552eb70 JB |
4561 | if (ret) |
4562 | goto err_unref; | |
4563 | ||
4564 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4565 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4566 | if (dev_priv->seqno_page == NULL) | |
4567 | goto err_unpin; | |
4568 | ||
4569 | dev_priv->seqno_obj = obj; | |
4570 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4571 | ||
4572 | return 0; | |
4573 | ||
4574 | err_unpin: | |
4575 | i915_gem_object_unpin(obj); | |
4576 | err_unref: | |
4577 | drm_gem_object_unreference(obj); | |
4578 | err: | |
4579 | return ret; | |
4580 | } | |
4581 | ||
8187a2b7 ZN |
4582 | |
4583 | static void | |
e552eb70 JB |
4584 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4585 | { | |
4586 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4587 | struct drm_gem_object *obj; | |
4588 | struct drm_i915_gem_object *obj_priv; | |
4589 | ||
4590 | obj = dev_priv->seqno_obj; | |
4591 | obj_priv = to_intel_bo(obj); | |
4592 | kunmap(obj_priv->pages[0]); | |
4593 | i915_gem_object_unpin(obj); | |
4594 | drm_gem_object_unreference(obj); | |
4595 | dev_priv->seqno_obj = NULL; | |
4596 | ||
4597 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4598 | } |
4599 | ||
8187a2b7 ZN |
4600 | int |
4601 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4602 | { | |
4603 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4604 | int ret; | |
68f95ba9 | 4605 | |
8187a2b7 ZN |
4606 | if (HAS_PIPE_CONTROL(dev)) { |
4607 | ret = i915_gem_init_pipe_control(dev); | |
4608 | if (ret) | |
4609 | return ret; | |
4610 | } | |
68f95ba9 | 4611 | |
5c1143bb | 4612 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4613 | if (ret) |
4614 | goto cleanup_pipe_control; | |
4615 | ||
4616 | if (HAS_BSD(dev)) { | |
5c1143bb | 4617 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4618 | if (ret) |
4619 | goto cleanup_render_ring; | |
d1b851fc | 4620 | } |
68f95ba9 | 4621 | |
549f7365 CW |
4622 | if (HAS_BLT(dev)) { |
4623 | ret = intel_init_blt_ring_buffer(dev); | |
4624 | if (ret) | |
4625 | goto cleanup_bsd_ring; | |
4626 | } | |
4627 | ||
6f392d54 CW |
4628 | dev_priv->next_seqno = 1; |
4629 | ||
68f95ba9 CW |
4630 | return 0; |
4631 | ||
549f7365 | 4632 | cleanup_bsd_ring: |
78501eac | 4633 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4634 | cleanup_render_ring: |
78501eac | 4635 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
68f95ba9 CW |
4636 | cleanup_pipe_control: |
4637 | if (HAS_PIPE_CONTROL(dev)) | |
4638 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4639 | return ret; |
4640 | } | |
4641 | ||
4642 | void | |
4643 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4644 | { | |
4645 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4646 | ||
78501eac CW |
4647 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4648 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4649 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4650 | if (HAS_PIPE_CONTROL(dev)) |
4651 | i915_gem_cleanup_pipe_control(dev); | |
4652 | } | |
4653 | ||
673a394b EA |
4654 | int |
4655 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4656 | struct drm_file *file_priv) | |
4657 | { | |
4658 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4659 | int ret; | |
4660 | ||
79e53945 JB |
4661 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4662 | return 0; | |
4663 | ||
ba1234d1 | 4664 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4665 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4666 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4667 | } |
4668 | ||
673a394b | 4669 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4670 | dev_priv->mm.suspended = 0; |
4671 | ||
4672 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4673 | if (ret != 0) { |
4674 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4675 | return ret; |
d816f6ac | 4676 | } |
9bb2d6f9 | 4677 | |
69dc4987 | 4678 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4679 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4680 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4681 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4682 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4683 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4684 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4685 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4686 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4687 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4688 | |
5f35308b CW |
4689 | ret = drm_irq_install(dev); |
4690 | if (ret) | |
4691 | goto cleanup_ringbuffer; | |
dbb19d30 | 4692 | |
673a394b | 4693 | return 0; |
5f35308b CW |
4694 | |
4695 | cleanup_ringbuffer: | |
4696 | mutex_lock(&dev->struct_mutex); | |
4697 | i915_gem_cleanup_ringbuffer(dev); | |
4698 | dev_priv->mm.suspended = 1; | |
4699 | mutex_unlock(&dev->struct_mutex); | |
4700 | ||
4701 | return ret; | |
673a394b EA |
4702 | } |
4703 | ||
4704 | int | |
4705 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4706 | struct drm_file *file_priv) | |
4707 | { | |
79e53945 JB |
4708 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4709 | return 0; | |
4710 | ||
dbb19d30 | 4711 | drm_irq_uninstall(dev); |
e6890f6f | 4712 | return i915_gem_idle(dev); |
673a394b EA |
4713 | } |
4714 | ||
4715 | void | |
4716 | i915_gem_lastclose(struct drm_device *dev) | |
4717 | { | |
4718 | int ret; | |
673a394b | 4719 | |
e806b495 EA |
4720 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4721 | return; | |
4722 | ||
6dbe2772 KP |
4723 | ret = i915_gem_idle(dev); |
4724 | if (ret) | |
4725 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4726 | } |
4727 | ||
64193406 CW |
4728 | static void |
4729 | init_ring_lists(struct intel_ring_buffer *ring) | |
4730 | { | |
4731 | INIT_LIST_HEAD(&ring->active_list); | |
4732 | INIT_LIST_HEAD(&ring->request_list); | |
4733 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4734 | } | |
4735 | ||
673a394b EA |
4736 | void |
4737 | i915_gem_load(struct drm_device *dev) | |
4738 | { | |
b5aa8a0f | 4739 | int i; |
673a394b EA |
4740 | drm_i915_private_t *dev_priv = dev->dev_private; |
4741 | ||
69dc4987 | 4742 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4743 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4744 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4745 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4746 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4747 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
64193406 CW |
4748 | init_ring_lists(&dev_priv->render_ring); |
4749 | init_ring_lists(&dev_priv->bsd_ring); | |
4750 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4751 | for (i = 0; i < 16; i++) |
4752 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4753 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4754 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4755 | init_completion(&dev_priv->error_completion); |
31169714 CW |
4756 | spin_lock(&shrink_list_lock); |
4757 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4758 | spin_unlock(&shrink_list_lock); | |
4759 | ||
94400120 DA |
4760 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4761 | if (IS_GEN3(dev)) { | |
4762 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4763 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4764 | /* arb state is a masked write, so set bit + bit in mask */ | |
4765 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4766 | I915_WRITE(MI_ARB_STATE, tmp); | |
4767 | } | |
4768 | } | |
4769 | ||
de151cf6 | 4770 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4771 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4772 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4773 | |
a6c45cf0 | 4774 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4775 | dev_priv->num_fence_regs = 16; |
4776 | else | |
4777 | dev_priv->num_fence_regs = 8; | |
4778 | ||
b5aa8a0f | 4779 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4780 | switch (INTEL_INFO(dev)->gen) { |
4781 | case 6: | |
4782 | for (i = 0; i < 16; i++) | |
4783 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4784 | break; | |
4785 | case 5: | |
4786 | case 4: | |
b5aa8a0f GH |
4787 | for (i = 0; i < 16; i++) |
4788 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4789 | break; |
4790 | case 3: | |
b5aa8a0f GH |
4791 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4792 | for (i = 0; i < 8; i++) | |
4793 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4794 | case 2: |
4795 | for (i = 0; i < 8; i++) | |
4796 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4797 | break; | |
b5aa8a0f | 4798 | } |
673a394b | 4799 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4800 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4801 | } |
71acb5eb DA |
4802 | |
4803 | /* | |
4804 | * Create a physically contiguous memory object for this object | |
4805 | * e.g. for cursor + overlay regs | |
4806 | */ | |
995b6762 CW |
4807 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4808 | int id, int size, int align) | |
71acb5eb DA |
4809 | { |
4810 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4811 | struct drm_i915_gem_phys_object *phys_obj; | |
4812 | int ret; | |
4813 | ||
4814 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4815 | return 0; | |
4816 | ||
9a298b2a | 4817 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4818 | if (!phys_obj) |
4819 | return -ENOMEM; | |
4820 | ||
4821 | phys_obj->id = id; | |
4822 | ||
6eeefaf3 | 4823 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4824 | if (!phys_obj->handle) { |
4825 | ret = -ENOMEM; | |
4826 | goto kfree_obj; | |
4827 | } | |
4828 | #ifdef CONFIG_X86 | |
4829 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4830 | #endif | |
4831 | ||
4832 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4833 | ||
4834 | return 0; | |
4835 | kfree_obj: | |
9a298b2a | 4836 | kfree(phys_obj); |
71acb5eb DA |
4837 | return ret; |
4838 | } | |
4839 | ||
995b6762 | 4840 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4841 | { |
4842 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4843 | struct drm_i915_gem_phys_object *phys_obj; | |
4844 | ||
4845 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4846 | return; | |
4847 | ||
4848 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4849 | if (phys_obj->cur_obj) { | |
4850 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4851 | } | |
4852 | ||
4853 | #ifdef CONFIG_X86 | |
4854 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4855 | #endif | |
4856 | drm_pci_free(dev, phys_obj->handle); | |
4857 | kfree(phys_obj); | |
4858 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4859 | } | |
4860 | ||
4861 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4862 | { | |
4863 | int i; | |
4864 | ||
260883c8 | 4865 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4866 | i915_gem_free_phys_object(dev, i); |
4867 | } | |
4868 | ||
4869 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4870 | struct drm_gem_object *obj) | |
4871 | { | |
4872 | struct drm_i915_gem_object *obj_priv; | |
4873 | int i; | |
4874 | int ret; | |
4875 | int page_count; | |
4876 | ||
23010e43 | 4877 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4878 | if (!obj_priv->phys_obj) |
4879 | return; | |
4880 | ||
4bdadb97 | 4881 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4882 | if (ret) |
4883 | goto out; | |
4884 | ||
4885 | page_count = obj->size / PAGE_SIZE; | |
4886 | ||
4887 | for (i = 0; i < page_count; i++) { | |
3e4d3af5 | 4888 | char *dst = kmap_atomic(obj_priv->pages[i]); |
71acb5eb DA |
4889 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4890 | ||
4891 | memcpy(dst, src, PAGE_SIZE); | |
3e4d3af5 | 4892 | kunmap_atomic(dst); |
71acb5eb | 4893 | } |
856fa198 | 4894 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4895 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4896 | |
4897 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4898 | out: |
4899 | obj_priv->phys_obj->cur_obj = NULL; | |
4900 | obj_priv->phys_obj = NULL; | |
4901 | } | |
4902 | ||
4903 | int | |
4904 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4905 | struct drm_gem_object *obj, |
4906 | int id, | |
4907 | int align) | |
71acb5eb DA |
4908 | { |
4909 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4910 | struct drm_i915_gem_object *obj_priv; | |
4911 | int ret = 0; | |
4912 | int page_count; | |
4913 | int i; | |
4914 | ||
4915 | if (id > I915_MAX_PHYS_OBJECT) | |
4916 | return -EINVAL; | |
4917 | ||
23010e43 | 4918 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4919 | |
4920 | if (obj_priv->phys_obj) { | |
4921 | if (obj_priv->phys_obj->id == id) | |
4922 | return 0; | |
4923 | i915_gem_detach_phys_object(dev, obj); | |
4924 | } | |
4925 | ||
71acb5eb DA |
4926 | /* create a new object */ |
4927 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4928 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4929 | obj->size, align); |
71acb5eb | 4930 | if (ret) { |
aeb565df | 4931 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4932 | goto out; |
4933 | } | |
4934 | } | |
4935 | ||
4936 | /* bind to the object */ | |
4937 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4938 | obj_priv->phys_obj->cur_obj = obj; | |
4939 | ||
4bdadb97 | 4940 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4941 | if (ret) { |
4942 | DRM_ERROR("failed to get page list\n"); | |
4943 | goto out; | |
4944 | } | |
4945 | ||
4946 | page_count = obj->size / PAGE_SIZE; | |
4947 | ||
4948 | for (i = 0; i < page_count; i++) { | |
3e4d3af5 | 4949 | char *src = kmap_atomic(obj_priv->pages[i]); |
71acb5eb DA |
4950 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4951 | ||
4952 | memcpy(dst, src, PAGE_SIZE); | |
3e4d3af5 | 4953 | kunmap_atomic(src); |
71acb5eb DA |
4954 | } |
4955 | ||
d78b47b9 CW |
4956 | i915_gem_object_put_pages(obj); |
4957 | ||
71acb5eb DA |
4958 | return 0; |
4959 | out: | |
4960 | return ret; | |
4961 | } | |
4962 | ||
4963 | static int | |
4964 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4965 | struct drm_i915_gem_pwrite *args, | |
4966 | struct drm_file *file_priv) | |
4967 | { | |
23010e43 | 4968 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4969 | void *obj_addr; |
4970 | int ret; | |
4971 | char __user *user_data; | |
4972 | ||
4973 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4974 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4975 | ||
44d98a61 | 4976 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4977 | ret = copy_from_user(obj_addr, user_data, args->size); |
4978 | if (ret) | |
4979 | return -EFAULT; | |
4980 | ||
4981 | drm_agp_chipset_flush(dev); | |
4982 | return 0; | |
4983 | } | |
b962442e | 4984 | |
f787a5f5 | 4985 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4986 | { |
f787a5f5 | 4987 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4988 | |
4989 | /* Clean up our request list when the client is going away, so that | |
4990 | * later retire_requests won't dereference our soon-to-be-gone | |
4991 | * file_priv. | |
4992 | */ | |
1c25595f | 4993 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4994 | while (!list_empty(&file_priv->mm.request_list)) { |
4995 | struct drm_i915_gem_request *request; | |
4996 | ||
4997 | request = list_first_entry(&file_priv->mm.request_list, | |
4998 | struct drm_i915_gem_request, | |
4999 | client_list); | |
5000 | list_del(&request->client_list); | |
5001 | request->file_priv = NULL; | |
5002 | } | |
1c25595f | 5003 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5004 | } |
31169714 | 5005 | |
1637ef41 CW |
5006 | static int |
5007 | i915_gpu_is_active(struct drm_device *dev) | |
5008 | { | |
5009 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5010 | int lists_empty; | |
5011 | ||
1637ef41 | 5012 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
87acb0a5 | 5013 | list_empty(&dev_priv->render_ring.active_list) && |
549f7365 CW |
5014 | list_empty(&dev_priv->bsd_ring.active_list) && |
5015 | list_empty(&dev_priv->blt_ring.active_list); | |
1637ef41 CW |
5016 | |
5017 | return !lists_empty; | |
5018 | } | |
5019 | ||
31169714 | 5020 | static int |
7f8275d0 | 5021 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
5022 | { |
5023 | drm_i915_private_t *dev_priv, *next_dev; | |
5024 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
5025 | int cnt = 0; | |
5026 | int would_deadlock = 1; | |
5027 | ||
5028 | /* "fast-path" to count number of available objects */ | |
5029 | if (nr_to_scan == 0) { | |
5030 | spin_lock(&shrink_list_lock); | |
5031 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5032 | struct drm_device *dev = dev_priv->dev; | |
5033 | ||
5034 | if (mutex_trylock(&dev->struct_mutex)) { | |
5035 | list_for_each_entry(obj_priv, | |
5036 | &dev_priv->mm.inactive_list, | |
69dc4987 | 5037 | mm_list) |
31169714 CW |
5038 | cnt++; |
5039 | mutex_unlock(&dev->struct_mutex); | |
5040 | } | |
5041 | } | |
5042 | spin_unlock(&shrink_list_lock); | |
5043 | ||
5044 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5045 | } | |
5046 | ||
5047 | spin_lock(&shrink_list_lock); | |
5048 | ||
1637ef41 | 5049 | rescan: |
31169714 CW |
5050 | /* first scan for clean buffers */ |
5051 | list_for_each_entry_safe(dev_priv, next_dev, | |
5052 | &shrink_list, mm.shrink_list) { | |
5053 | struct drm_device *dev = dev_priv->dev; | |
5054 | ||
5055 | if (! mutex_trylock(&dev->struct_mutex)) | |
5056 | continue; | |
5057 | ||
5058 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 5059 | i915_gem_retire_requests(dev); |
31169714 CW |
5060 | |
5061 | list_for_each_entry_safe(obj_priv, next_obj, | |
5062 | &dev_priv->mm.inactive_list, | |
69dc4987 | 5063 | mm_list) { |
31169714 | 5064 | if (i915_gem_object_is_purgeable(obj_priv)) { |
a8089e84 | 5065 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5066 | if (--nr_to_scan <= 0) |
5067 | break; | |
5068 | } | |
5069 | } | |
5070 | ||
5071 | spin_lock(&shrink_list_lock); | |
5072 | mutex_unlock(&dev->struct_mutex); | |
5073 | ||
963b4836 CW |
5074 | would_deadlock = 0; |
5075 | ||
31169714 CW |
5076 | if (nr_to_scan <= 0) |
5077 | break; | |
5078 | } | |
5079 | ||
5080 | /* second pass, evict/count anything still on the inactive list */ | |
5081 | list_for_each_entry_safe(dev_priv, next_dev, | |
5082 | &shrink_list, mm.shrink_list) { | |
5083 | struct drm_device *dev = dev_priv->dev; | |
5084 | ||
5085 | if (! mutex_trylock(&dev->struct_mutex)) | |
5086 | continue; | |
5087 | ||
5088 | spin_unlock(&shrink_list_lock); | |
5089 | ||
5090 | list_for_each_entry_safe(obj_priv, next_obj, | |
5091 | &dev_priv->mm.inactive_list, | |
69dc4987 | 5092 | mm_list) { |
31169714 | 5093 | if (nr_to_scan > 0) { |
a8089e84 | 5094 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5095 | nr_to_scan--; |
5096 | } else | |
5097 | cnt++; | |
5098 | } | |
5099 | ||
5100 | spin_lock(&shrink_list_lock); | |
5101 | mutex_unlock(&dev->struct_mutex); | |
5102 | ||
5103 | would_deadlock = 0; | |
5104 | } | |
5105 | ||
1637ef41 CW |
5106 | if (nr_to_scan) { |
5107 | int active = 0; | |
5108 | ||
5109 | /* | |
5110 | * We are desperate for pages, so as a last resort, wait | |
5111 | * for the GPU to finish and discard whatever we can. | |
5112 | * This has a dramatic impact to reduce the number of | |
5113 | * OOM-killer events whilst running the GPU aggressively. | |
5114 | */ | |
5115 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5116 | struct drm_device *dev = dev_priv->dev; | |
5117 | ||
5118 | if (!mutex_trylock(&dev->struct_mutex)) | |
5119 | continue; | |
5120 | ||
5121 | spin_unlock(&shrink_list_lock); | |
5122 | ||
5123 | if (i915_gpu_is_active(dev)) { | |
5124 | i915_gpu_idle(dev); | |
5125 | active++; | |
5126 | } | |
5127 | ||
5128 | spin_lock(&shrink_list_lock); | |
5129 | mutex_unlock(&dev->struct_mutex); | |
5130 | } | |
5131 | ||
5132 | if (active) | |
5133 | goto rescan; | |
5134 | } | |
5135 | ||
31169714 CW |
5136 | spin_unlock(&shrink_list_lock); |
5137 | ||
5138 | if (would_deadlock) | |
5139 | return -1; | |
5140 | else if (cnt > 0) | |
5141 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5142 | else | |
5143 | return 0; | |
5144 | } | |
5145 | ||
5146 | static struct shrinker shrinker = { | |
5147 | .shrink = i915_gem_shrink, | |
5148 | .seeks = DEFAULT_SEEKS, | |
5149 | }; | |
5150 | ||
5151 | __init void | |
5152 | i915_gem_shrinker_init(void) | |
5153 | { | |
5154 | register_shrinker(&shrinker); | |
5155 | } | |
5156 | ||
5157 | __exit void | |
5158 | i915_gem_shrinker_exit(void) | |
5159 | { | |
5160 | unregister_shrinker(&shrinker); | |
5161 | } |