Commit | Line | Data |
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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c BW |
90 | #include "i915_drv.h" |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
b731d33d BW |
96 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 98 | |
67e3d297 BW |
99 | static int do_switch(struct intel_ring_buffer *ring, |
100 | struct i915_hw_context *to); | |
40521054 | 101 | |
b18b6bde | 102 | static void do_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
321f2ada | 103 | { |
321f2ada BW |
104 | struct drm_device *dev = ppgtt->base.dev; |
105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
106 | struct i915_address_space *vm = &ppgtt->base; | |
107 | ||
108 | if (ppgtt == dev_priv->mm.aliasing_ppgtt || | |
109 | (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) { | |
110 | ppgtt->base.cleanup(&ppgtt->base); | |
111 | return; | |
112 | } | |
113 | ||
114 | /* | |
115 | * Make sure vmas are unbound before we take down the drm_mm | |
116 | * | |
117 | * FIXME: Proper refcounting should take care of this, this shouldn't be | |
118 | * needed at all. | |
119 | */ | |
120 | if (!list_empty(&vm->active_list)) { | |
121 | struct i915_vma *vma; | |
122 | ||
123 | list_for_each_entry(vma, &vm->active_list, mm_list) | |
124 | if (WARN_ON(list_empty(&vma->vma_link) || | |
125 | list_is_singular(&vma->vma_link))) | |
126 | break; | |
127 | ||
128 | i915_gem_evict_vm(&ppgtt->base, true); | |
129 | } else { | |
130 | i915_gem_retire_requests(dev); | |
131 | i915_gem_evict_vm(&ppgtt->base, false); | |
132 | } | |
133 | ||
134 | ppgtt->base.cleanup(&ppgtt->base); | |
135 | } | |
136 | ||
b18b6bde BW |
137 | static void ppgtt_release(struct kref *kref) |
138 | { | |
139 | struct i915_hw_ppgtt *ppgtt = | |
140 | container_of(kref, struct i915_hw_ppgtt, ref); | |
141 | ||
142 | do_ppgtt_cleanup(ppgtt); | |
143 | kfree(ppgtt); | |
144 | } | |
145 | ||
b731d33d BW |
146 | static size_t get_context_alignment(struct drm_device *dev) |
147 | { | |
148 | if (IS_GEN6(dev)) | |
149 | return GEN6_CONTEXT_ALIGN; | |
150 | ||
151 | return GEN7_CONTEXT_ALIGN; | |
152 | } | |
153 | ||
254f965c BW |
154 | static int get_context_size(struct drm_device *dev) |
155 | { | |
156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
157 | int ret; | |
158 | u32 reg; | |
159 | ||
160 | switch (INTEL_INFO(dev)->gen) { | |
161 | case 6: | |
162 | reg = I915_READ(CXT_SIZE); | |
163 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
164 | break; | |
165 | case 7: | |
4f91dd6f | 166 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 167 | if (IS_HASWELL(dev)) |
a0de80a0 | 168 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
169 | else |
170 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 171 | break; |
8897644a BW |
172 | case 8: |
173 | ret = GEN8_CXT_TOTAL_SIZE; | |
174 | break; | |
254f965c BW |
175 | default: |
176 | BUG(); | |
177 | } | |
178 | ||
179 | return ret; | |
180 | } | |
181 | ||
dce3271b | 182 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 183 | { |
dce3271b MK |
184 | struct i915_hw_context *ctx = container_of(ctx_ref, |
185 | typeof(*ctx), ref); | |
c7c48dfd | 186 | struct i915_hw_ppgtt *ppgtt = NULL; |
40521054 | 187 | |
c7c48dfd | 188 | /* We refcount even the aliasing PPGTT to keep the code symmetric */ |
c5dc5cec | 189 | if (USES_PPGTT(ctx->obj->base.dev)) |
0eea67eb | 190 | ppgtt = ctx_to_ppgtt(ctx); |
c7c48dfd BW |
191 | |
192 | /* XXX: Free up the object before tearing down the address space, in | |
193 | * case we're bound in the PPGTT */ | |
40521054 | 194 | drm_gem_object_unreference(&ctx->obj->base); |
c7c48dfd BW |
195 | |
196 | if (ppgtt) | |
197 | kref_put(&ppgtt->ref, ppgtt_release); | |
198 | list_del(&ctx->link); | |
40521054 BW |
199 | kfree(ctx); |
200 | } | |
201 | ||
bdf4fd7e BW |
202 | static struct i915_hw_ppgtt * |
203 | create_vm_for_ctx(struct drm_device *dev, struct i915_hw_context *ctx) | |
204 | { | |
205 | struct i915_hw_ppgtt *ppgtt; | |
206 | int ret; | |
207 | ||
208 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
209 | if (!ppgtt) | |
210 | return ERR_PTR(-ENOMEM); | |
211 | ||
212 | ret = i915_gem_init_ppgtt(dev, ppgtt); | |
213 | if (ret) { | |
214 | kfree(ppgtt); | |
215 | return ERR_PTR(ret); | |
216 | } | |
217 | ||
6313c204 | 218 | ppgtt->ctx = ctx; |
bdf4fd7e BW |
219 | return ppgtt; |
220 | } | |
221 | ||
146937e5 | 222 | static struct i915_hw_context * |
0eea67eb | 223 | __create_hw_context(struct drm_device *dev, |
146937e5 | 224 | struct drm_i915_file_private *file_priv) |
40521054 BW |
225 | { |
226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146937e5 | 227 | struct i915_hw_context *ctx; |
c8c470af | 228 | int ret; |
40521054 | 229 | |
f94982b0 | 230 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
231 | if (ctx == NULL) |
232 | return ERR_PTR(-ENOMEM); | |
40521054 | 233 | |
dce3271b | 234 | kref_init(&ctx->ref); |
146937e5 | 235 | ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); |
a33afea5 | 236 | INIT_LIST_HEAD(&ctx->link); |
146937e5 BW |
237 | if (ctx->obj == NULL) { |
238 | kfree(ctx); | |
40521054 | 239 | DRM_DEBUG_DRIVER("Context object allocated failed\n"); |
146937e5 | 240 | return ERR_PTR(-ENOMEM); |
40521054 BW |
241 | } |
242 | ||
4615d4c9 CW |
243 | if (INTEL_INFO(dev)->gen >= 7) { |
244 | ret = i915_gem_object_set_cache_level(ctx->obj, | |
350ec881 | 245 | I915_CACHE_L3_LLC); |
bb036413 BW |
246 | /* Failure shouldn't ever happen this early */ |
247 | if (WARN_ON(ret)) | |
4615d4c9 CW |
248 | goto err_out; |
249 | } | |
250 | ||
a33afea5 | 251 | list_add_tail(&ctx->link, &dev_priv->context_list); |
40521054 BW |
252 | |
253 | /* Default context will never have a file_priv */ | |
254 | if (file_priv == NULL) | |
146937e5 | 255 | return ctx; |
40521054 | 256 | |
0eea67eb | 257 | ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID, 0, |
c8c470af TH |
258 | GFP_KERNEL); |
259 | if (ret < 0) | |
40521054 | 260 | goto err_out; |
dce3271b MK |
261 | |
262 | ctx->file_priv = file_priv; | |
c8c470af | 263 | ctx->id = ret; |
3ccfd19d BW |
264 | /* NB: Mark all slices as needing a remap so that when the context first |
265 | * loads it will restore whatever remap state already exists. If there | |
266 | * is no remap info, it will be a NOP. */ | |
267 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 268 | |
146937e5 | 269 | return ctx; |
40521054 BW |
270 | |
271 | err_out: | |
dce3271b | 272 | i915_gem_context_unreference(ctx); |
146937e5 | 273 | return ERR_PTR(ret); |
40521054 BW |
274 | } |
275 | ||
254f965c BW |
276 | /** |
277 | * The default context needs to exist per ring that uses contexts. It stores the | |
278 | * context state of the GPU for applications that don't utilize HW contexts, as | |
279 | * well as an idle case. | |
280 | */ | |
a45d0f6a | 281 | static struct i915_hw_context * |
0eea67eb BW |
282 | i915_gem_create_context(struct drm_device *dev, |
283 | struct drm_i915_file_private *file_priv, | |
284 | bool create_vm) | |
254f965c | 285 | { |
42c3b603 | 286 | const bool is_global_default_ctx = file_priv == NULL; |
bdf4fd7e | 287 | struct drm_i915_private *dev_priv = dev->dev_private; |
40521054 | 288 | struct i915_hw_context *ctx; |
bdf4fd7e | 289 | int ret = 0; |
40521054 | 290 | |
b731d33d | 291 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 292 | |
0eea67eb | 293 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 294 | if (IS_ERR(ctx)) |
a45d0f6a | 295 | return ctx; |
40521054 | 296 | |
42c3b603 CW |
297 | if (is_global_default_ctx) { |
298 | /* We may need to do things with the shrinker which | |
299 | * require us to immediately switch back to the default | |
300 | * context. This can cause a problem as pinning the | |
301 | * default context also requires GTT space which may not | |
302 | * be available. To avoid this we always pin the default | |
303 | * context. | |
304 | */ | |
305 | ret = i915_gem_obj_ggtt_pin(ctx->obj, | |
1ec9e26d | 306 | get_context_alignment(dev), 0); |
42c3b603 CW |
307 | if (ret) { |
308 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
309 | goto err_destroy; | |
310 | } | |
311 | } | |
312 | ||
bdf4fd7e BW |
313 | if (create_vm) { |
314 | struct i915_hw_ppgtt *ppgtt = create_vm_for_ctx(dev, ctx); | |
315 | ||
316 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
317 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
318 | PTR_ERR(ppgtt)); | |
bdf4fd7e | 319 | ret = PTR_ERR(ppgtt); |
42c3b603 | 320 | goto err_unpin; |
bdf4fd7e BW |
321 | } else |
322 | ctx->vm = &ppgtt->base; | |
323 | ||
324 | /* This case is reserved for the global default context and | |
325 | * should only happen once. */ | |
42c3b603 | 326 | if (is_global_default_ctx) { |
bdf4fd7e BW |
327 | if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) { |
328 | ret = -EEXIST; | |
42c3b603 | 329 | goto err_unpin; |
bdf4fd7e BW |
330 | } |
331 | ||
332 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
bdf4fd7e | 333 | } |
c5dc5cec | 334 | } else if (USES_PPGTT(dev)) { |
bdf4fd7e BW |
335 | /* For platforms which only have aliasing PPGTT, we fake the |
336 | * address space and refcounting. */ | |
bdf4fd7e | 337 | ctx->vm = &dev_priv->mm.aliasing_ppgtt->base; |
7e0d96bc BW |
338 | kref_get(&dev_priv->mm.aliasing_ppgtt->ref); |
339 | } else | |
bdf4fd7e BW |
340 | ctx->vm = &dev_priv->gtt.base; |
341 | ||
a45d0f6a | 342 | return ctx; |
9a3b5304 | 343 | |
42c3b603 CW |
344 | err_unpin: |
345 | if (is_global_default_ctx) | |
346 | i915_gem_object_ggtt_unpin(ctx->obj); | |
9a3b5304 | 347 | err_destroy: |
dce3271b | 348 | i915_gem_context_unreference(ctx); |
a45d0f6a | 349 | return ERR_PTR(ret); |
254f965c BW |
350 | } |
351 | ||
acce9ffa BW |
352 | void i915_gem_context_reset(struct drm_device *dev) |
353 | { | |
354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
355 | struct intel_ring_buffer *ring; | |
356 | int i; | |
357 | ||
358 | if (!HAS_HW_CONTEXTS(dev)) | |
359 | return; | |
360 | ||
361 | /* Prevent the hardware from restoring the last context (which hung) on | |
362 | * the next switch */ | |
363 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
364 | struct i915_hw_context *dctx; | |
365 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
366 | continue; | |
367 | ||
368 | /* Do a fake switch to the default context */ | |
369 | ring = &dev_priv->ring[i]; | |
370 | dctx = ring->default_context; | |
371 | if (WARN_ON(!dctx)) | |
372 | continue; | |
373 | ||
374 | if (!ring->last_context) | |
375 | continue; | |
376 | ||
377 | if (ring->last_context == dctx) | |
378 | continue; | |
379 | ||
380 | if (i == RCS) { | |
381 | WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj, | |
1ec9e26d | 382 | get_context_alignment(dev), 0)); |
acce9ffa BW |
383 | /* Fake a finish/inactive */ |
384 | dctx->obj->base.write_domain = 0; | |
385 | dctx->obj->active = 0; | |
386 | } | |
387 | ||
388 | i915_gem_context_unreference(ring->last_context); | |
389 | i915_gem_context_reference(dctx); | |
390 | ring->last_context = dctx; | |
391 | } | |
392 | } | |
393 | ||
8245be31 | 394 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
395 | { |
396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
67e3d297 | 397 | struct intel_ring_buffer *ring; |
a45d0f6a | 398 | int i; |
254f965c | 399 | |
8245be31 BW |
400 | if (!HAS_HW_CONTEXTS(dev)) |
401 | return 0; | |
254f965c | 402 | |
2fa48d8d BW |
403 | /* Init should only be called once per module load. Eventually the |
404 | * restriction on the context_disabled check can be loosened. */ | |
405 | if (WARN_ON(dev_priv->ring[RCS].default_context)) | |
8245be31 | 406 | return 0; |
254f965c | 407 | |
07ea0d85 | 408 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
254f965c | 409 | |
07ea0d85 | 410 | if (dev_priv->hw_context_size > (1<<20)) { |
bb036413 | 411 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n"); |
8245be31 | 412 | return -E2BIG; |
254f965c BW |
413 | } |
414 | ||
bdf4fd7e | 415 | dev_priv->ring[RCS].default_context = |
c5dc5cec | 416 | i915_gem_create_context(dev, NULL, USES_PPGTT(dev)); |
a45d0f6a | 417 | |
a45d0f6a BW |
418 | if (IS_ERR_OR_NULL(dev_priv->ring[RCS].default_context)) { |
419 | DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed %ld\n", | |
420 | PTR_ERR(dev_priv->ring[RCS].default_context)); | |
421 | return PTR_ERR(dev_priv->ring[RCS].default_context); | |
254f965c BW |
422 | } |
423 | ||
67e3d297 BW |
424 | for (i = RCS + 1; i < I915_NUM_RINGS; i++) { |
425 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
426 | continue; | |
427 | ||
428 | ring = &dev_priv->ring[i]; | |
429 | ||
430 | /* NB: RCS will hold a ref for all rings */ | |
431 | ring->default_context = dev_priv->ring[RCS].default_context; | |
432 | } | |
433 | ||
254f965c | 434 | DRM_DEBUG_DRIVER("HW context support initialized\n"); |
8245be31 | 435 | return 0; |
254f965c BW |
436 | } |
437 | ||
438 | void i915_gem_context_fini(struct drm_device *dev) | |
439 | { | |
440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dce3271b | 441 | struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 442 | int i; |
254f965c | 443 | |
8245be31 | 444 | if (!HAS_HW_CONTEXTS(dev)) |
254f965c | 445 | return; |
40521054 | 446 | |
55a66628 DV |
447 | /* The only known way to stop the gpu from accessing the hw context is |
448 | * to reset it. Do this as the very last operation to avoid confusing | |
449 | * other code, leading to spurious errors. */ | |
450 | intel_gpu_reset(dev); | |
451 | ||
168f8366 MK |
452 | /* When default context is created and switched to, base object refcount |
453 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
454 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
455 | * to default context. So we need to unreference the base object once | |
456 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
457 | * can then free the base object correctly. */ | |
71b76d00 BW |
458 | WARN_ON(!dev_priv->ring[RCS].last_context); |
459 | if (dev_priv->ring[RCS].last_context == dctx) { | |
460 | /* Fake switch to NULL context */ | |
461 | WARN_ON(dctx->obj->active); | |
d7f46fc4 | 462 | i915_gem_object_ggtt_unpin(dctx->obj); |
71b76d00 | 463 | i915_gem_context_unreference(dctx); |
67e3d297 BW |
464 | dev_priv->ring[RCS].last_context = NULL; |
465 | } | |
466 | ||
467 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
468 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
469 | if (!(INTEL_INFO(dev)->ring_mask & (1<<i))) | |
470 | continue; | |
471 | ||
472 | if (ring->last_context) | |
473 | i915_gem_context_unreference(ring->last_context); | |
474 | ||
475 | ring->default_context = NULL; | |
0009e46c | 476 | ring->last_context = NULL; |
71b76d00 BW |
477 | } |
478 | ||
d7f46fc4 | 479 | i915_gem_object_ggtt_unpin(dctx->obj); |
dce3271b | 480 | i915_gem_context_unreference(dctx); |
bdf4fd7e | 481 | dev_priv->mm.aliasing_ppgtt = NULL; |
254f965c BW |
482 | } |
483 | ||
2fa48d8d BW |
484 | int i915_gem_context_enable(struct drm_i915_private *dev_priv) |
485 | { | |
486 | struct intel_ring_buffer *ring; | |
487 | int ret, i; | |
488 | ||
489 | if (!HAS_HW_CONTEXTS(dev_priv->dev)) | |
490 | return 0; | |
491 | ||
bdf4fd7e BW |
492 | /* This is the only place the aliasing PPGTT gets enabled, which means |
493 | * it has to happen before we bail on reset */ | |
494 | if (dev_priv->mm.aliasing_ppgtt) { | |
495 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
496 | ppgtt->enable(ppgtt); | |
497 | } | |
498 | ||
2fa48d8d BW |
499 | /* FIXME: We should make this work, even in reset */ |
500 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
501 | return 0; | |
502 | ||
503 | BUG_ON(!dev_priv->ring[RCS].default_context); | |
bdf4fd7e | 504 | |
2fa48d8d BW |
505 | for_each_ring(ring, dev_priv, i) { |
506 | ret = do_switch(ring, ring->default_context); | |
507 | if (ret) | |
508 | return ret; | |
509 | } | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
40521054 BW |
514 | static int context_idr_cleanup(int id, void *p, void *data) |
515 | { | |
73c273eb | 516 | struct i915_hw_context *ctx = p; |
40521054 | 517 | |
0eea67eb | 518 | /* Ignore the default context because close will handle it */ |
3fac8978 | 519 | if (i915_gem_context_is_default(ctx)) |
0eea67eb | 520 | return 0; |
40521054 | 521 | |
dce3271b | 522 | i915_gem_context_unreference(ctx); |
40521054 | 523 | return 0; |
254f965c BW |
524 | } |
525 | ||
e422b888 BW |
526 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
527 | { | |
528 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
c482972a | 529 | struct drm_i915_private *dev_priv = dev->dev_private; |
e422b888 | 530 | |
c482972a BW |
531 | if (!HAS_HW_CONTEXTS(dev)) { |
532 | /* Cheat for hang stats */ | |
533 | file_priv->private_default_ctx = | |
534 | kzalloc(sizeof(struct i915_hw_context), GFP_KERNEL); | |
7f76b23a MK |
535 | |
536 | if (file_priv->private_default_ctx == NULL) | |
537 | return -ENOMEM; | |
538 | ||
c482972a | 539 | file_priv->private_default_ctx->vm = &dev_priv->gtt.base; |
e422b888 | 540 | return 0; |
c482972a | 541 | } |
e422b888 BW |
542 | |
543 | idr_init(&file_priv->context_idr); | |
544 | ||
0eea67eb BW |
545 | mutex_lock(&dev->struct_mutex); |
546 | file_priv->private_default_ctx = | |
7e0d96bc | 547 | i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
0eea67eb BW |
548 | mutex_unlock(&dev->struct_mutex); |
549 | ||
550 | if (IS_ERR(file_priv->private_default_ctx)) { | |
551 | idr_destroy(&file_priv->context_idr); | |
552 | return PTR_ERR(file_priv->private_default_ctx); | |
553 | } | |
554 | ||
e422b888 BW |
555 | return 0; |
556 | } | |
557 | ||
254f965c BW |
558 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
559 | { | |
40521054 | 560 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 561 | |
c482972a BW |
562 | if (!HAS_HW_CONTEXTS(dev)) { |
563 | kfree(file_priv->private_default_ctx); | |
e422b888 | 564 | return; |
c482972a | 565 | } |
e422b888 | 566 | |
73c273eb | 567 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
0eea67eb | 568 | i915_gem_context_unreference(file_priv->private_default_ctx); |
40521054 | 569 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
570 | } |
571 | ||
41bde553 | 572 | struct i915_hw_context * |
40521054 BW |
573 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
574 | { | |
72ad5c45 BW |
575 | struct i915_hw_context *ctx; |
576 | ||
41bde553 BW |
577 | if (!HAS_HW_CONTEXTS(file_priv->dev_priv->dev)) |
578 | return file_priv->private_default_ctx; | |
579 | ||
72ad5c45 BW |
580 | ctx = (struct i915_hw_context *)idr_find(&file_priv->context_idr, id); |
581 | if (!ctx) | |
582 | return ERR_PTR(-ENOENT); | |
583 | ||
584 | return ctx; | |
254f965c | 585 | } |
e0556841 BW |
586 | |
587 | static inline int | |
588 | mi_set_context(struct intel_ring_buffer *ring, | |
589 | struct i915_hw_context *new_context, | |
590 | u32 hw_flags) | |
591 | { | |
592 | int ret; | |
593 | ||
12b0286f BW |
594 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
595 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
596 | * explicitly, so we rely on the value at ring init, stored in | |
597 | * itlb_before_ctx_switch. | |
598 | */ | |
599 | if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { | |
ac82ea2e | 600 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
601 | if (ret) |
602 | return ret; | |
603 | } | |
604 | ||
e37ec39b | 605 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
606 | if (ret) |
607 | return ret; | |
608 | ||
8693a824 | 609 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */ |
e37ec39b BW |
610 | if (IS_GEN7(ring->dev)) |
611 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
612 | else | |
613 | intel_ring_emit(ring, MI_NOOP); | |
614 | ||
e0556841 BW |
615 | intel_ring_emit(ring, MI_NOOP); |
616 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 617 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) | |
e0556841 BW |
618 | MI_MM_SPACE_GTT | |
619 | MI_SAVE_EXT_STATE_EN | | |
620 | MI_RESTORE_EXT_STATE_EN | | |
621 | hw_flags); | |
2b7e8082 VS |
622 | /* |
623 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
624 | * WaMiSetContext_Hang:snb,ivb,vlv | |
625 | */ | |
e0556841 BW |
626 | intel_ring_emit(ring, MI_NOOP); |
627 | ||
e37ec39b BW |
628 | if (IS_GEN7(ring->dev)) |
629 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
630 | else | |
631 | intel_ring_emit(ring, MI_NOOP); | |
632 | ||
e0556841 BW |
633 | intel_ring_advance(ring); |
634 | ||
635 | return ret; | |
636 | } | |
637 | ||
67e3d297 BW |
638 | static int do_switch(struct intel_ring_buffer *ring, |
639 | struct i915_hw_context *to) | |
e0556841 | 640 | { |
6f65e29a | 641 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
112522f6 | 642 | struct i915_hw_context *from = ring->last_context; |
7e0d96bc | 643 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to); |
e0556841 | 644 | u32 hw_flags = 0; |
3ccfd19d | 645 | int ret, i; |
e0556841 | 646 | |
67e3d297 BW |
647 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
648 | BUG_ON(from->obj == NULL); | |
649 | BUG_ON(!i915_gem_obj_is_pinned(from->obj)); | |
650 | } | |
e0556841 | 651 | |
0009e46c | 652 | if (from == to && from->last_ring == ring && !to->remap_slice) |
9a3b5304 CW |
653 | return 0; |
654 | ||
7e0d96bc BW |
655 | /* Trying to pin first makes error handling easier. */ |
656 | if (ring == &dev_priv->ring[RCS]) { | |
657 | ret = i915_gem_obj_ggtt_pin(to->obj, | |
1ec9e26d | 658 | get_context_alignment(ring->dev), 0); |
7e0d96bc BW |
659 | if (ret) |
660 | return ret; | |
67e3d297 BW |
661 | } |
662 | ||
acc240d4 DV |
663 | /* |
664 | * Pin can switch back to the default context if we end up calling into | |
665 | * evict_everything - as a last ditch gtt defrag effort that also | |
666 | * switches to the default context. Hence we need to reload from here. | |
667 | */ | |
668 | from = ring->last_context; | |
669 | ||
7e0d96bc BW |
670 | if (USES_FULL_PPGTT(ring->dev)) { |
671 | ret = ppgtt->switch_mm(ppgtt, ring, false); | |
672 | if (ret) | |
673 | goto unpin_out; | |
674 | } | |
675 | ||
676 | if (ring != &dev_priv->ring[RCS]) { | |
677 | if (from) | |
678 | i915_gem_context_unreference(from); | |
679 | goto done; | |
680 | } | |
681 | ||
acc240d4 DV |
682 | /* |
683 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
684 | * that thanks to write = false in this call and us not setting any gpu |
685 | * write domains when putting a context object onto the active list | |
686 | * (when switching away from it), this won't block. | |
acc240d4 DV |
687 | * |
688 | * XXX: We need a real interface to do this instead of trickery. | |
689 | */ | |
d3373a24 | 690 | ret = i915_gem_object_set_to_gtt_domain(to->obj, false); |
7e0d96bc BW |
691 | if (ret) |
692 | goto unpin_out; | |
d3373a24 | 693 | |
6f65e29a BW |
694 | if (!to->obj->has_global_gtt_mapping) { |
695 | struct i915_vma *vma = i915_gem_obj_to_vma(to->obj, | |
696 | &dev_priv->gtt.base); | |
697 | vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND); | |
698 | } | |
3af7b857 | 699 | |
3fac8978 | 700 | if (!to->is_initialized || i915_gem_context_is_default(to)) |
e0556841 | 701 | hw_flags |= MI_RESTORE_INHIBIT; |
e0556841 | 702 | |
e0556841 | 703 | ret = mi_set_context(ring, to, hw_flags); |
7e0d96bc BW |
704 | if (ret) |
705 | goto unpin_out; | |
e0556841 | 706 | |
3ccfd19d BW |
707 | for (i = 0; i < MAX_L3_SLICES; i++) { |
708 | if (!(to->remap_slice & (1<<i))) | |
709 | continue; | |
710 | ||
711 | ret = i915_gem_l3_remap(ring, i); | |
712 | /* If it failed, try again next round */ | |
713 | if (ret) | |
714 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
715 | else | |
716 | to->remap_slice &= ~(1<<i); | |
717 | } | |
718 | ||
e0556841 BW |
719 | /* The backing object for the context is done after switching to the |
720 | * *next* context. Therefore we cannot retire the previous context until | |
721 | * the next context has already started running. In fact, the below code | |
722 | * is a bit suboptimal because the retiring can occur simply after the | |
723 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
724 | */ | |
112522f6 CW |
725 | if (from != NULL) { |
726 | from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; | |
e2d05a8b | 727 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring); |
e0556841 BW |
728 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
729 | * whole damn pipeline, we don't need to explicitly mark the | |
730 | * object dirty. The only exception is that the context must be | |
731 | * correct in case the object gets swapped out. Ideally we'd be | |
732 | * able to defer doing this until we know the object would be | |
733 | * swapped, but there is no way to do that yet. | |
734 | */ | |
112522f6 CW |
735 | from->obj->dirty = 1; |
736 | BUG_ON(from->obj->ring != ring); | |
737 | ||
c0321e2c | 738 | /* obj is kept alive until the next request by its active ref */ |
d7f46fc4 | 739 | i915_gem_object_ggtt_unpin(from->obj); |
112522f6 | 740 | i915_gem_context_unreference(from); |
e0556841 BW |
741 | } |
742 | ||
ad1d2199 BW |
743 | to->is_initialized = true; |
744 | ||
67e3d297 | 745 | done: |
112522f6 CW |
746 | i915_gem_context_reference(to); |
747 | ring->last_context = to; | |
0009e46c | 748 | to->last_ring = ring; |
e0556841 BW |
749 | |
750 | return 0; | |
7e0d96bc BW |
751 | |
752 | unpin_out: | |
753 | if (ring->id == RCS) | |
754 | i915_gem_object_ggtt_unpin(to->obj); | |
755 | return ret; | |
e0556841 BW |
756 | } |
757 | ||
758 | /** | |
759 | * i915_switch_context() - perform a GPU context switch. | |
760 | * @ring: ring for which we'll execute the context switch | |
761 | * @file_priv: file_priv associated with the context, may be NULL | |
96a6f0f1 | 762 | * @to: the context to switch to |
e0556841 BW |
763 | * |
764 | * The context life cycle is simple. The context refcount is incremented and | |
765 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
766 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
767 | * object while letting the normal object tracking destroy the backing BO. | |
768 | */ | |
769 | int i915_switch_context(struct intel_ring_buffer *ring, | |
770 | struct drm_file *file, | |
41bde553 | 771 | struct i915_hw_context *to) |
e0556841 BW |
772 | { |
773 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 774 | |
0eea67eb BW |
775 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
776 | ||
41bde553 | 777 | BUG_ON(file && to == NULL); |
e0556841 | 778 | |
a95f6a00 MK |
779 | /* We have the fake context */ |
780 | if (!HAS_HW_CONTEXTS(ring->dev)) { | |
781 | ring->last_context = to; | |
c482972a | 782 | return 0; |
a95f6a00 | 783 | } |
c482972a | 784 | |
67e3d297 | 785 | return do_switch(ring, to); |
e0556841 | 786 | } |
84624813 BW |
787 | |
788 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | |
789 | struct drm_file *file) | |
790 | { | |
84624813 BW |
791 | struct drm_i915_gem_context_create *args = data; |
792 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
793 | struct i915_hw_context *ctx; | |
794 | int ret; | |
795 | ||
8245be31 | 796 | if (!HAS_HW_CONTEXTS(dev)) |
5fa8be65 DV |
797 | return -ENODEV; |
798 | ||
84624813 BW |
799 | ret = i915_mutex_lock_interruptible(dev); |
800 | if (ret) | |
801 | return ret; | |
802 | ||
7e0d96bc | 803 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
84624813 | 804 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
805 | if (IS_ERR(ctx)) |
806 | return PTR_ERR(ctx); | |
84624813 BW |
807 | |
808 | args->ctx_id = ctx->id; | |
809 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); | |
810 | ||
be636387 | 811 | return 0; |
84624813 BW |
812 | } |
813 | ||
814 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
815 | struct drm_file *file) | |
816 | { | |
817 | struct drm_i915_gem_context_destroy *args = data; | |
818 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
84624813 BW |
819 | struct i915_hw_context *ctx; |
820 | int ret; | |
821 | ||
0eea67eb | 822 | if (args->ctx_id == DEFAULT_CONTEXT_ID) |
c2cf2416 | 823 | return -ENOENT; |
0eea67eb | 824 | |
84624813 BW |
825 | ret = i915_mutex_lock_interruptible(dev); |
826 | if (ret) | |
827 | return ret; | |
828 | ||
829 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
72ad5c45 | 830 | if (IS_ERR(ctx)) { |
84624813 | 831 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 832 | return PTR_ERR(ctx); |
84624813 BW |
833 | } |
834 | ||
dce3271b MK |
835 | idr_remove(&ctx->file_priv->context_idr, ctx->id); |
836 | i915_gem_context_unreference(ctx); | |
84624813 BW |
837 | mutex_unlock(&dev->struct_mutex); |
838 | ||
839 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
840 | return 0; | |
841 | } |