Commit | Line | Data |
---|---|---|
254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
40521054 BW |
93 | /* This is a HW constraint. The value below is the largest known requirement |
94 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
95 | * part. It should be safe to decrease this, but it's more future proof as is. | |
96 | */ | |
b731d33d BW |
97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
98 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 99 | |
b731d33d BW |
100 | static size_t get_context_alignment(struct drm_device *dev) |
101 | { | |
102 | if (IS_GEN6(dev)) | |
103 | return GEN6_CONTEXT_ALIGN; | |
104 | ||
105 | return GEN7_CONTEXT_ALIGN; | |
106 | } | |
107 | ||
254f965c BW |
108 | static int get_context_size(struct drm_device *dev) |
109 | { | |
110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
111 | int ret; | |
112 | u32 reg; | |
113 | ||
114 | switch (INTEL_INFO(dev)->gen) { | |
115 | case 6: | |
116 | reg = I915_READ(CXT_SIZE); | |
117 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
118 | break; | |
119 | case 7: | |
4f91dd6f | 120 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 121 | if (IS_HASWELL(dev)) |
a0de80a0 | 122 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
123 | else |
124 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 125 | break; |
8897644a BW |
126 | case 8: |
127 | ret = GEN8_CXT_TOTAL_SIZE; | |
128 | break; | |
254f965c BW |
129 | default: |
130 | BUG(); | |
131 | } | |
132 | ||
133 | return ret; | |
134 | } | |
135 | ||
e9f24d5f TU |
136 | static void i915_gem_context_clean(struct intel_context *ctx) |
137 | { | |
138 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; | |
139 | struct i915_vma *vma, *next; | |
140 | ||
61fb5881 | 141 | if (!ppgtt) |
e9f24d5f TU |
142 | return; |
143 | ||
144 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
145 | ||
146 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, | |
147 | mm_list) { | |
148 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) | |
149 | break; | |
150 | } | |
151 | } | |
152 | ||
dce3271b | 153 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 154 | { |
9ea4feec | 155 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
40521054 | 156 | |
198c974d DCS |
157 | trace_i915_context_free(ctx); |
158 | ||
ae6c4806 | 159 | if (i915.enable_execlists) |
ede7d42b | 160 | intel_lr_context_free(ctx); |
c7c48dfd | 161 | |
e9f24d5f TU |
162 | /* |
163 | * This context is going away and we need to remove all VMAs still | |
164 | * around. This is to handle imported shared objects for which | |
165 | * destructor did not run when their handles were closed. | |
166 | */ | |
167 | i915_gem_context_clean(ctx); | |
168 | ||
ae6c4806 DV |
169 | i915_ppgtt_put(ctx->ppgtt); |
170 | ||
2f295791 BW |
171 | if (ctx->legacy_hw_ctx.rcs_state) |
172 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); | |
c7c48dfd | 173 | list_del(&ctx->link); |
40521054 BW |
174 | kfree(ctx); |
175 | } | |
176 | ||
8c857917 | 177 | struct drm_i915_gem_object * |
aa0c13da OM |
178 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
179 | { | |
180 | struct drm_i915_gem_object *obj; | |
181 | int ret; | |
182 | ||
52613921 | 183 | obj = i915_gem_alloc_object(dev, size); |
aa0c13da OM |
184 | if (obj == NULL) |
185 | return ERR_PTR(-ENOMEM); | |
186 | ||
187 | /* | |
188 | * Try to make the context utilize L3 as well as LLC. | |
189 | * | |
190 | * On VLV we don't have L3 controls in the PTEs so we | |
191 | * shouldn't touch the cache level, especially as that | |
192 | * would make the object snooped which might have a | |
193 | * negative performance impact. | |
194 | */ | |
195 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { | |
196 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
197 | /* Failure shouldn't ever happen this early */ | |
198 | if (WARN_ON(ret)) { | |
199 | drm_gem_object_unreference(&obj->base); | |
200 | return ERR_PTR(ret); | |
201 | } | |
202 | } | |
203 | ||
204 | return obj; | |
205 | } | |
206 | ||
273497e5 | 207 | static struct intel_context * |
0eea67eb | 208 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 209 | struct drm_i915_file_private *file_priv) |
40521054 BW |
210 | { |
211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 212 | struct intel_context *ctx; |
c8c470af | 213 | int ret; |
40521054 | 214 | |
f94982b0 | 215 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
216 | if (ctx == NULL) |
217 | return ERR_PTR(-ENOMEM); | |
40521054 | 218 | |
dce3271b | 219 | kref_init(&ctx->ref); |
691e6415 | 220 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 221 | ctx->i915 = dev_priv; |
40521054 | 222 | |
691e6415 | 223 | if (dev_priv->hw_context_size) { |
aa0c13da OM |
224 | struct drm_i915_gem_object *obj = |
225 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); | |
226 | if (IS_ERR(obj)) { | |
227 | ret = PTR_ERR(obj); | |
4615d4c9 | 228 | goto err_out; |
691e6415 | 229 | } |
ea0c76f8 | 230 | ctx->legacy_hw_ctx.rcs_state = obj; |
691e6415 | 231 | } |
40521054 BW |
232 | |
233 | /* Default context will never have a file_priv */ | |
691e6415 CW |
234 | if (file_priv != NULL) { |
235 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 236 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
237 | if (ret < 0) |
238 | goto err_out; | |
239 | } else | |
821d66dd | 240 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
241 | |
242 | ctx->file_priv = file_priv; | |
821d66dd | 243 | ctx->user_handle = ret; |
3ccfd19d BW |
244 | /* NB: Mark all slices as needing a remap so that when the context first |
245 | * loads it will restore whatever remap state already exists. If there | |
246 | * is no remap info, it will be a NOP. */ | |
247 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 248 | |
676fa572 CW |
249 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
250 | ||
146937e5 | 251 | return ctx; |
40521054 BW |
252 | |
253 | err_out: | |
dce3271b | 254 | i915_gem_context_unreference(ctx); |
146937e5 | 255 | return ERR_PTR(ret); |
40521054 BW |
256 | } |
257 | ||
254f965c BW |
258 | /** |
259 | * The default context needs to exist per ring that uses contexts. It stores the | |
260 | * context state of the GPU for applications that don't utilize HW contexts, as | |
261 | * well as an idle case. | |
262 | */ | |
273497e5 | 263 | static struct intel_context * |
0eea67eb | 264 | i915_gem_create_context(struct drm_device *dev, |
d624d86e | 265 | struct drm_i915_file_private *file_priv) |
254f965c | 266 | { |
42c3b603 | 267 | const bool is_global_default_ctx = file_priv == NULL; |
273497e5 | 268 | struct intel_context *ctx; |
bdf4fd7e | 269 | int ret = 0; |
40521054 | 270 | |
b731d33d | 271 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 272 | |
0eea67eb | 273 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 274 | if (IS_ERR(ctx)) |
a45d0f6a | 275 | return ctx; |
40521054 | 276 | |
ea0c76f8 | 277 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
42c3b603 CW |
278 | /* We may need to do things with the shrinker which |
279 | * require us to immediately switch back to the default | |
280 | * context. This can cause a problem as pinning the | |
281 | * default context also requires GTT space which may not | |
282 | * be available. To avoid this we always pin the default | |
283 | * context. | |
284 | */ | |
ea0c76f8 | 285 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
1ec9e26d | 286 | get_context_alignment(dev), 0); |
42c3b603 CW |
287 | if (ret) { |
288 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
289 | goto err_destroy; | |
290 | } | |
291 | } | |
292 | ||
d624d86e | 293 | if (USES_FULL_PPGTT(dev)) { |
4d884705 | 294 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
bdf4fd7e BW |
295 | |
296 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
297 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
298 | PTR_ERR(ppgtt)); | |
bdf4fd7e | 299 | ret = PTR_ERR(ppgtt); |
42c3b603 | 300 | goto err_unpin; |
ae6c4806 DV |
301 | } |
302 | ||
303 | ctx->ppgtt = ppgtt; | |
304 | } | |
bdf4fd7e | 305 | |
198c974d DCS |
306 | trace_i915_context_create(ctx); |
307 | ||
a45d0f6a | 308 | return ctx; |
9a3b5304 | 309 | |
42c3b603 | 310 | err_unpin: |
ea0c76f8 OM |
311 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
312 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); | |
9a3b5304 | 313 | err_destroy: |
37876df6 | 314 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
dce3271b | 315 | i915_gem_context_unreference(ctx); |
a45d0f6a | 316 | return ERR_PTR(ret); |
254f965c BW |
317 | } |
318 | ||
acce9ffa BW |
319 | void i915_gem_context_reset(struct drm_device *dev) |
320 | { | |
321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
acce9ffa BW |
322 | int i; |
323 | ||
3e5b6f05 TD |
324 | if (i915.enable_execlists) { |
325 | struct intel_context *ctx; | |
326 | ||
327 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
328 | intel_lr_context_reset(dev, ctx); | |
329 | } | |
330 | ||
ecdb5fd8 | 331 | return; |
3e5b6f05 | 332 | } |
ecdb5fd8 | 333 | |
acce9ffa | 334 | for (i = 0; i < I915_NUM_RINGS; i++) { |
a4872ba6 | 335 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
ea0c76f8 | 336 | struct intel_context *lctx = ring->last_context; |
acce9ffa | 337 | |
6689c167 MA |
338 | if (lctx) { |
339 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) | |
340 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); | |
acce9ffa | 341 | |
6689c167 MA |
342 | i915_gem_context_unreference(lctx); |
343 | ring->last_context = NULL; | |
acce9ffa | 344 | } |
acce9ffa BW |
345 | } |
346 | } | |
347 | ||
8245be31 | 348 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
349 | { |
350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 351 | struct intel_context *ctx; |
a45d0f6a | 352 | int i; |
254f965c | 353 | |
2fa48d8d BW |
354 | /* Init should only be called once per module load. Eventually the |
355 | * restriction on the context_disabled check can be loosened. */ | |
356 | if (WARN_ON(dev_priv->ring[RCS].default_context)) | |
8245be31 | 357 | return 0; |
254f965c | 358 | |
a0bd6c31 ZL |
359 | if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) { |
360 | if (!i915.enable_execlists) { | |
361 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
362 | return -EINVAL; | |
363 | } | |
364 | } | |
365 | ||
ede7d42b OM |
366 | if (i915.enable_execlists) { |
367 | /* NB: intentionally left blank. We will allocate our own | |
368 | * backing objects as we need them, thank you very much */ | |
369 | dev_priv->hw_context_size = 0; | |
370 | } else if (HAS_HW_CONTEXTS(dev)) { | |
691e6415 CW |
371 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
372 | if (dev_priv->hw_context_size > (1<<20)) { | |
373 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
374 | dev_priv->hw_context_size); | |
375 | dev_priv->hw_context_size = 0; | |
376 | } | |
254f965c BW |
377 | } |
378 | ||
d624d86e | 379 | ctx = i915_gem_create_context(dev, NULL); |
691e6415 CW |
380 | if (IS_ERR(ctx)) { |
381 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
382 | PTR_ERR(ctx)); | |
383 | return PTR_ERR(ctx); | |
254f965c BW |
384 | } |
385 | ||
ede7d42b OM |
386 | for (i = 0; i < I915_NUM_RINGS; i++) { |
387 | struct intel_engine_cs *ring = &dev_priv->ring[i]; | |
388 | ||
389 | /* NB: RCS will hold a ref for all rings */ | |
390 | ring->default_context = ctx; | |
ede7d42b | 391 | } |
67e3d297 | 392 | |
ede7d42b OM |
393 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
394 | i915.enable_execlists ? "LR" : | |
395 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 396 | return 0; |
254f965c BW |
397 | } |
398 | ||
399 | void i915_gem_context_fini(struct drm_device *dev) | |
400 | { | |
401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 402 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 403 | int i; |
254f965c | 404 | |
ea0c76f8 | 405 | if (dctx->legacy_hw_ctx.rcs_state) { |
691e6415 CW |
406 | /* The only known way to stop the gpu from accessing the hw context is |
407 | * to reset it. Do this as the very last operation to avoid confusing | |
408 | * other code, leading to spurious errors. */ | |
409 | intel_gpu_reset(dev); | |
410 | ||
411 | /* When default context is created and switched to, base object refcount | |
412 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
413 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
414 | * to default context. So we need to unreference the base object once | |
415 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
416 | * can then free the base object correctly. */ | |
417 | WARN_ON(!dev_priv->ring[RCS].last_context); | |
418 | if (dev_priv->ring[RCS].last_context == dctx) { | |
419 | /* Fake switch to NULL context */ | |
ea0c76f8 OM |
420 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
421 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); | |
691e6415 CW |
422 | i915_gem_context_unreference(dctx); |
423 | dev_priv->ring[RCS].last_context = NULL; | |
424 | } | |
d3b448d9 | 425 | |
ea0c76f8 | 426 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
67e3d297 BW |
427 | } |
428 | ||
429 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
a4872ba6 | 430 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
67e3d297 BW |
431 | |
432 | if (ring->last_context) | |
433 | i915_gem_context_unreference(ring->last_context); | |
434 | ||
435 | ring->default_context = NULL; | |
0009e46c | 436 | ring->last_context = NULL; |
71b76d00 BW |
437 | } |
438 | ||
dce3271b | 439 | i915_gem_context_unreference(dctx); |
254f965c BW |
440 | } |
441 | ||
b3dd6b96 | 442 | int i915_gem_context_enable(struct drm_i915_gem_request *req) |
2fa48d8d | 443 | { |
b3dd6b96 | 444 | struct intel_engine_cs *ring = req->ring; |
90638cc1 | 445 | int ret; |
bdf4fd7e | 446 | |
e7778be1 | 447 | if (i915.enable_execlists) { |
90638cc1 JH |
448 | if (ring->init_context == NULL) |
449 | return 0; | |
ecdb5fd8 | 450 | |
8753181e | 451 | ret = ring->init_context(req); |
e7778be1 | 452 | } else |
ba01cc93 | 453 | ret = i915_switch_context(req); |
90638cc1 JH |
454 | |
455 | if (ret) { | |
456 | DRM_ERROR("ring init context: %d\n", ret); | |
457 | return ret; | |
458 | } | |
2fa48d8d BW |
459 | |
460 | return 0; | |
461 | } | |
462 | ||
40521054 BW |
463 | static int context_idr_cleanup(int id, void *p, void *data) |
464 | { | |
273497e5 | 465 | struct intel_context *ctx = p; |
40521054 | 466 | |
dce3271b | 467 | i915_gem_context_unreference(ctx); |
40521054 | 468 | return 0; |
254f965c BW |
469 | } |
470 | ||
e422b888 BW |
471 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
472 | { | |
473 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
f83d6518 | 474 | struct intel_context *ctx; |
e422b888 BW |
475 | |
476 | idr_init(&file_priv->context_idr); | |
477 | ||
0eea67eb | 478 | mutex_lock(&dev->struct_mutex); |
d624d86e | 479 | ctx = i915_gem_create_context(dev, file_priv); |
0eea67eb BW |
480 | mutex_unlock(&dev->struct_mutex); |
481 | ||
f83d6518 | 482 | if (IS_ERR(ctx)) { |
0eea67eb | 483 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 484 | return PTR_ERR(ctx); |
0eea67eb BW |
485 | } |
486 | ||
e422b888 BW |
487 | return 0; |
488 | } | |
489 | ||
254f965c BW |
490 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
491 | { | |
40521054 | 492 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 493 | |
73c273eb | 494 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 495 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
496 | } |
497 | ||
273497e5 | 498 | struct intel_context * |
40521054 BW |
499 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
500 | { | |
273497e5 | 501 | struct intel_context *ctx; |
72ad5c45 | 502 | |
273497e5 | 503 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
72ad5c45 BW |
504 | if (!ctx) |
505 | return ERR_PTR(-ENOENT); | |
506 | ||
507 | return ctx; | |
254f965c | 508 | } |
e0556841 BW |
509 | |
510 | static inline int | |
1d719cda | 511 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
e0556841 | 512 | { |
1d719cda | 513 | struct intel_engine_cs *ring = req->ring; |
e80f14b6 | 514 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
515 | const int num_rings = |
516 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
517 | i915_semaphore_is_enabled(ring->dev) ? | |
518 | hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : | |
519 | 0; | |
520 | int len, i, ret; | |
e0556841 | 521 | |
12b0286f BW |
522 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
523 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
524 | * explicitly, so we rely on the value at ring init, stored in | |
525 | * itlb_before_ctx_switch. | |
526 | */ | |
057f6a8a | 527 | if (IS_GEN6(ring->dev)) { |
a84c3ae1 | 528 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
529 | if (ret) |
530 | return ret; | |
531 | } | |
532 | ||
e80f14b6 | 533 | /* These flags are for resource streamer on HSW+ */ |
4c436d55 AJ |
534 | if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8) |
535 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); | |
536 | else if (INTEL_INFO(ring->dev)->gen < 8) | |
e80f14b6 BW |
537 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
538 | ||
2c550183 CW |
539 | |
540 | len = 4; | |
541 | if (INTEL_INFO(ring->dev)->gen >= 7) | |
542 | len += 2 + (num_rings ? 4*num_rings + 2 : 0); | |
543 | ||
5fb9de1a | 544 | ret = intel_ring_begin(req, len); |
e0556841 BW |
545 | if (ret) |
546 | return ret; | |
547 | ||
b3f797ac | 548 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
2c550183 | 549 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
e37ec39b | 550 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
2c550183 CW |
551 | if (num_rings) { |
552 | struct intel_engine_cs *signaller; | |
553 | ||
554 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); | |
555 | for_each_ring(signaller, to_i915(ring->dev), i) { | |
556 | if (signaller == ring) | |
557 | continue; | |
558 | ||
559 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); | |
560 | intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
561 | } | |
562 | } | |
563 | } | |
e37ec39b | 564 | |
e0556841 BW |
565 | intel_ring_emit(ring, MI_NOOP); |
566 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
1d719cda | 567 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | |
e80f14b6 | 568 | flags); |
2b7e8082 VS |
569 | /* |
570 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
571 | * WaMiSetContext_Hang:snb,ivb,vlv | |
572 | */ | |
e0556841 BW |
573 | intel_ring_emit(ring, MI_NOOP); |
574 | ||
2c550183 CW |
575 | if (INTEL_INFO(ring->dev)->gen >= 7) { |
576 | if (num_rings) { | |
577 | struct intel_engine_cs *signaller; | |
578 | ||
579 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); | |
580 | for_each_ring(signaller, to_i915(ring->dev), i) { | |
581 | if (signaller == ring) | |
582 | continue; | |
583 | ||
584 | intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); | |
585 | intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
586 | } | |
587 | } | |
e37ec39b | 588 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 589 | } |
e37ec39b | 590 | |
e0556841 BW |
591 | intel_ring_advance(ring); |
592 | ||
593 | return ret; | |
594 | } | |
595 | ||
317b4e90 BW |
596 | static inline bool should_skip_switch(struct intel_engine_cs *ring, |
597 | struct intel_context *from, | |
598 | struct intel_context *to) | |
599 | { | |
563222a7 BW |
600 | if (to->remap_slice) |
601 | return false; | |
602 | ||
9258811c DV |
603 | if (to->ppgtt && from == to && |
604 | !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) | |
605 | return true; | |
317b4e90 BW |
606 | |
607 | return false; | |
608 | } | |
609 | ||
610 | static bool | |
611 | needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to) | |
612 | { | |
613 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
614 | ||
615 | if (!to->ppgtt) | |
616 | return false; | |
617 | ||
618 | if (INTEL_INFO(ring->dev)->gen < 8) | |
619 | return true; | |
620 | ||
621 | if (ring != &dev_priv->ring[RCS]) | |
622 | return true; | |
623 | ||
624 | return false; | |
625 | } | |
626 | ||
627 | static bool | |
6702cf16 BW |
628 | needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to, |
629 | u32 hw_flags) | |
317b4e90 BW |
630 | { |
631 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
632 | ||
633 | if (!to->ppgtt) | |
634 | return false; | |
635 | ||
636 | if (!IS_GEN8(ring->dev)) | |
637 | return false; | |
638 | ||
639 | if (ring != &dev_priv->ring[RCS]) | |
640 | return false; | |
641 | ||
6702cf16 | 642 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
643 | return true; |
644 | ||
645 | return false; | |
646 | } | |
647 | ||
abd68d9e | 648 | static int do_switch(struct drm_i915_gem_request *req) |
e0556841 | 649 | { |
abd68d9e JH |
650 | struct intel_context *to = req->ctx; |
651 | struct intel_engine_cs *ring = req->ring; | |
6f65e29a | 652 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
273497e5 | 653 | struct intel_context *from = ring->last_context; |
e0556841 | 654 | u32 hw_flags = 0; |
967ab6b1 | 655 | bool uninitialized = false; |
3ccfd19d | 656 | int ret, i; |
e0556841 | 657 | |
67e3d297 | 658 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
ea0c76f8 OM |
659 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
660 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); | |
67e3d297 | 661 | } |
e0556841 | 662 | |
317b4e90 | 663 | if (should_skip_switch(ring, from, to)) |
9a3b5304 CW |
664 | return 0; |
665 | ||
7e0d96bc BW |
666 | /* Trying to pin first makes error handling easier. */ |
667 | if (ring == &dev_priv->ring[RCS]) { | |
ea0c76f8 | 668 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
1ec9e26d | 669 | get_context_alignment(ring->dev), 0); |
7e0d96bc BW |
670 | if (ret) |
671 | return ret; | |
67e3d297 BW |
672 | } |
673 | ||
acc240d4 DV |
674 | /* |
675 | * Pin can switch back to the default context if we end up calling into | |
676 | * evict_everything - as a last ditch gtt defrag effort that also | |
677 | * switches to the default context. Hence we need to reload from here. | |
678 | */ | |
679 | from = ring->last_context; | |
680 | ||
317b4e90 BW |
681 | if (needs_pd_load_pre(ring, to)) { |
682 | /* Older GENs and non render rings still want the load first, | |
683 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
684 | * Register Immediate commands in Ring Buffer before submitting | |
685 | * a context."*/ | |
198c974d | 686 | trace_switch_mm(ring, to); |
e85b26dc | 687 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
7e0d96bc BW |
688 | if (ret) |
689 | goto unpin_out; | |
563222a7 BW |
690 | |
691 | /* Doing a PD load always reloads the page dirs */ | |
9258811c | 692 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
7e0d96bc BW |
693 | } |
694 | ||
695 | if (ring != &dev_priv->ring[RCS]) { | |
696 | if (from) | |
697 | i915_gem_context_unreference(from); | |
698 | goto done; | |
699 | } | |
700 | ||
acc240d4 DV |
701 | /* |
702 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
703 | * that thanks to write = false in this call and us not setting any gpu |
704 | * write domains when putting a context object onto the active list | |
705 | * (when switching away from it), this won't block. | |
acc240d4 DV |
706 | * |
707 | * XXX: We need a real interface to do this instead of trickery. | |
708 | */ | |
ea0c76f8 | 709 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
7e0d96bc BW |
710 | if (ret) |
711 | goto unpin_out; | |
d3373a24 | 712 | |
6702cf16 | 713 | if (!to->legacy_hw_ctx.initialized) { |
e0556841 | 714 | hw_flags |= MI_RESTORE_INHIBIT; |
6702cf16 BW |
715 | /* NB: If we inhibit the restore, the context is not allowed to |
716 | * die because future work may end up depending on valid address | |
717 | * space. This means we must enforce that a page table load | |
718 | * occur when this occurs. */ | |
719 | } else if (to->ppgtt && | |
9258811c | 720 | (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) { |
563222a7 | 721 | hw_flags |= MI_FORCE_RESTORE; |
9258811c DV |
722 | to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); |
723 | } | |
e0556841 | 724 | |
6702cf16 BW |
725 | /* We should never emit switch_mm more than once */ |
726 | WARN_ON(needs_pd_load_pre(ring, to) && | |
9258811c | 727 | needs_pd_load_post(ring, to, hw_flags)); |
6702cf16 | 728 | |
1d719cda | 729 | ret = mi_set_context(req, hw_flags); |
7e0d96bc BW |
730 | if (ret) |
731 | goto unpin_out; | |
e0556841 | 732 | |
6702cf16 BW |
733 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
734 | * setup, and we do not wish to move them. | |
735 | */ | |
736 | if (needs_pd_load_post(ring, to, hw_flags)) { | |
317b4e90 | 737 | trace_switch_mm(ring, to); |
e85b26dc | 738 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
317b4e90 BW |
739 | /* The hardware context switch is emitted, but we haven't |
740 | * actually changed the state - so it's probably safe to bail | |
741 | * here. Still, let the user know something dangerous has | |
742 | * happened. | |
743 | */ | |
744 | if (ret) { | |
745 | DRM_ERROR("Failed to change address space on context switch\n"); | |
746 | goto unpin_out; | |
747 | } | |
748 | } | |
749 | ||
3ccfd19d BW |
750 | for (i = 0; i < MAX_L3_SLICES; i++) { |
751 | if (!(to->remap_slice & (1<<i))) | |
752 | continue; | |
753 | ||
6909a666 | 754 | ret = i915_gem_l3_remap(req, i); |
3ccfd19d BW |
755 | /* If it failed, try again next round */ |
756 | if (ret) | |
757 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
758 | else | |
759 | to->remap_slice &= ~(1<<i); | |
760 | } | |
761 | ||
e0556841 BW |
762 | /* The backing object for the context is done after switching to the |
763 | * *next* context. Therefore we cannot retire the previous context until | |
764 | * the next context has already started running. In fact, the below code | |
765 | * is a bit suboptimal because the retiring can occur simply after the | |
766 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
767 | */ | |
112522f6 | 768 | if (from != NULL) { |
ea0c76f8 | 769 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
b2af0376 | 770 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
e0556841 BW |
771 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
772 | * whole damn pipeline, we don't need to explicitly mark the | |
773 | * object dirty. The only exception is that the context must be | |
774 | * correct in case the object gets swapped out. Ideally we'd be | |
775 | * able to defer doing this until we know the object would be | |
776 | * swapped, but there is no way to do that yet. | |
777 | */ | |
ea0c76f8 | 778 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
112522f6 | 779 | |
c0321e2c | 780 | /* obj is kept alive until the next request by its active ref */ |
ea0c76f8 | 781 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
112522f6 | 782 | i915_gem_context_unreference(from); |
e0556841 BW |
783 | } |
784 | ||
6702cf16 | 785 | uninitialized = !to->legacy_hw_ctx.initialized; |
ea0c76f8 | 786 | to->legacy_hw_ctx.initialized = true; |
967ab6b1 | 787 | |
67e3d297 | 788 | done: |
112522f6 CW |
789 | i915_gem_context_reference(to); |
790 | ring->last_context = to; | |
e0556841 | 791 | |
967ab6b1 | 792 | if (uninitialized) { |
86d7f238 | 793 | if (ring->init_context) { |
8753181e | 794 | ret = ring->init_context(req); |
86d7f238 AS |
795 | if (ret) |
796 | DRM_ERROR("ring init context: %d\n", ret); | |
797 | } | |
46470fc9 MK |
798 | } |
799 | ||
e0556841 | 800 | return 0; |
7e0d96bc BW |
801 | |
802 | unpin_out: | |
803 | if (ring->id == RCS) | |
ea0c76f8 | 804 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
7e0d96bc | 805 | return ret; |
e0556841 BW |
806 | } |
807 | ||
808 | /** | |
809 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 810 | * @req: request for which we'll execute the context switch |
e0556841 BW |
811 | * |
812 | * The context life cycle is simple. The context refcount is incremented and | |
813 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 814 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 815 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
816 | * |
817 | * This function should not be used in execlists mode. Instead the context is | |
818 | * switched by writing to the ELSP and requests keep a reference to their | |
819 | * context. | |
e0556841 | 820 | */ |
ba01cc93 | 821 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 822 | { |
ba01cc93 | 823 | struct intel_engine_cs *ring = req->ring; |
e0556841 | 824 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e0556841 | 825 | |
ecdb5fd8 | 826 | WARN_ON(i915.enable_execlists); |
0eea67eb BW |
827 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
828 | ||
ba01cc93 JH |
829 | if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
830 | if (req->ctx != ring->last_context) { | |
831 | i915_gem_context_reference(req->ctx); | |
691e6415 CW |
832 | if (ring->last_context) |
833 | i915_gem_context_unreference(ring->last_context); | |
ba01cc93 | 834 | ring->last_context = req->ctx; |
691e6415 | 835 | } |
c482972a | 836 | return 0; |
a95f6a00 | 837 | } |
c482972a | 838 | |
abd68d9e | 839 | return do_switch(req); |
e0556841 | 840 | } |
84624813 | 841 | |
ec3e9963 | 842 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 843 | { |
ec3e9963 | 844 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
845 | } |
846 | ||
84624813 BW |
847 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
848 | struct drm_file *file) | |
849 | { | |
84624813 BW |
850 | struct drm_i915_gem_context_create *args = data; |
851 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 852 | struct intel_context *ctx; |
84624813 BW |
853 | int ret; |
854 | ||
ec3e9963 | 855 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
856 | return -ENODEV; |
857 | ||
84624813 BW |
858 | ret = i915_mutex_lock_interruptible(dev); |
859 | if (ret) | |
860 | return ret; | |
861 | ||
d624d86e | 862 | ctx = i915_gem_create_context(dev, file_priv); |
84624813 | 863 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
864 | if (IS_ERR(ctx)) |
865 | return PTR_ERR(ctx); | |
84624813 | 866 | |
821d66dd | 867 | args->ctx_id = ctx->user_handle; |
84624813 BW |
868 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
869 | ||
be636387 | 870 | return 0; |
84624813 BW |
871 | } |
872 | ||
873 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
874 | struct drm_file *file) | |
875 | { | |
876 | struct drm_i915_gem_context_destroy *args = data; | |
877 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 878 | struct intel_context *ctx; |
84624813 BW |
879 | int ret; |
880 | ||
821d66dd | 881 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 882 | return -ENOENT; |
0eea67eb | 883 | |
84624813 BW |
884 | ret = i915_mutex_lock_interruptible(dev); |
885 | if (ret) | |
886 | return ret; | |
887 | ||
888 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
72ad5c45 | 889 | if (IS_ERR(ctx)) { |
84624813 | 890 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 891 | return PTR_ERR(ctx); |
84624813 BW |
892 | } |
893 | ||
821d66dd | 894 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
dce3271b | 895 | i915_gem_context_unreference(ctx); |
84624813 BW |
896 | mutex_unlock(&dev->struct_mutex); |
897 | ||
898 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
899 | return 0; | |
900 | } | |
c9dc0f35 CW |
901 | |
902 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
903 | struct drm_file *file) | |
904 | { | |
905 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
906 | struct drm_i915_gem_context_param *args = data; | |
907 | struct intel_context *ctx; | |
908 | int ret; | |
909 | ||
910 | ret = i915_mutex_lock_interruptible(dev); | |
911 | if (ret) | |
912 | return ret; | |
913 | ||
914 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
915 | if (IS_ERR(ctx)) { | |
916 | mutex_unlock(&dev->struct_mutex); | |
917 | return PTR_ERR(ctx); | |
918 | } | |
919 | ||
920 | args->size = 0; | |
921 | switch (args->param) { | |
922 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
923 | args->value = ctx->hang_stats.ban_period_seconds; | |
924 | break; | |
b1b38278 DW |
925 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
926 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
927 | break; | |
c9dc0f35 CW |
928 | default: |
929 | ret = -EINVAL; | |
930 | break; | |
931 | } | |
932 | mutex_unlock(&dev->struct_mutex); | |
933 | ||
934 | return ret; | |
935 | } | |
936 | ||
937 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
938 | struct drm_file *file) | |
939 | { | |
940 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
941 | struct drm_i915_gem_context_param *args = data; | |
942 | struct intel_context *ctx; | |
943 | int ret; | |
944 | ||
945 | ret = i915_mutex_lock_interruptible(dev); | |
946 | if (ret) | |
947 | return ret; | |
948 | ||
949 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
950 | if (IS_ERR(ctx)) { | |
951 | mutex_unlock(&dev->struct_mutex); | |
952 | return PTR_ERR(ctx); | |
953 | } | |
954 | ||
955 | switch (args->param) { | |
956 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
957 | if (args->size) | |
958 | ret = -EINVAL; | |
959 | else if (args->value < ctx->hang_stats.ban_period_seconds && | |
960 | !capable(CAP_SYS_ADMIN)) | |
961 | ret = -EPERM; | |
962 | else | |
963 | ctx->hang_stats.ban_period_seconds = args->value; | |
964 | break; | |
b1b38278 DW |
965 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
966 | if (args->size) { | |
967 | ret = -EINVAL; | |
968 | } else { | |
969 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
970 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
971 | } | |
972 | break; | |
c9dc0f35 CW |
973 | default: |
974 | ret = -EINVAL; | |
975 | break; | |
976 | } | |
977 | mutex_unlock(&dev->struct_mutex); | |
978 | ||
979 | return ret; | |
980 | } |