Commit | Line | Data |
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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
40521054 BW |
93 | /* This is a HW constraint. The value below is the largest known requirement |
94 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
95 | * part. It should be safe to decrease this, but it's more future proof as is. | |
96 | */ | |
b731d33d BW |
97 | #define GEN6_CONTEXT_ALIGN (64<<10) |
98 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 99 | |
b731d33d BW |
100 | static size_t get_context_alignment(struct drm_device *dev) |
101 | { | |
102 | if (IS_GEN6(dev)) | |
103 | return GEN6_CONTEXT_ALIGN; | |
104 | ||
105 | return GEN7_CONTEXT_ALIGN; | |
106 | } | |
107 | ||
254f965c BW |
108 | static int get_context_size(struct drm_device *dev) |
109 | { | |
110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
111 | int ret; | |
112 | u32 reg; | |
113 | ||
114 | switch (INTEL_INFO(dev)->gen) { | |
115 | case 6: | |
116 | reg = I915_READ(CXT_SIZE); | |
117 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
118 | break; | |
119 | case 7: | |
4f91dd6f | 120 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 121 | if (IS_HASWELL(dev)) |
a0de80a0 | 122 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
123 | else |
124 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 125 | break; |
8897644a BW |
126 | case 8: |
127 | ret = GEN8_CXT_TOTAL_SIZE; | |
128 | break; | |
254f965c BW |
129 | default: |
130 | BUG(); | |
131 | } | |
132 | ||
133 | return ret; | |
134 | } | |
135 | ||
e9f24d5f TU |
136 | static void i915_gem_context_clean(struct intel_context *ctx) |
137 | { | |
138 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; | |
139 | struct i915_vma *vma, *next; | |
140 | ||
61fb5881 | 141 | if (!ppgtt) |
e9f24d5f TU |
142 | return; |
143 | ||
e9f24d5f | 144 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
1c7f4bca | 145 | vm_link) { |
e9f24d5f TU |
146 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
147 | break; | |
148 | } | |
149 | } | |
150 | ||
dce3271b | 151 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 152 | { |
9ea4feec | 153 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
40521054 | 154 | |
198c974d DCS |
155 | trace_i915_context_free(ctx); |
156 | ||
ae6c4806 | 157 | if (i915.enable_execlists) |
ede7d42b | 158 | intel_lr_context_free(ctx); |
c7c48dfd | 159 | |
e9f24d5f TU |
160 | /* |
161 | * This context is going away and we need to remove all VMAs still | |
162 | * around. This is to handle imported shared objects for which | |
163 | * destructor did not run when their handles were closed. | |
164 | */ | |
165 | i915_gem_context_clean(ctx); | |
166 | ||
ae6c4806 DV |
167 | i915_ppgtt_put(ctx->ppgtt); |
168 | ||
2f295791 BW |
169 | if (ctx->legacy_hw_ctx.rcs_state) |
170 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); | |
c7c48dfd | 171 | list_del(&ctx->link); |
40521054 BW |
172 | kfree(ctx); |
173 | } | |
174 | ||
8c857917 | 175 | struct drm_i915_gem_object * |
aa0c13da OM |
176 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
177 | { | |
178 | struct drm_i915_gem_object *obj; | |
179 | int ret; | |
180 | ||
52613921 | 181 | obj = i915_gem_alloc_object(dev, size); |
aa0c13da OM |
182 | if (obj == NULL) |
183 | return ERR_PTR(-ENOMEM); | |
184 | ||
185 | /* | |
186 | * Try to make the context utilize L3 as well as LLC. | |
187 | * | |
188 | * On VLV we don't have L3 controls in the PTEs so we | |
189 | * shouldn't touch the cache level, especially as that | |
190 | * would make the object snooped which might have a | |
191 | * negative performance impact. | |
4d3e904c WB |
192 | * |
193 | * Snooping is required on non-llc platforms in execlist | |
194 | * mode, but since all GGTT accesses use PAT entry 0 we | |
195 | * get snooping anyway regardless of cache_level. | |
196 | * | |
197 | * This is only applicable for Ivy Bridge devices since | |
198 | * later platforms don't have L3 control bits in the PTE. | |
aa0c13da | 199 | */ |
4d3e904c | 200 | if (IS_IVYBRIDGE(dev)) { |
aa0c13da OM |
201 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
202 | /* Failure shouldn't ever happen this early */ | |
203 | if (WARN_ON(ret)) { | |
204 | drm_gem_object_unreference(&obj->base); | |
205 | return ERR_PTR(ret); | |
206 | } | |
207 | } | |
208 | ||
209 | return obj; | |
210 | } | |
211 | ||
273497e5 | 212 | static struct intel_context * |
0eea67eb | 213 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 214 | struct drm_i915_file_private *file_priv) |
40521054 BW |
215 | { |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 217 | struct intel_context *ctx; |
c8c470af | 218 | int ret; |
40521054 | 219 | |
f94982b0 | 220 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
221 | if (ctx == NULL) |
222 | return ERR_PTR(-ENOMEM); | |
40521054 | 223 | |
dce3271b | 224 | kref_init(&ctx->ref); |
691e6415 | 225 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 226 | ctx->i915 = dev_priv; |
40521054 | 227 | |
691e6415 | 228 | if (dev_priv->hw_context_size) { |
aa0c13da OM |
229 | struct drm_i915_gem_object *obj = |
230 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); | |
231 | if (IS_ERR(obj)) { | |
232 | ret = PTR_ERR(obj); | |
4615d4c9 | 233 | goto err_out; |
691e6415 | 234 | } |
ea0c76f8 | 235 | ctx->legacy_hw_ctx.rcs_state = obj; |
691e6415 | 236 | } |
40521054 BW |
237 | |
238 | /* Default context will never have a file_priv */ | |
691e6415 CW |
239 | if (file_priv != NULL) { |
240 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 241 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
242 | if (ret < 0) |
243 | goto err_out; | |
244 | } else | |
821d66dd | 245 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
246 | |
247 | ctx->file_priv = file_priv; | |
821d66dd | 248 | ctx->user_handle = ret; |
3ccfd19d BW |
249 | /* NB: Mark all slices as needing a remap so that when the context first |
250 | * loads it will restore whatever remap state already exists. If there | |
251 | * is no remap info, it will be a NOP. */ | |
252 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 253 | |
676fa572 CW |
254 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
255 | ||
146937e5 | 256 | return ctx; |
40521054 BW |
257 | |
258 | err_out: | |
dce3271b | 259 | i915_gem_context_unreference(ctx); |
146937e5 | 260 | return ERR_PTR(ret); |
40521054 BW |
261 | } |
262 | ||
254f965c BW |
263 | /** |
264 | * The default context needs to exist per ring that uses contexts. It stores the | |
265 | * context state of the GPU for applications that don't utilize HW contexts, as | |
266 | * well as an idle case. | |
267 | */ | |
273497e5 | 268 | static struct intel_context * |
0eea67eb | 269 | i915_gem_create_context(struct drm_device *dev, |
d624d86e | 270 | struct drm_i915_file_private *file_priv) |
254f965c | 271 | { |
42c3b603 | 272 | const bool is_global_default_ctx = file_priv == NULL; |
273497e5 | 273 | struct intel_context *ctx; |
bdf4fd7e | 274 | int ret = 0; |
40521054 | 275 | |
b731d33d | 276 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 277 | |
0eea67eb | 278 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 279 | if (IS_ERR(ctx)) |
a45d0f6a | 280 | return ctx; |
40521054 | 281 | |
ea0c76f8 | 282 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
42c3b603 CW |
283 | /* We may need to do things with the shrinker which |
284 | * require us to immediately switch back to the default | |
285 | * context. This can cause a problem as pinning the | |
286 | * default context also requires GTT space which may not | |
287 | * be available. To avoid this we always pin the default | |
288 | * context. | |
289 | */ | |
ea0c76f8 | 290 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
1ec9e26d | 291 | get_context_alignment(dev), 0); |
42c3b603 CW |
292 | if (ret) { |
293 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
294 | goto err_destroy; | |
295 | } | |
296 | } | |
297 | ||
d624d86e | 298 | if (USES_FULL_PPGTT(dev)) { |
4d884705 | 299 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
bdf4fd7e BW |
300 | |
301 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
302 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
303 | PTR_ERR(ppgtt)); | |
bdf4fd7e | 304 | ret = PTR_ERR(ppgtt); |
42c3b603 | 305 | goto err_unpin; |
ae6c4806 DV |
306 | } |
307 | ||
308 | ctx->ppgtt = ppgtt; | |
309 | } | |
bdf4fd7e | 310 | |
198c974d DCS |
311 | trace_i915_context_create(ctx); |
312 | ||
a45d0f6a | 313 | return ctx; |
9a3b5304 | 314 | |
42c3b603 | 315 | err_unpin: |
ea0c76f8 OM |
316 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
317 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); | |
9a3b5304 | 318 | err_destroy: |
37876df6 | 319 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
dce3271b | 320 | i915_gem_context_unreference(ctx); |
a45d0f6a | 321 | return ERR_PTR(ret); |
254f965c BW |
322 | } |
323 | ||
a0b4a6a8 TU |
324 | static void i915_gem_context_unpin(struct intel_context *ctx, |
325 | struct intel_engine_cs *engine) | |
326 | { | |
f4e2dece TU |
327 | if (i915.enable_execlists) { |
328 | intel_lr_context_unpin(ctx, engine); | |
329 | } else { | |
330 | if (engine->id == RCS && ctx->legacy_hw_ctx.rcs_state) | |
331 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); | |
332 | i915_gem_context_unreference(ctx); | |
333 | } | |
a0b4a6a8 TU |
334 | } |
335 | ||
acce9ffa BW |
336 | void i915_gem_context_reset(struct drm_device *dev) |
337 | { | |
338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
acce9ffa BW |
339 | int i; |
340 | ||
3e5b6f05 TD |
341 | if (i915.enable_execlists) { |
342 | struct intel_context *ctx; | |
343 | ||
a0b4a6a8 | 344 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
3e5b6f05 | 345 | intel_lr_context_reset(dev, ctx); |
3e5b6f05 | 346 | } |
ecdb5fd8 | 347 | |
666796da | 348 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
4a570db5 | 349 | struct intel_engine_cs *engine = &dev_priv->engine[i]; |
acce9ffa | 350 | |
e2f80391 TU |
351 | if (engine->last_context) { |
352 | i915_gem_context_unpin(engine->last_context, engine); | |
353 | engine->last_context = NULL; | |
acce9ffa | 354 | } |
acce9ffa | 355 | } |
ed54c1a1 DG |
356 | |
357 | /* Force the GPU state to be reinitialised on enabling */ | |
358 | dev_priv->kernel_context->legacy_hw_ctx.initialized = false; | |
acce9ffa BW |
359 | } |
360 | ||
8245be31 | 361 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
362 | { |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 364 | struct intel_context *ctx; |
254f965c | 365 | |
2fa48d8d BW |
366 | /* Init should only be called once per module load. Eventually the |
367 | * restriction on the context_disabled check can be loosened. */ | |
ed54c1a1 | 368 | if (WARN_ON(dev_priv->kernel_context)) |
8245be31 | 369 | return 0; |
254f965c | 370 | |
a0bd6c31 ZL |
371 | if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) { |
372 | if (!i915.enable_execlists) { | |
373 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
374 | return -EINVAL; | |
375 | } | |
376 | } | |
377 | ||
ede7d42b OM |
378 | if (i915.enable_execlists) { |
379 | /* NB: intentionally left blank. We will allocate our own | |
380 | * backing objects as we need them, thank you very much */ | |
381 | dev_priv->hw_context_size = 0; | |
382 | } else if (HAS_HW_CONTEXTS(dev)) { | |
691e6415 CW |
383 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
384 | if (dev_priv->hw_context_size > (1<<20)) { | |
385 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
386 | dev_priv->hw_context_size); | |
387 | dev_priv->hw_context_size = 0; | |
388 | } | |
254f965c BW |
389 | } |
390 | ||
d624d86e | 391 | ctx = i915_gem_create_context(dev, NULL); |
691e6415 CW |
392 | if (IS_ERR(ctx)) { |
393 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
394 | PTR_ERR(ctx)); | |
395 | return PTR_ERR(ctx); | |
254f965c BW |
396 | } |
397 | ||
ed54c1a1 | 398 | dev_priv->kernel_context = ctx; |
67e3d297 | 399 | |
ede7d42b OM |
400 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
401 | i915.enable_execlists ? "LR" : | |
402 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 403 | return 0; |
254f965c BW |
404 | } |
405 | ||
406 | void i915_gem_context_fini(struct drm_device *dev) | |
407 | { | |
408 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed54c1a1 | 409 | struct intel_context *dctx = dev_priv->kernel_context; |
67e3d297 | 410 | int i; |
254f965c | 411 | |
ea0c76f8 | 412 | if (dctx->legacy_hw_ctx.rcs_state) { |
691e6415 CW |
413 | /* The only known way to stop the gpu from accessing the hw context is |
414 | * to reset it. Do this as the very last operation to avoid confusing | |
415 | * other code, leading to spurious errors. */ | |
ee4b6faf | 416 | intel_gpu_reset(dev, ALL_ENGINES); |
691e6415 CW |
417 | |
418 | /* When default context is created and switched to, base object refcount | |
419 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
420 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
421 | * to default context. So we need to unreference the base object once | |
422 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
423 | * can then free the base object correctly. */ | |
4a570db5 | 424 | WARN_ON(!dev_priv->engine[RCS].last_context); |
d3b448d9 | 425 | |
ea0c76f8 | 426 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
67e3d297 BW |
427 | } |
428 | ||
666796da | 429 | for (i = I915_NUM_ENGINES; --i >= 0;) { |
4a570db5 | 430 | struct intel_engine_cs *engine = &dev_priv->engine[i]; |
67e3d297 | 431 | |
e2f80391 TU |
432 | if (engine->last_context) { |
433 | i915_gem_context_unpin(engine->last_context, engine); | |
434 | engine->last_context = NULL; | |
ed54c1a1 | 435 | } |
71b76d00 BW |
436 | } |
437 | ||
dce3271b | 438 | i915_gem_context_unreference(dctx); |
ed54c1a1 | 439 | dev_priv->kernel_context = NULL; |
254f965c BW |
440 | } |
441 | ||
b3dd6b96 | 442 | int i915_gem_context_enable(struct drm_i915_gem_request *req) |
2fa48d8d | 443 | { |
4a570db5 | 444 | struct intel_engine_cs *engine = req->engine; |
90638cc1 | 445 | int ret; |
bdf4fd7e | 446 | |
e7778be1 | 447 | if (i915.enable_execlists) { |
e2f80391 | 448 | if (engine->init_context == NULL) |
90638cc1 | 449 | return 0; |
ecdb5fd8 | 450 | |
e2f80391 | 451 | ret = engine->init_context(req); |
e7778be1 | 452 | } else |
ba01cc93 | 453 | ret = i915_switch_context(req); |
90638cc1 JH |
454 | |
455 | if (ret) { | |
456 | DRM_ERROR("ring init context: %d\n", ret); | |
457 | return ret; | |
458 | } | |
2fa48d8d BW |
459 | |
460 | return 0; | |
461 | } | |
462 | ||
40521054 BW |
463 | static int context_idr_cleanup(int id, void *p, void *data) |
464 | { | |
273497e5 | 465 | struct intel_context *ctx = p; |
40521054 | 466 | |
dce3271b | 467 | i915_gem_context_unreference(ctx); |
40521054 | 468 | return 0; |
254f965c BW |
469 | } |
470 | ||
e422b888 BW |
471 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
472 | { | |
473 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
f83d6518 | 474 | struct intel_context *ctx; |
e422b888 BW |
475 | |
476 | idr_init(&file_priv->context_idr); | |
477 | ||
0eea67eb | 478 | mutex_lock(&dev->struct_mutex); |
d624d86e | 479 | ctx = i915_gem_create_context(dev, file_priv); |
0eea67eb BW |
480 | mutex_unlock(&dev->struct_mutex); |
481 | ||
f83d6518 | 482 | if (IS_ERR(ctx)) { |
0eea67eb | 483 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 484 | return PTR_ERR(ctx); |
0eea67eb BW |
485 | } |
486 | ||
e422b888 BW |
487 | return 0; |
488 | } | |
489 | ||
254f965c BW |
490 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
491 | { | |
40521054 | 492 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 493 | |
73c273eb | 494 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 495 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
496 | } |
497 | ||
273497e5 | 498 | struct intel_context * |
40521054 BW |
499 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
500 | { | |
273497e5 | 501 | struct intel_context *ctx; |
72ad5c45 | 502 | |
273497e5 | 503 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
72ad5c45 BW |
504 | if (!ctx) |
505 | return ERR_PTR(-ENOENT); | |
506 | ||
507 | return ctx; | |
254f965c | 508 | } |
e0556841 BW |
509 | |
510 | static inline int | |
1d719cda | 511 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
e0556841 | 512 | { |
4a570db5 | 513 | struct intel_engine_cs *engine = req->engine; |
e80f14b6 | 514 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
515 | const int num_rings = |
516 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
e2f80391 TU |
517 | i915_semaphore_is_enabled(engine->dev) ? |
518 | hweight32(INTEL_INFO(engine->dev)->ring_mask) - 1 : | |
2c550183 | 519 | 0; |
b4ac5afc | 520 | int len, ret; |
e0556841 | 521 | |
12b0286f BW |
522 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
523 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
524 | * explicitly, so we rely on the value at ring init, stored in | |
525 | * itlb_before_ctx_switch. | |
526 | */ | |
e2f80391 TU |
527 | if (IS_GEN6(engine->dev)) { |
528 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0); | |
12b0286f BW |
529 | if (ret) |
530 | return ret; | |
531 | } | |
532 | ||
e80f14b6 | 533 | /* These flags are for resource streamer on HSW+ */ |
e2f80391 | 534 | if (IS_HASWELL(engine->dev) || INTEL_INFO(engine->dev)->gen >= 8) |
4c436d55 | 535 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
e2f80391 | 536 | else if (INTEL_INFO(engine->dev)->gen < 8) |
e80f14b6 BW |
537 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
538 | ||
2c550183 CW |
539 | |
540 | len = 4; | |
e2f80391 | 541 | if (INTEL_INFO(engine->dev)->gen >= 7) |
2c550183 CW |
542 | len += 2 + (num_rings ? 4*num_rings + 2 : 0); |
543 | ||
5fb9de1a | 544 | ret = intel_ring_begin(req, len); |
e0556841 BW |
545 | if (ret) |
546 | return ret; | |
547 | ||
b3f797ac | 548 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
e2f80391 TU |
549 | if (INTEL_INFO(engine->dev)->gen >= 7) { |
550 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
2c550183 CW |
551 | if (num_rings) { |
552 | struct intel_engine_cs *signaller; | |
553 | ||
e2f80391 TU |
554 | intel_ring_emit(engine, |
555 | MI_LOAD_REGISTER_IMM(num_rings)); | |
b4ac5afc | 556 | for_each_engine(signaller, to_i915(engine->dev)) { |
e2f80391 | 557 | if (signaller == engine) |
2c550183 CW |
558 | continue; |
559 | ||
e2f80391 TU |
560 | intel_ring_emit_reg(engine, |
561 | RING_PSMI_CTL(signaller->mmio_base)); | |
562 | intel_ring_emit(engine, | |
563 | _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
2c550183 CW |
564 | } |
565 | } | |
566 | } | |
e37ec39b | 567 | |
e2f80391 TU |
568 | intel_ring_emit(engine, MI_NOOP); |
569 | intel_ring_emit(engine, MI_SET_CONTEXT); | |
570 | intel_ring_emit(engine, | |
571 | i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | | |
e80f14b6 | 572 | flags); |
2b7e8082 VS |
573 | /* |
574 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
575 | * WaMiSetContext_Hang:snb,ivb,vlv | |
576 | */ | |
e2f80391 | 577 | intel_ring_emit(engine, MI_NOOP); |
e0556841 | 578 | |
e2f80391 | 579 | if (INTEL_INFO(engine->dev)->gen >= 7) { |
2c550183 CW |
580 | if (num_rings) { |
581 | struct intel_engine_cs *signaller; | |
582 | ||
e2f80391 TU |
583 | intel_ring_emit(engine, |
584 | MI_LOAD_REGISTER_IMM(num_rings)); | |
b4ac5afc | 585 | for_each_engine(signaller, to_i915(engine->dev)) { |
e2f80391 | 586 | if (signaller == engine) |
2c550183 CW |
587 | continue; |
588 | ||
e2f80391 TU |
589 | intel_ring_emit_reg(engine, |
590 | RING_PSMI_CTL(signaller->mmio_base)); | |
591 | intel_ring_emit(engine, | |
592 | _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); | |
2c550183 CW |
593 | } |
594 | } | |
e2f80391 | 595 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 596 | } |
e37ec39b | 597 | |
e2f80391 | 598 | intel_ring_advance(engine); |
e0556841 BW |
599 | |
600 | return ret; | |
601 | } | |
602 | ||
0bc40be8 | 603 | static inline bool should_skip_switch(struct intel_engine_cs *engine, |
317b4e90 BW |
604 | struct intel_context *from, |
605 | struct intel_context *to) | |
606 | { | |
563222a7 BW |
607 | if (to->remap_slice) |
608 | return false; | |
609 | ||
9258811c | 610 | if (to->ppgtt && from == to && |
666796da | 611 | !(intel_engine_flag(engine) & to->ppgtt->pd_dirty_rings)) |
9258811c | 612 | return true; |
317b4e90 BW |
613 | |
614 | return false; | |
615 | } | |
616 | ||
617 | static bool | |
0bc40be8 | 618 | needs_pd_load_pre(struct intel_engine_cs *engine, struct intel_context *to) |
317b4e90 | 619 | { |
0bc40be8 | 620 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
317b4e90 BW |
621 | |
622 | if (!to->ppgtt) | |
623 | return false; | |
624 | ||
0bc40be8 | 625 | if (INTEL_INFO(engine->dev)->gen < 8) |
317b4e90 BW |
626 | return true; |
627 | ||
4a570db5 | 628 | if (engine != &dev_priv->engine[RCS]) |
317b4e90 BW |
629 | return true; |
630 | ||
631 | return false; | |
632 | } | |
633 | ||
634 | static bool | |
0bc40be8 TU |
635 | needs_pd_load_post(struct intel_engine_cs *engine, struct intel_context *to, |
636 | u32 hw_flags) | |
317b4e90 | 637 | { |
0bc40be8 | 638 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
317b4e90 BW |
639 | |
640 | if (!to->ppgtt) | |
641 | return false; | |
642 | ||
0bc40be8 | 643 | if (!IS_GEN8(engine->dev)) |
317b4e90 BW |
644 | return false; |
645 | ||
4a570db5 | 646 | if (engine != &dev_priv->engine[RCS]) |
317b4e90 BW |
647 | return false; |
648 | ||
6702cf16 | 649 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
650 | return true; |
651 | ||
652 | return false; | |
653 | } | |
654 | ||
abd68d9e | 655 | static int do_switch(struct drm_i915_gem_request *req) |
e0556841 | 656 | { |
abd68d9e | 657 | struct intel_context *to = req->ctx; |
4a570db5 | 658 | struct intel_engine_cs *engine = req->engine; |
39dabecd | 659 | struct drm_i915_private *dev_priv = req->i915; |
e2f80391 | 660 | struct intel_context *from = engine->last_context; |
e0556841 | 661 | u32 hw_flags = 0; |
967ab6b1 | 662 | bool uninitialized = false; |
3ccfd19d | 663 | int ret, i; |
e0556841 | 664 | |
4a570db5 | 665 | if (from != NULL && engine == &dev_priv->engine[RCS]) { |
ea0c76f8 OM |
666 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
667 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); | |
67e3d297 | 668 | } |
e0556841 | 669 | |
e2f80391 | 670 | if (should_skip_switch(engine, from, to)) |
9a3b5304 CW |
671 | return 0; |
672 | ||
7e0d96bc | 673 | /* Trying to pin first makes error handling easier. */ |
4a570db5 | 674 | if (engine == &dev_priv->engine[RCS]) { |
ea0c76f8 | 675 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
e2f80391 TU |
676 | get_context_alignment(engine->dev), |
677 | 0); | |
7e0d96bc BW |
678 | if (ret) |
679 | return ret; | |
67e3d297 BW |
680 | } |
681 | ||
acc240d4 DV |
682 | /* |
683 | * Pin can switch back to the default context if we end up calling into | |
684 | * evict_everything - as a last ditch gtt defrag effort that also | |
685 | * switches to the default context. Hence we need to reload from here. | |
686 | */ | |
e2f80391 | 687 | from = engine->last_context; |
acc240d4 | 688 | |
e2f80391 | 689 | if (needs_pd_load_pre(engine, to)) { |
317b4e90 BW |
690 | /* Older GENs and non render rings still want the load first, |
691 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
692 | * Register Immediate commands in Ring Buffer before submitting | |
693 | * a context."*/ | |
e2f80391 | 694 | trace_switch_mm(engine, to); |
e85b26dc | 695 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
7e0d96bc BW |
696 | if (ret) |
697 | goto unpin_out; | |
563222a7 BW |
698 | |
699 | /* Doing a PD load always reloads the page dirs */ | |
666796da | 700 | to->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
7e0d96bc BW |
701 | } |
702 | ||
4a570db5 | 703 | if (engine != &dev_priv->engine[RCS]) { |
7e0d96bc BW |
704 | if (from) |
705 | i915_gem_context_unreference(from); | |
706 | goto done; | |
707 | } | |
708 | ||
acc240d4 DV |
709 | /* |
710 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
711 | * that thanks to write = false in this call and us not setting any gpu |
712 | * write domains when putting a context object onto the active list | |
713 | * (when switching away from it), this won't block. | |
acc240d4 DV |
714 | * |
715 | * XXX: We need a real interface to do this instead of trickery. | |
716 | */ | |
ea0c76f8 | 717 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
7e0d96bc BW |
718 | if (ret) |
719 | goto unpin_out; | |
d3373a24 | 720 | |
42f1cae8 | 721 | if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) { |
e0556841 | 722 | hw_flags |= MI_RESTORE_INHIBIT; |
6702cf16 BW |
723 | /* NB: If we inhibit the restore, the context is not allowed to |
724 | * die because future work may end up depending on valid address | |
725 | * space. This means we must enforce that a page table load | |
726 | * occur when this occurs. */ | |
727 | } else if (to->ppgtt && | |
666796da | 728 | (intel_engine_flag(engine) & to->ppgtt->pd_dirty_rings)) { |
563222a7 | 729 | hw_flags |= MI_FORCE_RESTORE; |
666796da | 730 | to->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
9258811c | 731 | } |
e0556841 | 732 | |
6702cf16 | 733 | /* We should never emit switch_mm more than once */ |
e2f80391 TU |
734 | WARN_ON(needs_pd_load_pre(engine, to) && |
735 | needs_pd_load_post(engine, to, hw_flags)); | |
6702cf16 | 736 | |
1d719cda | 737 | ret = mi_set_context(req, hw_flags); |
7e0d96bc BW |
738 | if (ret) |
739 | goto unpin_out; | |
e0556841 | 740 | |
6702cf16 BW |
741 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
742 | * setup, and we do not wish to move them. | |
743 | */ | |
e2f80391 TU |
744 | if (needs_pd_load_post(engine, to, hw_flags)) { |
745 | trace_switch_mm(engine, to); | |
e85b26dc | 746 | ret = to->ppgtt->switch_mm(to->ppgtt, req); |
317b4e90 BW |
747 | /* The hardware context switch is emitted, but we haven't |
748 | * actually changed the state - so it's probably safe to bail | |
749 | * here. Still, let the user know something dangerous has | |
750 | * happened. | |
751 | */ | |
752 | if (ret) { | |
753 | DRM_ERROR("Failed to change address space on context switch\n"); | |
754 | goto unpin_out; | |
755 | } | |
756 | } | |
757 | ||
3ccfd19d BW |
758 | for (i = 0; i < MAX_L3_SLICES; i++) { |
759 | if (!(to->remap_slice & (1<<i))) | |
760 | continue; | |
761 | ||
6909a666 | 762 | ret = i915_gem_l3_remap(req, i); |
3ccfd19d BW |
763 | /* If it failed, try again next round */ |
764 | if (ret) | |
765 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
766 | else | |
767 | to->remap_slice &= ~(1<<i); | |
768 | } | |
769 | ||
e0556841 BW |
770 | /* The backing object for the context is done after switching to the |
771 | * *next* context. Therefore we cannot retire the previous context until | |
772 | * the next context has already started running. In fact, the below code | |
773 | * is a bit suboptimal because the retiring can occur simply after the | |
774 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
775 | */ | |
112522f6 | 776 | if (from != NULL) { |
ea0c76f8 | 777 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
b2af0376 | 778 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
e0556841 BW |
779 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
780 | * whole damn pipeline, we don't need to explicitly mark the | |
781 | * object dirty. The only exception is that the context must be | |
782 | * correct in case the object gets swapped out. Ideally we'd be | |
783 | * able to defer doing this until we know the object would be | |
784 | * swapped, but there is no way to do that yet. | |
785 | */ | |
ea0c76f8 | 786 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
112522f6 | 787 | |
c0321e2c | 788 | /* obj is kept alive until the next request by its active ref */ |
ea0c76f8 | 789 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
112522f6 | 790 | i915_gem_context_unreference(from); |
e0556841 BW |
791 | } |
792 | ||
6702cf16 | 793 | uninitialized = !to->legacy_hw_ctx.initialized; |
ea0c76f8 | 794 | to->legacy_hw_ctx.initialized = true; |
967ab6b1 | 795 | |
67e3d297 | 796 | done: |
112522f6 | 797 | i915_gem_context_reference(to); |
e2f80391 | 798 | engine->last_context = to; |
e0556841 | 799 | |
967ab6b1 | 800 | if (uninitialized) { |
e2f80391 TU |
801 | if (engine->init_context) { |
802 | ret = engine->init_context(req); | |
86d7f238 AS |
803 | if (ret) |
804 | DRM_ERROR("ring init context: %d\n", ret); | |
805 | } | |
46470fc9 MK |
806 | } |
807 | ||
e0556841 | 808 | return 0; |
7e0d96bc BW |
809 | |
810 | unpin_out: | |
e2f80391 | 811 | if (engine->id == RCS) |
ea0c76f8 | 812 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
7e0d96bc | 813 | return ret; |
e0556841 BW |
814 | } |
815 | ||
816 | /** | |
817 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 818 | * @req: request for which we'll execute the context switch |
e0556841 BW |
819 | * |
820 | * The context life cycle is simple. The context refcount is incremented and | |
821 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 822 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 823 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
824 | * |
825 | * This function should not be used in execlists mode. Instead the context is | |
826 | * switched by writing to the ELSP and requests keep a reference to their | |
827 | * context. | |
e0556841 | 828 | */ |
ba01cc93 | 829 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 830 | { |
4a570db5 | 831 | struct intel_engine_cs *engine = req->engine; |
39dabecd | 832 | struct drm_i915_private *dev_priv = req->i915; |
e0556841 | 833 | |
ecdb5fd8 | 834 | WARN_ON(i915.enable_execlists); |
0eea67eb BW |
835 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
836 | ||
ba01cc93 | 837 | if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
e2f80391 | 838 | if (req->ctx != engine->last_context) { |
ba01cc93 | 839 | i915_gem_context_reference(req->ctx); |
e2f80391 TU |
840 | if (engine->last_context) |
841 | i915_gem_context_unreference(engine->last_context); | |
842 | engine->last_context = req->ctx; | |
691e6415 | 843 | } |
c482972a | 844 | return 0; |
a95f6a00 | 845 | } |
c482972a | 846 | |
abd68d9e | 847 | return do_switch(req); |
e0556841 | 848 | } |
84624813 | 849 | |
ec3e9963 | 850 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 851 | { |
ec3e9963 | 852 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
853 | } |
854 | ||
84624813 BW |
855 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
856 | struct drm_file *file) | |
857 | { | |
84624813 BW |
858 | struct drm_i915_gem_context_create *args = data; |
859 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 860 | struct intel_context *ctx; |
84624813 BW |
861 | int ret; |
862 | ||
ec3e9963 | 863 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
864 | return -ENODEV; |
865 | ||
b31e5136 CW |
866 | if (args->pad != 0) |
867 | return -EINVAL; | |
868 | ||
84624813 BW |
869 | ret = i915_mutex_lock_interruptible(dev); |
870 | if (ret) | |
871 | return ret; | |
872 | ||
d624d86e | 873 | ctx = i915_gem_create_context(dev, file_priv); |
84624813 | 874 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
875 | if (IS_ERR(ctx)) |
876 | return PTR_ERR(ctx); | |
84624813 | 877 | |
821d66dd | 878 | args->ctx_id = ctx->user_handle; |
84624813 BW |
879 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
880 | ||
be636387 | 881 | return 0; |
84624813 BW |
882 | } |
883 | ||
884 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
885 | struct drm_file *file) | |
886 | { | |
887 | struct drm_i915_gem_context_destroy *args = data; | |
888 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 889 | struct intel_context *ctx; |
84624813 BW |
890 | int ret; |
891 | ||
b31e5136 CW |
892 | if (args->pad != 0) |
893 | return -EINVAL; | |
894 | ||
821d66dd | 895 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 896 | return -ENOENT; |
0eea67eb | 897 | |
84624813 BW |
898 | ret = i915_mutex_lock_interruptible(dev); |
899 | if (ret) | |
900 | return ret; | |
901 | ||
902 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
72ad5c45 | 903 | if (IS_ERR(ctx)) { |
84624813 | 904 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 905 | return PTR_ERR(ctx); |
84624813 BW |
906 | } |
907 | ||
821d66dd | 908 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
dce3271b | 909 | i915_gem_context_unreference(ctx); |
84624813 BW |
910 | mutex_unlock(&dev->struct_mutex); |
911 | ||
912 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
913 | return 0; | |
914 | } | |
c9dc0f35 CW |
915 | |
916 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
917 | struct drm_file *file) | |
918 | { | |
919 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
920 | struct drm_i915_gem_context_param *args = data; | |
921 | struct intel_context *ctx; | |
922 | int ret; | |
923 | ||
924 | ret = i915_mutex_lock_interruptible(dev); | |
925 | if (ret) | |
926 | return ret; | |
927 | ||
928 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
929 | if (IS_ERR(ctx)) { | |
930 | mutex_unlock(&dev->struct_mutex); | |
931 | return PTR_ERR(ctx); | |
932 | } | |
933 | ||
934 | args->size = 0; | |
935 | switch (args->param) { | |
936 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
937 | args->value = ctx->hang_stats.ban_period_seconds; | |
938 | break; | |
b1b38278 DW |
939 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
940 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
941 | break; | |
fa8848f2 CW |
942 | case I915_CONTEXT_PARAM_GTT_SIZE: |
943 | if (ctx->ppgtt) | |
944 | args->value = ctx->ppgtt->base.total; | |
945 | else if (to_i915(dev)->mm.aliasing_ppgtt) | |
946 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; | |
947 | else | |
62106b4f | 948 | args->value = to_i915(dev)->ggtt.base.total; |
fa8848f2 | 949 | break; |
c9dc0f35 CW |
950 | default: |
951 | ret = -EINVAL; | |
952 | break; | |
953 | } | |
954 | mutex_unlock(&dev->struct_mutex); | |
955 | ||
956 | return ret; | |
957 | } | |
958 | ||
959 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
960 | struct drm_file *file) | |
961 | { | |
962 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
963 | struct drm_i915_gem_context_param *args = data; | |
964 | struct intel_context *ctx; | |
965 | int ret; | |
966 | ||
967 | ret = i915_mutex_lock_interruptible(dev); | |
968 | if (ret) | |
969 | return ret; | |
970 | ||
971 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
972 | if (IS_ERR(ctx)) { | |
973 | mutex_unlock(&dev->struct_mutex); | |
974 | return PTR_ERR(ctx); | |
975 | } | |
976 | ||
977 | switch (args->param) { | |
978 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
979 | if (args->size) | |
980 | ret = -EINVAL; | |
981 | else if (args->value < ctx->hang_stats.ban_period_seconds && | |
982 | !capable(CAP_SYS_ADMIN)) | |
983 | ret = -EPERM; | |
984 | else | |
985 | ctx->hang_stats.ban_period_seconds = args->value; | |
986 | break; | |
b1b38278 DW |
987 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
988 | if (args->size) { | |
989 | ret = -EINVAL; | |
990 | } else { | |
991 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
992 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
993 | } | |
994 | break; | |
c9dc0f35 CW |
995 | default: |
996 | ret = -EINVAL; | |
997 | break; | |
998 | } | |
999 | mutex_unlock(&dev->struct_mutex); | |
1000 | ||
1001 | return ret; | |
1002 | } |