Commit | Line | Data |
---|---|---|
254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c BW |
90 | #include "i915_drv.h" |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
b731d33d BW |
96 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 98 | |
b731d33d BW |
99 | static size_t get_context_alignment(struct drm_device *dev) |
100 | { | |
101 | if (IS_GEN6(dev)) | |
102 | return GEN6_CONTEXT_ALIGN; | |
103 | ||
104 | return GEN7_CONTEXT_ALIGN; | |
105 | } | |
106 | ||
254f965c BW |
107 | static int get_context_size(struct drm_device *dev) |
108 | { | |
109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
110 | int ret; | |
111 | u32 reg; | |
112 | ||
113 | switch (INTEL_INFO(dev)->gen) { | |
114 | case 6: | |
115 | reg = I915_READ(CXT_SIZE); | |
116 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
117 | break; | |
118 | case 7: | |
4f91dd6f | 119 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 120 | if (IS_HASWELL(dev)) |
a0de80a0 | 121 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
122 | else |
123 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 124 | break; |
8897644a BW |
125 | case 8: |
126 | ret = GEN8_CXT_TOTAL_SIZE; | |
127 | break; | |
254f965c BW |
128 | default: |
129 | BUG(); | |
130 | } | |
131 | ||
132 | return ret; | |
133 | } | |
134 | ||
dce3271b | 135 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 136 | { |
273497e5 | 137 | struct intel_context *ctx = container_of(ctx_ref, |
ae6c4806 | 138 | typeof(*ctx), ref); |
40521054 | 139 | |
ae6c4806 | 140 | if (i915.enable_execlists) |
ede7d42b | 141 | intel_lr_context_free(ctx); |
c7c48dfd | 142 | |
ae6c4806 DV |
143 | i915_ppgtt_put(ctx->ppgtt); |
144 | ||
2f295791 BW |
145 | if (ctx->legacy_hw_ctx.rcs_state) |
146 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); | |
c7c48dfd | 147 | list_del(&ctx->link); |
40521054 BW |
148 | kfree(ctx); |
149 | } | |
150 | ||
8c857917 | 151 | struct drm_i915_gem_object * |
aa0c13da OM |
152 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
153 | { | |
154 | struct drm_i915_gem_object *obj; | |
155 | int ret; | |
156 | ||
157 | obj = i915_gem_alloc_object(dev, size); | |
158 | if (obj == NULL) | |
159 | return ERR_PTR(-ENOMEM); | |
160 | ||
161 | /* | |
162 | * Try to make the context utilize L3 as well as LLC. | |
163 | * | |
164 | * On VLV we don't have L3 controls in the PTEs so we | |
165 | * shouldn't touch the cache level, especially as that | |
166 | * would make the object snooped which might have a | |
167 | * negative performance impact. | |
168 | */ | |
169 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { | |
170 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
171 | /* Failure shouldn't ever happen this early */ | |
172 | if (WARN_ON(ret)) { | |
173 | drm_gem_object_unreference(&obj->base); | |
174 | return ERR_PTR(ret); | |
175 | } | |
176 | } | |
177 | ||
178 | return obj; | |
179 | } | |
180 | ||
273497e5 | 181 | static struct intel_context * |
0eea67eb | 182 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 183 | struct drm_i915_file_private *file_priv) |
40521054 BW |
184 | { |
185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 186 | struct intel_context *ctx; |
c8c470af | 187 | int ret; |
40521054 | 188 | |
f94982b0 | 189 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
190 | if (ctx == NULL) |
191 | return ERR_PTR(-ENOMEM); | |
40521054 | 192 | |
dce3271b | 193 | kref_init(&ctx->ref); |
691e6415 | 194 | list_add_tail(&ctx->link, &dev_priv->context_list); |
40521054 | 195 | |
691e6415 | 196 | if (dev_priv->hw_context_size) { |
aa0c13da OM |
197 | struct drm_i915_gem_object *obj = |
198 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); | |
199 | if (IS_ERR(obj)) { | |
200 | ret = PTR_ERR(obj); | |
4615d4c9 | 201 | goto err_out; |
691e6415 | 202 | } |
ea0c76f8 | 203 | ctx->legacy_hw_ctx.rcs_state = obj; |
691e6415 | 204 | } |
40521054 BW |
205 | |
206 | /* Default context will never have a file_priv */ | |
691e6415 CW |
207 | if (file_priv != NULL) { |
208 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 209 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
210 | if (ret < 0) |
211 | goto err_out; | |
212 | } else | |
821d66dd | 213 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
214 | |
215 | ctx->file_priv = file_priv; | |
821d66dd | 216 | ctx->user_handle = ret; |
3ccfd19d BW |
217 | /* NB: Mark all slices as needing a remap so that when the context first |
218 | * loads it will restore whatever remap state already exists. If there | |
219 | * is no remap info, it will be a NOP. */ | |
220 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 221 | |
146937e5 | 222 | return ctx; |
40521054 BW |
223 | |
224 | err_out: | |
dce3271b | 225 | i915_gem_context_unreference(ctx); |
146937e5 | 226 | return ERR_PTR(ret); |
40521054 BW |
227 | } |
228 | ||
254f965c BW |
229 | /** |
230 | * The default context needs to exist per ring that uses contexts. It stores the | |
231 | * context state of the GPU for applications that don't utilize HW contexts, as | |
232 | * well as an idle case. | |
233 | */ | |
273497e5 | 234 | static struct intel_context * |
0eea67eb BW |
235 | i915_gem_create_context(struct drm_device *dev, |
236 | struct drm_i915_file_private *file_priv, | |
237 | bool create_vm) | |
254f965c | 238 | { |
42c3b603 | 239 | const bool is_global_default_ctx = file_priv == NULL; |
273497e5 | 240 | struct intel_context *ctx; |
bdf4fd7e | 241 | int ret = 0; |
40521054 | 242 | |
b731d33d | 243 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 244 | |
0eea67eb | 245 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 246 | if (IS_ERR(ctx)) |
a45d0f6a | 247 | return ctx; |
40521054 | 248 | |
ea0c76f8 | 249 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
42c3b603 CW |
250 | /* We may need to do things with the shrinker which |
251 | * require us to immediately switch back to the default | |
252 | * context. This can cause a problem as pinning the | |
253 | * default context also requires GTT space which may not | |
254 | * be available. To avoid this we always pin the default | |
255 | * context. | |
256 | */ | |
ea0c76f8 | 257 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
1ec9e26d | 258 | get_context_alignment(dev), 0); |
42c3b603 CW |
259 | if (ret) { |
260 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
261 | goto err_destroy; | |
262 | } | |
263 | } | |
264 | ||
bdf4fd7e | 265 | if (create_vm) { |
4d884705 | 266 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
bdf4fd7e BW |
267 | |
268 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
269 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
270 | PTR_ERR(ppgtt)); | |
bdf4fd7e | 271 | ret = PTR_ERR(ppgtt); |
42c3b603 | 272 | goto err_unpin; |
ae6c4806 DV |
273 | } |
274 | ||
275 | ctx->ppgtt = ppgtt; | |
276 | } | |
bdf4fd7e | 277 | |
a45d0f6a | 278 | return ctx; |
9a3b5304 | 279 | |
42c3b603 | 280 | err_unpin: |
ea0c76f8 OM |
281 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
282 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); | |
9a3b5304 | 283 | err_destroy: |
dce3271b | 284 | i915_gem_context_unreference(ctx); |
a45d0f6a | 285 | return ERR_PTR(ret); |
254f965c BW |
286 | } |
287 | ||
acce9ffa BW |
288 | void i915_gem_context_reset(struct drm_device *dev) |
289 | { | |
290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
acce9ffa BW |
291 | int i; |
292 | ||
acce9ffa BW |
293 | /* Prevent the hardware from restoring the last context (which hung) on |
294 | * the next switch */ | |
295 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
a4872ba6 | 296 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
273497e5 | 297 | struct intel_context *dctx = ring->default_context; |
ea0c76f8 | 298 | struct intel_context *lctx = ring->last_context; |
acce9ffa BW |
299 | |
300 | /* Do a fake switch to the default context */ | |
ea0c76f8 | 301 | if (lctx == dctx) |
acce9ffa BW |
302 | continue; |
303 | ||
ea0c76f8 | 304 | if (!lctx) |
acce9ffa BW |
305 | continue; |
306 | ||
ea0c76f8 OM |
307 | if (dctx->legacy_hw_ctx.rcs_state && i == RCS) { |
308 | WARN_ON(i915_gem_obj_ggtt_pin(dctx->legacy_hw_ctx.rcs_state, | |
1ec9e26d | 309 | get_context_alignment(dev), 0)); |
acce9ffa | 310 | /* Fake a finish/inactive */ |
ea0c76f8 OM |
311 | dctx->legacy_hw_ctx.rcs_state->base.write_domain = 0; |
312 | dctx->legacy_hw_ctx.rcs_state->active = 0; | |
acce9ffa BW |
313 | } |
314 | ||
ea0c76f8 OM |
315 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) |
316 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); | |
4bfad3dd | 317 | |
ea0c76f8 | 318 | i915_gem_context_unreference(lctx); |
acce9ffa BW |
319 | i915_gem_context_reference(dctx); |
320 | ring->last_context = dctx; | |
321 | } | |
322 | } | |
323 | ||
8245be31 | 324 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
325 | { |
326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 327 | struct intel_context *ctx; |
a45d0f6a | 328 | int i; |
254f965c | 329 | |
2fa48d8d BW |
330 | /* Init should only be called once per module load. Eventually the |
331 | * restriction on the context_disabled check can be loosened. */ | |
332 | if (WARN_ON(dev_priv->ring[RCS].default_context)) | |
8245be31 | 333 | return 0; |
254f965c | 334 | |
ede7d42b OM |
335 | if (i915.enable_execlists) { |
336 | /* NB: intentionally left blank. We will allocate our own | |
337 | * backing objects as we need them, thank you very much */ | |
338 | dev_priv->hw_context_size = 0; | |
339 | } else if (HAS_HW_CONTEXTS(dev)) { | |
691e6415 CW |
340 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); |
341 | if (dev_priv->hw_context_size > (1<<20)) { | |
342 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
343 | dev_priv->hw_context_size); | |
344 | dev_priv->hw_context_size = 0; | |
345 | } | |
254f965c BW |
346 | } |
347 | ||
fa76da34 | 348 | ctx = i915_gem_create_context(dev, NULL, USES_FULL_PPGTT(dev)); |
691e6415 CW |
349 | if (IS_ERR(ctx)) { |
350 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
351 | PTR_ERR(ctx)); | |
352 | return PTR_ERR(ctx); | |
254f965c BW |
353 | } |
354 | ||
ede7d42b OM |
355 | for (i = 0; i < I915_NUM_RINGS; i++) { |
356 | struct intel_engine_cs *ring = &dev_priv->ring[i]; | |
357 | ||
358 | /* NB: RCS will hold a ref for all rings */ | |
359 | ring->default_context = ctx; | |
ede7d42b | 360 | } |
67e3d297 | 361 | |
ede7d42b OM |
362 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
363 | i915.enable_execlists ? "LR" : | |
364 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 365 | return 0; |
254f965c BW |
366 | } |
367 | ||
368 | void i915_gem_context_fini(struct drm_device *dev) | |
369 | { | |
370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 371 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 372 | int i; |
254f965c | 373 | |
ea0c76f8 | 374 | if (dctx->legacy_hw_ctx.rcs_state) { |
691e6415 CW |
375 | /* The only known way to stop the gpu from accessing the hw context is |
376 | * to reset it. Do this as the very last operation to avoid confusing | |
377 | * other code, leading to spurious errors. */ | |
378 | intel_gpu_reset(dev); | |
379 | ||
380 | /* When default context is created and switched to, base object refcount | |
381 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
382 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
383 | * to default context. So we need to unreference the base object once | |
384 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
385 | * can then free the base object correctly. */ | |
386 | WARN_ON(!dev_priv->ring[RCS].last_context); | |
387 | if (dev_priv->ring[RCS].last_context == dctx) { | |
388 | /* Fake switch to NULL context */ | |
ea0c76f8 OM |
389 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
390 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); | |
691e6415 CW |
391 | i915_gem_context_unreference(dctx); |
392 | dev_priv->ring[RCS].last_context = NULL; | |
393 | } | |
d3b448d9 | 394 | |
ea0c76f8 | 395 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
67e3d297 BW |
396 | } |
397 | ||
398 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
a4872ba6 | 399 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
67e3d297 BW |
400 | |
401 | if (ring->last_context) | |
402 | i915_gem_context_unreference(ring->last_context); | |
403 | ||
404 | ring->default_context = NULL; | |
0009e46c | 405 | ring->last_context = NULL; |
71b76d00 BW |
406 | } |
407 | ||
dce3271b | 408 | i915_gem_context_unreference(dctx); |
254f965c BW |
409 | } |
410 | ||
2fa48d8d BW |
411 | int i915_gem_context_enable(struct drm_i915_private *dev_priv) |
412 | { | |
a4872ba6 | 413 | struct intel_engine_cs *ring; |
2fa48d8d BW |
414 | int ret, i; |
415 | ||
2fa48d8d BW |
416 | /* FIXME: We should make this work, even in reset */ |
417 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
418 | return 0; | |
419 | ||
420 | BUG_ON(!dev_priv->ring[RCS].default_context); | |
bdf4fd7e | 421 | |
2fa48d8d | 422 | for_each_ring(ring, dev_priv, i) { |
691e6415 | 423 | ret = i915_switch_context(ring, ring->default_context); |
2fa48d8d BW |
424 | if (ret) |
425 | return ret; | |
426 | } | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
40521054 BW |
431 | static int context_idr_cleanup(int id, void *p, void *data) |
432 | { | |
273497e5 | 433 | struct intel_context *ctx = p; |
40521054 | 434 | |
dce3271b | 435 | i915_gem_context_unreference(ctx); |
40521054 | 436 | return 0; |
254f965c BW |
437 | } |
438 | ||
e422b888 BW |
439 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
440 | { | |
441 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
f83d6518 | 442 | struct intel_context *ctx; |
e422b888 BW |
443 | |
444 | idr_init(&file_priv->context_idr); | |
445 | ||
0eea67eb | 446 | mutex_lock(&dev->struct_mutex); |
f83d6518 | 447 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
0eea67eb BW |
448 | mutex_unlock(&dev->struct_mutex); |
449 | ||
f83d6518 | 450 | if (IS_ERR(ctx)) { |
0eea67eb | 451 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 452 | return PTR_ERR(ctx); |
0eea67eb BW |
453 | } |
454 | ||
e422b888 BW |
455 | return 0; |
456 | } | |
457 | ||
254f965c BW |
458 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
459 | { | |
40521054 | 460 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 461 | |
73c273eb | 462 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 463 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
464 | } |
465 | ||
273497e5 | 466 | struct intel_context * |
40521054 BW |
467 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
468 | { | |
273497e5 | 469 | struct intel_context *ctx; |
72ad5c45 | 470 | |
273497e5 | 471 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
72ad5c45 BW |
472 | if (!ctx) |
473 | return ERR_PTR(-ENOENT); | |
474 | ||
475 | return ctx; | |
254f965c | 476 | } |
e0556841 BW |
477 | |
478 | static inline int | |
a4872ba6 | 479 | mi_set_context(struct intel_engine_cs *ring, |
273497e5 | 480 | struct intel_context *new_context, |
e0556841 BW |
481 | u32 hw_flags) |
482 | { | |
483 | int ret; | |
484 | ||
12b0286f BW |
485 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
486 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
487 | * explicitly, so we rely on the value at ring init, stored in | |
488 | * itlb_before_ctx_switch. | |
489 | */ | |
057f6a8a | 490 | if (IS_GEN6(ring->dev)) { |
ac82ea2e | 491 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
492 | if (ret) |
493 | return ret; | |
494 | } | |
495 | ||
e37ec39b | 496 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
497 | if (ret) |
498 | return ret; | |
499 | ||
b3f797ac | 500 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
64bed788 | 501 | if (INTEL_INFO(ring->dev)->gen >= 7) |
e37ec39b BW |
502 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
503 | else | |
504 | intel_ring_emit(ring, MI_NOOP); | |
505 | ||
e0556841 BW |
506 | intel_ring_emit(ring, MI_NOOP); |
507 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
ea0c76f8 | 508 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) | |
e0556841 BW |
509 | MI_MM_SPACE_GTT | |
510 | MI_SAVE_EXT_STATE_EN | | |
511 | MI_RESTORE_EXT_STATE_EN | | |
512 | hw_flags); | |
2b7e8082 VS |
513 | /* |
514 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
515 | * WaMiSetContext_Hang:snb,ivb,vlv | |
516 | */ | |
e0556841 BW |
517 | intel_ring_emit(ring, MI_NOOP); |
518 | ||
64bed788 | 519 | if (INTEL_INFO(ring->dev)->gen >= 7) |
e37ec39b BW |
520 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
521 | else | |
522 | intel_ring_emit(ring, MI_NOOP); | |
523 | ||
e0556841 BW |
524 | intel_ring_advance(ring); |
525 | ||
526 | return ret; | |
527 | } | |
528 | ||
a4872ba6 | 529 | static int do_switch(struct intel_engine_cs *ring, |
273497e5 | 530 | struct intel_context *to) |
e0556841 | 531 | { |
6f65e29a | 532 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
273497e5 | 533 | struct intel_context *from = ring->last_context; |
e0556841 | 534 | u32 hw_flags = 0; |
967ab6b1 | 535 | bool uninitialized = false; |
3ccfd19d | 536 | int ret, i; |
e0556841 | 537 | |
67e3d297 | 538 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
ea0c76f8 OM |
539 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
540 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); | |
67e3d297 | 541 | } |
e0556841 | 542 | |
14d8ec54 | 543 | if (from == to && !to->remap_slice) |
9a3b5304 CW |
544 | return 0; |
545 | ||
7e0d96bc BW |
546 | /* Trying to pin first makes error handling easier. */ |
547 | if (ring == &dev_priv->ring[RCS]) { | |
ea0c76f8 | 548 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
1ec9e26d | 549 | get_context_alignment(ring->dev), 0); |
7e0d96bc BW |
550 | if (ret) |
551 | return ret; | |
67e3d297 BW |
552 | } |
553 | ||
acc240d4 DV |
554 | /* |
555 | * Pin can switch back to the default context if we end up calling into | |
556 | * evict_everything - as a last ditch gtt defrag effort that also | |
557 | * switches to the default context. Hence we need to reload from here. | |
558 | */ | |
559 | from = ring->last_context; | |
560 | ||
ae6c4806 DV |
561 | if (to->ppgtt) { |
562 | ret = to->ppgtt->switch_mm(to->ppgtt, ring, false); | |
7e0d96bc BW |
563 | if (ret) |
564 | goto unpin_out; | |
565 | } | |
566 | ||
567 | if (ring != &dev_priv->ring[RCS]) { | |
568 | if (from) | |
569 | i915_gem_context_unreference(from); | |
570 | goto done; | |
571 | } | |
572 | ||
acc240d4 DV |
573 | /* |
574 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
575 | * that thanks to write = false in this call and us not setting any gpu |
576 | * write domains when putting a context object onto the active list | |
577 | * (when switching away from it), this won't block. | |
acc240d4 DV |
578 | * |
579 | * XXX: We need a real interface to do this instead of trickery. | |
580 | */ | |
ea0c76f8 | 581 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
7e0d96bc BW |
582 | if (ret) |
583 | goto unpin_out; | |
d3373a24 | 584 | |
ea0c76f8 OM |
585 | if (!to->legacy_hw_ctx.rcs_state->has_global_gtt_mapping) { |
586 | struct i915_vma *vma = i915_gem_obj_to_vma(to->legacy_hw_ctx.rcs_state, | |
6f65e29a | 587 | &dev_priv->gtt.base); |
ea0c76f8 | 588 | vma->bind_vma(vma, to->legacy_hw_ctx.rcs_state->cache_level, GLOBAL_BIND); |
6f65e29a | 589 | } |
3af7b857 | 590 | |
ea0c76f8 | 591 | if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) |
e0556841 | 592 | hw_flags |= MI_RESTORE_INHIBIT; |
e0556841 | 593 | |
e0556841 | 594 | ret = mi_set_context(ring, to, hw_flags); |
7e0d96bc BW |
595 | if (ret) |
596 | goto unpin_out; | |
e0556841 | 597 | |
3ccfd19d BW |
598 | for (i = 0; i < MAX_L3_SLICES; i++) { |
599 | if (!(to->remap_slice & (1<<i))) | |
600 | continue; | |
601 | ||
602 | ret = i915_gem_l3_remap(ring, i); | |
603 | /* If it failed, try again next round */ | |
604 | if (ret) | |
605 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
606 | else | |
607 | to->remap_slice &= ~(1<<i); | |
608 | } | |
609 | ||
e0556841 BW |
610 | /* The backing object for the context is done after switching to the |
611 | * *next* context. Therefore we cannot retire the previous context until | |
612 | * the next context has already started running. In fact, the below code | |
613 | * is a bit suboptimal because the retiring can occur simply after the | |
614 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
615 | */ | |
112522f6 | 616 | if (from != NULL) { |
ea0c76f8 OM |
617 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
618 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), ring); | |
e0556841 BW |
619 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
620 | * whole damn pipeline, we don't need to explicitly mark the | |
621 | * object dirty. The only exception is that the context must be | |
622 | * correct in case the object gets swapped out. Ideally we'd be | |
623 | * able to defer doing this until we know the object would be | |
624 | * swapped, but there is no way to do that yet. | |
625 | */ | |
ea0c76f8 OM |
626 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
627 | BUG_ON(from->legacy_hw_ctx.rcs_state->ring != ring); | |
112522f6 | 628 | |
c0321e2c | 629 | /* obj is kept alive until the next request by its active ref */ |
ea0c76f8 | 630 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
112522f6 | 631 | i915_gem_context_unreference(from); |
e0556841 BW |
632 | } |
633 | ||
ea0c76f8 OM |
634 | uninitialized = !to->legacy_hw_ctx.initialized && from == NULL; |
635 | to->legacy_hw_ctx.initialized = true; | |
967ab6b1 | 636 | |
67e3d297 | 637 | done: |
112522f6 CW |
638 | i915_gem_context_reference(to); |
639 | ring->last_context = to; | |
e0556841 | 640 | |
967ab6b1 | 641 | if (uninitialized) { |
46470fc9 MK |
642 | ret = i915_gem_render_state_init(ring); |
643 | if (ret) | |
644 | DRM_ERROR("init render state: %d\n", ret); | |
645 | } | |
646 | ||
e0556841 | 647 | return 0; |
7e0d96bc BW |
648 | |
649 | unpin_out: | |
650 | if (ring->id == RCS) | |
ea0c76f8 | 651 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
7e0d96bc | 652 | return ret; |
e0556841 BW |
653 | } |
654 | ||
655 | /** | |
656 | * i915_switch_context() - perform a GPU context switch. | |
657 | * @ring: ring for which we'll execute the context switch | |
96a6f0f1 | 658 | * @to: the context to switch to |
e0556841 BW |
659 | * |
660 | * The context life cycle is simple. The context refcount is incremented and | |
661 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
662 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
663 | * object while letting the normal object tracking destroy the backing BO. | |
664 | */ | |
a4872ba6 | 665 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 | 666 | struct intel_context *to) |
e0556841 BW |
667 | { |
668 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 669 | |
0eea67eb BW |
670 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
671 | ||
ea0c76f8 | 672 | if (to->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
691e6415 CW |
673 | if (to != ring->last_context) { |
674 | i915_gem_context_reference(to); | |
675 | if (ring->last_context) | |
676 | i915_gem_context_unreference(ring->last_context); | |
677 | ring->last_context = to; | |
678 | } | |
c482972a | 679 | return 0; |
a95f6a00 | 680 | } |
c482972a | 681 | |
67e3d297 | 682 | return do_switch(ring, to); |
e0556841 | 683 | } |
84624813 | 684 | |
ec3e9963 | 685 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 686 | { |
ec3e9963 | 687 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
688 | } |
689 | ||
84624813 BW |
690 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
691 | struct drm_file *file) | |
692 | { | |
84624813 BW |
693 | struct drm_i915_gem_context_create *args = data; |
694 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 695 | struct intel_context *ctx; |
84624813 BW |
696 | int ret; |
697 | ||
ec3e9963 | 698 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
699 | return -ENODEV; |
700 | ||
84624813 BW |
701 | ret = i915_mutex_lock_interruptible(dev); |
702 | if (ret) | |
703 | return ret; | |
704 | ||
7e0d96bc | 705 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
84624813 | 706 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
707 | if (IS_ERR(ctx)) |
708 | return PTR_ERR(ctx); | |
84624813 | 709 | |
821d66dd | 710 | args->ctx_id = ctx->user_handle; |
84624813 BW |
711 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
712 | ||
be636387 | 713 | return 0; |
84624813 BW |
714 | } |
715 | ||
716 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
717 | struct drm_file *file) | |
718 | { | |
719 | struct drm_i915_gem_context_destroy *args = data; | |
720 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 721 | struct intel_context *ctx; |
84624813 BW |
722 | int ret; |
723 | ||
821d66dd | 724 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 725 | return -ENOENT; |
0eea67eb | 726 | |
84624813 BW |
727 | ret = i915_mutex_lock_interruptible(dev); |
728 | if (ret) | |
729 | return ret; | |
730 | ||
731 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
72ad5c45 | 732 | if (IS_ERR(ctx)) { |
84624813 | 733 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 734 | return PTR_ERR(ctx); |
84624813 BW |
735 | } |
736 | ||
821d66dd | 737 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
dce3271b | 738 | i915_gem_context_unreference(ctx); |
84624813 BW |
739 | mutex_unlock(&dev->struct_mutex); |
740 | ||
741 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
742 | return 0; | |
743 | } |