Commit | Line | Data |
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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c BW |
90 | #include "i915_drv.h" |
91 | ||
40521054 BW |
92 | /* This is a HW constraint. The value below is the largest known requirement |
93 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
94 | * part. It should be safe to decrease this, but it's more future proof as is. | |
95 | */ | |
b731d33d BW |
96 | #define GEN6_CONTEXT_ALIGN (64<<10) |
97 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 98 | |
b18b6bde | 99 | static void do_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
321f2ada | 100 | { |
321f2ada BW |
101 | struct drm_device *dev = ppgtt->base.dev; |
102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
103 | struct i915_address_space *vm = &ppgtt->base; | |
104 | ||
105 | if (ppgtt == dev_priv->mm.aliasing_ppgtt || | |
106 | (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) { | |
107 | ppgtt->base.cleanup(&ppgtt->base); | |
108 | return; | |
109 | } | |
110 | ||
111 | /* | |
112 | * Make sure vmas are unbound before we take down the drm_mm | |
113 | * | |
114 | * FIXME: Proper refcounting should take care of this, this shouldn't be | |
115 | * needed at all. | |
116 | */ | |
117 | if (!list_empty(&vm->active_list)) { | |
118 | struct i915_vma *vma; | |
119 | ||
120 | list_for_each_entry(vma, &vm->active_list, mm_list) | |
121 | if (WARN_ON(list_empty(&vma->vma_link) || | |
122 | list_is_singular(&vma->vma_link))) | |
123 | break; | |
124 | ||
125 | i915_gem_evict_vm(&ppgtt->base, true); | |
126 | } else { | |
127 | i915_gem_retire_requests(dev); | |
128 | i915_gem_evict_vm(&ppgtt->base, false); | |
129 | } | |
130 | ||
131 | ppgtt->base.cleanup(&ppgtt->base); | |
132 | } | |
133 | ||
b18b6bde BW |
134 | static void ppgtt_release(struct kref *kref) |
135 | { | |
136 | struct i915_hw_ppgtt *ppgtt = | |
137 | container_of(kref, struct i915_hw_ppgtt, ref); | |
138 | ||
139 | do_ppgtt_cleanup(ppgtt); | |
140 | kfree(ppgtt); | |
141 | } | |
142 | ||
b731d33d BW |
143 | static size_t get_context_alignment(struct drm_device *dev) |
144 | { | |
145 | if (IS_GEN6(dev)) | |
146 | return GEN6_CONTEXT_ALIGN; | |
147 | ||
148 | return GEN7_CONTEXT_ALIGN; | |
149 | } | |
150 | ||
254f965c BW |
151 | static int get_context_size(struct drm_device *dev) |
152 | { | |
153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
154 | int ret; | |
155 | u32 reg; | |
156 | ||
157 | switch (INTEL_INFO(dev)->gen) { | |
158 | case 6: | |
159 | reg = I915_READ(CXT_SIZE); | |
160 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
161 | break; | |
162 | case 7: | |
4f91dd6f | 163 | reg = I915_READ(GEN7_CXT_SIZE); |
2e4291e0 | 164 | if (IS_HASWELL(dev)) |
a0de80a0 | 165 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
166 | else |
167 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 168 | break; |
8897644a BW |
169 | case 8: |
170 | ret = GEN8_CXT_TOTAL_SIZE; | |
171 | break; | |
254f965c BW |
172 | default: |
173 | BUG(); | |
174 | } | |
175 | ||
176 | return ret; | |
177 | } | |
178 | ||
dce3271b | 179 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 180 | { |
273497e5 | 181 | struct intel_context *ctx = container_of(ctx_ref, |
dce3271b | 182 | typeof(*ctx), ref); |
c7c48dfd | 183 | struct i915_hw_ppgtt *ppgtt = NULL; |
40521054 | 184 | |
ea0c76f8 | 185 | if (ctx->legacy_hw_ctx.rcs_state) { |
691e6415 | 186 | /* We refcount even the aliasing PPGTT to keep the code symmetric */ |
ea0c76f8 | 187 | if (USES_PPGTT(ctx->legacy_hw_ctx.rcs_state->base.dev)) |
691e6415 | 188 | ppgtt = ctx_to_ppgtt(ctx); |
691e6415 | 189 | } |
c7c48dfd BW |
190 | |
191 | if (ppgtt) | |
192 | kref_put(&ppgtt->ref, ppgtt_release); | |
2f295791 BW |
193 | if (ctx->legacy_hw_ctx.rcs_state) |
194 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); | |
c7c48dfd | 195 | list_del(&ctx->link); |
40521054 BW |
196 | kfree(ctx); |
197 | } | |
198 | ||
aa0c13da OM |
199 | static struct drm_i915_gem_object * |
200 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) | |
201 | { | |
202 | struct drm_i915_gem_object *obj; | |
203 | int ret; | |
204 | ||
205 | obj = i915_gem_alloc_object(dev, size); | |
206 | if (obj == NULL) | |
207 | return ERR_PTR(-ENOMEM); | |
208 | ||
209 | /* | |
210 | * Try to make the context utilize L3 as well as LLC. | |
211 | * | |
212 | * On VLV we don't have L3 controls in the PTEs so we | |
213 | * shouldn't touch the cache level, especially as that | |
214 | * would make the object snooped which might have a | |
215 | * negative performance impact. | |
216 | */ | |
217 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { | |
218 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
219 | /* Failure shouldn't ever happen this early */ | |
220 | if (WARN_ON(ret)) { | |
221 | drm_gem_object_unreference(&obj->base); | |
222 | return ERR_PTR(ret); | |
223 | } | |
224 | } | |
225 | ||
226 | return obj; | |
227 | } | |
228 | ||
bdf4fd7e | 229 | static struct i915_hw_ppgtt * |
273497e5 | 230 | create_vm_for_ctx(struct drm_device *dev, struct intel_context *ctx) |
bdf4fd7e BW |
231 | { |
232 | struct i915_hw_ppgtt *ppgtt; | |
233 | int ret; | |
234 | ||
235 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
236 | if (!ppgtt) | |
237 | return ERR_PTR(-ENOMEM); | |
238 | ||
239 | ret = i915_gem_init_ppgtt(dev, ppgtt); | |
240 | if (ret) { | |
241 | kfree(ppgtt); | |
242 | return ERR_PTR(ret); | |
243 | } | |
244 | ||
6313c204 | 245 | ppgtt->ctx = ctx; |
bdf4fd7e BW |
246 | return ppgtt; |
247 | } | |
248 | ||
273497e5 | 249 | static struct intel_context * |
0eea67eb | 250 | __create_hw_context(struct drm_device *dev, |
146937e5 | 251 | struct drm_i915_file_private *file_priv) |
40521054 BW |
252 | { |
253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 254 | struct intel_context *ctx; |
c8c470af | 255 | int ret; |
40521054 | 256 | |
f94982b0 | 257 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
258 | if (ctx == NULL) |
259 | return ERR_PTR(-ENOMEM); | |
40521054 | 260 | |
dce3271b | 261 | kref_init(&ctx->ref); |
691e6415 | 262 | list_add_tail(&ctx->link, &dev_priv->context_list); |
40521054 | 263 | |
691e6415 | 264 | if (dev_priv->hw_context_size) { |
aa0c13da OM |
265 | struct drm_i915_gem_object *obj = |
266 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); | |
267 | if (IS_ERR(obj)) { | |
268 | ret = PTR_ERR(obj); | |
4615d4c9 | 269 | goto err_out; |
691e6415 | 270 | } |
ea0c76f8 | 271 | ctx->legacy_hw_ctx.rcs_state = obj; |
691e6415 | 272 | } |
40521054 BW |
273 | |
274 | /* Default context will never have a file_priv */ | |
691e6415 CW |
275 | if (file_priv != NULL) { |
276 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 277 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
278 | if (ret < 0) |
279 | goto err_out; | |
280 | } else | |
821d66dd | 281 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
282 | |
283 | ctx->file_priv = file_priv; | |
821d66dd | 284 | ctx->user_handle = ret; |
3ccfd19d BW |
285 | /* NB: Mark all slices as needing a remap so that when the context first |
286 | * loads it will restore whatever remap state already exists. If there | |
287 | * is no remap info, it will be a NOP. */ | |
288 | ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1; | |
40521054 | 289 | |
146937e5 | 290 | return ctx; |
40521054 BW |
291 | |
292 | err_out: | |
dce3271b | 293 | i915_gem_context_unreference(ctx); |
146937e5 | 294 | return ERR_PTR(ret); |
40521054 BW |
295 | } |
296 | ||
254f965c BW |
297 | /** |
298 | * The default context needs to exist per ring that uses contexts. It stores the | |
299 | * context state of the GPU for applications that don't utilize HW contexts, as | |
300 | * well as an idle case. | |
301 | */ | |
273497e5 | 302 | static struct intel_context * |
0eea67eb BW |
303 | i915_gem_create_context(struct drm_device *dev, |
304 | struct drm_i915_file_private *file_priv, | |
305 | bool create_vm) | |
254f965c | 306 | { |
42c3b603 | 307 | const bool is_global_default_ctx = file_priv == NULL; |
bdf4fd7e | 308 | struct drm_i915_private *dev_priv = dev->dev_private; |
273497e5 | 309 | struct intel_context *ctx; |
bdf4fd7e | 310 | int ret = 0; |
40521054 | 311 | |
b731d33d | 312 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
40521054 | 313 | |
0eea67eb | 314 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 315 | if (IS_ERR(ctx)) |
a45d0f6a | 316 | return ctx; |
40521054 | 317 | |
ea0c76f8 | 318 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
42c3b603 CW |
319 | /* We may need to do things with the shrinker which |
320 | * require us to immediately switch back to the default | |
321 | * context. This can cause a problem as pinning the | |
322 | * default context also requires GTT space which may not | |
323 | * be available. To avoid this we always pin the default | |
324 | * context. | |
325 | */ | |
ea0c76f8 | 326 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
1ec9e26d | 327 | get_context_alignment(dev), 0); |
42c3b603 CW |
328 | if (ret) { |
329 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); | |
330 | goto err_destroy; | |
331 | } | |
332 | } | |
333 | ||
bdf4fd7e BW |
334 | if (create_vm) { |
335 | struct i915_hw_ppgtt *ppgtt = create_vm_for_ctx(dev, ctx); | |
336 | ||
337 | if (IS_ERR_OR_NULL(ppgtt)) { | |
0eea67eb BW |
338 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
339 | PTR_ERR(ppgtt)); | |
bdf4fd7e | 340 | ret = PTR_ERR(ppgtt); |
42c3b603 | 341 | goto err_unpin; |
bdf4fd7e BW |
342 | } else |
343 | ctx->vm = &ppgtt->base; | |
344 | ||
345 | /* This case is reserved for the global default context and | |
346 | * should only happen once. */ | |
42c3b603 | 347 | if (is_global_default_ctx) { |
bdf4fd7e BW |
348 | if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) { |
349 | ret = -EEXIST; | |
42c3b603 | 350 | goto err_unpin; |
bdf4fd7e BW |
351 | } |
352 | ||
353 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
bdf4fd7e | 354 | } |
c5dc5cec | 355 | } else if (USES_PPGTT(dev)) { |
bdf4fd7e BW |
356 | /* For platforms which only have aliasing PPGTT, we fake the |
357 | * address space and refcounting. */ | |
bdf4fd7e | 358 | ctx->vm = &dev_priv->mm.aliasing_ppgtt->base; |
7e0d96bc BW |
359 | kref_get(&dev_priv->mm.aliasing_ppgtt->ref); |
360 | } else | |
bdf4fd7e BW |
361 | ctx->vm = &dev_priv->gtt.base; |
362 | ||
a45d0f6a | 363 | return ctx; |
9a3b5304 | 364 | |
42c3b603 | 365 | err_unpin: |
ea0c76f8 OM |
366 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
367 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); | |
9a3b5304 | 368 | err_destroy: |
dce3271b | 369 | i915_gem_context_unreference(ctx); |
a45d0f6a | 370 | return ERR_PTR(ret); |
254f965c BW |
371 | } |
372 | ||
acce9ffa BW |
373 | void i915_gem_context_reset(struct drm_device *dev) |
374 | { | |
375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
acce9ffa BW |
376 | int i; |
377 | ||
acce9ffa BW |
378 | /* Prevent the hardware from restoring the last context (which hung) on |
379 | * the next switch */ | |
380 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
a4872ba6 | 381 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
273497e5 | 382 | struct intel_context *dctx = ring->default_context; |
ea0c76f8 | 383 | struct intel_context *lctx = ring->last_context; |
acce9ffa BW |
384 | |
385 | /* Do a fake switch to the default context */ | |
ea0c76f8 | 386 | if (lctx == dctx) |
acce9ffa BW |
387 | continue; |
388 | ||
ea0c76f8 | 389 | if (!lctx) |
acce9ffa BW |
390 | continue; |
391 | ||
ea0c76f8 OM |
392 | if (dctx->legacy_hw_ctx.rcs_state && i == RCS) { |
393 | WARN_ON(i915_gem_obj_ggtt_pin(dctx->legacy_hw_ctx.rcs_state, | |
1ec9e26d | 394 | get_context_alignment(dev), 0)); |
acce9ffa | 395 | /* Fake a finish/inactive */ |
ea0c76f8 OM |
396 | dctx->legacy_hw_ctx.rcs_state->base.write_domain = 0; |
397 | dctx->legacy_hw_ctx.rcs_state->active = 0; | |
acce9ffa BW |
398 | } |
399 | ||
ea0c76f8 OM |
400 | if (lctx->legacy_hw_ctx.rcs_state && i == RCS) |
401 | i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state); | |
4bfad3dd | 402 | |
ea0c76f8 | 403 | i915_gem_context_unreference(lctx); |
acce9ffa BW |
404 | i915_gem_context_reference(dctx); |
405 | ring->last_context = dctx; | |
406 | } | |
407 | } | |
408 | ||
8245be31 | 409 | int i915_gem_context_init(struct drm_device *dev) |
254f965c BW |
410 | { |
411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 412 | struct intel_context *ctx; |
a45d0f6a | 413 | int i; |
254f965c | 414 | |
2fa48d8d BW |
415 | /* Init should only be called once per module load. Eventually the |
416 | * restriction on the context_disabled check can be loosened. */ | |
417 | if (WARN_ON(dev_priv->ring[RCS].default_context)) | |
8245be31 | 418 | return 0; |
254f965c | 419 | |
691e6415 CW |
420 | if (HAS_HW_CONTEXTS(dev)) { |
421 | dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); | |
422 | if (dev_priv->hw_context_size > (1<<20)) { | |
423 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
424 | dev_priv->hw_context_size); | |
425 | dev_priv->hw_context_size = 0; | |
426 | } | |
254f965c BW |
427 | } |
428 | ||
691e6415 CW |
429 | ctx = i915_gem_create_context(dev, NULL, USES_PPGTT(dev)); |
430 | if (IS_ERR(ctx)) { | |
431 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
432 | PTR_ERR(ctx)); | |
433 | return PTR_ERR(ctx); | |
254f965c BW |
434 | } |
435 | ||
691e6415 CW |
436 | /* NB: RCS will hold a ref for all rings */ |
437 | for (i = 0; i < I915_NUM_RINGS; i++) | |
438 | dev_priv->ring[i].default_context = ctx; | |
67e3d297 | 439 | |
691e6415 | 440 | DRM_DEBUG_DRIVER("%s context support initialized\n", dev_priv->hw_context_size ? "HW" : "fake"); |
8245be31 | 441 | return 0; |
254f965c BW |
442 | } |
443 | ||
444 | void i915_gem_context_fini(struct drm_device *dev) | |
445 | { | |
446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273497e5 | 447 | struct intel_context *dctx = dev_priv->ring[RCS].default_context; |
67e3d297 | 448 | int i; |
254f965c | 449 | |
ea0c76f8 | 450 | if (dctx->legacy_hw_ctx.rcs_state) { |
691e6415 CW |
451 | /* The only known way to stop the gpu from accessing the hw context is |
452 | * to reset it. Do this as the very last operation to avoid confusing | |
453 | * other code, leading to spurious errors. */ | |
454 | intel_gpu_reset(dev); | |
455 | ||
456 | /* When default context is created and switched to, base object refcount | |
457 | * will be 2 (+1 from object creation and +1 from do_switch()). | |
458 | * i915_gem_context_fini() will be called after gpu_idle() has switched | |
459 | * to default context. So we need to unreference the base object once | |
460 | * to offset the do_switch part, so that i915_gem_context_unreference() | |
461 | * can then free the base object correctly. */ | |
462 | WARN_ON(!dev_priv->ring[RCS].last_context); | |
463 | if (dev_priv->ring[RCS].last_context == dctx) { | |
464 | /* Fake switch to NULL context */ | |
ea0c76f8 OM |
465 | WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); |
466 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); | |
691e6415 CW |
467 | i915_gem_context_unreference(dctx); |
468 | dev_priv->ring[RCS].last_context = NULL; | |
469 | } | |
d3b448d9 | 470 | |
ea0c76f8 | 471 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
67e3d297 BW |
472 | } |
473 | ||
474 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
a4872ba6 | 475 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
67e3d297 BW |
476 | |
477 | if (ring->last_context) | |
478 | i915_gem_context_unreference(ring->last_context); | |
479 | ||
480 | ring->default_context = NULL; | |
0009e46c | 481 | ring->last_context = NULL; |
71b76d00 BW |
482 | } |
483 | ||
dce3271b | 484 | i915_gem_context_unreference(dctx); |
254f965c BW |
485 | } |
486 | ||
2fa48d8d BW |
487 | int i915_gem_context_enable(struct drm_i915_private *dev_priv) |
488 | { | |
a4872ba6 | 489 | struct intel_engine_cs *ring; |
2fa48d8d BW |
490 | int ret, i; |
491 | ||
bdf4fd7e BW |
492 | /* This is the only place the aliasing PPGTT gets enabled, which means |
493 | * it has to happen before we bail on reset */ | |
494 | if (dev_priv->mm.aliasing_ppgtt) { | |
495 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
496 | ppgtt->enable(ppgtt); | |
497 | } | |
498 | ||
2fa48d8d BW |
499 | /* FIXME: We should make this work, even in reset */ |
500 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
501 | return 0; | |
502 | ||
503 | BUG_ON(!dev_priv->ring[RCS].default_context); | |
bdf4fd7e | 504 | |
2fa48d8d | 505 | for_each_ring(ring, dev_priv, i) { |
691e6415 | 506 | ret = i915_switch_context(ring, ring->default_context); |
2fa48d8d BW |
507 | if (ret) |
508 | return ret; | |
509 | } | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
40521054 BW |
514 | static int context_idr_cleanup(int id, void *p, void *data) |
515 | { | |
273497e5 | 516 | struct intel_context *ctx = p; |
40521054 | 517 | |
dce3271b | 518 | i915_gem_context_unreference(ctx); |
40521054 | 519 | return 0; |
254f965c BW |
520 | } |
521 | ||
e422b888 BW |
522 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
523 | { | |
524 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
f83d6518 | 525 | struct intel_context *ctx; |
e422b888 BW |
526 | |
527 | idr_init(&file_priv->context_idr); | |
528 | ||
0eea67eb | 529 | mutex_lock(&dev->struct_mutex); |
f83d6518 | 530 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
0eea67eb BW |
531 | mutex_unlock(&dev->struct_mutex); |
532 | ||
f83d6518 | 533 | if (IS_ERR(ctx)) { |
0eea67eb | 534 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 535 | return PTR_ERR(ctx); |
0eea67eb BW |
536 | } |
537 | ||
e422b888 BW |
538 | return 0; |
539 | } | |
540 | ||
254f965c BW |
541 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
542 | { | |
40521054 | 543 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 544 | |
73c273eb | 545 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 546 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
547 | } |
548 | ||
273497e5 | 549 | struct intel_context * |
40521054 BW |
550 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
551 | { | |
273497e5 | 552 | struct intel_context *ctx; |
72ad5c45 | 553 | |
273497e5 | 554 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
72ad5c45 BW |
555 | if (!ctx) |
556 | return ERR_PTR(-ENOENT); | |
557 | ||
558 | return ctx; | |
254f965c | 559 | } |
e0556841 BW |
560 | |
561 | static inline int | |
a4872ba6 | 562 | mi_set_context(struct intel_engine_cs *ring, |
273497e5 | 563 | struct intel_context *new_context, |
e0556841 BW |
564 | u32 hw_flags) |
565 | { | |
566 | int ret; | |
567 | ||
12b0286f BW |
568 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
569 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
570 | * explicitly, so we rely on the value at ring init, stored in | |
571 | * itlb_before_ctx_switch. | |
572 | */ | |
057f6a8a | 573 | if (IS_GEN6(ring->dev)) { |
ac82ea2e | 574 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); |
12b0286f BW |
575 | if (ret) |
576 | return ret; | |
577 | } | |
578 | ||
e37ec39b | 579 | ret = intel_ring_begin(ring, 6); |
e0556841 BW |
580 | if (ret) |
581 | return ret; | |
582 | ||
b3f797ac | 583 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
64bed788 | 584 | if (INTEL_INFO(ring->dev)->gen >= 7) |
e37ec39b BW |
585 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
586 | else | |
587 | intel_ring_emit(ring, MI_NOOP); | |
588 | ||
e0556841 BW |
589 | intel_ring_emit(ring, MI_NOOP); |
590 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
ea0c76f8 | 591 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) | |
e0556841 BW |
592 | MI_MM_SPACE_GTT | |
593 | MI_SAVE_EXT_STATE_EN | | |
594 | MI_RESTORE_EXT_STATE_EN | | |
595 | hw_flags); | |
2b7e8082 VS |
596 | /* |
597 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
598 | * WaMiSetContext_Hang:snb,ivb,vlv | |
599 | */ | |
e0556841 BW |
600 | intel_ring_emit(ring, MI_NOOP); |
601 | ||
64bed788 | 602 | if (INTEL_INFO(ring->dev)->gen >= 7) |
e37ec39b BW |
603 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
604 | else | |
605 | intel_ring_emit(ring, MI_NOOP); | |
606 | ||
e0556841 BW |
607 | intel_ring_advance(ring); |
608 | ||
609 | return ret; | |
610 | } | |
611 | ||
a4872ba6 | 612 | static int do_switch(struct intel_engine_cs *ring, |
273497e5 | 613 | struct intel_context *to) |
e0556841 | 614 | { |
6f65e29a | 615 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
273497e5 | 616 | struct intel_context *from = ring->last_context; |
7e0d96bc | 617 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to); |
e0556841 | 618 | u32 hw_flags = 0; |
967ab6b1 | 619 | bool uninitialized = false; |
3ccfd19d | 620 | int ret, i; |
e0556841 | 621 | |
67e3d297 | 622 | if (from != NULL && ring == &dev_priv->ring[RCS]) { |
ea0c76f8 OM |
623 | BUG_ON(from->legacy_hw_ctx.rcs_state == NULL); |
624 | BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state)); | |
67e3d297 | 625 | } |
e0556841 | 626 | |
14d8ec54 | 627 | if (from == to && !to->remap_slice) |
9a3b5304 CW |
628 | return 0; |
629 | ||
7e0d96bc BW |
630 | /* Trying to pin first makes error handling easier. */ |
631 | if (ring == &dev_priv->ring[RCS]) { | |
ea0c76f8 | 632 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
1ec9e26d | 633 | get_context_alignment(ring->dev), 0); |
7e0d96bc BW |
634 | if (ret) |
635 | return ret; | |
67e3d297 BW |
636 | } |
637 | ||
acc240d4 DV |
638 | /* |
639 | * Pin can switch back to the default context if we end up calling into | |
640 | * evict_everything - as a last ditch gtt defrag effort that also | |
641 | * switches to the default context. Hence we need to reload from here. | |
642 | */ | |
643 | from = ring->last_context; | |
644 | ||
7e0d96bc BW |
645 | if (USES_FULL_PPGTT(ring->dev)) { |
646 | ret = ppgtt->switch_mm(ppgtt, ring, false); | |
647 | if (ret) | |
648 | goto unpin_out; | |
649 | } | |
650 | ||
651 | if (ring != &dev_priv->ring[RCS]) { | |
652 | if (from) | |
653 | i915_gem_context_unreference(from); | |
654 | goto done; | |
655 | } | |
656 | ||
acc240d4 DV |
657 | /* |
658 | * Clear this page out of any CPU caches for coherent swap-in/out. Note | |
d3373a24 CW |
659 | * that thanks to write = false in this call and us not setting any gpu |
660 | * write domains when putting a context object onto the active list | |
661 | * (when switching away from it), this won't block. | |
acc240d4 DV |
662 | * |
663 | * XXX: We need a real interface to do this instead of trickery. | |
664 | */ | |
ea0c76f8 | 665 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
7e0d96bc BW |
666 | if (ret) |
667 | goto unpin_out; | |
d3373a24 | 668 | |
ea0c76f8 OM |
669 | if (!to->legacy_hw_ctx.rcs_state->has_global_gtt_mapping) { |
670 | struct i915_vma *vma = i915_gem_obj_to_vma(to->legacy_hw_ctx.rcs_state, | |
6f65e29a | 671 | &dev_priv->gtt.base); |
ea0c76f8 | 672 | vma->bind_vma(vma, to->legacy_hw_ctx.rcs_state->cache_level, GLOBAL_BIND); |
6f65e29a | 673 | } |
3af7b857 | 674 | |
ea0c76f8 | 675 | if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) |
e0556841 | 676 | hw_flags |= MI_RESTORE_INHIBIT; |
e0556841 | 677 | |
e0556841 | 678 | ret = mi_set_context(ring, to, hw_flags); |
7e0d96bc BW |
679 | if (ret) |
680 | goto unpin_out; | |
e0556841 | 681 | |
3ccfd19d BW |
682 | for (i = 0; i < MAX_L3_SLICES; i++) { |
683 | if (!(to->remap_slice & (1<<i))) | |
684 | continue; | |
685 | ||
686 | ret = i915_gem_l3_remap(ring, i); | |
687 | /* If it failed, try again next round */ | |
688 | if (ret) | |
689 | DRM_DEBUG_DRIVER("L3 remapping failed\n"); | |
690 | else | |
691 | to->remap_slice &= ~(1<<i); | |
692 | } | |
693 | ||
e0556841 BW |
694 | /* The backing object for the context is done after switching to the |
695 | * *next* context. Therefore we cannot retire the previous context until | |
696 | * the next context has already started running. In fact, the below code | |
697 | * is a bit suboptimal because the retiring can occur simply after the | |
698 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
699 | */ | |
112522f6 | 700 | if (from != NULL) { |
ea0c76f8 OM |
701 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
702 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), ring); | |
e0556841 BW |
703 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
704 | * whole damn pipeline, we don't need to explicitly mark the | |
705 | * object dirty. The only exception is that the context must be | |
706 | * correct in case the object gets swapped out. Ideally we'd be | |
707 | * able to defer doing this until we know the object would be | |
708 | * swapped, but there is no way to do that yet. | |
709 | */ | |
ea0c76f8 OM |
710 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
711 | BUG_ON(from->legacy_hw_ctx.rcs_state->ring != ring); | |
112522f6 | 712 | |
c0321e2c | 713 | /* obj is kept alive until the next request by its active ref */ |
ea0c76f8 | 714 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
112522f6 | 715 | i915_gem_context_unreference(from); |
e0556841 BW |
716 | } |
717 | ||
ea0c76f8 OM |
718 | uninitialized = !to->legacy_hw_ctx.initialized && from == NULL; |
719 | to->legacy_hw_ctx.initialized = true; | |
967ab6b1 | 720 | |
67e3d297 | 721 | done: |
112522f6 CW |
722 | i915_gem_context_reference(to); |
723 | ring->last_context = to; | |
e0556841 | 724 | |
967ab6b1 | 725 | if (uninitialized) { |
46470fc9 MK |
726 | ret = i915_gem_render_state_init(ring); |
727 | if (ret) | |
728 | DRM_ERROR("init render state: %d\n", ret); | |
729 | } | |
730 | ||
e0556841 | 731 | return 0; |
7e0d96bc BW |
732 | |
733 | unpin_out: | |
734 | if (ring->id == RCS) | |
ea0c76f8 | 735 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
7e0d96bc | 736 | return ret; |
e0556841 BW |
737 | } |
738 | ||
739 | /** | |
740 | * i915_switch_context() - perform a GPU context switch. | |
741 | * @ring: ring for which we'll execute the context switch | |
96a6f0f1 | 742 | * @to: the context to switch to |
e0556841 BW |
743 | * |
744 | * The context life cycle is simple. The context refcount is incremented and | |
745 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
746 | * it will have a refoucnt > 1. This allows us to destroy the context abstract | |
747 | * object while letting the normal object tracking destroy the backing BO. | |
748 | */ | |
a4872ba6 | 749 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 | 750 | struct intel_context *to) |
e0556841 BW |
751 | { |
752 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
e0556841 | 753 | |
0eea67eb BW |
754 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
755 | ||
ea0c76f8 | 756 | if (to->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ |
691e6415 CW |
757 | if (to != ring->last_context) { |
758 | i915_gem_context_reference(to); | |
759 | if (ring->last_context) | |
760 | i915_gem_context_unreference(ring->last_context); | |
761 | ring->last_context = to; | |
762 | } | |
c482972a | 763 | return 0; |
a95f6a00 | 764 | } |
c482972a | 765 | |
67e3d297 | 766 | return do_switch(ring, to); |
e0556841 | 767 | } |
84624813 | 768 | |
691e6415 CW |
769 | static bool hw_context_enabled(struct drm_device *dev) |
770 | { | |
771 | return to_i915(dev)->hw_context_size; | |
772 | } | |
773 | ||
84624813 BW |
774 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
775 | struct drm_file *file) | |
776 | { | |
84624813 BW |
777 | struct drm_i915_gem_context_create *args = data; |
778 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 779 | struct intel_context *ctx; |
84624813 BW |
780 | int ret; |
781 | ||
691e6415 | 782 | if (!hw_context_enabled(dev)) |
5fa8be65 DV |
783 | return -ENODEV; |
784 | ||
84624813 BW |
785 | ret = i915_mutex_lock_interruptible(dev); |
786 | if (ret) | |
787 | return ret; | |
788 | ||
7e0d96bc | 789 | ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev)); |
84624813 | 790 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
791 | if (IS_ERR(ctx)) |
792 | return PTR_ERR(ctx); | |
84624813 | 793 | |
821d66dd | 794 | args->ctx_id = ctx->user_handle; |
84624813 BW |
795 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
796 | ||
be636387 | 797 | return 0; |
84624813 BW |
798 | } |
799 | ||
800 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
801 | struct drm_file *file) | |
802 | { | |
803 | struct drm_i915_gem_context_destroy *args = data; | |
804 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
273497e5 | 805 | struct intel_context *ctx; |
84624813 BW |
806 | int ret; |
807 | ||
821d66dd | 808 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 809 | return -ENOENT; |
0eea67eb | 810 | |
84624813 BW |
811 | ret = i915_mutex_lock_interruptible(dev); |
812 | if (ret) | |
813 | return ret; | |
814 | ||
815 | ctx = i915_gem_context_get(file_priv, args->ctx_id); | |
72ad5c45 | 816 | if (IS_ERR(ctx)) { |
84624813 | 817 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 818 | return PTR_ERR(ctx); |
84624813 BW |
819 | } |
820 | ||
821d66dd | 821 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
dce3271b | 822 | i915_gem_context_unreference(ctx); |
84624813 BW |
823 | mutex_unlock(&dev->struct_mutex); |
824 | ||
825 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
826 | return 0; | |
827 | } |