Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
67731b87 | 36 | struct eb_objects { |
bcffc3fa | 37 | struct list_head objects; |
67731b87 | 38 | int and; |
eef90ccb CW |
39 | union { |
40 | struct drm_i915_gem_object *lut[0]; | |
41 | struct hlist_head buckets[0]; | |
42 | }; | |
67731b87 CW |
43 | }; |
44 | ||
45 | static struct eb_objects * | |
eef90ccb | 46 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 47 | { |
eef90ccb CW |
48 | struct eb_objects *eb = NULL; |
49 | ||
50 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
51 | int size = args->buffer_count; | |
52 | size *= sizeof(struct drm_i915_gem_object *); | |
53 | size += sizeof(struct eb_objects); | |
54 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); | |
55 | } | |
56 | ||
57 | if (eb == NULL) { | |
58 | int size = args->buffer_count; | |
59 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 60 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
61 | while (count > 2*size) |
62 | count >>= 1; | |
63 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
64 | sizeof(struct eb_objects), | |
65 | GFP_TEMPORARY); | |
66 | if (eb == NULL) | |
67 | return eb; | |
68 | ||
69 | eb->and = count - 1; | |
70 | } else | |
71 | eb->and = -args->buffer_count; | |
72 | ||
bcffc3fa | 73 | INIT_LIST_HEAD(&eb->objects); |
67731b87 CW |
74 | return eb; |
75 | } | |
76 | ||
77 | static void | |
78 | eb_reset(struct eb_objects *eb) | |
79 | { | |
eef90ccb CW |
80 | if (eb->and >= 0) |
81 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
82 | } |
83 | ||
3b96eff4 CW |
84 | static int |
85 | eb_lookup_objects(struct eb_objects *eb, | |
86 | struct drm_i915_gem_exec_object2 *exec, | |
eef90ccb | 87 | const struct drm_i915_gem_execbuffer2 *args, |
bcffc3fa | 88 | struct drm_file *file) |
3b96eff4 CW |
89 | { |
90 | int i; | |
91 | ||
92 | spin_lock(&file->table_lock); | |
eef90ccb | 93 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
94 | struct drm_i915_gem_object *obj; |
95 | ||
96 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); | |
97 | if (obj == NULL) { | |
98 | spin_unlock(&file->table_lock); | |
99 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
100 | exec[i].handle, i); | |
101 | return -ENOENT; | |
102 | } | |
103 | ||
104 | if (!list_empty(&obj->exec_list)) { | |
105 | spin_unlock(&file->table_lock); | |
106 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
107 | obj, exec[i].handle, i); | |
108 | return -EINVAL; | |
109 | } | |
110 | ||
111 | drm_gem_object_reference(&obj->base); | |
bcffc3fa | 112 | list_add_tail(&obj->exec_list, &eb->objects); |
3b96eff4 | 113 | |
3b96eff4 | 114 | obj->exec_entry = &exec[i]; |
eef90ccb CW |
115 | if (eb->and < 0) { |
116 | eb->lut[i] = obj; | |
117 | } else { | |
118 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
119 | obj->exec_handle = handle; | |
120 | hlist_add_head(&obj->exec_node, | |
121 | &eb->buckets[handle & eb->and]); | |
122 | } | |
3b96eff4 CW |
123 | } |
124 | spin_unlock(&file->table_lock); | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
67731b87 CW |
129 | static struct drm_i915_gem_object * |
130 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
131 | { | |
eef90ccb CW |
132 | if (eb->and < 0) { |
133 | if (handle >= -eb->and) | |
134 | return NULL; | |
135 | return eb->lut[handle]; | |
136 | } else { | |
137 | struct hlist_head *head; | |
138 | struct hlist_node *node; | |
67731b87 | 139 | |
eef90ccb CW |
140 | head = &eb->buckets[handle & eb->and]; |
141 | hlist_for_each(node, head) { | |
142 | struct drm_i915_gem_object *obj; | |
67731b87 | 143 | |
eef90ccb CW |
144 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); |
145 | if (obj->exec_handle == handle) | |
146 | return obj; | |
147 | } | |
148 | return NULL; | |
149 | } | |
67731b87 CW |
150 | } |
151 | ||
152 | static void | |
153 | eb_destroy(struct eb_objects *eb) | |
154 | { | |
bcffc3fa CW |
155 | while (!list_empty(&eb->objects)) { |
156 | struct drm_i915_gem_object *obj; | |
157 | ||
158 | obj = list_first_entry(&eb->objects, | |
159 | struct drm_i915_gem_object, | |
160 | exec_list); | |
161 | list_del_init(&obj->exec_list); | |
162 | drm_gem_object_unreference(&obj->base); | |
163 | } | |
67731b87 CW |
164 | kfree(eb); |
165 | } | |
166 | ||
dabdfe02 CW |
167 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
168 | { | |
169 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 170 | !obj->map_and_fenceable || |
dabdfe02 CW |
171 | obj->cache_level != I915_CACHE_NONE); |
172 | } | |
173 | ||
54cf91dc CW |
174 | static int |
175 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 176 | struct eb_objects *eb, |
54cf91dc CW |
177 | struct drm_i915_gem_relocation_entry *reloc) |
178 | { | |
179 | struct drm_device *dev = obj->base.dev; | |
180 | struct drm_gem_object *target_obj; | |
149c8407 | 181 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
182 | uint32_t target_offset; |
183 | int ret = -EINVAL; | |
184 | ||
67731b87 CW |
185 | /* we've already hold a reference to all valid objects */ |
186 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
187 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
188 | return -ENOENT; |
189 | ||
149c8407 | 190 | target_i915_obj = to_intel_bo(target_obj); |
f343c5f6 | 191 | target_offset = i915_gem_obj_ggtt_offset(target_i915_obj); |
54cf91dc | 192 | |
e844b990 EA |
193 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
194 | * pipe_control writes because the gpu doesn't properly redirect them | |
195 | * through the ppgtt for non_secure batchbuffers. */ | |
196 | if (unlikely(IS_GEN6(dev) && | |
197 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
198 | !target_i915_obj->has_global_gtt_mapping)) { | |
199 | i915_gem_gtt_bind_object(target_i915_obj, | |
200 | target_i915_obj->cache_level); | |
201 | } | |
202 | ||
54cf91dc | 203 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 204 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 205 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
206 | "obj %p target %d offset %d " |
207 | "read %08x write %08x", | |
208 | obj, reloc->target_handle, | |
209 | (int) reloc->offset, | |
210 | reloc->read_domains, | |
211 | reloc->write_domain); | |
67731b87 | 212 | return ret; |
54cf91dc | 213 | } |
4ca4a250 DV |
214 | if (unlikely((reloc->write_domain | reloc->read_domains) |
215 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 216 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
217 | "obj %p target %d offset %d " |
218 | "read %08x write %08x", | |
219 | obj, reloc->target_handle, | |
220 | (int) reloc->offset, | |
221 | reloc->read_domains, | |
222 | reloc->write_domain); | |
67731b87 | 223 | return ret; |
54cf91dc | 224 | } |
54cf91dc CW |
225 | |
226 | target_obj->pending_read_domains |= reloc->read_domains; | |
227 | target_obj->pending_write_domain |= reloc->write_domain; | |
228 | ||
229 | /* If the relocation already has the right value in it, no | |
230 | * more work needs to be done. | |
231 | */ | |
232 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 233 | return 0; |
54cf91dc CW |
234 | |
235 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 236 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 237 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
238 | "obj %p target %d offset %d size %d.\n", |
239 | obj, reloc->target_handle, | |
240 | (int) reloc->offset, | |
241 | (int) obj->base.size); | |
67731b87 | 242 | return ret; |
54cf91dc | 243 | } |
b8f7ab17 | 244 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 245 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
246 | "obj %p target %d offset %d.\n", |
247 | obj, reloc->target_handle, | |
248 | (int) reloc->offset); | |
67731b87 | 249 | return ret; |
54cf91dc CW |
250 | } |
251 | ||
dabdfe02 CW |
252 | /* We can't wait for rendering with pagefaults disabled */ |
253 | if (obj->active && in_atomic()) | |
254 | return -EFAULT; | |
255 | ||
54cf91dc | 256 | reloc->delta += target_offset; |
dabdfe02 | 257 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
258 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
259 | char *vaddr; | |
260 | ||
dabdfe02 CW |
261 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
262 | if (ret) | |
263 | return ret; | |
264 | ||
9da3da66 CW |
265 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, |
266 | reloc->offset >> PAGE_SHIFT)); | |
54cf91dc CW |
267 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
268 | kunmap_atomic(vaddr); | |
269 | } else { | |
270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
271 | uint32_t __iomem *reloc_entry; | |
272 | void __iomem *reloc_page; | |
273 | ||
7b09638f CW |
274 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
275 | if (ret) | |
276 | return ret; | |
277 | ||
278 | ret = i915_gem_object_put_fence(obj); | |
54cf91dc | 279 | if (ret) |
67731b87 | 280 | return ret; |
54cf91dc CW |
281 | |
282 | /* Map the page containing the relocation we're going to perform. */ | |
f343c5f6 | 283 | reloc->offset += i915_gem_obj_ggtt_offset(obj); |
5d4545ae | 284 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
54cf91dc CW |
285 | reloc->offset & PAGE_MASK); |
286 | reloc_entry = (uint32_t __iomem *) | |
287 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
288 | iowrite32(reloc->delta, reloc_entry); | |
289 | io_mapping_unmap_atomic(reloc_page); | |
290 | } | |
291 | ||
292 | /* and update the user's relocation entry */ | |
293 | reloc->presumed_offset = target_offset; | |
294 | ||
67731b87 | 295 | return 0; |
54cf91dc CW |
296 | } |
297 | ||
298 | static int | |
299 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 300 | struct eb_objects *eb) |
54cf91dc | 301 | { |
1d83f442 CW |
302 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
303 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 304 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 305 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 306 | int remain, ret; |
54cf91dc | 307 | |
2bb4629a | 308 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 309 | |
1d83f442 CW |
310 | remain = entry->relocation_count; |
311 | while (remain) { | |
312 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
313 | int count = remain; | |
314 | if (count > ARRAY_SIZE(stack_reloc)) | |
315 | count = ARRAY_SIZE(stack_reloc); | |
316 | remain -= count; | |
317 | ||
318 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
319 | return -EFAULT; |
320 | ||
1d83f442 CW |
321 | do { |
322 | u64 offset = r->presumed_offset; | |
54cf91dc | 323 | |
1d83f442 CW |
324 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
325 | if (ret) | |
326 | return ret; | |
327 | ||
328 | if (r->presumed_offset != offset && | |
329 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
330 | &r->presumed_offset, | |
331 | sizeof(r->presumed_offset))) { | |
332 | return -EFAULT; | |
333 | } | |
334 | ||
335 | user_relocs++; | |
336 | r++; | |
337 | } while (--count); | |
54cf91dc CW |
338 | } |
339 | ||
340 | return 0; | |
1d83f442 | 341 | #undef N_RELOC |
54cf91dc CW |
342 | } |
343 | ||
344 | static int | |
345 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 346 | struct eb_objects *eb, |
54cf91dc CW |
347 | struct drm_i915_gem_relocation_entry *relocs) |
348 | { | |
6fe4f140 | 349 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
350 | int i, ret; |
351 | ||
352 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 353 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
354 | if (ret) |
355 | return ret; | |
356 | } | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | static int | |
41fda596 | 362 | i915_gem_execbuffer_relocate(struct eb_objects *eb) |
54cf91dc | 363 | { |
432e58ed | 364 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
365 | int ret = 0; |
366 | ||
367 | /* This is the fast path and we cannot handle a pagefault whilst | |
368 | * holding the struct mutex lest the user pass in the relocations | |
369 | * contained within a mmaped bo. For in such a case we, the page | |
370 | * fault handler would call i915_gem_fault() and we would try to | |
371 | * acquire the struct mutex again. Obviously this is bad and so | |
372 | * lockdep complains vehemently. | |
373 | */ | |
374 | pagefault_disable(); | |
bcffc3fa | 375 | list_for_each_entry(obj, &eb->objects, exec_list) { |
6fe4f140 | 376 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 377 | if (ret) |
d4aeee77 | 378 | break; |
54cf91dc | 379 | } |
d4aeee77 | 380 | pagefault_enable(); |
54cf91dc | 381 | |
d4aeee77 | 382 | return ret; |
54cf91dc CW |
383 | } |
384 | ||
7788a765 CW |
385 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
386 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
1690e1eb | 387 | |
dabdfe02 CW |
388 | static int |
389 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
390 | { | |
391 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
392 | return entry->relocation_count && !use_cpu_reloc(obj); | |
393 | } | |
394 | ||
1690e1eb | 395 | static int |
7788a765 | 396 | i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj, |
ed5982e6 DV |
397 | struct intel_ring_buffer *ring, |
398 | bool *need_reloc) | |
1690e1eb | 399 | { |
7788a765 | 400 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1690e1eb CW |
401 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
402 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
403 | bool need_fence, need_mappable; | |
404 | int ret; | |
405 | ||
406 | need_fence = | |
407 | has_fenced_gpu_access && | |
408 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
409 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 410 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb | 411 | |
86a1ee26 | 412 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false); |
1690e1eb CW |
413 | if (ret) |
414 | return ret; | |
415 | ||
7788a765 CW |
416 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
417 | ||
1690e1eb CW |
418 | if (has_fenced_gpu_access) { |
419 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 420 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 421 | if (ret) |
7788a765 | 422 | return ret; |
1690e1eb | 423 | |
9a5a53b3 | 424 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 425 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 426 | |
7dd49065 | 427 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 428 | } |
1690e1eb CW |
429 | } |
430 | ||
7788a765 CW |
431 | /* Ensure ppgtt mapping exists if needed */ |
432 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
433 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
434 | obj, obj->cache_level); | |
435 | ||
436 | obj->has_aliasing_ppgtt_mapping = 1; | |
437 | } | |
438 | ||
f343c5f6 BW |
439 | if (entry->offset != i915_gem_obj_ggtt_offset(obj)) { |
440 | entry->offset = i915_gem_obj_ggtt_offset(obj); | |
ed5982e6 DV |
441 | *need_reloc = true; |
442 | } | |
443 | ||
444 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
445 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
446 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
447 | } | |
448 | ||
449 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT && | |
450 | !obj->has_global_gtt_mapping) | |
451 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
452 | ||
1690e1eb | 453 | return 0; |
7788a765 | 454 | } |
1690e1eb | 455 | |
7788a765 CW |
456 | static void |
457 | i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj) | |
458 | { | |
459 | struct drm_i915_gem_exec_object2 *entry; | |
460 | ||
f343c5f6 | 461 | if (!i915_gem_obj_ggtt_bound(obj)) |
7788a765 CW |
462 | return; |
463 | ||
464 | entry = obj->exec_entry; | |
465 | ||
466 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
467 | i915_gem_object_unpin_fence(obj); | |
468 | ||
469 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
470 | i915_gem_object_unpin(obj); | |
471 | ||
472 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
1690e1eb CW |
473 | } |
474 | ||
54cf91dc | 475 | static int |
d9e86c0e | 476 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
ed5982e6 DV |
477 | struct list_head *objects, |
478 | bool *need_relocs) | |
54cf91dc | 479 | { |
432e58ed | 480 | struct drm_i915_gem_object *obj; |
6fe4f140 | 481 | struct list_head ordered_objects; |
7788a765 CW |
482 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
483 | int retry; | |
6fe4f140 CW |
484 | |
485 | INIT_LIST_HEAD(&ordered_objects); | |
486 | while (!list_empty(objects)) { | |
487 | struct drm_i915_gem_exec_object2 *entry; | |
488 | bool need_fence, need_mappable; | |
489 | ||
490 | obj = list_first_entry(objects, | |
491 | struct drm_i915_gem_object, | |
492 | exec_list); | |
493 | entry = obj->exec_entry; | |
494 | ||
495 | need_fence = | |
496 | has_fenced_gpu_access && | |
497 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
498 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 499 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
500 | |
501 | if (need_mappable) | |
502 | list_move(&obj->exec_list, &ordered_objects); | |
503 | else | |
504 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 | 505 | |
ed5982e6 | 506 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 507 | obj->base.pending_write_domain = 0; |
016fd0c1 | 508 | obj->pending_fenced_gpu_access = false; |
6fe4f140 CW |
509 | } |
510 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
511 | |
512 | /* Attempt to pin all of the buffers into the GTT. | |
513 | * This is done in 3 phases: | |
514 | * | |
515 | * 1a. Unbind all objects that do not match the GTT constraints for | |
516 | * the execbuffer (fenceable, mappable, alignment etc). | |
517 | * 1b. Increment pin count for already bound objects. | |
518 | * 2. Bind new objects. | |
519 | * 3. Decrement pin count. | |
520 | * | |
7788a765 | 521 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
522 | * room for the earlier objects *unless* we need to defragment. |
523 | */ | |
524 | retry = 0; | |
525 | do { | |
7788a765 | 526 | int ret = 0; |
54cf91dc CW |
527 | |
528 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 529 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 530 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 531 | bool need_fence, need_mappable; |
1690e1eb | 532 | |
f343c5f6 | 533 | if (!i915_gem_obj_ggtt_bound(obj)) |
54cf91dc CW |
534 | continue; |
535 | ||
536 | need_fence = | |
9b3826bf | 537 | has_fenced_gpu_access && |
54cf91dc CW |
538 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
539 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 540 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc | 541 | |
f343c5f6 BW |
542 | if ((entry->alignment && |
543 | i915_gem_obj_ggtt_offset(obj) & (entry->alignment - 1)) || | |
54cf91dc CW |
544 | (need_mappable && !obj->map_and_fenceable)) |
545 | ret = i915_gem_object_unbind(obj); | |
546 | else | |
ed5982e6 | 547 | ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs); |
432e58ed | 548 | if (ret) |
54cf91dc | 549 | goto err; |
54cf91dc CW |
550 | } |
551 | ||
552 | /* Bind fresh objects */ | |
432e58ed | 553 | list_for_each_entry(obj, objects, exec_list) { |
f343c5f6 | 554 | if (i915_gem_obj_ggtt_bound(obj)) |
1690e1eb | 555 | continue; |
54cf91dc | 556 | |
ed5982e6 | 557 | ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs); |
7788a765 CW |
558 | if (ret) |
559 | goto err; | |
54cf91dc CW |
560 | } |
561 | ||
7788a765 CW |
562 | err: /* Decrement pin count for bound objects */ |
563 | list_for_each_entry(obj, objects, exec_list) | |
564 | i915_gem_execbuffer_unreserve_object(obj); | |
54cf91dc | 565 | |
6c085a72 | 566 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
567 | return ret; |
568 | ||
6c085a72 | 569 | ret = i915_gem_evict_everything(ring->dev); |
54cf91dc CW |
570 | if (ret) |
571 | return ret; | |
54cf91dc CW |
572 | } while (1); |
573 | } | |
574 | ||
575 | static int | |
576 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 577 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 578 | struct drm_file *file, |
d9e86c0e | 579 | struct intel_ring_buffer *ring, |
67731b87 | 580 | struct eb_objects *eb, |
ed5982e6 | 581 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
582 | { |
583 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 584 | struct drm_i915_gem_object *obj; |
ed5982e6 | 585 | bool need_relocs; |
dd6864a4 | 586 | int *reloc_offset; |
54cf91dc | 587 | int i, total, ret; |
ed5982e6 | 588 | int count = args->buffer_count; |
54cf91dc | 589 | |
67731b87 | 590 | /* We may process another execbuffer during the unlock... */ |
bcffc3fa CW |
591 | while (!list_empty(&eb->objects)) { |
592 | obj = list_first_entry(&eb->objects, | |
67731b87 CW |
593 | struct drm_i915_gem_object, |
594 | exec_list); | |
595 | list_del_init(&obj->exec_list); | |
596 | drm_gem_object_unreference(&obj->base); | |
597 | } | |
598 | ||
54cf91dc CW |
599 | mutex_unlock(&dev->struct_mutex); |
600 | ||
601 | total = 0; | |
602 | for (i = 0; i < count; i++) | |
432e58ed | 603 | total += exec[i].relocation_count; |
54cf91dc | 604 | |
dd6864a4 | 605 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 606 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
607 | if (reloc == NULL || reloc_offset == NULL) { |
608 | drm_free_large(reloc); | |
609 | drm_free_large(reloc_offset); | |
54cf91dc CW |
610 | mutex_lock(&dev->struct_mutex); |
611 | return -ENOMEM; | |
612 | } | |
613 | ||
614 | total = 0; | |
615 | for (i = 0; i < count; i++) { | |
616 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
617 | u64 invalid_offset = (u64)-1; |
618 | int j; | |
54cf91dc | 619 | |
2bb4629a | 620 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
621 | |
622 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 623 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
624 | ret = -EFAULT; |
625 | mutex_lock(&dev->struct_mutex); | |
626 | goto err; | |
627 | } | |
628 | ||
262b6d36 CW |
629 | /* As we do not update the known relocation offsets after |
630 | * relocating (due to the complexities in lock handling), | |
631 | * we need to mark them as invalid now so that we force the | |
632 | * relocation processing next time. Just in case the target | |
633 | * object is evicted and then rebound into its old | |
634 | * presumed_offset before the next execbuffer - if that | |
635 | * happened we would make the mistake of assuming that the | |
636 | * relocations were valid. | |
637 | */ | |
638 | for (j = 0; j < exec[i].relocation_count; j++) { | |
639 | if (copy_to_user(&user_relocs[j].presumed_offset, | |
640 | &invalid_offset, | |
641 | sizeof(invalid_offset))) { | |
642 | ret = -EFAULT; | |
643 | mutex_lock(&dev->struct_mutex); | |
644 | goto err; | |
645 | } | |
646 | } | |
647 | ||
dd6864a4 | 648 | reloc_offset[i] = total; |
432e58ed | 649 | total += exec[i].relocation_count; |
54cf91dc CW |
650 | } |
651 | ||
652 | ret = i915_mutex_lock_interruptible(dev); | |
653 | if (ret) { | |
654 | mutex_lock(&dev->struct_mutex); | |
655 | goto err; | |
656 | } | |
657 | ||
67731b87 | 658 | /* reacquire the objects */ |
67731b87 | 659 | eb_reset(eb); |
eef90ccb | 660 | ret = eb_lookup_objects(eb, exec, args, file); |
3b96eff4 CW |
661 | if (ret) |
662 | goto err; | |
67731b87 | 663 | |
ed5982e6 | 664 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
cf144969 | 665 | ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs); |
54cf91dc CW |
666 | if (ret) |
667 | goto err; | |
668 | ||
bcffc3fa | 669 | list_for_each_entry(obj, &eb->objects, exec_list) { |
dd6864a4 | 670 | int offset = obj->exec_entry - exec; |
67731b87 | 671 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 672 | reloc + reloc_offset[offset]); |
54cf91dc CW |
673 | if (ret) |
674 | goto err; | |
54cf91dc CW |
675 | } |
676 | ||
677 | /* Leave the user relocations as are, this is the painfully slow path, | |
678 | * and we want to avoid the complication of dropping the lock whilst | |
679 | * having buffers reserved in the aperture and so causing spurious | |
680 | * ENOSPC for random operations. | |
681 | */ | |
682 | ||
683 | err: | |
684 | drm_free_large(reloc); | |
dd6864a4 | 685 | drm_free_large(reloc_offset); |
54cf91dc CW |
686 | return ret; |
687 | } | |
688 | ||
54cf91dc | 689 | static int |
432e58ed CW |
690 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
691 | struct list_head *objects) | |
54cf91dc | 692 | { |
432e58ed | 693 | struct drm_i915_gem_object *obj; |
6ac42f41 | 694 | uint32_t flush_domains = 0; |
432e58ed | 695 | int ret; |
54cf91dc | 696 | |
6ac42f41 DV |
697 | list_for_each_entry(obj, objects, exec_list) { |
698 | ret = i915_gem_object_sync(obj, ring); | |
c59a333f CW |
699 | if (ret) |
700 | return ret; | |
6ac42f41 DV |
701 | |
702 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
703 | i915_gem_clflush_object(obj); | |
704 | ||
6ac42f41 | 705 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
706 | } |
707 | ||
6ac42f41 | 708 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
e76e9aeb | 709 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
710 | |
711 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
712 | wmb(); | |
713 | ||
09cf7c9a CW |
714 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
715 | * any residual writes from the previous batch. | |
716 | */ | |
a7b9761d | 717 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
718 | } |
719 | ||
432e58ed CW |
720 | static bool |
721 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 722 | { |
ed5982e6 DV |
723 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
724 | return false; | |
725 | ||
432e58ed | 726 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
727 | } |
728 | ||
729 | static int | |
730 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
731 | int count) | |
732 | { | |
733 | int i; | |
3118a4f6 KC |
734 | int relocs_total = 0; |
735 | int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
54cf91dc CW |
736 | |
737 | for (i = 0; i < count; i++) { | |
2bb4629a | 738 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
739 | int length; /* limited by fault_in_pages_readable() */ |
740 | ||
ed5982e6 DV |
741 | if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS) |
742 | return -EINVAL; | |
743 | ||
3118a4f6 KC |
744 | /* First check for malicious input causing overflow in |
745 | * the worst case where we need to allocate the entire | |
746 | * relocation tree as a single array. | |
747 | */ | |
748 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 749 | return -EINVAL; |
3118a4f6 | 750 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
751 | |
752 | length = exec[i].relocation_count * | |
753 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
754 | /* |
755 | * We must check that the entire relocation array is safe | |
756 | * to read, but since we may need to update the presumed | |
757 | * offsets during execution, check for full write access. | |
758 | */ | |
54cf91dc CW |
759 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
760 | return -EFAULT; | |
761 | ||
f56f821f | 762 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
763 | return -EFAULT; |
764 | } | |
765 | ||
766 | return 0; | |
767 | } | |
768 | ||
432e58ed CW |
769 | static void |
770 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
9d773091 | 771 | struct intel_ring_buffer *ring) |
432e58ed CW |
772 | { |
773 | struct drm_i915_gem_object *obj; | |
774 | ||
775 | list_for_each_entry(obj, objects, exec_list) { | |
69c2fc89 CW |
776 | u32 old_read = obj->base.read_domains; |
777 | u32 old_write = obj->base.write_domain; | |
db53a302 | 778 | |
432e58ed | 779 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
780 | if (obj->base.write_domain == 0) |
781 | obj->base.pending_read_domains |= obj->base.read_domains; | |
782 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed CW |
783 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
784 | ||
9d773091 | 785 | i915_gem_object_move_to_active(obj, ring); |
432e58ed CW |
786 | if (obj->base.write_domain) { |
787 | obj->dirty = 1; | |
9d773091 | 788 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
acb87dfb | 789 | if (obj->pin_count) /* check for potential scanout */ |
c65355bb | 790 | intel_mark_fb_busy(obj, ring); |
432e58ed CW |
791 | } |
792 | ||
db53a302 | 793 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
794 | } |
795 | } | |
796 | ||
54cf91dc CW |
797 | static void |
798 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 799 | struct drm_file *file, |
7d736f4f MK |
800 | struct intel_ring_buffer *ring, |
801 | struct drm_i915_gem_object *obj) | |
54cf91dc | 802 | { |
cc889e0f DV |
803 | /* Unconditionally force add_request to emit a full flush. */ |
804 | ring->gpu_caches_dirty = true; | |
54cf91dc | 805 | |
432e58ed | 806 | /* Add a breadcrumb for the completion of the batch buffer */ |
7d736f4f | 807 | (void)__i915_add_request(ring, file, obj, NULL); |
432e58ed | 808 | } |
54cf91dc | 809 | |
ae662d31 EA |
810 | static int |
811 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
812 | struct intel_ring_buffer *ring) | |
813 | { | |
814 | drm_i915_private_t *dev_priv = dev->dev_private; | |
815 | int ret, i; | |
816 | ||
817 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
818 | return 0; | |
819 | ||
820 | ret = intel_ring_begin(ring, 4 * 3); | |
821 | if (ret) | |
822 | return ret; | |
823 | ||
824 | for (i = 0; i < 4; i++) { | |
825 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
826 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
827 | intel_ring_emit(ring, 0); | |
828 | } | |
829 | ||
830 | intel_ring_advance(ring); | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
54cf91dc CW |
835 | static int |
836 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
837 | struct drm_file *file, | |
838 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 839 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
840 | { |
841 | drm_i915_private_t *dev_priv = dev->dev_private; | |
67731b87 | 842 | struct eb_objects *eb; |
54cf91dc CW |
843 | struct drm_i915_gem_object *batch_obj; |
844 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 845 | struct intel_ring_buffer *ring; |
6e0a69db | 846 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 847 | u32 exec_start, exec_len; |
ed5982e6 | 848 | u32 mask, flags; |
72bfa19c | 849 | int ret, mode, i; |
ed5982e6 | 850 | bool need_relocs; |
54cf91dc | 851 | |
ed5982e6 | 852 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 853 | return -EINVAL; |
432e58ed CW |
854 | |
855 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
856 | if (ret) |
857 | return ret; | |
858 | ||
d7d4eedd CW |
859 | flags = 0; |
860 | if (args->flags & I915_EXEC_SECURE) { | |
861 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
862 | return -EPERM; | |
863 | ||
864 | flags |= I915_DISPATCH_SECURE; | |
865 | } | |
b45305fc DV |
866 | if (args->flags & I915_EXEC_IS_PINNED) |
867 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 868 | |
54cf91dc CW |
869 | switch (args->flags & I915_EXEC_RING_MASK) { |
870 | case I915_EXEC_DEFAULT: | |
871 | case I915_EXEC_RENDER: | |
1ec14ad3 | 872 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
873 | break; |
874 | case I915_EXEC_BSD: | |
1ec14ad3 | 875 | ring = &dev_priv->ring[VCS]; |
6e0a69db BW |
876 | if (ctx_id != 0) { |
877 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
878 | ring->name); | |
879 | return -EPERM; | |
880 | } | |
54cf91dc CW |
881 | break; |
882 | case I915_EXEC_BLT: | |
1ec14ad3 | 883 | ring = &dev_priv->ring[BCS]; |
6e0a69db BW |
884 | if (ctx_id != 0) { |
885 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
886 | ring->name); | |
887 | return -EPERM; | |
888 | } | |
54cf91dc | 889 | break; |
82f91b6e XH |
890 | case I915_EXEC_VEBOX: |
891 | ring = &dev_priv->ring[VECS]; | |
892 | if (ctx_id != 0) { | |
893 | DRM_DEBUG("Ring %s doesn't support contexts\n", | |
894 | ring->name); | |
895 | return -EPERM; | |
896 | } | |
897 | break; | |
898 | ||
54cf91dc | 899 | default: |
ff240199 | 900 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
901 | (int)(args->flags & I915_EXEC_RING_MASK)); |
902 | return -EINVAL; | |
903 | } | |
a15817cf CW |
904 | if (!intel_ring_initialized(ring)) { |
905 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
906 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
907 | return -EINVAL; | |
908 | } | |
54cf91dc | 909 | |
72bfa19c | 910 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 911 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
912 | switch (mode) { |
913 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
914 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
915 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
916 | if (ring == &dev_priv->ring[RCS] && | |
917 | mode != dev_priv->relative_constants_mode) { | |
918 | if (INTEL_INFO(dev)->gen < 4) | |
919 | return -EINVAL; | |
920 | ||
921 | if (INTEL_INFO(dev)->gen > 5 && | |
922 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
923 | return -EINVAL; | |
84f9f938 BW |
924 | |
925 | /* The HW changed the meaning on this bit on gen6 */ | |
926 | if (INTEL_INFO(dev)->gen >= 6) | |
927 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
928 | } |
929 | break; | |
930 | default: | |
ff240199 | 931 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
932 | return -EINVAL; |
933 | } | |
934 | ||
54cf91dc | 935 | if (args->buffer_count < 1) { |
ff240199 | 936 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
937 | return -EINVAL; |
938 | } | |
54cf91dc CW |
939 | |
940 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 941 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 942 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
943 | return -EINVAL; |
944 | } | |
945 | ||
6ebebc92 DV |
946 | if (INTEL_INFO(dev)->gen >= 5) { |
947 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
948 | return -EINVAL; | |
949 | } | |
950 | ||
44afb3a0 XW |
951 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
952 | DRM_DEBUG("execbuf with %u cliprects\n", | |
953 | args->num_cliprects); | |
954 | return -EINVAL; | |
955 | } | |
5e13a0c5 | 956 | |
432e58ed | 957 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
958 | GFP_KERNEL); |
959 | if (cliprects == NULL) { | |
960 | ret = -ENOMEM; | |
961 | goto pre_mutex_err; | |
962 | } | |
963 | ||
432e58ed | 964 | if (copy_from_user(cliprects, |
2bb4629a VS |
965 | to_user_ptr(args->cliprects_ptr), |
966 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
967 | ret = -EFAULT; |
968 | goto pre_mutex_err; | |
969 | } | |
970 | } | |
971 | ||
54cf91dc CW |
972 | ret = i915_mutex_lock_interruptible(dev); |
973 | if (ret) | |
974 | goto pre_mutex_err; | |
975 | ||
976 | if (dev_priv->mm.suspended) { | |
977 | mutex_unlock(&dev->struct_mutex); | |
978 | ret = -EBUSY; | |
979 | goto pre_mutex_err; | |
980 | } | |
981 | ||
eef90ccb | 982 | eb = eb_create(args); |
67731b87 CW |
983 | if (eb == NULL) { |
984 | mutex_unlock(&dev->struct_mutex); | |
985 | ret = -ENOMEM; | |
986 | goto pre_mutex_err; | |
987 | } | |
988 | ||
54cf91dc | 989 | /* Look up object handles */ |
eef90ccb | 990 | ret = eb_lookup_objects(eb, exec, args, file); |
3b96eff4 CW |
991 | if (ret) |
992 | goto err; | |
54cf91dc | 993 | |
6fe4f140 | 994 | /* take note of the batch buffer before we might reorder the lists */ |
bcffc3fa | 995 | batch_obj = list_entry(eb->objects.prev, |
6fe4f140 CW |
996 | struct drm_i915_gem_object, |
997 | exec_list); | |
998 | ||
54cf91dc | 999 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1000 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
cf144969 | 1001 | ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs); |
54cf91dc CW |
1002 | if (ret) |
1003 | goto err; | |
1004 | ||
1005 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1006 | if (need_relocs) |
41fda596 | 1007 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1008 | if (ret) { |
1009 | if (ret == -EFAULT) { | |
ed5982e6 DV |
1010 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
1011 | eb, exec); | |
54cf91dc CW |
1012 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1013 | } | |
1014 | if (ret) | |
1015 | goto err; | |
1016 | } | |
1017 | ||
1018 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1019 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1020 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1021 | ret = -EINVAL; |
1022 | goto err; | |
1023 | } | |
1024 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1025 | ||
d7d4eedd CW |
1026 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1027 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
1028 | * hsw should have this fixed, but let's be paranoid and do it | |
1029 | * unconditionally for now. */ | |
1030 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) | |
1031 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); | |
1032 | ||
bcffc3fa | 1033 | ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects); |
432e58ed | 1034 | if (ret) |
54cf91dc | 1035 | goto err; |
54cf91dc | 1036 | |
0da5cec1 EA |
1037 | ret = i915_switch_context(ring, file, ctx_id); |
1038 | if (ret) | |
1039 | goto err; | |
1040 | ||
e2971bda BW |
1041 | if (ring == &dev_priv->ring[RCS] && |
1042 | mode != dev_priv->relative_constants_mode) { | |
1043 | ret = intel_ring_begin(ring, 4); | |
1044 | if (ret) | |
1045 | goto err; | |
1046 | ||
1047 | intel_ring_emit(ring, MI_NOOP); | |
1048 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1049 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1050 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1051 | intel_ring_advance(ring); |
1052 | ||
1053 | dev_priv->relative_constants_mode = mode; | |
1054 | } | |
1055 | ||
ae662d31 EA |
1056 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1057 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1058 | if (ret) | |
1059 | goto err; | |
1060 | } | |
1061 | ||
f343c5f6 | 1062 | exec_start = i915_gem_obj_ggtt_offset(batch_obj) + args->batch_start_offset; |
c4e7a414 CW |
1063 | exec_len = args->batch_len; |
1064 | if (cliprects) { | |
1065 | for (i = 0; i < args->num_cliprects; i++) { | |
1066 | ret = i915_emit_box(dev, &cliprects[i], | |
1067 | args->DR1, args->DR4); | |
1068 | if (ret) | |
1069 | goto err; | |
1070 | ||
1071 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1072 | exec_start, exec_len, |
1073 | flags); | |
c4e7a414 CW |
1074 | if (ret) |
1075 | goto err; | |
1076 | } | |
1077 | } else { | |
d7d4eedd CW |
1078 | ret = ring->dispatch_execbuffer(ring, |
1079 | exec_start, exec_len, | |
1080 | flags); | |
c4e7a414 CW |
1081 | if (ret) |
1082 | goto err; | |
1083 | } | |
54cf91dc | 1084 | |
9d773091 CW |
1085 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
1086 | ||
bcffc3fa | 1087 | i915_gem_execbuffer_move_to_active(&eb->objects, ring); |
7d736f4f | 1088 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
54cf91dc CW |
1089 | |
1090 | err: | |
67731b87 | 1091 | eb_destroy(eb); |
54cf91dc CW |
1092 | |
1093 | mutex_unlock(&dev->struct_mutex); | |
1094 | ||
1095 | pre_mutex_err: | |
54cf91dc | 1096 | kfree(cliprects); |
54cf91dc CW |
1097 | return ret; |
1098 | } | |
1099 | ||
1100 | /* | |
1101 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1102 | * list array and passes it to the real function. | |
1103 | */ | |
1104 | int | |
1105 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1106 | struct drm_file *file) | |
1107 | { | |
1108 | struct drm_i915_gem_execbuffer *args = data; | |
1109 | struct drm_i915_gem_execbuffer2 exec2; | |
1110 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1111 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1112 | int ret, i; | |
1113 | ||
54cf91dc | 1114 | if (args->buffer_count < 1) { |
ff240199 | 1115 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1116 | return -EINVAL; |
1117 | } | |
1118 | ||
1119 | /* Copy in the exec list from userland */ | |
1120 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1121 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1122 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1123 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1124 | args->buffer_count); |
1125 | drm_free_large(exec_list); | |
1126 | drm_free_large(exec2_list); | |
1127 | return -ENOMEM; | |
1128 | } | |
1129 | ret = copy_from_user(exec_list, | |
2bb4629a | 1130 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1131 | sizeof(*exec_list) * args->buffer_count); |
1132 | if (ret != 0) { | |
ff240199 | 1133 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1134 | args->buffer_count, ret); |
1135 | drm_free_large(exec_list); | |
1136 | drm_free_large(exec2_list); | |
1137 | return -EFAULT; | |
1138 | } | |
1139 | ||
1140 | for (i = 0; i < args->buffer_count; i++) { | |
1141 | exec2_list[i].handle = exec_list[i].handle; | |
1142 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1143 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1144 | exec2_list[i].alignment = exec_list[i].alignment; | |
1145 | exec2_list[i].offset = exec_list[i].offset; | |
1146 | if (INTEL_INFO(dev)->gen < 4) | |
1147 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1148 | else | |
1149 | exec2_list[i].flags = 0; | |
1150 | } | |
1151 | ||
1152 | exec2.buffers_ptr = args->buffers_ptr; | |
1153 | exec2.buffer_count = args->buffer_count; | |
1154 | exec2.batch_start_offset = args->batch_start_offset; | |
1155 | exec2.batch_len = args->batch_len; | |
1156 | exec2.DR1 = args->DR1; | |
1157 | exec2.DR4 = args->DR4; | |
1158 | exec2.num_cliprects = args->num_cliprects; | |
1159 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1160 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1161 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc CW |
1162 | |
1163 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1164 | if (!ret) { | |
1165 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1166 | for (i = 0; i < args->buffer_count; i++) | |
1167 | exec_list[i].offset = exec2_list[i].offset; | |
1168 | /* ... and back out to userspace */ | |
2bb4629a | 1169 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1170 | exec_list, |
1171 | sizeof(*exec_list) * args->buffer_count); | |
1172 | if (ret) { | |
1173 | ret = -EFAULT; | |
ff240199 | 1174 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1175 | "back to user (%d)\n", |
1176 | args->buffer_count, ret); | |
1177 | } | |
1178 | } | |
1179 | ||
1180 | drm_free_large(exec_list); | |
1181 | drm_free_large(exec2_list); | |
1182 | return ret; | |
1183 | } | |
1184 | ||
1185 | int | |
1186 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1187 | struct drm_file *file) | |
1188 | { | |
1189 | struct drm_i915_gem_execbuffer2 *args = data; | |
1190 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1191 | int ret; | |
1192 | ||
ed8cd3b2 XW |
1193 | if (args->buffer_count < 1 || |
1194 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1195 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1196 | return -EINVAL; |
1197 | } | |
1198 | ||
8408c282 | 1199 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1200 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1201 | if (exec2_list == NULL) |
1202 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1203 | args->buffer_count); | |
54cf91dc | 1204 | if (exec2_list == NULL) { |
ff240199 | 1205 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1206 | args->buffer_count); |
1207 | return -ENOMEM; | |
1208 | } | |
1209 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1210 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1211 | sizeof(*exec2_list) * args->buffer_count); |
1212 | if (ret != 0) { | |
ff240199 | 1213 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1214 | args->buffer_count, ret); |
1215 | drm_free_large(exec2_list); | |
1216 | return -EFAULT; | |
1217 | } | |
1218 | ||
1219 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1220 | if (!ret) { | |
1221 | /* Copy the new buffer offsets back to the user's exec list. */ | |
2bb4629a | 1222 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1223 | exec2_list, |
1224 | sizeof(*exec2_list) * args->buffer_count); | |
1225 | if (ret) { | |
1226 | ret = -EFAULT; | |
ff240199 | 1227 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1228 | "back to user (%d)\n", |
1229 | args->buffer_count, ret); | |
1230 | } | |
1231 | } | |
1232 | ||
1233 | drm_free_large(exec2_list); | |
1234 | return ret; | |
1235 | } |