Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
27173f1f BW |
36 | struct eb_vmas { |
37 | struct list_head vmas; | |
67731b87 | 38 | int and; |
eef90ccb | 39 | union { |
27173f1f | 40 | struct i915_vma *lut[0]; |
eef90ccb CW |
41 | struct hlist_head buckets[0]; |
42 | }; | |
67731b87 CW |
43 | }; |
44 | ||
27173f1f BW |
45 | static struct eb_vmas * |
46 | eb_create(struct drm_i915_gem_execbuffer2 *args, struct i915_address_space *vm) | |
67731b87 | 47 | { |
27173f1f | 48 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
49 | |
50 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
51 | int size = args->buffer_count; | |
27173f1f BW |
52 | size *= sizeof(struct i915_vma *); |
53 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
54 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
55 | } | |
56 | ||
57 | if (eb == NULL) { | |
58 | int size = args->buffer_count; | |
59 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 60 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
61 | while (count > 2*size) |
62 | count >>= 1; | |
63 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 64 | sizeof(struct eb_vmas), |
eef90ccb CW |
65 | GFP_TEMPORARY); |
66 | if (eb == NULL) | |
67 | return eb; | |
68 | ||
69 | eb->and = count - 1; | |
70 | } else | |
71 | eb->and = -args->buffer_count; | |
72 | ||
27173f1f | 73 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
74 | return eb; |
75 | } | |
76 | ||
77 | static void | |
27173f1f | 78 | eb_reset(struct eb_vmas *eb) |
67731b87 | 79 | { |
eef90ccb CW |
80 | if (eb->and >= 0) |
81 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
82 | } |
83 | ||
3b96eff4 | 84 | static int |
27173f1f BW |
85 | eb_lookup_vmas(struct eb_vmas *eb, |
86 | struct drm_i915_gem_exec_object2 *exec, | |
87 | const struct drm_i915_gem_execbuffer2 *args, | |
88 | struct i915_address_space *vm, | |
89 | struct drm_file *file) | |
3b96eff4 | 90 | { |
27173f1f BW |
91 | struct drm_i915_gem_object *obj; |
92 | struct list_head objects; | |
93 | int i, ret = 0; | |
3b96eff4 | 94 | |
27173f1f | 95 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 96 | spin_lock(&file->table_lock); |
27173f1f BW |
97 | /* Grab a reference to the object and release the lock so we can lookup |
98 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 99 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
100 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
101 | if (obj == NULL) { | |
102 | spin_unlock(&file->table_lock); | |
103 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
104 | exec[i].handle, i); | |
27173f1f BW |
105 | ret = -ENOENT; |
106 | goto out; | |
3b96eff4 CW |
107 | } |
108 | ||
27173f1f | 109 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
110 | spin_unlock(&file->table_lock); |
111 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
112 | obj, exec[i].handle, i); | |
27173f1f BW |
113 | ret = -EINVAL; |
114 | goto out; | |
3b96eff4 CW |
115 | } |
116 | ||
117 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
118 | list_add_tail(&obj->obj_exec_link, &objects); |
119 | } | |
120 | spin_unlock(&file->table_lock); | |
3b96eff4 | 121 | |
27173f1f BW |
122 | i = 0; |
123 | list_for_each_entry(obj, &objects, obj_exec_link) { | |
124 | struct i915_vma *vma; | |
125 | ||
e656a6cb DV |
126 | /* |
127 | * NOTE: We can leak any vmas created here when something fails | |
128 | * later on. But that's no issue since vma_unbind can deal with | |
129 | * vmas which are not actually bound. And since only | |
130 | * lookup_or_create exists as an interface to get at the vma | |
131 | * from the (obj, vm) we don't run the risk of creating | |
132 | * duplicated vmas for the same vm. | |
133 | */ | |
27173f1f BW |
134 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
135 | if (IS_ERR(vma)) { | |
27173f1f BW |
136 | DRM_DEBUG("Failed to lookup VMA\n"); |
137 | ret = PTR_ERR(vma); | |
138 | goto out; | |
139 | } | |
140 | ||
141 | list_add_tail(&vma->exec_list, &eb->vmas); | |
142 | ||
143 | vma->exec_entry = &exec[i]; | |
eef90ccb | 144 | if (eb->and < 0) { |
27173f1f | 145 | eb->lut[i] = vma; |
eef90ccb CW |
146 | } else { |
147 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
148 | vma->exec_handle = handle; |
149 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
150 | &eb->buckets[handle & eb->and]); |
151 | } | |
27173f1f | 152 | ++i; |
3b96eff4 | 153 | } |
3b96eff4 | 154 | |
27173f1f BW |
155 | |
156 | out: | |
157 | while (!list_empty(&objects)) { | |
158 | obj = list_first_entry(&objects, | |
159 | struct drm_i915_gem_object, | |
160 | obj_exec_link); | |
161 | list_del_init(&obj->obj_exec_link); | |
162 | if (ret) | |
163 | drm_gem_object_unreference(&obj->base); | |
164 | } | |
165 | return ret; | |
3b96eff4 CW |
166 | } |
167 | ||
27173f1f | 168 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 169 | { |
eef90ccb CW |
170 | if (eb->and < 0) { |
171 | if (handle >= -eb->and) | |
172 | return NULL; | |
173 | return eb->lut[handle]; | |
174 | } else { | |
175 | struct hlist_head *head; | |
176 | struct hlist_node *node; | |
67731b87 | 177 | |
eef90ccb CW |
178 | head = &eb->buckets[handle & eb->and]; |
179 | hlist_for_each(node, head) { | |
27173f1f | 180 | struct i915_vma *vma; |
67731b87 | 181 | |
27173f1f BW |
182 | vma = hlist_entry(node, struct i915_vma, exec_node); |
183 | if (vma->exec_handle == handle) | |
184 | return vma; | |
eef90ccb CW |
185 | } |
186 | return NULL; | |
187 | } | |
67731b87 CW |
188 | } |
189 | ||
27173f1f BW |
190 | static void eb_destroy(struct eb_vmas *eb) { |
191 | while (!list_empty(&eb->vmas)) { | |
192 | struct i915_vma *vma; | |
bcffc3fa | 193 | |
27173f1f BW |
194 | vma = list_first_entry(&eb->vmas, |
195 | struct i915_vma, | |
bcffc3fa | 196 | exec_list); |
27173f1f BW |
197 | list_del_init(&vma->exec_list); |
198 | drm_gem_object_unreference(&vma->obj->base); | |
bcffc3fa | 199 | } |
67731b87 CW |
200 | kfree(eb); |
201 | } | |
202 | ||
dabdfe02 CW |
203 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
204 | { | |
2cc86b82 CW |
205 | return (HAS_LLC(obj->base.dev) || |
206 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 207 | !obj->map_and_fenceable || |
dabdfe02 CW |
208 | obj->cache_level != I915_CACHE_NONE); |
209 | } | |
210 | ||
5032d871 RB |
211 | static int |
212 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
213 | struct drm_i915_gem_relocation_entry *reloc) | |
214 | { | |
215 | uint32_t page_offset = offset_in_page(reloc->offset); | |
216 | char *vaddr; | |
217 | int ret = -EINVAL; | |
218 | ||
2cc86b82 | 219 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
220 | if (ret) |
221 | return ret; | |
222 | ||
223 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
224 | reloc->offset >> PAGE_SHIFT)); | |
225 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
226 | kunmap_atomic(vaddr); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | static int | |
232 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
233 | struct drm_i915_gem_relocation_entry *reloc) | |
234 | { | |
235 | struct drm_device *dev = obj->base.dev; | |
236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
237 | uint32_t __iomem *reloc_entry; | |
238 | void __iomem *reloc_page; | |
239 | int ret = -EINVAL; | |
240 | ||
241 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
242 | if (ret) | |
243 | return ret; | |
244 | ||
245 | ret = i915_gem_object_put_fence(obj); | |
246 | if (ret) | |
247 | return ret; | |
248 | ||
249 | /* Map the page containing the relocation we're going to perform. */ | |
250 | reloc->offset += i915_gem_obj_ggtt_offset(obj); | |
251 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
252 | reloc->offset & PAGE_MASK); | |
253 | reloc_entry = (uint32_t __iomem *) | |
254 | (reloc_page + offset_in_page(reloc->offset)); | |
255 | iowrite32(reloc->delta, reloc_entry); | |
256 | io_mapping_unmap_atomic(reloc_page); | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
54cf91dc CW |
261 | static int |
262 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 263 | struct eb_vmas *eb, |
28d6a7bf BW |
264 | struct drm_i915_gem_relocation_entry *reloc, |
265 | struct i915_address_space *vm) | |
54cf91dc CW |
266 | { |
267 | struct drm_device *dev = obj->base.dev; | |
268 | struct drm_gem_object *target_obj; | |
149c8407 | 269 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 270 | struct i915_vma *target_vma; |
54cf91dc CW |
271 | uint32_t target_offset; |
272 | int ret = -EINVAL; | |
273 | ||
67731b87 | 274 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
275 | target_vma = eb_get_vma(eb, reloc->target_handle); |
276 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 277 | return -ENOENT; |
27173f1f BW |
278 | target_i915_obj = target_vma->obj; |
279 | target_obj = &target_vma->obj->base; | |
54cf91dc | 280 | |
f343c5f6 | 281 | target_offset = i915_gem_obj_ggtt_offset(target_i915_obj); |
54cf91dc | 282 | |
e844b990 EA |
283 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
284 | * pipe_control writes because the gpu doesn't properly redirect them | |
285 | * through the ppgtt for non_secure batchbuffers. */ | |
286 | if (unlikely(IS_GEN6(dev) && | |
287 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
288 | !target_i915_obj->has_global_gtt_mapping)) { | |
289 | i915_gem_gtt_bind_object(target_i915_obj, | |
290 | target_i915_obj->cache_level); | |
291 | } | |
292 | ||
54cf91dc | 293 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 294 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 295 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
296 | "obj %p target %d offset %d " |
297 | "read %08x write %08x", | |
298 | obj, reloc->target_handle, | |
299 | (int) reloc->offset, | |
300 | reloc->read_domains, | |
301 | reloc->write_domain); | |
67731b87 | 302 | return ret; |
54cf91dc | 303 | } |
4ca4a250 DV |
304 | if (unlikely((reloc->write_domain | reloc->read_domains) |
305 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 306 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
307 | "obj %p target %d offset %d " |
308 | "read %08x write %08x", | |
309 | obj, reloc->target_handle, | |
310 | (int) reloc->offset, | |
311 | reloc->read_domains, | |
312 | reloc->write_domain); | |
67731b87 | 313 | return ret; |
54cf91dc | 314 | } |
54cf91dc CW |
315 | |
316 | target_obj->pending_read_domains |= reloc->read_domains; | |
317 | target_obj->pending_write_domain |= reloc->write_domain; | |
318 | ||
319 | /* If the relocation already has the right value in it, no | |
320 | * more work needs to be done. | |
321 | */ | |
322 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 323 | return 0; |
54cf91dc CW |
324 | |
325 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 326 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 327 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
328 | "obj %p target %d offset %d size %d.\n", |
329 | obj, reloc->target_handle, | |
330 | (int) reloc->offset, | |
331 | (int) obj->base.size); | |
67731b87 | 332 | return ret; |
54cf91dc | 333 | } |
b8f7ab17 | 334 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 335 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
336 | "obj %p target %d offset %d.\n", |
337 | obj, reloc->target_handle, | |
338 | (int) reloc->offset); | |
67731b87 | 339 | return ret; |
54cf91dc CW |
340 | } |
341 | ||
dabdfe02 CW |
342 | /* We can't wait for rendering with pagefaults disabled */ |
343 | if (obj->active && in_atomic()) | |
344 | return -EFAULT; | |
345 | ||
54cf91dc | 346 | reloc->delta += target_offset; |
5032d871 RB |
347 | if (use_cpu_reloc(obj)) |
348 | ret = relocate_entry_cpu(obj, reloc); | |
349 | else | |
350 | ret = relocate_entry_gtt(obj, reloc); | |
54cf91dc | 351 | |
d4d36014 DV |
352 | if (ret) |
353 | return ret; | |
354 | ||
54cf91dc CW |
355 | /* and update the user's relocation entry */ |
356 | reloc->presumed_offset = target_offset; | |
357 | ||
67731b87 | 358 | return 0; |
54cf91dc CW |
359 | } |
360 | ||
361 | static int | |
27173f1f BW |
362 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
363 | struct eb_vmas *eb) | |
54cf91dc | 364 | { |
1d83f442 CW |
365 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
366 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 367 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 368 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 369 | int remain, ret; |
54cf91dc | 370 | |
2bb4629a | 371 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 372 | |
1d83f442 CW |
373 | remain = entry->relocation_count; |
374 | while (remain) { | |
375 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
376 | int count = remain; | |
377 | if (count > ARRAY_SIZE(stack_reloc)) | |
378 | count = ARRAY_SIZE(stack_reloc); | |
379 | remain -= count; | |
380 | ||
381 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
382 | return -EFAULT; |
383 | ||
1d83f442 CW |
384 | do { |
385 | u64 offset = r->presumed_offset; | |
54cf91dc | 386 | |
27173f1f BW |
387 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r, |
388 | vma->vm); | |
1d83f442 CW |
389 | if (ret) |
390 | return ret; | |
391 | ||
392 | if (r->presumed_offset != offset && | |
393 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
394 | &r->presumed_offset, | |
395 | sizeof(r->presumed_offset))) { | |
396 | return -EFAULT; | |
397 | } | |
398 | ||
399 | user_relocs++; | |
400 | r++; | |
401 | } while (--count); | |
54cf91dc CW |
402 | } |
403 | ||
404 | return 0; | |
1d83f442 | 405 | #undef N_RELOC |
54cf91dc CW |
406 | } |
407 | ||
408 | static int | |
27173f1f BW |
409 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
410 | struct eb_vmas *eb, | |
411 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 412 | { |
27173f1f | 413 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
414 | int i, ret; |
415 | ||
416 | for (i = 0; i < entry->relocation_count; i++) { | |
27173f1f BW |
417 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i], |
418 | vma->vm); | |
54cf91dc CW |
419 | if (ret) |
420 | return ret; | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | static int | |
27173f1f | 427 | i915_gem_execbuffer_relocate(struct eb_vmas *eb, |
28d6a7bf | 428 | struct i915_address_space *vm) |
54cf91dc | 429 | { |
27173f1f | 430 | struct i915_vma *vma; |
d4aeee77 CW |
431 | int ret = 0; |
432 | ||
433 | /* This is the fast path and we cannot handle a pagefault whilst | |
434 | * holding the struct mutex lest the user pass in the relocations | |
435 | * contained within a mmaped bo. For in such a case we, the page | |
436 | * fault handler would call i915_gem_fault() and we would try to | |
437 | * acquire the struct mutex again. Obviously this is bad and so | |
438 | * lockdep complains vehemently. | |
439 | */ | |
440 | pagefault_disable(); | |
27173f1f BW |
441 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
442 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 443 | if (ret) |
d4aeee77 | 444 | break; |
54cf91dc | 445 | } |
d4aeee77 | 446 | pagefault_enable(); |
54cf91dc | 447 | |
d4aeee77 | 448 | return ret; |
54cf91dc CW |
449 | } |
450 | ||
7788a765 CW |
451 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
452 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
1690e1eb | 453 | |
dabdfe02 | 454 | static int |
27173f1f | 455 | need_reloc_mappable(struct i915_vma *vma) |
dabdfe02 | 456 | { |
27173f1f BW |
457 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
458 | return entry->relocation_count && !use_cpu_reloc(vma->obj) && | |
459 | i915_is_ggtt(vma->vm); | |
dabdfe02 CW |
460 | } |
461 | ||
1690e1eb | 462 | static int |
27173f1f BW |
463 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
464 | struct intel_ring_buffer *ring, | |
465 | bool *need_reloc) | |
1690e1eb | 466 | { |
27173f1f BW |
467 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
468 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
1690e1eb CW |
469 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
470 | bool need_fence, need_mappable; | |
27173f1f | 471 | struct drm_i915_gem_object *obj = vma->obj; |
1690e1eb CW |
472 | int ret; |
473 | ||
474 | need_fence = | |
475 | has_fenced_gpu_access && | |
476 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
477 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 478 | need_mappable = need_fence || need_reloc_mappable(vma); |
1690e1eb | 479 | |
27173f1f | 480 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, need_mappable, |
28d6a7bf | 481 | false); |
1690e1eb CW |
482 | if (ret) |
483 | return ret; | |
484 | ||
7788a765 CW |
485 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
486 | ||
1690e1eb CW |
487 | if (has_fenced_gpu_access) { |
488 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
06d98131 | 489 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 | 490 | if (ret) |
7788a765 | 491 | return ret; |
1690e1eb | 492 | |
9a5a53b3 | 493 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 494 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 495 | |
7dd49065 | 496 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 497 | } |
1690e1eb CW |
498 | } |
499 | ||
7788a765 CW |
500 | /* Ensure ppgtt mapping exists if needed */ |
501 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
502 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
503 | obj, obj->cache_level); | |
504 | ||
505 | obj->has_aliasing_ppgtt_mapping = 1; | |
506 | } | |
507 | ||
27173f1f BW |
508 | if (entry->offset != vma->node.start) { |
509 | entry->offset = vma->node.start; | |
ed5982e6 DV |
510 | *need_reloc = true; |
511 | } | |
512 | ||
513 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
514 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
515 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
516 | } | |
517 | ||
518 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT && | |
519 | !obj->has_global_gtt_mapping) | |
520 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
521 | ||
1690e1eb | 522 | return 0; |
7788a765 | 523 | } |
1690e1eb | 524 | |
7788a765 | 525 | static void |
27173f1f | 526 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) |
7788a765 CW |
527 | { |
528 | struct drm_i915_gem_exec_object2 *entry; | |
27173f1f | 529 | struct drm_i915_gem_object *obj = vma->obj; |
7788a765 | 530 | |
27173f1f | 531 | if (!drm_mm_node_allocated(&vma->node)) |
7788a765 CW |
532 | return; |
533 | ||
27173f1f | 534 | entry = vma->exec_entry; |
7788a765 CW |
535 | |
536 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
537 | i915_gem_object_unpin_fence(obj); | |
538 | ||
539 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
540 | i915_gem_object_unpin(obj); | |
541 | ||
542 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
1690e1eb CW |
543 | } |
544 | ||
54cf91dc | 545 | static int |
d9e86c0e | 546 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
27173f1f | 547 | struct list_head *vmas, |
ed5982e6 | 548 | bool *need_relocs) |
54cf91dc | 549 | { |
432e58ed | 550 | struct drm_i915_gem_object *obj; |
27173f1f | 551 | struct i915_vma *vma; |
68c8c17f | 552 | struct i915_address_space *vm; |
27173f1f | 553 | struct list_head ordered_vmas; |
7788a765 CW |
554 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
555 | int retry; | |
6fe4f140 | 556 | |
68c8c17f BW |
557 | if (list_empty(vmas)) |
558 | return 0; | |
559 | ||
560 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; | |
561 | ||
27173f1f BW |
562 | INIT_LIST_HEAD(&ordered_vmas); |
563 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
564 | struct drm_i915_gem_exec_object2 *entry; |
565 | bool need_fence, need_mappable; | |
566 | ||
27173f1f BW |
567 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
568 | obj = vma->obj; | |
569 | entry = vma->exec_entry; | |
6fe4f140 CW |
570 | |
571 | need_fence = | |
572 | has_fenced_gpu_access && | |
573 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
574 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 575 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 CW |
576 | |
577 | if (need_mappable) | |
27173f1f | 578 | list_move(&vma->exec_list, &ordered_vmas); |
6fe4f140 | 579 | else |
27173f1f | 580 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 581 | |
ed5982e6 | 582 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 583 | obj->base.pending_write_domain = 0; |
016fd0c1 | 584 | obj->pending_fenced_gpu_access = false; |
6fe4f140 | 585 | } |
27173f1f | 586 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
587 | |
588 | /* Attempt to pin all of the buffers into the GTT. | |
589 | * This is done in 3 phases: | |
590 | * | |
591 | * 1a. Unbind all objects that do not match the GTT constraints for | |
592 | * the execbuffer (fenceable, mappable, alignment etc). | |
593 | * 1b. Increment pin count for already bound objects. | |
594 | * 2. Bind new objects. | |
595 | * 3. Decrement pin count. | |
596 | * | |
7788a765 | 597 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
598 | * room for the earlier objects *unless* we need to defragment. |
599 | */ | |
600 | retry = 0; | |
601 | do { | |
7788a765 | 602 | int ret = 0; |
54cf91dc CW |
603 | |
604 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f BW |
605 | list_for_each_entry(vma, vmas, exec_list) { |
606 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
54cf91dc | 607 | bool need_fence, need_mappable; |
1690e1eb | 608 | |
27173f1f BW |
609 | obj = vma->obj; |
610 | ||
611 | if (!drm_mm_node_allocated(&vma->node)) | |
54cf91dc CW |
612 | continue; |
613 | ||
614 | need_fence = | |
9b3826bf | 615 | has_fenced_gpu_access && |
54cf91dc CW |
616 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
617 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 618 | need_mappable = need_fence || need_reloc_mappable(vma); |
54cf91dc | 619 | |
28d6a7bf | 620 | WARN_ON((need_mappable || need_fence) && |
27173f1f | 621 | !i915_is_ggtt(vma->vm)); |
28d6a7bf | 622 | |
f343c5f6 | 623 | if ((entry->alignment && |
27173f1f | 624 | vma->node.start & (entry->alignment - 1)) || |
54cf91dc | 625 | (need_mappable && !obj->map_and_fenceable)) |
27173f1f | 626 | ret = i915_vma_unbind(vma); |
54cf91dc | 627 | else |
27173f1f | 628 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 629 | if (ret) |
54cf91dc | 630 | goto err; |
54cf91dc CW |
631 | } |
632 | ||
633 | /* Bind fresh objects */ | |
27173f1f BW |
634 | list_for_each_entry(vma, vmas, exec_list) { |
635 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 636 | continue; |
54cf91dc | 637 | |
27173f1f | 638 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
639 | if (ret) |
640 | goto err; | |
54cf91dc CW |
641 | } |
642 | ||
7788a765 | 643 | err: /* Decrement pin count for bound objects */ |
27173f1f BW |
644 | list_for_each_entry(vma, vmas, exec_list) |
645 | i915_gem_execbuffer_unreserve_vma(vma); | |
54cf91dc | 646 | |
6c085a72 | 647 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
648 | return ret; |
649 | ||
68c8c17f | 650 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
651 | if (ret) |
652 | return ret; | |
54cf91dc CW |
653 | } while (1); |
654 | } | |
655 | ||
656 | static int | |
657 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 658 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 659 | struct drm_file *file, |
d9e86c0e | 660 | struct intel_ring_buffer *ring, |
27173f1f BW |
661 | struct eb_vmas *eb, |
662 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc CW |
663 | { |
664 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
665 | struct i915_address_space *vm; |
666 | struct i915_vma *vma; | |
ed5982e6 | 667 | bool need_relocs; |
dd6864a4 | 668 | int *reloc_offset; |
54cf91dc | 669 | int i, total, ret; |
ed5982e6 | 670 | int count = args->buffer_count; |
54cf91dc | 671 | |
27173f1f BW |
672 | if (WARN_ON(list_empty(&eb->vmas))) |
673 | return 0; | |
674 | ||
675 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; | |
676 | ||
67731b87 | 677 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
678 | while (!list_empty(&eb->vmas)) { |
679 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
680 | list_del_init(&vma->exec_list); | |
681 | drm_gem_object_unreference(&vma->obj->base); | |
67731b87 CW |
682 | } |
683 | ||
54cf91dc CW |
684 | mutex_unlock(&dev->struct_mutex); |
685 | ||
686 | total = 0; | |
687 | for (i = 0; i < count; i++) | |
432e58ed | 688 | total += exec[i].relocation_count; |
54cf91dc | 689 | |
dd6864a4 | 690 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 691 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
692 | if (reloc == NULL || reloc_offset == NULL) { |
693 | drm_free_large(reloc); | |
694 | drm_free_large(reloc_offset); | |
54cf91dc CW |
695 | mutex_lock(&dev->struct_mutex); |
696 | return -ENOMEM; | |
697 | } | |
698 | ||
699 | total = 0; | |
700 | for (i = 0; i < count; i++) { | |
701 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
702 | u64 invalid_offset = (u64)-1; |
703 | int j; | |
54cf91dc | 704 | |
2bb4629a | 705 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
706 | |
707 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 708 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
709 | ret = -EFAULT; |
710 | mutex_lock(&dev->struct_mutex); | |
711 | goto err; | |
712 | } | |
713 | ||
262b6d36 CW |
714 | /* As we do not update the known relocation offsets after |
715 | * relocating (due to the complexities in lock handling), | |
716 | * we need to mark them as invalid now so that we force the | |
717 | * relocation processing next time. Just in case the target | |
718 | * object is evicted and then rebound into its old | |
719 | * presumed_offset before the next execbuffer - if that | |
720 | * happened we would make the mistake of assuming that the | |
721 | * relocations were valid. | |
722 | */ | |
723 | for (j = 0; j < exec[i].relocation_count; j++) { | |
724 | if (copy_to_user(&user_relocs[j].presumed_offset, | |
725 | &invalid_offset, | |
726 | sizeof(invalid_offset))) { | |
727 | ret = -EFAULT; | |
728 | mutex_lock(&dev->struct_mutex); | |
729 | goto err; | |
730 | } | |
731 | } | |
732 | ||
dd6864a4 | 733 | reloc_offset[i] = total; |
432e58ed | 734 | total += exec[i].relocation_count; |
54cf91dc CW |
735 | } |
736 | ||
737 | ret = i915_mutex_lock_interruptible(dev); | |
738 | if (ret) { | |
739 | mutex_lock(&dev->struct_mutex); | |
740 | goto err; | |
741 | } | |
742 | ||
67731b87 | 743 | /* reacquire the objects */ |
67731b87 | 744 | eb_reset(eb); |
27173f1f | 745 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
746 | if (ret) |
747 | goto err; | |
67731b87 | 748 | |
ed5982e6 | 749 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 750 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
751 | if (ret) |
752 | goto err; | |
753 | ||
27173f1f BW |
754 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
755 | int offset = vma->exec_entry - exec; | |
756 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
757 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
758 | if (ret) |
759 | goto err; | |
54cf91dc CW |
760 | } |
761 | ||
762 | /* Leave the user relocations as are, this is the painfully slow path, | |
763 | * and we want to avoid the complication of dropping the lock whilst | |
764 | * having buffers reserved in the aperture and so causing spurious | |
765 | * ENOSPC for random operations. | |
766 | */ | |
767 | ||
768 | err: | |
769 | drm_free_large(reloc); | |
dd6864a4 | 770 | drm_free_large(reloc_offset); |
54cf91dc CW |
771 | return ret; |
772 | } | |
773 | ||
54cf91dc | 774 | static int |
432e58ed | 775 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
27173f1f | 776 | struct list_head *vmas) |
54cf91dc | 777 | { |
27173f1f | 778 | struct i915_vma *vma; |
6ac42f41 | 779 | uint32_t flush_domains = 0; |
000433b6 | 780 | bool flush_chipset = false; |
432e58ed | 781 | int ret; |
54cf91dc | 782 | |
27173f1f BW |
783 | list_for_each_entry(vma, vmas, exec_list) { |
784 | struct drm_i915_gem_object *obj = vma->obj; | |
6ac42f41 | 785 | ret = i915_gem_object_sync(obj, ring); |
c59a333f CW |
786 | if (ret) |
787 | return ret; | |
6ac42f41 DV |
788 | |
789 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 790 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 791 | |
6ac42f41 | 792 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
793 | } |
794 | ||
000433b6 | 795 | if (flush_chipset) |
e76e9aeb | 796 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
797 | |
798 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
799 | wmb(); | |
800 | ||
09cf7c9a CW |
801 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
802 | * any residual writes from the previous batch. | |
803 | */ | |
a7b9761d | 804 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
805 | } |
806 | ||
432e58ed CW |
807 | static bool |
808 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 809 | { |
ed5982e6 DV |
810 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
811 | return false; | |
812 | ||
432e58ed | 813 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
814 | } |
815 | ||
816 | static int | |
817 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
818 | int count) | |
819 | { | |
820 | int i; | |
3118a4f6 KC |
821 | int relocs_total = 0; |
822 | int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
54cf91dc CW |
823 | |
824 | for (i = 0; i < count; i++) { | |
2bb4629a | 825 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
826 | int length; /* limited by fault_in_pages_readable() */ |
827 | ||
ed5982e6 DV |
828 | if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS) |
829 | return -EINVAL; | |
830 | ||
3118a4f6 KC |
831 | /* First check for malicious input causing overflow in |
832 | * the worst case where we need to allocate the entire | |
833 | * relocation tree as a single array. | |
834 | */ | |
835 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 836 | return -EINVAL; |
3118a4f6 | 837 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
838 | |
839 | length = exec[i].relocation_count * | |
840 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
841 | /* |
842 | * We must check that the entire relocation array is safe | |
843 | * to read, but since we may need to update the presumed | |
844 | * offsets during execution, check for full write access. | |
845 | */ | |
54cf91dc CW |
846 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
847 | return -EFAULT; | |
848 | ||
0b74b508 XZ |
849 | if (likely(!i915_prefault_disable)) { |
850 | if (fault_in_multipages_readable(ptr, length)) | |
851 | return -EFAULT; | |
852 | } | |
54cf91dc CW |
853 | } |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
432e58ed | 858 | static void |
27173f1f | 859 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
9d773091 | 860 | struct intel_ring_buffer *ring) |
432e58ed | 861 | { |
27173f1f | 862 | struct i915_vma *vma; |
432e58ed | 863 | |
27173f1f BW |
864 | list_for_each_entry(vma, vmas, exec_list) { |
865 | struct drm_i915_gem_object *obj = vma->obj; | |
69c2fc89 CW |
866 | u32 old_read = obj->base.read_domains; |
867 | u32 old_write = obj->base.write_domain; | |
db53a302 | 868 | |
432e58ed | 869 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
870 | if (obj->base.write_domain == 0) |
871 | obj->base.pending_read_domains |= obj->base.read_domains; | |
872 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed CW |
873 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
874 | ||
27173f1f | 875 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
9d773091 | 876 | i915_gem_object_move_to_active(obj, ring); |
432e58ed CW |
877 | if (obj->base.write_domain) { |
878 | obj->dirty = 1; | |
9d773091 | 879 | obj->last_write_seqno = intel_ring_get_seqno(ring); |
acb87dfb | 880 | if (obj->pin_count) /* check for potential scanout */ |
c65355bb | 881 | intel_mark_fb_busy(obj, ring); |
432e58ed CW |
882 | } |
883 | ||
db53a302 | 884 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
885 | } |
886 | } | |
887 | ||
54cf91dc CW |
888 | static void |
889 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 890 | struct drm_file *file, |
7d736f4f MK |
891 | struct intel_ring_buffer *ring, |
892 | struct drm_i915_gem_object *obj) | |
54cf91dc | 893 | { |
cc889e0f DV |
894 | /* Unconditionally force add_request to emit a full flush. */ |
895 | ring->gpu_caches_dirty = true; | |
54cf91dc | 896 | |
432e58ed | 897 | /* Add a breadcrumb for the completion of the batch buffer */ |
7d736f4f | 898 | (void)__i915_add_request(ring, file, obj, NULL); |
432e58ed | 899 | } |
54cf91dc | 900 | |
ae662d31 EA |
901 | static int |
902 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
903 | struct intel_ring_buffer *ring) | |
904 | { | |
905 | drm_i915_private_t *dev_priv = dev->dev_private; | |
906 | int ret, i; | |
907 | ||
908 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
909 | return 0; | |
910 | ||
911 | ret = intel_ring_begin(ring, 4 * 3); | |
912 | if (ret) | |
913 | return ret; | |
914 | ||
915 | for (i = 0; i < 4; i++) { | |
916 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
917 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
918 | intel_ring_emit(ring, 0); | |
919 | } | |
920 | ||
921 | intel_ring_advance(ring); | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
54cf91dc CW |
926 | static int |
927 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
928 | struct drm_file *file, | |
929 | struct drm_i915_gem_execbuffer2 *args, | |
28d6a7bf BW |
930 | struct drm_i915_gem_exec_object2 *exec, |
931 | struct i915_address_space *vm) | |
54cf91dc CW |
932 | { |
933 | drm_i915_private_t *dev_priv = dev->dev_private; | |
27173f1f | 934 | struct eb_vmas *eb; |
54cf91dc CW |
935 | struct drm_i915_gem_object *batch_obj; |
936 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 937 | struct intel_ring_buffer *ring; |
be62acb4 | 938 | struct i915_ctx_hang_stats *hs; |
6e0a69db | 939 | u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
c4e7a414 | 940 | u32 exec_start, exec_len; |
ed5982e6 | 941 | u32 mask, flags; |
72bfa19c | 942 | int ret, mode, i; |
ed5982e6 | 943 | bool need_relocs; |
54cf91dc | 944 | |
ed5982e6 | 945 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 946 | return -EINVAL; |
432e58ed CW |
947 | |
948 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
949 | if (ret) |
950 | return ret; | |
951 | ||
d7d4eedd CW |
952 | flags = 0; |
953 | if (args->flags & I915_EXEC_SECURE) { | |
954 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
955 | return -EPERM; | |
956 | ||
957 | flags |= I915_DISPATCH_SECURE; | |
958 | } | |
b45305fc DV |
959 | if (args->flags & I915_EXEC_IS_PINNED) |
960 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 961 | |
54cf91dc CW |
962 | switch (args->flags & I915_EXEC_RING_MASK) { |
963 | case I915_EXEC_DEFAULT: | |
964 | case I915_EXEC_RENDER: | |
1ec14ad3 | 965 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
966 | break; |
967 | case I915_EXEC_BSD: | |
1ec14ad3 | 968 | ring = &dev_priv->ring[VCS]; |
e8520969 | 969 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
6e0a69db BW |
970 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
971 | ring->name); | |
972 | return -EPERM; | |
973 | } | |
54cf91dc CW |
974 | break; |
975 | case I915_EXEC_BLT: | |
1ec14ad3 | 976 | ring = &dev_priv->ring[BCS]; |
e8520969 | 977 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
6e0a69db BW |
978 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
979 | ring->name); | |
980 | return -EPERM; | |
981 | } | |
54cf91dc | 982 | break; |
82f91b6e XH |
983 | case I915_EXEC_VEBOX: |
984 | ring = &dev_priv->ring[VECS]; | |
e8520969 | 985 | if (ctx_id != DEFAULT_CONTEXT_ID) { |
82f91b6e XH |
986 | DRM_DEBUG("Ring %s doesn't support contexts\n", |
987 | ring->name); | |
988 | return -EPERM; | |
989 | } | |
990 | break; | |
991 | ||
54cf91dc | 992 | default: |
ff240199 | 993 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
994 | (int)(args->flags & I915_EXEC_RING_MASK)); |
995 | return -EINVAL; | |
996 | } | |
a15817cf CW |
997 | if (!intel_ring_initialized(ring)) { |
998 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
999 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1000 | return -EINVAL; | |
1001 | } | |
54cf91dc | 1002 | |
72bfa19c | 1003 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 1004 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
1005 | switch (mode) { |
1006 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1007 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1008 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1009 | if (ring == &dev_priv->ring[RCS] && | |
1010 | mode != dev_priv->relative_constants_mode) { | |
1011 | if (INTEL_INFO(dev)->gen < 4) | |
1012 | return -EINVAL; | |
1013 | ||
1014 | if (INTEL_INFO(dev)->gen > 5 && | |
1015 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
1016 | return -EINVAL; | |
84f9f938 BW |
1017 | |
1018 | /* The HW changed the meaning on this bit on gen6 */ | |
1019 | if (INTEL_INFO(dev)->gen >= 6) | |
1020 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
1021 | } |
1022 | break; | |
1023 | default: | |
ff240199 | 1024 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
1025 | return -EINVAL; |
1026 | } | |
1027 | ||
54cf91dc | 1028 | if (args->buffer_count < 1) { |
ff240199 | 1029 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1030 | return -EINVAL; |
1031 | } | |
54cf91dc CW |
1032 | |
1033 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 1034 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 1035 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
1036 | return -EINVAL; |
1037 | } | |
1038 | ||
6ebebc92 DV |
1039 | if (INTEL_INFO(dev)->gen >= 5) { |
1040 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1041 | return -EINVAL; | |
1042 | } | |
1043 | ||
44afb3a0 XW |
1044 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { |
1045 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1046 | args->num_cliprects); | |
1047 | return -EINVAL; | |
1048 | } | |
5e13a0c5 | 1049 | |
432e58ed | 1050 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
1051 | GFP_KERNEL); |
1052 | if (cliprects == NULL) { | |
1053 | ret = -ENOMEM; | |
1054 | goto pre_mutex_err; | |
1055 | } | |
1056 | ||
432e58ed | 1057 | if (copy_from_user(cliprects, |
2bb4629a VS |
1058 | to_user_ptr(args->cliprects_ptr), |
1059 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
1060 | ret = -EFAULT; |
1061 | goto pre_mutex_err; | |
1062 | } | |
1063 | } | |
1064 | ||
54cf91dc CW |
1065 | ret = i915_mutex_lock_interruptible(dev); |
1066 | if (ret) | |
1067 | goto pre_mutex_err; | |
1068 | ||
db1b76ca | 1069 | if (dev_priv->ums.mm_suspended) { |
54cf91dc CW |
1070 | mutex_unlock(&dev->struct_mutex); |
1071 | ret = -EBUSY; | |
1072 | goto pre_mutex_err; | |
1073 | } | |
1074 | ||
27173f1f | 1075 | eb = eb_create(args, vm); |
67731b87 CW |
1076 | if (eb == NULL) { |
1077 | mutex_unlock(&dev->struct_mutex); | |
1078 | ret = -ENOMEM; | |
1079 | goto pre_mutex_err; | |
1080 | } | |
1081 | ||
54cf91dc | 1082 | /* Look up object handles */ |
27173f1f | 1083 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1084 | if (ret) |
1085 | goto err; | |
54cf91dc | 1086 | |
6fe4f140 | 1087 | /* take note of the batch buffer before we might reorder the lists */ |
27173f1f | 1088 | batch_obj = list_entry(eb->vmas.prev, struct i915_vma, exec_list)->obj; |
6fe4f140 | 1089 | |
54cf91dc | 1090 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1091 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 1092 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
1093 | if (ret) |
1094 | goto err; | |
1095 | ||
1096 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1097 | if (need_relocs) |
28d6a7bf | 1098 | ret = i915_gem_execbuffer_relocate(eb, vm); |
54cf91dc CW |
1099 | if (ret) { |
1100 | if (ret == -EFAULT) { | |
ed5982e6 | 1101 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
27173f1f | 1102 | eb, exec); |
54cf91dc CW |
1103 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1104 | } | |
1105 | if (ret) | |
1106 | goto err; | |
1107 | } | |
1108 | ||
1109 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1110 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1111 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1112 | ret = -EINVAL; |
1113 | goto err; | |
1114 | } | |
1115 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1116 | ||
d7d4eedd CW |
1117 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1118 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
1119 | * hsw should have this fixed, but let's be paranoid and do it | |
1120 | * unconditionally for now. */ | |
1121 | if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping) | |
1122 | i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level); | |
1123 | ||
27173f1f | 1124 | ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas); |
432e58ed | 1125 | if (ret) |
54cf91dc | 1126 | goto err; |
54cf91dc | 1127 | |
be62acb4 MK |
1128 | hs = i915_gem_context_get_hang_stats(dev, file, ctx_id); |
1129 | if (IS_ERR(hs)) { | |
1130 | ret = PTR_ERR(hs); | |
1131 | goto err; | |
1132 | } | |
1133 | ||
1134 | if (hs->banned) { | |
1135 | ret = -EIO; | |
1136 | goto err; | |
1137 | } | |
1138 | ||
0da5cec1 EA |
1139 | ret = i915_switch_context(ring, file, ctx_id); |
1140 | if (ret) | |
1141 | goto err; | |
1142 | ||
e2971bda BW |
1143 | if (ring == &dev_priv->ring[RCS] && |
1144 | mode != dev_priv->relative_constants_mode) { | |
1145 | ret = intel_ring_begin(ring, 4); | |
1146 | if (ret) | |
1147 | goto err; | |
1148 | ||
1149 | intel_ring_emit(ring, MI_NOOP); | |
1150 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1151 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1152 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1153 | intel_ring_advance(ring); |
1154 | ||
1155 | dev_priv->relative_constants_mode = mode; | |
1156 | } | |
1157 | ||
ae662d31 EA |
1158 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1159 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1160 | if (ret) | |
1161 | goto err; | |
1162 | } | |
1163 | ||
28d6a7bf BW |
1164 | exec_start = i915_gem_obj_offset(batch_obj, vm) + |
1165 | args->batch_start_offset; | |
c4e7a414 CW |
1166 | exec_len = args->batch_len; |
1167 | if (cliprects) { | |
1168 | for (i = 0; i < args->num_cliprects; i++) { | |
1169 | ret = i915_emit_box(dev, &cliprects[i], | |
1170 | args->DR1, args->DR4); | |
1171 | if (ret) | |
1172 | goto err; | |
1173 | ||
1174 | ret = ring->dispatch_execbuffer(ring, | |
d7d4eedd CW |
1175 | exec_start, exec_len, |
1176 | flags); | |
c4e7a414 CW |
1177 | if (ret) |
1178 | goto err; | |
1179 | } | |
1180 | } else { | |
d7d4eedd CW |
1181 | ret = ring->dispatch_execbuffer(ring, |
1182 | exec_start, exec_len, | |
1183 | flags); | |
c4e7a414 CW |
1184 | if (ret) |
1185 | goto err; | |
1186 | } | |
54cf91dc | 1187 | |
9d773091 CW |
1188 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); |
1189 | ||
27173f1f | 1190 | i915_gem_execbuffer_move_to_active(&eb->vmas, ring); |
7d736f4f | 1191 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); |
54cf91dc CW |
1192 | |
1193 | err: | |
67731b87 | 1194 | eb_destroy(eb); |
54cf91dc CW |
1195 | |
1196 | mutex_unlock(&dev->struct_mutex); | |
1197 | ||
1198 | pre_mutex_err: | |
54cf91dc | 1199 | kfree(cliprects); |
54cf91dc CW |
1200 | return ret; |
1201 | } | |
1202 | ||
1203 | /* | |
1204 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1205 | * list array and passes it to the real function. | |
1206 | */ | |
1207 | int | |
1208 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1209 | struct drm_file *file) | |
1210 | { | |
28d6a7bf | 1211 | struct drm_i915_private *dev_priv = dev->dev_private; |
54cf91dc CW |
1212 | struct drm_i915_gem_execbuffer *args = data; |
1213 | struct drm_i915_gem_execbuffer2 exec2; | |
1214 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1215 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1216 | int ret, i; | |
1217 | ||
54cf91dc | 1218 | if (args->buffer_count < 1) { |
ff240199 | 1219 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1220 | return -EINVAL; |
1221 | } | |
1222 | ||
1223 | /* Copy in the exec list from userland */ | |
1224 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1225 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1226 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1227 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1228 | args->buffer_count); |
1229 | drm_free_large(exec_list); | |
1230 | drm_free_large(exec2_list); | |
1231 | return -ENOMEM; | |
1232 | } | |
1233 | ret = copy_from_user(exec_list, | |
2bb4629a | 1234 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1235 | sizeof(*exec_list) * args->buffer_count); |
1236 | if (ret != 0) { | |
ff240199 | 1237 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1238 | args->buffer_count, ret); |
1239 | drm_free_large(exec_list); | |
1240 | drm_free_large(exec2_list); | |
1241 | return -EFAULT; | |
1242 | } | |
1243 | ||
1244 | for (i = 0; i < args->buffer_count; i++) { | |
1245 | exec2_list[i].handle = exec_list[i].handle; | |
1246 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1247 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1248 | exec2_list[i].alignment = exec_list[i].alignment; | |
1249 | exec2_list[i].offset = exec_list[i].offset; | |
1250 | if (INTEL_INFO(dev)->gen < 4) | |
1251 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1252 | else | |
1253 | exec2_list[i].flags = 0; | |
1254 | } | |
1255 | ||
1256 | exec2.buffers_ptr = args->buffers_ptr; | |
1257 | exec2.buffer_count = args->buffer_count; | |
1258 | exec2.batch_start_offset = args->batch_start_offset; | |
1259 | exec2.batch_len = args->batch_len; | |
1260 | exec2.DR1 = args->DR1; | |
1261 | exec2.DR4 = args->DR4; | |
1262 | exec2.num_cliprects = args->num_cliprects; | |
1263 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1264 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1265 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1266 | |
28d6a7bf BW |
1267 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list, |
1268 | &dev_priv->gtt.base); | |
54cf91dc CW |
1269 | if (!ret) { |
1270 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1271 | for (i = 0; i < args->buffer_count; i++) | |
1272 | exec_list[i].offset = exec2_list[i].offset; | |
1273 | /* ... and back out to userspace */ | |
2bb4629a | 1274 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1275 | exec_list, |
1276 | sizeof(*exec_list) * args->buffer_count); | |
1277 | if (ret) { | |
1278 | ret = -EFAULT; | |
ff240199 | 1279 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1280 | "back to user (%d)\n", |
1281 | args->buffer_count, ret); | |
1282 | } | |
1283 | } | |
1284 | ||
1285 | drm_free_large(exec_list); | |
1286 | drm_free_large(exec2_list); | |
1287 | return ret; | |
1288 | } | |
1289 | ||
1290 | int | |
1291 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1292 | struct drm_file *file) | |
1293 | { | |
28d6a7bf | 1294 | struct drm_i915_private *dev_priv = dev->dev_private; |
54cf91dc CW |
1295 | struct drm_i915_gem_execbuffer2 *args = data; |
1296 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1297 | int ret; | |
1298 | ||
ed8cd3b2 XW |
1299 | if (args->buffer_count < 1 || |
1300 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1301 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1302 | return -EINVAL; |
1303 | } | |
1304 | ||
8408c282 | 1305 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1306 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1307 | if (exec2_list == NULL) |
1308 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1309 | args->buffer_count); | |
54cf91dc | 1310 | if (exec2_list == NULL) { |
ff240199 | 1311 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1312 | args->buffer_count); |
1313 | return -ENOMEM; | |
1314 | } | |
1315 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1316 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1317 | sizeof(*exec2_list) * args->buffer_count); |
1318 | if (ret != 0) { | |
ff240199 | 1319 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1320 | args->buffer_count, ret); |
1321 | drm_free_large(exec2_list); | |
1322 | return -EFAULT; | |
1323 | } | |
1324 | ||
28d6a7bf BW |
1325 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list, |
1326 | &dev_priv->gtt.base); | |
54cf91dc CW |
1327 | if (!ret) { |
1328 | /* Copy the new buffer offsets back to the user's exec list. */ | |
2bb4629a | 1329 | ret = copy_to_user(to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1330 | exec2_list, |
1331 | sizeof(*exec2_list) * args->buffer_count); | |
1332 | if (ret) { | |
1333 | ret = -EFAULT; | |
ff240199 | 1334 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1335 | "back to user (%d)\n", |
1336 | args->buffer_count, ret); | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | drm_free_large(exec2_list); | |
1341 | return ret; | |
1342 | } |