Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
32d82067 | 35 | #include <linux/uaccess.h> |
54cf91dc | 36 | |
a415d355 CW |
37 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
38 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
e6a84468 | 39 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) |
d23db88c CW |
40 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) |
41 | ||
42 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 43 | |
27173f1f BW |
44 | struct eb_vmas { |
45 | struct list_head vmas; | |
67731b87 | 46 | int and; |
eef90ccb | 47 | union { |
27173f1f | 48 | struct i915_vma *lut[0]; |
eef90ccb CW |
49 | struct hlist_head buckets[0]; |
50 | }; | |
67731b87 CW |
51 | }; |
52 | ||
27173f1f | 53 | static struct eb_vmas * |
17601cbc | 54 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 55 | { |
27173f1f | 56 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
57 | |
58 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 59 | unsigned size = args->buffer_count; |
27173f1f BW |
60 | size *= sizeof(struct i915_vma *); |
61 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
62 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
63 | } | |
64 | ||
65 | if (eb == NULL) { | |
b205ca57 DV |
66 | unsigned size = args->buffer_count; |
67 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 68 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
69 | while (count > 2*size) |
70 | count >>= 1; | |
71 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 72 | sizeof(struct eb_vmas), |
eef90ccb CW |
73 | GFP_TEMPORARY); |
74 | if (eb == NULL) | |
75 | return eb; | |
76 | ||
77 | eb->and = count - 1; | |
78 | } else | |
79 | eb->and = -args->buffer_count; | |
80 | ||
27173f1f | 81 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
82 | return eb; |
83 | } | |
84 | ||
85 | static void | |
27173f1f | 86 | eb_reset(struct eb_vmas *eb) |
67731b87 | 87 | { |
eef90ccb CW |
88 | if (eb->and >= 0) |
89 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
90 | } |
91 | ||
3b96eff4 | 92 | static int |
27173f1f BW |
93 | eb_lookup_vmas(struct eb_vmas *eb, |
94 | struct drm_i915_gem_exec_object2 *exec, | |
95 | const struct drm_i915_gem_execbuffer2 *args, | |
96 | struct i915_address_space *vm, | |
97 | struct drm_file *file) | |
3b96eff4 | 98 | { |
27173f1f BW |
99 | struct drm_i915_gem_object *obj; |
100 | struct list_head objects; | |
9ae9ab52 | 101 | int i, ret; |
3b96eff4 | 102 | |
27173f1f | 103 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 104 | spin_lock(&file->table_lock); |
27173f1f BW |
105 | /* Grab a reference to the object and release the lock so we can lookup |
106 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 107 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
108 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
109 | if (obj == NULL) { | |
110 | spin_unlock(&file->table_lock); | |
111 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
112 | exec[i].handle, i); | |
27173f1f | 113 | ret = -ENOENT; |
9ae9ab52 | 114 | goto err; |
3b96eff4 CW |
115 | } |
116 | ||
27173f1f | 117 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
118 | spin_unlock(&file->table_lock); |
119 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
120 | obj, exec[i].handle, i); | |
27173f1f | 121 | ret = -EINVAL; |
9ae9ab52 | 122 | goto err; |
3b96eff4 CW |
123 | } |
124 | ||
125 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
126 | list_add_tail(&obj->obj_exec_link, &objects); |
127 | } | |
128 | spin_unlock(&file->table_lock); | |
3b96eff4 | 129 | |
27173f1f | 130 | i = 0; |
9ae9ab52 | 131 | while (!list_empty(&objects)) { |
27173f1f | 132 | struct i915_vma *vma; |
6f65e29a | 133 | |
9ae9ab52 CW |
134 | obj = list_first_entry(&objects, |
135 | struct drm_i915_gem_object, | |
136 | obj_exec_link); | |
137 | ||
e656a6cb DV |
138 | /* |
139 | * NOTE: We can leak any vmas created here when something fails | |
140 | * later on. But that's no issue since vma_unbind can deal with | |
141 | * vmas which are not actually bound. And since only | |
142 | * lookup_or_create exists as an interface to get at the vma | |
143 | * from the (obj, vm) we don't run the risk of creating | |
144 | * duplicated vmas for the same vm. | |
145 | */ | |
da51a1e7 | 146 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 147 | if (IS_ERR(vma)) { |
27173f1f BW |
148 | DRM_DEBUG("Failed to lookup VMA\n"); |
149 | ret = PTR_ERR(vma); | |
9ae9ab52 | 150 | goto err; |
27173f1f BW |
151 | } |
152 | ||
9ae9ab52 | 153 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 154 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 155 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
156 | |
157 | vma->exec_entry = &exec[i]; | |
eef90ccb | 158 | if (eb->and < 0) { |
27173f1f | 159 | eb->lut[i] = vma; |
eef90ccb CW |
160 | } else { |
161 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
162 | vma->exec_handle = handle; |
163 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
164 | &eb->buckets[handle & eb->and]); |
165 | } | |
27173f1f | 166 | ++i; |
3b96eff4 | 167 | } |
3b96eff4 | 168 | |
9ae9ab52 | 169 | return 0; |
27173f1f | 170 | |
27173f1f | 171 | |
9ae9ab52 | 172 | err: |
27173f1f BW |
173 | while (!list_empty(&objects)) { |
174 | obj = list_first_entry(&objects, | |
175 | struct drm_i915_gem_object, | |
176 | obj_exec_link); | |
177 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 178 | drm_gem_object_unreference(&obj->base); |
27173f1f | 179 | } |
9ae9ab52 CW |
180 | /* |
181 | * Objects already transfered to the vmas list will be unreferenced by | |
182 | * eb_destroy. | |
183 | */ | |
184 | ||
27173f1f | 185 | return ret; |
3b96eff4 CW |
186 | } |
187 | ||
27173f1f | 188 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 189 | { |
eef90ccb CW |
190 | if (eb->and < 0) { |
191 | if (handle >= -eb->and) | |
192 | return NULL; | |
193 | return eb->lut[handle]; | |
194 | } else { | |
195 | struct hlist_head *head; | |
aa45950b | 196 | struct i915_vma *vma; |
67731b87 | 197 | |
eef90ccb | 198 | head = &eb->buckets[handle & eb->and]; |
aa45950b | 199 | hlist_for_each_entry(vma, head, exec_node) { |
27173f1f BW |
200 | if (vma->exec_handle == handle) |
201 | return vma; | |
eef90ccb CW |
202 | } |
203 | return NULL; | |
204 | } | |
67731b87 CW |
205 | } |
206 | ||
a415d355 CW |
207 | static void |
208 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
209 | { | |
210 | struct drm_i915_gem_exec_object2 *entry; | |
211 | struct drm_i915_gem_object *obj = vma->obj; | |
212 | ||
213 | if (!drm_mm_node_allocated(&vma->node)) | |
214 | return; | |
215 | ||
216 | entry = vma->exec_entry; | |
217 | ||
218 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
219 | i915_gem_object_unpin_fence(obj); | |
220 | ||
221 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 222 | vma->pin_count--; |
a415d355 | 223 | |
de4e783a | 224 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
a415d355 CW |
225 | } |
226 | ||
227 | static void eb_destroy(struct eb_vmas *eb) | |
228 | { | |
27173f1f BW |
229 | while (!list_empty(&eb->vmas)) { |
230 | struct i915_vma *vma; | |
bcffc3fa | 231 | |
27173f1f BW |
232 | vma = list_first_entry(&eb->vmas, |
233 | struct i915_vma, | |
bcffc3fa | 234 | exec_list); |
27173f1f | 235 | list_del_init(&vma->exec_list); |
a415d355 | 236 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 237 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 238 | } |
67731b87 CW |
239 | kfree(eb); |
240 | } | |
241 | ||
dabdfe02 CW |
242 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
243 | { | |
2cc86b82 CW |
244 | return (HAS_LLC(obj->base.dev) || |
245 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
dabdfe02 CW |
246 | obj->cache_level != I915_CACHE_NONE); |
247 | } | |
248 | ||
934acce3 MW |
249 | /* Used to convert any address to canonical form. |
250 | * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, | |
251 | * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the | |
252 | * addresses to be in a canonical form: | |
253 | * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct | |
254 | * canonical form [63:48] == [47]." | |
255 | */ | |
256 | #define GEN8_HIGH_ADDRESS_BIT 47 | |
257 | static inline uint64_t gen8_canonical_addr(uint64_t address) | |
258 | { | |
259 | return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT); | |
260 | } | |
261 | ||
262 | static inline uint64_t gen8_noncanonical_addr(uint64_t address) | |
263 | { | |
264 | return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1); | |
265 | } | |
266 | ||
267 | static inline uint64_t | |
268 | relocation_target(struct drm_i915_gem_relocation_entry *reloc, | |
269 | uint64_t target_offset) | |
270 | { | |
271 | return gen8_canonical_addr((int)reloc->delta + target_offset); | |
272 | } | |
273 | ||
5032d871 RB |
274 | static int |
275 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
276 | struct drm_i915_gem_relocation_entry *reloc, |
277 | uint64_t target_offset) | |
5032d871 | 278 | { |
3c94ceee | 279 | struct drm_device *dev = obj->base.dev; |
5032d871 | 280 | uint32_t page_offset = offset_in_page(reloc->offset); |
934acce3 | 281 | uint64_t delta = relocation_target(reloc, target_offset); |
5032d871 | 282 | char *vaddr; |
8b78f0e5 | 283 | int ret; |
5032d871 | 284 | |
2cc86b82 | 285 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
286 | if (ret) |
287 | return ret; | |
288 | ||
033908ae | 289 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
5032d871 | 290 | reloc->offset >> PAGE_SHIFT)); |
d9ceb957 | 291 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
292 | |
293 | if (INTEL_INFO(dev)->gen >= 8) { | |
294 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
295 | ||
296 | if (page_offset == 0) { | |
297 | kunmap_atomic(vaddr); | |
033908ae | 298 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
3c94ceee BW |
299 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
300 | } | |
301 | ||
d9ceb957 | 302 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
303 | } |
304 | ||
5032d871 RB |
305 | kunmap_atomic(vaddr); |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | static int | |
311 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
312 | struct drm_i915_gem_relocation_entry *reloc, |
313 | uint64_t target_offset) | |
5032d871 RB |
314 | { |
315 | struct drm_device *dev = obj->base.dev; | |
316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
934acce3 | 317 | uint64_t delta = relocation_target(reloc, target_offset); |
906843c3 | 318 | uint64_t offset; |
5032d871 | 319 | void __iomem *reloc_page; |
8b78f0e5 | 320 | int ret; |
5032d871 RB |
321 | |
322 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
323 | if (ret) | |
324 | return ret; | |
325 | ||
326 | ret = i915_gem_object_put_fence(obj); | |
327 | if (ret) | |
328 | return ret; | |
329 | ||
330 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
331 | offset = i915_gem_obj_ggtt_offset(obj); |
332 | offset += reloc->offset; | |
62106b4f | 333 | reloc_page = io_mapping_map_atomic_wc(dev_priv->ggtt.mappable, |
906843c3 CW |
334 | offset & PAGE_MASK); |
335 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
336 | |
337 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 338 | offset += sizeof(uint32_t); |
3c94ceee | 339 | |
906843c3 | 340 | if (offset_in_page(offset) == 0) { |
3c94ceee | 341 | io_mapping_unmap_atomic(reloc_page); |
906843c3 | 342 | reloc_page = |
62106b4f | 343 | io_mapping_map_atomic_wc(dev_priv->ggtt.mappable, |
906843c3 | 344 | offset); |
3c94ceee BW |
345 | } |
346 | ||
906843c3 CW |
347 | iowrite32(upper_32_bits(delta), |
348 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
349 | } |
350 | ||
5032d871 RB |
351 | io_mapping_unmap_atomic(reloc_page); |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
edf4427b CW |
356 | static void |
357 | clflush_write32(void *addr, uint32_t value) | |
358 | { | |
359 | /* This is not a fast path, so KISS. */ | |
360 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
361 | *(uint32_t *)addr = value; | |
362 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
363 | } | |
364 | ||
365 | static int | |
366 | relocate_entry_clflush(struct drm_i915_gem_object *obj, | |
367 | struct drm_i915_gem_relocation_entry *reloc, | |
368 | uint64_t target_offset) | |
369 | { | |
370 | struct drm_device *dev = obj->base.dev; | |
371 | uint32_t page_offset = offset_in_page(reloc->offset); | |
934acce3 | 372 | uint64_t delta = relocation_target(reloc, target_offset); |
edf4427b CW |
373 | char *vaddr; |
374 | int ret; | |
375 | ||
376 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
377 | if (ret) | |
378 | return ret; | |
379 | ||
033908ae | 380 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
381 | reloc->offset >> PAGE_SHIFT)); |
382 | clflush_write32(vaddr + page_offset, lower_32_bits(delta)); | |
383 | ||
384 | if (INTEL_INFO(dev)->gen >= 8) { | |
385 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
386 | ||
387 | if (page_offset == 0) { | |
388 | kunmap_atomic(vaddr); | |
033908ae | 389 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, |
edf4427b CW |
390 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); |
391 | } | |
392 | ||
393 | clflush_write32(vaddr + page_offset, upper_32_bits(delta)); | |
394 | } | |
395 | ||
396 | kunmap_atomic(vaddr); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
54cf91dc CW |
401 | static int |
402 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 403 | struct eb_vmas *eb, |
3e7a0322 | 404 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
405 | { |
406 | struct drm_device *dev = obj->base.dev; | |
407 | struct drm_gem_object *target_obj; | |
149c8407 | 408 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 409 | struct i915_vma *target_vma; |
d9ceb957 | 410 | uint64_t target_offset; |
8b78f0e5 | 411 | int ret; |
54cf91dc | 412 | |
67731b87 | 413 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
414 | target_vma = eb_get_vma(eb, reloc->target_handle); |
415 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 416 | return -ENOENT; |
27173f1f BW |
417 | target_i915_obj = target_vma->obj; |
418 | target_obj = &target_vma->obj->base; | |
54cf91dc | 419 | |
934acce3 | 420 | target_offset = gen8_canonical_addr(target_vma->node.start); |
54cf91dc | 421 | |
e844b990 EA |
422 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
423 | * pipe_control writes because the gpu doesn't properly redirect them | |
424 | * through the ppgtt for non_secure batchbuffers. */ | |
425 | if (unlikely(IS_GEN6(dev) && | |
0875546c | 426 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { |
fe14d5f4 | 427 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, |
0875546c | 428 | PIN_GLOBAL); |
fe14d5f4 TU |
429 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) |
430 | return ret; | |
431 | } | |
e844b990 | 432 | |
54cf91dc | 433 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 434 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 435 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
436 | "obj %p target %d offset %d " |
437 | "read %08x write %08x", | |
438 | obj, reloc->target_handle, | |
439 | (int) reloc->offset, | |
440 | reloc->read_domains, | |
441 | reloc->write_domain); | |
8b78f0e5 | 442 | return -EINVAL; |
54cf91dc | 443 | } |
4ca4a250 DV |
444 | if (unlikely((reloc->write_domain | reloc->read_domains) |
445 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 446 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
447 | "obj %p target %d offset %d " |
448 | "read %08x write %08x", | |
449 | obj, reloc->target_handle, | |
450 | (int) reloc->offset, | |
451 | reloc->read_domains, | |
452 | reloc->write_domain); | |
8b78f0e5 | 453 | return -EINVAL; |
54cf91dc | 454 | } |
54cf91dc CW |
455 | |
456 | target_obj->pending_read_domains |= reloc->read_domains; | |
457 | target_obj->pending_write_domain |= reloc->write_domain; | |
458 | ||
459 | /* If the relocation already has the right value in it, no | |
460 | * more work needs to be done. | |
461 | */ | |
462 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 463 | return 0; |
54cf91dc CW |
464 | |
465 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
466 | if (unlikely(reloc->offset > |
467 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 468 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
469 | "obj %p target %d offset %d size %d.\n", |
470 | obj, reloc->target_handle, | |
471 | (int) reloc->offset, | |
472 | (int) obj->base.size); | |
8b78f0e5 | 473 | return -EINVAL; |
54cf91dc | 474 | } |
b8f7ab17 | 475 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 476 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
477 | "obj %p target %d offset %d.\n", |
478 | obj, reloc->target_handle, | |
479 | (int) reloc->offset); | |
8b78f0e5 | 480 | return -EINVAL; |
54cf91dc CW |
481 | } |
482 | ||
dabdfe02 | 483 | /* We can't wait for rendering with pagefaults disabled */ |
32d82067 | 484 | if (obj->active && pagefault_disabled()) |
dabdfe02 CW |
485 | return -EFAULT; |
486 | ||
5032d871 | 487 | if (use_cpu_reloc(obj)) |
d9ceb957 | 488 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
edf4427b | 489 | else if (obj->map_and_fenceable) |
d9ceb957 | 490 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
edf4427b CW |
491 | else if (cpu_has_clflush) |
492 | ret = relocate_entry_clflush(obj, reloc, target_offset); | |
493 | else { | |
494 | WARN_ONCE(1, "Impossible case in relocation handling\n"); | |
495 | ret = -ENODEV; | |
496 | } | |
54cf91dc | 497 | |
d4d36014 DV |
498 | if (ret) |
499 | return ret; | |
500 | ||
54cf91dc CW |
501 | /* and update the user's relocation entry */ |
502 | reloc->presumed_offset = target_offset; | |
503 | ||
67731b87 | 504 | return 0; |
54cf91dc CW |
505 | } |
506 | ||
507 | static int | |
27173f1f BW |
508 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
509 | struct eb_vmas *eb) | |
54cf91dc | 510 | { |
1d83f442 CW |
511 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
512 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 513 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 514 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 515 | int remain, ret; |
54cf91dc | 516 | |
2bb4629a | 517 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 518 | |
1d83f442 CW |
519 | remain = entry->relocation_count; |
520 | while (remain) { | |
521 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
522 | int count = remain; | |
523 | if (count > ARRAY_SIZE(stack_reloc)) | |
524 | count = ARRAY_SIZE(stack_reloc); | |
525 | remain -= count; | |
526 | ||
527 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
528 | return -EFAULT; |
529 | ||
1d83f442 CW |
530 | do { |
531 | u64 offset = r->presumed_offset; | |
54cf91dc | 532 | |
3e7a0322 | 533 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
534 | if (ret) |
535 | return ret; | |
536 | ||
537 | if (r->presumed_offset != offset && | |
538 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
539 | &r->presumed_offset, | |
540 | sizeof(r->presumed_offset))) { | |
541 | return -EFAULT; | |
542 | } | |
543 | ||
544 | user_relocs++; | |
545 | r++; | |
546 | } while (--count); | |
54cf91dc CW |
547 | } |
548 | ||
549 | return 0; | |
1d83f442 | 550 | #undef N_RELOC |
54cf91dc CW |
551 | } |
552 | ||
553 | static int | |
27173f1f BW |
554 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
555 | struct eb_vmas *eb, | |
556 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 557 | { |
27173f1f | 558 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
559 | int i, ret; |
560 | ||
561 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 562 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
563 | if (ret) |
564 | return ret; | |
565 | } | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | static int | |
17601cbc | 571 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 572 | { |
27173f1f | 573 | struct i915_vma *vma; |
d4aeee77 CW |
574 | int ret = 0; |
575 | ||
576 | /* This is the fast path and we cannot handle a pagefault whilst | |
577 | * holding the struct mutex lest the user pass in the relocations | |
578 | * contained within a mmaped bo. For in such a case we, the page | |
579 | * fault handler would call i915_gem_fault() and we would try to | |
580 | * acquire the struct mutex again. Obviously this is bad and so | |
581 | * lockdep complains vehemently. | |
582 | */ | |
583 | pagefault_disable(); | |
27173f1f BW |
584 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
585 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 586 | if (ret) |
d4aeee77 | 587 | break; |
54cf91dc | 588 | } |
d4aeee77 | 589 | pagefault_enable(); |
54cf91dc | 590 | |
d4aeee77 | 591 | return ret; |
54cf91dc CW |
592 | } |
593 | ||
edf4427b CW |
594 | static bool only_mappable_for_reloc(unsigned int flags) |
595 | { | |
596 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
597 | __EXEC_OBJECT_NEEDS_MAP; | |
598 | } | |
599 | ||
1690e1eb | 600 | static int |
27173f1f | 601 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
0bc40be8 | 602 | struct intel_engine_cs *engine, |
27173f1f | 603 | bool *need_reloc) |
1690e1eb | 604 | { |
6f65e29a | 605 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 606 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 607 | uint64_t flags; |
1690e1eb CW |
608 | int ret; |
609 | ||
0875546c | 610 | flags = PIN_USER; |
0229da32 DV |
611 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
612 | flags |= PIN_GLOBAL; | |
613 | ||
edf4427b | 614 | if (!drm_mm_node_allocated(&vma->node)) { |
101b506a MT |
615 | /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, |
616 | * limit address to the first 4GBs for unflagged objects. | |
617 | */ | |
618 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0) | |
619 | flags |= PIN_ZONE_4G; | |
edf4427b CW |
620 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
621 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
622 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
623 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
506a8e87 CW |
624 | if (entry->flags & EXEC_OBJECT_PINNED) |
625 | flags |= entry->offset | PIN_OFFSET_FIXED; | |
101b506a MT |
626 | if ((flags & PIN_MAPPABLE) == 0) |
627 | flags |= PIN_HIGH; | |
edf4427b | 628 | } |
1ec9e26d DV |
629 | |
630 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
edf4427b CW |
631 | if ((ret == -ENOSPC || ret == -E2BIG) && |
632 | only_mappable_for_reloc(entry->flags)) | |
633 | ret = i915_gem_object_pin(obj, vma->vm, | |
634 | entry->alignment, | |
0229da32 | 635 | flags & ~PIN_MAPPABLE); |
1690e1eb CW |
636 | if (ret) |
637 | return ret; | |
638 | ||
7788a765 CW |
639 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
640 | ||
82b6b6d7 CW |
641 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
642 | ret = i915_gem_object_get_fence(obj); | |
643 | if (ret) | |
644 | return ret; | |
9a5a53b3 | 645 | |
82b6b6d7 CW |
646 | if (i915_gem_object_pin_fence(obj)) |
647 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
648 | } |
649 | ||
27173f1f BW |
650 | if (entry->offset != vma->node.start) { |
651 | entry->offset = vma->node.start; | |
ed5982e6 DV |
652 | *need_reloc = true; |
653 | } | |
654 | ||
655 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
656 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
657 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
658 | } | |
659 | ||
1690e1eb | 660 | return 0; |
7788a765 | 661 | } |
1690e1eb | 662 | |
d23db88c | 663 | static bool |
e6a84468 | 664 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
665 | { |
666 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 667 | |
e6a84468 CW |
668 | if (entry->relocation_count == 0) |
669 | return false; | |
670 | ||
596c5923 | 671 | if (!vma->is_ggtt) |
e6a84468 CW |
672 | return false; |
673 | ||
674 | /* See also use_cpu_reloc() */ | |
675 | if (HAS_LLC(vma->obj->base.dev)) | |
676 | return false; | |
677 | ||
678 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
679 | return false; | |
680 | ||
681 | return true; | |
682 | } | |
683 | ||
684 | static bool | |
685 | eb_vma_misplaced(struct i915_vma *vma) | |
686 | { | |
687 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
688 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 689 | |
596c5923 | 690 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !vma->is_ggtt); |
d23db88c CW |
691 | |
692 | if (entry->alignment && | |
693 | vma->node.start & (entry->alignment - 1)) | |
694 | return true; | |
695 | ||
506a8e87 CW |
696 | if (entry->flags & EXEC_OBJECT_PINNED && |
697 | vma->node.start != entry->offset) | |
698 | return true; | |
699 | ||
d23db88c CW |
700 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
701 | vma->node.start < BATCH_OFFSET_BIAS) | |
702 | return true; | |
703 | ||
edf4427b CW |
704 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
705 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) | |
706 | return !only_mappable_for_reloc(entry->flags); | |
707 | ||
101b506a MT |
708 | if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 && |
709 | (vma->node.start + vma->node.size - 1) >> 32) | |
710 | return true; | |
711 | ||
d23db88c CW |
712 | return false; |
713 | } | |
714 | ||
54cf91dc | 715 | static int |
0bc40be8 | 716 | i915_gem_execbuffer_reserve(struct intel_engine_cs *engine, |
27173f1f | 717 | struct list_head *vmas, |
b1b38278 | 718 | struct intel_context *ctx, |
ed5982e6 | 719 | bool *need_relocs) |
54cf91dc | 720 | { |
432e58ed | 721 | struct drm_i915_gem_object *obj; |
27173f1f | 722 | struct i915_vma *vma; |
68c8c17f | 723 | struct i915_address_space *vm; |
27173f1f | 724 | struct list_head ordered_vmas; |
506a8e87 | 725 | struct list_head pinned_vmas; |
0bc40be8 | 726 | bool has_fenced_gpu_access = INTEL_INFO(engine->dev)->gen < 4; |
7788a765 | 727 | int retry; |
6fe4f140 | 728 | |
0bc40be8 | 729 | i915_gem_retire_requests_ring(engine); |
227f782e | 730 | |
68c8c17f BW |
731 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
732 | ||
27173f1f | 733 | INIT_LIST_HEAD(&ordered_vmas); |
506a8e87 | 734 | INIT_LIST_HEAD(&pinned_vmas); |
27173f1f | 735 | while (!list_empty(vmas)) { |
6fe4f140 CW |
736 | struct drm_i915_gem_exec_object2 *entry; |
737 | bool need_fence, need_mappable; | |
738 | ||
27173f1f BW |
739 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
740 | obj = vma->obj; | |
741 | entry = vma->exec_entry; | |
6fe4f140 | 742 | |
b1b38278 DW |
743 | if (ctx->flags & CONTEXT_NO_ZEROMAP) |
744 | entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
745 | ||
82b6b6d7 CW |
746 | if (!has_fenced_gpu_access) |
747 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 748 | need_fence = |
6fe4f140 CW |
749 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
750 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 751 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 752 | |
506a8e87 CW |
753 | if (entry->flags & EXEC_OBJECT_PINNED) |
754 | list_move_tail(&vma->exec_list, &pinned_vmas); | |
755 | else if (need_mappable) { | |
e6a84468 | 756 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; |
27173f1f | 757 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 758 | } else |
27173f1f | 759 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 760 | |
ed5982e6 | 761 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 762 | obj->base.pending_write_domain = 0; |
6fe4f140 | 763 | } |
27173f1f | 764 | list_splice(&ordered_vmas, vmas); |
506a8e87 | 765 | list_splice(&pinned_vmas, vmas); |
54cf91dc CW |
766 | |
767 | /* Attempt to pin all of the buffers into the GTT. | |
768 | * This is done in 3 phases: | |
769 | * | |
770 | * 1a. Unbind all objects that do not match the GTT constraints for | |
771 | * the execbuffer (fenceable, mappable, alignment etc). | |
772 | * 1b. Increment pin count for already bound objects. | |
773 | * 2. Bind new objects. | |
774 | * 3. Decrement pin count. | |
775 | * | |
7788a765 | 776 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
777 | * room for the earlier objects *unless* we need to defragment. |
778 | */ | |
779 | retry = 0; | |
780 | do { | |
7788a765 | 781 | int ret = 0; |
54cf91dc CW |
782 | |
783 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 784 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 785 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
786 | continue; |
787 | ||
e6a84468 | 788 | if (eb_vma_misplaced(vma)) |
27173f1f | 789 | ret = i915_vma_unbind(vma); |
54cf91dc | 790 | else |
0bc40be8 TU |
791 | ret = i915_gem_execbuffer_reserve_vma(vma, |
792 | engine, | |
793 | need_relocs); | |
432e58ed | 794 | if (ret) |
54cf91dc | 795 | goto err; |
54cf91dc CW |
796 | } |
797 | ||
798 | /* Bind fresh objects */ | |
27173f1f BW |
799 | list_for_each_entry(vma, vmas, exec_list) { |
800 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 801 | continue; |
54cf91dc | 802 | |
0bc40be8 TU |
803 | ret = i915_gem_execbuffer_reserve_vma(vma, engine, |
804 | need_relocs); | |
7788a765 CW |
805 | if (ret) |
806 | goto err; | |
54cf91dc CW |
807 | } |
808 | ||
a415d355 | 809 | err: |
6c085a72 | 810 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
811 | return ret; |
812 | ||
a415d355 CW |
813 | /* Decrement pin count for bound objects */ |
814 | list_for_each_entry(vma, vmas, exec_list) | |
815 | i915_gem_execbuffer_unreserve_vma(vma); | |
816 | ||
68c8c17f | 817 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
818 | if (ret) |
819 | return ret; | |
54cf91dc CW |
820 | } while (1); |
821 | } | |
822 | ||
823 | static int | |
824 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 825 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 826 | struct drm_file *file, |
0bc40be8 | 827 | struct intel_engine_cs *engine, |
27173f1f | 828 | struct eb_vmas *eb, |
b1b38278 DW |
829 | struct drm_i915_gem_exec_object2 *exec, |
830 | struct intel_context *ctx) | |
54cf91dc CW |
831 | { |
832 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
833 | struct i915_address_space *vm; |
834 | struct i915_vma *vma; | |
ed5982e6 | 835 | bool need_relocs; |
dd6864a4 | 836 | int *reloc_offset; |
54cf91dc | 837 | int i, total, ret; |
b205ca57 | 838 | unsigned count = args->buffer_count; |
54cf91dc | 839 | |
27173f1f BW |
840 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
841 | ||
67731b87 | 842 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
843 | while (!list_empty(&eb->vmas)) { |
844 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
845 | list_del_init(&vma->exec_list); | |
a415d355 | 846 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 847 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
848 | } |
849 | ||
54cf91dc CW |
850 | mutex_unlock(&dev->struct_mutex); |
851 | ||
852 | total = 0; | |
853 | for (i = 0; i < count; i++) | |
432e58ed | 854 | total += exec[i].relocation_count; |
54cf91dc | 855 | |
dd6864a4 | 856 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 857 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
858 | if (reloc == NULL || reloc_offset == NULL) { |
859 | drm_free_large(reloc); | |
860 | drm_free_large(reloc_offset); | |
54cf91dc CW |
861 | mutex_lock(&dev->struct_mutex); |
862 | return -ENOMEM; | |
863 | } | |
864 | ||
865 | total = 0; | |
866 | for (i = 0; i < count; i++) { | |
867 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
868 | u64 invalid_offset = (u64)-1; |
869 | int j; | |
54cf91dc | 870 | |
2bb4629a | 871 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
872 | |
873 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 874 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
875 | ret = -EFAULT; |
876 | mutex_lock(&dev->struct_mutex); | |
877 | goto err; | |
878 | } | |
879 | ||
262b6d36 CW |
880 | /* As we do not update the known relocation offsets after |
881 | * relocating (due to the complexities in lock handling), | |
882 | * we need to mark them as invalid now so that we force the | |
883 | * relocation processing next time. Just in case the target | |
884 | * object is evicted and then rebound into its old | |
885 | * presumed_offset before the next execbuffer - if that | |
886 | * happened we would make the mistake of assuming that the | |
887 | * relocations were valid. | |
888 | */ | |
889 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
890 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
891 | &invalid_offset, | |
892 | sizeof(invalid_offset))) { | |
262b6d36 CW |
893 | ret = -EFAULT; |
894 | mutex_lock(&dev->struct_mutex); | |
895 | goto err; | |
896 | } | |
897 | } | |
898 | ||
dd6864a4 | 899 | reloc_offset[i] = total; |
432e58ed | 900 | total += exec[i].relocation_count; |
54cf91dc CW |
901 | } |
902 | ||
903 | ret = i915_mutex_lock_interruptible(dev); | |
904 | if (ret) { | |
905 | mutex_lock(&dev->struct_mutex); | |
906 | goto err; | |
907 | } | |
908 | ||
67731b87 | 909 | /* reacquire the objects */ |
67731b87 | 910 | eb_reset(eb); |
27173f1f | 911 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
912 | if (ret) |
913 | goto err; | |
67731b87 | 914 | |
ed5982e6 | 915 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
0bc40be8 TU |
916 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
917 | &need_relocs); | |
54cf91dc CW |
918 | if (ret) |
919 | goto err; | |
920 | ||
27173f1f BW |
921 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
922 | int offset = vma->exec_entry - exec; | |
923 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
924 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
925 | if (ret) |
926 | goto err; | |
54cf91dc CW |
927 | } |
928 | ||
929 | /* Leave the user relocations as are, this is the painfully slow path, | |
930 | * and we want to avoid the complication of dropping the lock whilst | |
931 | * having buffers reserved in the aperture and so causing spurious | |
932 | * ENOSPC for random operations. | |
933 | */ | |
934 | ||
935 | err: | |
936 | drm_free_large(reloc); | |
dd6864a4 | 937 | drm_free_large(reloc_offset); |
54cf91dc CW |
938 | return ret; |
939 | } | |
940 | ||
54cf91dc | 941 | static int |
535fbe82 | 942 | i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, |
27173f1f | 943 | struct list_head *vmas) |
54cf91dc | 944 | { |
666796da | 945 | const unsigned other_rings = ~intel_engine_flag(req->engine); |
27173f1f | 946 | struct i915_vma *vma; |
6ac42f41 | 947 | uint32_t flush_domains = 0; |
000433b6 | 948 | bool flush_chipset = false; |
432e58ed | 949 | int ret; |
54cf91dc | 950 | |
27173f1f BW |
951 | list_for_each_entry(vma, vmas, exec_list) { |
952 | struct drm_i915_gem_object *obj = vma->obj; | |
03ade511 CW |
953 | |
954 | if (obj->active & other_rings) { | |
4a570db5 | 955 | ret = i915_gem_object_sync(obj, req->engine, &req); |
03ade511 CW |
956 | if (ret) |
957 | return ret; | |
958 | } | |
6ac42f41 DV |
959 | |
960 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 961 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 962 | |
6ac42f41 | 963 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
964 | } |
965 | ||
000433b6 | 966 | if (flush_chipset) |
4a570db5 | 967 | i915_gem_chipset_flush(req->engine->dev); |
6ac42f41 DV |
968 | |
969 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
970 | wmb(); | |
971 | ||
09cf7c9a CW |
972 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
973 | * any residual writes from the previous batch. | |
974 | */ | |
2f20055d | 975 | return intel_ring_invalidate_all_caches(req); |
54cf91dc CW |
976 | } |
977 | ||
432e58ed CW |
978 | static bool |
979 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 980 | { |
ed5982e6 DV |
981 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
982 | return false; | |
983 | ||
2f5945bc CW |
984 | /* Kernel clipping was a DRI1 misfeature */ |
985 | if (exec->num_cliprects || exec->cliprects_ptr) | |
986 | return false; | |
987 | ||
988 | if (exec->DR4 == 0xffffffff) { | |
989 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
990 | exec->DR4 = 0; | |
991 | } | |
992 | if (exec->DR1 || exec->DR4) | |
993 | return false; | |
994 | ||
995 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
996 | return false; | |
997 | ||
998 | return true; | |
54cf91dc CW |
999 | } |
1000 | ||
1001 | static int | |
ad19f10b CW |
1002 | validate_exec_list(struct drm_device *dev, |
1003 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
1004 | int count) |
1005 | { | |
b205ca57 DV |
1006 | unsigned relocs_total = 0; |
1007 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
1008 | unsigned invalid_flags; |
1009 | int i; | |
1010 | ||
1011 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; | |
1012 | if (USES_FULL_PPGTT(dev)) | |
1013 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
1014 | |
1015 | for (i = 0; i < count; i++) { | |
2bb4629a | 1016 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
1017 | int length; /* limited by fault_in_pages_readable() */ |
1018 | ||
ad19f10b | 1019 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
1020 | return -EINVAL; |
1021 | ||
934acce3 MW |
1022 | /* Offset can be used as input (EXEC_OBJECT_PINNED), reject |
1023 | * any non-page-aligned or non-canonical addresses. | |
1024 | */ | |
1025 | if (exec[i].flags & EXEC_OBJECT_PINNED) { | |
1026 | if (exec[i].offset != | |
1027 | gen8_canonical_addr(exec[i].offset & PAGE_MASK)) | |
1028 | return -EINVAL; | |
1029 | ||
1030 | /* From drm_mm perspective address space is continuous, | |
1031 | * so from this point we're always using non-canonical | |
1032 | * form internally. | |
1033 | */ | |
1034 | exec[i].offset = gen8_noncanonical_addr(exec[i].offset); | |
1035 | } | |
1036 | ||
55a9785d CW |
1037 | if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) |
1038 | return -EINVAL; | |
1039 | ||
3118a4f6 KC |
1040 | /* First check for malicious input causing overflow in |
1041 | * the worst case where we need to allocate the entire | |
1042 | * relocation tree as a single array. | |
1043 | */ | |
1044 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 1045 | return -EINVAL; |
3118a4f6 | 1046 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
1047 | |
1048 | length = exec[i].relocation_count * | |
1049 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
1050 | /* |
1051 | * We must check that the entire relocation array is safe | |
1052 | * to read, but since we may need to update the presumed | |
1053 | * offsets during execution, check for full write access. | |
1054 | */ | |
54cf91dc CW |
1055 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
1056 | return -EFAULT; | |
1057 | ||
d330a953 | 1058 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1059 | if (fault_in_multipages_readable(ptr, length)) |
1060 | return -EFAULT; | |
1061 | } | |
54cf91dc CW |
1062 | } |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | ||
273497e5 | 1067 | static struct intel_context * |
d299cce7 | 1068 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
0bc40be8 | 1069 | struct intel_engine_cs *engine, const u32 ctx_id) |
d299cce7 | 1070 | { |
273497e5 | 1071 | struct intel_context *ctx = NULL; |
d299cce7 MK |
1072 | struct i915_ctx_hang_stats *hs; |
1073 | ||
0bc40be8 | 1074 | if (engine->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
1075 | return ERR_PTR(-EINVAL); |
1076 | ||
41bde553 | 1077 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 1078 | if (IS_ERR(ctx)) |
41bde553 | 1079 | return ctx; |
d299cce7 | 1080 | |
41bde553 | 1081 | hs = &ctx->hang_stats; |
d299cce7 MK |
1082 | if (hs->banned) { |
1083 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 1084 | return ERR_PTR(-EIO); |
d299cce7 MK |
1085 | } |
1086 | ||
0bc40be8 TU |
1087 | if (i915.enable_execlists && !ctx->engine[engine->id].state) { |
1088 | int ret = intel_lr_context_deferred_alloc(ctx, engine); | |
ec3e9963 OM |
1089 | if (ret) { |
1090 | DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); | |
1091 | return ERR_PTR(ret); | |
1092 | } | |
1093 | } | |
1094 | ||
41bde553 | 1095 | return ctx; |
d299cce7 MK |
1096 | } |
1097 | ||
ba8b7ccb | 1098 | void |
27173f1f | 1099 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 1100 | struct drm_i915_gem_request *req) |
432e58ed | 1101 | { |
666796da | 1102 | struct intel_engine_cs *engine = i915_gem_request_get_engine(req); |
27173f1f | 1103 | struct i915_vma *vma; |
432e58ed | 1104 | |
27173f1f | 1105 | list_for_each_entry(vma, vmas, exec_list) { |
82b6b6d7 | 1106 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
27173f1f | 1107 | struct drm_i915_gem_object *obj = vma->obj; |
69c2fc89 CW |
1108 | u32 old_read = obj->base.read_domains; |
1109 | u32 old_write = obj->base.write_domain; | |
db53a302 | 1110 | |
51bc1404 | 1111 | obj->dirty = 1; /* be paranoid */ |
432e58ed | 1112 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
1113 | if (obj->base.write_domain == 0) |
1114 | obj->base.pending_read_domains |= obj->base.read_domains; | |
1115 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 1116 | |
b2af0376 | 1117 | i915_vma_move_to_active(vma, req); |
432e58ed | 1118 | if (obj->base.write_domain) { |
97b2a6a1 | 1119 | i915_gem_request_assign(&obj->last_write_req, req); |
f99d7069 | 1120 | |
77a0d1ca | 1121 | intel_fb_obj_invalidate(obj, ORIGIN_CS); |
c8725f3d CW |
1122 | |
1123 | /* update for the implicit flush after a batch */ | |
1124 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed | 1125 | } |
82b6b6d7 | 1126 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
97b2a6a1 | 1127 | i915_gem_request_assign(&obj->last_fenced_req, req); |
82b6b6d7 | 1128 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
e2f80391 | 1129 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
82b6b6d7 CW |
1130 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, |
1131 | &dev_priv->mm.fence_list); | |
1132 | } | |
1133 | } | |
432e58ed | 1134 | |
db53a302 | 1135 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
1136 | } |
1137 | } | |
1138 | ||
ba8b7ccb | 1139 | void |
adeca76d | 1140 | i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params) |
54cf91dc | 1141 | { |
cc889e0f | 1142 | /* Unconditionally force add_request to emit a full flush. */ |
4a570db5 | 1143 | params->engine->gpu_caches_dirty = true; |
54cf91dc | 1144 | |
432e58ed | 1145 | /* Add a breadcrumb for the completion of the batch buffer */ |
fcfa423c | 1146 | __i915_add_request(params->request, params->batch_obj, true); |
432e58ed | 1147 | } |
54cf91dc | 1148 | |
ae662d31 EA |
1149 | static int |
1150 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
2f20055d | 1151 | struct drm_i915_gem_request *req) |
ae662d31 | 1152 | { |
4a570db5 | 1153 | struct intel_engine_cs *engine = req->engine; |
50227e1c | 1154 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
1155 | int ret, i; |
1156 | ||
4a570db5 | 1157 | if (!IS_GEN7(dev) || engine != &dev_priv->engine[RCS]) { |
9d662da8 DV |
1158 | DRM_DEBUG("sol reset is gen7/rcs only\n"); |
1159 | return -EINVAL; | |
1160 | } | |
ae662d31 | 1161 | |
5fb9de1a | 1162 | ret = intel_ring_begin(req, 4 * 3); |
ae662d31 EA |
1163 | if (ret) |
1164 | return ret; | |
1165 | ||
1166 | for (i = 0; i < 4; i++) { | |
e2f80391 TU |
1167 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); |
1168 | intel_ring_emit_reg(engine, GEN7_SO_WRITE_OFFSET(i)); | |
1169 | intel_ring_emit(engine, 0); | |
ae662d31 EA |
1170 | } |
1171 | ||
e2f80391 | 1172 | intel_ring_advance(engine); |
ae662d31 EA |
1173 | |
1174 | return 0; | |
1175 | } | |
1176 | ||
71745376 | 1177 | static struct drm_i915_gem_object* |
0bc40be8 | 1178 | i915_gem_execbuffer_parse(struct intel_engine_cs *engine, |
71745376 BV |
1179 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, |
1180 | struct eb_vmas *eb, | |
1181 | struct drm_i915_gem_object *batch_obj, | |
1182 | u32 batch_start_offset, | |
1183 | u32 batch_len, | |
17cabf57 | 1184 | bool is_master) |
71745376 | 1185 | { |
71745376 | 1186 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1187 | struct i915_vma *vma; |
71745376 BV |
1188 | int ret; |
1189 | ||
0bc40be8 | 1190 | shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool, |
17cabf57 | 1191 | PAGE_ALIGN(batch_len)); |
71745376 BV |
1192 | if (IS_ERR(shadow_batch_obj)) |
1193 | return shadow_batch_obj; | |
1194 | ||
0bc40be8 | 1195 | ret = i915_parse_cmds(engine, |
71745376 BV |
1196 | batch_obj, |
1197 | shadow_batch_obj, | |
1198 | batch_start_offset, | |
1199 | batch_len, | |
1200 | is_master); | |
17cabf57 CW |
1201 | if (ret) |
1202 | goto err; | |
71745376 | 1203 | |
17cabf57 CW |
1204 | ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0); |
1205 | if (ret) | |
1206 | goto err; | |
71745376 | 1207 | |
de4e783a CW |
1208 | i915_gem_object_unpin_pages(shadow_batch_obj); |
1209 | ||
17cabf57 | 1210 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1211 | |
17cabf57 CW |
1212 | vma = i915_gem_obj_to_ggtt(shadow_batch_obj); |
1213 | vma->exec_entry = shadow_exec_entry; | |
de4e783a | 1214 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
17cabf57 CW |
1215 | drm_gem_object_reference(&shadow_batch_obj->base); |
1216 | list_add_tail(&vma->exec_list, &eb->vmas); | |
71745376 | 1217 | |
17cabf57 CW |
1218 | shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND; |
1219 | ||
1220 | return shadow_batch_obj; | |
71745376 | 1221 | |
17cabf57 | 1222 | err: |
de4e783a | 1223 | i915_gem_object_unpin_pages(shadow_batch_obj); |
17cabf57 CW |
1224 | if (ret == -EACCES) /* unhandled chained batch */ |
1225 | return batch_obj; | |
1226 | else | |
1227 | return ERR_PTR(ret); | |
71745376 | 1228 | } |
5c6c6003 | 1229 | |
a83014d3 | 1230 | int |
5f19e2bf | 1231 | i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 1232 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1233 | struct list_head *vmas) |
78382593 | 1234 | { |
5f19e2bf | 1235 | struct drm_device *dev = params->dev; |
4a570db5 | 1236 | struct intel_engine_cs *engine = params->engine; |
78382593 | 1237 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf | 1238 | u64 exec_start, exec_len; |
78382593 OM |
1239 | int instp_mode; |
1240 | u32 instp_mask; | |
2f5945bc | 1241 | int ret; |
78382593 | 1242 | |
535fbe82 | 1243 | ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); |
78382593 | 1244 | if (ret) |
2f5945bc | 1245 | return ret; |
78382593 | 1246 | |
ba01cc93 | 1247 | ret = i915_switch_context(params->request); |
78382593 | 1248 | if (ret) |
2f5945bc | 1249 | return ret; |
78382593 | 1250 | |
e2f80391 TU |
1251 | WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<engine->id), |
1252 | "%s didn't clear reload\n", engine->name); | |
563222a7 | 1253 | |
78382593 OM |
1254 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
1255 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1256 | switch (instp_mode) { | |
1257 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1258 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1259 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
4a570db5 | 1260 | if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) { |
78382593 | 1261 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
2f5945bc | 1262 | return -EINVAL; |
78382593 OM |
1263 | } |
1264 | ||
1265 | if (instp_mode != dev_priv->relative_constants_mode) { | |
1266 | if (INTEL_INFO(dev)->gen < 4) { | |
1267 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
2f5945bc | 1268 | return -EINVAL; |
78382593 OM |
1269 | } |
1270 | ||
1271 | if (INTEL_INFO(dev)->gen > 5 && | |
1272 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
1273 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
2f5945bc | 1274 | return -EINVAL; |
78382593 OM |
1275 | } |
1276 | ||
1277 | /* The HW changed the meaning on this bit on gen6 */ | |
1278 | if (INTEL_INFO(dev)->gen >= 6) | |
1279 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
1280 | } | |
1281 | break; | |
1282 | default: | |
1283 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
2f5945bc | 1284 | return -EINVAL; |
78382593 OM |
1285 | } |
1286 | ||
4a570db5 | 1287 | if (engine == &dev_priv->engine[RCS] && |
2f5945bc | 1288 | instp_mode != dev_priv->relative_constants_mode) { |
5fb9de1a | 1289 | ret = intel_ring_begin(params->request, 4); |
78382593 | 1290 | if (ret) |
2f5945bc | 1291 | return ret; |
78382593 | 1292 | |
e2f80391 TU |
1293 | intel_ring_emit(engine, MI_NOOP); |
1294 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
1295 | intel_ring_emit_reg(engine, INSTPM); | |
1296 | intel_ring_emit(engine, instp_mask << 16 | instp_mode); | |
1297 | intel_ring_advance(engine); | |
78382593 OM |
1298 | |
1299 | dev_priv->relative_constants_mode = instp_mode; | |
1300 | } | |
1301 | ||
1302 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
2f20055d | 1303 | ret = i915_reset_gen7_sol_offsets(dev, params->request); |
78382593 | 1304 | if (ret) |
2f5945bc | 1305 | return ret; |
78382593 OM |
1306 | } |
1307 | ||
5f19e2bf JH |
1308 | exec_len = args->batch_len; |
1309 | exec_start = params->batch_obj_vm_offset + | |
1310 | params->args_batch_start_offset; | |
1311 | ||
9d611c03 VS |
1312 | if (exec_len == 0) |
1313 | exec_len = params->batch_obj->base.size; | |
1314 | ||
e2f80391 | 1315 | ret = engine->dispatch_execbuffer(params->request, |
2f5945bc CW |
1316 | exec_start, exec_len, |
1317 | params->dispatch_flags); | |
1318 | if (ret) | |
1319 | return ret; | |
78382593 | 1320 | |
95c24161 | 1321 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
78382593 | 1322 | |
8a8edb59 | 1323 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 1324 | i915_gem_execbuffer_retire_commands(params); |
78382593 | 1325 | |
2f5945bc | 1326 | return 0; |
78382593 OM |
1327 | } |
1328 | ||
a8ebba75 ZY |
1329 | /** |
1330 | * Find one BSD ring to dispatch the corresponding BSD command. | |
de1add36 | 1331 | * The ring index is returned. |
a8ebba75 | 1332 | */ |
de1add36 TU |
1333 | static unsigned int |
1334 | gen8_dispatch_bsd_ring(struct drm_i915_private *dev_priv, struct drm_file *file) | |
a8ebba75 | 1335 | { |
a8ebba75 ZY |
1336 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1337 | ||
de1add36 TU |
1338 | /* Check whether the file_priv has already selected one ring. */ |
1339 | if ((int)file_priv->bsd_ring < 0) { | |
1340 | /* If not, use the ping-pong mechanism to select one. */ | |
1341 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1342 | file_priv->bsd_ring = dev_priv->mm.bsd_ring_dispatch_index; | |
1343 | dev_priv->mm.bsd_ring_dispatch_index ^= 1; | |
1344 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
a8ebba75 | 1345 | } |
de1add36 TU |
1346 | |
1347 | return file_priv->bsd_ring; | |
a8ebba75 ZY |
1348 | } |
1349 | ||
d23db88c CW |
1350 | static struct drm_i915_gem_object * |
1351 | eb_get_batch(struct eb_vmas *eb) | |
1352 | { | |
1353 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
1354 | ||
1355 | /* | |
1356 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
1357 | * to negative relocation deltas. Usually that works out ok since the | |
1358 | * relocate address is still positive, except when the batch is placed | |
1359 | * very low in the GTT. Ensure this doesn't happen. | |
1360 | * | |
1361 | * Note that actual hangs have only been observed on gen7, but for | |
1362 | * paranoia do it everywhere. | |
1363 | */ | |
506a8e87 CW |
1364 | if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0) |
1365 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
d23db88c CW |
1366 | |
1367 | return vma->obj; | |
1368 | } | |
1369 | ||
de1add36 TU |
1370 | #define I915_USER_RINGS (4) |
1371 | ||
117897f4 | 1372 | static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = { |
de1add36 TU |
1373 | [I915_EXEC_DEFAULT] = RCS, |
1374 | [I915_EXEC_RENDER] = RCS, | |
1375 | [I915_EXEC_BLT] = BCS, | |
1376 | [I915_EXEC_BSD] = VCS, | |
1377 | [I915_EXEC_VEBOX] = VECS | |
1378 | }; | |
1379 | ||
1380 | static int | |
1381 | eb_select_ring(struct drm_i915_private *dev_priv, | |
1382 | struct drm_file *file, | |
1383 | struct drm_i915_gem_execbuffer2 *args, | |
1384 | struct intel_engine_cs **ring) | |
1385 | { | |
1386 | unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; | |
1387 | ||
1388 | if (user_ring_id > I915_USER_RINGS) { | |
1389 | DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id); | |
1390 | return -EINVAL; | |
1391 | } | |
1392 | ||
1393 | if ((user_ring_id != I915_EXEC_BSD) && | |
1394 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1395 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1396 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
1397 | return -EINVAL; | |
1398 | } | |
1399 | ||
1400 | if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) { | |
1401 | unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; | |
1402 | ||
1403 | if (bsd_idx == I915_EXEC_BSD_DEFAULT) { | |
1404 | bsd_idx = gen8_dispatch_bsd_ring(dev_priv, file); | |
1405 | } else if (bsd_idx >= I915_EXEC_BSD_RING1 && | |
1406 | bsd_idx <= I915_EXEC_BSD_RING2) { | |
d9da6aa0 | 1407 | bsd_idx >>= I915_EXEC_BSD_SHIFT; |
de1add36 TU |
1408 | bsd_idx--; |
1409 | } else { | |
1410 | DRM_DEBUG("execbuf with unknown bsd ring: %u\n", | |
1411 | bsd_idx); | |
1412 | return -EINVAL; | |
1413 | } | |
1414 | ||
4a570db5 | 1415 | *ring = &dev_priv->engine[_VCS(bsd_idx)]; |
de1add36 | 1416 | } else { |
4a570db5 | 1417 | *ring = &dev_priv->engine[user_ring_map[user_ring_id]]; |
de1add36 TU |
1418 | } |
1419 | ||
117897f4 | 1420 | if (!intel_engine_initialized(*ring)) { |
de1add36 TU |
1421 | DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id); |
1422 | return -EINVAL; | |
1423 | } | |
1424 | ||
1425 | return 0; | |
1426 | } | |
1427 | ||
54cf91dc CW |
1428 | static int |
1429 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1430 | struct drm_file *file, | |
1431 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1432 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1433 | { |
50227e1c | 1434 | struct drm_i915_private *dev_priv = dev->dev_private; |
26827088 | 1435 | struct drm_i915_gem_request *req = NULL; |
27173f1f | 1436 | struct eb_vmas *eb; |
54cf91dc | 1437 | struct drm_i915_gem_object *batch_obj; |
78a42377 | 1438 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
e2f80391 | 1439 | struct intel_engine_cs *engine; |
273497e5 | 1440 | struct intel_context *ctx; |
41bde553 | 1441 | struct i915_address_space *vm; |
5f19e2bf JH |
1442 | struct i915_execbuffer_params params_master; /* XXX: will be removed later */ |
1443 | struct i915_execbuffer_params *params = ¶ms_master; | |
d299cce7 | 1444 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
8e004efc | 1445 | u32 dispatch_flags; |
78382593 | 1446 | int ret; |
ed5982e6 | 1447 | bool need_relocs; |
54cf91dc | 1448 | |
ed5982e6 | 1449 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1450 | return -EINVAL; |
432e58ed | 1451 | |
ad19f10b | 1452 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1453 | if (ret) |
1454 | return ret; | |
1455 | ||
8e004efc | 1456 | dispatch_flags = 0; |
d7d4eedd CW |
1457 | if (args->flags & I915_EXEC_SECURE) { |
1458 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1459 | return -EPERM; | |
1460 | ||
8e004efc | 1461 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1462 | } |
b45305fc | 1463 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1464 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1465 | |
e2f80391 | 1466 | ret = eb_select_ring(dev_priv, file, args, &engine); |
de1add36 TU |
1467 | if (ret) |
1468 | return ret; | |
54cf91dc CW |
1469 | |
1470 | if (args->buffer_count < 1) { | |
ff240199 | 1471 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1472 | return -EINVAL; |
1473 | } | |
54cf91dc | 1474 | |
a9ed33ca AJ |
1475 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
1476 | if (!HAS_RESOURCE_STREAMER(dev)) { | |
1477 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); | |
1478 | return -EINVAL; | |
1479 | } | |
e2f80391 | 1480 | if (engine->id != RCS) { |
a9ed33ca | 1481 | DRM_DEBUG("RS is not available on %s\n", |
e2f80391 | 1482 | engine->name); |
a9ed33ca AJ |
1483 | return -EINVAL; |
1484 | } | |
1485 | ||
1486 | dispatch_flags |= I915_DISPATCH_RS; | |
1487 | } | |
1488 | ||
f65c9168 PZ |
1489 | intel_runtime_pm_get(dev_priv); |
1490 | ||
54cf91dc CW |
1491 | ret = i915_mutex_lock_interruptible(dev); |
1492 | if (ret) | |
1493 | goto pre_mutex_err; | |
1494 | ||
e2f80391 | 1495 | ctx = i915_gem_validate_context(dev, file, engine, ctx_id); |
72ad5c45 | 1496 | if (IS_ERR(ctx)) { |
d299cce7 | 1497 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1498 | ret = PTR_ERR(ctx); |
d299cce7 | 1499 | goto pre_mutex_err; |
935f38d6 | 1500 | } |
41bde553 BW |
1501 | |
1502 | i915_gem_context_reference(ctx); | |
1503 | ||
ae6c4806 DV |
1504 | if (ctx->ppgtt) |
1505 | vm = &ctx->ppgtt->base; | |
1506 | else | |
62106b4f | 1507 | vm = &dev_priv->ggtt.base; |
d299cce7 | 1508 | |
5f19e2bf JH |
1509 | memset(¶ms_master, 0x00, sizeof(params_master)); |
1510 | ||
17601cbc | 1511 | eb = eb_create(args); |
67731b87 | 1512 | if (eb == NULL) { |
935f38d6 | 1513 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1514 | mutex_unlock(&dev->struct_mutex); |
1515 | ret = -ENOMEM; | |
1516 | goto pre_mutex_err; | |
1517 | } | |
1518 | ||
54cf91dc | 1519 | /* Look up object handles */ |
27173f1f | 1520 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1521 | if (ret) |
1522 | goto err; | |
54cf91dc | 1523 | |
6fe4f140 | 1524 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1525 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1526 | |
54cf91dc | 1527 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1528 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
e2f80391 TU |
1529 | ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx, |
1530 | &need_relocs); | |
54cf91dc CW |
1531 | if (ret) |
1532 | goto err; | |
1533 | ||
1534 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1535 | if (need_relocs) |
17601cbc | 1536 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1537 | if (ret) { |
1538 | if (ret == -EFAULT) { | |
e2f80391 TU |
1539 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, |
1540 | engine, | |
b1b38278 | 1541 | eb, exec, ctx); |
54cf91dc CW |
1542 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1543 | } | |
1544 | if (ret) | |
1545 | goto err; | |
1546 | } | |
1547 | ||
1548 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1549 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1550 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1551 | ret = -EINVAL; |
1552 | goto err; | |
1553 | } | |
54cf91dc | 1554 | |
5f19e2bf | 1555 | params->args_batch_start_offset = args->batch_start_offset; |
e2f80391 | 1556 | if (i915_needs_cmd_parser(engine) && args->batch_len) { |
c7c7372e RP |
1557 | struct drm_i915_gem_object *parsed_batch_obj; |
1558 | ||
e2f80391 TU |
1559 | parsed_batch_obj = i915_gem_execbuffer_parse(engine, |
1560 | &shadow_exec_entry, | |
1561 | eb, | |
1562 | batch_obj, | |
1563 | args->batch_start_offset, | |
1564 | args->batch_len, | |
1565 | file->is_master); | |
c7c7372e RP |
1566 | if (IS_ERR(parsed_batch_obj)) { |
1567 | ret = PTR_ERR(parsed_batch_obj); | |
78a42377 BV |
1568 | goto err; |
1569 | } | |
17cabf57 CW |
1570 | |
1571 | /* | |
c7c7372e RP |
1572 | * parsed_batch_obj == batch_obj means batch not fully parsed: |
1573 | * Accept, but don't promote to secure. | |
17cabf57 | 1574 | */ |
17cabf57 | 1575 | |
c7c7372e RP |
1576 | if (parsed_batch_obj != batch_obj) { |
1577 | /* | |
1578 | * Batch parsed and accepted: | |
1579 | * | |
1580 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1581 | * bit from MI_BATCH_BUFFER_START commands issued in | |
1582 | * the dispatch_execbuffer implementations. We | |
1583 | * specifically don't want that set on batches the | |
1584 | * command parser has accepted. | |
1585 | */ | |
1586 | dispatch_flags |= I915_DISPATCH_SECURE; | |
5f19e2bf | 1587 | params->args_batch_start_offset = 0; |
c7c7372e RP |
1588 | batch_obj = parsed_batch_obj; |
1589 | } | |
351e3db2 BV |
1590 | } |
1591 | ||
78a42377 BV |
1592 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
1593 | ||
d7d4eedd CW |
1594 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1595 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1596 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1597 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
da51a1e7 DV |
1598 | /* |
1599 | * So on first glance it looks freaky that we pin the batch here | |
1600 | * outside of the reservation loop. But: | |
1601 | * - The batch is already pinned into the relevant ppgtt, so we | |
1602 | * already have the backing storage fully allocated. | |
1603 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1604 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1605 | * fitting due to fragmentation. |
1606 | * So this is actually safe. | |
1607 | */ | |
1608 | ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); | |
1609 | if (ret) | |
1610 | goto err; | |
d7d4eedd | 1611 | |
5f19e2bf | 1612 | params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj); |
da51a1e7 | 1613 | } else |
5f19e2bf | 1614 | params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm); |
d7d4eedd | 1615 | |
0c8dac88 | 1616 | /* Allocate a request for this batch buffer nice and early. */ |
e2f80391 | 1617 | req = i915_gem_request_alloc(engine, ctx); |
26827088 DG |
1618 | if (IS_ERR(req)) { |
1619 | ret = PTR_ERR(req); | |
0c8dac88 | 1620 | goto err_batch_unpin; |
26827088 | 1621 | } |
0c8dac88 | 1622 | |
26827088 | 1623 | ret = i915_gem_request_add_to_client(req, file); |
fcfa423c JH |
1624 | if (ret) |
1625 | goto err_batch_unpin; | |
1626 | ||
5f19e2bf JH |
1627 | /* |
1628 | * Save assorted stuff away to pass through to *_submission(). | |
1629 | * NB: This data should be 'persistent' and not local as it will | |
1630 | * kept around beyond the duration of the IOCTL once the GPU | |
1631 | * scheduler arrives. | |
1632 | */ | |
1633 | params->dev = dev; | |
1634 | params->file = file; | |
4a570db5 | 1635 | params->engine = engine; |
5f19e2bf JH |
1636 | params->dispatch_flags = dispatch_flags; |
1637 | params->batch_obj = batch_obj; | |
1638 | params->ctx = ctx; | |
26827088 | 1639 | params->request = req; |
5f19e2bf JH |
1640 | |
1641 | ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas); | |
54cf91dc | 1642 | |
0c8dac88 | 1643 | err_batch_unpin: |
da51a1e7 DV |
1644 | /* |
1645 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1646 | * batch vma for correctness. For less ugly and less fragility this | |
1647 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1648 | * active. | |
1649 | */ | |
8e004efc | 1650 | if (dispatch_flags & I915_DISPATCH_SECURE) |
da51a1e7 | 1651 | i915_gem_object_ggtt_unpin(batch_obj); |
0c8dac88 | 1652 | |
54cf91dc | 1653 | err: |
41bde553 BW |
1654 | /* the request owns the ref now */ |
1655 | i915_gem_context_unreference(ctx); | |
67731b87 | 1656 | eb_destroy(eb); |
54cf91dc | 1657 | |
6a6ae79a JH |
1658 | /* |
1659 | * If the request was created but not successfully submitted then it | |
1660 | * must be freed again. If it was submitted then it is being tracked | |
1661 | * on the active request list and no clean up is required here. | |
1662 | */ | |
0aa498d5 | 1663 | if (ret && !IS_ERR_OR_NULL(req)) |
26827088 | 1664 | i915_gem_request_cancel(req); |
6a6ae79a | 1665 | |
54cf91dc CW |
1666 | mutex_unlock(&dev->struct_mutex); |
1667 | ||
1668 | pre_mutex_err: | |
f65c9168 PZ |
1669 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1670 | * is really idle. */ | |
1671 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1672 | return ret; |
1673 | } | |
1674 | ||
1675 | /* | |
1676 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1677 | * list array and passes it to the real function. | |
1678 | */ | |
1679 | int | |
1680 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1681 | struct drm_file *file) | |
1682 | { | |
1683 | struct drm_i915_gem_execbuffer *args = data; | |
1684 | struct drm_i915_gem_execbuffer2 exec2; | |
1685 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1686 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1687 | int ret, i; | |
1688 | ||
54cf91dc | 1689 | if (args->buffer_count < 1) { |
ff240199 | 1690 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1691 | return -EINVAL; |
1692 | } | |
1693 | ||
1694 | /* Copy in the exec list from userland */ | |
1695 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1696 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1697 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1698 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1699 | args->buffer_count); |
1700 | drm_free_large(exec_list); | |
1701 | drm_free_large(exec2_list); | |
1702 | return -ENOMEM; | |
1703 | } | |
1704 | ret = copy_from_user(exec_list, | |
2bb4629a | 1705 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1706 | sizeof(*exec_list) * args->buffer_count); |
1707 | if (ret != 0) { | |
ff240199 | 1708 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1709 | args->buffer_count, ret); |
1710 | drm_free_large(exec_list); | |
1711 | drm_free_large(exec2_list); | |
1712 | return -EFAULT; | |
1713 | } | |
1714 | ||
1715 | for (i = 0; i < args->buffer_count; i++) { | |
1716 | exec2_list[i].handle = exec_list[i].handle; | |
1717 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1718 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1719 | exec2_list[i].alignment = exec_list[i].alignment; | |
1720 | exec2_list[i].offset = exec_list[i].offset; | |
1721 | if (INTEL_INFO(dev)->gen < 4) | |
1722 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1723 | else | |
1724 | exec2_list[i].flags = 0; | |
1725 | } | |
1726 | ||
1727 | exec2.buffers_ptr = args->buffers_ptr; | |
1728 | exec2.buffer_count = args->buffer_count; | |
1729 | exec2.batch_start_offset = args->batch_start_offset; | |
1730 | exec2.batch_len = args->batch_len; | |
1731 | exec2.DR1 = args->DR1; | |
1732 | exec2.DR4 = args->DR4; | |
1733 | exec2.num_cliprects = args->num_cliprects; | |
1734 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1735 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1736 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1737 | |
41bde553 | 1738 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1739 | if (!ret) { |
9aab8bff CW |
1740 | struct drm_i915_gem_exec_object __user *user_exec_list = |
1741 | to_user_ptr(args->buffers_ptr); | |
1742 | ||
54cf91dc | 1743 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff | 1744 | for (i = 0; i < args->buffer_count; i++) { |
934acce3 MW |
1745 | exec2_list[i].offset = |
1746 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1747 | ret = __copy_to_user(&user_exec_list[i].offset, |
1748 | &exec2_list[i].offset, | |
1749 | sizeof(user_exec_list[i].offset)); | |
1750 | if (ret) { | |
1751 | ret = -EFAULT; | |
1752 | DRM_DEBUG("failed to copy %d exec entries " | |
1753 | "back to user (%d)\n", | |
1754 | args->buffer_count, ret); | |
1755 | break; | |
1756 | } | |
54cf91dc CW |
1757 | } |
1758 | } | |
1759 | ||
1760 | drm_free_large(exec_list); | |
1761 | drm_free_large(exec2_list); | |
1762 | return ret; | |
1763 | } | |
1764 | ||
1765 | int | |
1766 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1767 | struct drm_file *file) | |
1768 | { | |
1769 | struct drm_i915_gem_execbuffer2 *args = data; | |
1770 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1771 | int ret; | |
1772 | ||
ed8cd3b2 XW |
1773 | if (args->buffer_count < 1 || |
1774 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1775 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1776 | return -EINVAL; |
1777 | } | |
1778 | ||
9cb34664 DV |
1779 | if (args->rsvd2 != 0) { |
1780 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1781 | return -EINVAL; | |
1782 | } | |
1783 | ||
8408c282 | 1784 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1785 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1786 | if (exec2_list == NULL) |
1787 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1788 | args->buffer_count); | |
54cf91dc | 1789 | if (exec2_list == NULL) { |
ff240199 | 1790 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1791 | args->buffer_count); |
1792 | return -ENOMEM; | |
1793 | } | |
1794 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1795 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1796 | sizeof(*exec2_list) * args->buffer_count); |
1797 | if (ret != 0) { | |
ff240199 | 1798 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1799 | args->buffer_count, ret); |
1800 | drm_free_large(exec2_list); | |
1801 | return -EFAULT; | |
1802 | } | |
1803 | ||
41bde553 | 1804 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1805 | if (!ret) { |
1806 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1807 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
9aab8bff CW |
1808 | to_user_ptr(args->buffers_ptr); |
1809 | int i; | |
1810 | ||
1811 | for (i = 0; i < args->buffer_count; i++) { | |
934acce3 MW |
1812 | exec2_list[i].offset = |
1813 | gen8_canonical_addr(exec2_list[i].offset); | |
9aab8bff CW |
1814 | ret = __copy_to_user(&user_exec_list[i].offset, |
1815 | &exec2_list[i].offset, | |
1816 | sizeof(user_exec_list[i].offset)); | |
1817 | if (ret) { | |
1818 | ret = -EFAULT; | |
1819 | DRM_DEBUG("failed to copy %d exec entries " | |
1820 | "back to user\n", | |
1821 | args->buffer_count); | |
1822 | break; | |
1823 | } | |
54cf91dc CW |
1824 | } |
1825 | } | |
1826 | ||
1827 | drm_free_large(exec2_list); | |
1828 | return ret; | |
1829 | } |