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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | #include "i915_trace.h" | |
34 | #include "intel_drv.h" | |
f45b5557 | 35 | #include <linux/dma_remapping.h> |
54cf91dc CW |
36 | |
37 | struct change_domains { | |
38 | uint32_t invalidate_domains; | |
39 | uint32_t flush_domains; | |
40 | uint32_t flush_rings; | |
c59a333f | 41 | uint32_t flips; |
54cf91dc CW |
42 | }; |
43 | ||
44 | /* | |
45 | * Set the next domain for the specified object. This | |
46 | * may not actually perform the necessary flushing/invaliding though, | |
47 | * as that may want to be batched with other set_domain operations | |
48 | * | |
49 | * This is (we hope) the only really tricky part of gem. The goal | |
50 | * is fairly simple -- track which caches hold bits of the object | |
51 | * and make sure they remain coherent. A few concrete examples may | |
52 | * help to explain how it works. For shorthand, we use the notation | |
53 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
54 | * a pair of read and write domain masks. | |
55 | * | |
56 | * Case 1: the batch buffer | |
57 | * | |
58 | * 1. Allocated | |
59 | * 2. Written by CPU | |
60 | * 3. Mapped to GTT | |
61 | * 4. Read by GPU | |
62 | * 5. Unmapped from GTT | |
63 | * 6. Freed | |
64 | * | |
65 | * Let's take these a step at a time | |
66 | * | |
67 | * 1. Allocated | |
68 | * Pages allocated from the kernel may still have | |
69 | * cache contents, so we set them to (CPU, CPU) always. | |
70 | * 2. Written by CPU (using pwrite) | |
71 | * The pwrite function calls set_domain (CPU, CPU) and | |
72 | * this function does nothing (as nothing changes) | |
73 | * 3. Mapped by GTT | |
74 | * This function asserts that the object is not | |
75 | * currently in any GPU-based read or write domains | |
76 | * 4. Read by GPU | |
77 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
78 | * As write_domain is zero, this function adds in the | |
79 | * current read domains (CPU+COMMAND, 0). | |
80 | * flush_domains is set to CPU. | |
81 | * invalidate_domains is set to COMMAND | |
82 | * clflush is run to get data out of the CPU caches | |
83 | * then i915_dev_set_domain calls i915_gem_flush to | |
84 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
85 | * 5. Unmapped from GTT | |
86 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
87 | * flush_domains and invalidate_domains end up both zero | |
88 | * so no flushing/invalidating happens | |
89 | * 6. Freed | |
90 | * yay, done | |
91 | * | |
92 | * Case 2: The shared render buffer | |
93 | * | |
94 | * 1. Allocated | |
95 | * 2. Mapped to GTT | |
96 | * 3. Read/written by GPU | |
97 | * 4. set_domain to (CPU,CPU) | |
98 | * 5. Read/written by CPU | |
99 | * 6. Read/written by GPU | |
100 | * | |
101 | * 1. Allocated | |
102 | * Same as last example, (CPU, CPU) | |
103 | * 2. Mapped to GTT | |
104 | * Nothing changes (assertions find that it is not in the GPU) | |
105 | * 3. Read/written by GPU | |
106 | * execbuffer calls set_domain (RENDER, RENDER) | |
107 | * flush_domains gets CPU | |
108 | * invalidate_domains gets GPU | |
109 | * clflush (obj) | |
110 | * MI_FLUSH and drm_agp_chipset_flush | |
111 | * 4. set_domain (CPU, CPU) | |
112 | * flush_domains gets GPU | |
113 | * invalidate_domains gets CPU | |
114 | * wait_rendering (obj) to make sure all drawing is complete. | |
115 | * This will include an MI_FLUSH to get the data from GPU | |
116 | * to memory | |
117 | * clflush (obj) to invalidate the CPU cache | |
118 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
119 | * 5. Read/written by CPU | |
120 | * cache lines are loaded and dirtied | |
121 | * 6. Read written by GPU | |
122 | * Same as last GPU access | |
123 | * | |
124 | * Case 3: The constant buffer | |
125 | * | |
126 | * 1. Allocated | |
127 | * 2. Written by CPU | |
128 | * 3. Read by GPU | |
129 | * 4. Updated (written) by CPU again | |
130 | * 5. Read by GPU | |
131 | * | |
132 | * 1. Allocated | |
133 | * (CPU, CPU) | |
134 | * 2. Written by CPU | |
135 | * (CPU, CPU) | |
136 | * 3. Read by GPU | |
137 | * (CPU+RENDER, 0) | |
138 | * flush_domains = CPU | |
139 | * invalidate_domains = RENDER | |
140 | * clflush (obj) | |
141 | * MI_FLUSH | |
142 | * drm_agp_chipset_flush | |
143 | * 4. Updated (written) by CPU again | |
144 | * (CPU, CPU) | |
145 | * flush_domains = 0 (no previous write domain) | |
146 | * invalidate_domains = 0 (no new read domains) | |
147 | * 5. Read by GPU | |
148 | * (CPU+RENDER, 0) | |
149 | * flush_domains = CPU | |
150 | * invalidate_domains = RENDER | |
151 | * clflush (obj) | |
152 | * MI_FLUSH | |
153 | * drm_agp_chipset_flush | |
154 | */ | |
155 | static void | |
156 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, | |
157 | struct intel_ring_buffer *ring, | |
158 | struct change_domains *cd) | |
159 | { | |
160 | uint32_t invalidate_domains = 0, flush_domains = 0; | |
161 | ||
162 | /* | |
163 | * If the object isn't moving to a new write domain, | |
164 | * let the object stay in multiple read domains | |
165 | */ | |
166 | if (obj->base.pending_write_domain == 0) | |
167 | obj->base.pending_read_domains |= obj->base.read_domains; | |
168 | ||
169 | /* | |
170 | * Flush the current write domain if | |
171 | * the new read domains don't match. Invalidate | |
172 | * any read domains which differ from the old | |
173 | * write domain | |
174 | */ | |
175 | if (obj->base.write_domain && | |
176 | (((obj->base.write_domain != obj->base.pending_read_domains || | |
177 | obj->ring != ring)) || | |
178 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { | |
179 | flush_domains |= obj->base.write_domain; | |
180 | invalidate_domains |= | |
181 | obj->base.pending_read_domains & ~obj->base.write_domain; | |
182 | } | |
183 | /* | |
184 | * Invalidate any read caches which may have | |
185 | * stale data. That is, any new read domains. | |
186 | */ | |
187 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; | |
188 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) | |
189 | i915_gem_clflush_object(obj); | |
190 | ||
c59a333f CW |
191 | if (obj->base.pending_write_domain) |
192 | cd->flips |= atomic_read(&obj->pending_flip); | |
193 | ||
54cf91dc CW |
194 | /* The actual obj->write_domain will be updated with |
195 | * pending_write_domain after we emit the accumulated flush for all | |
196 | * of our domain changes in execbuffers (which clears objects' | |
197 | * write_domains). So if we have a current write domain that we | |
198 | * aren't changing, set pending_write_domain to that. | |
199 | */ | |
200 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) | |
201 | obj->base.pending_write_domain = obj->base.write_domain; | |
202 | ||
203 | cd->invalidate_domains |= invalidate_domains; | |
204 | cd->flush_domains |= flush_domains; | |
205 | if (flush_domains & I915_GEM_GPU_DOMAINS) | |
96154f2f | 206 | cd->flush_rings |= intel_ring_flag(obj->ring); |
54cf91dc | 207 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
96154f2f | 208 | cd->flush_rings |= intel_ring_flag(ring); |
54cf91dc CW |
209 | } |
210 | ||
67731b87 CW |
211 | struct eb_objects { |
212 | int and; | |
213 | struct hlist_head buckets[0]; | |
214 | }; | |
215 | ||
216 | static struct eb_objects * | |
217 | eb_create(int size) | |
218 | { | |
219 | struct eb_objects *eb; | |
220 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
221 | while (count > size) | |
222 | count >>= 1; | |
223 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
224 | sizeof(struct eb_objects), | |
225 | GFP_KERNEL); | |
226 | if (eb == NULL) | |
227 | return eb; | |
228 | ||
229 | eb->and = count - 1; | |
230 | return eb; | |
231 | } | |
232 | ||
233 | static void | |
234 | eb_reset(struct eb_objects *eb) | |
235 | { | |
236 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
237 | } | |
238 | ||
239 | static void | |
240 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) | |
241 | { | |
242 | hlist_add_head(&obj->exec_node, | |
243 | &eb->buckets[obj->exec_handle & eb->and]); | |
244 | } | |
245 | ||
246 | static struct drm_i915_gem_object * | |
247 | eb_get_object(struct eb_objects *eb, unsigned long handle) | |
248 | { | |
249 | struct hlist_head *head; | |
250 | struct hlist_node *node; | |
251 | struct drm_i915_gem_object *obj; | |
252 | ||
253 | head = &eb->buckets[handle & eb->and]; | |
254 | hlist_for_each(node, head) { | |
255 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); | |
256 | if (obj->exec_handle == handle) | |
257 | return obj; | |
258 | } | |
259 | ||
260 | return NULL; | |
261 | } | |
262 | ||
263 | static void | |
264 | eb_destroy(struct eb_objects *eb) | |
265 | { | |
266 | kfree(eb); | |
267 | } | |
268 | ||
dabdfe02 CW |
269 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
270 | { | |
271 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
272 | obj->cache_level != I915_CACHE_NONE); | |
273 | } | |
274 | ||
54cf91dc CW |
275 | static int |
276 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
67731b87 | 277 | struct eb_objects *eb, |
54cf91dc CW |
278 | struct drm_i915_gem_relocation_entry *reloc) |
279 | { | |
280 | struct drm_device *dev = obj->base.dev; | |
281 | struct drm_gem_object *target_obj; | |
149c8407 | 282 | struct drm_i915_gem_object *target_i915_obj; |
54cf91dc CW |
283 | uint32_t target_offset; |
284 | int ret = -EINVAL; | |
285 | ||
67731b87 CW |
286 | /* we've already hold a reference to all valid objects */ |
287 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; | |
288 | if (unlikely(target_obj == NULL)) | |
54cf91dc CW |
289 | return -ENOENT; |
290 | ||
149c8407 DV |
291 | target_i915_obj = to_intel_bo(target_obj); |
292 | target_offset = target_i915_obj->gtt_offset; | |
54cf91dc | 293 | |
54cf91dc CW |
294 | /* The target buffer should have appeared before us in the |
295 | * exec_object list, so it should have a GTT space bound by now. | |
296 | */ | |
b8f7ab17 | 297 | if (unlikely(target_offset == 0)) { |
ff240199 | 298 | DRM_DEBUG("No GTT space found for object %d\n", |
54cf91dc | 299 | reloc->target_handle); |
67731b87 | 300 | return ret; |
54cf91dc CW |
301 | } |
302 | ||
303 | /* Validate that the target is in a valid r/w GPU domain */ | |
b8f7ab17 | 304 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 305 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
306 | "obj %p target %d offset %d " |
307 | "read %08x write %08x", | |
308 | obj, reloc->target_handle, | |
309 | (int) reloc->offset, | |
310 | reloc->read_domains, | |
311 | reloc->write_domain); | |
67731b87 | 312 | return ret; |
54cf91dc | 313 | } |
4ca4a250 DV |
314 | if (unlikely((reloc->write_domain | reloc->read_domains) |
315 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 316 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
317 | "obj %p target %d offset %d " |
318 | "read %08x write %08x", | |
319 | obj, reloc->target_handle, | |
320 | (int) reloc->offset, | |
321 | reloc->read_domains, | |
322 | reloc->write_domain); | |
67731b87 | 323 | return ret; |
54cf91dc | 324 | } |
b8f7ab17 CW |
325 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
326 | reloc->write_domain != target_obj->pending_write_domain)) { | |
ff240199 | 327 | DRM_DEBUG("Write domain conflict: " |
54cf91dc CW |
328 | "obj %p target %d offset %d " |
329 | "new %08x old %08x\n", | |
330 | obj, reloc->target_handle, | |
331 | (int) reloc->offset, | |
332 | reloc->write_domain, | |
333 | target_obj->pending_write_domain); | |
67731b87 | 334 | return ret; |
54cf91dc CW |
335 | } |
336 | ||
337 | target_obj->pending_read_domains |= reloc->read_domains; | |
338 | target_obj->pending_write_domain |= reloc->write_domain; | |
339 | ||
340 | /* If the relocation already has the right value in it, no | |
341 | * more work needs to be done. | |
342 | */ | |
343 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 344 | return 0; |
54cf91dc CW |
345 | |
346 | /* Check that the relocation address is valid... */ | |
b8f7ab17 | 347 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
ff240199 | 348 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
349 | "obj %p target %d offset %d size %d.\n", |
350 | obj, reloc->target_handle, | |
351 | (int) reloc->offset, | |
352 | (int) obj->base.size); | |
67731b87 | 353 | return ret; |
54cf91dc | 354 | } |
b8f7ab17 | 355 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 356 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
357 | "obj %p target %d offset %d.\n", |
358 | obj, reloc->target_handle, | |
359 | (int) reloc->offset); | |
67731b87 | 360 | return ret; |
54cf91dc CW |
361 | } |
362 | ||
dabdfe02 CW |
363 | /* We can't wait for rendering with pagefaults disabled */ |
364 | if (obj->active && in_atomic()) | |
365 | return -EFAULT; | |
366 | ||
54cf91dc | 367 | reloc->delta += target_offset; |
dabdfe02 | 368 | if (use_cpu_reloc(obj)) { |
54cf91dc CW |
369 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
370 | char *vaddr; | |
371 | ||
dabdfe02 CW |
372 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
373 | if (ret) | |
374 | return ret; | |
375 | ||
54cf91dc CW |
376 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
377 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
378 | kunmap_atomic(vaddr); | |
379 | } else { | |
380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
381 | uint32_t __iomem *reloc_entry; | |
382 | void __iomem *reloc_page; | |
383 | ||
384 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
385 | if (ret) | |
67731b87 | 386 | return ret; |
54cf91dc CW |
387 | |
388 | /* Map the page containing the relocation we're going to perform. */ | |
389 | reloc->offset += obj->gtt_offset; | |
390 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
391 | reloc->offset & PAGE_MASK); | |
392 | reloc_entry = (uint32_t __iomem *) | |
393 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
394 | iowrite32(reloc->delta, reloc_entry); | |
395 | io_mapping_unmap_atomic(reloc_page); | |
396 | } | |
397 | ||
149c8407 DV |
398 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
399 | * pipe_control writes because the gpu doesn't properly redirect them | |
400 | * through the ppgtt for non_secure batchbuffers. */ | |
401 | if (unlikely(IS_GEN6(dev) && | |
402 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
403 | !target_i915_obj->has_global_gtt_mapping)) { | |
404 | i915_gem_gtt_bind_object(target_i915_obj, | |
405 | target_i915_obj->cache_level); | |
406 | } | |
407 | ||
54cf91dc CW |
408 | /* and update the user's relocation entry */ |
409 | reloc->presumed_offset = target_offset; | |
410 | ||
67731b87 | 411 | return 0; |
54cf91dc CW |
412 | } |
413 | ||
414 | static int | |
415 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
6fe4f140 | 416 | struct eb_objects *eb) |
54cf91dc | 417 | { |
1d83f442 CW |
418 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
419 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 420 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
6fe4f140 | 421 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
1d83f442 | 422 | int remain, ret; |
54cf91dc CW |
423 | |
424 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
54cf91dc | 425 | |
1d83f442 CW |
426 | remain = entry->relocation_count; |
427 | while (remain) { | |
428 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
429 | int count = remain; | |
430 | if (count > ARRAY_SIZE(stack_reloc)) | |
431 | count = ARRAY_SIZE(stack_reloc); | |
432 | remain -= count; | |
433 | ||
434 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
435 | return -EFAULT; |
436 | ||
1d83f442 CW |
437 | do { |
438 | u64 offset = r->presumed_offset; | |
54cf91dc | 439 | |
1d83f442 CW |
440 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
441 | if (ret) | |
442 | return ret; | |
443 | ||
444 | if (r->presumed_offset != offset && | |
445 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
446 | &r->presumed_offset, | |
447 | sizeof(r->presumed_offset))) { | |
448 | return -EFAULT; | |
449 | } | |
450 | ||
451 | user_relocs++; | |
452 | r++; | |
453 | } while (--count); | |
54cf91dc CW |
454 | } |
455 | ||
456 | return 0; | |
1d83f442 | 457 | #undef N_RELOC |
54cf91dc CW |
458 | } |
459 | ||
460 | static int | |
461 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
67731b87 | 462 | struct eb_objects *eb, |
54cf91dc CW |
463 | struct drm_i915_gem_relocation_entry *relocs) |
464 | { | |
6fe4f140 | 465 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc CW |
466 | int i, ret; |
467 | ||
468 | for (i = 0; i < entry->relocation_count; i++) { | |
6fe4f140 | 469 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
54cf91dc CW |
470 | if (ret) |
471 | return ret; | |
472 | } | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | static int | |
478 | i915_gem_execbuffer_relocate(struct drm_device *dev, | |
67731b87 | 479 | struct eb_objects *eb, |
6fe4f140 | 480 | struct list_head *objects) |
54cf91dc | 481 | { |
432e58ed | 482 | struct drm_i915_gem_object *obj; |
d4aeee77 CW |
483 | int ret = 0; |
484 | ||
485 | /* This is the fast path and we cannot handle a pagefault whilst | |
486 | * holding the struct mutex lest the user pass in the relocations | |
487 | * contained within a mmaped bo. For in such a case we, the page | |
488 | * fault handler would call i915_gem_fault() and we would try to | |
489 | * acquire the struct mutex again. Obviously this is bad and so | |
490 | * lockdep complains vehemently. | |
491 | */ | |
492 | pagefault_disable(); | |
432e58ed | 493 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 494 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
54cf91dc | 495 | if (ret) |
d4aeee77 | 496 | break; |
54cf91dc | 497 | } |
d4aeee77 | 498 | pagefault_enable(); |
54cf91dc | 499 | |
d4aeee77 | 500 | return ret; |
54cf91dc CW |
501 | } |
502 | ||
1690e1eb CW |
503 | #define __EXEC_OBJECT_HAS_FENCE (1<<31) |
504 | ||
dabdfe02 CW |
505 | static int |
506 | need_reloc_mappable(struct drm_i915_gem_object *obj) | |
507 | { | |
508 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
509 | return entry->relocation_count && !use_cpu_reloc(obj); | |
510 | } | |
511 | ||
1690e1eb CW |
512 | static int |
513 | pin_and_fence_object(struct drm_i915_gem_object *obj, | |
514 | struct intel_ring_buffer *ring) | |
515 | { | |
516 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; | |
517 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; | |
518 | bool need_fence, need_mappable; | |
519 | int ret; | |
520 | ||
521 | need_fence = | |
522 | has_fenced_gpu_access && | |
523 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
524 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 525 | need_mappable = need_fence || need_reloc_mappable(obj); |
1690e1eb CW |
526 | |
527 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable); | |
528 | if (ret) | |
529 | return ret; | |
530 | ||
531 | if (has_fenced_gpu_access) { | |
532 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { | |
9a5a53b3 CW |
533 | ret = i915_gem_object_get_fence(obj, ring); |
534 | if (ret) | |
535 | goto err_unpin; | |
1690e1eb | 536 | |
9a5a53b3 | 537 | if (i915_gem_object_pin_fence(obj)) |
1690e1eb | 538 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
9a5a53b3 | 539 | |
7dd49065 | 540 | obj->pending_fenced_gpu_access = true; |
1690e1eb | 541 | } |
1690e1eb CW |
542 | } |
543 | ||
544 | entry->offset = obj->gtt_offset; | |
545 | return 0; | |
546 | ||
547 | err_unpin: | |
548 | i915_gem_object_unpin(obj); | |
549 | return ret; | |
550 | } | |
551 | ||
54cf91dc | 552 | static int |
d9e86c0e | 553 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
54cf91dc | 554 | struct drm_file *file, |
6fe4f140 | 555 | struct list_head *objects) |
54cf91dc | 556 | { |
7bddb01f | 557 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
432e58ed | 558 | struct drm_i915_gem_object *obj; |
432e58ed | 559 | int ret, retry; |
9b3826bf | 560 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
6fe4f140 CW |
561 | struct list_head ordered_objects; |
562 | ||
563 | INIT_LIST_HEAD(&ordered_objects); | |
564 | while (!list_empty(objects)) { | |
565 | struct drm_i915_gem_exec_object2 *entry; | |
566 | bool need_fence, need_mappable; | |
567 | ||
568 | obj = list_first_entry(objects, | |
569 | struct drm_i915_gem_object, | |
570 | exec_list); | |
571 | entry = obj->exec_entry; | |
572 | ||
573 | need_fence = | |
574 | has_fenced_gpu_access && | |
575 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
576 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 577 | need_mappable = need_fence || need_reloc_mappable(obj); |
6fe4f140 CW |
578 | |
579 | if (need_mappable) | |
580 | list_move(&obj->exec_list, &ordered_objects); | |
581 | else | |
582 | list_move_tail(&obj->exec_list, &ordered_objects); | |
595dad76 CW |
583 | |
584 | obj->base.pending_read_domains = 0; | |
585 | obj->base.pending_write_domain = 0; | |
6fe4f140 CW |
586 | } |
587 | list_splice(&ordered_objects, objects); | |
54cf91dc CW |
588 | |
589 | /* Attempt to pin all of the buffers into the GTT. | |
590 | * This is done in 3 phases: | |
591 | * | |
592 | * 1a. Unbind all objects that do not match the GTT constraints for | |
593 | * the execbuffer (fenceable, mappable, alignment etc). | |
594 | * 1b. Increment pin count for already bound objects. | |
595 | * 2. Bind new objects. | |
596 | * 3. Decrement pin count. | |
597 | * | |
598 | * This avoid unnecessary unbinding of later objects in order to makr | |
599 | * room for the earlier objects *unless* we need to defragment. | |
600 | */ | |
601 | retry = 0; | |
602 | do { | |
603 | ret = 0; | |
604 | ||
605 | /* Unbind any ill-fitting objects or pin. */ | |
432e58ed | 606 | list_for_each_entry(obj, objects, exec_list) { |
6fe4f140 | 607 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
54cf91dc | 608 | bool need_fence, need_mappable; |
1690e1eb | 609 | |
6fe4f140 | 610 | if (!obj->gtt_space) |
54cf91dc CW |
611 | continue; |
612 | ||
613 | need_fence = | |
9b3826bf | 614 | has_fenced_gpu_access && |
54cf91dc CW |
615 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
616 | obj->tiling_mode != I915_TILING_NONE; | |
dabdfe02 | 617 | need_mappable = need_fence || need_reloc_mappable(obj); |
54cf91dc CW |
618 | |
619 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || | |
620 | (need_mappable && !obj->map_and_fenceable)) | |
621 | ret = i915_gem_object_unbind(obj); | |
622 | else | |
1690e1eb | 623 | ret = pin_and_fence_object(obj, ring); |
432e58ed | 624 | if (ret) |
54cf91dc | 625 | goto err; |
54cf91dc CW |
626 | } |
627 | ||
628 | /* Bind fresh objects */ | |
432e58ed | 629 | list_for_each_entry(obj, objects, exec_list) { |
1690e1eb CW |
630 | if (obj->gtt_space) |
631 | continue; | |
54cf91dc | 632 | |
1690e1eb CW |
633 | ret = pin_and_fence_object(obj, ring); |
634 | if (ret) { | |
635 | int ret_ignore; | |
636 | ||
637 | /* This can potentially raise a harmless | |
638 | * -EINVAL if we failed to bind in the above | |
639 | * call. It cannot raise -EINTR since we know | |
640 | * that the bo is freshly bound and so will | |
641 | * not need to be flushed or waited upon. | |
642 | */ | |
643 | ret_ignore = i915_gem_object_unbind(obj); | |
644 | (void)ret_ignore; | |
645 | WARN_ON(obj->gtt_space); | |
646 | break; | |
54cf91dc | 647 | } |
54cf91dc CW |
648 | } |
649 | ||
432e58ed CW |
650 | /* Decrement pin count for bound objects */ |
651 | list_for_each_entry(obj, objects, exec_list) { | |
1690e1eb CW |
652 | struct drm_i915_gem_exec_object2 *entry; |
653 | ||
654 | if (!obj->gtt_space) | |
655 | continue; | |
656 | ||
657 | entry = obj->exec_entry; | |
658 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
659 | i915_gem_object_unpin_fence(obj); | |
660 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
661 | } | |
662 | ||
663 | i915_gem_object_unpin(obj); | |
7bddb01f DV |
664 | |
665 | /* ... and ensure ppgtt mapping exist if needed. */ | |
666 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { | |
667 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
668 | obj, obj->cache_level); | |
669 | ||
670 | obj->has_aliasing_ppgtt_mapping = 1; | |
671 | } | |
54cf91dc CW |
672 | } |
673 | ||
674 | if (ret != -ENOSPC || retry > 1) | |
675 | return ret; | |
676 | ||
677 | /* First attempt, just clear anything that is purgeable. | |
678 | * Second attempt, clear the entire GTT. | |
679 | */ | |
d9e86c0e | 680 | ret = i915_gem_evict_everything(ring->dev, retry == 0); |
54cf91dc CW |
681 | if (ret) |
682 | return ret; | |
683 | ||
684 | retry++; | |
685 | } while (1); | |
432e58ed CW |
686 | |
687 | err: | |
1690e1eb CW |
688 | list_for_each_entry_continue_reverse(obj, objects, exec_list) { |
689 | struct drm_i915_gem_exec_object2 *entry; | |
690 | ||
691 | if (!obj->gtt_space) | |
692 | continue; | |
693 | ||
694 | entry = obj->exec_entry; | |
695 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { | |
696 | i915_gem_object_unpin_fence(obj); | |
697 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; | |
698 | } | |
432e58ed | 699 | |
1690e1eb | 700 | i915_gem_object_unpin(obj); |
432e58ed CW |
701 | } |
702 | ||
703 | return ret; | |
54cf91dc CW |
704 | } |
705 | ||
706 | static int | |
707 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
708 | struct drm_file *file, | |
d9e86c0e | 709 | struct intel_ring_buffer *ring, |
432e58ed | 710 | struct list_head *objects, |
67731b87 | 711 | struct eb_objects *eb, |
432e58ed | 712 | struct drm_i915_gem_exec_object2 *exec, |
54cf91dc CW |
713 | int count) |
714 | { | |
715 | struct drm_i915_gem_relocation_entry *reloc; | |
432e58ed | 716 | struct drm_i915_gem_object *obj; |
dd6864a4 | 717 | int *reloc_offset; |
54cf91dc CW |
718 | int i, total, ret; |
719 | ||
67731b87 | 720 | /* We may process another execbuffer during the unlock... */ |
36cf1742 | 721 | while (!list_empty(objects)) { |
67731b87 CW |
722 | obj = list_first_entry(objects, |
723 | struct drm_i915_gem_object, | |
724 | exec_list); | |
725 | list_del_init(&obj->exec_list); | |
726 | drm_gem_object_unreference(&obj->base); | |
727 | } | |
728 | ||
54cf91dc CW |
729 | mutex_unlock(&dev->struct_mutex); |
730 | ||
731 | total = 0; | |
732 | for (i = 0; i < count; i++) | |
432e58ed | 733 | total += exec[i].relocation_count; |
54cf91dc | 734 | |
dd6864a4 | 735 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 736 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
737 | if (reloc == NULL || reloc_offset == NULL) { |
738 | drm_free_large(reloc); | |
739 | drm_free_large(reloc_offset); | |
54cf91dc CW |
740 | mutex_lock(&dev->struct_mutex); |
741 | return -ENOMEM; | |
742 | } | |
743 | ||
744 | total = 0; | |
745 | for (i = 0; i < count; i++) { | |
746 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
747 | ||
432e58ed | 748 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
54cf91dc CW |
749 | |
750 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 751 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
752 | ret = -EFAULT; |
753 | mutex_lock(&dev->struct_mutex); | |
754 | goto err; | |
755 | } | |
756 | ||
dd6864a4 | 757 | reloc_offset[i] = total; |
432e58ed | 758 | total += exec[i].relocation_count; |
54cf91dc CW |
759 | } |
760 | ||
761 | ret = i915_mutex_lock_interruptible(dev); | |
762 | if (ret) { | |
763 | mutex_lock(&dev->struct_mutex); | |
764 | goto err; | |
765 | } | |
766 | ||
67731b87 | 767 | /* reacquire the objects */ |
67731b87 CW |
768 | eb_reset(eb); |
769 | for (i = 0; i < count; i++) { | |
67731b87 CW |
770 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
771 | exec[i].handle)); | |
c8725226 | 772 | if (&obj->base == NULL) { |
ff240199 | 773 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
67731b87 CW |
774 | exec[i].handle, i); |
775 | ret = -ENOENT; | |
776 | goto err; | |
777 | } | |
778 | ||
779 | list_add_tail(&obj->exec_list, objects); | |
780 | obj->exec_handle = exec[i].handle; | |
6fe4f140 | 781 | obj->exec_entry = &exec[i]; |
67731b87 CW |
782 | eb_add_object(eb, obj); |
783 | } | |
784 | ||
6fe4f140 | 785 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
54cf91dc CW |
786 | if (ret) |
787 | goto err; | |
788 | ||
432e58ed | 789 | list_for_each_entry(obj, objects, exec_list) { |
dd6864a4 | 790 | int offset = obj->exec_entry - exec; |
67731b87 | 791 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
dd6864a4 | 792 | reloc + reloc_offset[offset]); |
54cf91dc CW |
793 | if (ret) |
794 | goto err; | |
54cf91dc CW |
795 | } |
796 | ||
797 | /* Leave the user relocations as are, this is the painfully slow path, | |
798 | * and we want to avoid the complication of dropping the lock whilst | |
799 | * having buffers reserved in the aperture and so causing spurious | |
800 | * ENOSPC for random operations. | |
801 | */ | |
802 | ||
803 | err: | |
804 | drm_free_large(reloc); | |
dd6864a4 | 805 | drm_free_large(reloc_offset); |
54cf91dc CW |
806 | return ret; |
807 | } | |
808 | ||
88241785 | 809 | static int |
54cf91dc CW |
810 | i915_gem_execbuffer_flush(struct drm_device *dev, |
811 | uint32_t invalidate_domains, | |
812 | uint32_t flush_domains, | |
813 | uint32_t flush_rings) | |
814 | { | |
815 | drm_i915_private_t *dev_priv = dev->dev_private; | |
88241785 | 816 | int i, ret; |
54cf91dc CW |
817 | |
818 | if (flush_domains & I915_GEM_DOMAIN_CPU) | |
819 | intel_gtt_chipset_flush(); | |
820 | ||
63256ec5 CW |
821 | if (flush_domains & I915_GEM_DOMAIN_GTT) |
822 | wmb(); | |
823 | ||
54cf91dc | 824 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
1ec14ad3 | 825 | for (i = 0; i < I915_NUM_RINGS; i++) |
88241785 | 826 | if (flush_rings & (1 << i)) { |
db53a302 | 827 | ret = i915_gem_flush_ring(&dev_priv->ring[i], |
88241785 CW |
828 | invalidate_domains, |
829 | flush_domains); | |
830 | if (ret) | |
831 | return ret; | |
832 | } | |
54cf91dc | 833 | } |
88241785 CW |
834 | |
835 | return 0; | |
54cf91dc CW |
836 | } |
837 | ||
c59a333f CW |
838 | static int |
839 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) | |
840 | { | |
841 | u32 plane, flip_mask; | |
842 | int ret; | |
843 | ||
844 | /* Check for any pending flips. As we only maintain a flip queue depth | |
845 | * of 1, we can simply insert a WAIT for the next display flip prior | |
846 | * to executing the batch and avoid stalling the CPU. | |
847 | */ | |
848 | ||
849 | for (plane = 0; flips >> plane; plane++) { | |
850 | if (((flips >> plane) & 1) == 0) | |
851 | continue; | |
852 | ||
853 | if (plane) | |
854 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
855 | else | |
856 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
857 | ||
858 | ret = intel_ring_begin(ring, 2); | |
859 | if (ret) | |
860 | return ret; | |
861 | ||
862 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); | |
863 | intel_ring_emit(ring, MI_NOOP); | |
864 | intel_ring_advance(ring); | |
865 | } | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
870 | ||
54cf91dc | 871 | static int |
432e58ed CW |
872 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
873 | struct list_head *objects) | |
54cf91dc | 874 | { |
432e58ed | 875 | struct drm_i915_gem_object *obj; |
54cf91dc | 876 | struct change_domains cd; |
432e58ed | 877 | int ret; |
54cf91dc | 878 | |
c59a333f | 879 | memset(&cd, 0, sizeof(cd)); |
432e58ed CW |
880 | list_for_each_entry(obj, objects, exec_list) |
881 | i915_gem_object_set_to_gpu_domain(obj, ring, &cd); | |
54cf91dc CW |
882 | |
883 | if (cd.invalidate_domains | cd.flush_domains) { | |
88241785 CW |
884 | ret = i915_gem_execbuffer_flush(ring->dev, |
885 | cd.invalidate_domains, | |
886 | cd.flush_domains, | |
887 | cd.flush_rings); | |
888 | if (ret) | |
889 | return ret; | |
54cf91dc CW |
890 | } |
891 | ||
c59a333f CW |
892 | if (cd.flips) { |
893 | ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips); | |
894 | if (ret) | |
895 | return ret; | |
896 | } | |
897 | ||
432e58ed | 898 | list_for_each_entry(obj, objects, exec_list) { |
2911a35b | 899 | ret = i915_gem_object_sync(obj, ring); |
1ec14ad3 CW |
900 | if (ret) |
901 | return ret; | |
54cf91dc CW |
902 | } |
903 | ||
904 | return 0; | |
905 | } | |
906 | ||
432e58ed CW |
907 | static bool |
908 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 909 | { |
432e58ed | 910 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
911 | } |
912 | ||
913 | static int | |
914 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, | |
915 | int count) | |
916 | { | |
917 | int i; | |
918 | ||
919 | for (i = 0; i < count; i++) { | |
920 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
921 | int length; /* limited by fault_in_pages_readable() */ | |
922 | ||
923 | /* First check for malicious input causing overflow */ | |
924 | if (exec[i].relocation_count > | |
925 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
926 | return -EINVAL; | |
927 | ||
928 | length = exec[i].relocation_count * | |
929 | sizeof(struct drm_i915_gem_relocation_entry); | |
930 | if (!access_ok(VERIFY_READ, ptr, length)) | |
931 | return -EFAULT; | |
932 | ||
933 | /* we may also need to update the presumed offsets */ | |
934 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
935 | return -EFAULT; | |
936 | ||
f56f821f | 937 | if (fault_in_multipages_readable(ptr, length)) |
54cf91dc CW |
938 | return -EFAULT; |
939 | } | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
432e58ed CW |
944 | static void |
945 | i915_gem_execbuffer_move_to_active(struct list_head *objects, | |
1ec14ad3 CW |
946 | struct intel_ring_buffer *ring, |
947 | u32 seqno) | |
432e58ed CW |
948 | { |
949 | struct drm_i915_gem_object *obj; | |
950 | ||
951 | list_for_each_entry(obj, objects, exec_list) { | |
db53a302 CW |
952 | u32 old_read = obj->base.read_domains; |
953 | u32 old_write = obj->base.write_domain; | |
954 | ||
955 | ||
432e58ed CW |
956 | obj->base.read_domains = obj->base.pending_read_domains; |
957 | obj->base.write_domain = obj->base.pending_write_domain; | |
958 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; | |
959 | ||
1ec14ad3 | 960 | i915_gem_object_move_to_active(obj, ring, seqno); |
432e58ed CW |
961 | if (obj->base.write_domain) { |
962 | obj->dirty = 1; | |
87ca9c8a | 963 | obj->pending_gpu_write = true; |
432e58ed CW |
964 | list_move_tail(&obj->gpu_write_list, |
965 | &ring->gpu_write_list); | |
966 | intel_mark_busy(ring->dev, obj); | |
967 | } | |
968 | ||
db53a302 | 969 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
970 | } |
971 | } | |
972 | ||
54cf91dc CW |
973 | static void |
974 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
432e58ed | 975 | struct drm_file *file, |
54cf91dc CW |
976 | struct intel_ring_buffer *ring) |
977 | { | |
432e58ed | 978 | struct drm_i915_gem_request *request; |
b72f3acb | 979 | u32 invalidate; |
54cf91dc | 980 | |
432e58ed CW |
981 | /* |
982 | * Ensure that the commands in the batch buffer are | |
983 | * finished before the interrupt fires. | |
984 | * | |
985 | * The sampler always gets flushed on i965 (sigh). | |
986 | */ | |
b72f3acb | 987 | invalidate = I915_GEM_DOMAIN_COMMAND; |
54cf91dc | 988 | if (INTEL_INFO(dev)->gen >= 4) |
b72f3acb CW |
989 | invalidate |= I915_GEM_DOMAIN_SAMPLER; |
990 | if (ring->flush(ring, invalidate, 0)) { | |
db53a302 | 991 | i915_gem_next_request_seqno(ring); |
b72f3acb CW |
992 | return; |
993 | } | |
54cf91dc | 994 | |
432e58ed CW |
995 | /* Add a breadcrumb for the completion of the batch buffer */ |
996 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
db53a302 CW |
997 | if (request == NULL || i915_add_request(ring, file, request)) { |
998 | i915_gem_next_request_seqno(ring); | |
432e58ed CW |
999 | kfree(request); |
1000 | } | |
1001 | } | |
54cf91dc | 1002 | |
ae662d31 EA |
1003 | static int |
1004 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
1005 | struct intel_ring_buffer *ring) | |
1006 | { | |
1007 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1008 | int ret, i; | |
1009 | ||
1010 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) | |
1011 | return 0; | |
1012 | ||
1013 | ret = intel_ring_begin(ring, 4 * 3); | |
1014 | if (ret) | |
1015 | return ret; | |
1016 | ||
1017 | for (i = 0; i < 4; i++) { | |
1018 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1019 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1020 | intel_ring_emit(ring, 0); | |
1021 | } | |
1022 | ||
1023 | intel_ring_advance(ring); | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
54cf91dc CW |
1028 | static int |
1029 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1030 | struct drm_file *file, | |
1031 | struct drm_i915_gem_execbuffer2 *args, | |
432e58ed | 1032 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc CW |
1033 | { |
1034 | drm_i915_private_t *dev_priv = dev->dev_private; | |
432e58ed | 1035 | struct list_head objects; |
67731b87 | 1036 | struct eb_objects *eb; |
54cf91dc CW |
1037 | struct drm_i915_gem_object *batch_obj; |
1038 | struct drm_clip_rect *cliprects = NULL; | |
54cf91dc | 1039 | struct intel_ring_buffer *ring; |
c4e7a414 | 1040 | u32 exec_start, exec_len; |
1ec14ad3 | 1041 | u32 seqno; |
84f9f938 | 1042 | u32 mask; |
72bfa19c | 1043 | int ret, mode, i; |
54cf91dc | 1044 | |
432e58ed | 1045 | if (!i915_gem_check_execbuffer(args)) { |
ff240199 | 1046 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
432e58ed CW |
1047 | return -EINVAL; |
1048 | } | |
1049 | ||
1050 | ret = validate_exec_list(exec, args->buffer_count); | |
54cf91dc CW |
1051 | if (ret) |
1052 | return ret; | |
1053 | ||
54cf91dc CW |
1054 | switch (args->flags & I915_EXEC_RING_MASK) { |
1055 | case I915_EXEC_DEFAULT: | |
1056 | case I915_EXEC_RENDER: | |
1ec14ad3 | 1057 | ring = &dev_priv->ring[RCS]; |
54cf91dc CW |
1058 | break; |
1059 | case I915_EXEC_BSD: | |
1060 | if (!HAS_BSD(dev)) { | |
ff240199 | 1061 | DRM_DEBUG("execbuf with invalid ring (BSD)\n"); |
54cf91dc CW |
1062 | return -EINVAL; |
1063 | } | |
1ec14ad3 | 1064 | ring = &dev_priv->ring[VCS]; |
54cf91dc CW |
1065 | break; |
1066 | case I915_EXEC_BLT: | |
1067 | if (!HAS_BLT(dev)) { | |
ff240199 | 1068 | DRM_DEBUG("execbuf with invalid ring (BLT)\n"); |
54cf91dc CW |
1069 | return -EINVAL; |
1070 | } | |
1ec14ad3 | 1071 | ring = &dev_priv->ring[BCS]; |
54cf91dc CW |
1072 | break; |
1073 | default: | |
ff240199 | 1074 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1075 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1076 | return -EINVAL; | |
1077 | } | |
1078 | ||
72bfa19c | 1079 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
84f9f938 | 1080 | mask = I915_EXEC_CONSTANTS_MASK; |
72bfa19c CW |
1081 | switch (mode) { |
1082 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1083 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1084 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1085 | if (ring == &dev_priv->ring[RCS] && | |
1086 | mode != dev_priv->relative_constants_mode) { | |
1087 | if (INTEL_INFO(dev)->gen < 4) | |
1088 | return -EINVAL; | |
1089 | ||
1090 | if (INTEL_INFO(dev)->gen > 5 && | |
1091 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) | |
1092 | return -EINVAL; | |
84f9f938 BW |
1093 | |
1094 | /* The HW changed the meaning on this bit on gen6 */ | |
1095 | if (INTEL_INFO(dev)->gen >= 6) | |
1096 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
72bfa19c CW |
1097 | } |
1098 | break; | |
1099 | default: | |
ff240199 | 1100 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
72bfa19c CW |
1101 | return -EINVAL; |
1102 | } | |
1103 | ||
54cf91dc | 1104 | if (args->buffer_count < 1) { |
ff240199 | 1105 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1106 | return -EINVAL; |
1107 | } | |
54cf91dc CW |
1108 | |
1109 | if (args->num_cliprects != 0) { | |
1ec14ad3 | 1110 | if (ring != &dev_priv->ring[RCS]) { |
ff240199 | 1111 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
c4e7a414 CW |
1112 | return -EINVAL; |
1113 | } | |
1114 | ||
432e58ed | 1115 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
54cf91dc CW |
1116 | GFP_KERNEL); |
1117 | if (cliprects == NULL) { | |
1118 | ret = -ENOMEM; | |
1119 | goto pre_mutex_err; | |
1120 | } | |
1121 | ||
432e58ed CW |
1122 | if (copy_from_user(cliprects, |
1123 | (struct drm_clip_rect __user *)(uintptr_t) | |
1124 | args->cliprects_ptr, | |
1125 | sizeof(*cliprects)*args->num_cliprects)) { | |
54cf91dc CW |
1126 | ret = -EFAULT; |
1127 | goto pre_mutex_err; | |
1128 | } | |
1129 | } | |
1130 | ||
54cf91dc CW |
1131 | ret = i915_mutex_lock_interruptible(dev); |
1132 | if (ret) | |
1133 | goto pre_mutex_err; | |
1134 | ||
1135 | if (dev_priv->mm.suspended) { | |
1136 | mutex_unlock(&dev->struct_mutex); | |
1137 | ret = -EBUSY; | |
1138 | goto pre_mutex_err; | |
1139 | } | |
1140 | ||
67731b87 CW |
1141 | eb = eb_create(args->buffer_count); |
1142 | if (eb == NULL) { | |
1143 | mutex_unlock(&dev->struct_mutex); | |
1144 | ret = -ENOMEM; | |
1145 | goto pre_mutex_err; | |
1146 | } | |
1147 | ||
54cf91dc | 1148 | /* Look up object handles */ |
432e58ed | 1149 | INIT_LIST_HEAD(&objects); |
54cf91dc CW |
1150 | for (i = 0; i < args->buffer_count; i++) { |
1151 | struct drm_i915_gem_object *obj; | |
1152 | ||
432e58ed CW |
1153 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
1154 | exec[i].handle)); | |
c8725226 | 1155 | if (&obj->base == NULL) { |
ff240199 | 1156 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
432e58ed | 1157 | exec[i].handle, i); |
54cf91dc | 1158 | /* prevent error path from reading uninitialized data */ |
54cf91dc CW |
1159 | ret = -ENOENT; |
1160 | goto err; | |
1161 | } | |
54cf91dc | 1162 | |
432e58ed | 1163 | if (!list_empty(&obj->exec_list)) { |
ff240199 | 1164 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
432e58ed | 1165 | obj, exec[i].handle, i); |
54cf91dc CW |
1166 | ret = -EINVAL; |
1167 | goto err; | |
1168 | } | |
432e58ed CW |
1169 | |
1170 | list_add_tail(&obj->exec_list, &objects); | |
67731b87 | 1171 | obj->exec_handle = exec[i].handle; |
6fe4f140 | 1172 | obj->exec_entry = &exec[i]; |
67731b87 | 1173 | eb_add_object(eb, obj); |
54cf91dc CW |
1174 | } |
1175 | ||
6fe4f140 CW |
1176 | /* take note of the batch buffer before we might reorder the lists */ |
1177 | batch_obj = list_entry(objects.prev, | |
1178 | struct drm_i915_gem_object, | |
1179 | exec_list); | |
1180 | ||
54cf91dc | 1181 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
6fe4f140 | 1182 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
54cf91dc CW |
1183 | if (ret) |
1184 | goto err; | |
1185 | ||
1186 | /* The objects are in their final locations, apply the relocations. */ | |
6fe4f140 | 1187 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
54cf91dc CW |
1188 | if (ret) { |
1189 | if (ret == -EFAULT) { | |
d9e86c0e | 1190 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
67731b87 CW |
1191 | &objects, eb, |
1192 | exec, | |
54cf91dc CW |
1193 | args->buffer_count); |
1194 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1195 | } | |
1196 | if (ret) | |
1197 | goto err; | |
1198 | } | |
1199 | ||
1200 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1201 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1202 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1203 | ret = -EINVAL; |
1204 | goto err; | |
1205 | } | |
1206 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1207 | ||
432e58ed CW |
1208 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
1209 | if (ret) | |
54cf91dc | 1210 | goto err; |
54cf91dc | 1211 | |
db53a302 | 1212 | seqno = i915_gem_next_request_seqno(ring); |
076e2c0e | 1213 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
1ec14ad3 CW |
1214 | if (seqno < ring->sync_seqno[i]) { |
1215 | /* The GPU can not handle its semaphore value wrapping, | |
1216 | * so every billion or so execbuffers, we need to stall | |
1217 | * the GPU in order to reset the counters. | |
1218 | */ | |
b93f9cf1 | 1219 | ret = i915_gpu_idle(dev, true); |
1ec14ad3 CW |
1220 | if (ret) |
1221 | goto err; | |
1222 | ||
1223 | BUG_ON(ring->sync_seqno[i]); | |
1224 | } | |
1225 | } | |
1226 | ||
e2971bda BW |
1227 | if (ring == &dev_priv->ring[RCS] && |
1228 | mode != dev_priv->relative_constants_mode) { | |
1229 | ret = intel_ring_begin(ring, 4); | |
1230 | if (ret) | |
1231 | goto err; | |
1232 | ||
1233 | intel_ring_emit(ring, MI_NOOP); | |
1234 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1235 | intel_ring_emit(ring, INSTPM); | |
84f9f938 | 1236 | intel_ring_emit(ring, mask << 16 | mode); |
e2971bda BW |
1237 | intel_ring_advance(ring); |
1238 | ||
1239 | dev_priv->relative_constants_mode = mode; | |
1240 | } | |
1241 | ||
ae662d31 EA |
1242 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
1243 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1244 | if (ret) | |
1245 | goto err; | |
1246 | } | |
1247 | ||
db53a302 CW |
1248 | trace_i915_gem_ring_dispatch(ring, seqno); |
1249 | ||
c4e7a414 CW |
1250 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
1251 | exec_len = args->batch_len; | |
1252 | if (cliprects) { | |
1253 | for (i = 0; i < args->num_cliprects; i++) { | |
1254 | ret = i915_emit_box(dev, &cliprects[i], | |
1255 | args->DR1, args->DR4); | |
1256 | if (ret) | |
1257 | goto err; | |
1258 | ||
1259 | ret = ring->dispatch_execbuffer(ring, | |
1260 | exec_start, exec_len); | |
1261 | if (ret) | |
1262 | goto err; | |
1263 | } | |
1264 | } else { | |
1265 | ret = ring->dispatch_execbuffer(ring, exec_start, exec_len); | |
1266 | if (ret) | |
1267 | goto err; | |
1268 | } | |
54cf91dc | 1269 | |
1ec14ad3 | 1270 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
432e58ed | 1271 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
54cf91dc CW |
1272 | |
1273 | err: | |
67731b87 | 1274 | eb_destroy(eb); |
432e58ed CW |
1275 | while (!list_empty(&objects)) { |
1276 | struct drm_i915_gem_object *obj; | |
1277 | ||
1278 | obj = list_first_entry(&objects, | |
1279 | struct drm_i915_gem_object, | |
1280 | exec_list); | |
1281 | list_del_init(&obj->exec_list); | |
1282 | drm_gem_object_unreference(&obj->base); | |
54cf91dc CW |
1283 | } |
1284 | ||
1285 | mutex_unlock(&dev->struct_mutex); | |
1286 | ||
1287 | pre_mutex_err: | |
54cf91dc | 1288 | kfree(cliprects); |
54cf91dc CW |
1289 | return ret; |
1290 | } | |
1291 | ||
1292 | /* | |
1293 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1294 | * list array and passes it to the real function. | |
1295 | */ | |
1296 | int | |
1297 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1298 | struct drm_file *file) | |
1299 | { | |
1300 | struct drm_i915_gem_execbuffer *args = data; | |
1301 | struct drm_i915_gem_execbuffer2 exec2; | |
1302 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1303 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1304 | int ret, i; | |
1305 | ||
54cf91dc | 1306 | if (args->buffer_count < 1) { |
ff240199 | 1307 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1308 | return -EINVAL; |
1309 | } | |
1310 | ||
1311 | /* Copy in the exec list from userland */ | |
1312 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1313 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1314 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1315 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1316 | args->buffer_count); |
1317 | drm_free_large(exec_list); | |
1318 | drm_free_large(exec2_list); | |
1319 | return -ENOMEM; | |
1320 | } | |
1321 | ret = copy_from_user(exec_list, | |
1322 | (struct drm_i915_relocation_entry __user *) | |
1323 | (uintptr_t) args->buffers_ptr, | |
1324 | sizeof(*exec_list) * args->buffer_count); | |
1325 | if (ret != 0) { | |
ff240199 | 1326 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1327 | args->buffer_count, ret); |
1328 | drm_free_large(exec_list); | |
1329 | drm_free_large(exec2_list); | |
1330 | return -EFAULT; | |
1331 | } | |
1332 | ||
1333 | for (i = 0; i < args->buffer_count; i++) { | |
1334 | exec2_list[i].handle = exec_list[i].handle; | |
1335 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1336 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1337 | exec2_list[i].alignment = exec_list[i].alignment; | |
1338 | exec2_list[i].offset = exec_list[i].offset; | |
1339 | if (INTEL_INFO(dev)->gen < 4) | |
1340 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1341 | else | |
1342 | exec2_list[i].flags = 0; | |
1343 | } | |
1344 | ||
1345 | exec2.buffers_ptr = args->buffers_ptr; | |
1346 | exec2.buffer_count = args->buffer_count; | |
1347 | exec2.batch_start_offset = args->batch_start_offset; | |
1348 | exec2.batch_len = args->batch_len; | |
1349 | exec2.DR1 = args->DR1; | |
1350 | exec2.DR4 = args->DR4; | |
1351 | exec2.num_cliprects = args->num_cliprects; | |
1352 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1353 | exec2.flags = I915_EXEC_RENDER; | |
1354 | ||
1355 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); | |
1356 | if (!ret) { | |
1357 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1358 | for (i = 0; i < args->buffer_count; i++) | |
1359 | exec_list[i].offset = exec2_list[i].offset; | |
1360 | /* ... and back out to userspace */ | |
1361 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1362 | (uintptr_t) args->buffers_ptr, | |
1363 | exec_list, | |
1364 | sizeof(*exec_list) * args->buffer_count); | |
1365 | if (ret) { | |
1366 | ret = -EFAULT; | |
ff240199 | 1367 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1368 | "back to user (%d)\n", |
1369 | args->buffer_count, ret); | |
1370 | } | |
1371 | } | |
1372 | ||
1373 | drm_free_large(exec_list); | |
1374 | drm_free_large(exec2_list); | |
1375 | return ret; | |
1376 | } | |
1377 | ||
1378 | int | |
1379 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1380 | struct drm_file *file) | |
1381 | { | |
1382 | struct drm_i915_gem_execbuffer2 *args = data; | |
1383 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1384 | int ret; | |
1385 | ||
54cf91dc | 1386 | if (args->buffer_count < 1) { |
ff240199 | 1387 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1388 | return -EINVAL; |
1389 | } | |
1390 | ||
8408c282 CW |
1391 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
1392 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); | |
1393 | if (exec2_list == NULL) | |
1394 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1395 | args->buffer_count); | |
54cf91dc | 1396 | if (exec2_list == NULL) { |
ff240199 | 1397 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1398 | args->buffer_count); |
1399 | return -ENOMEM; | |
1400 | } | |
1401 | ret = copy_from_user(exec2_list, | |
1402 | (struct drm_i915_relocation_entry __user *) | |
1403 | (uintptr_t) args->buffers_ptr, | |
1404 | sizeof(*exec2_list) * args->buffer_count); | |
1405 | if (ret != 0) { | |
ff240199 | 1406 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1407 | args->buffer_count, ret); |
1408 | drm_free_large(exec2_list); | |
1409 | return -EFAULT; | |
1410 | } | |
1411 | ||
1412 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); | |
1413 | if (!ret) { | |
1414 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1415 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1416 | (uintptr_t) args->buffers_ptr, | |
1417 | exec2_list, | |
1418 | sizeof(*exec2_list) * args->buffer_count); | |
1419 | if (ret) { | |
1420 | ret = -EFAULT; | |
ff240199 | 1421 | DRM_DEBUG("failed to copy %d exec entries " |
54cf91dc CW |
1422 | "back to user (%d)\n", |
1423 | args->buffer_count, ret); | |
1424 | } | |
1425 | } | |
1426 | ||
1427 | drm_free_large(exec2_list); | |
1428 | return ret; | |
1429 | } |